2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 bool nmi_known_unmasked
;
203 struct list_head loaded_vmcss_on_cpu_link
;
206 struct shared_msr_entry
{
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width
;
226 struct __packed vmcs12
{
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding
[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr
;
240 u64 vm_exit_msr_load_addr
;
241 u64 vm_entry_msr_load_addr
;
243 u64 virtual_apic_page_addr
;
244 u64 apic_access_addr
;
245 u64 posted_intr_desc_addr
;
246 u64 vm_function_control
;
248 u64 eoi_exit_bitmap0
;
249 u64 eoi_exit_bitmap1
;
250 u64 eoi_exit_bitmap2
;
251 u64 eoi_exit_bitmap3
;
252 u64 eptp_list_address
;
254 u64 guest_physical_address
;
255 u64 vmcs_link_pointer
;
257 u64 guest_ia32_debugctl
;
260 u64 guest_ia32_perf_global_ctrl
;
268 u64 host_ia32_perf_global_ctrl
;
269 u64 padding64
[8]; /* room for future expansion */
271 * To allow migration of L1 (complete with its L2 guests) between
272 * machines of different natural widths (32 or 64 bit), we cannot have
273 * unsigned long fields with no explict size. We use u64 (aliased
274 * natural_width) instead. Luckily, x86 is little-endian.
276 natural_width cr0_guest_host_mask
;
277 natural_width cr4_guest_host_mask
;
278 natural_width cr0_read_shadow
;
279 natural_width cr4_read_shadow
;
280 natural_width cr3_target_value0
;
281 natural_width cr3_target_value1
;
282 natural_width cr3_target_value2
;
283 natural_width cr3_target_value3
;
284 natural_width exit_qualification
;
285 natural_width guest_linear_address
;
286 natural_width guest_cr0
;
287 natural_width guest_cr3
;
288 natural_width guest_cr4
;
289 natural_width guest_es_base
;
290 natural_width guest_cs_base
;
291 natural_width guest_ss_base
;
292 natural_width guest_ds_base
;
293 natural_width guest_fs_base
;
294 natural_width guest_gs_base
;
295 natural_width guest_ldtr_base
;
296 natural_width guest_tr_base
;
297 natural_width guest_gdtr_base
;
298 natural_width guest_idtr_base
;
299 natural_width guest_dr7
;
300 natural_width guest_rsp
;
301 natural_width guest_rip
;
302 natural_width guest_rflags
;
303 natural_width guest_pending_dbg_exceptions
;
304 natural_width guest_sysenter_esp
;
305 natural_width guest_sysenter_eip
;
306 natural_width host_cr0
;
307 natural_width host_cr3
;
308 natural_width host_cr4
;
309 natural_width host_fs_base
;
310 natural_width host_gs_base
;
311 natural_width host_tr_base
;
312 natural_width host_gdtr_base
;
313 natural_width host_idtr_base
;
314 natural_width host_ia32_sysenter_esp
;
315 natural_width host_ia32_sysenter_eip
;
316 natural_width host_rsp
;
317 natural_width host_rip
;
318 natural_width paddingl
[8]; /* room for future expansion */
319 u32 pin_based_vm_exec_control
;
320 u32 cpu_based_vm_exec_control
;
321 u32 exception_bitmap
;
322 u32 page_fault_error_code_mask
;
323 u32 page_fault_error_code_match
;
324 u32 cr3_target_count
;
325 u32 vm_exit_controls
;
326 u32 vm_exit_msr_store_count
;
327 u32 vm_exit_msr_load_count
;
328 u32 vm_entry_controls
;
329 u32 vm_entry_msr_load_count
;
330 u32 vm_entry_intr_info_field
;
331 u32 vm_entry_exception_error_code
;
332 u32 vm_entry_instruction_len
;
334 u32 secondary_vm_exec_control
;
335 u32 vm_instruction_error
;
337 u32 vm_exit_intr_info
;
338 u32 vm_exit_intr_error_code
;
339 u32 idt_vectoring_info_field
;
340 u32 idt_vectoring_error_code
;
341 u32 vm_exit_instruction_len
;
342 u32 vmx_instruction_info
;
349 u32 guest_ldtr_limit
;
351 u32 guest_gdtr_limit
;
352 u32 guest_idtr_limit
;
353 u32 guest_es_ar_bytes
;
354 u32 guest_cs_ar_bytes
;
355 u32 guest_ss_ar_bytes
;
356 u32 guest_ds_ar_bytes
;
357 u32 guest_fs_ar_bytes
;
358 u32 guest_gs_ar_bytes
;
359 u32 guest_ldtr_ar_bytes
;
360 u32 guest_tr_ar_bytes
;
361 u32 guest_interruptibility_info
;
362 u32 guest_activity_state
;
363 u32 guest_sysenter_cs
;
364 u32 host_ia32_sysenter_cs
;
365 u32 vmx_preemption_timer_value
;
366 u32 padding32
[7]; /* room for future expansion */
367 u16 virtual_processor_id
;
369 u16 guest_es_selector
;
370 u16 guest_cs_selector
;
371 u16 guest_ss_selector
;
372 u16 guest_ds_selector
;
373 u16 guest_fs_selector
;
374 u16 guest_gs_selector
;
375 u16 guest_ldtr_selector
;
376 u16 guest_tr_selector
;
377 u16 guest_intr_status
;
379 u16 host_es_selector
;
380 u16 host_cs_selector
;
381 u16 host_ss_selector
;
382 u16 host_ds_selector
;
383 u16 host_fs_selector
;
384 u16 host_gs_selector
;
385 u16 host_tr_selector
;
389 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
390 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
391 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
393 #define VMCS12_REVISION 0x11e57ed0
396 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
397 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
398 * current implementation, 4K are reserved to avoid future complications.
400 #define VMCS12_SIZE 0x1000
402 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
404 struct list_head list
;
406 struct loaded_vmcs vmcs02
;
410 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
411 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
414 /* Has the level1 guest done vmxon? */
419 /* The guest-physical address of the current VMCS L1 keeps for L2 */
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMCLEAR and VMPTRLD.
426 struct vmcs12
*cached_vmcs12
;
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
431 bool sync_shadow_vmcs
;
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool
;
436 bool change_vmcs01_virtual_x2apic_mode
;
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending
;
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
443 struct page
*apic_access_page
;
444 struct page
*virtual_apic_page
;
445 struct page
*pi_desc_page
;
446 struct pi_desc
*pi_desc
;
450 unsigned long *msr_bitmap
;
452 struct hrtimer preemption_timer
;
453 bool preemption_timer_expired
;
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
466 u32 nested_vmx_procbased_ctls_low
;
467 u32 nested_vmx_procbased_ctls_high
;
468 u32 nested_vmx_secondary_ctls_low
;
469 u32 nested_vmx_secondary_ctls_high
;
470 u32 nested_vmx_pinbased_ctls_low
;
471 u32 nested_vmx_pinbased_ctls_high
;
472 u32 nested_vmx_exit_ctls_low
;
473 u32 nested_vmx_exit_ctls_high
;
474 u32 nested_vmx_entry_ctls_low
;
475 u32 nested_vmx_entry_ctls_high
;
476 u32 nested_vmx_misc_low
;
477 u32 nested_vmx_misc_high
;
478 u32 nested_vmx_ept_caps
;
479 u32 nested_vmx_vpid_caps
;
480 u64 nested_vmx_basic
;
481 u64 nested_vmx_cr0_fixed0
;
482 u64 nested_vmx_cr0_fixed1
;
483 u64 nested_vmx_cr4_fixed0
;
484 u64 nested_vmx_cr4_fixed1
;
485 u64 nested_vmx_vmcs_enum
;
486 u64 nested_vmx_vmfunc_controls
;
489 #define POSTED_INTR_ON 0
490 #define POSTED_INTR_SN 1
492 /* Posted-Interrupt Descriptor */
494 u32 pir
[8]; /* Posted interrupt requested */
497 /* bit 256 - Outstanding Notification */
499 /* bit 257 - Suppress Notification */
501 /* bit 271:258 - Reserved */
503 /* bit 279:272 - Notification Vector */
505 /* bit 287:280 - Reserved */
507 /* bit 319:288 - Notification Destination */
515 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
517 return test_and_set_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
523 return test_and_clear_bit(POSTED_INTR_ON
,
524 (unsigned long *)&pi_desc
->control
);
527 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
529 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
532 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
534 return clear_bit(POSTED_INTR_SN
,
535 (unsigned long *)&pi_desc
->control
);
538 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
540 return set_bit(POSTED_INTR_SN
,
541 (unsigned long *)&pi_desc
->control
);
544 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
546 clear_bit(POSTED_INTR_ON
,
547 (unsigned long *)&pi_desc
->control
);
550 static inline int pi_test_on(struct pi_desc
*pi_desc
)
552 return test_bit(POSTED_INTR_ON
,
553 (unsigned long *)&pi_desc
->control
);
556 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
558 return test_bit(POSTED_INTR_SN
,
559 (unsigned long *)&pi_desc
->control
);
563 struct kvm_vcpu vcpu
;
564 unsigned long host_rsp
;
567 u32 idt_vectoring_info
;
569 struct shared_msr_entry
*guest_msrs
;
572 unsigned long host_idt_base
;
574 u64 msr_host_kernel_gs_base
;
575 u64 msr_guest_kernel_gs_base
;
577 u32 vm_entry_controls_shadow
;
578 u32 vm_exit_controls_shadow
;
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
584 struct loaded_vmcs vmcs01
;
585 struct loaded_vmcs
*loaded_vmcs
;
586 bool __launched
; /* temporary, used in vmx_vcpu_run */
587 struct msr_autoload
{
589 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
590 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
594 u16 fs_sel
, gs_sel
, ldt_sel
;
598 int gs_ldt_reload_needed
;
599 int fs_reload_needed
;
600 u64 msr_host_bndcfgs
;
601 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
602 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
607 struct kvm_segment segs
[8];
610 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
611 struct kvm_save_segment
{
619 bool emulation_required
;
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc
;
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested
;
629 /* Dynamic PLE window. */
631 bool ple_window_dirty
;
633 /* Support for PML */
634 #define PML_ENTITY_NUM 512
637 /* apic deadline value in host tsc */
640 u64 current_tsc_ratio
;
642 bool guest_pkru_valid
;
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
651 u64 msr_ia32_feature_control
;
652 u64 msr_ia32_feature_control_valid_bits
;
655 enum segment_cache_field
{
664 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
666 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
669 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
671 return &(to_vmx(vcpu
)->pi_desc
);
674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
680 static unsigned long shadow_read_only_fields
[] = {
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
695 VM_EXIT_INSTRUCTION_LEN
,
696 IDT_VECTORING_INFO_FIELD
,
697 IDT_VECTORING_ERROR_CODE
,
698 VM_EXIT_INTR_ERROR_CODE
,
700 GUEST_LINEAR_ADDRESS
,
701 GUEST_PHYSICAL_ADDRESS
703 static int max_shadow_read_only_fields
=
704 ARRAY_SIZE(shadow_read_only_fields
);
706 static unsigned long shadow_read_write_fields
[] = {
713 GUEST_INTERRUPTIBILITY_INFO
,
726 CPU_BASED_VM_EXEC_CONTROL
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
728 VM_ENTRY_INTR_INFO_FIELD
,
729 VM_ENTRY_INSTRUCTION_LEN
,
730 VM_ENTRY_EXCEPTION_ERROR_CODE
,
736 static int max_shadow_read_write_fields
=
737 ARRAY_SIZE(shadow_read_write_fields
);
739 static const unsigned short vmcs_field_to_offset_table
[] = {
740 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
741 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
742 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
743 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
744 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
745 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
746 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
747 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
748 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
749 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
750 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
751 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
752 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
753 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
754 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
755 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
756 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
757 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
758 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
759 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
760 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
761 FIELD64(MSR_BITMAP
, msr_bitmap
),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
765 FIELD64(TSC_OFFSET
, tsc_offset
),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
767 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
768 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
769 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
770 FIELD64(EPT_POINTER
, ept_pointer
),
771 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
772 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
773 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
774 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
775 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
776 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
777 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
778 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
779 FIELD64(PML_ADDRESS
, pml_address
),
780 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
781 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
782 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
783 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
784 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
785 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
786 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
787 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
788 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
789 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
790 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
791 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
792 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
793 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
794 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
795 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
796 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
797 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
798 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
799 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
800 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
801 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
802 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
803 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
804 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
805 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
806 FIELD(TPR_THRESHOLD
, tpr_threshold
),
807 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
808 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
809 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
810 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
811 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
812 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
813 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
814 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
815 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
816 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
817 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
818 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
819 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
820 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
821 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
822 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
823 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
824 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
825 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
826 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
827 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
828 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
829 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
830 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
831 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
832 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
833 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
834 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
835 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
836 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
837 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
838 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
839 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
840 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
841 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
842 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
843 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
844 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
845 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
846 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
847 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
848 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
849 FIELD(GUEST_CR0
, guest_cr0
),
850 FIELD(GUEST_CR3
, guest_cr3
),
851 FIELD(GUEST_CR4
, guest_cr4
),
852 FIELD(GUEST_ES_BASE
, guest_es_base
),
853 FIELD(GUEST_CS_BASE
, guest_cs_base
),
854 FIELD(GUEST_SS_BASE
, guest_ss_base
),
855 FIELD(GUEST_DS_BASE
, guest_ds_base
),
856 FIELD(GUEST_FS_BASE
, guest_fs_base
),
857 FIELD(GUEST_GS_BASE
, guest_gs_base
),
858 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
859 FIELD(GUEST_TR_BASE
, guest_tr_base
),
860 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
861 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
862 FIELD(GUEST_DR7
, guest_dr7
),
863 FIELD(GUEST_RSP
, guest_rsp
),
864 FIELD(GUEST_RIP
, guest_rip
),
865 FIELD(GUEST_RFLAGS
, guest_rflags
),
866 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
867 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
868 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
869 FIELD(HOST_CR0
, host_cr0
),
870 FIELD(HOST_CR3
, host_cr3
),
871 FIELD(HOST_CR4
, host_cr4
),
872 FIELD(HOST_FS_BASE
, host_fs_base
),
873 FIELD(HOST_GS_BASE
, host_gs_base
),
874 FIELD(HOST_TR_BASE
, host_tr_base
),
875 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
876 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
877 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
878 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
879 FIELD(HOST_RSP
, host_rsp
),
880 FIELD(HOST_RIP
, host_rip
),
883 static inline short vmcs_field_to_offset(unsigned long field
)
885 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
887 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
888 vmcs_field_to_offset_table
[field
] == 0)
891 return vmcs_field_to_offset_table
[field
];
894 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
896 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
899 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
900 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
901 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
902 static bool vmx_xsaves_supported(void);
903 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
904 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
905 struct kvm_segment
*var
, int seg
);
906 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
907 struct kvm_segment
*var
, int seg
);
908 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
909 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
910 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
911 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
912 static int alloc_identity_pagetable(struct kvm
*kvm
);
913 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
914 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
918 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
919 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
921 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
922 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
924 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
927 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
928 * can find which vCPU should be waken up.
930 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
931 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
936 VMX_MSR_BITMAP_LEGACY
,
937 VMX_MSR_BITMAP_LONGMODE
,
938 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
939 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
940 VMX_MSR_BITMAP_LEGACY_X2APIC
,
941 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
947 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
949 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
950 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
951 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
952 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
953 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
954 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
955 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
956 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
957 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
958 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
960 static bool cpu_has_load_ia32_efer
;
961 static bool cpu_has_load_perf_global_ctrl
;
963 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
964 static DEFINE_SPINLOCK(vmx_vpid_lock
);
966 static struct vmcs_config
{
971 u32 pin_based_exec_ctrl
;
972 u32 cpu_based_exec_ctrl
;
973 u32 cpu_based_2nd_exec_ctrl
;
978 static struct vmx_capability
{
983 #define VMX_SEGMENT_FIELD(seg) \
984 [VCPU_SREG_##seg] = { \
985 .selector = GUEST_##seg##_SELECTOR, \
986 .base = GUEST_##seg##_BASE, \
987 .limit = GUEST_##seg##_LIMIT, \
988 .ar_bytes = GUEST_##seg##_AR_BYTES, \
991 static const struct kvm_vmx_segment_field
{
996 } kvm_vmx_segment_fields
[] = {
997 VMX_SEGMENT_FIELD(CS
),
998 VMX_SEGMENT_FIELD(DS
),
999 VMX_SEGMENT_FIELD(ES
),
1000 VMX_SEGMENT_FIELD(FS
),
1001 VMX_SEGMENT_FIELD(GS
),
1002 VMX_SEGMENT_FIELD(SS
),
1003 VMX_SEGMENT_FIELD(TR
),
1004 VMX_SEGMENT_FIELD(LDTR
),
1007 static u64 host_efer
;
1009 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1012 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1013 * away by decrementing the array size.
1015 static const u32 vmx_msr_index
[] = {
1016 #ifdef CONFIG_X86_64
1017 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1019 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1022 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1024 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1025 INTR_INFO_VALID_MASK
)) ==
1026 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1029 static inline bool is_debug(u32 intr_info
)
1031 return is_exception_n(intr_info
, DB_VECTOR
);
1034 static inline bool is_breakpoint(u32 intr_info
)
1036 return is_exception_n(intr_info
, BP_VECTOR
);
1039 static inline bool is_page_fault(u32 intr_info
)
1041 return is_exception_n(intr_info
, PF_VECTOR
);
1044 static inline bool is_no_device(u32 intr_info
)
1046 return is_exception_n(intr_info
, NM_VECTOR
);
1049 static inline bool is_invalid_opcode(u32 intr_info
)
1051 return is_exception_n(intr_info
, UD_VECTOR
);
1054 static inline bool is_external_interrupt(u32 intr_info
)
1056 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1057 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1060 static inline bool is_machine_check(u32 intr_info
)
1062 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1063 INTR_INFO_VALID_MASK
)) ==
1064 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1067 static inline bool cpu_has_vmx_msr_bitmap(void)
1069 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1072 static inline bool cpu_has_vmx_tpr_shadow(void)
1074 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1077 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1079 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1082 static inline bool cpu_has_secondary_exec_ctrls(void)
1084 return vmcs_config
.cpu_based_exec_ctrl
&
1085 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1088 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1090 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1091 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1094 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1096 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1097 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1100 static inline bool cpu_has_vmx_apic_register_virt(void)
1102 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1103 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1106 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1113 * Comment's format: document - errata name - stepping - processor name.
1115 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1117 static u32 vmx_preemption_cpu_tfms
[] = {
1118 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1120 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1121 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1122 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1124 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1126 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1127 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1129 * 320767.pdf - AAP86 - B1 -
1130 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1133 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1135 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1137 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1139 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1140 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1141 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1145 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1147 u32 eax
= cpuid_eax(0x00000001), i
;
1149 /* Clear the reserved bits */
1150 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1151 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1152 if (eax
== vmx_preemption_cpu_tfms
[i
])
1158 static inline bool cpu_has_vmx_preemption_timer(void)
1160 return vmcs_config
.pin_based_exec_ctrl
&
1161 PIN_BASED_VMX_PREEMPTION_TIMER
;
1164 static inline bool cpu_has_vmx_posted_intr(void)
1166 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1167 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1170 static inline bool cpu_has_vmx_apicv(void)
1172 return cpu_has_vmx_apic_register_virt() &&
1173 cpu_has_vmx_virtual_intr_delivery() &&
1174 cpu_has_vmx_posted_intr();
1177 static inline bool cpu_has_vmx_flexpriority(void)
1179 return cpu_has_vmx_tpr_shadow() &&
1180 cpu_has_vmx_virtualize_apic_accesses();
1183 static inline bool cpu_has_vmx_ept_execute_only(void)
1185 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1188 static inline bool cpu_has_vmx_ept_2m_page(void)
1190 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1193 static inline bool cpu_has_vmx_ept_1g_page(void)
1195 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1198 static inline bool cpu_has_vmx_ept_4levels(void)
1200 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1203 static inline bool cpu_has_vmx_ept_ad_bits(void)
1205 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1208 static inline bool cpu_has_vmx_invept_context(void)
1210 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1213 static inline bool cpu_has_vmx_invept_global(void)
1215 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1218 static inline bool cpu_has_vmx_invvpid_single(void)
1220 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1223 static inline bool cpu_has_vmx_invvpid_global(void)
1225 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1228 static inline bool cpu_has_vmx_invvpid(void)
1230 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1233 static inline bool cpu_has_vmx_ept(void)
1235 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1236 SECONDARY_EXEC_ENABLE_EPT
;
1239 static inline bool cpu_has_vmx_unrestricted_guest(void)
1241 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1242 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1245 static inline bool cpu_has_vmx_ple(void)
1247 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1248 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1251 static inline bool cpu_has_vmx_basic_inout(void)
1253 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1256 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1258 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1261 static inline bool cpu_has_vmx_vpid(void)
1263 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1264 SECONDARY_EXEC_ENABLE_VPID
;
1267 static inline bool cpu_has_vmx_rdtscp(void)
1269 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1270 SECONDARY_EXEC_RDTSCP
;
1273 static inline bool cpu_has_vmx_invpcid(void)
1275 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1276 SECONDARY_EXEC_ENABLE_INVPCID
;
1279 static inline bool cpu_has_vmx_wbinvd_exit(void)
1281 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1282 SECONDARY_EXEC_WBINVD_EXITING
;
1285 static inline bool cpu_has_vmx_shadow_vmcs(void)
1288 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1289 /* check if the cpu supports writing r/o exit information fields */
1290 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1293 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1294 SECONDARY_EXEC_SHADOW_VMCS
;
1297 static inline bool cpu_has_vmx_pml(void)
1299 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1302 static inline bool cpu_has_vmx_tsc_scaling(void)
1304 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1305 SECONDARY_EXEC_TSC_SCALING
;
1308 static inline bool cpu_has_vmx_vmfunc(void)
1310 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1311 SECONDARY_EXEC_ENABLE_VMFUNC
;
1314 static inline bool report_flexpriority(void)
1316 return flexpriority_enabled
;
1319 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1321 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1324 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1326 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1329 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1331 return (vmcs12
->cpu_based_vm_exec_control
&
1332 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1333 (vmcs12
->secondary_vm_exec_control
& bit
);
1336 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1338 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1341 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1343 return vmcs12
->pin_based_vm_exec_control
&
1344 PIN_BASED_VMX_PREEMPTION_TIMER
;
1347 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1349 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1352 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1354 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1355 vmx_xsaves_supported();
1358 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1360 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1363 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1365 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1368 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1370 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1373 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1375 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1378 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1380 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1383 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1385 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1388 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1390 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1393 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1395 return nested_cpu_has_vmfunc(vmcs12
) &&
1396 (vmcs12
->vm_function_control
&
1397 VMX_VMFUNC_EPTP_SWITCHING
);
1400 static inline bool is_nmi(u32 intr_info
)
1402 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1403 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1406 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1408 unsigned long exit_qualification
);
1409 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1410 struct vmcs12
*vmcs12
,
1411 u32 reason
, unsigned long qualification
);
1413 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1417 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1418 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1423 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1429 } operand
= { vpid
, 0, gva
};
1431 asm volatile (__ex(ASM_VMX_INVVPID
)
1432 /* CF==1 or ZF==1 --> rc = -1 */
1433 "; ja 1f ; ud2 ; 1:"
1434 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1437 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1441 } operand
= {eptp
, gpa
};
1443 asm volatile (__ex(ASM_VMX_INVEPT
)
1444 /* CF==1 or ZF==1 --> rc = -1 */
1445 "; ja 1f ; ud2 ; 1:\n"
1446 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1449 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1453 i
= __find_msr_index(vmx
, msr
);
1455 return &vmx
->guest_msrs
[i
];
1459 static void vmcs_clear(struct vmcs
*vmcs
)
1461 u64 phys_addr
= __pa(vmcs
);
1464 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1465 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1468 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1472 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1474 vmcs_clear(loaded_vmcs
->vmcs
);
1475 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1476 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1477 loaded_vmcs
->cpu
= -1;
1478 loaded_vmcs
->launched
= 0;
1481 static void vmcs_load(struct vmcs
*vmcs
)
1483 u64 phys_addr
= __pa(vmcs
);
1486 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1487 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1490 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1494 #ifdef CONFIG_KEXEC_CORE
1496 * This bitmap is used to indicate whether the vmclear
1497 * operation is enabled on all cpus. All disabled by
1500 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1502 static inline void crash_enable_local_vmclear(int cpu
)
1504 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1507 static inline void crash_disable_local_vmclear(int cpu
)
1509 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1512 static inline int crash_local_vmclear_enabled(int cpu
)
1514 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1517 static void crash_vmclear_local_loaded_vmcss(void)
1519 int cpu
= raw_smp_processor_id();
1520 struct loaded_vmcs
*v
;
1522 if (!crash_local_vmclear_enabled(cpu
))
1525 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1526 loaded_vmcss_on_cpu_link
)
1527 vmcs_clear(v
->vmcs
);
1530 static inline void crash_enable_local_vmclear(int cpu
) { }
1531 static inline void crash_disable_local_vmclear(int cpu
) { }
1532 #endif /* CONFIG_KEXEC_CORE */
1534 static void __loaded_vmcs_clear(void *arg
)
1536 struct loaded_vmcs
*loaded_vmcs
= arg
;
1537 int cpu
= raw_smp_processor_id();
1539 if (loaded_vmcs
->cpu
!= cpu
)
1540 return; /* vcpu migration can race with cpu offline */
1541 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1542 per_cpu(current_vmcs
, cpu
) = NULL
;
1543 crash_disable_local_vmclear(cpu
);
1544 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1547 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1548 * is before setting loaded_vmcs->vcpu to -1 which is done in
1549 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1550 * then adds the vmcs into percpu list before it is deleted.
1554 loaded_vmcs_init(loaded_vmcs
);
1555 crash_enable_local_vmclear(cpu
);
1558 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1560 int cpu
= loaded_vmcs
->cpu
;
1563 smp_call_function_single(cpu
,
1564 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1567 static inline void vpid_sync_vcpu_single(int vpid
)
1572 if (cpu_has_vmx_invvpid_single())
1573 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1576 static inline void vpid_sync_vcpu_global(void)
1578 if (cpu_has_vmx_invvpid_global())
1579 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1582 static inline void vpid_sync_context(int vpid
)
1584 if (cpu_has_vmx_invvpid_single())
1585 vpid_sync_vcpu_single(vpid
);
1587 vpid_sync_vcpu_global();
1590 static inline void ept_sync_global(void)
1592 if (cpu_has_vmx_invept_global())
1593 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1596 static inline void ept_sync_context(u64 eptp
)
1599 if (cpu_has_vmx_invept_context())
1600 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1606 static __always_inline
void vmcs_check16(unsigned long field
)
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1609 "16-bit accessor invalid for 64-bit field");
1610 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1611 "16-bit accessor invalid for 64-bit high field");
1612 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1613 "16-bit accessor invalid for 32-bit high field");
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1615 "16-bit accessor invalid for natural width field");
1618 static __always_inline
void vmcs_check32(unsigned long field
)
1620 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1621 "32-bit accessor invalid for 16-bit field");
1622 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1623 "32-bit accessor invalid for natural width field");
1626 static __always_inline
void vmcs_check64(unsigned long field
)
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1629 "64-bit accessor invalid for 16-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1631 "64-bit accessor invalid for 64-bit high field");
1632 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1633 "64-bit accessor invalid for 32-bit field");
1634 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1635 "64-bit accessor invalid for natural width field");
1638 static __always_inline
void vmcs_checkl(unsigned long field
)
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1641 "Natural width accessor invalid for 16-bit field");
1642 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1643 "Natural width accessor invalid for 64-bit field");
1644 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1645 "Natural width accessor invalid for 64-bit high field");
1646 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1647 "Natural width accessor invalid for 32-bit field");
1650 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1652 unsigned long value
;
1654 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1655 : "=a"(value
) : "d"(field
) : "cc");
1659 static __always_inline u16
vmcs_read16(unsigned long field
)
1661 vmcs_check16(field
);
1662 return __vmcs_readl(field
);
1665 static __always_inline u32
vmcs_read32(unsigned long field
)
1667 vmcs_check32(field
);
1668 return __vmcs_readl(field
);
1671 static __always_inline u64
vmcs_read64(unsigned long field
)
1673 vmcs_check64(field
);
1674 #ifdef CONFIG_X86_64
1675 return __vmcs_readl(field
);
1677 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1681 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1684 return __vmcs_readl(field
);
1687 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1689 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1690 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1694 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1698 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1699 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1700 if (unlikely(error
))
1701 vmwrite_error(field
, value
);
1704 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1706 vmcs_check16(field
);
1707 __vmcs_writel(field
, value
);
1710 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1712 vmcs_check32(field
);
1713 __vmcs_writel(field
, value
);
1716 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1718 vmcs_check64(field
);
1719 __vmcs_writel(field
, value
);
1720 #ifndef CONFIG_X86_64
1722 __vmcs_writel(field
+1, value
>> 32);
1726 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1729 __vmcs_writel(field
, value
);
1732 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1734 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1735 "vmcs_clear_bits does not support 64-bit fields");
1736 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1739 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1741 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1742 "vmcs_set_bits does not support 64-bit fields");
1743 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1746 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1748 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1751 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1753 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1754 vmx
->vm_entry_controls_shadow
= val
;
1757 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1759 if (vmx
->vm_entry_controls_shadow
!= val
)
1760 vm_entry_controls_init(vmx
, val
);
1763 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1765 return vmx
->vm_entry_controls_shadow
;
1769 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1771 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1774 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1776 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1779 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1781 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1784 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1786 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1787 vmx
->vm_exit_controls_shadow
= val
;
1790 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1792 if (vmx
->vm_exit_controls_shadow
!= val
)
1793 vm_exit_controls_init(vmx
, val
);
1796 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1798 return vmx
->vm_exit_controls_shadow
;
1802 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1804 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1807 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1809 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1812 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1814 vmx
->segment_cache
.bitmask
= 0;
1817 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1821 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1823 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1824 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1825 vmx
->segment_cache
.bitmask
= 0;
1827 ret
= vmx
->segment_cache
.bitmask
& mask
;
1828 vmx
->segment_cache
.bitmask
|= mask
;
1832 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1834 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1836 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1837 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1841 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1843 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1845 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1846 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1850 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1852 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1854 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1855 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1859 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1861 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1863 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1864 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1868 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1872 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1873 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1874 if ((vcpu
->guest_debug
&
1875 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1876 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1877 eb
|= 1u << BP_VECTOR
;
1878 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1881 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1883 /* When we are running a nested L2 guest and L1 specified for it a
1884 * certain exception bitmap, we must trap the same exceptions and pass
1885 * them to L1. When running L2, we will only handle the exceptions
1886 * specified above if L1 did not want them.
1888 if (is_guest_mode(vcpu
))
1889 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1891 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1894 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1895 unsigned long entry
, unsigned long exit
)
1897 vm_entry_controls_clearbit(vmx
, entry
);
1898 vm_exit_controls_clearbit(vmx
, exit
);
1901 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1904 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1908 if (cpu_has_load_ia32_efer
) {
1909 clear_atomic_switch_msr_special(vmx
,
1910 VM_ENTRY_LOAD_IA32_EFER
,
1911 VM_EXIT_LOAD_IA32_EFER
);
1915 case MSR_CORE_PERF_GLOBAL_CTRL
:
1916 if (cpu_has_load_perf_global_ctrl
) {
1917 clear_atomic_switch_msr_special(vmx
,
1918 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1919 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1925 for (i
= 0; i
< m
->nr
; ++i
)
1926 if (m
->guest
[i
].index
== msr
)
1932 m
->guest
[i
] = m
->guest
[m
->nr
];
1933 m
->host
[i
] = m
->host
[m
->nr
];
1934 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1935 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1938 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1939 unsigned long entry
, unsigned long exit
,
1940 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1941 u64 guest_val
, u64 host_val
)
1943 vmcs_write64(guest_val_vmcs
, guest_val
);
1944 vmcs_write64(host_val_vmcs
, host_val
);
1945 vm_entry_controls_setbit(vmx
, entry
);
1946 vm_exit_controls_setbit(vmx
, exit
);
1949 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1950 u64 guest_val
, u64 host_val
)
1953 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1957 if (cpu_has_load_ia32_efer
) {
1958 add_atomic_switch_msr_special(vmx
,
1959 VM_ENTRY_LOAD_IA32_EFER
,
1960 VM_EXIT_LOAD_IA32_EFER
,
1963 guest_val
, host_val
);
1967 case MSR_CORE_PERF_GLOBAL_CTRL
:
1968 if (cpu_has_load_perf_global_ctrl
) {
1969 add_atomic_switch_msr_special(vmx
,
1970 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1971 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1972 GUEST_IA32_PERF_GLOBAL_CTRL
,
1973 HOST_IA32_PERF_GLOBAL_CTRL
,
1974 guest_val
, host_val
);
1978 case MSR_IA32_PEBS_ENABLE
:
1979 /* PEBS needs a quiescent period after being disabled (to write
1980 * a record). Disabling PEBS through VMX MSR swapping doesn't
1981 * provide that period, so a CPU could write host's record into
1984 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1987 for (i
= 0; i
< m
->nr
; ++i
)
1988 if (m
->guest
[i
].index
== msr
)
1991 if (i
== NR_AUTOLOAD_MSRS
) {
1992 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1993 "Can't add msr %x\n", msr
);
1995 } else if (i
== m
->nr
) {
1997 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1998 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2001 m
->guest
[i
].index
= msr
;
2002 m
->guest
[i
].value
= guest_val
;
2003 m
->host
[i
].index
= msr
;
2004 m
->host
[i
].value
= host_val
;
2007 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2009 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2010 u64 ignore_bits
= 0;
2014 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2015 * host CPUID is more efficient than testing guest CPUID
2016 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2018 if (boot_cpu_has(X86_FEATURE_SMEP
))
2019 guest_efer
|= EFER_NX
;
2020 else if (!(guest_efer
& EFER_NX
))
2021 ignore_bits
|= EFER_NX
;
2025 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2027 ignore_bits
|= EFER_SCE
;
2028 #ifdef CONFIG_X86_64
2029 ignore_bits
|= EFER_LMA
| EFER_LME
;
2030 /* SCE is meaningful only in long mode on Intel */
2031 if (guest_efer
& EFER_LMA
)
2032 ignore_bits
&= ~(u64
)EFER_SCE
;
2035 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2038 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2039 * On CPUs that support "load IA32_EFER", always switch EFER
2040 * atomically, since it's faster than switching it manually.
2042 if (cpu_has_load_ia32_efer
||
2043 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2044 if (!(guest_efer
& EFER_LMA
))
2045 guest_efer
&= ~EFER_LME
;
2046 if (guest_efer
!= host_efer
)
2047 add_atomic_switch_msr(vmx
, MSR_EFER
,
2048 guest_efer
, host_efer
);
2051 guest_efer
&= ~ignore_bits
;
2052 guest_efer
|= host_efer
& ignore_bits
;
2054 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2055 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2061 #ifdef CONFIG_X86_32
2063 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2064 * VMCS rather than the segment table. KVM uses this helper to figure
2065 * out the current bases to poke them into the VMCS before entry.
2067 static unsigned long segment_base(u16 selector
)
2069 struct desc_struct
*table
;
2072 if (!(selector
& ~SEGMENT_RPL_MASK
))
2075 table
= get_current_gdt_ro();
2077 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2078 u16 ldt_selector
= kvm_read_ldt();
2080 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2083 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2085 v
= get_desc_base(&table
[selector
>> 3]);
2090 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2092 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2095 if (vmx
->host_state
.loaded
)
2098 vmx
->host_state
.loaded
= 1;
2100 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2101 * allow segment selectors with cpl > 0 or ti == 1.
2103 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2104 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2105 savesegment(fs
, vmx
->host_state
.fs_sel
);
2106 if (!(vmx
->host_state
.fs_sel
& 7)) {
2107 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2108 vmx
->host_state
.fs_reload_needed
= 0;
2110 vmcs_write16(HOST_FS_SELECTOR
, 0);
2111 vmx
->host_state
.fs_reload_needed
= 1;
2113 savesegment(gs
, vmx
->host_state
.gs_sel
);
2114 if (!(vmx
->host_state
.gs_sel
& 7))
2115 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2117 vmcs_write16(HOST_GS_SELECTOR
, 0);
2118 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2121 #ifdef CONFIG_X86_64
2122 savesegment(ds
, vmx
->host_state
.ds_sel
);
2123 savesegment(es
, vmx
->host_state
.es_sel
);
2126 #ifdef CONFIG_X86_64
2127 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2128 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2130 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2131 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2134 #ifdef CONFIG_X86_64
2135 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2136 if (is_long_mode(&vmx
->vcpu
))
2137 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2139 if (boot_cpu_has(X86_FEATURE_MPX
))
2140 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2141 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2142 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2143 vmx
->guest_msrs
[i
].data
,
2144 vmx
->guest_msrs
[i
].mask
);
2147 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2149 if (!vmx
->host_state
.loaded
)
2152 ++vmx
->vcpu
.stat
.host_state_reload
;
2153 vmx
->host_state
.loaded
= 0;
2154 #ifdef CONFIG_X86_64
2155 if (is_long_mode(&vmx
->vcpu
))
2156 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2158 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2159 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2160 #ifdef CONFIG_X86_64
2161 load_gs_index(vmx
->host_state
.gs_sel
);
2163 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2166 if (vmx
->host_state
.fs_reload_needed
)
2167 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2168 #ifdef CONFIG_X86_64
2169 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2170 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2171 loadsegment(es
, vmx
->host_state
.es_sel
);
2174 invalidate_tss_limit();
2175 #ifdef CONFIG_X86_64
2176 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2178 if (vmx
->host_state
.msr_host_bndcfgs
)
2179 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2180 load_fixmap_gdt(raw_smp_processor_id());
2183 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2186 __vmx_load_host_state(vmx
);
2190 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2192 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2193 struct pi_desc old
, new;
2196 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2197 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2198 !kvm_vcpu_apicv_active(vcpu
))
2202 old
.control
= new.control
= pi_desc
->control
;
2205 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2206 * are two possible cases:
2207 * 1. After running 'pre_block', context switch
2208 * happened. For this case, 'sn' was set in
2209 * vmx_vcpu_put(), so we need to clear it here.
2210 * 2. After running 'pre_block', we were blocked,
2211 * and woken up by some other guy. For this case,
2212 * we don't need to do anything, 'pi_post_block'
2213 * will do everything for us. However, we cannot
2214 * check whether it is case #1 or case #2 here
2215 * (maybe, not needed), so we also clear sn here,
2216 * I think it is not a big deal.
2218 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2219 if (vcpu
->cpu
!= cpu
) {
2220 dest
= cpu_physical_id(cpu
);
2222 if (x2apic_enabled())
2225 new.ndst
= (dest
<< 8) & 0xFF00;
2228 /* set 'NV' to 'notification vector' */
2229 new.nv
= POSTED_INTR_VECTOR
;
2232 /* Allow posting non-urgent interrupts */
2234 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2235 new.control
) != old
.control
);
2238 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2240 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2241 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2245 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2246 * vcpu mutex is already taken.
2248 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2250 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2251 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2253 if (!already_loaded
) {
2254 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2255 local_irq_disable();
2256 crash_disable_local_vmclear(cpu
);
2259 * Read loaded_vmcs->cpu should be before fetching
2260 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2261 * See the comments in __loaded_vmcs_clear().
2265 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2266 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2267 crash_enable_local_vmclear(cpu
);
2271 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2272 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2273 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2276 if (!already_loaded
) {
2277 void *gdt
= get_current_gdt_ro();
2278 unsigned long sysenter_esp
;
2280 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2283 * Linux uses per-cpu TSS and GDT, so set these when switching
2284 * processors. See 22.2.4.
2286 vmcs_writel(HOST_TR_BASE
,
2287 (unsigned long)this_cpu_ptr(&cpu_tss
));
2288 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2291 * VM exits change the host TR limit to 0x67 after a VM
2292 * exit. This is okay, since 0x67 covers everything except
2293 * the IO bitmap and have have code to handle the IO bitmap
2294 * being lost after a VM exit.
2296 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2298 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2299 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2301 vmx
->loaded_vmcs
->cpu
= cpu
;
2304 /* Setup TSC multiplier */
2305 if (kvm_has_tsc_control
&&
2306 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2307 decache_tsc_multiplier(vmx
);
2309 vmx_vcpu_pi_load(vcpu
, cpu
);
2310 vmx
->host_pkru
= read_pkru();
2313 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2315 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2317 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2318 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2319 !kvm_vcpu_apicv_active(vcpu
))
2322 /* Set SN when the vCPU is preempted */
2323 if (vcpu
->preempted
)
2327 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2329 vmx_vcpu_pi_put(vcpu
);
2331 __vmx_load_host_state(to_vmx(vcpu
));
2334 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2336 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2339 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2342 * Return the cr0 value that a nested guest would read. This is a combination
2343 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2344 * its hypervisor (cr0_read_shadow).
2346 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2348 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2349 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2351 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2353 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2354 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2357 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2359 unsigned long rflags
, save_rflags
;
2361 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2362 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2363 rflags
= vmcs_readl(GUEST_RFLAGS
);
2364 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2365 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2366 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2367 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2369 to_vmx(vcpu
)->rflags
= rflags
;
2371 return to_vmx(vcpu
)->rflags
;
2374 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2376 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2378 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2379 to_vmx(vcpu
)->rflags
= rflags
;
2380 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2381 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2382 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2384 vmcs_writel(GUEST_RFLAGS
, rflags
);
2386 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2387 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2390 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2392 return to_vmx(vcpu
)->guest_pkru
;
2395 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2397 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2400 if (interruptibility
& GUEST_INTR_STATE_STI
)
2401 ret
|= KVM_X86_SHADOW_INT_STI
;
2402 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2403 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2408 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2410 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2411 u32 interruptibility
= interruptibility_old
;
2413 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2415 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2416 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2417 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2418 interruptibility
|= GUEST_INTR_STATE_STI
;
2420 if ((interruptibility
!= interruptibility_old
))
2421 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2424 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2428 rip
= kvm_rip_read(vcpu
);
2429 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2430 kvm_rip_write(vcpu
, rip
);
2432 /* skipping an emulated instruction also counts */
2433 vmx_set_interrupt_shadow(vcpu
, 0);
2436 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2437 unsigned long exit_qual
)
2439 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2440 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2441 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2443 if (vcpu
->arch
.exception
.has_error_code
) {
2444 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2445 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2448 if (kvm_exception_is_soft(nr
))
2449 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2451 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2453 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2454 vmx_get_nmi_mask(vcpu
))
2455 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2457 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2461 * KVM wants to inject page-faults which it got to the guest. This function
2462 * checks whether in a nested guest, we need to inject them to L1 or L2.
2464 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
)
2466 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2467 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2469 if (nr
== PF_VECTOR
) {
2470 if (vcpu
->arch
.exception
.nested_apf
) {
2471 nested_vmx_inject_exception_vmexit(vcpu
,
2472 vcpu
->arch
.apf
.nested_apf_token
);
2476 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2477 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2478 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2479 * can be written only when inject_pending_event runs. This should be
2480 * conditional on a new capability---if the capability is disabled,
2481 * kvm_multiple_exception would write the ancillary information to
2482 * CR2 or DR6, for backwards ABI-compatibility.
2484 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2485 vcpu
->arch
.exception
.error_code
)) {
2486 nested_vmx_inject_exception_vmexit(vcpu
, vcpu
->arch
.cr2
);
2490 unsigned long exit_qual
= 0;
2491 if (nr
== DB_VECTOR
)
2492 exit_qual
= vcpu
->arch
.dr6
;
2494 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2495 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
2503 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2505 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2506 unsigned nr
= vcpu
->arch
.exception
.nr
;
2507 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2508 bool reinject
= vcpu
->arch
.exception
.reinject
;
2509 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2510 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2512 if (!reinject
&& is_guest_mode(vcpu
) &&
2513 nested_vmx_check_exception(vcpu
))
2516 if (has_error_code
) {
2517 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2518 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2521 if (vmx
->rmode
.vm86_active
) {
2523 if (kvm_exception_is_soft(nr
))
2524 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2525 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2526 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2530 if (kvm_exception_is_soft(nr
)) {
2531 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2532 vmx
->vcpu
.arch
.event_exit_inst_len
);
2533 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2535 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2537 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2540 static bool vmx_rdtscp_supported(void)
2542 return cpu_has_vmx_rdtscp();
2545 static bool vmx_invpcid_supported(void)
2547 return cpu_has_vmx_invpcid() && enable_ept
;
2551 * Swap MSR entry in host/guest MSR entry array.
2553 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2555 struct shared_msr_entry tmp
;
2557 tmp
= vmx
->guest_msrs
[to
];
2558 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2559 vmx
->guest_msrs
[from
] = tmp
;
2562 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2564 unsigned long *msr_bitmap
;
2566 if (is_guest_mode(vcpu
))
2567 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2568 else if (cpu_has_secondary_exec_ctrls() &&
2569 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2570 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2571 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2572 if (is_long_mode(vcpu
))
2573 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2575 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2577 if (is_long_mode(vcpu
))
2578 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2580 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2583 if (is_long_mode(vcpu
))
2584 msr_bitmap
= vmx_msr_bitmap_longmode
;
2586 msr_bitmap
= vmx_msr_bitmap_legacy
;
2589 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2593 * Set up the vmcs to automatically save and restore system
2594 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2595 * mode, as fiddling with msrs is very expensive.
2597 static void setup_msrs(struct vcpu_vmx
*vmx
)
2599 int save_nmsrs
, index
;
2602 #ifdef CONFIG_X86_64
2603 if (is_long_mode(&vmx
->vcpu
)) {
2604 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2606 move_msr_up(vmx
, index
, save_nmsrs
++);
2607 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2609 move_msr_up(vmx
, index
, save_nmsrs
++);
2610 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2612 move_msr_up(vmx
, index
, save_nmsrs
++);
2613 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2614 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2615 move_msr_up(vmx
, index
, save_nmsrs
++);
2617 * MSR_STAR is only needed on long mode guests, and only
2618 * if efer.sce is enabled.
2620 index
= __find_msr_index(vmx
, MSR_STAR
);
2621 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2622 move_msr_up(vmx
, index
, save_nmsrs
++);
2625 index
= __find_msr_index(vmx
, MSR_EFER
);
2626 if (index
>= 0 && update_transition_efer(vmx
, index
))
2627 move_msr_up(vmx
, index
, save_nmsrs
++);
2629 vmx
->save_nmsrs
= save_nmsrs
;
2631 if (cpu_has_vmx_msr_bitmap())
2632 vmx_set_msr_bitmap(&vmx
->vcpu
);
2636 * reads and returns guest's timestamp counter "register"
2637 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2638 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2640 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2642 u64 host_tsc
, tsc_offset
;
2645 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2646 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2650 * writes 'offset' into guest's timestamp counter offset register
2652 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2654 if (is_guest_mode(vcpu
)) {
2656 * We're here if L1 chose not to trap WRMSR to TSC. According
2657 * to the spec, this should set L1's TSC; The offset that L1
2658 * set for L2 remains unchanged, and still needs to be added
2659 * to the newly set TSC to get L2's TSC.
2661 struct vmcs12
*vmcs12
;
2662 /* recalculate vmcs02.TSC_OFFSET: */
2663 vmcs12
= get_vmcs12(vcpu
);
2664 vmcs_write64(TSC_OFFSET
, offset
+
2665 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2666 vmcs12
->tsc_offset
: 0));
2668 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2669 vmcs_read64(TSC_OFFSET
), offset
);
2670 vmcs_write64(TSC_OFFSET
, offset
);
2675 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2676 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2677 * all guests if the "nested" module option is off, and can also be disabled
2678 * for a single guest by disabling its VMX cpuid bit.
2680 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2682 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2686 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2687 * returned for the various VMX controls MSRs when nested VMX is enabled.
2688 * The same values should also be used to verify that vmcs12 control fields are
2689 * valid during nested entry from L1 to L2.
2690 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2691 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2692 * bit in the high half is on if the corresponding bit in the control field
2693 * may be on. See also vmx_control_verify().
2695 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2698 * Note that as a general rule, the high half of the MSRs (bits in
2699 * the control fields which may be 1) should be initialized by the
2700 * intersection of the underlying hardware's MSR (i.e., features which
2701 * can be supported) and the list of features we want to expose -
2702 * because they are known to be properly supported in our code.
2703 * Also, usually, the low half of the MSRs (bits which must be 1) can
2704 * be set to 0, meaning that L1 may turn off any of these bits. The
2705 * reason is that if one of these bits is necessary, it will appear
2706 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2707 * fields of vmcs01 and vmcs02, will turn these bits off - and
2708 * nested_vmx_exit_reflected() will not pass related exits to L1.
2709 * These rules have exceptions below.
2712 /* pin-based controls */
2713 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2714 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2715 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2716 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2717 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2718 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2719 PIN_BASED_EXT_INTR_MASK
|
2720 PIN_BASED_NMI_EXITING
|
2721 PIN_BASED_VIRTUAL_NMIS
;
2722 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2723 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2724 PIN_BASED_VMX_PREEMPTION_TIMER
;
2725 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2726 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2727 PIN_BASED_POSTED_INTR
;
2730 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2731 vmx
->nested
.nested_vmx_exit_ctls_low
,
2732 vmx
->nested
.nested_vmx_exit_ctls_high
);
2733 vmx
->nested
.nested_vmx_exit_ctls_low
=
2734 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2736 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2737 #ifdef CONFIG_X86_64
2738 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2740 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2741 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2742 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2743 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2744 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2746 if (kvm_mpx_supported())
2747 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2749 /* We support free control of debug control saving. */
2750 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2752 /* entry controls */
2753 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2754 vmx
->nested
.nested_vmx_entry_ctls_low
,
2755 vmx
->nested
.nested_vmx_entry_ctls_high
);
2756 vmx
->nested
.nested_vmx_entry_ctls_low
=
2757 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2758 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2759 #ifdef CONFIG_X86_64
2760 VM_ENTRY_IA32E_MODE
|
2762 VM_ENTRY_LOAD_IA32_PAT
;
2763 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2764 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2765 if (kvm_mpx_supported())
2766 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2768 /* We support free control of debug control loading. */
2769 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2771 /* cpu-based controls */
2772 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2773 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2774 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2775 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2776 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2777 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2778 CPU_BASED_VIRTUAL_INTR_PENDING
|
2779 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2780 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2781 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2782 CPU_BASED_CR3_STORE_EXITING
|
2783 #ifdef CONFIG_X86_64
2784 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2786 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2787 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2788 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2789 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2790 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2792 * We can allow some features even when not supported by the
2793 * hardware. For example, L1 can specify an MSR bitmap - and we
2794 * can use it to avoid exits to L1 - even when L0 runs L2
2795 * without MSR bitmaps.
2797 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2798 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2799 CPU_BASED_USE_MSR_BITMAPS
;
2801 /* We support free control of CR3 access interception. */
2802 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2803 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2805 /* secondary cpu-based controls */
2806 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2809 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2810 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2811 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2812 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2813 SECONDARY_EXEC_RDTSCP
|
2814 SECONDARY_EXEC_DESC
|
2815 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2816 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2817 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2818 SECONDARY_EXEC_WBINVD_EXITING
|
2819 SECONDARY_EXEC_XSAVES
;
2822 /* nested EPT: emulate EPT also to L1 */
2823 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2824 SECONDARY_EXEC_ENABLE_EPT
;
2825 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2826 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2827 if (cpu_has_vmx_ept_execute_only())
2828 vmx
->nested
.nested_vmx_ept_caps
|=
2829 VMX_EPT_EXECUTE_ONLY_BIT
;
2830 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2831 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2832 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2833 VMX_EPT_1GB_PAGE_BIT
;
2834 if (enable_ept_ad_bits
) {
2835 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2836 SECONDARY_EXEC_ENABLE_PML
;
2837 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2840 vmx
->nested
.nested_vmx_ept_caps
= 0;
2842 if (cpu_has_vmx_vmfunc()) {
2843 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2844 SECONDARY_EXEC_ENABLE_VMFUNC
;
2846 * Advertise EPTP switching unconditionally
2847 * since we emulate it
2849 vmx
->nested
.nested_vmx_vmfunc_controls
=
2850 VMX_VMFUNC_EPTP_SWITCHING
;
2854 * Old versions of KVM use the single-context version without
2855 * checking for support, so declare that it is supported even
2856 * though it is treated as global context. The alternative is
2857 * not failing the single-context invvpid, and it is worse.
2860 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2861 SECONDARY_EXEC_ENABLE_VPID
;
2862 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2863 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2865 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2867 if (enable_unrestricted_guest
)
2868 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2869 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2871 /* miscellaneous data */
2872 rdmsr(MSR_IA32_VMX_MISC
,
2873 vmx
->nested
.nested_vmx_misc_low
,
2874 vmx
->nested
.nested_vmx_misc_high
);
2875 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2876 vmx
->nested
.nested_vmx_misc_low
|=
2877 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2878 VMX_MISC_ACTIVITY_HLT
;
2879 vmx
->nested
.nested_vmx_misc_high
= 0;
2882 * This MSR reports some information about VMX support. We
2883 * should return information about the VMX we emulate for the
2884 * guest, and the VMCS structure we give it - not about the
2885 * VMX support of the underlying hardware.
2887 vmx
->nested
.nested_vmx_basic
=
2889 VMX_BASIC_TRUE_CTLS
|
2890 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2891 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2893 if (cpu_has_vmx_basic_inout())
2894 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2897 * These MSRs specify bits which the guest must keep fixed on
2898 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2899 * We picked the standard core2 setting.
2901 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2902 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2903 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2904 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2906 /* These MSRs specify bits which the guest must keep fixed off. */
2907 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2908 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2910 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2911 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2915 * if fixed0[i] == 1: val[i] must be 1
2916 * if fixed1[i] == 0: val[i] must be 0
2918 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2920 return ((val
& fixed1
) | fixed0
) == val
;
2923 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2925 return fixed_bits_valid(control
, low
, high
);
2928 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2930 return low
| ((u64
)high
<< 32);
2933 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2938 return (superset
| subset
) == superset
;
2941 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2943 const u64 feature_and_reserved
=
2944 /* feature (except bit 48; see below) */
2945 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2947 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2948 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2950 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2954 * KVM does not emulate a version of VMX that constrains physical
2955 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2957 if (data
& BIT_ULL(48))
2960 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2961 vmx_basic_vmcs_revision_id(data
))
2964 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2967 vmx
->nested
.nested_vmx_basic
= data
;
2972 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2977 switch (msr_index
) {
2978 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2979 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2980 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2982 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2983 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2984 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2986 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2987 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2988 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2990 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2991 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2992 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2994 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2995 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2996 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3002 supported
= vmx_control_msr(*lowp
, *highp
);
3004 /* Check must-be-1 bits are still 1. */
3005 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3008 /* Check must-be-0 bits are still 0. */
3009 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3013 *highp
= data
>> 32;
3017 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3019 const u64 feature_and_reserved_bits
=
3021 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3022 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3024 GENMASK_ULL(13, 9) | BIT_ULL(31);
3027 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3028 vmx
->nested
.nested_vmx_misc_high
);
3030 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3033 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3034 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3035 vmx_misc_preemption_timer_rate(data
) !=
3036 vmx_misc_preemption_timer_rate(vmx_misc
))
3039 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3042 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3045 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3048 vmx
->nested
.nested_vmx_misc_low
= data
;
3049 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3053 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3055 u64 vmx_ept_vpid_cap
;
3057 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3058 vmx
->nested
.nested_vmx_vpid_caps
);
3060 /* Every bit is either reserved or a feature bit. */
3061 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3064 vmx
->nested
.nested_vmx_ept_caps
= data
;
3065 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3069 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3073 switch (msr_index
) {
3074 case MSR_IA32_VMX_CR0_FIXED0
:
3075 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3077 case MSR_IA32_VMX_CR4_FIXED0
:
3078 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3085 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3086 * must be 1 in the restored value.
3088 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3096 * Called when userspace is restoring VMX MSRs.
3098 * Returns 0 on success, non-0 otherwise.
3100 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3102 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3104 switch (msr_index
) {
3105 case MSR_IA32_VMX_BASIC
:
3106 return vmx_restore_vmx_basic(vmx
, data
);
3107 case MSR_IA32_VMX_PINBASED_CTLS
:
3108 case MSR_IA32_VMX_PROCBASED_CTLS
:
3109 case MSR_IA32_VMX_EXIT_CTLS
:
3110 case MSR_IA32_VMX_ENTRY_CTLS
:
3112 * The "non-true" VMX capability MSRs are generated from the
3113 * "true" MSRs, so we do not support restoring them directly.
3115 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3116 * should restore the "true" MSRs with the must-be-1 bits
3117 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3118 * DEFAULT SETTINGS".
3121 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3122 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3123 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3124 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3125 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3126 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3127 case MSR_IA32_VMX_MISC
:
3128 return vmx_restore_vmx_misc(vmx
, data
);
3129 case MSR_IA32_VMX_CR0_FIXED0
:
3130 case MSR_IA32_VMX_CR4_FIXED0
:
3131 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3132 case MSR_IA32_VMX_CR0_FIXED1
:
3133 case MSR_IA32_VMX_CR4_FIXED1
:
3135 * These MSRs are generated based on the vCPU's CPUID, so we
3136 * do not support restoring them directly.
3139 case MSR_IA32_VMX_EPT_VPID_CAP
:
3140 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3141 case MSR_IA32_VMX_VMCS_ENUM
:
3142 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3146 * The rest of the VMX capability MSRs do not support restore.
3152 /* Returns 0 on success, non-0 otherwise. */
3153 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3157 switch (msr_index
) {
3158 case MSR_IA32_VMX_BASIC
:
3159 *pdata
= vmx
->nested
.nested_vmx_basic
;
3161 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3162 case MSR_IA32_VMX_PINBASED_CTLS
:
3163 *pdata
= vmx_control_msr(
3164 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3165 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3166 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3167 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3169 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3170 case MSR_IA32_VMX_PROCBASED_CTLS
:
3171 *pdata
= vmx_control_msr(
3172 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3173 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3174 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3175 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3177 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3178 case MSR_IA32_VMX_EXIT_CTLS
:
3179 *pdata
= vmx_control_msr(
3180 vmx
->nested
.nested_vmx_exit_ctls_low
,
3181 vmx
->nested
.nested_vmx_exit_ctls_high
);
3182 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3183 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3185 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3186 case MSR_IA32_VMX_ENTRY_CTLS
:
3187 *pdata
= vmx_control_msr(
3188 vmx
->nested
.nested_vmx_entry_ctls_low
,
3189 vmx
->nested
.nested_vmx_entry_ctls_high
);
3190 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3191 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3193 case MSR_IA32_VMX_MISC
:
3194 *pdata
= vmx_control_msr(
3195 vmx
->nested
.nested_vmx_misc_low
,
3196 vmx
->nested
.nested_vmx_misc_high
);
3198 case MSR_IA32_VMX_CR0_FIXED0
:
3199 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3201 case MSR_IA32_VMX_CR0_FIXED1
:
3202 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3204 case MSR_IA32_VMX_CR4_FIXED0
:
3205 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3207 case MSR_IA32_VMX_CR4_FIXED1
:
3208 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3210 case MSR_IA32_VMX_VMCS_ENUM
:
3211 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3213 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3214 *pdata
= vmx_control_msr(
3215 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3216 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3218 case MSR_IA32_VMX_EPT_VPID_CAP
:
3219 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3220 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3222 case MSR_IA32_VMX_VMFUNC
:
3223 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3232 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3235 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3237 return !(val
& ~valid_bits
);
3241 * Reads an msr value (of 'msr_index') into 'pdata'.
3242 * Returns 0 on success, non-0 otherwise.
3243 * Assumes vcpu_load() was already called.
3245 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3247 struct shared_msr_entry
*msr
;
3249 switch (msr_info
->index
) {
3250 #ifdef CONFIG_X86_64
3252 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3255 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3257 case MSR_KERNEL_GS_BASE
:
3258 vmx_load_host_state(to_vmx(vcpu
));
3259 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3263 return kvm_get_msr_common(vcpu
, msr_info
);
3265 msr_info
->data
= guest_read_tsc(vcpu
);
3267 case MSR_IA32_SYSENTER_CS
:
3268 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3270 case MSR_IA32_SYSENTER_EIP
:
3271 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3273 case MSR_IA32_SYSENTER_ESP
:
3274 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3276 case MSR_IA32_BNDCFGS
:
3277 if (!kvm_mpx_supported() ||
3278 (!msr_info
->host_initiated
&&
3279 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3281 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3283 case MSR_IA32_MCG_EXT_CTL
:
3284 if (!msr_info
->host_initiated
&&
3285 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3286 FEATURE_CONTROL_LMCE
))
3288 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3290 case MSR_IA32_FEATURE_CONTROL
:
3291 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3293 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3294 if (!nested_vmx_allowed(vcpu
))
3296 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3298 if (!vmx_xsaves_supported())
3300 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3303 if (!msr_info
->host_initiated
&&
3304 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3306 /* Otherwise falls through */
3308 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3310 msr_info
->data
= msr
->data
;
3313 return kvm_get_msr_common(vcpu
, msr_info
);
3319 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3322 * Writes msr value into into the appropriate "register".
3323 * Returns 0 on success, non-0 otherwise.
3324 * Assumes vcpu_load() was already called.
3326 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3328 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3329 struct shared_msr_entry
*msr
;
3331 u32 msr_index
= msr_info
->index
;
3332 u64 data
= msr_info
->data
;
3334 switch (msr_index
) {
3336 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3338 #ifdef CONFIG_X86_64
3340 vmx_segment_cache_clear(vmx
);
3341 vmcs_writel(GUEST_FS_BASE
, data
);
3344 vmx_segment_cache_clear(vmx
);
3345 vmcs_writel(GUEST_GS_BASE
, data
);
3347 case MSR_KERNEL_GS_BASE
:
3348 vmx_load_host_state(vmx
);
3349 vmx
->msr_guest_kernel_gs_base
= data
;
3352 case MSR_IA32_SYSENTER_CS
:
3353 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3355 case MSR_IA32_SYSENTER_EIP
:
3356 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3358 case MSR_IA32_SYSENTER_ESP
:
3359 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3361 case MSR_IA32_BNDCFGS
:
3362 if (!kvm_mpx_supported() ||
3363 (!msr_info
->host_initiated
&&
3364 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3366 if (is_noncanonical_address(data
& PAGE_MASK
) ||
3367 (data
& MSR_IA32_BNDCFGS_RSVD
))
3369 vmcs_write64(GUEST_BNDCFGS
, data
);
3372 kvm_write_tsc(vcpu
, msr_info
);
3374 case MSR_IA32_CR_PAT
:
3375 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3376 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3378 vmcs_write64(GUEST_IA32_PAT
, data
);
3379 vcpu
->arch
.pat
= data
;
3382 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3384 case MSR_IA32_TSC_ADJUST
:
3385 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3387 case MSR_IA32_MCG_EXT_CTL
:
3388 if ((!msr_info
->host_initiated
&&
3389 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3390 FEATURE_CONTROL_LMCE
)) ||
3391 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3393 vcpu
->arch
.mcg_ext_ctl
= data
;
3395 case MSR_IA32_FEATURE_CONTROL
:
3396 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3397 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3398 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3400 vmx
->msr_ia32_feature_control
= data
;
3401 if (msr_info
->host_initiated
&& data
== 0)
3402 vmx_leave_nested(vcpu
);
3404 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3405 if (!msr_info
->host_initiated
)
3406 return 1; /* they are read-only */
3407 if (!nested_vmx_allowed(vcpu
))
3409 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3411 if (!vmx_xsaves_supported())
3414 * The only supported bit as of Skylake is bit 8, but
3415 * it is not supported on KVM.
3419 vcpu
->arch
.ia32_xss
= data
;
3420 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3421 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3422 vcpu
->arch
.ia32_xss
, host_xss
);
3424 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3427 if (!msr_info
->host_initiated
&&
3428 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3430 /* Check reserved bit, higher 32 bits should be zero */
3431 if ((data
>> 32) != 0)
3433 /* Otherwise falls through */
3435 msr
= find_msr_entry(vmx
, msr_index
);
3437 u64 old_msr_data
= msr
->data
;
3439 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3441 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3445 msr
->data
= old_msr_data
;
3449 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3455 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3457 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3460 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3463 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3465 case VCPU_EXREG_PDPTR
:
3467 ept_save_pdptrs(vcpu
);
3474 static __init
int cpu_has_kvm_support(void)
3476 return cpu_has_vmx();
3479 static __init
int vmx_disabled_by_bios(void)
3483 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3484 if (msr
& FEATURE_CONTROL_LOCKED
) {
3485 /* launched w/ TXT and VMX disabled */
3486 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3489 /* launched w/o TXT and VMX only enabled w/ TXT */
3490 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3491 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3492 && !tboot_enabled()) {
3493 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3494 "activate TXT before enabling KVM\n");
3497 /* launched w/o TXT and VMX disabled */
3498 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3499 && !tboot_enabled())
3506 static void kvm_cpu_vmxon(u64 addr
)
3508 cr4_set_bits(X86_CR4_VMXE
);
3509 intel_pt_handle_vmx(1);
3511 asm volatile (ASM_VMX_VMXON_RAX
3512 : : "a"(&addr
), "m"(addr
)
3516 static int hardware_enable(void)
3518 int cpu
= raw_smp_processor_id();
3519 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3522 if (cr4_read_shadow() & X86_CR4_VMXE
)
3525 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3526 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3527 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3530 * Now we can enable the vmclear operation in kdump
3531 * since the loaded_vmcss_on_cpu list on this cpu
3532 * has been initialized.
3534 * Though the cpu is not in VMX operation now, there
3535 * is no problem to enable the vmclear operation
3536 * for the loaded_vmcss_on_cpu list is empty!
3538 crash_enable_local_vmclear(cpu
);
3540 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3542 test_bits
= FEATURE_CONTROL_LOCKED
;
3543 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3544 if (tboot_enabled())
3545 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3547 if ((old
& test_bits
) != test_bits
) {
3548 /* enable and lock */
3549 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3551 kvm_cpu_vmxon(phys_addr
);
3557 static void vmclear_local_loaded_vmcss(void)
3559 int cpu
= raw_smp_processor_id();
3560 struct loaded_vmcs
*v
, *n
;
3562 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3563 loaded_vmcss_on_cpu_link
)
3564 __loaded_vmcs_clear(v
);
3568 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3571 static void kvm_cpu_vmxoff(void)
3573 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3575 intel_pt_handle_vmx(0);
3576 cr4_clear_bits(X86_CR4_VMXE
);
3579 static void hardware_disable(void)
3581 vmclear_local_loaded_vmcss();
3585 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3586 u32 msr
, u32
*result
)
3588 u32 vmx_msr_low
, vmx_msr_high
;
3589 u32 ctl
= ctl_min
| ctl_opt
;
3591 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3593 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3594 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3596 /* Ensure minimum (required) set of control bits are supported. */
3604 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3606 u32 vmx_msr_low
, vmx_msr_high
;
3608 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3609 return vmx_msr_high
& ctl
;
3612 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3614 u32 vmx_msr_low
, vmx_msr_high
;
3615 u32 min
, opt
, min2
, opt2
;
3616 u32 _pin_based_exec_control
= 0;
3617 u32 _cpu_based_exec_control
= 0;
3618 u32 _cpu_based_2nd_exec_control
= 0;
3619 u32 _vmexit_control
= 0;
3620 u32 _vmentry_control
= 0;
3622 min
= CPU_BASED_HLT_EXITING
|
3623 #ifdef CONFIG_X86_64
3624 CPU_BASED_CR8_LOAD_EXITING
|
3625 CPU_BASED_CR8_STORE_EXITING
|
3627 CPU_BASED_CR3_LOAD_EXITING
|
3628 CPU_BASED_CR3_STORE_EXITING
|
3629 CPU_BASED_USE_IO_BITMAPS
|
3630 CPU_BASED_MOV_DR_EXITING
|
3631 CPU_BASED_USE_TSC_OFFSETING
|
3632 CPU_BASED_INVLPG_EXITING
|
3633 CPU_BASED_RDPMC_EXITING
;
3635 if (!kvm_mwait_in_guest())
3636 min
|= CPU_BASED_MWAIT_EXITING
|
3637 CPU_BASED_MONITOR_EXITING
;
3639 opt
= CPU_BASED_TPR_SHADOW
|
3640 CPU_BASED_USE_MSR_BITMAPS
|
3641 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3642 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3643 &_cpu_based_exec_control
) < 0)
3645 #ifdef CONFIG_X86_64
3646 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3647 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3648 ~CPU_BASED_CR8_STORE_EXITING
;
3650 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3652 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3653 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3654 SECONDARY_EXEC_WBINVD_EXITING
|
3655 SECONDARY_EXEC_ENABLE_VPID
|
3656 SECONDARY_EXEC_ENABLE_EPT
|
3657 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3658 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3659 SECONDARY_EXEC_RDTSCP
|
3660 SECONDARY_EXEC_ENABLE_INVPCID
|
3661 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3662 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3663 SECONDARY_EXEC_SHADOW_VMCS
|
3664 SECONDARY_EXEC_XSAVES
|
3665 SECONDARY_EXEC_ENABLE_PML
|
3666 SECONDARY_EXEC_TSC_SCALING
|
3667 SECONDARY_EXEC_ENABLE_VMFUNC
;
3668 if (adjust_vmx_controls(min2
, opt2
,
3669 MSR_IA32_VMX_PROCBASED_CTLS2
,
3670 &_cpu_based_2nd_exec_control
) < 0)
3673 #ifndef CONFIG_X86_64
3674 if (!(_cpu_based_2nd_exec_control
&
3675 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3676 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3679 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3680 _cpu_based_2nd_exec_control
&= ~(
3681 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3682 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3683 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3685 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3686 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3688 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3689 CPU_BASED_CR3_STORE_EXITING
|
3690 CPU_BASED_INVLPG_EXITING
);
3691 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3692 vmx_capability
.ept
, vmx_capability
.vpid
);
3695 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3696 #ifdef CONFIG_X86_64
3697 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3699 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3700 VM_EXIT_CLEAR_BNDCFGS
;
3701 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3702 &_vmexit_control
) < 0)
3705 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3706 PIN_BASED_VIRTUAL_NMIS
;
3707 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3708 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3709 &_pin_based_exec_control
) < 0)
3712 if (cpu_has_broken_vmx_preemption_timer())
3713 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3714 if (!(_cpu_based_2nd_exec_control
&
3715 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3716 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3718 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3719 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3720 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3721 &_vmentry_control
) < 0)
3724 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3726 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3727 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3730 #ifdef CONFIG_X86_64
3731 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3732 if (vmx_msr_high
& (1u<<16))
3736 /* Require Write-Back (WB) memory type for VMCS accesses. */
3737 if (((vmx_msr_high
>> 18) & 15) != 6)
3740 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3741 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3742 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3743 vmcs_conf
->revision_id
= vmx_msr_low
;
3745 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3746 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3747 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3748 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3749 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3751 cpu_has_load_ia32_efer
=
3752 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3753 VM_ENTRY_LOAD_IA32_EFER
)
3754 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3755 VM_EXIT_LOAD_IA32_EFER
);
3757 cpu_has_load_perf_global_ctrl
=
3758 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3759 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3760 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3761 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3764 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3765 * but due to errata below it can't be used. Workaround is to use
3766 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3768 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3773 * BC86,AAY89,BD102 (model 44)
3777 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3778 switch (boot_cpu_data
.x86_model
) {
3784 cpu_has_load_perf_global_ctrl
= false;
3785 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3786 "does not work properly. Using workaround\n");
3793 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3794 rdmsrl(MSR_IA32_XSS
, host_xss
);
3799 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3801 int node
= cpu_to_node(cpu
);
3805 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3808 vmcs
= page_address(pages
);
3809 memset(vmcs
, 0, vmcs_config
.size
);
3810 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3814 static struct vmcs
*alloc_vmcs(void)
3816 return alloc_vmcs_cpu(raw_smp_processor_id());
3819 static void free_vmcs(struct vmcs
*vmcs
)
3821 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3825 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3827 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3829 if (!loaded_vmcs
->vmcs
)
3831 loaded_vmcs_clear(loaded_vmcs
);
3832 free_vmcs(loaded_vmcs
->vmcs
);
3833 loaded_vmcs
->vmcs
= NULL
;
3834 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3837 static void free_kvm_area(void)
3841 for_each_possible_cpu(cpu
) {
3842 free_vmcs(per_cpu(vmxarea
, cpu
));
3843 per_cpu(vmxarea
, cpu
) = NULL
;
3847 enum vmcs_field_type
{
3848 VMCS_FIELD_TYPE_U16
= 0,
3849 VMCS_FIELD_TYPE_U64
= 1,
3850 VMCS_FIELD_TYPE_U32
= 2,
3851 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3854 static inline int vmcs_field_type(unsigned long field
)
3856 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3857 return VMCS_FIELD_TYPE_U32
;
3858 return (field
>> 13) & 0x3 ;
3861 static inline int vmcs_field_readonly(unsigned long field
)
3863 return (((field
>> 10) & 0x3) == 1);
3866 static void init_vmcs_shadow_fields(void)
3870 /* No checks for read only fields yet */
3872 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3873 switch (shadow_read_write_fields
[i
]) {
3875 if (!kvm_mpx_supported())
3883 shadow_read_write_fields
[j
] =
3884 shadow_read_write_fields
[i
];
3887 max_shadow_read_write_fields
= j
;
3889 /* shadowed fields guest access without vmexit */
3890 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3891 unsigned long field
= shadow_read_write_fields
[i
];
3893 clear_bit(field
, vmx_vmwrite_bitmap
);
3894 clear_bit(field
, vmx_vmread_bitmap
);
3895 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3896 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3897 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3900 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3901 unsigned long field
= shadow_read_only_fields
[i
];
3903 clear_bit(field
, vmx_vmread_bitmap
);
3904 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3905 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3909 static __init
int alloc_kvm_area(void)
3913 for_each_possible_cpu(cpu
) {
3916 vmcs
= alloc_vmcs_cpu(cpu
);
3922 per_cpu(vmxarea
, cpu
) = vmcs
;
3927 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3928 struct kvm_segment
*save
)
3930 if (!emulate_invalid_guest_state
) {
3932 * CS and SS RPL should be equal during guest entry according
3933 * to VMX spec, but in reality it is not always so. Since vcpu
3934 * is in the middle of the transition from real mode to
3935 * protected mode it is safe to assume that RPL 0 is a good
3938 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3939 save
->selector
&= ~SEGMENT_RPL_MASK
;
3940 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3943 vmx_set_segment(vcpu
, save
, seg
);
3946 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3948 unsigned long flags
;
3949 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3952 * Update real mode segment cache. It may be not up-to-date if sement
3953 * register was written while vcpu was in a guest mode.
3955 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3956 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3957 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3958 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3959 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3960 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3962 vmx
->rmode
.vm86_active
= 0;
3964 vmx_segment_cache_clear(vmx
);
3966 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3968 flags
= vmcs_readl(GUEST_RFLAGS
);
3969 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3970 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3971 vmcs_writel(GUEST_RFLAGS
, flags
);
3973 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3974 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3976 update_exception_bitmap(vcpu
);
3978 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3979 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3980 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3981 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3982 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3983 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3986 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3988 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3989 struct kvm_segment var
= *save
;
3992 if (seg
== VCPU_SREG_CS
)
3995 if (!emulate_invalid_guest_state
) {
3996 var
.selector
= var
.base
>> 4;
3997 var
.base
= var
.base
& 0xffff0;
4007 if (save
->base
& 0xf)
4008 printk_once(KERN_WARNING
"kvm: segment base is not "
4009 "paragraph aligned when entering "
4010 "protected mode (seg=%d)", seg
);
4013 vmcs_write16(sf
->selector
, var
.selector
);
4014 vmcs_writel(sf
->base
, var
.base
);
4015 vmcs_write32(sf
->limit
, var
.limit
);
4016 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4019 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4021 unsigned long flags
;
4022 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4024 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4025 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4026 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4027 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4028 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4029 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4030 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4032 vmx
->rmode
.vm86_active
= 1;
4035 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4036 * vcpu. Warn the user that an update is overdue.
4038 if (!vcpu
->kvm
->arch
.tss_addr
)
4039 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4040 "called before entering vcpu\n");
4042 vmx_segment_cache_clear(vmx
);
4044 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4045 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4046 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4048 flags
= vmcs_readl(GUEST_RFLAGS
);
4049 vmx
->rmode
.save_rflags
= flags
;
4051 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4053 vmcs_writel(GUEST_RFLAGS
, flags
);
4054 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4055 update_exception_bitmap(vcpu
);
4057 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4058 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4059 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4060 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4061 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4062 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4064 kvm_mmu_reset_context(vcpu
);
4067 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4069 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4070 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4076 * Force kernel_gs_base reloading before EFER changes, as control
4077 * of this msr depends on is_long_mode().
4079 vmx_load_host_state(to_vmx(vcpu
));
4080 vcpu
->arch
.efer
= efer
;
4081 if (efer
& EFER_LMA
) {
4082 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4085 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4087 msr
->data
= efer
& ~EFER_LME
;
4092 #ifdef CONFIG_X86_64
4094 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4098 vmx_segment_cache_clear(to_vmx(vcpu
));
4100 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4101 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4102 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4104 vmcs_write32(GUEST_TR_AR_BYTES
,
4105 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4106 | VMX_AR_TYPE_BUSY_64_TSS
);
4108 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4111 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4113 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4114 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4119 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4122 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4124 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4126 vpid_sync_context(vpid
);
4130 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4132 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4135 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4138 vmx_flush_tlb(vcpu
);
4141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4143 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4145 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4146 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4149 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4151 if (enable_ept
&& is_paging(vcpu
))
4152 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4153 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4156 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4158 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4160 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4161 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4164 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4166 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4168 if (!test_bit(VCPU_EXREG_PDPTR
,
4169 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4172 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4173 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4174 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4175 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4176 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4180 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4182 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4184 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4185 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4186 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4187 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4188 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4191 __set_bit(VCPU_EXREG_PDPTR
,
4192 (unsigned long *)&vcpu
->arch
.regs_avail
);
4193 __set_bit(VCPU_EXREG_PDPTR
,
4194 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4197 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4199 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4200 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4201 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4203 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4204 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4205 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4206 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4208 return fixed_bits_valid(val
, fixed0
, fixed1
);
4211 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4213 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4214 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4216 return fixed_bits_valid(val
, fixed0
, fixed1
);
4219 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4221 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4222 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4224 return fixed_bits_valid(val
, fixed0
, fixed1
);
4227 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4228 #define nested_guest_cr4_valid nested_cr4_valid
4229 #define nested_host_cr4_valid nested_cr4_valid
4231 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4233 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4235 struct kvm_vcpu
*vcpu
)
4237 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4238 vmx_decache_cr3(vcpu
);
4239 if (!(cr0
& X86_CR0_PG
)) {
4240 /* From paging/starting to nonpaging */
4241 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4242 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4243 (CPU_BASED_CR3_LOAD_EXITING
|
4244 CPU_BASED_CR3_STORE_EXITING
));
4245 vcpu
->arch
.cr0
= cr0
;
4246 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4247 } else if (!is_paging(vcpu
)) {
4248 /* From nonpaging to paging */
4249 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4250 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4251 ~(CPU_BASED_CR3_LOAD_EXITING
|
4252 CPU_BASED_CR3_STORE_EXITING
));
4253 vcpu
->arch
.cr0
= cr0
;
4254 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4257 if (!(cr0
& X86_CR0_WP
))
4258 *hw_cr0
&= ~X86_CR0_WP
;
4261 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4263 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4264 unsigned long hw_cr0
;
4266 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4267 if (enable_unrestricted_guest
)
4268 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4270 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4272 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4275 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4279 #ifdef CONFIG_X86_64
4280 if (vcpu
->arch
.efer
& EFER_LME
) {
4281 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4283 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4289 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4291 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4292 vmcs_writel(GUEST_CR0
, hw_cr0
);
4293 vcpu
->arch
.cr0
= cr0
;
4295 /* depends on vcpu->arch.cr0 to be set to a new value */
4296 vmx
->emulation_required
= emulation_required(vcpu
);
4299 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4303 /* TODO write the value reading from MSR */
4304 eptp
= VMX_EPT_DEFAULT_MT
|
4305 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4306 if (enable_ept_ad_bits
&&
4307 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4308 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4309 eptp
|= (root_hpa
& PAGE_MASK
);
4314 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4316 unsigned long guest_cr3
;
4321 eptp
= construct_eptp(vcpu
, cr3
);
4322 vmcs_write64(EPT_POINTER
, eptp
);
4323 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4324 guest_cr3
= kvm_read_cr3(vcpu
);
4326 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4327 ept_load_pdptrs(vcpu
);
4330 vmx_flush_tlb(vcpu
);
4331 vmcs_writel(GUEST_CR3
, guest_cr3
);
4334 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4337 * Pass through host's Machine Check Enable value to hw_cr4, which
4338 * is in force while we are in guest mode. Do not let guests control
4339 * this bit, even if host CR4.MCE == 0.
4341 unsigned long hw_cr4
=
4342 (cr4_read_shadow() & X86_CR4_MCE
) |
4343 (cr4
& ~X86_CR4_MCE
) |
4344 (to_vmx(vcpu
)->rmode
.vm86_active
?
4345 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4347 if (cr4
& X86_CR4_VMXE
) {
4349 * To use VMXON (and later other VMX instructions), a guest
4350 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4351 * So basically the check on whether to allow nested VMX
4354 if (!nested_vmx_allowed(vcpu
))
4358 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4361 vcpu
->arch
.cr4
= cr4
;
4363 if (!is_paging(vcpu
)) {
4364 hw_cr4
&= ~X86_CR4_PAE
;
4365 hw_cr4
|= X86_CR4_PSE
;
4366 } else if (!(cr4
& X86_CR4_PAE
)) {
4367 hw_cr4
&= ~X86_CR4_PAE
;
4371 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4373 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4374 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4375 * to be manually disabled when guest switches to non-paging
4378 * If !enable_unrestricted_guest, the CPU is always running
4379 * with CR0.PG=1 and CR4 needs to be modified.
4380 * If enable_unrestricted_guest, the CPU automatically
4381 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4383 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4385 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4386 vmcs_writel(GUEST_CR4
, hw_cr4
);
4390 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4391 struct kvm_segment
*var
, int seg
)
4393 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4396 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4397 *var
= vmx
->rmode
.segs
[seg
];
4398 if (seg
== VCPU_SREG_TR
4399 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4401 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4402 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4405 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4406 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4407 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4408 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4409 var
->unusable
= (ar
>> 16) & 1;
4410 var
->type
= ar
& 15;
4411 var
->s
= (ar
>> 4) & 1;
4412 var
->dpl
= (ar
>> 5) & 3;
4414 * Some userspaces do not preserve unusable property. Since usable
4415 * segment has to be present according to VMX spec we can use present
4416 * property to amend userspace bug by making unusable segment always
4417 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4418 * segment as unusable.
4420 var
->present
= !var
->unusable
;
4421 var
->avl
= (ar
>> 12) & 1;
4422 var
->l
= (ar
>> 13) & 1;
4423 var
->db
= (ar
>> 14) & 1;
4424 var
->g
= (ar
>> 15) & 1;
4427 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4429 struct kvm_segment s
;
4431 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4432 vmx_get_segment(vcpu
, &s
, seg
);
4435 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4438 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4440 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4442 if (unlikely(vmx
->rmode
.vm86_active
))
4445 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4446 return VMX_AR_DPL(ar
);
4450 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4454 if (var
->unusable
|| !var
->present
)
4457 ar
= var
->type
& 15;
4458 ar
|= (var
->s
& 1) << 4;
4459 ar
|= (var
->dpl
& 3) << 5;
4460 ar
|= (var
->present
& 1) << 7;
4461 ar
|= (var
->avl
& 1) << 12;
4462 ar
|= (var
->l
& 1) << 13;
4463 ar
|= (var
->db
& 1) << 14;
4464 ar
|= (var
->g
& 1) << 15;
4470 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4471 struct kvm_segment
*var
, int seg
)
4473 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4474 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4476 vmx_segment_cache_clear(vmx
);
4478 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4479 vmx
->rmode
.segs
[seg
] = *var
;
4480 if (seg
== VCPU_SREG_TR
)
4481 vmcs_write16(sf
->selector
, var
->selector
);
4483 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4487 vmcs_writel(sf
->base
, var
->base
);
4488 vmcs_write32(sf
->limit
, var
->limit
);
4489 vmcs_write16(sf
->selector
, var
->selector
);
4492 * Fix the "Accessed" bit in AR field of segment registers for older
4494 * IA32 arch specifies that at the time of processor reset the
4495 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4496 * is setting it to 0 in the userland code. This causes invalid guest
4497 * state vmexit when "unrestricted guest" mode is turned on.
4498 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4499 * tree. Newer qemu binaries with that qemu fix would not need this
4502 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4503 var
->type
|= 0x1; /* Accessed */
4505 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4508 vmx
->emulation_required
= emulation_required(vcpu
);
4511 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4513 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4515 *db
= (ar
>> 14) & 1;
4516 *l
= (ar
>> 13) & 1;
4519 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4521 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4522 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4525 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4527 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4528 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4531 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4533 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4534 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4537 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4539 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4540 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4543 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4545 struct kvm_segment var
;
4548 vmx_get_segment(vcpu
, &var
, seg
);
4550 if (seg
== VCPU_SREG_CS
)
4552 ar
= vmx_segment_access_rights(&var
);
4554 if (var
.base
!= (var
.selector
<< 4))
4556 if (var
.limit
!= 0xffff)
4564 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4566 struct kvm_segment cs
;
4567 unsigned int cs_rpl
;
4569 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4570 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4574 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4578 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4579 if (cs
.dpl
> cs_rpl
)
4582 if (cs
.dpl
!= cs_rpl
)
4588 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4592 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4594 struct kvm_segment ss
;
4595 unsigned int ss_rpl
;
4597 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4598 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4602 if (ss
.type
!= 3 && ss
.type
!= 7)
4606 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4614 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4616 struct kvm_segment var
;
4619 vmx_get_segment(vcpu
, &var
, seg
);
4620 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4628 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4629 if (var
.dpl
< rpl
) /* DPL < RPL */
4633 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4639 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4641 struct kvm_segment tr
;
4643 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4647 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4649 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4657 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4659 struct kvm_segment ldtr
;
4661 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4665 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4675 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4677 struct kvm_segment cs
, ss
;
4679 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4680 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4682 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4683 (ss
.selector
& SEGMENT_RPL_MASK
));
4687 * Check if guest state is valid. Returns true if valid, false if
4689 * We assume that registers are always usable
4691 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4693 if (enable_unrestricted_guest
)
4696 /* real mode guest state checks */
4697 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4698 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4700 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4702 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4704 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4706 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4708 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4711 /* protected mode guest state checks */
4712 if (!cs_ss_rpl_check(vcpu
))
4714 if (!code_segment_valid(vcpu
))
4716 if (!stack_segment_valid(vcpu
))
4718 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4720 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4722 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4724 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4726 if (!tr_valid(vcpu
))
4728 if (!ldtr_valid(vcpu
))
4732 * - Add checks on RIP
4733 * - Add checks on RFLAGS
4739 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4741 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4744 static int init_rmode_tss(struct kvm
*kvm
)
4750 idx
= srcu_read_lock(&kvm
->srcu
);
4751 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4752 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4755 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4756 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4757 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4760 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4763 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4767 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4768 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4771 srcu_read_unlock(&kvm
->srcu
, idx
);
4775 static int init_rmode_identity_map(struct kvm
*kvm
)
4778 kvm_pfn_t identity_map_pfn
;
4784 /* Protect kvm->arch.ept_identity_pagetable_done. */
4785 mutex_lock(&kvm
->slots_lock
);
4787 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4790 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4792 r
= alloc_identity_pagetable(kvm
);
4796 idx
= srcu_read_lock(&kvm
->srcu
);
4797 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4800 /* Set up identity-mapping pagetable for EPT in real mode */
4801 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4802 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4803 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4804 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4805 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4809 kvm
->arch
.ept_identity_pagetable_done
= true;
4812 srcu_read_unlock(&kvm
->srcu
, idx
);
4815 mutex_unlock(&kvm
->slots_lock
);
4819 static void seg_setup(int seg
)
4821 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4824 vmcs_write16(sf
->selector
, 0);
4825 vmcs_writel(sf
->base
, 0);
4826 vmcs_write32(sf
->limit
, 0xffff);
4828 if (seg
== VCPU_SREG_CS
)
4829 ar
|= 0x08; /* code segment */
4831 vmcs_write32(sf
->ar_bytes
, ar
);
4834 static int alloc_apic_access_page(struct kvm
*kvm
)
4839 mutex_lock(&kvm
->slots_lock
);
4840 if (kvm
->arch
.apic_access_page_done
)
4842 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4843 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4847 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4848 if (is_error_page(page
)) {
4854 * Do not pin the page in memory, so that memory hot-unplug
4855 * is able to migrate it.
4858 kvm
->arch
.apic_access_page_done
= true;
4860 mutex_unlock(&kvm
->slots_lock
);
4864 static int alloc_identity_pagetable(struct kvm
*kvm
)
4866 /* Called with kvm->slots_lock held. */
4870 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4872 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4873 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4878 static int allocate_vpid(void)
4884 spin_lock(&vmx_vpid_lock
);
4885 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4886 if (vpid
< VMX_NR_VPIDS
)
4887 __set_bit(vpid
, vmx_vpid_bitmap
);
4890 spin_unlock(&vmx_vpid_lock
);
4894 static void free_vpid(int vpid
)
4896 if (!enable_vpid
|| vpid
== 0)
4898 spin_lock(&vmx_vpid_lock
);
4899 __clear_bit(vpid
, vmx_vpid_bitmap
);
4900 spin_unlock(&vmx_vpid_lock
);
4903 #define MSR_TYPE_R 1
4904 #define MSR_TYPE_W 2
4905 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4908 int f
= sizeof(unsigned long);
4910 if (!cpu_has_vmx_msr_bitmap())
4914 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4915 * have the write-low and read-high bitmap offsets the wrong way round.
4916 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4918 if (msr
<= 0x1fff) {
4919 if (type
& MSR_TYPE_R
)
4921 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4923 if (type
& MSR_TYPE_W
)
4925 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4927 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4929 if (type
& MSR_TYPE_R
)
4931 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4933 if (type
& MSR_TYPE_W
)
4935 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4941 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4942 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4944 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4945 unsigned long *msr_bitmap_nested
,
4948 int f
= sizeof(unsigned long);
4950 if (!cpu_has_vmx_msr_bitmap()) {
4956 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4957 * have the write-low and read-high bitmap offsets the wrong way round.
4958 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4960 if (msr
<= 0x1fff) {
4961 if (type
& MSR_TYPE_R
&&
4962 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4964 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4966 if (type
& MSR_TYPE_W
&&
4967 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4969 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4971 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4973 if (type
& MSR_TYPE_R
&&
4974 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4976 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4978 if (type
& MSR_TYPE_W
&&
4979 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4981 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4986 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4989 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4990 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4991 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4992 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4995 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4998 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5000 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5003 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5005 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5010 static bool vmx_get_enable_apicv(void)
5012 return enable_apicv
;
5015 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5017 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5021 * Don't need to mark the APIC access page dirty; it is never
5022 * written to by the CPU during APIC virtualization.
5025 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5026 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5027 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5030 if (nested_cpu_has_posted_intr(vmcs12
)) {
5031 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5032 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5037 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5039 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5044 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5047 vmx
->nested
.pi_pending
= false;
5048 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5051 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5052 if (max_irr
!= 256) {
5053 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5054 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5055 kunmap(vmx
->nested
.virtual_apic_page
);
5057 status
= vmcs_read16(GUEST_INTR_STATUS
);
5058 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5060 status
|= (u8
)max_irr
;
5061 vmcs_write16(GUEST_INTR_STATUS
, status
);
5065 nested_mark_vmcs12_pages_dirty(vcpu
);
5068 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5072 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5074 if (vcpu
->mode
== IN_GUEST_MODE
) {
5075 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5078 * Currently, we don't support urgent interrupt,
5079 * all interrupts are recognized as non-urgent
5080 * interrupt, so we cannot post interrupts when
5083 * If the vcpu is in guest mode, it means it is
5084 * running instead of being scheduled out and
5085 * waiting in the run queue, and that's the only
5086 * case when 'SN' is set currently, warning if
5089 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
5091 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5098 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5101 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5103 if (is_guest_mode(vcpu
) &&
5104 vector
== vmx
->nested
.posted_intr_nv
) {
5105 /* the PIR and ON have been set by L1. */
5106 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5108 * If a posted intr is not recognized by hardware,
5109 * we will accomplish it in the next vmentry.
5111 vmx
->nested
.pi_pending
= true;
5112 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5118 * Send interrupt to vcpu via posted interrupt way.
5119 * 1. If target vcpu is running(non-root mode), send posted interrupt
5120 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5121 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5122 * interrupt from PIR in next vmentry.
5124 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5126 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5129 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5133 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5136 /* If a previous notification has sent the IPI, nothing to do. */
5137 if (pi_test_and_set_on(&vmx
->pi_desc
))
5140 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5141 kvm_vcpu_kick(vcpu
);
5145 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5146 * will not change in the lifetime of the guest.
5147 * Note that host-state that does change is set elsewhere. E.g., host-state
5148 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5150 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5155 unsigned long cr0
, cr3
, cr4
;
5158 WARN_ON(cr0
& X86_CR0_TS
);
5159 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5162 * Save the most likely value for this task's CR3 in the VMCS.
5163 * We can't use __get_current_cr3_fast() because we're not atomic.
5166 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5167 vmx
->host_state
.vmcs_host_cr3
= cr3
;
5169 /* Save the most likely value for this task's CR4 in the VMCS. */
5170 cr4
= cr4_read_shadow();
5171 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5172 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5174 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5175 #ifdef CONFIG_X86_64
5177 * Load null selectors, so we can avoid reloading them in
5178 * __vmx_load_host_state(), in case userspace uses the null selectors
5179 * too (the expected case).
5181 vmcs_write16(HOST_DS_SELECTOR
, 0);
5182 vmcs_write16(HOST_ES_SELECTOR
, 0);
5184 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5185 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5187 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5188 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5190 native_store_idt(&dt
);
5191 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5192 vmx
->host_idt_base
= dt
.address
;
5194 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5196 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5197 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5198 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5199 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5201 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5202 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5203 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5207 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5209 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5211 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5212 if (is_guest_mode(&vmx
->vcpu
))
5213 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5214 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5215 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5218 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5220 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5222 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5223 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5224 /* Enable the preemption timer dynamically */
5225 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5226 return pin_based_exec_ctrl
;
5229 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5231 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5233 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5234 if (cpu_has_secondary_exec_ctrls()) {
5235 if (kvm_vcpu_apicv_active(vcpu
))
5236 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5237 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5238 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5240 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5241 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5242 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5245 if (cpu_has_vmx_msr_bitmap())
5246 vmx_set_msr_bitmap(vcpu
);
5249 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5251 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5253 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5254 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5256 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5257 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5258 #ifdef CONFIG_X86_64
5259 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5260 CPU_BASED_CR8_LOAD_EXITING
;
5264 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5265 CPU_BASED_CR3_LOAD_EXITING
|
5266 CPU_BASED_INVLPG_EXITING
;
5267 return exec_control
;
5270 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5272 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5273 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5274 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5276 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5278 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5279 enable_unrestricted_guest
= 0;
5280 /* Enable INVPCID for non-ept guests may cause performance regression. */
5281 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5283 if (!enable_unrestricted_guest
)
5284 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5286 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5287 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5288 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5289 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5290 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5291 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5293 We can NOT enable shadow_vmcs here because we don't have yet
5296 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5299 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5301 return exec_control
;
5304 static void ept_set_mmio_spte_mask(void)
5307 * EPT Misconfigurations can be generated if the value of bits 2:0
5308 * of an EPT paging-structure entry is 110b (write/execute).
5310 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5311 VMX_EPT_MISCONFIG_WX_VALUE
);
5314 #define VMX_XSS_EXIT_BITMAP 0
5316 * Sets up the vmcs for emulated real mode.
5318 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5320 #ifdef CONFIG_X86_64
5326 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5327 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5329 if (enable_shadow_vmcs
) {
5330 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5331 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5333 if (cpu_has_vmx_msr_bitmap())
5334 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5336 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5339 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5340 vmx
->hv_deadline_tsc
= -1;
5342 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5344 if (cpu_has_secondary_exec_ctrls()) {
5345 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5346 vmx_secondary_exec_control(vmx
));
5349 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5350 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5351 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5352 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5353 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5355 vmcs_write16(GUEST_INTR_STATUS
, 0);
5357 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5358 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5362 vmcs_write32(PLE_GAP
, ple_gap
);
5363 vmx
->ple_window
= ple_window
;
5364 vmx
->ple_window_dirty
= true;
5367 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5368 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5369 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5371 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5372 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5373 vmx_set_constant_host_state(vmx
);
5374 #ifdef CONFIG_X86_64
5375 rdmsrl(MSR_FS_BASE
, a
);
5376 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5377 rdmsrl(MSR_GS_BASE
, a
);
5378 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5380 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5381 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5384 if (cpu_has_vmx_vmfunc())
5385 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5387 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5388 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5389 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5390 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5391 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5393 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5394 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5396 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5397 u32 index
= vmx_msr_index
[i
];
5398 u32 data_low
, data_high
;
5401 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5403 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5405 vmx
->guest_msrs
[j
].index
= i
;
5406 vmx
->guest_msrs
[j
].data
= 0;
5407 vmx
->guest_msrs
[j
].mask
= -1ull;
5412 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5414 /* 22.2.1, 20.8.1 */
5415 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5417 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5418 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5420 set_cr4_guest_host_mask(vmx
);
5422 if (vmx_xsaves_supported())
5423 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5426 ASSERT(vmx
->pml_pg
);
5427 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5428 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5434 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5436 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5437 struct msr_data apic_base_msr
;
5440 vmx
->rmode
.vm86_active
= 0;
5442 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5443 kvm_set_cr8(vcpu
, 0);
5446 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5447 MSR_IA32_APICBASE_ENABLE
;
5448 if (kvm_vcpu_is_reset_bsp(vcpu
))
5449 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5450 apic_base_msr
.host_initiated
= true;
5451 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5454 vmx_segment_cache_clear(vmx
);
5456 seg_setup(VCPU_SREG_CS
);
5457 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5458 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5460 seg_setup(VCPU_SREG_DS
);
5461 seg_setup(VCPU_SREG_ES
);
5462 seg_setup(VCPU_SREG_FS
);
5463 seg_setup(VCPU_SREG_GS
);
5464 seg_setup(VCPU_SREG_SS
);
5466 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5467 vmcs_writel(GUEST_TR_BASE
, 0);
5468 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5469 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5471 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5472 vmcs_writel(GUEST_LDTR_BASE
, 0);
5473 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5474 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5477 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5478 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5479 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5480 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5483 vmcs_writel(GUEST_RFLAGS
, 0x02);
5484 kvm_rip_write(vcpu
, 0xfff0);
5486 vmcs_writel(GUEST_GDTR_BASE
, 0);
5487 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5489 vmcs_writel(GUEST_IDTR_BASE
, 0);
5490 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5492 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5493 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5494 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5498 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5500 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5501 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5502 if (cpu_need_tpr_shadow(vcpu
))
5503 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5504 __pa(vcpu
->arch
.apic
->regs
));
5505 vmcs_write32(TPR_THRESHOLD
, 0);
5508 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5510 if (kvm_vcpu_apicv_active(vcpu
))
5511 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5514 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5516 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5517 vmx
->vcpu
.arch
.cr0
= cr0
;
5518 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5519 vmx_set_cr4(vcpu
, 0);
5520 vmx_set_efer(vcpu
, 0);
5522 update_exception_bitmap(vcpu
);
5524 vpid_sync_context(vmx
->vpid
);
5528 * In nested virtualization, check if L1 asked to exit on external interrupts.
5529 * For most existing hypervisors, this will always return true.
5531 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5533 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5534 PIN_BASED_EXT_INTR_MASK
;
5538 * In nested virtualization, check if L1 has set
5539 * VM_EXIT_ACK_INTR_ON_EXIT
5541 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5543 return get_vmcs12(vcpu
)->vm_exit_controls
&
5544 VM_EXIT_ACK_INTR_ON_EXIT
;
5547 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5549 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5550 PIN_BASED_NMI_EXITING
;
5553 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5555 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5556 CPU_BASED_VIRTUAL_INTR_PENDING
);
5559 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5561 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5562 enable_irq_window(vcpu
);
5566 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5567 CPU_BASED_VIRTUAL_NMI_PENDING
);
5570 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5572 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5574 int irq
= vcpu
->arch
.interrupt
.nr
;
5576 trace_kvm_inj_virq(irq
);
5578 ++vcpu
->stat
.irq_injections
;
5579 if (vmx
->rmode
.vm86_active
) {
5581 if (vcpu
->arch
.interrupt
.soft
)
5582 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5583 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5584 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5587 intr
= irq
| INTR_INFO_VALID_MASK
;
5588 if (vcpu
->arch
.interrupt
.soft
) {
5589 intr
|= INTR_TYPE_SOFT_INTR
;
5590 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5591 vmx
->vcpu
.arch
.event_exit_inst_len
);
5593 intr
|= INTR_TYPE_EXT_INTR
;
5594 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5597 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5601 ++vcpu
->stat
.nmi_injections
;
5602 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5604 if (vmx
->rmode
.vm86_active
) {
5605 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5606 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5610 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5611 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5614 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5616 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5619 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5621 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5622 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5626 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5628 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5630 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5632 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5633 GUEST_INTR_STATE_NMI
);
5635 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5636 GUEST_INTR_STATE_NMI
);
5639 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5641 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5644 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5645 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5646 | GUEST_INTR_STATE_NMI
));
5649 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5651 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5652 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5653 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5654 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5657 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5661 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5665 kvm
->arch
.tss_addr
= addr
;
5666 return init_rmode_tss(kvm
);
5669 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5674 * Update instruction length as we may reinject the exception
5675 * from user space while in guest debugging mode.
5677 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5678 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5679 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5683 if (vcpu
->guest_debug
&
5684 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5701 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5702 int vec
, u32 err_code
)
5705 * Instruction with address size override prefix opcode 0x67
5706 * Cause the #SS fault with 0 error code in VM86 mode.
5708 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5709 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5710 if (vcpu
->arch
.halt_request
) {
5711 vcpu
->arch
.halt_request
= 0;
5712 return kvm_vcpu_halt(vcpu
);
5720 * Forward all other exceptions that are valid in real mode.
5721 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5722 * the required debugging infrastructure rework.
5724 kvm_queue_exception(vcpu
, vec
);
5729 * Trigger machine check on the host. We assume all the MSRs are already set up
5730 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5731 * We pass a fake environment to the machine check handler because we want
5732 * the guest to be always treated like user space, no matter what context
5733 * it used internally.
5735 static void kvm_machine_check(void)
5737 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5738 struct pt_regs regs
= {
5739 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5740 .flags
= X86_EFLAGS_IF
,
5743 do_machine_check(®s
, 0);
5747 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5749 /* already handled by vcpu_run */
5753 static int handle_exception(struct kvm_vcpu
*vcpu
)
5755 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5756 struct kvm_run
*kvm_run
= vcpu
->run
;
5757 u32 intr_info
, ex_no
, error_code
;
5758 unsigned long cr2
, rip
, dr6
;
5760 enum emulation_result er
;
5762 vect_info
= vmx
->idt_vectoring_info
;
5763 intr_info
= vmx
->exit_intr_info
;
5765 if (is_machine_check(intr_info
))
5766 return handle_machine_check(vcpu
);
5768 if (is_nmi(intr_info
))
5769 return 1; /* already handled by vmx_vcpu_run() */
5771 if (is_invalid_opcode(intr_info
)) {
5772 if (is_guest_mode(vcpu
)) {
5773 kvm_queue_exception(vcpu
, UD_VECTOR
);
5776 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5777 if (er
!= EMULATE_DONE
)
5778 kvm_queue_exception(vcpu
, UD_VECTOR
);
5783 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5784 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5787 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5788 * MMIO, it is better to report an internal error.
5789 * See the comments in vmx_handle_exit.
5791 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5792 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5793 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5794 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5795 vcpu
->run
->internal
.ndata
= 3;
5796 vcpu
->run
->internal
.data
[0] = vect_info
;
5797 vcpu
->run
->internal
.data
[1] = intr_info
;
5798 vcpu
->run
->internal
.data
[2] = error_code
;
5802 if (is_page_fault(intr_info
)) {
5803 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5804 /* EPT won't cause page fault directly */
5805 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5806 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5810 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5812 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5813 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5817 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5820 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5821 if (!(vcpu
->guest_debug
&
5822 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5823 vcpu
->arch
.dr6
&= ~15;
5824 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5825 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5826 skip_emulated_instruction(vcpu
);
5828 kvm_queue_exception(vcpu
, DB_VECTOR
);
5831 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5832 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5836 * Update instruction length as we may reinject #BP from
5837 * user space while in guest debugging mode. Reading it for
5838 * #DB as well causes no harm, it is not used in that case.
5840 vmx
->vcpu
.arch
.event_exit_inst_len
=
5841 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5842 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5843 rip
= kvm_rip_read(vcpu
);
5844 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5845 kvm_run
->debug
.arch
.exception
= ex_no
;
5848 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5849 kvm_run
->ex
.exception
= ex_no
;
5850 kvm_run
->ex
.error_code
= error_code
;
5856 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5858 ++vcpu
->stat
.irq_exits
;
5862 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5864 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5865 vcpu
->mmio_needed
= 0;
5869 static int handle_io(struct kvm_vcpu
*vcpu
)
5871 unsigned long exit_qualification
;
5872 int size
, in
, string
, ret
;
5875 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5876 string
= (exit_qualification
& 16) != 0;
5877 in
= (exit_qualification
& 8) != 0;
5879 ++vcpu
->stat
.io_exits
;
5882 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5884 port
= exit_qualification
>> 16;
5885 size
= (exit_qualification
& 7) + 1;
5887 ret
= kvm_skip_emulated_instruction(vcpu
);
5890 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5891 * KVM_EXIT_DEBUG here.
5893 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5897 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5900 * Patch in the VMCALL instruction:
5902 hypercall
[0] = 0x0f;
5903 hypercall
[1] = 0x01;
5904 hypercall
[2] = 0xc1;
5907 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5908 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5910 if (is_guest_mode(vcpu
)) {
5911 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5912 unsigned long orig_val
= val
;
5915 * We get here when L2 changed cr0 in a way that did not change
5916 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5917 * but did change L0 shadowed bits. So we first calculate the
5918 * effective cr0 value that L1 would like to write into the
5919 * hardware. It consists of the L2-owned bits from the new
5920 * value combined with the L1-owned bits from L1's guest_cr0.
5922 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5923 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5925 if (!nested_guest_cr0_valid(vcpu
, val
))
5928 if (kvm_set_cr0(vcpu
, val
))
5930 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5933 if (to_vmx(vcpu
)->nested
.vmxon
&&
5934 !nested_host_cr0_valid(vcpu
, val
))
5937 return kvm_set_cr0(vcpu
, val
);
5941 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5943 if (is_guest_mode(vcpu
)) {
5944 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5945 unsigned long orig_val
= val
;
5947 /* analogously to handle_set_cr0 */
5948 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5949 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5950 if (kvm_set_cr4(vcpu
, val
))
5952 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5955 return kvm_set_cr4(vcpu
, val
);
5958 static int handle_cr(struct kvm_vcpu
*vcpu
)
5960 unsigned long exit_qualification
, val
;
5966 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5967 cr
= exit_qualification
& 15;
5968 reg
= (exit_qualification
>> 8) & 15;
5969 switch ((exit_qualification
>> 4) & 3) {
5970 case 0: /* mov to cr */
5971 val
= kvm_register_readl(vcpu
, reg
);
5972 trace_kvm_cr_write(cr
, val
);
5975 err
= handle_set_cr0(vcpu
, val
);
5976 return kvm_complete_insn_gp(vcpu
, err
);
5978 err
= kvm_set_cr3(vcpu
, val
);
5979 return kvm_complete_insn_gp(vcpu
, err
);
5981 err
= handle_set_cr4(vcpu
, val
);
5982 return kvm_complete_insn_gp(vcpu
, err
);
5984 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5986 err
= kvm_set_cr8(vcpu
, cr8
);
5987 ret
= kvm_complete_insn_gp(vcpu
, err
);
5988 if (lapic_in_kernel(vcpu
))
5990 if (cr8_prev
<= cr8
)
5993 * TODO: we might be squashing a
5994 * KVM_GUESTDBG_SINGLESTEP-triggered
5995 * KVM_EXIT_DEBUG here.
5997 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6003 WARN_ONCE(1, "Guest should always own CR0.TS");
6004 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6005 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6006 return kvm_skip_emulated_instruction(vcpu
);
6007 case 1: /*mov from cr*/
6010 val
= kvm_read_cr3(vcpu
);
6011 kvm_register_write(vcpu
, reg
, val
);
6012 trace_kvm_cr_read(cr
, val
);
6013 return kvm_skip_emulated_instruction(vcpu
);
6015 val
= kvm_get_cr8(vcpu
);
6016 kvm_register_write(vcpu
, reg
, val
);
6017 trace_kvm_cr_read(cr
, val
);
6018 return kvm_skip_emulated_instruction(vcpu
);
6022 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6023 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6024 kvm_lmsw(vcpu
, val
);
6026 return kvm_skip_emulated_instruction(vcpu
);
6030 vcpu
->run
->exit_reason
= 0;
6031 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6032 (int)(exit_qualification
>> 4) & 3, cr
);
6036 static int handle_dr(struct kvm_vcpu
*vcpu
)
6038 unsigned long exit_qualification
;
6041 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6042 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6044 /* First, if DR does not exist, trigger UD */
6045 if (!kvm_require_dr(vcpu
, dr
))
6048 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6049 if (!kvm_require_cpl(vcpu
, 0))
6051 dr7
= vmcs_readl(GUEST_DR7
);
6054 * As the vm-exit takes precedence over the debug trap, we
6055 * need to emulate the latter, either for the host or the
6056 * guest debugging itself.
6058 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6059 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6060 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6061 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6062 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6063 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6066 vcpu
->arch
.dr6
&= ~15;
6067 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6068 kvm_queue_exception(vcpu
, DB_VECTOR
);
6073 if (vcpu
->guest_debug
== 0) {
6074 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6075 CPU_BASED_MOV_DR_EXITING
);
6078 * No more DR vmexits; force a reload of the debug registers
6079 * and reenter on this instruction. The next vmexit will
6080 * retrieve the full state of the debug registers.
6082 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6086 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6087 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6090 if (kvm_get_dr(vcpu
, dr
, &val
))
6092 kvm_register_write(vcpu
, reg
, val
);
6094 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6097 return kvm_skip_emulated_instruction(vcpu
);
6100 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6102 return vcpu
->arch
.dr6
;
6105 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6109 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6111 get_debugreg(vcpu
->arch
.db
[0], 0);
6112 get_debugreg(vcpu
->arch
.db
[1], 1);
6113 get_debugreg(vcpu
->arch
.db
[2], 2);
6114 get_debugreg(vcpu
->arch
.db
[3], 3);
6115 get_debugreg(vcpu
->arch
.dr6
, 6);
6116 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6118 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6119 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6122 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6124 vmcs_writel(GUEST_DR7
, val
);
6127 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6129 return kvm_emulate_cpuid(vcpu
);
6132 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6134 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6135 struct msr_data msr_info
;
6137 msr_info
.index
= ecx
;
6138 msr_info
.host_initiated
= false;
6139 if (vmx_get_msr(vcpu
, &msr_info
)) {
6140 trace_kvm_msr_read_ex(ecx
);
6141 kvm_inject_gp(vcpu
, 0);
6145 trace_kvm_msr_read(ecx
, msr_info
.data
);
6147 /* FIXME: handling of bits 32:63 of rax, rdx */
6148 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6149 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6150 return kvm_skip_emulated_instruction(vcpu
);
6153 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6155 struct msr_data msr
;
6156 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6157 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6158 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6162 msr
.host_initiated
= false;
6163 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6164 trace_kvm_msr_write_ex(ecx
, data
);
6165 kvm_inject_gp(vcpu
, 0);
6169 trace_kvm_msr_write(ecx
, data
);
6170 return kvm_skip_emulated_instruction(vcpu
);
6173 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6175 kvm_apic_update_ppr(vcpu
);
6179 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6181 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6182 CPU_BASED_VIRTUAL_INTR_PENDING
);
6184 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6186 ++vcpu
->stat
.irq_window_exits
;
6190 static int handle_halt(struct kvm_vcpu
*vcpu
)
6192 return kvm_emulate_halt(vcpu
);
6195 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6197 return kvm_emulate_hypercall(vcpu
);
6200 static int handle_invd(struct kvm_vcpu
*vcpu
)
6202 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6205 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6207 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6209 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6210 return kvm_skip_emulated_instruction(vcpu
);
6213 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6217 err
= kvm_rdpmc(vcpu
);
6218 return kvm_complete_insn_gp(vcpu
, err
);
6221 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6223 return kvm_emulate_wbinvd(vcpu
);
6226 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6228 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6229 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6231 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6232 return kvm_skip_emulated_instruction(vcpu
);
6236 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6238 kvm_skip_emulated_instruction(vcpu
);
6239 WARN(1, "this should never happen\n");
6243 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6245 kvm_skip_emulated_instruction(vcpu
);
6246 WARN(1, "this should never happen\n");
6250 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6252 if (likely(fasteoi
)) {
6253 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6254 int access_type
, offset
;
6256 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6257 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6259 * Sane guest uses MOV to write EOI, with written value
6260 * not cared. So make a short-circuit here by avoiding
6261 * heavy instruction emulation.
6263 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6264 (offset
== APIC_EOI
)) {
6265 kvm_lapic_set_eoi(vcpu
);
6266 return kvm_skip_emulated_instruction(vcpu
);
6269 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6272 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6274 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6275 int vector
= exit_qualification
& 0xff;
6277 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6278 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6282 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6284 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6285 u32 offset
= exit_qualification
& 0xfff;
6287 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6288 kvm_apic_write_nodecode(vcpu
, offset
);
6292 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6294 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6295 unsigned long exit_qualification
;
6296 bool has_error_code
= false;
6299 int reason
, type
, idt_v
, idt_index
;
6301 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6302 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6303 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6305 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6307 reason
= (u32
)exit_qualification
>> 30;
6308 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6310 case INTR_TYPE_NMI_INTR
:
6311 vcpu
->arch
.nmi_injected
= false;
6312 vmx_set_nmi_mask(vcpu
, true);
6314 case INTR_TYPE_EXT_INTR
:
6315 case INTR_TYPE_SOFT_INTR
:
6316 kvm_clear_interrupt_queue(vcpu
);
6318 case INTR_TYPE_HARD_EXCEPTION
:
6319 if (vmx
->idt_vectoring_info
&
6320 VECTORING_INFO_DELIVER_CODE_MASK
) {
6321 has_error_code
= true;
6323 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6326 case INTR_TYPE_SOFT_EXCEPTION
:
6327 kvm_clear_exception_queue(vcpu
);
6333 tss_selector
= exit_qualification
;
6335 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6336 type
!= INTR_TYPE_EXT_INTR
&&
6337 type
!= INTR_TYPE_NMI_INTR
))
6338 skip_emulated_instruction(vcpu
);
6340 if (kvm_task_switch(vcpu
, tss_selector
,
6341 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6342 has_error_code
, error_code
) == EMULATE_FAIL
) {
6343 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6344 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6345 vcpu
->run
->internal
.ndata
= 0;
6350 * TODO: What about debug traps on tss switch?
6351 * Are we supposed to inject them and update dr6?
6357 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6359 unsigned long exit_qualification
;
6363 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6366 * EPT violation happened while executing iret from NMI,
6367 * "blocked by NMI" bit has to be set before next VM entry.
6368 * There are errata that may cause this bit to not be set:
6371 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6372 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6373 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6375 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6376 trace_kvm_page_fault(gpa
, exit_qualification
);
6378 /* Is it a read fault? */
6379 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6380 ? PFERR_USER_MASK
: 0;
6381 /* Is it a write fault? */
6382 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6383 ? PFERR_WRITE_MASK
: 0;
6384 /* Is it a fetch fault? */
6385 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6386 ? PFERR_FETCH_MASK
: 0;
6387 /* ept page table entry is present? */
6388 error_code
|= (exit_qualification
&
6389 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6390 EPT_VIOLATION_EXECUTABLE
))
6391 ? PFERR_PRESENT_MASK
: 0;
6393 error_code
|= (exit_qualification
& 0x100) != 0 ?
6394 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6396 vcpu
->arch
.gpa_available
= true;
6397 vcpu
->arch
.exit_qualification
= exit_qualification
;
6399 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6402 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6407 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6408 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6409 trace_kvm_fast_mmio(gpa
);
6410 return kvm_skip_emulated_instruction(vcpu
);
6413 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6414 vcpu
->arch
.gpa_available
= true;
6415 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6416 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6419 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6420 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6422 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6425 /* It is the real ept misconfig */
6428 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6429 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6434 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6436 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6437 CPU_BASED_VIRTUAL_NMI_PENDING
);
6438 ++vcpu
->stat
.nmi_window_exits
;
6439 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6444 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6446 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6447 enum emulation_result err
= EMULATE_DONE
;
6450 bool intr_window_requested
;
6451 unsigned count
= 130;
6453 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6454 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6456 while (vmx
->emulation_required
&& count
-- != 0) {
6457 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6458 return handle_interrupt_window(&vmx
->vcpu
);
6460 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6463 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6465 if (err
== EMULATE_USER_EXIT
) {
6466 ++vcpu
->stat
.mmio_exits
;
6471 if (err
!= EMULATE_DONE
) {
6472 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6473 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6474 vcpu
->run
->internal
.ndata
= 0;
6478 if (vcpu
->arch
.halt_request
) {
6479 vcpu
->arch
.halt_request
= 0;
6480 ret
= kvm_vcpu_halt(vcpu
);
6484 if (signal_pending(current
))
6494 static int __grow_ple_window(int val
)
6496 if (ple_window_grow
< 1)
6499 val
= min(val
, ple_window_actual_max
);
6501 if (ple_window_grow
< ple_window
)
6502 val
*= ple_window_grow
;
6504 val
+= ple_window_grow
;
6509 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6514 if (modifier
< ple_window
)
6519 return max(val
, minimum
);
6522 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6524 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6525 int old
= vmx
->ple_window
;
6527 vmx
->ple_window
= __grow_ple_window(old
);
6529 if (vmx
->ple_window
!= old
)
6530 vmx
->ple_window_dirty
= true;
6532 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6535 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6537 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6538 int old
= vmx
->ple_window
;
6540 vmx
->ple_window
= __shrink_ple_window(old
,
6541 ple_window_shrink
, ple_window
);
6543 if (vmx
->ple_window
!= old
)
6544 vmx
->ple_window_dirty
= true;
6546 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6550 * ple_window_actual_max is computed to be one grow_ple_window() below
6551 * ple_window_max. (See __grow_ple_window for the reason.)
6552 * This prevents overflows, because ple_window_max is int.
6553 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6555 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6557 static void update_ple_window_actual_max(void)
6559 ple_window_actual_max
=
6560 __shrink_ple_window(max(ple_window_max
, ple_window
),
6561 ple_window_grow
, INT_MIN
);
6565 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6567 static void wakeup_handler(void)
6569 struct kvm_vcpu
*vcpu
;
6570 int cpu
= smp_processor_id();
6572 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6573 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6574 blocked_vcpu_list
) {
6575 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6577 if (pi_test_on(pi_desc
) == 1)
6578 kvm_vcpu_kick(vcpu
);
6580 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6583 void vmx_enable_tdp(void)
6585 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6586 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6587 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6588 0ull, VMX_EPT_EXECUTABLE_MASK
,
6589 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6592 ept_set_mmio_spte_mask();
6596 static __init
int hardware_setup(void)
6598 int r
= -ENOMEM
, i
, msr
;
6600 rdmsrl_safe(MSR_EFER
, &host_efer
);
6602 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6603 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6605 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6606 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6611 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6612 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6613 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6616 * Allow direct access to the PC debug port (it is often used for I/O
6617 * delays, but the vmexits simply slow things down).
6619 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6620 clear_bit(0x80, vmx_io_bitmap_a
);
6622 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6624 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6625 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6627 if (setup_vmcs_config(&vmcs_config
) < 0) {
6632 if (boot_cpu_has(X86_FEATURE_NX
))
6633 kvm_enable_efer_bits(EFER_NX
);
6635 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6636 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6639 if (!cpu_has_vmx_shadow_vmcs())
6640 enable_shadow_vmcs
= 0;
6641 if (enable_shadow_vmcs
)
6642 init_vmcs_shadow_fields();
6644 if (!cpu_has_vmx_ept() ||
6645 !cpu_has_vmx_ept_4levels()) {
6647 enable_unrestricted_guest
= 0;
6648 enable_ept_ad_bits
= 0;
6651 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6652 enable_ept_ad_bits
= 0;
6654 if (!cpu_has_vmx_unrestricted_guest())
6655 enable_unrestricted_guest
= 0;
6657 if (!cpu_has_vmx_flexpriority())
6658 flexpriority_enabled
= 0;
6661 * set_apic_access_page_addr() is used to reload apic access
6662 * page upon invalidation. No need to do anything if not
6663 * using the APIC_ACCESS_ADDR VMCS field.
6665 if (!flexpriority_enabled
)
6666 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6668 if (!cpu_has_vmx_tpr_shadow())
6669 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6671 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6672 kvm_disable_largepages();
6674 if (!cpu_has_vmx_ple())
6677 if (!cpu_has_vmx_apicv()) {
6679 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6682 if (cpu_has_vmx_tsc_scaling()) {
6683 kvm_has_tsc_control
= true;
6684 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6685 kvm_tsc_scaling_ratio_frac_bits
= 48;
6688 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6689 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6690 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6691 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6692 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6693 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6695 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6696 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6697 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6698 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6699 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6700 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6701 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6702 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6704 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6706 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6707 if (msr
== 0x839 /* TMCCT */)
6709 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6713 * TPR reads and writes can be virtualized even if virtual interrupt
6714 * delivery is not in use.
6716 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6717 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6720 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6722 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6729 update_ple_window_actual_max();
6732 * Only enable PML when hardware supports PML feature, and both EPT
6733 * and EPT A/D bit features are enabled -- PML depends on them to work.
6735 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6739 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6740 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6741 kvm_x86_ops
->flush_log_dirty
= NULL
;
6742 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6745 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6748 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6749 cpu_preemption_timer_multi
=
6750 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6752 kvm_x86_ops
->set_hv_timer
= NULL
;
6753 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6756 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6758 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6760 return alloc_kvm_area();
6763 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6764 free_page((unsigned long)vmx_bitmap
[i
]);
6769 static __exit
void hardware_unsetup(void)
6773 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6774 free_page((unsigned long)vmx_bitmap
[i
]);
6780 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6781 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6783 static int handle_pause(struct kvm_vcpu
*vcpu
)
6786 grow_ple_window(vcpu
);
6789 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6790 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6791 * never set PAUSE_EXITING and just set PLE if supported,
6792 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6794 kvm_vcpu_on_spin(vcpu
, true);
6795 return kvm_skip_emulated_instruction(vcpu
);
6798 static int handle_nop(struct kvm_vcpu
*vcpu
)
6800 return kvm_skip_emulated_instruction(vcpu
);
6803 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6805 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6806 return handle_nop(vcpu
);
6809 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6814 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6816 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6817 return handle_nop(vcpu
);
6821 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6822 * We could reuse a single VMCS for all the L2 guests, but we also want the
6823 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6824 * allows keeping them loaded on the processor, and in the future will allow
6825 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6826 * every entry if they never change.
6827 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6828 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6830 * The following functions allocate and free a vmcs02 in this pool.
6833 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6834 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6836 struct vmcs02_list
*item
;
6837 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6838 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6839 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6840 return &item
->vmcs02
;
6843 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6844 /* Recycle the least recently used VMCS. */
6845 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6846 struct vmcs02_list
, list
);
6847 item
->vmptr
= vmx
->nested
.current_vmptr
;
6848 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6849 return &item
->vmcs02
;
6852 /* Create a new VMCS */
6853 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6856 item
->vmcs02
.vmcs
= alloc_vmcs();
6857 item
->vmcs02
.shadow_vmcs
= NULL
;
6858 if (!item
->vmcs02
.vmcs
) {
6862 loaded_vmcs_init(&item
->vmcs02
);
6863 item
->vmptr
= vmx
->nested
.current_vmptr
;
6864 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6865 vmx
->nested
.vmcs02_num
++;
6866 return &item
->vmcs02
;
6869 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6870 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6872 struct vmcs02_list
*item
;
6873 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6874 if (item
->vmptr
== vmptr
) {
6875 free_loaded_vmcs(&item
->vmcs02
);
6876 list_del(&item
->list
);
6878 vmx
->nested
.vmcs02_num
--;
6884 * Free all VMCSs saved for this vcpu, except the one pointed by
6885 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6886 * must be &vmx->vmcs01.
6888 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6890 struct vmcs02_list
*item
, *n
;
6892 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6893 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6895 * Something will leak if the above WARN triggers. Better than
6898 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6901 free_loaded_vmcs(&item
->vmcs02
);
6902 list_del(&item
->list
);
6904 vmx
->nested
.vmcs02_num
--;
6909 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6910 * set the success or error code of an emulated VMX instruction, as specified
6911 * by Vol 2B, VMX Instruction Reference, "Conventions".
6913 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6915 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6916 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6917 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6920 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6922 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6923 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6924 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6928 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6929 u32 vm_instruction_error
)
6931 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6933 * failValid writes the error number to the current VMCS, which
6934 * can't be done there isn't a current VMCS.
6936 nested_vmx_failInvalid(vcpu
);
6939 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6940 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6941 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6943 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6945 * We don't need to force a shadow sync because
6946 * VM_INSTRUCTION_ERROR is not shadowed
6950 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6952 /* TODO: not to reset guest simply here. */
6953 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6954 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6957 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6959 struct vcpu_vmx
*vmx
=
6960 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6962 vmx
->nested
.preemption_timer_expired
= true;
6963 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6964 kvm_vcpu_kick(&vmx
->vcpu
);
6966 return HRTIMER_NORESTART
;
6970 * Decode the memory-address operand of a vmx instruction, as recorded on an
6971 * exit caused by such an instruction (run by a guest hypervisor).
6972 * On success, returns 0. When the operand is invalid, returns 1 and throws
6975 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6976 unsigned long exit_qualification
,
6977 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6981 struct kvm_segment s
;
6984 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6985 * Execution", on an exit, vmx_instruction_info holds most of the
6986 * addressing components of the operand. Only the displacement part
6987 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6988 * For how an actual address is calculated from all these components,
6989 * refer to Vol. 1, "Operand Addressing".
6991 int scaling
= vmx_instruction_info
& 3;
6992 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6993 bool is_reg
= vmx_instruction_info
& (1u << 10);
6994 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6995 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6996 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6997 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6998 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7001 kvm_queue_exception(vcpu
, UD_VECTOR
);
7005 /* Addr = segment_base + offset */
7006 /* offset = base + [index * scale] + displacement */
7007 off
= exit_qualification
; /* holds the displacement */
7009 off
+= kvm_register_read(vcpu
, base_reg
);
7011 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7012 vmx_get_segment(vcpu
, &s
, seg_reg
);
7013 *ret
= s
.base
+ off
;
7015 if (addr_size
== 1) /* 32 bit */
7018 /* Checks for #GP/#SS exceptions. */
7020 if (is_long_mode(vcpu
)) {
7021 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7022 * non-canonical form. This is the only check on the memory
7023 * destination for long mode!
7025 exn
= is_noncanonical_address(*ret
);
7026 } else if (is_protmode(vcpu
)) {
7027 /* Protected mode: apply checks for segment validity in the
7029 * - segment type check (#GP(0) may be thrown)
7030 * - usability check (#GP(0)/#SS(0))
7031 * - limit check (#GP(0)/#SS(0))
7034 /* #GP(0) if the destination operand is located in a
7035 * read-only data segment or any code segment.
7037 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7039 /* #GP(0) if the source operand is located in an
7040 * execute-only code segment
7042 exn
= ((s
.type
& 0xa) == 8);
7044 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7047 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7049 exn
= (s
.unusable
!= 0);
7050 /* Protected mode: #GP(0)/#SS(0) if the memory
7051 * operand is outside the segment limit.
7053 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7056 kvm_queue_exception_e(vcpu
,
7057 seg_reg
== VCPU_SREG_SS
?
7058 SS_VECTOR
: GP_VECTOR
,
7066 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7069 struct x86_exception e
;
7071 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7072 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7075 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7076 sizeof(*vmpointer
), &e
)) {
7077 kvm_inject_page_fault(vcpu
, &e
);
7084 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7086 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7087 struct vmcs
*shadow_vmcs
;
7089 if (cpu_has_vmx_msr_bitmap()) {
7090 vmx
->nested
.msr_bitmap
=
7091 (unsigned long *)__get_free_page(GFP_KERNEL
);
7092 if (!vmx
->nested
.msr_bitmap
)
7093 goto out_msr_bitmap
;
7096 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7097 if (!vmx
->nested
.cached_vmcs12
)
7098 goto out_cached_vmcs12
;
7100 if (enable_shadow_vmcs
) {
7101 shadow_vmcs
= alloc_vmcs();
7103 goto out_shadow_vmcs
;
7104 /* mark vmcs as shadow */
7105 shadow_vmcs
->revision_id
|= (1u << 31);
7106 /* init shadow vmcs */
7107 vmcs_clear(shadow_vmcs
);
7108 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7111 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7112 vmx
->nested
.vmcs02_num
= 0;
7114 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7115 HRTIMER_MODE_REL_PINNED
);
7116 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7118 vmx
->nested
.vmxon
= true;
7122 kfree(vmx
->nested
.cached_vmcs12
);
7125 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7132 * Emulate the VMXON instruction.
7133 * Currently, we just remember that VMX is active, and do not save or even
7134 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7135 * do not currently need to store anything in that guest-allocated memory
7136 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7137 * argument is different from the VMXON pointer (which the spec says they do).
7139 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7144 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7145 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7146 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7149 * The Intel VMX Instruction Reference lists a bunch of bits that are
7150 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7151 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7152 * Otherwise, we should fail with #UD. But most faulting conditions
7153 * have already been checked by hardware, prior to the VM-exit for
7154 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7155 * that bit set to 1 in non-root mode.
7157 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7158 kvm_queue_exception(vcpu
, UD_VECTOR
);
7162 if (vmx
->nested
.vmxon
) {
7163 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7164 return kvm_skip_emulated_instruction(vcpu
);
7167 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7168 != VMXON_NEEDED_FEATURES
) {
7169 kvm_inject_gp(vcpu
, 0);
7173 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7178 * The first 4 bytes of VMXON region contain the supported
7179 * VMCS revision identifier
7181 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7182 * which replaces physical address width with 32
7184 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7185 nested_vmx_failInvalid(vcpu
);
7186 return kvm_skip_emulated_instruction(vcpu
);
7189 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7190 if (is_error_page(page
)) {
7191 nested_vmx_failInvalid(vcpu
);
7192 return kvm_skip_emulated_instruction(vcpu
);
7194 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7196 kvm_release_page_clean(page
);
7197 nested_vmx_failInvalid(vcpu
);
7198 return kvm_skip_emulated_instruction(vcpu
);
7201 kvm_release_page_clean(page
);
7203 vmx
->nested
.vmxon_ptr
= vmptr
;
7204 ret
= enter_vmx_operation(vcpu
);
7208 nested_vmx_succeed(vcpu
);
7209 return kvm_skip_emulated_instruction(vcpu
);
7213 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7214 * for running VMX instructions (except VMXON, whose prerequisites are
7215 * slightly different). It also specifies what exception to inject otherwise.
7216 * Note that many of these exceptions have priority over VM exits, so they
7217 * don't have to be checked again here.
7219 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7221 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7222 kvm_queue_exception(vcpu
, UD_VECTOR
);
7228 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7230 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7231 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7234 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7236 if (vmx
->nested
.current_vmptr
== -1ull)
7239 if (enable_shadow_vmcs
) {
7240 /* copy to memory all shadowed fields in case
7241 they were modified */
7242 copy_shadow_to_vmcs12(vmx
);
7243 vmx
->nested
.sync_shadow_vmcs
= false;
7244 vmx_disable_shadow_vmcs(vmx
);
7246 vmx
->nested
.posted_intr_nv
= -1;
7248 /* Flush VMCS12 to guest memory */
7249 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7250 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7251 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7253 vmx
->nested
.current_vmptr
= -1ull;
7257 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7258 * just stops using VMX.
7260 static void free_nested(struct vcpu_vmx
*vmx
)
7262 if (!vmx
->nested
.vmxon
)
7265 vmx
->nested
.vmxon
= false;
7266 free_vpid(vmx
->nested
.vpid02
);
7267 vmx
->nested
.posted_intr_nv
= -1;
7268 vmx
->nested
.current_vmptr
= -1ull;
7269 if (vmx
->nested
.msr_bitmap
) {
7270 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7271 vmx
->nested
.msr_bitmap
= NULL
;
7273 if (enable_shadow_vmcs
) {
7274 vmx_disable_shadow_vmcs(vmx
);
7275 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7276 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7277 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7279 kfree(vmx
->nested
.cached_vmcs12
);
7280 /* Unpin physical memory we referred to in current vmcs02 */
7281 if (vmx
->nested
.apic_access_page
) {
7282 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7283 vmx
->nested
.apic_access_page
= NULL
;
7285 if (vmx
->nested
.virtual_apic_page
) {
7286 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7287 vmx
->nested
.virtual_apic_page
= NULL
;
7289 if (vmx
->nested
.pi_desc_page
) {
7290 kunmap(vmx
->nested
.pi_desc_page
);
7291 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7292 vmx
->nested
.pi_desc_page
= NULL
;
7293 vmx
->nested
.pi_desc
= NULL
;
7296 nested_free_all_saved_vmcss(vmx
);
7299 /* Emulate the VMXOFF instruction */
7300 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7302 if (!nested_vmx_check_permission(vcpu
))
7304 free_nested(to_vmx(vcpu
));
7305 nested_vmx_succeed(vcpu
);
7306 return kvm_skip_emulated_instruction(vcpu
);
7309 /* Emulate the VMCLEAR instruction */
7310 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7312 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7316 if (!nested_vmx_check_permission(vcpu
))
7319 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7322 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7323 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7324 return kvm_skip_emulated_instruction(vcpu
);
7327 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7328 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7329 return kvm_skip_emulated_instruction(vcpu
);
7332 if (vmptr
== vmx
->nested
.current_vmptr
)
7333 nested_release_vmcs12(vmx
);
7335 kvm_vcpu_write_guest(vcpu
,
7336 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7337 &zero
, sizeof(zero
));
7339 nested_free_vmcs02(vmx
, vmptr
);
7341 nested_vmx_succeed(vcpu
);
7342 return kvm_skip_emulated_instruction(vcpu
);
7345 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7347 /* Emulate the VMLAUNCH instruction */
7348 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7350 return nested_vmx_run(vcpu
, true);
7353 /* Emulate the VMRESUME instruction */
7354 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7357 return nested_vmx_run(vcpu
, false);
7361 * Read a vmcs12 field. Since these can have varying lengths and we return
7362 * one type, we chose the biggest type (u64) and zero-extend the return value
7363 * to that size. Note that the caller, handle_vmread, might need to use only
7364 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7365 * 64-bit fields are to be returned).
7367 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7368 unsigned long field
, u64
*ret
)
7370 short offset
= vmcs_field_to_offset(field
);
7376 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7378 switch (vmcs_field_type(field
)) {
7379 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7380 *ret
= *((natural_width
*)p
);
7382 case VMCS_FIELD_TYPE_U16
:
7385 case VMCS_FIELD_TYPE_U32
:
7388 case VMCS_FIELD_TYPE_U64
:
7398 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7399 unsigned long field
, u64 field_value
){
7400 short offset
= vmcs_field_to_offset(field
);
7401 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7405 switch (vmcs_field_type(field
)) {
7406 case VMCS_FIELD_TYPE_U16
:
7407 *(u16
*)p
= field_value
;
7409 case VMCS_FIELD_TYPE_U32
:
7410 *(u32
*)p
= field_value
;
7412 case VMCS_FIELD_TYPE_U64
:
7413 *(u64
*)p
= field_value
;
7415 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7416 *(natural_width
*)p
= field_value
;
7425 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7428 unsigned long field
;
7430 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7431 const unsigned long *fields
= shadow_read_write_fields
;
7432 const int num_fields
= max_shadow_read_write_fields
;
7436 vmcs_load(shadow_vmcs
);
7438 for (i
= 0; i
< num_fields
; i
++) {
7440 switch (vmcs_field_type(field
)) {
7441 case VMCS_FIELD_TYPE_U16
:
7442 field_value
= vmcs_read16(field
);
7444 case VMCS_FIELD_TYPE_U32
:
7445 field_value
= vmcs_read32(field
);
7447 case VMCS_FIELD_TYPE_U64
:
7448 field_value
= vmcs_read64(field
);
7450 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7451 field_value
= vmcs_readl(field
);
7457 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7460 vmcs_clear(shadow_vmcs
);
7461 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7466 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7468 const unsigned long *fields
[] = {
7469 shadow_read_write_fields
,
7470 shadow_read_only_fields
7472 const int max_fields
[] = {
7473 max_shadow_read_write_fields
,
7474 max_shadow_read_only_fields
7477 unsigned long field
;
7478 u64 field_value
= 0;
7479 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7481 vmcs_load(shadow_vmcs
);
7483 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7484 for (i
= 0; i
< max_fields
[q
]; i
++) {
7485 field
= fields
[q
][i
];
7486 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7488 switch (vmcs_field_type(field
)) {
7489 case VMCS_FIELD_TYPE_U16
:
7490 vmcs_write16(field
, (u16
)field_value
);
7492 case VMCS_FIELD_TYPE_U32
:
7493 vmcs_write32(field
, (u32
)field_value
);
7495 case VMCS_FIELD_TYPE_U64
:
7496 vmcs_write64(field
, (u64
)field_value
);
7498 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7499 vmcs_writel(field
, (long)field_value
);
7508 vmcs_clear(shadow_vmcs
);
7509 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7513 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7514 * used before) all generate the same failure when it is missing.
7516 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7518 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7519 if (vmx
->nested
.current_vmptr
== -1ull) {
7520 nested_vmx_failInvalid(vcpu
);
7526 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7528 unsigned long field
;
7530 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7531 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7534 if (!nested_vmx_check_permission(vcpu
))
7537 if (!nested_vmx_check_vmcs12(vcpu
))
7538 return kvm_skip_emulated_instruction(vcpu
);
7540 /* Decode instruction info and find the field to read */
7541 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7542 /* Read the field, zero-extended to a u64 field_value */
7543 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7544 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7545 return kvm_skip_emulated_instruction(vcpu
);
7548 * Now copy part of this value to register or memory, as requested.
7549 * Note that the number of bits actually copied is 32 or 64 depending
7550 * on the guest's mode (32 or 64 bit), not on the given field's length.
7552 if (vmx_instruction_info
& (1u << 10)) {
7553 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7556 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7557 vmx_instruction_info
, true, &gva
))
7559 /* _system ok, as hardware has verified cpl=0 */
7560 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7561 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7564 nested_vmx_succeed(vcpu
);
7565 return kvm_skip_emulated_instruction(vcpu
);
7569 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7571 unsigned long field
;
7573 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7574 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7575 /* The value to write might be 32 or 64 bits, depending on L1's long
7576 * mode, and eventually we need to write that into a field of several
7577 * possible lengths. The code below first zero-extends the value to 64
7578 * bit (field_value), and then copies only the appropriate number of
7579 * bits into the vmcs12 field.
7581 u64 field_value
= 0;
7582 struct x86_exception e
;
7584 if (!nested_vmx_check_permission(vcpu
))
7587 if (!nested_vmx_check_vmcs12(vcpu
))
7588 return kvm_skip_emulated_instruction(vcpu
);
7590 if (vmx_instruction_info
& (1u << 10))
7591 field_value
= kvm_register_readl(vcpu
,
7592 (((vmx_instruction_info
) >> 3) & 0xf));
7594 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7595 vmx_instruction_info
, false, &gva
))
7597 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7598 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7599 kvm_inject_page_fault(vcpu
, &e
);
7605 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7606 if (vmcs_field_readonly(field
)) {
7607 nested_vmx_failValid(vcpu
,
7608 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7609 return kvm_skip_emulated_instruction(vcpu
);
7612 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7613 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7614 return kvm_skip_emulated_instruction(vcpu
);
7617 nested_vmx_succeed(vcpu
);
7618 return kvm_skip_emulated_instruction(vcpu
);
7621 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7623 vmx
->nested
.current_vmptr
= vmptr
;
7624 if (enable_shadow_vmcs
) {
7625 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7626 SECONDARY_EXEC_SHADOW_VMCS
);
7627 vmcs_write64(VMCS_LINK_POINTER
,
7628 __pa(vmx
->vmcs01
.shadow_vmcs
));
7629 vmx
->nested
.sync_shadow_vmcs
= true;
7633 /* Emulate the VMPTRLD instruction */
7634 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7636 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7639 if (!nested_vmx_check_permission(vcpu
))
7642 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7645 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7646 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7647 return kvm_skip_emulated_instruction(vcpu
);
7650 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7651 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7652 return kvm_skip_emulated_instruction(vcpu
);
7655 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7656 struct vmcs12
*new_vmcs12
;
7658 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7659 if (is_error_page(page
)) {
7660 nested_vmx_failInvalid(vcpu
);
7661 return kvm_skip_emulated_instruction(vcpu
);
7663 new_vmcs12
= kmap(page
);
7664 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7666 kvm_release_page_clean(page
);
7667 nested_vmx_failValid(vcpu
,
7668 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7669 return kvm_skip_emulated_instruction(vcpu
);
7672 nested_release_vmcs12(vmx
);
7674 * Load VMCS12 from guest memory since it is not already
7677 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7679 kvm_release_page_clean(page
);
7681 set_current_vmptr(vmx
, vmptr
);
7684 nested_vmx_succeed(vcpu
);
7685 return kvm_skip_emulated_instruction(vcpu
);
7688 /* Emulate the VMPTRST instruction */
7689 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7691 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7692 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7694 struct x86_exception e
;
7696 if (!nested_vmx_check_permission(vcpu
))
7699 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7700 vmx_instruction_info
, true, &vmcs_gva
))
7702 /* ok to use *_system, as hardware has verified cpl=0 */
7703 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7704 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7706 kvm_inject_page_fault(vcpu
, &e
);
7709 nested_vmx_succeed(vcpu
);
7710 return kvm_skip_emulated_instruction(vcpu
);
7713 /* Emulate the INVEPT instruction */
7714 static int handle_invept(struct kvm_vcpu
*vcpu
)
7716 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7717 u32 vmx_instruction_info
, types
;
7720 struct x86_exception e
;
7725 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7726 SECONDARY_EXEC_ENABLE_EPT
) ||
7727 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7728 kvm_queue_exception(vcpu
, UD_VECTOR
);
7732 if (!nested_vmx_check_permission(vcpu
))
7735 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7736 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7738 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7740 if (type
>= 32 || !(types
& (1 << type
))) {
7741 nested_vmx_failValid(vcpu
,
7742 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7743 return kvm_skip_emulated_instruction(vcpu
);
7746 /* According to the Intel VMX instruction reference, the memory
7747 * operand is read even if it isn't needed (e.g., for type==global)
7749 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7750 vmx_instruction_info
, false, &gva
))
7752 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7753 sizeof(operand
), &e
)) {
7754 kvm_inject_page_fault(vcpu
, &e
);
7759 case VMX_EPT_EXTENT_GLOBAL
:
7761 * TODO: track mappings and invalidate
7762 * single context requests appropriately
7764 case VMX_EPT_EXTENT_CONTEXT
:
7765 kvm_mmu_sync_roots(vcpu
);
7766 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7767 nested_vmx_succeed(vcpu
);
7774 return kvm_skip_emulated_instruction(vcpu
);
7777 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7779 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7780 u32 vmx_instruction_info
;
7781 unsigned long type
, types
;
7783 struct x86_exception e
;
7789 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7790 SECONDARY_EXEC_ENABLE_VPID
) ||
7791 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7792 kvm_queue_exception(vcpu
, UD_VECTOR
);
7796 if (!nested_vmx_check_permission(vcpu
))
7799 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7800 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7802 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7803 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7805 if (type
>= 32 || !(types
& (1 << type
))) {
7806 nested_vmx_failValid(vcpu
,
7807 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7808 return kvm_skip_emulated_instruction(vcpu
);
7811 /* according to the intel vmx instruction reference, the memory
7812 * operand is read even if it isn't needed (e.g., for type==global)
7814 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7815 vmx_instruction_info
, false, &gva
))
7817 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7818 sizeof(operand
), &e
)) {
7819 kvm_inject_page_fault(vcpu
, &e
);
7822 if (operand
.vpid
>> 16) {
7823 nested_vmx_failValid(vcpu
,
7824 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7825 return kvm_skip_emulated_instruction(vcpu
);
7829 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7830 if (is_noncanonical_address(operand
.gla
)) {
7831 nested_vmx_failValid(vcpu
,
7832 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7833 return kvm_skip_emulated_instruction(vcpu
);
7836 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7837 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7838 if (!operand
.vpid
) {
7839 nested_vmx_failValid(vcpu
,
7840 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7841 return kvm_skip_emulated_instruction(vcpu
);
7844 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7848 return kvm_skip_emulated_instruction(vcpu
);
7851 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7852 nested_vmx_succeed(vcpu
);
7854 return kvm_skip_emulated_instruction(vcpu
);
7857 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7859 unsigned long exit_qualification
;
7861 trace_kvm_pml_full(vcpu
->vcpu_id
);
7863 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7866 * PML buffer FULL happened while executing iret from NMI,
7867 * "blocked by NMI" bit has to be set before next VM entry.
7869 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7870 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7871 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7872 GUEST_INTR_STATE_NMI
);
7875 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7876 * here.., and there's no userspace involvement needed for PML.
7881 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7883 kvm_lapic_expired_hv_timer(vcpu
);
7887 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
7889 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7890 u64 mask
= address
& 0x7;
7891 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
7893 /* Check for memory type validity */
7896 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
7900 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
7907 /* Bits 5:3 must be 3 */
7908 if (((address
>> VMX_EPT_GAW_EPTP_SHIFT
) & 0x7) != VMX_EPT_DEFAULT_GAW
)
7911 /* Reserved bits should not be set */
7912 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
7915 /* AD, if set, should be supported */
7916 if ((address
& VMX_EPT_AD_ENABLE_BIT
)) {
7917 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
7924 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
7925 struct vmcs12
*vmcs12
)
7927 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7929 bool accessed_dirty
;
7930 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
7932 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
7933 !nested_cpu_has_ept(vmcs12
))
7936 if (index
>= VMFUNC_EPTP_ENTRIES
)
7940 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
7941 &address
, index
* 8, 8))
7944 accessed_dirty
= !!(address
& VMX_EPT_AD_ENABLE_BIT
);
7947 * If the (L2) guest does a vmfunc to the currently
7948 * active ept pointer, we don't have to do anything else
7950 if (vmcs12
->ept_pointer
!= address
) {
7951 if (!valid_ept_address(vcpu
, address
))
7954 kvm_mmu_unload(vcpu
);
7955 mmu
->ept_ad
= accessed_dirty
;
7956 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
7957 vmcs12
->ept_pointer
= address
;
7959 * TODO: Check what's the correct approach in case
7960 * mmu reload fails. Currently, we just let the next
7961 * reload potentially fail
7963 kvm_mmu_reload(vcpu
);
7969 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
7971 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7972 struct vmcs12
*vmcs12
;
7973 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
7976 * VMFUNC is only supported for nested guests, but we always enable the
7977 * secondary control for simplicity; for non-nested mode, fake that we
7978 * didn't by injecting #UD.
7980 if (!is_guest_mode(vcpu
)) {
7981 kvm_queue_exception(vcpu
, UD_VECTOR
);
7985 vmcs12
= get_vmcs12(vcpu
);
7986 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
7991 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
7997 return kvm_skip_emulated_instruction(vcpu
);
8000 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8001 vmcs_read32(VM_EXIT_INTR_INFO
),
8002 vmcs_readl(EXIT_QUALIFICATION
));
8007 * The exit handlers return 1 if the exit was handled fully and guest execution
8008 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8009 * to be done to userspace and return 0.
8011 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8012 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8013 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8014 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8015 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8016 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8017 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8018 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8019 [EXIT_REASON_CPUID
] = handle_cpuid
,
8020 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8021 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8022 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8023 [EXIT_REASON_HLT
] = handle_halt
,
8024 [EXIT_REASON_INVD
] = handle_invd
,
8025 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8026 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8027 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8028 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8029 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8030 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8031 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8032 [EXIT_REASON_VMREAD
] = handle_vmread
,
8033 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8034 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8035 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8036 [EXIT_REASON_VMON
] = handle_vmon
,
8037 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8038 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8039 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8040 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8041 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8042 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8043 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8044 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8045 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8046 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8047 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8048 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8049 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8050 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8051 [EXIT_REASON_INVEPT
] = handle_invept
,
8052 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8053 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8054 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8055 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8056 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8057 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8060 static const int kvm_vmx_max_exit_handlers
=
8061 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8063 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8064 struct vmcs12
*vmcs12
)
8066 unsigned long exit_qualification
;
8067 gpa_t bitmap
, last_bitmap
;
8072 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8073 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8075 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8077 port
= exit_qualification
>> 16;
8078 size
= (exit_qualification
& 7) + 1;
8080 last_bitmap
= (gpa_t
)-1;
8085 bitmap
= vmcs12
->io_bitmap_a
;
8086 else if (port
< 0x10000)
8087 bitmap
= vmcs12
->io_bitmap_b
;
8090 bitmap
+= (port
& 0x7fff) / 8;
8092 if (last_bitmap
!= bitmap
)
8093 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8095 if (b
& (1 << (port
& 7)))
8100 last_bitmap
= bitmap
;
8107 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8108 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8109 * disinterest in the current event (read or write a specific MSR) by using an
8110 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8112 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8113 struct vmcs12
*vmcs12
, u32 exit_reason
)
8115 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8118 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8122 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8123 * for the four combinations of read/write and low/high MSR numbers.
8124 * First we need to figure out which of the four to use:
8126 bitmap
= vmcs12
->msr_bitmap
;
8127 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8129 if (msr_index
>= 0xc0000000) {
8130 msr_index
-= 0xc0000000;
8134 /* Then read the msr_index'th bit from this bitmap: */
8135 if (msr_index
< 1024*8) {
8137 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8139 return 1 & (b
>> (msr_index
& 7));
8141 return true; /* let L1 handle the wrong parameter */
8145 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8146 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8147 * intercept (via guest_host_mask etc.) the current event.
8149 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8150 struct vmcs12
*vmcs12
)
8152 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8153 int cr
= exit_qualification
& 15;
8157 switch ((exit_qualification
>> 4) & 3) {
8158 case 0: /* mov to cr */
8159 reg
= (exit_qualification
>> 8) & 15;
8160 val
= kvm_register_readl(vcpu
, reg
);
8163 if (vmcs12
->cr0_guest_host_mask
&
8164 (val
^ vmcs12
->cr0_read_shadow
))
8168 if ((vmcs12
->cr3_target_count
>= 1 &&
8169 vmcs12
->cr3_target_value0
== val
) ||
8170 (vmcs12
->cr3_target_count
>= 2 &&
8171 vmcs12
->cr3_target_value1
== val
) ||
8172 (vmcs12
->cr3_target_count
>= 3 &&
8173 vmcs12
->cr3_target_value2
== val
) ||
8174 (vmcs12
->cr3_target_count
>= 4 &&
8175 vmcs12
->cr3_target_value3
== val
))
8177 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8181 if (vmcs12
->cr4_guest_host_mask
&
8182 (vmcs12
->cr4_read_shadow
^ val
))
8186 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8192 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8193 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8196 case 1: /* mov from cr */
8199 if (vmcs12
->cpu_based_vm_exec_control
&
8200 CPU_BASED_CR3_STORE_EXITING
)
8204 if (vmcs12
->cpu_based_vm_exec_control
&
8205 CPU_BASED_CR8_STORE_EXITING
)
8212 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8213 * cr0. Other attempted changes are ignored, with no exit.
8215 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8216 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8217 (val
^ vmcs12
->cr0_read_shadow
))
8219 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8220 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8229 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8230 * should handle it ourselves in L0 (and then continue L2). Only call this
8231 * when in is_guest_mode (L2).
8233 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8235 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8236 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8237 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8239 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8240 vmcs_readl(EXIT_QUALIFICATION
),
8241 vmx
->idt_vectoring_info
,
8243 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8247 * The host physical addresses of some pages of guest memory
8248 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8249 * may write to these pages via their host physical address while
8250 * L2 is running, bypassing any address-translation-based dirty
8251 * tracking (e.g. EPT write protection).
8253 * Mark them dirty on every exit from L2 to prevent them from
8254 * getting out of sync with dirty tracking.
8256 nested_mark_vmcs12_pages_dirty(vcpu
);
8258 if (vmx
->nested
.nested_run_pending
)
8261 if (unlikely(vmx
->fail
)) {
8262 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8263 vmcs_read32(VM_INSTRUCTION_ERROR
));
8267 switch (exit_reason
) {
8268 case EXIT_REASON_EXCEPTION_NMI
:
8269 if (is_nmi(intr_info
))
8271 else if (is_page_fault(intr_info
))
8272 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8273 else if (is_no_device(intr_info
) &&
8274 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8276 else if (is_debug(intr_info
) &&
8278 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8280 else if (is_breakpoint(intr_info
) &&
8281 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8283 return vmcs12
->exception_bitmap
&
8284 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8285 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8287 case EXIT_REASON_TRIPLE_FAULT
:
8289 case EXIT_REASON_PENDING_INTERRUPT
:
8290 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8291 case EXIT_REASON_NMI_WINDOW
:
8292 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8293 case EXIT_REASON_TASK_SWITCH
:
8295 case EXIT_REASON_CPUID
:
8297 case EXIT_REASON_HLT
:
8298 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8299 case EXIT_REASON_INVD
:
8301 case EXIT_REASON_INVLPG
:
8302 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8303 case EXIT_REASON_RDPMC
:
8304 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8305 case EXIT_REASON_RDRAND
:
8306 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8307 case EXIT_REASON_RDSEED
:
8308 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8309 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8310 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8311 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8312 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8313 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8314 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8315 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8316 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8318 * VMX instructions trap unconditionally. This allows L1 to
8319 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8322 case EXIT_REASON_CR_ACCESS
:
8323 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8324 case EXIT_REASON_DR_ACCESS
:
8325 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8326 case EXIT_REASON_IO_INSTRUCTION
:
8327 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8328 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8329 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8330 case EXIT_REASON_MSR_READ
:
8331 case EXIT_REASON_MSR_WRITE
:
8332 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8333 case EXIT_REASON_INVALID_STATE
:
8335 case EXIT_REASON_MWAIT_INSTRUCTION
:
8336 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8337 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8338 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8339 case EXIT_REASON_MONITOR_INSTRUCTION
:
8340 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8341 case EXIT_REASON_PAUSE_INSTRUCTION
:
8342 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8343 nested_cpu_has2(vmcs12
,
8344 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8345 case EXIT_REASON_MCE_DURING_VMENTRY
:
8347 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8348 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8349 case EXIT_REASON_APIC_ACCESS
:
8350 return nested_cpu_has2(vmcs12
,
8351 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8352 case EXIT_REASON_APIC_WRITE
:
8353 case EXIT_REASON_EOI_INDUCED
:
8354 /* apic_write and eoi_induced should exit unconditionally. */
8356 case EXIT_REASON_EPT_VIOLATION
:
8358 * L0 always deals with the EPT violation. If nested EPT is
8359 * used, and the nested mmu code discovers that the address is
8360 * missing in the guest EPT table (EPT12), the EPT violation
8361 * will be injected with nested_ept_inject_page_fault()
8364 case EXIT_REASON_EPT_MISCONFIG
:
8366 * L2 never uses directly L1's EPT, but rather L0's own EPT
8367 * table (shadow on EPT) or a merged EPT table that L0 built
8368 * (EPT on EPT). So any problems with the structure of the
8369 * table is L0's fault.
8372 case EXIT_REASON_INVPCID
:
8374 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8375 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8376 case EXIT_REASON_WBINVD
:
8377 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8378 case EXIT_REASON_XSETBV
:
8380 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8382 * This should never happen, since it is not possible to
8383 * set XSS to a non-zero value---neither in L1 nor in L2.
8384 * If if it were, XSS would have to be checked against
8385 * the XSS exit bitmap in vmcs12.
8387 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8388 case EXIT_REASON_PREEMPTION_TIMER
:
8390 case EXIT_REASON_PML_FULL
:
8391 /* We emulate PML support to L1. */
8393 case EXIT_REASON_VMFUNC
:
8394 /* VM functions are emulated through L2->L0 vmexits. */
8401 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8403 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8406 * At this point, the exit interruption info in exit_intr_info
8407 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8408 * we need to query the in-kernel LAPIC.
8410 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8411 if ((exit_intr_info
&
8412 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8413 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8414 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8415 vmcs12
->vm_exit_intr_error_code
=
8416 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8419 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8420 vmcs_readl(EXIT_QUALIFICATION
));
8424 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8426 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8427 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8430 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8433 __free_page(vmx
->pml_pg
);
8438 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8440 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8444 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8446 /* Do nothing if PML buffer is empty */
8447 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8450 /* PML index always points to next available PML buffer entity */
8451 if (pml_idx
>= PML_ENTITY_NUM
)
8456 pml_buf
= page_address(vmx
->pml_pg
);
8457 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8460 gpa
= pml_buf
[pml_idx
];
8461 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8462 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8465 /* reset PML index */
8466 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8470 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8471 * Called before reporting dirty_bitmap to userspace.
8473 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8476 struct kvm_vcpu
*vcpu
;
8478 * We only need to kick vcpu out of guest mode here, as PML buffer
8479 * is flushed at beginning of all VMEXITs, and it's obvious that only
8480 * vcpus running in guest are possible to have unflushed GPAs in PML
8483 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8484 kvm_vcpu_kick(vcpu
);
8487 static void vmx_dump_sel(char *name
, uint32_t sel
)
8489 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8490 name
, vmcs_read16(sel
),
8491 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8492 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8493 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8496 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8498 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8499 name
, vmcs_read32(limit
),
8500 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8503 static void dump_vmcs(void)
8505 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8506 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8507 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8508 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8509 u32 secondary_exec_control
= 0;
8510 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8511 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8514 if (cpu_has_secondary_exec_ctrls())
8515 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8517 pr_err("*** Guest State ***\n");
8518 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8519 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8520 vmcs_readl(CR0_GUEST_HOST_MASK
));
8521 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8522 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8523 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8524 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8525 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8527 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8528 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8529 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8530 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8532 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8533 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8534 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8535 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8536 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8537 vmcs_readl(GUEST_SYSENTER_ESP
),
8538 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8539 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8540 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8541 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8542 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8543 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8544 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8545 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8546 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8547 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8548 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8549 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8550 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8551 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8552 efer
, vmcs_read64(GUEST_IA32_PAT
));
8553 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8554 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8555 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8556 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8557 pr_err("PerfGlobCtl = 0x%016llx\n",
8558 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8559 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8560 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8561 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8562 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8563 vmcs_read32(GUEST_ACTIVITY_STATE
));
8564 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8565 pr_err("InterruptStatus = %04x\n",
8566 vmcs_read16(GUEST_INTR_STATUS
));
8568 pr_err("*** Host State ***\n");
8569 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8570 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8571 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8572 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8573 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8574 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8575 vmcs_read16(HOST_TR_SELECTOR
));
8576 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8577 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8578 vmcs_readl(HOST_TR_BASE
));
8579 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8580 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8581 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8582 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8583 vmcs_readl(HOST_CR4
));
8584 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8585 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8586 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8587 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8588 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8589 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8590 vmcs_read64(HOST_IA32_EFER
),
8591 vmcs_read64(HOST_IA32_PAT
));
8592 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8593 pr_err("PerfGlobCtl = 0x%016llx\n",
8594 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8596 pr_err("*** Control State ***\n");
8597 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8598 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8599 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8600 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8601 vmcs_read32(EXCEPTION_BITMAP
),
8602 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8603 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8604 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8605 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8606 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8607 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8608 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8609 vmcs_read32(VM_EXIT_INTR_INFO
),
8610 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8611 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8612 pr_err(" reason=%08x qualification=%016lx\n",
8613 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8614 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8615 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8616 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8617 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8618 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8619 pr_err("TSC Multiplier = 0x%016llx\n",
8620 vmcs_read64(TSC_MULTIPLIER
));
8621 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8622 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8623 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8624 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8625 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8626 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8627 n
= vmcs_read32(CR3_TARGET_COUNT
);
8628 for (i
= 0; i
+ 1 < n
; i
+= 4)
8629 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8630 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8631 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8633 pr_err("CR3 target%u=%016lx\n",
8634 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8635 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8636 pr_err("PLE Gap=%08x Window=%08x\n",
8637 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8638 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8639 pr_err("Virtual processor ID = 0x%04x\n",
8640 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8644 * The guest has exited. See if we can fix it or if we need userspace
8647 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8649 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8650 u32 exit_reason
= vmx
->exit_reason
;
8651 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8653 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8654 vcpu
->arch
.gpa_available
= false;
8657 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8658 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8659 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8660 * mode as if vcpus is in root mode, the PML buffer must has been
8664 vmx_flush_pml_buffer(vcpu
);
8666 /* If guest state is invalid, start emulating */
8667 if (vmx
->emulation_required
)
8668 return handle_invalid_guest_state(vcpu
);
8670 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8671 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8673 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8675 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8676 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8681 if (unlikely(vmx
->fail
)) {
8682 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8683 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8684 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8690 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8691 * delivery event since it indicates guest is accessing MMIO.
8692 * The vm-exit can be triggered again after return to guest that
8693 * will cause infinite loop.
8695 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8696 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8697 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8698 exit_reason
!= EXIT_REASON_PML_FULL
&&
8699 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8700 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8701 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8702 vcpu
->run
->internal
.ndata
= 3;
8703 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8704 vcpu
->run
->internal
.data
[1] = exit_reason
;
8705 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8706 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8707 vcpu
->run
->internal
.ndata
++;
8708 vcpu
->run
->internal
.data
[3] =
8709 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8714 if (exit_reason
< kvm_vmx_max_exit_handlers
8715 && kvm_vmx_exit_handlers
[exit_reason
])
8716 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8718 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8720 kvm_queue_exception(vcpu
, UD_VECTOR
);
8725 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8727 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8729 if (is_guest_mode(vcpu
) &&
8730 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8733 if (irr
== -1 || tpr
< irr
) {
8734 vmcs_write32(TPR_THRESHOLD
, 0);
8738 vmcs_write32(TPR_THRESHOLD
, irr
);
8741 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8743 u32 sec_exec_control
;
8745 /* Postpone execution until vmcs01 is the current VMCS. */
8746 if (is_guest_mode(vcpu
)) {
8747 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8751 if (!cpu_has_vmx_virtualize_x2apic_mode())
8754 if (!cpu_need_tpr_shadow(vcpu
))
8757 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8760 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8761 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8763 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8764 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8765 vmx_flush_tlb_ept_only(vcpu
);
8767 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8769 vmx_set_msr_bitmap(vcpu
);
8772 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8774 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8777 * Currently we do not handle the nested case where L2 has an
8778 * APIC access page of its own; that page is still pinned.
8779 * Hence, we skip the case where the VCPU is in guest mode _and_
8780 * L1 prepared an APIC access page for L2.
8782 * For the case where L1 and L2 share the same APIC access page
8783 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8784 * in the vmcs12), this function will only update either the vmcs01
8785 * or the vmcs02. If the former, the vmcs02 will be updated by
8786 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8787 * the next L2->L1 exit.
8789 if (!is_guest_mode(vcpu
) ||
8790 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8791 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8792 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8793 vmx_flush_tlb_ept_only(vcpu
);
8797 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8805 status
= vmcs_read16(GUEST_INTR_STATUS
);
8807 if (max_isr
!= old
) {
8809 status
|= max_isr
<< 8;
8810 vmcs_write16(GUEST_INTR_STATUS
, status
);
8814 static void vmx_set_rvi(int vector
)
8822 status
= vmcs_read16(GUEST_INTR_STATUS
);
8823 old
= (u8
)status
& 0xff;
8824 if ((u8
)vector
!= old
) {
8826 status
|= (u8
)vector
;
8827 vmcs_write16(GUEST_INTR_STATUS
, status
);
8831 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8833 if (!is_guest_mode(vcpu
)) {
8834 vmx_set_rvi(max_irr
);
8842 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8845 if (nested_exit_on_intr(vcpu
))
8849 * Else, fall back to pre-APICv interrupt injection since L2
8850 * is run without virtual interrupt delivery.
8852 if (!kvm_event_needs_reinjection(vcpu
) &&
8853 vmx_interrupt_allowed(vcpu
)) {
8854 kvm_queue_interrupt(vcpu
, max_irr
, false);
8855 vmx_inject_irq(vcpu
);
8859 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8861 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8864 WARN_ON(!vcpu
->arch
.apicv_active
);
8865 if (pi_test_on(&vmx
->pi_desc
)) {
8866 pi_clear_on(&vmx
->pi_desc
);
8868 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8869 * But on x86 this is just a compiler barrier anyway.
8871 smp_mb__after_atomic();
8872 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8874 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8876 vmx_hwapic_irr_update(vcpu
, max_irr
);
8880 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8882 if (!kvm_vcpu_apicv_active(vcpu
))
8885 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8886 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8887 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8888 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8891 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8895 pi_clear_on(&vmx
->pi_desc
);
8896 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8899 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8901 u32 exit_intr_info
= 0;
8902 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8904 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8905 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8908 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8909 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8910 vmx
->exit_intr_info
= exit_intr_info
;
8912 /* if exit due to PF check for async PF */
8913 if (is_page_fault(exit_intr_info
))
8914 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
8916 /* Handle machine checks before interrupts are enabled */
8917 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
8918 is_machine_check(exit_intr_info
))
8919 kvm_machine_check();
8921 /* We need to handle NMIs before interrupts are enabled */
8922 if (is_nmi(exit_intr_info
)) {
8923 kvm_before_handle_nmi(&vmx
->vcpu
);
8925 kvm_after_handle_nmi(&vmx
->vcpu
);
8929 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8931 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8932 register void *__sp
asm(_ASM_SP
);
8934 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8935 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8936 unsigned int vector
;
8937 unsigned long entry
;
8939 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8940 #ifdef CONFIG_X86_64
8944 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8945 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8946 entry
= gate_offset(*desc
);
8948 #ifdef CONFIG_X86_64
8949 "mov %%" _ASM_SP
", %[sp]\n\t"
8950 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8955 __ASM_SIZE(push
) " $%c[cs]\n\t"
8956 "call *%[entry]\n\t"
8958 #ifdef CONFIG_X86_64
8964 [ss
]"i"(__KERNEL_DS
),
8965 [cs
]"i"(__KERNEL_CS
)
8969 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8971 static bool vmx_has_high_real_mode_segbase(void)
8973 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8976 static bool vmx_mpx_supported(void)
8978 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8979 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8982 static bool vmx_xsaves_supported(void)
8984 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8985 SECONDARY_EXEC_XSAVES
;
8988 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8993 bool idtv_info_valid
;
8995 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8997 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9000 * Can't use vmx->exit_intr_info since we're not sure what
9001 * the exit reason is.
9003 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9004 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9005 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9007 * SDM 3: 27.7.1.2 (September 2008)
9008 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9009 * a guest IRET fault.
9010 * SDM 3: 23.2.2 (September 2008)
9011 * Bit 12 is undefined in any of the following cases:
9012 * If the VM exit sets the valid bit in the IDT-vectoring
9013 * information field.
9014 * If the VM exit is due to a double fault.
9016 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9017 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9018 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9019 GUEST_INTR_STATE_NMI
);
9021 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9022 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9023 & GUEST_INTR_STATE_NMI
);
9026 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9027 u32 idt_vectoring_info
,
9028 int instr_len_field
,
9029 int error_code_field
)
9033 bool idtv_info_valid
;
9035 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9037 vcpu
->arch
.nmi_injected
= false;
9038 kvm_clear_exception_queue(vcpu
);
9039 kvm_clear_interrupt_queue(vcpu
);
9041 if (!idtv_info_valid
)
9044 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9046 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9047 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9050 case INTR_TYPE_NMI_INTR
:
9051 vcpu
->arch
.nmi_injected
= true;
9053 * SDM 3: 27.7.1.2 (September 2008)
9054 * Clear bit "block by NMI" before VM entry if a NMI
9057 vmx_set_nmi_mask(vcpu
, false);
9059 case INTR_TYPE_SOFT_EXCEPTION
:
9060 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9062 case INTR_TYPE_HARD_EXCEPTION
:
9063 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9064 u32 err
= vmcs_read32(error_code_field
);
9065 kvm_requeue_exception_e(vcpu
, vector
, err
);
9067 kvm_requeue_exception(vcpu
, vector
);
9069 case INTR_TYPE_SOFT_INTR
:
9070 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9072 case INTR_TYPE_EXT_INTR
:
9073 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9080 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9082 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9083 VM_EXIT_INSTRUCTION_LEN
,
9084 IDT_VECTORING_ERROR_CODE
);
9087 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9089 __vmx_complete_interrupts(vcpu
,
9090 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9091 VM_ENTRY_INSTRUCTION_LEN
,
9092 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9094 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9097 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9100 struct perf_guest_switch_msr
*msrs
;
9102 msrs
= perf_guest_get_msrs(&nr_msrs
);
9107 for (i
= 0; i
< nr_msrs
; i
++)
9108 if (msrs
[i
].host
== msrs
[i
].guest
)
9109 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9111 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9115 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9117 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9121 if (vmx
->hv_deadline_tsc
== -1)
9125 if (vmx
->hv_deadline_tsc
> tscl
)
9126 /* sure to be 32 bit only because checked on set_hv_timer */
9127 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9128 cpu_preemption_timer_multi
);
9132 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9135 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9137 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9138 unsigned long debugctlmsr
, cr3
, cr4
;
9140 /* Don't enter VMX if guest state is invalid, let the exit handler
9141 start emulation until we arrive back to a valid state */
9142 if (vmx
->emulation_required
)
9145 if (vmx
->ple_window_dirty
) {
9146 vmx
->ple_window_dirty
= false;
9147 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9150 if (vmx
->nested
.sync_shadow_vmcs
) {
9151 copy_vmcs12_to_shadow(vmx
);
9152 vmx
->nested
.sync_shadow_vmcs
= false;
9155 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9156 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9157 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9158 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9160 cr3
= __get_current_cr3_fast();
9161 if (unlikely(cr3
!= vmx
->host_state
.vmcs_host_cr3
)) {
9162 vmcs_writel(HOST_CR3
, cr3
);
9163 vmx
->host_state
.vmcs_host_cr3
= cr3
;
9166 cr4
= cr4_read_shadow();
9167 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
9168 vmcs_writel(HOST_CR4
, cr4
);
9169 vmx
->host_state
.vmcs_host_cr4
= cr4
;
9172 /* When single-stepping over STI and MOV SS, we must clear the
9173 * corresponding interruptibility bits in the guest state. Otherwise
9174 * vmentry fails as it then expects bit 14 (BS) in pending debug
9175 * exceptions being set, but that's not correct for the guest debugging
9177 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9178 vmx_set_interrupt_shadow(vcpu
, 0);
9180 if (vmx
->guest_pkru_valid
)
9181 __write_pkru(vmx
->guest_pkru
);
9183 atomic_switch_perf_msrs(vmx
);
9184 debugctlmsr
= get_debugctlmsr();
9186 vmx_arm_hv_timer(vcpu
);
9188 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9190 /* Store host registers */
9191 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9192 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9193 "push %%" _ASM_CX
" \n\t"
9194 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9196 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9197 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9199 /* Reload cr2 if changed */
9200 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9201 "mov %%cr2, %%" _ASM_DX
" \n\t"
9202 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9204 "mov %%" _ASM_AX
", %%cr2 \n\t"
9206 /* Check if vmlaunch of vmresume is needed */
9207 "cmpl $0, %c[launched](%0) \n\t"
9208 /* Load guest registers. Don't clobber flags. */
9209 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9210 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9211 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9212 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9213 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9214 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9215 #ifdef CONFIG_X86_64
9216 "mov %c[r8](%0), %%r8 \n\t"
9217 "mov %c[r9](%0), %%r9 \n\t"
9218 "mov %c[r10](%0), %%r10 \n\t"
9219 "mov %c[r11](%0), %%r11 \n\t"
9220 "mov %c[r12](%0), %%r12 \n\t"
9221 "mov %c[r13](%0), %%r13 \n\t"
9222 "mov %c[r14](%0), %%r14 \n\t"
9223 "mov %c[r15](%0), %%r15 \n\t"
9225 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9227 /* Enter guest mode */
9229 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9231 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9233 /* Save guest registers, load host registers, keep flags */
9234 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9236 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9237 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9238 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9239 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9240 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9241 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9242 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9243 #ifdef CONFIG_X86_64
9244 "mov %%r8, %c[r8](%0) \n\t"
9245 "mov %%r9, %c[r9](%0) \n\t"
9246 "mov %%r10, %c[r10](%0) \n\t"
9247 "mov %%r11, %c[r11](%0) \n\t"
9248 "mov %%r12, %c[r12](%0) \n\t"
9249 "mov %%r13, %c[r13](%0) \n\t"
9250 "mov %%r14, %c[r14](%0) \n\t"
9251 "mov %%r15, %c[r15](%0) \n\t"
9253 "mov %%cr2, %%" _ASM_AX
" \n\t"
9254 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9256 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9257 "setbe %c[fail](%0) \n\t"
9258 ".pushsection .rodata \n\t"
9259 ".global vmx_return \n\t"
9260 "vmx_return: " _ASM_PTR
" 2b \n\t"
9262 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9263 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9264 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9265 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9266 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9267 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9268 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9269 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9270 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9271 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9272 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9273 #ifdef CONFIG_X86_64
9274 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9275 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9276 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9277 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9278 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9279 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9280 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9281 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9283 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9284 [wordsize
]"i"(sizeof(ulong
))
9286 #ifdef CONFIG_X86_64
9287 , "rax", "rbx", "rdi", "rsi"
9288 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9290 , "eax", "ebx", "edi", "esi"
9294 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9296 update_debugctlmsr(debugctlmsr
);
9298 #ifndef CONFIG_X86_64
9300 * The sysexit path does not restore ds/es, so we must set them to
9301 * a reasonable value ourselves.
9303 * We can't defer this to vmx_load_host_state() since that function
9304 * may be executed in interrupt context, which saves and restore segments
9305 * around it, nullifying its effect.
9307 loadsegment(ds
, __USER_DS
);
9308 loadsegment(es
, __USER_DS
);
9311 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9312 | (1 << VCPU_EXREG_RFLAGS
)
9313 | (1 << VCPU_EXREG_PDPTR
)
9314 | (1 << VCPU_EXREG_SEGMENTS
)
9315 | (1 << VCPU_EXREG_CR3
));
9316 vcpu
->arch
.regs_dirty
= 0;
9318 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9320 vmx
->loaded_vmcs
->launched
= 1;
9322 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9325 * eager fpu is enabled if PKEY is supported and CR4 is switched
9326 * back on host, so it is safe to read guest PKRU from current
9329 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9330 vmx
->guest_pkru
= __read_pkru();
9331 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9332 vmx
->guest_pkru_valid
= true;
9333 __write_pkru(vmx
->host_pkru
);
9335 vmx
->guest_pkru_valid
= false;
9339 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9340 * we did not inject a still-pending event to L1 now because of
9341 * nested_run_pending, we need to re-enable this bit.
9343 if (vmx
->nested
.nested_run_pending
)
9344 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9346 vmx
->nested
.nested_run_pending
= 0;
9348 vmx_complete_atomic_exit(vmx
);
9349 vmx_recover_nmi_blocking(vmx
);
9350 vmx_complete_interrupts(vmx
);
9352 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9354 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9356 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9359 if (vmx
->loaded_vmcs
== vmcs
)
9363 vmx
->loaded_vmcs
= vmcs
;
9365 vmx_vcpu_load(vcpu
, cpu
);
9371 * Ensure that the current vmcs of the logical processor is the
9372 * vmcs01 of the vcpu before calling free_nested().
9374 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9376 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9379 r
= vcpu_load(vcpu
);
9381 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9386 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9388 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9391 vmx_destroy_pml_buffer(vmx
);
9392 free_vpid(vmx
->vpid
);
9393 leave_guest_mode(vcpu
);
9394 vmx_free_vcpu_nested(vcpu
);
9395 free_loaded_vmcs(vmx
->loaded_vmcs
);
9396 kfree(vmx
->guest_msrs
);
9397 kvm_vcpu_uninit(vcpu
);
9398 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9401 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9404 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9408 return ERR_PTR(-ENOMEM
);
9410 vmx
->vpid
= allocate_vpid();
9412 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9419 * If PML is turned on, failure on enabling PML just results in failure
9420 * of creating the vcpu, therefore we can simplify PML logic (by
9421 * avoiding dealing with cases, such as enabling PML partially on vcpus
9422 * for the guest, etc.
9425 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9430 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9431 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9434 if (!vmx
->guest_msrs
)
9437 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9438 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9439 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9440 if (!vmx
->loaded_vmcs
->vmcs
)
9442 loaded_vmcs_init(vmx
->loaded_vmcs
);
9445 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9446 vmx
->vcpu
.cpu
= cpu
;
9447 err
= vmx_vcpu_setup(vmx
);
9448 vmx_vcpu_put(&vmx
->vcpu
);
9452 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9453 err
= alloc_apic_access_page(kvm
);
9459 if (!kvm
->arch
.ept_identity_map_addr
)
9460 kvm
->arch
.ept_identity_map_addr
=
9461 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9462 err
= init_rmode_identity_map(kvm
);
9468 nested_vmx_setup_ctls_msrs(vmx
);
9469 vmx
->nested
.vpid02
= allocate_vpid();
9472 vmx
->nested
.posted_intr_nv
= -1;
9473 vmx
->nested
.current_vmptr
= -1ull;
9475 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9480 free_vpid(vmx
->nested
.vpid02
);
9481 free_loaded_vmcs(vmx
->loaded_vmcs
);
9483 kfree(vmx
->guest_msrs
);
9485 vmx_destroy_pml_buffer(vmx
);
9487 kvm_vcpu_uninit(&vmx
->vcpu
);
9489 free_vpid(vmx
->vpid
);
9490 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9491 return ERR_PTR(err
);
9494 static void __init
vmx_check_processor_compat(void *rtn
)
9496 struct vmcs_config vmcs_conf
;
9499 if (setup_vmcs_config(&vmcs_conf
) < 0)
9501 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9502 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9503 smp_processor_id());
9508 static int get_ept_level(void)
9510 return VMX_EPT_DEFAULT_GAW
+ 1;
9513 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9518 /* For VT-d and EPT combination
9519 * 1. MMIO: always map as UC
9521 * a. VT-d without snooping control feature: can't guarantee the
9522 * result, try to trust guest.
9523 * b. VT-d with snooping control feature: snooping control feature of
9524 * VT-d engine can guarantee the cache correctness. Just set it
9525 * to WB to keep consistent with host. So the same as item 3.
9526 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9527 * consistent with host MTRR
9530 cache
= MTRR_TYPE_UNCACHABLE
;
9534 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9535 ipat
= VMX_EPT_IPAT_BIT
;
9536 cache
= MTRR_TYPE_WRBACK
;
9540 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9541 ipat
= VMX_EPT_IPAT_BIT
;
9542 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9543 cache
= MTRR_TYPE_WRBACK
;
9545 cache
= MTRR_TYPE_UNCACHABLE
;
9549 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9552 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9555 static int vmx_get_lpage_level(void)
9557 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9558 return PT_DIRECTORY_LEVEL
;
9560 /* For shadow and EPT supported 1GB page */
9561 return PT_PDPE_LEVEL
;
9564 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9567 * These bits in the secondary execution controls field
9568 * are dynamic, the others are mostly based on the hypervisor
9569 * architecture and the guest's CPUID. Do not touch the
9573 SECONDARY_EXEC_SHADOW_VMCS
|
9574 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9575 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9577 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9579 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9580 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9584 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9585 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9587 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9589 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9590 struct kvm_cpuid_entry2
*entry
;
9592 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9593 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9595 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9596 if (entry && (entry->_reg & (_cpuid_mask))) \
9597 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9600 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9601 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9602 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9603 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9604 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9605 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9606 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9607 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9608 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9609 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9610 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9611 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9612 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9613 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9614 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9616 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9617 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9618 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9619 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9620 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9621 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9622 cr4_fixed1_update(bit(11), ecx
, bit(2));
9624 #undef cr4_fixed1_update
9627 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9629 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9630 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9632 if (vmx_rdtscp_supported()) {
9633 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
9634 if (!rdtscp_enabled
)
9635 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9639 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9640 SECONDARY_EXEC_RDTSCP
;
9642 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9643 ~SECONDARY_EXEC_RDTSCP
;
9647 if (vmx_invpcid_supported()) {
9648 /* Exposing INVPCID only when PCID is exposed */
9649 bool invpcid_enabled
=
9650 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
9651 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
9653 if (!invpcid_enabled
) {
9654 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9655 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
9659 if (invpcid_enabled
)
9660 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9661 SECONDARY_EXEC_ENABLE_INVPCID
;
9663 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9664 ~SECONDARY_EXEC_ENABLE_INVPCID
;
9668 if (cpu_has_secondary_exec_ctrls())
9669 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9671 if (nested_vmx_allowed(vcpu
))
9672 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9673 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9675 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9676 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9678 if (nested_vmx_allowed(vcpu
))
9679 nested_vmx_cr_fixed1_bits_update(vcpu
);
9682 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9684 if (func
== 1 && nested
)
9685 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9688 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9689 struct x86_exception
*fault
)
9691 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9692 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9694 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9696 if (vmx
->nested
.pml_full
) {
9697 exit_reason
= EXIT_REASON_PML_FULL
;
9698 vmx
->nested
.pml_full
= false;
9699 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9700 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9701 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9703 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9705 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9706 vmcs12
->guest_physical_address
= fault
->address
;
9709 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9711 return nested_ept_get_cr3(vcpu
) & VMX_EPT_AD_ENABLE_BIT
;
9714 /* Callbacks for nested_ept_init_mmu_context: */
9716 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9718 /* return the page table to be shadowed - in our case, EPT12 */
9719 return get_vmcs12(vcpu
)->ept_pointer
;
9722 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9726 WARN_ON(mmu_is_nested(vcpu
));
9727 wants_ad
= nested_ept_ad_enabled(vcpu
);
9728 if (wants_ad
&& !enable_ept_ad_bits
)
9731 kvm_mmu_unload(vcpu
);
9732 kvm_init_shadow_ept_mmu(vcpu
,
9733 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9734 VMX_EPT_EXECUTE_ONLY_BIT
,
9736 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9737 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9738 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9740 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9744 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9746 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9749 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9752 bool inequality
, bit
;
9754 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9756 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9757 vmcs12
->page_fault_error_code_match
;
9758 return inequality
^ bit
;
9761 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9762 struct x86_exception
*fault
)
9764 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9766 WARN_ON(!is_guest_mode(vcpu
));
9768 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9769 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9770 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9771 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9772 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9775 kvm_inject_page_fault(vcpu
, fault
);
9779 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9780 struct vmcs12
*vmcs12
);
9782 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9783 struct vmcs12
*vmcs12
)
9785 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9789 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9791 * Translate L1 physical address to host physical
9792 * address for vmcs02. Keep the page pinned, so this
9793 * physical address remains valid. We keep a reference
9794 * to it so we can release it later.
9796 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9797 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9798 vmx
->nested
.apic_access_page
= NULL
;
9800 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9802 * If translation failed, no matter: This feature asks
9803 * to exit when accessing the given address, and if it
9804 * can never be accessed, this feature won't do
9807 if (!is_error_page(page
)) {
9808 vmx
->nested
.apic_access_page
= page
;
9809 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9810 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9812 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9813 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9815 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9816 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9817 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9818 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9819 kvm_vcpu_reload_apic_access_page(vcpu
);
9822 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9823 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9824 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9825 vmx
->nested
.virtual_apic_page
= NULL
;
9827 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9830 * If translation failed, VM entry will fail because
9831 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9832 * Failing the vm entry is _not_ what the processor
9833 * does but it's basically the only possibility we
9834 * have. We could still enter the guest if CR8 load
9835 * exits are enabled, CR8 store exits are enabled, and
9836 * virtualize APIC access is disabled; in this case
9837 * the processor would never use the TPR shadow and we
9838 * could simply clear the bit from the execution
9839 * control. But such a configuration is useless, so
9840 * let's keep the code simple.
9842 if (!is_error_page(page
)) {
9843 vmx
->nested
.virtual_apic_page
= page
;
9844 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9845 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9849 if (nested_cpu_has_posted_intr(vmcs12
)) {
9850 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9851 kunmap(vmx
->nested
.pi_desc_page
);
9852 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9853 vmx
->nested
.pi_desc_page
= NULL
;
9855 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9856 if (is_error_page(page
))
9858 vmx
->nested
.pi_desc_page
= page
;
9859 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9860 vmx
->nested
.pi_desc
=
9861 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9862 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9864 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9865 page_to_phys(vmx
->nested
.pi_desc_page
) +
9866 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9869 if (cpu_has_vmx_msr_bitmap() &&
9870 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9871 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9874 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9875 CPU_BASED_USE_MSR_BITMAPS
);
9878 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9880 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9881 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9883 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9886 /* Make sure short timeouts reliably trigger an immediate vmexit.
9887 * hrtimer_start does not guarantee this. */
9888 if (preemption_timeout
<= 1) {
9889 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9893 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9894 preemption_timeout
*= 1000000;
9895 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9896 hrtimer_start(&vmx
->nested
.preemption_timer
,
9897 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9900 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9901 struct vmcs12
*vmcs12
)
9903 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9906 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9907 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9913 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9914 struct vmcs12
*vmcs12
)
9916 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9919 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9926 * Merge L0's and L1's MSR bitmap, return false to indicate that
9927 * we do not use the hardware.
9929 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9930 struct vmcs12
*vmcs12
)
9934 unsigned long *msr_bitmap_l1
;
9935 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9937 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9938 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9941 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
9942 if (is_error_page(page
))
9944 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9946 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9948 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9949 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9950 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9951 nested_vmx_disable_intercept_for_msr(
9952 msr_bitmap_l1
, msr_bitmap_l0
,
9955 nested_vmx_disable_intercept_for_msr(
9956 msr_bitmap_l1
, msr_bitmap_l0
,
9957 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9958 MSR_TYPE_R
| MSR_TYPE_W
);
9960 if (nested_cpu_has_vid(vmcs12
)) {
9961 nested_vmx_disable_intercept_for_msr(
9962 msr_bitmap_l1
, msr_bitmap_l0
,
9963 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9965 nested_vmx_disable_intercept_for_msr(
9966 msr_bitmap_l1
, msr_bitmap_l0
,
9967 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9972 kvm_release_page_clean(page
);
9977 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9978 struct vmcs12
*vmcs12
)
9980 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9981 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9982 !nested_cpu_has_vid(vmcs12
) &&
9983 !nested_cpu_has_posted_intr(vmcs12
))
9987 * If virtualize x2apic mode is enabled,
9988 * virtualize apic access must be disabled.
9990 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9991 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9995 * If virtual interrupt delivery is enabled,
9996 * we must exit on external interrupts.
9998 if (nested_cpu_has_vid(vmcs12
) &&
9999 !nested_exit_on_intr(vcpu
))
10003 * bits 15:8 should be zero in posted_intr_nv,
10004 * the descriptor address has been already checked
10005 * in nested_get_vmcs12_pages.
10007 if (nested_cpu_has_posted_intr(vmcs12
) &&
10008 (!nested_cpu_has_vid(vmcs12
) ||
10009 !nested_exit_intr_ack_set(vcpu
) ||
10010 vmcs12
->posted_intr_nv
& 0xff00))
10013 /* tpr shadow is needed by all apicv features. */
10014 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10020 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10021 unsigned long count_field
,
10022 unsigned long addr_field
)
10027 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10028 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10034 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10035 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10036 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10037 pr_debug_ratelimited(
10038 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10039 addr_field
, maxphyaddr
, count
, addr
);
10045 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10046 struct vmcs12
*vmcs12
)
10048 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10049 vmcs12
->vm_exit_msr_store_count
== 0 &&
10050 vmcs12
->vm_entry_msr_load_count
== 0)
10051 return 0; /* Fast path */
10052 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10053 VM_EXIT_MSR_LOAD_ADDR
) ||
10054 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10055 VM_EXIT_MSR_STORE_ADDR
) ||
10056 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10057 VM_ENTRY_MSR_LOAD_ADDR
))
10062 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10063 struct vmcs12
*vmcs12
)
10065 u64 address
= vmcs12
->pml_address
;
10066 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10068 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10069 if (!nested_cpu_has_ept(vmcs12
) ||
10070 !IS_ALIGNED(address
, 4096) ||
10071 address
>> maxphyaddr
)
10078 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10079 struct vmx_msr_entry
*e
)
10081 /* x2APIC MSR accesses are not allowed */
10082 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10084 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10085 e
->index
== MSR_IA32_UCODE_REV
)
10087 if (e
->reserved
!= 0)
10092 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10093 struct vmx_msr_entry
*e
)
10095 if (e
->index
== MSR_FS_BASE
||
10096 e
->index
== MSR_GS_BASE
||
10097 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10098 nested_vmx_msr_check_common(vcpu
, e
))
10103 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10104 struct vmx_msr_entry
*e
)
10106 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10107 nested_vmx_msr_check_common(vcpu
, e
))
10113 * Load guest's/host's msr at nested entry/exit.
10114 * return 0 for success, entry index for failure.
10116 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10119 struct vmx_msr_entry e
;
10120 struct msr_data msr
;
10122 msr
.host_initiated
= false;
10123 for (i
= 0; i
< count
; i
++) {
10124 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10126 pr_debug_ratelimited(
10127 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10128 __func__
, i
, gpa
+ i
* sizeof(e
));
10131 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10132 pr_debug_ratelimited(
10133 "%s check failed (%u, 0x%x, 0x%x)\n",
10134 __func__
, i
, e
.index
, e
.reserved
);
10137 msr
.index
= e
.index
;
10138 msr
.data
= e
.value
;
10139 if (kvm_set_msr(vcpu
, &msr
)) {
10140 pr_debug_ratelimited(
10141 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10142 __func__
, i
, e
.index
, e
.value
);
10151 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10154 struct vmx_msr_entry e
;
10156 for (i
= 0; i
< count
; i
++) {
10157 struct msr_data msr_info
;
10158 if (kvm_vcpu_read_guest(vcpu
,
10159 gpa
+ i
* sizeof(e
),
10160 &e
, 2 * sizeof(u32
))) {
10161 pr_debug_ratelimited(
10162 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10163 __func__
, i
, gpa
+ i
* sizeof(e
));
10166 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10167 pr_debug_ratelimited(
10168 "%s check failed (%u, 0x%x, 0x%x)\n",
10169 __func__
, i
, e
.index
, e
.reserved
);
10172 msr_info
.host_initiated
= false;
10173 msr_info
.index
= e
.index
;
10174 if (kvm_get_msr(vcpu
, &msr_info
)) {
10175 pr_debug_ratelimited(
10176 "%s cannot read MSR (%u, 0x%x)\n",
10177 __func__
, i
, e
.index
);
10180 if (kvm_vcpu_write_guest(vcpu
,
10181 gpa
+ i
* sizeof(e
) +
10182 offsetof(struct vmx_msr_entry
, value
),
10183 &msr_info
.data
, sizeof(msr_info
.data
))) {
10184 pr_debug_ratelimited(
10185 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10186 __func__
, i
, e
.index
, msr_info
.data
);
10193 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10195 unsigned long invalid_mask
;
10197 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10198 return (val
& invalid_mask
) == 0;
10202 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10203 * emulating VM entry into a guest with EPT enabled.
10204 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10205 * is assigned to entry_failure_code on failure.
10207 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10208 u32
*entry_failure_code
)
10210 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10211 if (!nested_cr3_valid(vcpu
, cr3
)) {
10212 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10217 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10218 * must not be dereferenced.
10220 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10222 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10223 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10228 vcpu
->arch
.cr3
= cr3
;
10229 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10232 kvm_mmu_reset_context(vcpu
);
10237 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10238 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10239 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10240 * guest in a way that will both be appropriate to L1's requests, and our
10241 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10242 * function also has additional necessary side-effects, like setting various
10243 * vcpu->arch fields.
10244 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10245 * is assigned to entry_failure_code on failure.
10247 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10248 bool from_vmentry
, u32
*entry_failure_code
)
10250 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10251 u32 exec_control
, vmcs12_exec_ctrl
;
10253 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10254 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10255 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10256 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10257 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10258 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10259 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10260 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10261 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10262 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10263 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10264 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10265 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10266 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10267 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10268 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10269 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10270 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10271 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10272 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10273 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10274 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10275 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10276 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10277 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10278 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10279 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10280 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10281 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10282 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10283 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10284 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10285 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10286 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10287 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10288 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10290 if (from_vmentry
&&
10291 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10292 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10293 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10295 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10296 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10298 if (from_vmentry
) {
10299 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10300 vmcs12
->vm_entry_intr_info_field
);
10301 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10302 vmcs12
->vm_entry_exception_error_code
);
10303 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10304 vmcs12
->vm_entry_instruction_len
);
10305 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10306 vmcs12
->guest_interruptibility_info
);
10307 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10308 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10310 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10312 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10313 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10314 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10315 vmcs12
->guest_pending_dbg_exceptions
);
10316 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10317 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10319 if (nested_cpu_has_xsaves(vmcs12
))
10320 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10321 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10323 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10325 /* Preemption timer setting is only taken from vmcs01. */
10326 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10327 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10328 if (vmx
->hv_deadline_tsc
== -1)
10329 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10331 /* Posted interrupts setting is only taken from vmcs12. */
10332 if (nested_cpu_has_posted_intr(vmcs12
)) {
10333 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10334 vmx
->nested
.pi_pending
= false;
10335 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10337 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10340 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10342 vmx
->nested
.preemption_timer_expired
= false;
10343 if (nested_cpu_has_preemption_timer(vmcs12
))
10344 vmx_start_preemption_timer(vcpu
);
10347 * Whether page-faults are trapped is determined by a combination of
10348 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10349 * If enable_ept, L0 doesn't care about page faults and we should
10350 * set all of these to L1's desires. However, if !enable_ept, L0 does
10351 * care about (at least some) page faults, and because it is not easy
10352 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10353 * to exit on each and every L2 page fault. This is done by setting
10354 * MASK=MATCH=0 and (see below) EB.PF=1.
10355 * Note that below we don't need special code to set EB.PF beyond the
10356 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10357 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10358 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10360 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10361 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10362 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10363 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10365 if (cpu_has_secondary_exec_ctrls()) {
10366 exec_control
= vmx_secondary_exec_control(vmx
);
10368 /* Take the following fields only from vmcs12 */
10369 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10370 SECONDARY_EXEC_ENABLE_INVPCID
|
10371 SECONDARY_EXEC_RDTSCP
|
10372 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10373 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10374 SECONDARY_EXEC_ENABLE_VMFUNC
);
10375 if (nested_cpu_has(vmcs12
,
10376 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10377 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10378 ~SECONDARY_EXEC_ENABLE_PML
;
10379 exec_control
|= vmcs12_exec_ctrl
;
10382 /* All VMFUNCs are currently emulated through L0 vmexits. */
10383 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10384 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10386 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10387 vmcs_write64(EOI_EXIT_BITMAP0
,
10388 vmcs12
->eoi_exit_bitmap0
);
10389 vmcs_write64(EOI_EXIT_BITMAP1
,
10390 vmcs12
->eoi_exit_bitmap1
);
10391 vmcs_write64(EOI_EXIT_BITMAP2
,
10392 vmcs12
->eoi_exit_bitmap2
);
10393 vmcs_write64(EOI_EXIT_BITMAP3
,
10394 vmcs12
->eoi_exit_bitmap3
);
10395 vmcs_write16(GUEST_INTR_STATUS
,
10396 vmcs12
->guest_intr_status
);
10400 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10401 * nested_get_vmcs12_pages will either fix it up or
10402 * remove the VM execution control.
10404 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10405 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10407 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10412 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10413 * Some constant fields are set here by vmx_set_constant_host_state().
10414 * Other fields are different per CPU, and will be set later when
10415 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10417 vmx_set_constant_host_state(vmx
);
10420 * Set the MSR load/store lists to match L0's settings.
10422 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10423 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10424 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10425 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10426 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10429 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10430 * entry, but only if the current (host) sp changed from the value
10431 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10432 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10433 * here we just force the write to happen on entry.
10437 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10438 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10439 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10440 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10441 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10444 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10445 * nested_get_vmcs12_pages can't fix it up, the illegal value
10446 * will result in a VM entry failure.
10448 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10449 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10450 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10454 * Merging of IO bitmap not currently supported.
10455 * Rather, exit every time.
10457 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10458 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10462 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10463 * bitwise-or of what L1 wants to trap for L2, and what we want to
10464 * trap. Note that CR0.TS also needs updating - we do this later.
10466 update_exception_bitmap(vcpu
);
10467 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10468 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10470 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10471 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10472 * bits are further modified by vmx_set_efer() below.
10474 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10476 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10477 * emulated by vmx_set_efer(), below.
10479 vm_entry_controls_init(vmx
,
10480 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10481 ~VM_ENTRY_IA32E_MODE
) |
10482 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10484 if (from_vmentry
&&
10485 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10486 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10487 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10488 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10489 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10492 set_cr4_guest_host_mask(vmx
);
10494 if (from_vmentry
&&
10495 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10496 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10498 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10499 vmcs_write64(TSC_OFFSET
,
10500 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10502 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10503 if (kvm_has_tsc_control
)
10504 decache_tsc_multiplier(vmx
);
10508 * There is no direct mapping between vpid02 and vpid12, the
10509 * vpid02 is per-vCPU for L0 and reused while the value of
10510 * vpid12 is changed w/ one invvpid during nested vmentry.
10511 * The vpid12 is allocated by L1 for L2, so it will not
10512 * influence global bitmap(for vpid01 and vpid02 allocation)
10513 * even if spawn a lot of nested vCPUs.
10515 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10516 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10517 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10518 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10519 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10522 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10523 vmx_flush_tlb(vcpu
);
10530 * Conceptually we want to copy the PML address and index from
10531 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10532 * since we always flush the log on each vmexit, this happens
10533 * to be equivalent to simply resetting the fields in vmcs02.
10535 ASSERT(vmx
->pml_pg
);
10536 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10537 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10540 if (nested_cpu_has_ept(vmcs12
)) {
10541 if (nested_ept_init_mmu_context(vcpu
)) {
10542 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10545 } else if (nested_cpu_has2(vmcs12
,
10546 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10547 vmx_flush_tlb_ept_only(vcpu
);
10551 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10552 * bits which we consider mandatory enabled.
10553 * The CR0_READ_SHADOW is what L2 should have expected to read given
10554 * the specifications by L1; It's not enough to take
10555 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10556 * have more bits than L1 expected.
10558 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10559 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10561 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10562 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10564 if (from_vmentry
&&
10565 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10566 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10567 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10568 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10570 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10571 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10572 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10574 /* Shadow page tables on either EPT or shadow page tables. */
10575 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10576 entry_failure_code
))
10580 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10583 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10586 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10587 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10588 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10589 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10592 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10593 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10597 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10601 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10602 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10603 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10605 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10606 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10608 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10609 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10611 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10612 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10614 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10615 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10617 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10618 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10620 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10621 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10622 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10623 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10624 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10625 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10626 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10627 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10628 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10629 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10630 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10631 vmx
->nested
.nested_vmx_exit_ctls_low
,
10632 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10633 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10634 vmx
->nested
.nested_vmx_entry_ctls_low
,
10635 vmx
->nested
.nested_vmx_entry_ctls_high
))
10636 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10638 if (nested_cpu_has_vmfunc(vmcs12
)) {
10639 if (vmcs12
->vm_function_control
&
10640 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10641 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10643 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10644 if (!nested_cpu_has_ept(vmcs12
) ||
10645 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10646 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10650 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10651 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10653 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10654 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10655 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10656 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10661 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10666 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10668 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10669 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10672 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10673 vmcs12
->vmcs_link_pointer
!= -1ull) {
10674 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10679 * If the load IA32_EFER VM-entry control is 1, the following checks
10680 * are performed on the field for the IA32_EFER MSR:
10681 * - Bits reserved in the IA32_EFER MSR must be 0.
10682 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10683 * the IA-32e mode guest VM-exit control. It must also be identical
10684 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10687 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10688 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10689 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10690 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10691 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10692 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10693 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10698 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10699 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10700 * the values of the LMA and LME bits in the field must each be that of
10701 * the host address-space size VM-exit control.
10703 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10704 ia32e
= (vmcs12
->vm_exit_controls
&
10705 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10706 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10707 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10708 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10715 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10718 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10719 struct loaded_vmcs
*vmcs02
;
10723 vmcs02
= nested_get_current_vmcs02(vmx
);
10727 enter_guest_mode(vcpu
);
10729 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10730 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10732 vmx_switch_vmcs(vcpu
, vmcs02
);
10733 vmx_segment_cache_clear(vmx
);
10735 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10736 leave_guest_mode(vcpu
);
10737 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10738 nested_vmx_entry_failure(vcpu
, vmcs12
,
10739 EXIT_REASON_INVALID_STATE
, exit_qual
);
10743 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10745 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10746 vmcs12
->vm_entry_msr_load_addr
,
10747 vmcs12
->vm_entry_msr_load_count
);
10748 if (msr_entry_idx
) {
10749 leave_guest_mode(vcpu
);
10750 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10751 nested_vmx_entry_failure(vcpu
, vmcs12
,
10752 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10757 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10758 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10759 * returned as far as L1 is concerned. It will only return (and set
10760 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10766 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10767 * for running an L2 nested guest.
10769 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10771 struct vmcs12
*vmcs12
;
10772 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10773 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10777 if (!nested_vmx_check_permission(vcpu
))
10780 if (!nested_vmx_check_vmcs12(vcpu
))
10783 vmcs12
= get_vmcs12(vcpu
);
10785 if (enable_shadow_vmcs
)
10786 copy_shadow_to_vmcs12(vmx
);
10789 * The nested entry process starts with enforcing various prerequisites
10790 * on vmcs12 as required by the Intel SDM, and act appropriately when
10791 * they fail: As the SDM explains, some conditions should cause the
10792 * instruction to fail, while others will cause the instruction to seem
10793 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10794 * To speed up the normal (success) code path, we should avoid checking
10795 * for misconfigurations which will anyway be caught by the processor
10796 * when using the merged vmcs02.
10798 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10799 nested_vmx_failValid(vcpu
,
10800 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10804 if (vmcs12
->launch_state
== launch
) {
10805 nested_vmx_failValid(vcpu
,
10806 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10807 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10811 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10813 nested_vmx_failValid(vcpu
, ret
);
10818 * After this point, the trap flag no longer triggers a singlestep trap
10819 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10820 * This is not 100% correct; for performance reasons, we delegate most
10821 * of the checks on host state to the processor. If those fail,
10822 * the singlestep trap is missed.
10824 skip_emulated_instruction(vcpu
);
10826 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10828 nested_vmx_entry_failure(vcpu
, vmcs12
,
10829 EXIT_REASON_INVALID_STATE
, exit_qual
);
10834 * We're finally done with prerequisite checking, and can start with
10835 * the nested entry.
10838 ret
= enter_vmx_non_root_mode(vcpu
, true);
10842 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10843 return kvm_vcpu_halt(vcpu
);
10845 vmx
->nested
.nested_run_pending
= 1;
10850 return kvm_skip_emulated_instruction(vcpu
);
10854 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10855 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10856 * This function returns the new value we should put in vmcs12.guest_cr0.
10857 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10858 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10859 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10860 * didn't trap the bit, because if L1 did, so would L0).
10861 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10862 * been modified by L2, and L1 knows it. So just leave the old value of
10863 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10864 * isn't relevant, because if L0 traps this bit it can set it to anything.
10865 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10866 * changed these bits, and therefore they need to be updated, but L0
10867 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10868 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10870 static inline unsigned long
10871 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10874 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10875 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10876 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10877 vcpu
->arch
.cr0_guest_owned_bits
));
10880 static inline unsigned long
10881 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10884 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10885 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10886 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10887 vcpu
->arch
.cr4_guest_owned_bits
));
10890 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10891 struct vmcs12
*vmcs12
)
10896 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10897 nr
= vcpu
->arch
.exception
.nr
;
10898 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10900 if (kvm_exception_is_soft(nr
)) {
10901 vmcs12
->vm_exit_instruction_len
=
10902 vcpu
->arch
.event_exit_inst_len
;
10903 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10905 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10907 if (vcpu
->arch
.exception
.has_error_code
) {
10908 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10909 vmcs12
->idt_vectoring_error_code
=
10910 vcpu
->arch
.exception
.error_code
;
10913 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10914 } else if (vcpu
->arch
.nmi_injected
) {
10915 vmcs12
->idt_vectoring_info_field
=
10916 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10917 } else if (vcpu
->arch
.interrupt
.pending
) {
10918 nr
= vcpu
->arch
.interrupt
.nr
;
10919 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10921 if (vcpu
->arch
.interrupt
.soft
) {
10922 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10923 vmcs12
->vm_entry_instruction_len
=
10924 vcpu
->arch
.event_exit_inst_len
;
10926 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10928 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10932 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10934 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10936 if (vcpu
->arch
.exception
.pending
||
10937 vcpu
->arch
.nmi_injected
||
10938 vcpu
->arch
.interrupt
.pending
)
10941 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10942 vmx
->nested
.preemption_timer_expired
) {
10943 if (vmx
->nested
.nested_run_pending
)
10945 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10949 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10950 if (vmx
->nested
.nested_run_pending
)
10952 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10953 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10954 INTR_INFO_VALID_MASK
, 0);
10956 * The NMI-triggered VM exit counts as injection:
10957 * clear this one and block further NMIs.
10959 vcpu
->arch
.nmi_pending
= 0;
10960 vmx_set_nmi_mask(vcpu
, true);
10964 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10965 nested_exit_on_intr(vcpu
)) {
10966 if (vmx
->nested
.nested_run_pending
)
10968 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10972 vmx_complete_nested_posted_interrupt(vcpu
);
10976 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10978 ktime_t remaining
=
10979 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10982 if (ktime_to_ns(remaining
) <= 0)
10985 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10986 do_div(value
, 1000000);
10987 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10991 * Update the guest state fields of vmcs12 to reflect changes that
10992 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10993 * VM-entry controls is also updated, since this is really a guest
10996 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10998 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10999 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11001 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11002 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11003 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11005 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11006 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11007 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11008 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11009 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11010 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11011 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11012 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11013 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11014 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11015 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11016 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11017 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11018 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11019 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11020 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11021 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11022 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11023 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11024 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11025 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11026 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11027 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11028 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11029 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11030 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11031 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11032 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11033 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11034 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11035 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11036 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11037 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11038 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11039 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11040 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11042 vmcs12
->guest_interruptibility_info
=
11043 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11044 vmcs12
->guest_pending_dbg_exceptions
=
11045 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11046 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11047 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11049 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11051 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11052 if (vmcs12
->vm_exit_controls
&
11053 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11054 vmcs12
->vmx_preemption_timer_value
=
11055 vmx_get_preemption_timer_value(vcpu
);
11056 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11060 * In some cases (usually, nested EPT), L2 is allowed to change its
11061 * own CR3 without exiting. If it has changed it, we must keep it.
11062 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11063 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11065 * Additionally, restore L2's PDPTR to vmcs12.
11068 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11069 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11070 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11071 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11072 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11075 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11077 if (nested_cpu_has_vid(vmcs12
))
11078 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11080 vmcs12
->vm_entry_controls
=
11081 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11082 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11084 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11085 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11086 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11089 /* TODO: These cannot have changed unless we have MSR bitmaps and
11090 * the relevant bit asks not to trap the change */
11091 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11092 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11093 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11094 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11095 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11096 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11097 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11098 if (kvm_mpx_supported())
11099 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11103 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11104 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11105 * and this function updates it to reflect the changes to the guest state while
11106 * L2 was running (and perhaps made some exits which were handled directly by L0
11107 * without going back to L1), and to reflect the exit reason.
11108 * Note that we do not have to copy here all VMCS fields, just those that
11109 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11110 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11111 * which already writes to vmcs12 directly.
11113 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11114 u32 exit_reason
, u32 exit_intr_info
,
11115 unsigned long exit_qualification
)
11117 /* update guest state fields: */
11118 sync_vmcs12(vcpu
, vmcs12
);
11120 /* update exit information fields: */
11122 vmcs12
->vm_exit_reason
= exit_reason
;
11123 vmcs12
->exit_qualification
= exit_qualification
;
11124 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11126 vmcs12
->idt_vectoring_info_field
= 0;
11127 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11128 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11130 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11131 vmcs12
->launch_state
= 1;
11133 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11134 * instead of reading the real value. */
11135 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11138 * Transfer the event that L0 or L1 may wanted to inject into
11139 * L2 to IDT_VECTORING_INFO_FIELD.
11141 vmcs12_save_pending_event(vcpu
, vmcs12
);
11145 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11146 * preserved above and would only end up incorrectly in L1.
11148 vcpu
->arch
.nmi_injected
= false;
11149 kvm_clear_exception_queue(vcpu
);
11150 kvm_clear_interrupt_queue(vcpu
);
11154 * A part of what we need to when the nested L2 guest exits and we want to
11155 * run its L1 parent, is to reset L1's guest state to the host state specified
11157 * This function is to be called not only on normal nested exit, but also on
11158 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11159 * Failures During or After Loading Guest State").
11160 * This function should be called when the active VMCS is L1's (vmcs01).
11162 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11163 struct vmcs12
*vmcs12
)
11165 struct kvm_segment seg
;
11166 u32 entry_failure_code
;
11168 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11169 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11170 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11171 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11173 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11174 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11176 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11177 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11178 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11180 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11181 * actually changed, because vmx_set_cr0 refers to efer set above.
11183 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11184 * (KVM doesn't change it);
11186 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11187 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11189 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11190 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11191 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
11193 nested_ept_uninit_mmu_context(vcpu
);
11196 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11197 * couldn't have changed.
11199 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11200 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11203 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11207 * Trivially support vpid by letting L2s share their parent
11208 * L1's vpid. TODO: move to a more elaborate solution, giving
11209 * each L2 its own vpid and exposing the vpid feature to L1.
11211 vmx_flush_tlb(vcpu
);
11213 /* Restore posted intr vector. */
11214 if (nested_cpu_has_posted_intr(vmcs12
))
11215 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11217 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11218 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11219 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11220 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11221 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11223 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11224 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11225 vmcs_write64(GUEST_BNDCFGS
, 0);
11227 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11228 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11229 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11231 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11232 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11233 vmcs12
->host_ia32_perf_global_ctrl
);
11235 /* Set L1 segment info according to Intel SDM
11236 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11237 seg
= (struct kvm_segment
) {
11239 .limit
= 0xFFFFFFFF,
11240 .selector
= vmcs12
->host_cs_selector
,
11246 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11250 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11251 seg
= (struct kvm_segment
) {
11253 .limit
= 0xFFFFFFFF,
11260 seg
.selector
= vmcs12
->host_ds_selector
;
11261 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11262 seg
.selector
= vmcs12
->host_es_selector
;
11263 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11264 seg
.selector
= vmcs12
->host_ss_selector
;
11265 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11266 seg
.selector
= vmcs12
->host_fs_selector
;
11267 seg
.base
= vmcs12
->host_fs_base
;
11268 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11269 seg
.selector
= vmcs12
->host_gs_selector
;
11270 seg
.base
= vmcs12
->host_gs_base
;
11271 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11272 seg
= (struct kvm_segment
) {
11273 .base
= vmcs12
->host_tr_base
,
11275 .selector
= vmcs12
->host_tr_selector
,
11279 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11281 kvm_set_dr(vcpu
, 7, 0x400);
11282 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11284 if (cpu_has_vmx_msr_bitmap())
11285 vmx_set_msr_bitmap(vcpu
);
11287 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11288 vmcs12
->vm_exit_msr_load_count
))
11289 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11293 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11294 * and modify vmcs12 to make it see what it would expect to see there if
11295 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11297 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11298 u32 exit_intr_info
,
11299 unsigned long exit_qualification
)
11301 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11302 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11303 u32 vm_inst_error
= 0;
11305 /* trying to cancel vmlaunch/vmresume is a bug */
11306 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11308 leave_guest_mode(vcpu
);
11309 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11310 exit_qualification
);
11312 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11313 vmcs12
->vm_exit_msr_store_count
))
11314 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11316 if (unlikely(vmx
->fail
))
11317 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11319 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11322 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11323 * the VM-exit interrupt information (valid interrupt) is always set to
11324 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11325 * kvm_cpu_has_interrupt(). See the commit message for details.
11327 if (nested_exit_intr_ack_set(vcpu
) &&
11328 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11329 kvm_cpu_has_interrupt(vcpu
)) {
11330 int irq
= kvm_cpu_get_interrupt(vcpu
);
11332 vmcs12
->vm_exit_intr_info
= irq
|
11333 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11336 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11337 vmcs12
->exit_qualification
,
11338 vmcs12
->idt_vectoring_info_field
,
11339 vmcs12
->vm_exit_intr_info
,
11340 vmcs12
->vm_exit_intr_error_code
,
11343 vm_entry_controls_reset_shadow(vmx
);
11344 vm_exit_controls_reset_shadow(vmx
);
11345 vmx_segment_cache_clear(vmx
);
11347 /* if no vmcs02 cache requested, remove the one we used */
11348 if (VMCS02_POOL_SIZE
== 0)
11349 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11351 load_vmcs12_host_state(vcpu
, vmcs12
);
11353 /* Update any VMCS fields that might have changed while L2 ran */
11354 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11355 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11356 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11357 if (vmx
->hv_deadline_tsc
== -1)
11358 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11359 PIN_BASED_VMX_PREEMPTION_TIMER
);
11361 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11362 PIN_BASED_VMX_PREEMPTION_TIMER
);
11363 if (kvm_has_tsc_control
)
11364 decache_tsc_multiplier(vmx
);
11366 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11367 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11368 vmx_set_virtual_x2apic_mode(vcpu
,
11369 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11370 } else if (!nested_cpu_has_ept(vmcs12
) &&
11371 nested_cpu_has2(vmcs12
,
11372 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11373 vmx_flush_tlb_ept_only(vcpu
);
11376 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11379 /* Unpin physical memory we referred to in vmcs02 */
11380 if (vmx
->nested
.apic_access_page
) {
11381 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11382 vmx
->nested
.apic_access_page
= NULL
;
11384 if (vmx
->nested
.virtual_apic_page
) {
11385 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11386 vmx
->nested
.virtual_apic_page
= NULL
;
11388 if (vmx
->nested
.pi_desc_page
) {
11389 kunmap(vmx
->nested
.pi_desc_page
);
11390 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11391 vmx
->nested
.pi_desc_page
= NULL
;
11392 vmx
->nested
.pi_desc
= NULL
;
11396 * We are now running in L2, mmu_notifier will force to reload the
11397 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11399 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11402 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11403 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11404 * success or failure flag accordingly.
11406 if (unlikely(vmx
->fail
)) {
11408 nested_vmx_failValid(vcpu
, vm_inst_error
);
11410 nested_vmx_succeed(vcpu
);
11411 if (enable_shadow_vmcs
)
11412 vmx
->nested
.sync_shadow_vmcs
= true;
11414 /* in case we halted in L2 */
11415 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11419 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11421 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11423 if (is_guest_mode(vcpu
)) {
11424 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11425 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11427 free_nested(to_vmx(vcpu
));
11431 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11432 * 23.7 "VM-entry failures during or after loading guest state" (this also
11433 * lists the acceptable exit-reason and exit-qualification parameters).
11434 * It should only be called before L2 actually succeeded to run, and when
11435 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11437 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11438 struct vmcs12
*vmcs12
,
11439 u32 reason
, unsigned long qualification
)
11441 load_vmcs12_host_state(vcpu
, vmcs12
);
11442 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11443 vmcs12
->exit_qualification
= qualification
;
11444 nested_vmx_succeed(vcpu
);
11445 if (enable_shadow_vmcs
)
11446 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11449 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11450 struct x86_instruction_info
*info
,
11451 enum x86_intercept_stage stage
)
11453 return X86EMUL_CONTINUE
;
11456 #ifdef CONFIG_X86_64
11457 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11458 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11459 u64 divisor
, u64
*result
)
11461 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11463 /* To avoid the overflow on divq */
11464 if (high
>= divisor
)
11467 /* Low hold the result, high hold rem which is discarded */
11468 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11469 "rm" (divisor
), "0" (low
), "1" (high
));
11475 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11477 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11478 u64 tscl
= rdtsc();
11479 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11480 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11482 /* Convert to host delta tsc if tsc scaling is enabled */
11483 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11484 u64_shl_div_u64(delta_tsc
,
11485 kvm_tsc_scaling_ratio_frac_bits
,
11486 vcpu
->arch
.tsc_scaling_ratio
,
11491 * If the delta tsc can't fit in the 32 bit after the multi shift,
11492 * we can't use the preemption timer.
11493 * It's possible that it fits on later vmentries, but checking
11494 * on every vmentry is costly so we just use an hrtimer.
11496 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11499 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11500 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11501 PIN_BASED_VMX_PREEMPTION_TIMER
);
11503 return delta_tsc
== 0;
11506 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11508 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11509 vmx
->hv_deadline_tsc
= -1;
11510 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11511 PIN_BASED_VMX_PREEMPTION_TIMER
);
11515 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11518 shrink_ple_window(vcpu
);
11521 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11522 struct kvm_memory_slot
*slot
)
11524 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11525 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11528 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11529 struct kvm_memory_slot
*slot
)
11531 kvm_mmu_slot_set_dirty(kvm
, slot
);
11534 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11536 kvm_flush_pml_buffers(kvm
);
11539 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11541 struct vmcs12
*vmcs12
;
11542 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11544 struct page
*page
= NULL
;
11547 if (is_guest_mode(vcpu
)) {
11548 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11551 * Check if PML is enabled for the nested guest.
11552 * Whether eptp bit 6 is set is already checked
11553 * as part of A/D emulation.
11555 vmcs12
= get_vmcs12(vcpu
);
11556 if (!nested_cpu_has_pml(vmcs12
))
11559 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11560 vmx
->nested
.pml_full
= true;
11564 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11566 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11567 if (is_error_page(page
))
11570 pml_address
= kmap(page
);
11571 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11573 kvm_release_page_clean(page
);
11579 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11580 struct kvm_memory_slot
*memslot
,
11581 gfn_t offset
, unsigned long mask
)
11583 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11587 * This routine does the following things for vCPU which is going
11588 * to be blocked if VT-d PI is enabled.
11589 * - Store the vCPU to the wakeup list, so when interrupts happen
11590 * we can find the right vCPU to wake up.
11591 * - Change the Posted-interrupt descriptor as below:
11592 * 'NDST' <-- vcpu->pre_pcpu
11593 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11594 * - If 'ON' is set during this process, which means at least one
11595 * interrupt is posted for this vCPU, we cannot block it, in
11596 * this case, return 1, otherwise, return 0.
11599 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11601 unsigned long flags
;
11603 struct pi_desc old
, new;
11604 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11606 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11607 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11608 !kvm_vcpu_apicv_active(vcpu
))
11611 vcpu
->pre_pcpu
= vcpu
->cpu
;
11612 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11613 vcpu
->pre_pcpu
), flags
);
11614 list_add_tail(&vcpu
->blocked_vcpu_list
,
11615 &per_cpu(blocked_vcpu_on_cpu
,
11617 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11618 vcpu
->pre_pcpu
), flags
);
11621 old
.control
= new.control
= pi_desc
->control
;
11624 * We should not block the vCPU if
11625 * an interrupt is posted for it.
11627 if (pi_test_on(pi_desc
) == 1) {
11628 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11629 vcpu
->pre_pcpu
), flags
);
11630 list_del(&vcpu
->blocked_vcpu_list
);
11631 spin_unlock_irqrestore(
11632 &per_cpu(blocked_vcpu_on_cpu_lock
,
11633 vcpu
->pre_pcpu
), flags
);
11634 vcpu
->pre_pcpu
= -1;
11639 WARN((pi_desc
->sn
== 1),
11640 "Warning: SN field of posted-interrupts "
11641 "is set before blocking\n");
11644 * Since vCPU can be preempted during this process,
11645 * vcpu->cpu could be different with pre_pcpu, we
11646 * need to set pre_pcpu as the destination of wakeup
11647 * notification event, then we can find the right vCPU
11648 * to wakeup in wakeup handler if interrupts happen
11649 * when the vCPU is in blocked state.
11651 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11653 if (x2apic_enabled())
11656 new.ndst
= (dest
<< 8) & 0xFF00;
11658 /* set 'NV' to 'wakeup vector' */
11659 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11660 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11661 new.control
) != old
.control
);
11666 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11668 if (pi_pre_block(vcpu
))
11671 if (kvm_lapic_hv_timer_in_use(vcpu
))
11672 kvm_lapic_switch_to_sw_timer(vcpu
);
11677 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11679 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11680 struct pi_desc old
, new;
11682 unsigned long flags
;
11684 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11685 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11686 !kvm_vcpu_apicv_active(vcpu
))
11690 old
.control
= new.control
= pi_desc
->control
;
11692 dest
= cpu_physical_id(vcpu
->cpu
);
11694 if (x2apic_enabled())
11697 new.ndst
= (dest
<< 8) & 0xFF00;
11699 /* Allow posting non-urgent interrupts */
11702 /* set 'NV' to 'notification vector' */
11703 new.nv
= POSTED_INTR_VECTOR
;
11704 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11705 new.control
) != old
.control
);
11707 if(vcpu
->pre_pcpu
!= -1) {
11709 &per_cpu(blocked_vcpu_on_cpu_lock
,
11710 vcpu
->pre_pcpu
), flags
);
11711 list_del(&vcpu
->blocked_vcpu_list
);
11712 spin_unlock_irqrestore(
11713 &per_cpu(blocked_vcpu_on_cpu_lock
,
11714 vcpu
->pre_pcpu
), flags
);
11715 vcpu
->pre_pcpu
= -1;
11719 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11721 if (kvm_x86_ops
->set_hv_timer
)
11722 kvm_lapic_switch_to_hv_timer(vcpu
);
11724 pi_post_block(vcpu
);
11728 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11731 * @host_irq: host irq of the interrupt
11732 * @guest_irq: gsi of the interrupt
11733 * @set: set or unset PI
11734 * returns 0 on success, < 0 on failure
11736 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11737 uint32_t guest_irq
, bool set
)
11739 struct kvm_kernel_irq_routing_entry
*e
;
11740 struct kvm_irq_routing_table
*irq_rt
;
11741 struct kvm_lapic_irq irq
;
11742 struct kvm_vcpu
*vcpu
;
11743 struct vcpu_data vcpu_info
;
11744 int idx
, ret
= -EINVAL
;
11746 if (!kvm_arch_has_assigned_device(kvm
) ||
11747 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11748 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11751 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11752 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11753 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11755 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11756 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11759 * VT-d PI cannot support posting multicast/broadcast
11760 * interrupts to a vCPU, we still use interrupt remapping
11761 * for these kind of interrupts.
11763 * For lowest-priority interrupts, we only support
11764 * those with single CPU as the destination, e.g. user
11765 * configures the interrupts via /proc/irq or uses
11766 * irqbalance to make the interrupts single-CPU.
11768 * We will support full lowest-priority interrupt later.
11771 kvm_set_msi_irq(kvm
, e
, &irq
);
11772 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11774 * Make sure the IRTE is in remapped mode if
11775 * we don't handle it in posted mode.
11777 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11780 "failed to back to remapped mode, irq: %u\n",
11788 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11789 vcpu_info
.vector
= irq
.vector
;
11791 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11792 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11795 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11797 /* suppress notification event before unposting */
11798 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11799 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11800 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11804 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11812 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11816 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11818 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11819 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11820 FEATURE_CONTROL_LMCE
;
11822 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11823 ~FEATURE_CONTROL_LMCE
;
11826 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11827 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11828 .disabled_by_bios
= vmx_disabled_by_bios
,
11829 .hardware_setup
= hardware_setup
,
11830 .hardware_unsetup
= hardware_unsetup
,
11831 .check_processor_compatibility
= vmx_check_processor_compat
,
11832 .hardware_enable
= hardware_enable
,
11833 .hardware_disable
= hardware_disable
,
11834 .cpu_has_accelerated_tpr
= report_flexpriority
,
11835 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11837 .vcpu_create
= vmx_create_vcpu
,
11838 .vcpu_free
= vmx_free_vcpu
,
11839 .vcpu_reset
= vmx_vcpu_reset
,
11841 .prepare_guest_switch
= vmx_save_host_state
,
11842 .vcpu_load
= vmx_vcpu_load
,
11843 .vcpu_put
= vmx_vcpu_put
,
11845 .update_bp_intercept
= update_exception_bitmap
,
11846 .get_msr
= vmx_get_msr
,
11847 .set_msr
= vmx_set_msr
,
11848 .get_segment_base
= vmx_get_segment_base
,
11849 .get_segment
= vmx_get_segment
,
11850 .set_segment
= vmx_set_segment
,
11851 .get_cpl
= vmx_get_cpl
,
11852 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11853 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11854 .decache_cr3
= vmx_decache_cr3
,
11855 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11856 .set_cr0
= vmx_set_cr0
,
11857 .set_cr3
= vmx_set_cr3
,
11858 .set_cr4
= vmx_set_cr4
,
11859 .set_efer
= vmx_set_efer
,
11860 .get_idt
= vmx_get_idt
,
11861 .set_idt
= vmx_set_idt
,
11862 .get_gdt
= vmx_get_gdt
,
11863 .set_gdt
= vmx_set_gdt
,
11864 .get_dr6
= vmx_get_dr6
,
11865 .set_dr6
= vmx_set_dr6
,
11866 .set_dr7
= vmx_set_dr7
,
11867 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11868 .cache_reg
= vmx_cache_reg
,
11869 .get_rflags
= vmx_get_rflags
,
11870 .set_rflags
= vmx_set_rflags
,
11872 .get_pkru
= vmx_get_pkru
,
11874 .tlb_flush
= vmx_flush_tlb
,
11876 .run
= vmx_vcpu_run
,
11877 .handle_exit
= vmx_handle_exit
,
11878 .skip_emulated_instruction
= skip_emulated_instruction
,
11879 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11880 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11881 .patch_hypercall
= vmx_patch_hypercall
,
11882 .set_irq
= vmx_inject_irq
,
11883 .set_nmi
= vmx_inject_nmi
,
11884 .queue_exception
= vmx_queue_exception
,
11885 .cancel_injection
= vmx_cancel_injection
,
11886 .interrupt_allowed
= vmx_interrupt_allowed
,
11887 .nmi_allowed
= vmx_nmi_allowed
,
11888 .get_nmi_mask
= vmx_get_nmi_mask
,
11889 .set_nmi_mask
= vmx_set_nmi_mask
,
11890 .enable_nmi_window
= enable_nmi_window
,
11891 .enable_irq_window
= enable_irq_window
,
11892 .update_cr8_intercept
= update_cr8_intercept
,
11893 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11894 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11895 .get_enable_apicv
= vmx_get_enable_apicv
,
11896 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11897 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11898 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11899 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11900 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11901 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11902 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11904 .set_tss_addr
= vmx_set_tss_addr
,
11905 .get_tdp_level
= get_ept_level
,
11906 .get_mt_mask
= vmx_get_mt_mask
,
11908 .get_exit_info
= vmx_get_exit_info
,
11910 .get_lpage_level
= vmx_get_lpage_level
,
11912 .cpuid_update
= vmx_cpuid_update
,
11914 .rdtscp_supported
= vmx_rdtscp_supported
,
11915 .invpcid_supported
= vmx_invpcid_supported
,
11917 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11919 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11921 .write_tsc_offset
= vmx_write_tsc_offset
,
11923 .set_tdp_cr3
= vmx_set_cr3
,
11925 .check_intercept
= vmx_check_intercept
,
11926 .handle_external_intr
= vmx_handle_external_intr
,
11927 .mpx_supported
= vmx_mpx_supported
,
11928 .xsaves_supported
= vmx_xsaves_supported
,
11930 .check_nested_events
= vmx_check_nested_events
,
11932 .sched_in
= vmx_sched_in
,
11934 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11935 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11936 .flush_log_dirty
= vmx_flush_log_dirty
,
11937 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11938 .write_log_dirty
= vmx_write_pml_buffer
,
11940 .pre_block
= vmx_pre_block
,
11941 .post_block
= vmx_post_block
,
11943 .pmu_ops
= &intel_pmu_ops
,
11945 .update_pi_irte
= vmx_update_pi_irte
,
11947 #ifdef CONFIG_X86_64
11948 .set_hv_timer
= vmx_set_hv_timer
,
11949 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11952 .setup_mce
= vmx_setup_mce
,
11955 static int __init
vmx_init(void)
11957 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11958 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11962 #ifdef CONFIG_KEXEC_CORE
11963 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11964 crash_vmclear_local_loaded_vmcss
);
11970 static void __exit
vmx_exit(void)
11972 #ifdef CONFIG_KEXEC_CORE
11973 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11980 module_init(vmx_init
)
11981 module_exit(vmx_exit
)