2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/microcode.h>
55 #include <asm/spec-ctrl.h>
60 #define __ex(x) __kvm_handle_fault_on_reboot(x)
61 #define __ex_clear(x, reg) \
62 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id
[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
71 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
73 static bool __read_mostly nosmt
;
74 module_param(nosmt
, bool, S_IRUGO
);
76 static bool __read_mostly enable_vpid
= 1;
77 module_param_named(vpid
, enable_vpid
, bool, 0444);
79 static bool __read_mostly enable_vnmi
= 1;
80 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
82 static bool __read_mostly flexpriority_enabled
= 1;
83 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
85 static bool __read_mostly enable_ept
= 1;
86 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
88 static bool __read_mostly enable_unrestricted_guest
= 1;
89 module_param_named(unrestricted_guest
,
90 enable_unrestricted_guest
, bool, S_IRUGO
);
92 static bool __read_mostly enable_ept_ad_bits
= 1;
93 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
95 static bool __read_mostly emulate_invalid_guest_state
= true;
96 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
98 static bool __read_mostly fasteoi
= 1;
99 module_param(fasteoi
, bool, S_IRUGO
);
101 static bool __read_mostly enable_apicv
= 1;
102 module_param(enable_apicv
, bool, S_IRUGO
);
104 static bool __read_mostly enable_shadow_vmcs
= 1;
105 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
107 * If nested=1, nested virtualization is supported, i.e., guests may use
108 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
109 * use VMX instructions.
111 static bool __read_mostly nested
= 0;
112 module_param(nested
, bool, S_IRUGO
);
114 static u64 __read_mostly host_xss
;
116 static bool __read_mostly enable_pml
= 1;
117 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
121 #define MSR_TYPE_RW 3
123 #define MSR_BITMAP_MODE_X2APIC 1
124 #define MSR_BITMAP_MODE_X2APIC_APICV 2
125 #define MSR_BITMAP_MODE_LM 4
127 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
129 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
130 static int __read_mostly cpu_preemption_timer_multi
;
131 static bool __read_mostly enable_preemption_timer
= 1;
133 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
136 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
138 #define KVM_VM_CR0_ALWAYS_ON \
139 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
140 #define KVM_CR4_GUEST_OWNED_BITS \
141 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
142 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
152 * Hyper-V requires all of these, so mark them as supported even though
153 * they are just treated the same as all-context.
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
156 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
157 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
158 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
162 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163 * ple_gap: upper bound on the amount of time between two successive
164 * executions of PAUSE in a loop. Also indicate if ple enabled.
165 * According to test, this time is usually smaller than 128 cycles.
166 * ple_window: upper bound on the amount of time a guest is allowed to execute
167 * in a PAUSE loop. Tests indicate that most spinlocks are held for
168 * less than 2^12 cycles
169 * Time is measured based on a counter that runs at the same rate as the TSC,
170 * refer SDM volume 3b section 21.6.13 & 22.1.3.
172 #define KVM_VMX_DEFAULT_PLE_GAP 128
173 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
174 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
175 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
176 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
177 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
179 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
180 module_param(ple_gap
, int, S_IRUGO
);
182 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
183 module_param(ple_window
, int, S_IRUGO
);
185 /* Default doubles per-vcpu window every exit. */
186 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
187 module_param(ple_window_grow
, int, S_IRUGO
);
189 /* Default resets per-vcpu window every exit to ple_window. */
190 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
191 module_param(ple_window_shrink
, int, S_IRUGO
);
193 /* Default is to compute the maximum so we can never overflow. */
194 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
195 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
196 module_param(ple_window_max
, int, S_IRUGO
);
198 extern const ulong vmx_return
;
200 #define NR_AUTOLOAD_MSRS 8
209 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
210 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
211 * loaded on this CPU (so we can clear them if the CPU goes down).
215 struct vmcs
*shadow_vmcs
;
218 bool nmi_known_unmasked
;
219 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
220 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
221 /* Support for vnmi-less CPUs */
222 int soft_vnmi_blocked
;
224 s64 vnmi_blocked_time
;
225 unsigned long *msr_bitmap
;
226 struct list_head loaded_vmcss_on_cpu_link
;
229 struct shared_msr_entry
{
236 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
237 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
238 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
239 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
240 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
241 * More than one of these structures may exist, if L1 runs multiple L2 guests.
242 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
243 * underlying hardware which will be used to run L2.
244 * This structure is packed to ensure that its layout is identical across
245 * machines (necessary for live migration).
246 * If there are changes in this struct, VMCS12_REVISION must be changed.
248 typedef u64 natural_width
;
249 struct __packed vmcs12
{
250 /* According to the Intel spec, a VMCS region must start with the
251 * following two fields. Then follow implementation-specific data.
256 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
257 u32 padding
[7]; /* room for future expansion */
262 u64 vm_exit_msr_store_addr
;
263 u64 vm_exit_msr_load_addr
;
264 u64 vm_entry_msr_load_addr
;
266 u64 virtual_apic_page_addr
;
267 u64 apic_access_addr
;
268 u64 posted_intr_desc_addr
;
269 u64 vm_function_control
;
271 u64 eoi_exit_bitmap0
;
272 u64 eoi_exit_bitmap1
;
273 u64 eoi_exit_bitmap2
;
274 u64 eoi_exit_bitmap3
;
275 u64 eptp_list_address
;
277 u64 guest_physical_address
;
278 u64 vmcs_link_pointer
;
280 u64 guest_ia32_debugctl
;
283 u64 guest_ia32_perf_global_ctrl
;
291 u64 host_ia32_perf_global_ctrl
;
292 u64 padding64
[8]; /* room for future expansion */
294 * To allow migration of L1 (complete with its L2 guests) between
295 * machines of different natural widths (32 or 64 bit), we cannot have
296 * unsigned long fields with no explict size. We use u64 (aliased
297 * natural_width) instead. Luckily, x86 is little-endian.
299 natural_width cr0_guest_host_mask
;
300 natural_width cr4_guest_host_mask
;
301 natural_width cr0_read_shadow
;
302 natural_width cr4_read_shadow
;
303 natural_width cr3_target_value0
;
304 natural_width cr3_target_value1
;
305 natural_width cr3_target_value2
;
306 natural_width cr3_target_value3
;
307 natural_width exit_qualification
;
308 natural_width guest_linear_address
;
309 natural_width guest_cr0
;
310 natural_width guest_cr3
;
311 natural_width guest_cr4
;
312 natural_width guest_es_base
;
313 natural_width guest_cs_base
;
314 natural_width guest_ss_base
;
315 natural_width guest_ds_base
;
316 natural_width guest_fs_base
;
317 natural_width guest_gs_base
;
318 natural_width guest_ldtr_base
;
319 natural_width guest_tr_base
;
320 natural_width guest_gdtr_base
;
321 natural_width guest_idtr_base
;
322 natural_width guest_dr7
;
323 natural_width guest_rsp
;
324 natural_width guest_rip
;
325 natural_width guest_rflags
;
326 natural_width guest_pending_dbg_exceptions
;
327 natural_width guest_sysenter_esp
;
328 natural_width guest_sysenter_eip
;
329 natural_width host_cr0
;
330 natural_width host_cr3
;
331 natural_width host_cr4
;
332 natural_width host_fs_base
;
333 natural_width host_gs_base
;
334 natural_width host_tr_base
;
335 natural_width host_gdtr_base
;
336 natural_width host_idtr_base
;
337 natural_width host_ia32_sysenter_esp
;
338 natural_width host_ia32_sysenter_eip
;
339 natural_width host_rsp
;
340 natural_width host_rip
;
341 natural_width paddingl
[8]; /* room for future expansion */
342 u32 pin_based_vm_exec_control
;
343 u32 cpu_based_vm_exec_control
;
344 u32 exception_bitmap
;
345 u32 page_fault_error_code_mask
;
346 u32 page_fault_error_code_match
;
347 u32 cr3_target_count
;
348 u32 vm_exit_controls
;
349 u32 vm_exit_msr_store_count
;
350 u32 vm_exit_msr_load_count
;
351 u32 vm_entry_controls
;
352 u32 vm_entry_msr_load_count
;
353 u32 vm_entry_intr_info_field
;
354 u32 vm_entry_exception_error_code
;
355 u32 vm_entry_instruction_len
;
357 u32 secondary_vm_exec_control
;
358 u32 vm_instruction_error
;
360 u32 vm_exit_intr_info
;
361 u32 vm_exit_intr_error_code
;
362 u32 idt_vectoring_info_field
;
363 u32 idt_vectoring_error_code
;
364 u32 vm_exit_instruction_len
;
365 u32 vmx_instruction_info
;
372 u32 guest_ldtr_limit
;
374 u32 guest_gdtr_limit
;
375 u32 guest_idtr_limit
;
376 u32 guest_es_ar_bytes
;
377 u32 guest_cs_ar_bytes
;
378 u32 guest_ss_ar_bytes
;
379 u32 guest_ds_ar_bytes
;
380 u32 guest_fs_ar_bytes
;
381 u32 guest_gs_ar_bytes
;
382 u32 guest_ldtr_ar_bytes
;
383 u32 guest_tr_ar_bytes
;
384 u32 guest_interruptibility_info
;
385 u32 guest_activity_state
;
386 u32 guest_sysenter_cs
;
387 u32 host_ia32_sysenter_cs
;
388 u32 vmx_preemption_timer_value
;
389 u32 padding32
[7]; /* room for future expansion */
390 u16 virtual_processor_id
;
392 u16 guest_es_selector
;
393 u16 guest_cs_selector
;
394 u16 guest_ss_selector
;
395 u16 guest_ds_selector
;
396 u16 guest_fs_selector
;
397 u16 guest_gs_selector
;
398 u16 guest_ldtr_selector
;
399 u16 guest_tr_selector
;
400 u16 guest_intr_status
;
402 u16 host_es_selector
;
403 u16 host_cs_selector
;
404 u16 host_ss_selector
;
405 u16 host_ds_selector
;
406 u16 host_fs_selector
;
407 u16 host_gs_selector
;
408 u16 host_tr_selector
;
412 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
413 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
414 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
416 #define VMCS12_REVISION 0x11e57ed0
419 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
420 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
421 * current implementation, 4K are reserved to avoid future complications.
423 #define VMCS12_SIZE 0x1000
426 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
427 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
430 /* Has the level1 guest done vmxon? */
435 /* The guest-physical address of the current VMCS L1 keeps for L2 */
438 * Cache of the guest's VMCS, existing outside of guest memory.
439 * Loaded from guest memory during VMPTRLD. Flushed to guest
440 * memory during VMCLEAR and VMPTRLD.
442 struct vmcs12
*cached_vmcs12
;
444 * Indicates if the shadow vmcs must be updated with the
445 * data hold by vmcs12
447 bool sync_shadow_vmcs
;
449 bool change_vmcs01_virtual_x2apic_mode
;
450 /* L2 must run next, and mustn't decide to exit to L1. */
451 bool nested_run_pending
;
453 struct loaded_vmcs vmcs02
;
456 * Guest pages referred to in the vmcs02 with host-physical
457 * pointers, so we must keep them pinned while L2 runs.
459 struct page
*apic_access_page
;
460 struct page
*virtual_apic_page
;
461 struct page
*pi_desc_page
;
462 struct pi_desc
*pi_desc
;
466 struct hrtimer preemption_timer
;
467 bool preemption_timer_expired
;
469 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
476 * We only store the "true" versions of the VMX capability MSRs. We
477 * generate the "non-true" versions by setting the must-be-1 bits
478 * according to the SDM.
480 u32 nested_vmx_procbased_ctls_low
;
481 u32 nested_vmx_procbased_ctls_high
;
482 u32 nested_vmx_secondary_ctls_low
;
483 u32 nested_vmx_secondary_ctls_high
;
484 u32 nested_vmx_pinbased_ctls_low
;
485 u32 nested_vmx_pinbased_ctls_high
;
486 u32 nested_vmx_exit_ctls_low
;
487 u32 nested_vmx_exit_ctls_high
;
488 u32 nested_vmx_entry_ctls_low
;
489 u32 nested_vmx_entry_ctls_high
;
490 u32 nested_vmx_misc_low
;
491 u32 nested_vmx_misc_high
;
492 u32 nested_vmx_ept_caps
;
493 u32 nested_vmx_vpid_caps
;
494 u64 nested_vmx_basic
;
495 u64 nested_vmx_cr0_fixed0
;
496 u64 nested_vmx_cr0_fixed1
;
497 u64 nested_vmx_cr4_fixed0
;
498 u64 nested_vmx_cr4_fixed1
;
499 u64 nested_vmx_vmcs_enum
;
500 u64 nested_vmx_vmfunc_controls
;
502 /* SMM related state */
504 /* in VMX operation on SMM entry? */
506 /* in guest mode on SMM entry? */
511 #define POSTED_INTR_ON 0
512 #define POSTED_INTR_SN 1
514 /* Posted-Interrupt Descriptor */
516 u32 pir
[8]; /* Posted interrupt requested */
519 /* bit 256 - Outstanding Notification */
521 /* bit 257 - Suppress Notification */
523 /* bit 271:258 - Reserved */
525 /* bit 279:272 - Notification Vector */
527 /* bit 287:280 - Reserved */
529 /* bit 319:288 - Notification Destination */
537 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
539 return test_and_set_bit(POSTED_INTR_ON
,
540 (unsigned long *)&pi_desc
->control
);
543 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
545 return test_and_clear_bit(POSTED_INTR_ON
,
546 (unsigned long *)&pi_desc
->control
);
549 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
551 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
554 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
556 return clear_bit(POSTED_INTR_SN
,
557 (unsigned long *)&pi_desc
->control
);
560 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
562 return set_bit(POSTED_INTR_SN
,
563 (unsigned long *)&pi_desc
->control
);
566 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
568 clear_bit(POSTED_INTR_ON
,
569 (unsigned long *)&pi_desc
->control
);
572 static inline int pi_test_on(struct pi_desc
*pi_desc
)
574 return test_bit(POSTED_INTR_ON
,
575 (unsigned long *)&pi_desc
->control
);
578 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
580 return test_bit(POSTED_INTR_SN
,
581 (unsigned long *)&pi_desc
->control
);
585 struct kvm_vcpu vcpu
;
586 unsigned long host_rsp
;
590 u32 idt_vectoring_info
;
592 struct shared_msr_entry
*guest_msrs
;
595 unsigned long host_idt_base
;
597 u64 msr_host_kernel_gs_base
;
598 u64 msr_guest_kernel_gs_base
;
601 u64 arch_capabilities
;
604 u32 vm_entry_controls_shadow
;
605 u32 vm_exit_controls_shadow
;
606 u32 secondary_exec_control
;
609 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
610 * non-nested (L1) guest, it always points to vmcs01. For a nested
611 * guest (L2), it points to a different VMCS.
613 struct loaded_vmcs vmcs01
;
614 struct loaded_vmcs
*loaded_vmcs
;
615 bool __launched
; /* temporary, used in vmx_vcpu_run */
616 struct msr_autoload
{
618 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
619 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
623 u16 fs_sel
, gs_sel
, ldt_sel
;
627 int gs_ldt_reload_needed
;
628 int fs_reload_needed
;
629 u64 msr_host_bndcfgs
;
634 struct kvm_segment segs
[8];
637 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
638 struct kvm_save_segment
{
646 bool emulation_required
;
650 /* Posted interrupt descriptor */
651 struct pi_desc pi_desc
;
653 /* Support for a guest hypervisor (nested VMX) */
654 struct nested_vmx nested
;
656 /* Dynamic PLE window. */
658 bool ple_window_dirty
;
660 /* Support for PML */
661 #define PML_ENTITY_NUM 512
664 /* apic deadline value in host tsc */
667 u64 current_tsc_ratio
;
672 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
673 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
674 * in msr_ia32_feature_control_valid_bits.
676 u64 msr_ia32_feature_control
;
677 u64 msr_ia32_feature_control_valid_bits
;
680 enum segment_cache_field
{
689 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
691 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
694 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
696 return &(to_vmx(vcpu
)->pi_desc
);
699 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
700 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
701 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
702 [number##_HIGH] = VMCS12_OFFSET(name)+4
705 static unsigned long shadow_read_only_fields
[] = {
707 * We do NOT shadow fields that are modified when L0
708 * traps and emulates any vmx instruction (e.g. VMPTRLD,
709 * VMXON...) executed by L1.
710 * For example, VM_INSTRUCTION_ERROR is read
711 * by L1 if a vmx instruction fails (part of the error path).
712 * Note the code assumes this logic. If for some reason
713 * we start shadowing these fields then we need to
714 * force a shadow sync when L0 emulates vmx instructions
715 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
716 * by nested_vmx_failValid)
720 VM_EXIT_INSTRUCTION_LEN
,
721 IDT_VECTORING_INFO_FIELD
,
722 IDT_VECTORING_ERROR_CODE
,
723 VM_EXIT_INTR_ERROR_CODE
,
725 GUEST_LINEAR_ADDRESS
,
726 GUEST_PHYSICAL_ADDRESS
728 static int max_shadow_read_only_fields
=
729 ARRAY_SIZE(shadow_read_only_fields
);
731 static unsigned long shadow_read_write_fields
[] = {
738 GUEST_INTERRUPTIBILITY_INFO
,
751 CPU_BASED_VM_EXEC_CONTROL
,
752 VM_ENTRY_EXCEPTION_ERROR_CODE
,
753 VM_ENTRY_INTR_INFO_FIELD
,
754 VM_ENTRY_INSTRUCTION_LEN
,
755 VM_ENTRY_EXCEPTION_ERROR_CODE
,
761 static int max_shadow_read_write_fields
=
762 ARRAY_SIZE(shadow_read_write_fields
);
764 static const unsigned short vmcs_field_to_offset_table
[] = {
765 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
766 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
767 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
768 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
769 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
770 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
771 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
772 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
773 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
774 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
775 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
776 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
777 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
778 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
779 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
780 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
781 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
782 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
783 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
784 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
785 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
786 FIELD64(MSR_BITMAP
, msr_bitmap
),
787 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
788 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
789 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
790 FIELD64(TSC_OFFSET
, tsc_offset
),
791 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
792 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
793 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
794 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
795 FIELD64(EPT_POINTER
, ept_pointer
),
796 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
797 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
798 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
799 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
800 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
801 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
802 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
803 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
804 FIELD64(PML_ADDRESS
, pml_address
),
805 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
806 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
807 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
808 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
809 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
810 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
811 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
812 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
813 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
814 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
815 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
816 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
817 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
818 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
819 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
820 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
821 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
822 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
823 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
824 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
825 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
826 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
827 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
828 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
829 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
830 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
831 FIELD(TPR_THRESHOLD
, tpr_threshold
),
832 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
833 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
834 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
835 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
836 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
837 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
838 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
839 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
840 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
841 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
842 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
843 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
844 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
845 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
846 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
847 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
848 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
849 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
850 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
851 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
852 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
853 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
854 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
855 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
856 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
857 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
858 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
859 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
860 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
861 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
862 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
863 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
864 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
865 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
866 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
867 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
868 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
869 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
870 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
871 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
872 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
873 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
874 FIELD(GUEST_CR0
, guest_cr0
),
875 FIELD(GUEST_CR3
, guest_cr3
),
876 FIELD(GUEST_CR4
, guest_cr4
),
877 FIELD(GUEST_ES_BASE
, guest_es_base
),
878 FIELD(GUEST_CS_BASE
, guest_cs_base
),
879 FIELD(GUEST_SS_BASE
, guest_ss_base
),
880 FIELD(GUEST_DS_BASE
, guest_ds_base
),
881 FIELD(GUEST_FS_BASE
, guest_fs_base
),
882 FIELD(GUEST_GS_BASE
, guest_gs_base
),
883 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
884 FIELD(GUEST_TR_BASE
, guest_tr_base
),
885 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
886 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
887 FIELD(GUEST_DR7
, guest_dr7
),
888 FIELD(GUEST_RSP
, guest_rsp
),
889 FIELD(GUEST_RIP
, guest_rip
),
890 FIELD(GUEST_RFLAGS
, guest_rflags
),
891 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
892 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
893 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
894 FIELD(HOST_CR0
, host_cr0
),
895 FIELD(HOST_CR3
, host_cr3
),
896 FIELD(HOST_CR4
, host_cr4
),
897 FIELD(HOST_FS_BASE
, host_fs_base
),
898 FIELD(HOST_GS_BASE
, host_gs_base
),
899 FIELD(HOST_TR_BASE
, host_tr_base
),
900 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
901 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
902 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
903 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
904 FIELD(HOST_RSP
, host_rsp
),
905 FIELD(HOST_RIP
, host_rip
),
908 static inline short vmcs_field_to_offset(unsigned long field
)
910 const size_t size
= ARRAY_SIZE(vmcs_field_to_offset_table
);
911 unsigned short offset
;
913 BUILD_BUG_ON(size
> SHRT_MAX
);
917 field
= array_index_nospec(field
, size
);
918 offset
= vmcs_field_to_offset_table
[field
];
924 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
926 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
929 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
930 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
931 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
932 static bool vmx_xsaves_supported(void);
933 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
934 struct kvm_segment
*var
, int seg
);
935 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
936 struct kvm_segment
*var
, int seg
);
937 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
938 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
939 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
940 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
941 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
942 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
944 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
);
945 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
948 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
949 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
951 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
952 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
954 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
957 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
958 * can find which vCPU should be waken up.
960 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
961 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
971 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
973 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
974 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
975 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
976 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
978 static bool cpu_has_load_ia32_efer
;
979 static bool cpu_has_load_perf_global_ctrl
;
981 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
982 static DEFINE_SPINLOCK(vmx_vpid_lock
);
984 static struct vmcs_config
{
989 u32 pin_based_exec_ctrl
;
990 u32 cpu_based_exec_ctrl
;
991 u32 cpu_based_2nd_exec_ctrl
;
996 static struct vmx_capability
{
1001 #define VMX_SEGMENT_FIELD(seg) \
1002 [VCPU_SREG_##seg] = { \
1003 .selector = GUEST_##seg##_SELECTOR, \
1004 .base = GUEST_##seg##_BASE, \
1005 .limit = GUEST_##seg##_LIMIT, \
1006 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1009 static const struct kvm_vmx_segment_field
{
1014 } kvm_vmx_segment_fields
[] = {
1015 VMX_SEGMENT_FIELD(CS
),
1016 VMX_SEGMENT_FIELD(DS
),
1017 VMX_SEGMENT_FIELD(ES
),
1018 VMX_SEGMENT_FIELD(FS
),
1019 VMX_SEGMENT_FIELD(GS
),
1020 VMX_SEGMENT_FIELD(SS
),
1021 VMX_SEGMENT_FIELD(TR
),
1022 VMX_SEGMENT_FIELD(LDTR
),
1025 static u64 host_efer
;
1027 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1030 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1031 * away by decrementing the array size.
1033 static const u32 vmx_msr_index
[] = {
1034 #ifdef CONFIG_X86_64
1035 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1037 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1040 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1042 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1043 INTR_INFO_VALID_MASK
)) ==
1044 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1047 static inline bool is_debug(u32 intr_info
)
1049 return is_exception_n(intr_info
, DB_VECTOR
);
1052 static inline bool is_breakpoint(u32 intr_info
)
1054 return is_exception_n(intr_info
, BP_VECTOR
);
1057 static inline bool is_page_fault(u32 intr_info
)
1059 return is_exception_n(intr_info
, PF_VECTOR
);
1062 static inline bool is_no_device(u32 intr_info
)
1064 return is_exception_n(intr_info
, NM_VECTOR
);
1067 static inline bool is_invalid_opcode(u32 intr_info
)
1069 return is_exception_n(intr_info
, UD_VECTOR
);
1072 static inline bool is_external_interrupt(u32 intr_info
)
1074 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1075 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1078 static inline bool is_machine_check(u32 intr_info
)
1080 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1081 INTR_INFO_VALID_MASK
)) ==
1082 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1085 /* Undocumented: icebp/int1 */
1086 static inline bool is_icebp(u32 intr_info
)
1088 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1089 == (INTR_TYPE_PRIV_SW_EXCEPTION
| INTR_INFO_VALID_MASK
);
1092 static inline bool cpu_has_vmx_msr_bitmap(void)
1094 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1097 static inline bool cpu_has_vmx_tpr_shadow(void)
1099 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1102 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1104 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1107 static inline bool cpu_has_secondary_exec_ctrls(void)
1109 return vmcs_config
.cpu_based_exec_ctrl
&
1110 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1113 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1115 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1116 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1119 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1121 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1122 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1125 static inline bool cpu_has_vmx_apic_register_virt(void)
1127 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1128 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1131 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1133 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1134 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1138 * Comment's format: document - errata name - stepping - processor name.
1140 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1142 static u32 vmx_preemption_cpu_tfms
[] = {
1143 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1145 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1146 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1147 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1149 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1151 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1152 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1154 * 320767.pdf - AAP86 - B1 -
1155 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1158 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1160 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1162 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1164 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1165 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1166 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1170 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1172 u32 eax
= cpuid_eax(0x00000001), i
;
1174 /* Clear the reserved bits */
1175 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1176 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1177 if (eax
== vmx_preemption_cpu_tfms
[i
])
1183 static inline bool cpu_has_vmx_preemption_timer(void)
1185 return vmcs_config
.pin_based_exec_ctrl
&
1186 PIN_BASED_VMX_PREEMPTION_TIMER
;
1189 static inline bool cpu_has_vmx_posted_intr(void)
1191 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1192 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1195 static inline bool cpu_has_vmx_apicv(void)
1197 return cpu_has_vmx_apic_register_virt() &&
1198 cpu_has_vmx_virtual_intr_delivery() &&
1199 cpu_has_vmx_posted_intr();
1202 static inline bool cpu_has_vmx_flexpriority(void)
1204 return cpu_has_vmx_tpr_shadow() &&
1205 cpu_has_vmx_virtualize_apic_accesses();
1208 static inline bool cpu_has_vmx_ept_execute_only(void)
1210 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1213 static inline bool cpu_has_vmx_ept_2m_page(void)
1215 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1218 static inline bool cpu_has_vmx_ept_1g_page(void)
1220 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1223 static inline bool cpu_has_vmx_ept_4levels(void)
1225 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1228 static inline bool cpu_has_vmx_ept_mt_wb(void)
1230 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1233 static inline bool cpu_has_vmx_ept_5levels(void)
1235 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1238 static inline bool cpu_has_vmx_ept_ad_bits(void)
1240 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1243 static inline bool cpu_has_vmx_invept_context(void)
1245 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1248 static inline bool cpu_has_vmx_invept_global(void)
1250 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1253 static inline bool cpu_has_vmx_invvpid_single(void)
1255 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1258 static inline bool cpu_has_vmx_invvpid_global(void)
1260 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1263 static inline bool cpu_has_vmx_invvpid(void)
1265 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1268 static inline bool cpu_has_vmx_ept(void)
1270 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1271 SECONDARY_EXEC_ENABLE_EPT
;
1274 static inline bool cpu_has_vmx_unrestricted_guest(void)
1276 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1277 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1280 static inline bool cpu_has_vmx_ple(void)
1282 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1283 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1286 static inline bool cpu_has_vmx_basic_inout(void)
1288 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1291 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1293 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1296 static inline bool cpu_has_vmx_vpid(void)
1298 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1299 SECONDARY_EXEC_ENABLE_VPID
;
1302 static inline bool cpu_has_vmx_rdtscp(void)
1304 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1305 SECONDARY_EXEC_RDTSCP
;
1308 static inline bool cpu_has_vmx_invpcid(void)
1310 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1311 SECONDARY_EXEC_ENABLE_INVPCID
;
1314 static inline bool cpu_has_virtual_nmis(void)
1316 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1319 static inline bool cpu_has_vmx_wbinvd_exit(void)
1321 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1322 SECONDARY_EXEC_WBINVD_EXITING
;
1325 static inline bool cpu_has_vmx_shadow_vmcs(void)
1328 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1329 /* check if the cpu supports writing r/o exit information fields */
1330 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1333 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1334 SECONDARY_EXEC_SHADOW_VMCS
;
1337 static inline bool cpu_has_vmx_pml(void)
1339 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1342 static inline bool cpu_has_vmx_tsc_scaling(void)
1344 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1345 SECONDARY_EXEC_TSC_SCALING
;
1348 static inline bool cpu_has_vmx_vmfunc(void)
1350 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1351 SECONDARY_EXEC_ENABLE_VMFUNC
;
1354 static inline bool report_flexpriority(void)
1356 return flexpriority_enabled
;
1359 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1361 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1364 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1366 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1369 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1371 return (vmcs12
->cpu_based_vm_exec_control
&
1372 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1373 (vmcs12
->secondary_vm_exec_control
& bit
);
1376 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1378 return vmcs12
->pin_based_vm_exec_control
&
1379 PIN_BASED_VMX_PREEMPTION_TIMER
;
1382 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1384 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1387 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1389 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1392 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1394 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1397 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1399 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1402 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1404 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1407 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1409 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1412 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1414 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1417 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1419 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1422 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1424 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1427 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1429 return nested_cpu_has_vmfunc(vmcs12
) &&
1430 (vmcs12
->vm_function_control
&
1431 VMX_VMFUNC_EPTP_SWITCHING
);
1434 static inline bool is_nmi(u32 intr_info
)
1436 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1437 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1440 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1442 unsigned long exit_qualification
);
1443 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1444 struct vmcs12
*vmcs12
,
1445 u32 reason
, unsigned long qualification
);
1447 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1451 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1452 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1457 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1463 } operand
= { vpid
, 0, gva
};
1465 asm volatile (__ex(ASM_VMX_INVVPID
)
1466 /* CF==1 or ZF==1 --> rc = -1 */
1467 "; ja 1f ; ud2 ; 1:"
1468 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1471 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1475 } operand
= {eptp
, gpa
};
1477 asm volatile (__ex(ASM_VMX_INVEPT
)
1478 /* CF==1 or ZF==1 --> rc = -1 */
1479 "; ja 1f ; ud2 ; 1:\n"
1480 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1483 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1487 i
= __find_msr_index(vmx
, msr
);
1489 return &vmx
->guest_msrs
[i
];
1493 static void vmcs_clear(struct vmcs
*vmcs
)
1495 u64 phys_addr
= __pa(vmcs
);
1498 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1499 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1502 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1506 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1508 vmcs_clear(loaded_vmcs
->vmcs
);
1509 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1510 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1511 loaded_vmcs
->cpu
= -1;
1512 loaded_vmcs
->launched
= 0;
1515 static void vmcs_load(struct vmcs
*vmcs
)
1517 u64 phys_addr
= __pa(vmcs
);
1520 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1521 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1524 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1528 #ifdef CONFIG_KEXEC_CORE
1530 * This bitmap is used to indicate whether the vmclear
1531 * operation is enabled on all cpus. All disabled by
1534 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1536 static inline void crash_enable_local_vmclear(int cpu
)
1538 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1541 static inline void crash_disable_local_vmclear(int cpu
)
1543 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1546 static inline int crash_local_vmclear_enabled(int cpu
)
1548 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1551 static void crash_vmclear_local_loaded_vmcss(void)
1553 int cpu
= raw_smp_processor_id();
1554 struct loaded_vmcs
*v
;
1556 if (!crash_local_vmclear_enabled(cpu
))
1559 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1560 loaded_vmcss_on_cpu_link
)
1561 vmcs_clear(v
->vmcs
);
1564 static inline void crash_enable_local_vmclear(int cpu
) { }
1565 static inline void crash_disable_local_vmclear(int cpu
) { }
1566 #endif /* CONFIG_KEXEC_CORE */
1568 static void __loaded_vmcs_clear(void *arg
)
1570 struct loaded_vmcs
*loaded_vmcs
= arg
;
1571 int cpu
= raw_smp_processor_id();
1573 if (loaded_vmcs
->cpu
!= cpu
)
1574 return; /* vcpu migration can race with cpu offline */
1575 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1576 per_cpu(current_vmcs
, cpu
) = NULL
;
1577 crash_disable_local_vmclear(cpu
);
1578 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1581 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1582 * is before setting loaded_vmcs->vcpu to -1 which is done in
1583 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1584 * then adds the vmcs into percpu list before it is deleted.
1588 loaded_vmcs_init(loaded_vmcs
);
1589 crash_enable_local_vmclear(cpu
);
1592 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1594 int cpu
= loaded_vmcs
->cpu
;
1597 smp_call_function_single(cpu
,
1598 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1601 static inline void vpid_sync_vcpu_single(int vpid
)
1606 if (cpu_has_vmx_invvpid_single())
1607 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1610 static inline void vpid_sync_vcpu_global(void)
1612 if (cpu_has_vmx_invvpid_global())
1613 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1616 static inline void vpid_sync_context(int vpid
)
1618 if (cpu_has_vmx_invvpid_single())
1619 vpid_sync_vcpu_single(vpid
);
1621 vpid_sync_vcpu_global();
1624 static inline void ept_sync_global(void)
1626 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1629 static inline void ept_sync_context(u64 eptp
)
1631 if (cpu_has_vmx_invept_context())
1632 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1637 static __always_inline
void vmcs_check16(unsigned long field
)
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1640 "16-bit accessor invalid for 64-bit field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1642 "16-bit accessor invalid for 64-bit high field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1644 "16-bit accessor invalid for 32-bit high field");
1645 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1646 "16-bit accessor invalid for natural width field");
1649 static __always_inline
void vmcs_check32(unsigned long field
)
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1652 "32-bit accessor invalid for 16-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1654 "32-bit accessor invalid for natural width field");
1657 static __always_inline
void vmcs_check64(unsigned long field
)
1659 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1660 "64-bit accessor invalid for 16-bit field");
1661 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1662 "64-bit accessor invalid for 64-bit high field");
1663 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1664 "64-bit accessor invalid for 32-bit field");
1665 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1666 "64-bit accessor invalid for natural width field");
1669 static __always_inline
void vmcs_checkl(unsigned long field
)
1671 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1672 "Natural width accessor invalid for 16-bit field");
1673 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1674 "Natural width accessor invalid for 64-bit field");
1675 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1676 "Natural width accessor invalid for 64-bit high field");
1677 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1678 "Natural width accessor invalid for 32-bit field");
1681 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1683 unsigned long value
;
1685 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1686 : "=a"(value
) : "d"(field
) : "cc");
1690 static __always_inline u16
vmcs_read16(unsigned long field
)
1692 vmcs_check16(field
);
1693 return __vmcs_readl(field
);
1696 static __always_inline u32
vmcs_read32(unsigned long field
)
1698 vmcs_check32(field
);
1699 return __vmcs_readl(field
);
1702 static __always_inline u64
vmcs_read64(unsigned long field
)
1704 vmcs_check64(field
);
1705 #ifdef CONFIG_X86_64
1706 return __vmcs_readl(field
);
1708 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1712 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1715 return __vmcs_readl(field
);
1718 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1720 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1721 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1725 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1729 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1730 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1731 if (unlikely(error
))
1732 vmwrite_error(field
, value
);
1735 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1737 vmcs_check16(field
);
1738 __vmcs_writel(field
, value
);
1741 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1743 vmcs_check32(field
);
1744 __vmcs_writel(field
, value
);
1747 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1749 vmcs_check64(field
);
1750 __vmcs_writel(field
, value
);
1751 #ifndef CONFIG_X86_64
1753 __vmcs_writel(field
+1, value
>> 32);
1757 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1760 __vmcs_writel(field
, value
);
1763 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1765 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1766 "vmcs_clear_bits does not support 64-bit fields");
1767 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1770 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1772 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1773 "vmcs_set_bits does not support 64-bit fields");
1774 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1777 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1779 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1782 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1784 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1785 vmx
->vm_entry_controls_shadow
= val
;
1788 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1790 if (vmx
->vm_entry_controls_shadow
!= val
)
1791 vm_entry_controls_init(vmx
, val
);
1794 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1796 return vmx
->vm_entry_controls_shadow
;
1800 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1802 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1805 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1807 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1810 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1812 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1815 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1817 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1818 vmx
->vm_exit_controls_shadow
= val
;
1821 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1823 if (vmx
->vm_exit_controls_shadow
!= val
)
1824 vm_exit_controls_init(vmx
, val
);
1827 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1829 return vmx
->vm_exit_controls_shadow
;
1833 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1835 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1838 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1840 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1843 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1845 vmx
->segment_cache
.bitmask
= 0;
1848 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1852 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1854 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1855 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1856 vmx
->segment_cache
.bitmask
= 0;
1858 ret
= vmx
->segment_cache
.bitmask
& mask
;
1859 vmx
->segment_cache
.bitmask
|= mask
;
1863 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1865 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1867 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1868 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1872 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1874 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1876 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1877 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1881 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1883 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1885 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1886 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1890 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1892 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1894 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1895 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1899 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1903 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1904 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1905 if ((vcpu
->guest_debug
&
1906 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1907 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1908 eb
|= 1u << BP_VECTOR
;
1909 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1912 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1914 /* When we are running a nested L2 guest and L1 specified for it a
1915 * certain exception bitmap, we must trap the same exceptions and pass
1916 * them to L1. When running L2, we will only handle the exceptions
1917 * specified above if L1 did not want them.
1919 if (is_guest_mode(vcpu
))
1920 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1922 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1926 * Check if MSR is intercepted for currently loaded MSR bitmap.
1928 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
1930 unsigned long *msr_bitmap
;
1931 int f
= sizeof(unsigned long);
1933 if (!cpu_has_vmx_msr_bitmap())
1936 msr_bitmap
= to_vmx(vcpu
)->loaded_vmcs
->msr_bitmap
;
1938 if (msr
<= 0x1fff) {
1939 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
1940 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1942 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
1949 * Check if MSR is intercepted for L01 MSR bitmap.
1951 static bool msr_write_intercepted_l01(struct kvm_vcpu
*vcpu
, u32 msr
)
1953 unsigned long *msr_bitmap
;
1954 int f
= sizeof(unsigned long);
1956 if (!cpu_has_vmx_msr_bitmap())
1959 msr_bitmap
= to_vmx(vcpu
)->vmcs01
.msr_bitmap
;
1961 if (msr
<= 0x1fff) {
1962 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
1963 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1965 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
1971 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1972 unsigned long entry
, unsigned long exit
)
1974 vm_entry_controls_clearbit(vmx
, entry
);
1975 vm_exit_controls_clearbit(vmx
, exit
);
1978 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1981 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1985 if (cpu_has_load_ia32_efer
) {
1986 clear_atomic_switch_msr_special(vmx
,
1987 VM_ENTRY_LOAD_IA32_EFER
,
1988 VM_EXIT_LOAD_IA32_EFER
);
1992 case MSR_CORE_PERF_GLOBAL_CTRL
:
1993 if (cpu_has_load_perf_global_ctrl
) {
1994 clear_atomic_switch_msr_special(vmx
,
1995 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1996 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2002 for (i
= 0; i
< m
->nr
; ++i
)
2003 if (m
->guest
[i
].index
== msr
)
2009 m
->guest
[i
] = m
->guest
[m
->nr
];
2010 m
->host
[i
] = m
->host
[m
->nr
];
2011 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2012 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2015 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
2016 unsigned long entry
, unsigned long exit
,
2017 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
2018 u64 guest_val
, u64 host_val
)
2020 vmcs_write64(guest_val_vmcs
, guest_val
);
2021 vmcs_write64(host_val_vmcs
, host_val
);
2022 vm_entry_controls_setbit(vmx
, entry
);
2023 vm_exit_controls_setbit(vmx
, exit
);
2026 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
2027 u64 guest_val
, u64 host_val
)
2030 struct msr_autoload
*m
= &vmx
->msr_autoload
;
2034 if (cpu_has_load_ia32_efer
) {
2035 add_atomic_switch_msr_special(vmx
,
2036 VM_ENTRY_LOAD_IA32_EFER
,
2037 VM_EXIT_LOAD_IA32_EFER
,
2040 guest_val
, host_val
);
2044 case MSR_CORE_PERF_GLOBAL_CTRL
:
2045 if (cpu_has_load_perf_global_ctrl
) {
2046 add_atomic_switch_msr_special(vmx
,
2047 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2048 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2049 GUEST_IA32_PERF_GLOBAL_CTRL
,
2050 HOST_IA32_PERF_GLOBAL_CTRL
,
2051 guest_val
, host_val
);
2055 case MSR_IA32_PEBS_ENABLE
:
2056 /* PEBS needs a quiescent period after being disabled (to write
2057 * a record). Disabling PEBS through VMX MSR swapping doesn't
2058 * provide that period, so a CPU could write host's record into
2061 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2064 for (i
= 0; i
< m
->nr
; ++i
)
2065 if (m
->guest
[i
].index
== msr
)
2068 if (i
== NR_AUTOLOAD_MSRS
) {
2069 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2070 "Can't add msr %x\n", msr
);
2072 } else if (i
== m
->nr
) {
2074 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2075 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2078 m
->guest
[i
].index
= msr
;
2079 m
->guest
[i
].value
= guest_val
;
2080 m
->host
[i
].index
= msr
;
2081 m
->host
[i
].value
= host_val
;
2084 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2086 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2087 u64 ignore_bits
= 0;
2091 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2092 * host CPUID is more efficient than testing guest CPUID
2093 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2095 if (boot_cpu_has(X86_FEATURE_SMEP
))
2096 guest_efer
|= EFER_NX
;
2097 else if (!(guest_efer
& EFER_NX
))
2098 ignore_bits
|= EFER_NX
;
2102 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2104 ignore_bits
|= EFER_SCE
;
2105 #ifdef CONFIG_X86_64
2106 ignore_bits
|= EFER_LMA
| EFER_LME
;
2107 /* SCE is meaningful only in long mode on Intel */
2108 if (guest_efer
& EFER_LMA
)
2109 ignore_bits
&= ~(u64
)EFER_SCE
;
2112 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2115 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2116 * On CPUs that support "load IA32_EFER", always switch EFER
2117 * atomically, since it's faster than switching it manually.
2119 if (cpu_has_load_ia32_efer
||
2120 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2121 if (!(guest_efer
& EFER_LMA
))
2122 guest_efer
&= ~EFER_LME
;
2123 if (guest_efer
!= host_efer
)
2124 add_atomic_switch_msr(vmx
, MSR_EFER
,
2125 guest_efer
, host_efer
);
2128 guest_efer
&= ~ignore_bits
;
2129 guest_efer
|= host_efer
& ignore_bits
;
2131 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2132 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2138 #ifdef CONFIG_X86_32
2140 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2141 * VMCS rather than the segment table. KVM uses this helper to figure
2142 * out the current bases to poke them into the VMCS before entry.
2144 static unsigned long segment_base(u16 selector
)
2146 struct desc_struct
*table
;
2149 if (!(selector
& ~SEGMENT_RPL_MASK
))
2152 table
= get_current_gdt_ro();
2154 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2155 u16 ldt_selector
= kvm_read_ldt();
2157 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2160 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2162 v
= get_desc_base(&table
[selector
>> 3]);
2167 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2169 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2172 if (vmx
->host_state
.loaded
)
2175 vmx
->host_state
.loaded
= 1;
2177 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2178 * allow segment selectors with cpl > 0 or ti == 1.
2180 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2181 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2182 savesegment(fs
, vmx
->host_state
.fs_sel
);
2183 if (!(vmx
->host_state
.fs_sel
& 7)) {
2184 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2185 vmx
->host_state
.fs_reload_needed
= 0;
2187 vmcs_write16(HOST_FS_SELECTOR
, 0);
2188 vmx
->host_state
.fs_reload_needed
= 1;
2190 savesegment(gs
, vmx
->host_state
.gs_sel
);
2191 if (!(vmx
->host_state
.gs_sel
& 7))
2192 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2194 vmcs_write16(HOST_GS_SELECTOR
, 0);
2195 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2198 #ifdef CONFIG_X86_64
2199 savesegment(ds
, vmx
->host_state
.ds_sel
);
2200 savesegment(es
, vmx
->host_state
.es_sel
);
2203 #ifdef CONFIG_X86_64
2204 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2205 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2207 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2208 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2211 #ifdef CONFIG_X86_64
2212 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2213 if (is_long_mode(&vmx
->vcpu
))
2214 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2216 if (boot_cpu_has(X86_FEATURE_MPX
))
2217 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2218 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2219 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2220 vmx
->guest_msrs
[i
].data
,
2221 vmx
->guest_msrs
[i
].mask
);
2224 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2226 if (!vmx
->host_state
.loaded
)
2229 ++vmx
->vcpu
.stat
.host_state_reload
;
2230 vmx
->host_state
.loaded
= 0;
2231 #ifdef CONFIG_X86_64
2232 if (is_long_mode(&vmx
->vcpu
))
2233 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2235 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2236 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2237 #ifdef CONFIG_X86_64
2238 load_gs_index(vmx
->host_state
.gs_sel
);
2240 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2243 if (vmx
->host_state
.fs_reload_needed
)
2244 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2245 #ifdef CONFIG_X86_64
2246 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2247 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2248 loadsegment(es
, vmx
->host_state
.es_sel
);
2251 invalidate_tss_limit();
2252 #ifdef CONFIG_X86_64
2253 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2255 if (vmx
->host_state
.msr_host_bndcfgs
)
2256 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2257 load_fixmap_gdt(raw_smp_processor_id());
2260 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2263 __vmx_load_host_state(vmx
);
2267 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2269 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2270 struct pi_desc old
, new;
2274 * In case of hot-plug or hot-unplug, we may have to undo
2275 * vmx_vcpu_pi_put even if there is no assigned device. And we
2276 * always keep PI.NDST up to date for simplicity: it makes the
2277 * code easier, and CPU migration is not a fast path.
2279 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2283 * First handle the simple case where no cmpxchg is necessary; just
2284 * allow posting non-urgent interrupts.
2286 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2287 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2288 * expects the VCPU to be on the blocked_vcpu_list that matches
2291 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2293 pi_clear_sn(pi_desc
);
2297 /* The full case. */
2299 old
.control
= new.control
= pi_desc
->control
;
2301 dest
= cpu_physical_id(cpu
);
2303 if (x2apic_enabled())
2306 new.ndst
= (dest
<< 8) & 0xFF00;
2309 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2310 new.control
) != old
.control
);
2313 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2315 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2316 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2320 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2321 * vcpu mutex is already taken.
2323 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2325 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2326 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2328 if (!already_loaded
) {
2329 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2330 local_irq_disable();
2331 crash_disable_local_vmclear(cpu
);
2334 * Read loaded_vmcs->cpu should be before fetching
2335 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2336 * See the comments in __loaded_vmcs_clear().
2340 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2341 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2342 crash_enable_local_vmclear(cpu
);
2346 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2347 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2348 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2349 indirect_branch_prediction_barrier();
2352 if (!already_loaded
) {
2353 void *gdt
= get_current_gdt_ro();
2354 unsigned long sysenter_esp
;
2356 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2359 * Linux uses per-cpu TSS and GDT, so set these when switching
2360 * processors. See 22.2.4.
2362 vmcs_writel(HOST_TR_BASE
,
2363 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2364 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2367 * VM exits change the host TR limit to 0x67 after a VM
2368 * exit. This is okay, since 0x67 covers everything except
2369 * the IO bitmap and have have code to handle the IO bitmap
2370 * being lost after a VM exit.
2372 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2374 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2375 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2377 vmx
->loaded_vmcs
->cpu
= cpu
;
2380 /* Setup TSC multiplier */
2381 if (kvm_has_tsc_control
&&
2382 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2383 decache_tsc_multiplier(vmx
);
2385 vmx_vcpu_pi_load(vcpu
, cpu
);
2386 vmx
->host_pkru
= read_pkru();
2389 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2391 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2393 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2394 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2395 !kvm_vcpu_apicv_active(vcpu
))
2398 /* Set SN when the vCPU is preempted */
2399 if (vcpu
->preempted
)
2403 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2405 vmx_vcpu_pi_put(vcpu
);
2407 __vmx_load_host_state(to_vmx(vcpu
));
2410 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2412 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2415 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2418 * Return the cr0 value that a nested guest would read. This is a combination
2419 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2420 * its hypervisor (cr0_read_shadow).
2422 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2424 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2425 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2427 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2429 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2430 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2433 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2435 unsigned long rflags
, save_rflags
;
2437 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2438 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2439 rflags
= vmcs_readl(GUEST_RFLAGS
);
2440 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2441 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2442 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2443 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2445 to_vmx(vcpu
)->rflags
= rflags
;
2447 return to_vmx(vcpu
)->rflags
;
2450 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2452 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2454 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2455 to_vmx(vcpu
)->rflags
= rflags
;
2456 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2457 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2458 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2460 vmcs_writel(GUEST_RFLAGS
, rflags
);
2462 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2463 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2466 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2468 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2471 if (interruptibility
& GUEST_INTR_STATE_STI
)
2472 ret
|= KVM_X86_SHADOW_INT_STI
;
2473 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2474 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2479 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2481 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2482 u32 interruptibility
= interruptibility_old
;
2484 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2486 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2487 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2488 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2489 interruptibility
|= GUEST_INTR_STATE_STI
;
2491 if ((interruptibility
!= interruptibility_old
))
2492 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2495 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2499 rip
= kvm_rip_read(vcpu
);
2500 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2501 kvm_rip_write(vcpu
, rip
);
2503 /* skipping an emulated instruction also counts */
2504 vmx_set_interrupt_shadow(vcpu
, 0);
2507 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2508 unsigned long exit_qual
)
2510 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2511 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2512 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2514 if (vcpu
->arch
.exception
.has_error_code
) {
2515 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2516 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2519 if (kvm_exception_is_soft(nr
))
2520 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2522 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2524 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2525 vmx_get_nmi_mask(vcpu
))
2526 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2528 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2532 * KVM wants to inject page-faults which it got to the guest. This function
2533 * checks whether in a nested guest, we need to inject them to L1 or L2.
2535 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2537 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2538 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2540 if (nr
== PF_VECTOR
) {
2541 if (vcpu
->arch
.exception
.nested_apf
) {
2542 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2546 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2547 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2548 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2549 * can be written only when inject_pending_event runs. This should be
2550 * conditional on a new capability---if the capability is disabled,
2551 * kvm_multiple_exception would write the ancillary information to
2552 * CR2 or DR6, for backwards ABI-compatibility.
2554 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2555 vcpu
->arch
.exception
.error_code
)) {
2556 *exit_qual
= vcpu
->arch
.cr2
;
2560 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2561 if (nr
== DB_VECTOR
)
2562 *exit_qual
= vcpu
->arch
.dr6
;
2572 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2574 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2575 unsigned nr
= vcpu
->arch
.exception
.nr
;
2576 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2577 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2578 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2580 if (has_error_code
) {
2581 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2582 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2585 if (vmx
->rmode
.vm86_active
) {
2587 if (kvm_exception_is_soft(nr
))
2588 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2589 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2590 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2594 if (kvm_exception_is_soft(nr
)) {
2595 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2596 vmx
->vcpu
.arch
.event_exit_inst_len
);
2597 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2599 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2604 static bool vmx_rdtscp_supported(void)
2606 return cpu_has_vmx_rdtscp();
2609 static bool vmx_invpcid_supported(void)
2611 return cpu_has_vmx_invpcid() && enable_ept
;
2615 * Swap MSR entry in host/guest MSR entry array.
2617 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2619 struct shared_msr_entry tmp
;
2621 tmp
= vmx
->guest_msrs
[to
];
2622 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2623 vmx
->guest_msrs
[from
] = tmp
;
2627 * Set up the vmcs to automatically save and restore system
2628 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2629 * mode, as fiddling with msrs is very expensive.
2631 static void setup_msrs(struct vcpu_vmx
*vmx
)
2633 int save_nmsrs
, index
;
2636 #ifdef CONFIG_X86_64
2637 if (is_long_mode(&vmx
->vcpu
)) {
2638 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2640 move_msr_up(vmx
, index
, save_nmsrs
++);
2641 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2643 move_msr_up(vmx
, index
, save_nmsrs
++);
2644 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2646 move_msr_up(vmx
, index
, save_nmsrs
++);
2647 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2648 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2649 move_msr_up(vmx
, index
, save_nmsrs
++);
2651 * MSR_STAR is only needed on long mode guests, and only
2652 * if efer.sce is enabled.
2654 index
= __find_msr_index(vmx
, MSR_STAR
);
2655 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2656 move_msr_up(vmx
, index
, save_nmsrs
++);
2659 index
= __find_msr_index(vmx
, MSR_EFER
);
2660 if (index
>= 0 && update_transition_efer(vmx
, index
))
2661 move_msr_up(vmx
, index
, save_nmsrs
++);
2663 vmx
->save_nmsrs
= save_nmsrs
;
2665 if (cpu_has_vmx_msr_bitmap())
2666 vmx_update_msr_bitmap(&vmx
->vcpu
);
2670 * reads and returns guest's timestamp counter "register"
2671 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2672 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2674 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2676 u64 host_tsc
, tsc_offset
;
2679 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2680 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2684 * writes 'offset' into guest's timestamp counter offset register
2686 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2688 if (is_guest_mode(vcpu
)) {
2690 * We're here if L1 chose not to trap WRMSR to TSC. According
2691 * to the spec, this should set L1's TSC; The offset that L1
2692 * set for L2 remains unchanged, and still needs to be added
2693 * to the newly set TSC to get L2's TSC.
2695 struct vmcs12
*vmcs12
;
2696 /* recalculate vmcs02.TSC_OFFSET: */
2697 vmcs12
= get_vmcs12(vcpu
);
2698 vmcs_write64(TSC_OFFSET
, offset
+
2699 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2700 vmcs12
->tsc_offset
: 0));
2702 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2703 vmcs_read64(TSC_OFFSET
), offset
);
2704 vmcs_write64(TSC_OFFSET
, offset
);
2709 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2710 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2711 * all guests if the "nested" module option is off, and can also be disabled
2712 * for a single guest by disabling its VMX cpuid bit.
2714 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2716 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2720 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2721 * returned for the various VMX controls MSRs when nested VMX is enabled.
2722 * The same values should also be used to verify that vmcs12 control fields are
2723 * valid during nested entry from L1 to L2.
2724 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2725 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2726 * bit in the high half is on if the corresponding bit in the control field
2727 * may be on. See also vmx_control_verify().
2729 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2732 * Note that as a general rule, the high half of the MSRs (bits in
2733 * the control fields which may be 1) should be initialized by the
2734 * intersection of the underlying hardware's MSR (i.e., features which
2735 * can be supported) and the list of features we want to expose -
2736 * because they are known to be properly supported in our code.
2737 * Also, usually, the low half of the MSRs (bits which must be 1) can
2738 * be set to 0, meaning that L1 may turn off any of these bits. The
2739 * reason is that if one of these bits is necessary, it will appear
2740 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2741 * fields of vmcs01 and vmcs02, will turn these bits off - and
2742 * nested_vmx_exit_reflected() will not pass related exits to L1.
2743 * These rules have exceptions below.
2746 /* pin-based controls */
2747 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2748 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2749 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2750 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2751 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2752 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2753 PIN_BASED_EXT_INTR_MASK
|
2754 PIN_BASED_NMI_EXITING
|
2755 PIN_BASED_VIRTUAL_NMIS
;
2756 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2757 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2758 PIN_BASED_VMX_PREEMPTION_TIMER
;
2759 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2760 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2761 PIN_BASED_POSTED_INTR
;
2764 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2765 vmx
->nested
.nested_vmx_exit_ctls_low
,
2766 vmx
->nested
.nested_vmx_exit_ctls_high
);
2767 vmx
->nested
.nested_vmx_exit_ctls_low
=
2768 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2770 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2771 #ifdef CONFIG_X86_64
2772 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2774 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2775 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2776 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2777 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2778 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2780 if (kvm_mpx_supported())
2781 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2783 /* We support free control of debug control saving. */
2784 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2786 /* entry controls */
2787 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2788 vmx
->nested
.nested_vmx_entry_ctls_low
,
2789 vmx
->nested
.nested_vmx_entry_ctls_high
);
2790 vmx
->nested
.nested_vmx_entry_ctls_low
=
2791 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2792 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2793 #ifdef CONFIG_X86_64
2794 VM_ENTRY_IA32E_MODE
|
2796 VM_ENTRY_LOAD_IA32_PAT
;
2797 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2798 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2799 if (kvm_mpx_supported())
2800 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2802 /* We support free control of debug control loading. */
2803 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2805 /* cpu-based controls */
2806 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2807 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2808 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2809 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2810 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2811 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2812 CPU_BASED_VIRTUAL_INTR_PENDING
|
2813 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2814 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2815 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2816 CPU_BASED_CR3_STORE_EXITING
|
2817 #ifdef CONFIG_X86_64
2818 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2820 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2821 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2822 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2823 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2824 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2826 * We can allow some features even when not supported by the
2827 * hardware. For example, L1 can specify an MSR bitmap - and we
2828 * can use it to avoid exits to L1 - even when L0 runs L2
2829 * without MSR bitmaps.
2831 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2832 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2833 CPU_BASED_USE_MSR_BITMAPS
;
2835 /* We support free control of CR3 access interception. */
2836 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2837 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2840 * secondary cpu-based controls. Do not include those that
2841 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2843 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2844 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2845 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2846 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2847 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2848 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2849 SECONDARY_EXEC_DESC
|
2850 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2851 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2852 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2853 SECONDARY_EXEC_WBINVD_EXITING
;
2856 /* nested EPT: emulate EPT also to L1 */
2857 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2858 SECONDARY_EXEC_ENABLE_EPT
;
2859 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2860 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2861 if (cpu_has_vmx_ept_execute_only())
2862 vmx
->nested
.nested_vmx_ept_caps
|=
2863 VMX_EPT_EXECUTE_ONLY_BIT
;
2864 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2865 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2866 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2867 VMX_EPT_1GB_PAGE_BIT
;
2868 if (enable_ept_ad_bits
) {
2869 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2870 SECONDARY_EXEC_ENABLE_PML
;
2871 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2875 if (cpu_has_vmx_vmfunc()) {
2876 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2877 SECONDARY_EXEC_ENABLE_VMFUNC
;
2879 * Advertise EPTP switching unconditionally
2880 * since we emulate it
2883 vmx
->nested
.nested_vmx_vmfunc_controls
=
2884 VMX_VMFUNC_EPTP_SWITCHING
;
2888 * Old versions of KVM use the single-context version without
2889 * checking for support, so declare that it is supported even
2890 * though it is treated as global context. The alternative is
2891 * not failing the single-context invvpid, and it is worse.
2894 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2895 SECONDARY_EXEC_ENABLE_VPID
;
2896 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2897 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2900 if (enable_unrestricted_guest
)
2901 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2902 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2904 /* miscellaneous data */
2905 rdmsr(MSR_IA32_VMX_MISC
,
2906 vmx
->nested
.nested_vmx_misc_low
,
2907 vmx
->nested
.nested_vmx_misc_high
);
2908 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2909 vmx
->nested
.nested_vmx_misc_low
|=
2910 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2911 VMX_MISC_ACTIVITY_HLT
;
2912 vmx
->nested
.nested_vmx_misc_high
= 0;
2915 * This MSR reports some information about VMX support. We
2916 * should return information about the VMX we emulate for the
2917 * guest, and the VMCS structure we give it - not about the
2918 * VMX support of the underlying hardware.
2920 vmx
->nested
.nested_vmx_basic
=
2922 VMX_BASIC_TRUE_CTLS
|
2923 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2924 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2926 if (cpu_has_vmx_basic_inout())
2927 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2930 * These MSRs specify bits which the guest must keep fixed on
2931 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2932 * We picked the standard core2 setting.
2934 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2935 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2936 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2937 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2939 /* These MSRs specify bits which the guest must keep fixed off. */
2940 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2941 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2943 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2944 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2948 * if fixed0[i] == 1: val[i] must be 1
2949 * if fixed1[i] == 0: val[i] must be 0
2951 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2953 return ((val
& fixed1
) | fixed0
) == val
;
2956 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2958 return fixed_bits_valid(control
, low
, high
);
2961 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2963 return low
| ((u64
)high
<< 32);
2966 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2971 return (superset
| subset
) == superset
;
2974 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2976 const u64 feature_and_reserved
=
2977 /* feature (except bit 48; see below) */
2978 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2980 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2981 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2983 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2987 * KVM does not emulate a version of VMX that constrains physical
2988 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2990 if (data
& BIT_ULL(48))
2993 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2994 vmx_basic_vmcs_revision_id(data
))
2997 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
3000 vmx
->nested
.nested_vmx_basic
= data
;
3005 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3010 switch (msr_index
) {
3011 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3012 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
3013 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
3015 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3016 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
3017 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
3019 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3020 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
3021 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
3023 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3024 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
3025 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
3027 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3028 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
3029 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3035 supported
= vmx_control_msr(*lowp
, *highp
);
3037 /* Check must-be-1 bits are still 1. */
3038 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3041 /* Check must-be-0 bits are still 0. */
3042 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3046 *highp
= data
>> 32;
3050 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3052 const u64 feature_and_reserved_bits
=
3054 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3055 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3057 GENMASK_ULL(13, 9) | BIT_ULL(31);
3060 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3061 vmx
->nested
.nested_vmx_misc_high
);
3063 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3066 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3067 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3068 vmx_misc_preemption_timer_rate(data
) !=
3069 vmx_misc_preemption_timer_rate(vmx_misc
))
3072 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3075 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3078 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3081 vmx
->nested
.nested_vmx_misc_low
= data
;
3082 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3086 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3088 u64 vmx_ept_vpid_cap
;
3090 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3091 vmx
->nested
.nested_vmx_vpid_caps
);
3093 /* Every bit is either reserved or a feature bit. */
3094 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3097 vmx
->nested
.nested_vmx_ept_caps
= data
;
3098 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3102 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3106 switch (msr_index
) {
3107 case MSR_IA32_VMX_CR0_FIXED0
:
3108 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3110 case MSR_IA32_VMX_CR4_FIXED0
:
3111 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3118 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3119 * must be 1 in the restored value.
3121 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3129 * Called when userspace is restoring VMX MSRs.
3131 * Returns 0 on success, non-0 otherwise.
3133 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3135 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3137 switch (msr_index
) {
3138 case MSR_IA32_VMX_BASIC
:
3139 return vmx_restore_vmx_basic(vmx
, data
);
3140 case MSR_IA32_VMX_PINBASED_CTLS
:
3141 case MSR_IA32_VMX_PROCBASED_CTLS
:
3142 case MSR_IA32_VMX_EXIT_CTLS
:
3143 case MSR_IA32_VMX_ENTRY_CTLS
:
3145 * The "non-true" VMX capability MSRs are generated from the
3146 * "true" MSRs, so we do not support restoring them directly.
3148 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3149 * should restore the "true" MSRs with the must-be-1 bits
3150 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3151 * DEFAULT SETTINGS".
3154 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3155 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3156 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3157 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3158 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3159 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3160 case MSR_IA32_VMX_MISC
:
3161 return vmx_restore_vmx_misc(vmx
, data
);
3162 case MSR_IA32_VMX_CR0_FIXED0
:
3163 case MSR_IA32_VMX_CR4_FIXED0
:
3164 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3165 case MSR_IA32_VMX_CR0_FIXED1
:
3166 case MSR_IA32_VMX_CR4_FIXED1
:
3168 * These MSRs are generated based on the vCPU's CPUID, so we
3169 * do not support restoring them directly.
3172 case MSR_IA32_VMX_EPT_VPID_CAP
:
3173 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3174 case MSR_IA32_VMX_VMCS_ENUM
:
3175 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3179 * The rest of the VMX capability MSRs do not support restore.
3185 /* Returns 0 on success, non-0 otherwise. */
3186 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3188 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3190 switch (msr_index
) {
3191 case MSR_IA32_VMX_BASIC
:
3192 *pdata
= vmx
->nested
.nested_vmx_basic
;
3194 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3195 case MSR_IA32_VMX_PINBASED_CTLS
:
3196 *pdata
= vmx_control_msr(
3197 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3198 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3199 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3200 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3202 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3203 case MSR_IA32_VMX_PROCBASED_CTLS
:
3204 *pdata
= vmx_control_msr(
3205 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3206 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3207 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3208 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3210 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3211 case MSR_IA32_VMX_EXIT_CTLS
:
3212 *pdata
= vmx_control_msr(
3213 vmx
->nested
.nested_vmx_exit_ctls_low
,
3214 vmx
->nested
.nested_vmx_exit_ctls_high
);
3215 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3216 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3218 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3219 case MSR_IA32_VMX_ENTRY_CTLS
:
3220 *pdata
= vmx_control_msr(
3221 vmx
->nested
.nested_vmx_entry_ctls_low
,
3222 vmx
->nested
.nested_vmx_entry_ctls_high
);
3223 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3224 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3226 case MSR_IA32_VMX_MISC
:
3227 *pdata
= vmx_control_msr(
3228 vmx
->nested
.nested_vmx_misc_low
,
3229 vmx
->nested
.nested_vmx_misc_high
);
3231 case MSR_IA32_VMX_CR0_FIXED0
:
3232 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3234 case MSR_IA32_VMX_CR0_FIXED1
:
3235 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3237 case MSR_IA32_VMX_CR4_FIXED0
:
3238 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3240 case MSR_IA32_VMX_CR4_FIXED1
:
3241 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3243 case MSR_IA32_VMX_VMCS_ENUM
:
3244 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3246 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3247 *pdata
= vmx_control_msr(
3248 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3249 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3251 case MSR_IA32_VMX_EPT_VPID_CAP
:
3252 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3253 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3255 case MSR_IA32_VMX_VMFUNC
:
3256 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3265 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3268 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3270 return !(val
& ~valid_bits
);
3274 * Reads an msr value (of 'msr_index') into 'pdata'.
3275 * Returns 0 on success, non-0 otherwise.
3276 * Assumes vcpu_load() was already called.
3278 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3280 struct shared_msr_entry
*msr
;
3282 switch (msr_info
->index
) {
3283 #ifdef CONFIG_X86_64
3285 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3288 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3290 case MSR_KERNEL_GS_BASE
:
3291 vmx_load_host_state(to_vmx(vcpu
));
3292 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3296 return kvm_get_msr_common(vcpu
, msr_info
);
3298 msr_info
->data
= guest_read_tsc(vcpu
);
3300 case MSR_IA32_SPEC_CTRL
:
3301 if (!msr_info
->host_initiated
&&
3302 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3305 msr_info
->data
= to_vmx(vcpu
)->spec_ctrl
;
3307 case MSR_IA32_ARCH_CAPABILITIES
:
3308 if (!msr_info
->host_initiated
&&
3309 !guest_cpuid_has(vcpu
, X86_FEATURE_ARCH_CAPABILITIES
))
3311 msr_info
->data
= to_vmx(vcpu
)->arch_capabilities
;
3313 case MSR_IA32_SYSENTER_CS
:
3314 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3316 case MSR_IA32_SYSENTER_EIP
:
3317 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3319 case MSR_IA32_SYSENTER_ESP
:
3320 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3322 case MSR_IA32_BNDCFGS
:
3323 if (!kvm_mpx_supported() ||
3324 (!msr_info
->host_initiated
&&
3325 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3327 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3329 case MSR_IA32_MCG_EXT_CTL
:
3330 if (!msr_info
->host_initiated
&&
3331 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3332 FEATURE_CONTROL_LMCE
))
3334 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3336 case MSR_IA32_FEATURE_CONTROL
:
3337 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3339 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3340 if (!nested_vmx_allowed(vcpu
))
3342 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3344 if (!vmx_xsaves_supported())
3346 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3349 if (!msr_info
->host_initiated
&&
3350 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3352 /* Otherwise falls through */
3354 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3356 msr_info
->data
= msr
->data
;
3359 return kvm_get_msr_common(vcpu
, msr_info
);
3365 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3368 * Writes msr value into into the appropriate "register".
3369 * Returns 0 on success, non-0 otherwise.
3370 * Assumes vcpu_load() was already called.
3372 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3374 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3375 struct shared_msr_entry
*msr
;
3377 u32 msr_index
= msr_info
->index
;
3378 u64 data
= msr_info
->data
;
3380 switch (msr_index
) {
3382 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3384 #ifdef CONFIG_X86_64
3386 vmx_segment_cache_clear(vmx
);
3387 vmcs_writel(GUEST_FS_BASE
, data
);
3390 vmx_segment_cache_clear(vmx
);
3391 vmcs_writel(GUEST_GS_BASE
, data
);
3393 case MSR_KERNEL_GS_BASE
:
3394 vmx_load_host_state(vmx
);
3395 vmx
->msr_guest_kernel_gs_base
= data
;
3398 case MSR_IA32_SYSENTER_CS
:
3399 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3401 case MSR_IA32_SYSENTER_EIP
:
3402 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3404 case MSR_IA32_SYSENTER_ESP
:
3405 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3407 case MSR_IA32_BNDCFGS
:
3408 if (!kvm_mpx_supported() ||
3409 (!msr_info
->host_initiated
&&
3410 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3412 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3413 (data
& MSR_IA32_BNDCFGS_RSVD
))
3415 vmcs_write64(GUEST_BNDCFGS
, data
);
3418 kvm_write_tsc(vcpu
, msr_info
);
3420 case MSR_IA32_SPEC_CTRL
:
3421 if (!msr_info
->host_initiated
&&
3422 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3425 /* The STIBP bit doesn't fault even if it's not advertised */
3426 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
3429 vmx
->spec_ctrl
= data
;
3436 * When it's written (to non-zero) for the first time, pass
3440 * The handling of the MSR bitmap for L2 guests is done in
3441 * nested_vmx_merge_msr_bitmap. We should not touch the
3442 * vmcs02.msr_bitmap here since it gets completely overwritten
3443 * in the merging. We update the vmcs01 here for L1 as well
3444 * since it will end up touching the MSR anyway now.
3446 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
,
3450 case MSR_IA32_PRED_CMD
:
3451 if (!msr_info
->host_initiated
&&
3452 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3455 if (data
& ~PRED_CMD_IBPB
)
3461 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
3465 * When it's written (to non-zero) for the first time, pass
3469 * The handling of the MSR bitmap for L2 guests is done in
3470 * nested_vmx_merge_msr_bitmap. We should not touch the
3471 * vmcs02.msr_bitmap here since it gets completely overwritten
3474 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
, MSR_IA32_PRED_CMD
,
3477 case MSR_IA32_ARCH_CAPABILITIES
:
3478 if (!msr_info
->host_initiated
)
3480 vmx
->arch_capabilities
= data
;
3482 case MSR_IA32_CR_PAT
:
3483 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3484 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3486 vmcs_write64(GUEST_IA32_PAT
, data
);
3487 vcpu
->arch
.pat
= data
;
3490 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3492 case MSR_IA32_TSC_ADJUST
:
3493 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3495 case MSR_IA32_MCG_EXT_CTL
:
3496 if ((!msr_info
->host_initiated
&&
3497 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3498 FEATURE_CONTROL_LMCE
)) ||
3499 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3501 vcpu
->arch
.mcg_ext_ctl
= data
;
3503 case MSR_IA32_FEATURE_CONTROL
:
3504 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3505 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3506 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3508 vmx
->msr_ia32_feature_control
= data
;
3509 if (msr_info
->host_initiated
&& data
== 0)
3510 vmx_leave_nested(vcpu
);
3512 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3513 if (!msr_info
->host_initiated
)
3514 return 1; /* they are read-only */
3515 if (!nested_vmx_allowed(vcpu
))
3517 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3519 if (!vmx_xsaves_supported())
3522 * The only supported bit as of Skylake is bit 8, but
3523 * it is not supported on KVM.
3527 vcpu
->arch
.ia32_xss
= data
;
3528 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3529 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3530 vcpu
->arch
.ia32_xss
, host_xss
);
3532 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3535 if (!msr_info
->host_initiated
&&
3536 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3538 /* Check reserved bit, higher 32 bits should be zero */
3539 if ((data
>> 32) != 0)
3541 /* Otherwise falls through */
3543 msr
= find_msr_entry(vmx
, msr_index
);
3545 u64 old_msr_data
= msr
->data
;
3547 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3549 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3553 msr
->data
= old_msr_data
;
3557 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3563 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3565 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3568 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3571 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3573 case VCPU_EXREG_PDPTR
:
3575 ept_save_pdptrs(vcpu
);
3582 static __init
int cpu_has_kvm_support(void)
3584 return cpu_has_vmx();
3587 static __init
int vmx_disabled_by_bios(void)
3591 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3592 if (msr
& FEATURE_CONTROL_LOCKED
) {
3593 /* launched w/ TXT and VMX disabled */
3594 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3597 /* launched w/o TXT and VMX only enabled w/ TXT */
3598 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3599 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3600 && !tboot_enabled()) {
3601 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3602 "activate TXT before enabling KVM\n");
3605 /* launched w/o TXT and VMX disabled */
3606 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3607 && !tboot_enabled())
3614 static void kvm_cpu_vmxon(u64 addr
)
3616 cr4_set_bits(X86_CR4_VMXE
);
3617 intel_pt_handle_vmx(1);
3619 asm volatile (ASM_VMX_VMXON_RAX
3620 : : "a"(&addr
), "m"(addr
)
3624 static int hardware_enable(void)
3626 int cpu
= raw_smp_processor_id();
3627 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3630 if (cr4_read_shadow() & X86_CR4_VMXE
)
3633 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3634 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3635 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3638 * Now we can enable the vmclear operation in kdump
3639 * since the loaded_vmcss_on_cpu list on this cpu
3640 * has been initialized.
3642 * Though the cpu is not in VMX operation now, there
3643 * is no problem to enable the vmclear operation
3644 * for the loaded_vmcss_on_cpu list is empty!
3646 crash_enable_local_vmclear(cpu
);
3648 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3650 test_bits
= FEATURE_CONTROL_LOCKED
;
3651 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3652 if (tboot_enabled())
3653 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3655 if ((old
& test_bits
) != test_bits
) {
3656 /* enable and lock */
3657 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3659 kvm_cpu_vmxon(phys_addr
);
3666 static void vmclear_local_loaded_vmcss(void)
3668 int cpu
= raw_smp_processor_id();
3669 struct loaded_vmcs
*v
, *n
;
3671 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3672 loaded_vmcss_on_cpu_link
)
3673 __loaded_vmcs_clear(v
);
3677 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3680 static void kvm_cpu_vmxoff(void)
3682 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3684 intel_pt_handle_vmx(0);
3685 cr4_clear_bits(X86_CR4_VMXE
);
3688 static void hardware_disable(void)
3690 vmclear_local_loaded_vmcss();
3694 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3695 u32 msr
, u32
*result
)
3697 u32 vmx_msr_low
, vmx_msr_high
;
3698 u32 ctl
= ctl_min
| ctl_opt
;
3700 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3702 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3703 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3705 /* Ensure minimum (required) set of control bits are supported. */
3713 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3715 u32 vmx_msr_low
, vmx_msr_high
;
3717 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3718 return vmx_msr_high
& ctl
;
3721 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3723 u32 vmx_msr_low
, vmx_msr_high
;
3724 u32 min
, opt
, min2
, opt2
;
3725 u32 _pin_based_exec_control
= 0;
3726 u32 _cpu_based_exec_control
= 0;
3727 u32 _cpu_based_2nd_exec_control
= 0;
3728 u32 _vmexit_control
= 0;
3729 u32 _vmentry_control
= 0;
3731 min
= CPU_BASED_HLT_EXITING
|
3732 #ifdef CONFIG_X86_64
3733 CPU_BASED_CR8_LOAD_EXITING
|
3734 CPU_BASED_CR8_STORE_EXITING
|
3736 CPU_BASED_CR3_LOAD_EXITING
|
3737 CPU_BASED_CR3_STORE_EXITING
|
3738 CPU_BASED_USE_IO_BITMAPS
|
3739 CPU_BASED_MOV_DR_EXITING
|
3740 CPU_BASED_USE_TSC_OFFSETING
|
3741 CPU_BASED_INVLPG_EXITING
|
3742 CPU_BASED_RDPMC_EXITING
;
3744 if (!kvm_mwait_in_guest())
3745 min
|= CPU_BASED_MWAIT_EXITING
|
3746 CPU_BASED_MONITOR_EXITING
;
3748 opt
= CPU_BASED_TPR_SHADOW
|
3749 CPU_BASED_USE_MSR_BITMAPS
|
3750 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3751 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3752 &_cpu_based_exec_control
) < 0)
3754 #ifdef CONFIG_X86_64
3755 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3756 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3757 ~CPU_BASED_CR8_STORE_EXITING
;
3759 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3761 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3762 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3763 SECONDARY_EXEC_WBINVD_EXITING
|
3764 SECONDARY_EXEC_ENABLE_VPID
|
3765 SECONDARY_EXEC_ENABLE_EPT
|
3766 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3767 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3768 SECONDARY_EXEC_RDTSCP
|
3769 SECONDARY_EXEC_ENABLE_INVPCID
|
3770 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3771 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3772 SECONDARY_EXEC_SHADOW_VMCS
|
3773 SECONDARY_EXEC_XSAVES
|
3774 SECONDARY_EXEC_RDSEED_EXITING
|
3775 SECONDARY_EXEC_RDRAND_EXITING
|
3776 SECONDARY_EXEC_ENABLE_PML
|
3777 SECONDARY_EXEC_TSC_SCALING
|
3778 SECONDARY_EXEC_ENABLE_VMFUNC
;
3779 if (adjust_vmx_controls(min2
, opt2
,
3780 MSR_IA32_VMX_PROCBASED_CTLS2
,
3781 &_cpu_based_2nd_exec_control
) < 0)
3784 #ifndef CONFIG_X86_64
3785 if (!(_cpu_based_2nd_exec_control
&
3786 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3787 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3790 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3791 _cpu_based_2nd_exec_control
&= ~(
3792 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3793 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3794 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3796 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3797 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3799 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3800 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3802 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3803 CPU_BASED_CR3_STORE_EXITING
|
3804 CPU_BASED_INVLPG_EXITING
);
3805 } else if (vmx_capability
.ept
) {
3806 vmx_capability
.ept
= 0;
3807 pr_warn_once("EPT CAP should not exist if not support "
3808 "1-setting enable EPT VM-execution control\n");
3810 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3811 vmx_capability
.vpid
) {
3812 vmx_capability
.vpid
= 0;
3813 pr_warn_once("VPID CAP should not exist if not support "
3814 "1-setting enable VPID VM-execution control\n");
3817 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3818 #ifdef CONFIG_X86_64
3819 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3821 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3822 VM_EXIT_CLEAR_BNDCFGS
;
3823 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3824 &_vmexit_control
) < 0)
3827 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3828 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3829 PIN_BASED_VMX_PREEMPTION_TIMER
;
3830 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3831 &_pin_based_exec_control
) < 0)
3834 if (cpu_has_broken_vmx_preemption_timer())
3835 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3836 if (!(_cpu_based_2nd_exec_control
&
3837 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3838 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3840 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3841 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3842 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3843 &_vmentry_control
) < 0)
3846 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3848 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3849 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3852 #ifdef CONFIG_X86_64
3853 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3854 if (vmx_msr_high
& (1u<<16))
3858 /* Require Write-Back (WB) memory type for VMCS accesses. */
3859 if (((vmx_msr_high
>> 18) & 15) != 6)
3862 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3863 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3864 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3865 vmcs_conf
->revision_id
= vmx_msr_low
;
3867 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3868 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3869 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3870 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3871 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3873 cpu_has_load_ia32_efer
=
3874 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3875 VM_ENTRY_LOAD_IA32_EFER
)
3876 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3877 VM_EXIT_LOAD_IA32_EFER
);
3879 cpu_has_load_perf_global_ctrl
=
3880 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3881 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3882 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3886 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3887 * but due to errata below it can't be used. Workaround is to use
3888 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3890 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3895 * BC86,AAY89,BD102 (model 44)
3899 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3900 switch (boot_cpu_data
.x86_model
) {
3906 cpu_has_load_perf_global_ctrl
= false;
3907 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3908 "does not work properly. Using workaround\n");
3915 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3916 rdmsrl(MSR_IA32_XSS
, host_xss
);
3921 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3923 int node
= cpu_to_node(cpu
);
3927 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3930 vmcs
= page_address(pages
);
3931 memset(vmcs
, 0, vmcs_config
.size
);
3932 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3936 static void free_vmcs(struct vmcs
*vmcs
)
3938 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3942 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3944 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3946 if (!loaded_vmcs
->vmcs
)
3948 loaded_vmcs_clear(loaded_vmcs
);
3949 free_vmcs(loaded_vmcs
->vmcs
);
3950 loaded_vmcs
->vmcs
= NULL
;
3951 if (loaded_vmcs
->msr_bitmap
)
3952 free_page((unsigned long)loaded_vmcs
->msr_bitmap
);
3953 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3956 static struct vmcs
*alloc_vmcs(void)
3958 return alloc_vmcs_cpu(raw_smp_processor_id());
3961 static int alloc_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3963 loaded_vmcs
->vmcs
= alloc_vmcs();
3964 if (!loaded_vmcs
->vmcs
)
3967 loaded_vmcs
->shadow_vmcs
= NULL
;
3968 loaded_vmcs_init(loaded_vmcs
);
3970 if (cpu_has_vmx_msr_bitmap()) {
3971 loaded_vmcs
->msr_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3972 if (!loaded_vmcs
->msr_bitmap
)
3974 memset(loaded_vmcs
->msr_bitmap
, 0xff, PAGE_SIZE
);
3979 free_loaded_vmcs(loaded_vmcs
);
3983 static void free_kvm_area(void)
3987 for_each_possible_cpu(cpu
) {
3988 free_vmcs(per_cpu(vmxarea
, cpu
));
3989 per_cpu(vmxarea
, cpu
) = NULL
;
3993 enum vmcs_field_type
{
3994 VMCS_FIELD_TYPE_U16
= 0,
3995 VMCS_FIELD_TYPE_U64
= 1,
3996 VMCS_FIELD_TYPE_U32
= 2,
3997 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
4000 static inline int vmcs_field_type(unsigned long field
)
4002 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
4003 return VMCS_FIELD_TYPE_U32
;
4004 return (field
>> 13) & 0x3 ;
4007 static inline int vmcs_field_readonly(unsigned long field
)
4009 return (((field
>> 10) & 0x3) == 1);
4012 static void init_vmcs_shadow_fields(void)
4016 /* No checks for read only fields yet */
4018 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
4019 switch (shadow_read_write_fields
[i
]) {
4021 if (!kvm_mpx_supported())
4029 shadow_read_write_fields
[j
] =
4030 shadow_read_write_fields
[i
];
4033 max_shadow_read_write_fields
= j
;
4035 /* shadowed fields guest access without vmexit */
4036 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
4037 unsigned long field
= shadow_read_write_fields
[i
];
4039 clear_bit(field
, vmx_vmwrite_bitmap
);
4040 clear_bit(field
, vmx_vmread_bitmap
);
4041 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
4042 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
4043 clear_bit(field
+ 1, vmx_vmread_bitmap
);
4046 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
4047 unsigned long field
= shadow_read_only_fields
[i
];
4049 clear_bit(field
, vmx_vmread_bitmap
);
4050 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
4051 clear_bit(field
+ 1, vmx_vmread_bitmap
);
4055 static __init
int alloc_kvm_area(void)
4059 for_each_possible_cpu(cpu
) {
4062 vmcs
= alloc_vmcs_cpu(cpu
);
4068 per_cpu(vmxarea
, cpu
) = vmcs
;
4073 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
4074 struct kvm_segment
*save
)
4076 if (!emulate_invalid_guest_state
) {
4078 * CS and SS RPL should be equal during guest entry according
4079 * to VMX spec, but in reality it is not always so. Since vcpu
4080 * is in the middle of the transition from real mode to
4081 * protected mode it is safe to assume that RPL 0 is a good
4084 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
4085 save
->selector
&= ~SEGMENT_RPL_MASK
;
4086 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
4089 vmx_set_segment(vcpu
, save
, seg
);
4092 static void enter_pmode(struct kvm_vcpu
*vcpu
)
4094 unsigned long flags
;
4095 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4098 * Update real mode segment cache. It may be not up-to-date if sement
4099 * register was written while vcpu was in a guest mode.
4101 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4102 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4103 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4104 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4105 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4106 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4108 vmx
->rmode
.vm86_active
= 0;
4110 vmx_segment_cache_clear(vmx
);
4112 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4114 flags
= vmcs_readl(GUEST_RFLAGS
);
4115 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
4116 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
4117 vmcs_writel(GUEST_RFLAGS
, flags
);
4119 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
4120 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
4122 update_exception_bitmap(vcpu
);
4124 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4125 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4126 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4127 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4128 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4129 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4132 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4134 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4135 struct kvm_segment var
= *save
;
4138 if (seg
== VCPU_SREG_CS
)
4141 if (!emulate_invalid_guest_state
) {
4142 var
.selector
= var
.base
>> 4;
4143 var
.base
= var
.base
& 0xffff0;
4153 if (save
->base
& 0xf)
4154 printk_once(KERN_WARNING
"kvm: segment base is not "
4155 "paragraph aligned when entering "
4156 "protected mode (seg=%d)", seg
);
4159 vmcs_write16(sf
->selector
, var
.selector
);
4160 vmcs_writel(sf
->base
, var
.base
);
4161 vmcs_write32(sf
->limit
, var
.limit
);
4162 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4165 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4167 unsigned long flags
;
4168 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4170 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4171 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4172 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4173 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4174 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4175 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4176 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4178 vmx
->rmode
.vm86_active
= 1;
4181 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4182 * vcpu. Warn the user that an update is overdue.
4184 if (!vcpu
->kvm
->arch
.tss_addr
)
4185 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4186 "called before entering vcpu\n");
4188 vmx_segment_cache_clear(vmx
);
4190 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4191 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4192 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4194 flags
= vmcs_readl(GUEST_RFLAGS
);
4195 vmx
->rmode
.save_rflags
= flags
;
4197 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4199 vmcs_writel(GUEST_RFLAGS
, flags
);
4200 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4201 update_exception_bitmap(vcpu
);
4203 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4204 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4205 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4206 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4207 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4208 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4210 kvm_mmu_reset_context(vcpu
);
4213 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4215 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4216 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4222 * Force kernel_gs_base reloading before EFER changes, as control
4223 * of this msr depends on is_long_mode().
4225 vmx_load_host_state(to_vmx(vcpu
));
4226 vcpu
->arch
.efer
= efer
;
4227 if (efer
& EFER_LMA
) {
4228 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4231 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4233 msr
->data
= efer
& ~EFER_LME
;
4238 #ifdef CONFIG_X86_64
4240 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4244 vmx_segment_cache_clear(to_vmx(vcpu
));
4246 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4247 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4248 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4250 vmcs_write32(GUEST_TR_AR_BYTES
,
4251 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4252 | VMX_AR_TYPE_BUSY_64_TSS
);
4254 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4257 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4259 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4260 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4265 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4268 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4270 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4272 vpid_sync_context(vpid
);
4276 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4278 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4281 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4284 vmx_flush_tlb(vcpu
);
4287 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4289 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4291 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4292 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4295 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4297 if (enable_ept
&& is_paging(vcpu
))
4298 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4299 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4302 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4304 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4306 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4307 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4310 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4312 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4314 if (!test_bit(VCPU_EXREG_PDPTR
,
4315 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4318 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4319 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4320 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4321 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4322 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4326 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4328 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4330 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4331 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4332 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4333 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4334 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4337 __set_bit(VCPU_EXREG_PDPTR
,
4338 (unsigned long *)&vcpu
->arch
.regs_avail
);
4339 __set_bit(VCPU_EXREG_PDPTR
,
4340 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4343 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4345 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4346 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4347 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4349 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4350 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4351 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4352 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4354 return fixed_bits_valid(val
, fixed0
, fixed1
);
4357 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4359 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4360 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4362 return fixed_bits_valid(val
, fixed0
, fixed1
);
4365 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4367 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4368 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4370 return fixed_bits_valid(val
, fixed0
, fixed1
);
4373 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4374 #define nested_guest_cr4_valid nested_cr4_valid
4375 #define nested_host_cr4_valid nested_cr4_valid
4377 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4379 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4381 struct kvm_vcpu
*vcpu
)
4383 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4384 vmx_decache_cr3(vcpu
);
4385 if (!(cr0
& X86_CR0_PG
)) {
4386 /* From paging/starting to nonpaging */
4387 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4388 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4389 (CPU_BASED_CR3_LOAD_EXITING
|
4390 CPU_BASED_CR3_STORE_EXITING
));
4391 vcpu
->arch
.cr0
= cr0
;
4392 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4393 } else if (!is_paging(vcpu
)) {
4394 /* From nonpaging to paging */
4395 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4396 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4397 ~(CPU_BASED_CR3_LOAD_EXITING
|
4398 CPU_BASED_CR3_STORE_EXITING
));
4399 vcpu
->arch
.cr0
= cr0
;
4400 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4403 if (!(cr0
& X86_CR0_WP
))
4404 *hw_cr0
&= ~X86_CR0_WP
;
4407 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4409 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4410 unsigned long hw_cr0
;
4412 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4413 if (enable_unrestricted_guest
)
4414 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4416 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4418 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4421 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4425 #ifdef CONFIG_X86_64
4426 if (vcpu
->arch
.efer
& EFER_LME
) {
4427 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4429 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4435 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4437 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4438 vmcs_writel(GUEST_CR0
, hw_cr0
);
4439 vcpu
->arch
.cr0
= cr0
;
4441 /* depends on vcpu->arch.cr0 to be set to a new value */
4442 vmx
->emulation_required
= emulation_required(vcpu
);
4445 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4447 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4452 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4454 u64 eptp
= VMX_EPTP_MT_WB
;
4456 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4458 if (enable_ept_ad_bits
&&
4459 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4460 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4461 eptp
|= (root_hpa
& PAGE_MASK
);
4466 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4468 unsigned long guest_cr3
;
4473 eptp
= construct_eptp(vcpu
, cr3
);
4474 vmcs_write64(EPT_POINTER
, eptp
);
4475 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4476 guest_cr3
= kvm_read_cr3(vcpu
);
4478 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4479 ept_load_pdptrs(vcpu
);
4482 vmx_flush_tlb(vcpu
);
4483 vmcs_writel(GUEST_CR3
, guest_cr3
);
4486 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4489 * Pass through host's Machine Check Enable value to hw_cr4, which
4490 * is in force while we are in guest mode. Do not let guests control
4491 * this bit, even if host CR4.MCE == 0.
4493 unsigned long hw_cr4
=
4494 (cr4_read_shadow() & X86_CR4_MCE
) |
4495 (cr4
& ~X86_CR4_MCE
) |
4496 (to_vmx(vcpu
)->rmode
.vm86_active
?
4497 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4499 if (cr4
& X86_CR4_VMXE
) {
4501 * To use VMXON (and later other VMX instructions), a guest
4502 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4503 * So basically the check on whether to allow nested VMX
4506 if (!nested_vmx_allowed(vcpu
))
4510 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4513 vcpu
->arch
.cr4
= cr4
;
4515 if (!is_paging(vcpu
)) {
4516 hw_cr4
&= ~X86_CR4_PAE
;
4517 hw_cr4
|= X86_CR4_PSE
;
4518 } else if (!(cr4
& X86_CR4_PAE
)) {
4519 hw_cr4
&= ~X86_CR4_PAE
;
4523 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4525 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4526 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4527 * to be manually disabled when guest switches to non-paging
4530 * If !enable_unrestricted_guest, the CPU is always running
4531 * with CR0.PG=1 and CR4 needs to be modified.
4532 * If enable_unrestricted_guest, the CPU automatically
4533 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4535 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4537 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4538 vmcs_writel(GUEST_CR4
, hw_cr4
);
4542 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4543 struct kvm_segment
*var
, int seg
)
4545 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4548 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4549 *var
= vmx
->rmode
.segs
[seg
];
4550 if (seg
== VCPU_SREG_TR
4551 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4553 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4554 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4557 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4558 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4559 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4560 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4561 var
->unusable
= (ar
>> 16) & 1;
4562 var
->type
= ar
& 15;
4563 var
->s
= (ar
>> 4) & 1;
4564 var
->dpl
= (ar
>> 5) & 3;
4566 * Some userspaces do not preserve unusable property. Since usable
4567 * segment has to be present according to VMX spec we can use present
4568 * property to amend userspace bug by making unusable segment always
4569 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4570 * segment as unusable.
4572 var
->present
= !var
->unusable
;
4573 var
->avl
= (ar
>> 12) & 1;
4574 var
->l
= (ar
>> 13) & 1;
4575 var
->db
= (ar
>> 14) & 1;
4576 var
->g
= (ar
>> 15) & 1;
4579 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4581 struct kvm_segment s
;
4583 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4584 vmx_get_segment(vcpu
, &s
, seg
);
4587 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4590 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4592 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4594 if (unlikely(vmx
->rmode
.vm86_active
))
4597 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4598 return VMX_AR_DPL(ar
);
4602 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4606 if (var
->unusable
|| !var
->present
)
4609 ar
= var
->type
& 15;
4610 ar
|= (var
->s
& 1) << 4;
4611 ar
|= (var
->dpl
& 3) << 5;
4612 ar
|= (var
->present
& 1) << 7;
4613 ar
|= (var
->avl
& 1) << 12;
4614 ar
|= (var
->l
& 1) << 13;
4615 ar
|= (var
->db
& 1) << 14;
4616 ar
|= (var
->g
& 1) << 15;
4622 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4623 struct kvm_segment
*var
, int seg
)
4625 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4626 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4628 vmx_segment_cache_clear(vmx
);
4630 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4631 vmx
->rmode
.segs
[seg
] = *var
;
4632 if (seg
== VCPU_SREG_TR
)
4633 vmcs_write16(sf
->selector
, var
->selector
);
4635 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4639 vmcs_writel(sf
->base
, var
->base
);
4640 vmcs_write32(sf
->limit
, var
->limit
);
4641 vmcs_write16(sf
->selector
, var
->selector
);
4644 * Fix the "Accessed" bit in AR field of segment registers for older
4646 * IA32 arch specifies that at the time of processor reset the
4647 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4648 * is setting it to 0 in the userland code. This causes invalid guest
4649 * state vmexit when "unrestricted guest" mode is turned on.
4650 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4651 * tree. Newer qemu binaries with that qemu fix would not need this
4654 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4655 var
->type
|= 0x1; /* Accessed */
4657 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4660 vmx
->emulation_required
= emulation_required(vcpu
);
4663 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4665 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4667 *db
= (ar
>> 14) & 1;
4668 *l
= (ar
>> 13) & 1;
4671 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4673 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4674 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4677 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4679 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4680 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4683 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4685 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4686 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4689 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4691 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4692 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4695 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4697 struct kvm_segment var
;
4700 vmx_get_segment(vcpu
, &var
, seg
);
4702 if (seg
== VCPU_SREG_CS
)
4704 ar
= vmx_segment_access_rights(&var
);
4706 if (var
.base
!= (var
.selector
<< 4))
4708 if (var
.limit
!= 0xffff)
4716 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4718 struct kvm_segment cs
;
4719 unsigned int cs_rpl
;
4721 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4722 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4726 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4730 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4731 if (cs
.dpl
> cs_rpl
)
4734 if (cs
.dpl
!= cs_rpl
)
4740 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4744 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4746 struct kvm_segment ss
;
4747 unsigned int ss_rpl
;
4749 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4750 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4754 if (ss
.type
!= 3 && ss
.type
!= 7)
4758 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4766 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4768 struct kvm_segment var
;
4771 vmx_get_segment(vcpu
, &var
, seg
);
4772 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4780 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4781 if (var
.dpl
< rpl
) /* DPL < RPL */
4785 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4791 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4793 struct kvm_segment tr
;
4795 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4799 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4801 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4809 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4811 struct kvm_segment ldtr
;
4813 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4817 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4827 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4829 struct kvm_segment cs
, ss
;
4831 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4832 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4834 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4835 (ss
.selector
& SEGMENT_RPL_MASK
));
4839 * Check if guest state is valid. Returns true if valid, false if
4841 * We assume that registers are always usable
4843 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4845 if (enable_unrestricted_guest
)
4848 /* real mode guest state checks */
4849 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4850 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4852 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4854 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4856 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4858 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4860 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4863 /* protected mode guest state checks */
4864 if (!cs_ss_rpl_check(vcpu
))
4866 if (!code_segment_valid(vcpu
))
4868 if (!stack_segment_valid(vcpu
))
4870 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4872 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4874 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4876 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4878 if (!tr_valid(vcpu
))
4880 if (!ldtr_valid(vcpu
))
4884 * - Add checks on RIP
4885 * - Add checks on RFLAGS
4891 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4893 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4896 static int init_rmode_tss(struct kvm
*kvm
)
4902 idx
= srcu_read_lock(&kvm
->srcu
);
4903 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4904 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4907 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4908 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4909 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4912 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4915 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4919 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4920 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4923 srcu_read_unlock(&kvm
->srcu
, idx
);
4927 static int init_rmode_identity_map(struct kvm
*kvm
)
4930 kvm_pfn_t identity_map_pfn
;
4933 /* Protect kvm->arch.ept_identity_pagetable_done. */
4934 mutex_lock(&kvm
->slots_lock
);
4936 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4939 if (!kvm
->arch
.ept_identity_map_addr
)
4940 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4941 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4943 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4944 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4948 idx
= srcu_read_lock(&kvm
->srcu
);
4949 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4952 /* Set up identity-mapping pagetable for EPT in real mode */
4953 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4954 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4955 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4956 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4957 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4961 kvm
->arch
.ept_identity_pagetable_done
= true;
4964 srcu_read_unlock(&kvm
->srcu
, idx
);
4967 mutex_unlock(&kvm
->slots_lock
);
4971 static void seg_setup(int seg
)
4973 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4976 vmcs_write16(sf
->selector
, 0);
4977 vmcs_writel(sf
->base
, 0);
4978 vmcs_write32(sf
->limit
, 0xffff);
4980 if (seg
== VCPU_SREG_CS
)
4981 ar
|= 0x08; /* code segment */
4983 vmcs_write32(sf
->ar_bytes
, ar
);
4986 static int alloc_apic_access_page(struct kvm
*kvm
)
4991 mutex_lock(&kvm
->slots_lock
);
4992 if (kvm
->arch
.apic_access_page_done
)
4994 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4995 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4999 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
5000 if (is_error_page(page
)) {
5006 * Do not pin the page in memory, so that memory hot-unplug
5007 * is able to migrate it.
5010 kvm
->arch
.apic_access_page_done
= true;
5012 mutex_unlock(&kvm
->slots_lock
);
5016 static int allocate_vpid(void)
5022 spin_lock(&vmx_vpid_lock
);
5023 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
5024 if (vpid
< VMX_NR_VPIDS
)
5025 __set_bit(vpid
, vmx_vpid_bitmap
);
5028 spin_unlock(&vmx_vpid_lock
);
5032 static void free_vpid(int vpid
)
5034 if (!enable_vpid
|| vpid
== 0)
5036 spin_lock(&vmx_vpid_lock
);
5037 __clear_bit(vpid
, vmx_vpid_bitmap
);
5038 spin_unlock(&vmx_vpid_lock
);
5041 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
5044 int f
= sizeof(unsigned long);
5046 if (!cpu_has_vmx_msr_bitmap())
5050 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5051 * have the write-low and read-high bitmap offsets the wrong way round.
5052 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5054 if (msr
<= 0x1fff) {
5055 if (type
& MSR_TYPE_R
)
5057 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
5059 if (type
& MSR_TYPE_W
)
5061 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
5063 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5065 if (type
& MSR_TYPE_R
)
5067 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
5069 if (type
& MSR_TYPE_W
)
5071 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5076 static void __always_inline
vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
5079 int f
= sizeof(unsigned long);
5081 if (!cpu_has_vmx_msr_bitmap())
5085 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5086 * have the write-low and read-high bitmap offsets the wrong way round.
5087 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5089 if (msr
<= 0x1fff) {
5090 if (type
& MSR_TYPE_R
)
5092 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
5094 if (type
& MSR_TYPE_W
)
5096 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
5098 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5100 if (type
& MSR_TYPE_R
)
5102 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
5104 if (type
& MSR_TYPE_W
)
5106 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5111 static void __always_inline
vmx_set_intercept_for_msr(unsigned long *msr_bitmap
,
5112 u32 msr
, int type
, bool value
)
5115 vmx_enable_intercept_for_msr(msr_bitmap
, msr
, type
);
5117 vmx_disable_intercept_for_msr(msr_bitmap
, msr
, type
);
5121 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5122 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5124 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
5125 unsigned long *msr_bitmap_nested
,
5128 int f
= sizeof(unsigned long);
5130 if (!cpu_has_vmx_msr_bitmap()) {
5136 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5137 * have the write-low and read-high bitmap offsets the wrong way round.
5138 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5140 if (msr
<= 0x1fff) {
5141 if (type
& MSR_TYPE_R
&&
5142 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
5144 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
5146 if (type
& MSR_TYPE_W
&&
5147 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
5149 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
5151 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5153 if (type
& MSR_TYPE_R
&&
5154 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
5156 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
5158 if (type
& MSR_TYPE_W
&&
5159 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
5161 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
5166 static u8
vmx_msr_bitmap_mode(struct kvm_vcpu
*vcpu
)
5170 if (cpu_has_secondary_exec_ctrls() &&
5171 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
5172 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
5173 mode
|= MSR_BITMAP_MODE_X2APIC
;
5174 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
))
5175 mode
|= MSR_BITMAP_MODE_X2APIC_APICV
;
5178 if (is_long_mode(vcpu
))
5179 mode
|= MSR_BITMAP_MODE_LM
;
5184 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5186 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap
,
5191 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
5192 unsigned word
= msr
/ BITS_PER_LONG
;
5193 msr_bitmap
[word
] = (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) ? 0 : ~0;
5194 msr_bitmap
[word
+ (0x800 / sizeof(long))] = ~0;
5197 if (mode
& MSR_BITMAP_MODE_X2APIC
) {
5199 * TPR reads and writes can be virtualized even if virtual interrupt
5200 * delivery is not in use.
5202 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TASKPRI
), MSR_TYPE_RW
);
5203 if (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) {
5204 vmx_enable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TMCCT
), MSR_TYPE_R
);
5205 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_EOI
), MSR_TYPE_W
);
5206 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_SELF_IPI
), MSR_TYPE_W
);
5211 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
)
5213 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5214 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
5215 u8 mode
= vmx_msr_bitmap_mode(vcpu
);
5216 u8 changed
= mode
^ vmx
->msr_bitmap_mode
;
5221 vmx_set_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
,
5222 !(mode
& MSR_BITMAP_MODE_LM
));
5224 if (changed
& (MSR_BITMAP_MODE_X2APIC
| MSR_BITMAP_MODE_X2APIC_APICV
))
5225 vmx_update_msr_bitmap_x2apic(msr_bitmap
, mode
);
5227 vmx
->msr_bitmap_mode
= mode
;
5230 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5232 return enable_apicv
;
5235 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5237 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5241 * Don't need to mark the APIC access page dirty; it is never
5242 * written to by the CPU during APIC virtualization.
5245 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5246 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5247 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5250 if (nested_cpu_has_posted_intr(vmcs12
)) {
5251 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5252 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5257 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5259 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5264 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5267 vmx
->nested
.pi_pending
= false;
5268 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5271 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5272 if (max_irr
!= 256) {
5273 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5274 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5275 kunmap(vmx
->nested
.virtual_apic_page
);
5277 status
= vmcs_read16(GUEST_INTR_STATUS
);
5278 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5280 status
|= (u8
)max_irr
;
5281 vmcs_write16(GUEST_INTR_STATUS
, status
);
5285 nested_mark_vmcs12_pages_dirty(vcpu
);
5288 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5292 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5294 if (vcpu
->mode
== IN_GUEST_MODE
) {
5296 * The vector of interrupt to be delivered to vcpu had
5297 * been set in PIR before this function.
5299 * Following cases will be reached in this block, and
5300 * we always send a notification event in all cases as
5303 * Case 1: vcpu keeps in non-root mode. Sending a
5304 * notification event posts the interrupt to vcpu.
5306 * Case 2: vcpu exits to root mode and is still
5307 * runnable. PIR will be synced to vIRR before the
5308 * next vcpu entry. Sending a notification event in
5309 * this case has no effect, as vcpu is not in root
5312 * Case 3: vcpu exits to root mode and is blocked.
5313 * vcpu_block() has already synced PIR to vIRR and
5314 * never blocks vcpu if vIRR is not cleared. Therefore,
5315 * a blocked vcpu here does not wait for any requested
5316 * interrupts in PIR, and sending a notification event
5317 * which has no effect is safe here.
5320 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5327 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5330 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5332 if (is_guest_mode(vcpu
) &&
5333 vector
== vmx
->nested
.posted_intr_nv
) {
5335 * If a posted intr is not recognized by hardware,
5336 * we will accomplish it in the next vmentry.
5338 vmx
->nested
.pi_pending
= true;
5339 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5340 /* the PIR and ON have been set by L1. */
5341 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, true))
5342 kvm_vcpu_kick(vcpu
);
5348 * Send interrupt to vcpu via posted interrupt way.
5349 * 1. If target vcpu is running(non-root mode), send posted interrupt
5350 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5351 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5352 * interrupt from PIR in next vmentry.
5354 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5356 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5359 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5363 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5366 /* If a previous notification has sent the IPI, nothing to do. */
5367 if (pi_test_and_set_on(&vmx
->pi_desc
))
5370 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5371 kvm_vcpu_kick(vcpu
);
5375 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5376 * will not change in the lifetime of the guest.
5377 * Note that host-state that does change is set elsewhere. E.g., host-state
5378 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5380 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5385 unsigned long cr0
, cr3
, cr4
;
5388 WARN_ON(cr0
& X86_CR0_TS
);
5389 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5392 * Save the most likely value for this task's CR3 in the VMCS.
5393 * We can't use __get_current_cr3_fast() because we're not atomic.
5396 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5397 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5399 /* Save the most likely value for this task's CR4 in the VMCS. */
5400 cr4
= cr4_read_shadow();
5401 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5402 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5404 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5405 #ifdef CONFIG_X86_64
5407 * Load null selectors, so we can avoid reloading them in
5408 * __vmx_load_host_state(), in case userspace uses the null selectors
5409 * too (the expected case).
5411 vmcs_write16(HOST_DS_SELECTOR
, 0);
5412 vmcs_write16(HOST_ES_SELECTOR
, 0);
5414 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5415 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5417 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5418 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5421 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5422 vmx
->host_idt_base
= dt
.address
;
5424 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5426 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5427 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5428 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5429 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5431 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5432 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5433 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5437 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5439 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5441 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5442 if (is_guest_mode(&vmx
->vcpu
))
5443 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5444 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5445 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5448 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5450 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5452 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5453 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5456 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
5458 /* Enable the preemption timer dynamically */
5459 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5460 return pin_based_exec_ctrl
;
5463 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5465 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5467 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5468 if (cpu_has_secondary_exec_ctrls()) {
5469 if (kvm_vcpu_apicv_active(vcpu
))
5470 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5471 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5472 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5474 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5475 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5479 if (cpu_has_vmx_msr_bitmap())
5480 vmx_update_msr_bitmap(vcpu
);
5483 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5485 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5487 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5488 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5490 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5491 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5492 #ifdef CONFIG_X86_64
5493 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5494 CPU_BASED_CR8_LOAD_EXITING
;
5498 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5499 CPU_BASED_CR3_LOAD_EXITING
|
5500 CPU_BASED_INVLPG_EXITING
;
5501 return exec_control
;
5504 static bool vmx_rdrand_supported(void)
5506 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5507 SECONDARY_EXEC_RDRAND_EXITING
;
5510 static bool vmx_rdseed_supported(void)
5512 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5513 SECONDARY_EXEC_RDSEED_EXITING
;
5516 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5518 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5520 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5521 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5522 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5524 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5526 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5527 enable_unrestricted_guest
= 0;
5528 /* Enable INVPCID for non-ept guests may cause performance regression. */
5529 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5531 if (!enable_unrestricted_guest
)
5532 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5534 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5535 if (!kvm_vcpu_apicv_active(vcpu
))
5536 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5537 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5538 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5539 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5541 We can NOT enable shadow_vmcs here because we don't have yet
5544 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5547 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5549 if (vmx_xsaves_supported()) {
5550 /* Exposing XSAVES only when XSAVE is exposed */
5551 bool xsaves_enabled
=
5552 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5553 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5555 if (!xsaves_enabled
)
5556 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5560 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5561 SECONDARY_EXEC_XSAVES
;
5563 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5564 ~SECONDARY_EXEC_XSAVES
;
5568 if (vmx_rdtscp_supported()) {
5569 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5570 if (!rdtscp_enabled
)
5571 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5575 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5576 SECONDARY_EXEC_RDTSCP
;
5578 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5579 ~SECONDARY_EXEC_RDTSCP
;
5583 if (vmx_invpcid_supported()) {
5584 /* Exposing INVPCID only when PCID is exposed */
5585 bool invpcid_enabled
=
5586 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5587 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5589 if (!invpcid_enabled
) {
5590 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5591 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5595 if (invpcid_enabled
)
5596 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5597 SECONDARY_EXEC_ENABLE_INVPCID
;
5599 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5600 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5604 if (vmx_rdrand_supported()) {
5605 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5607 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5611 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5612 SECONDARY_EXEC_RDRAND_EXITING
;
5614 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5615 ~SECONDARY_EXEC_RDRAND_EXITING
;
5619 if (vmx_rdseed_supported()) {
5620 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5622 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5626 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5627 SECONDARY_EXEC_RDSEED_EXITING
;
5629 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5630 ~SECONDARY_EXEC_RDSEED_EXITING
;
5634 vmx
->secondary_exec_control
= exec_control
;
5637 static void ept_set_mmio_spte_mask(void)
5640 * EPT Misconfigurations can be generated if the value of bits 2:0
5641 * of an EPT paging-structure entry is 110b (write/execute).
5643 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5644 VMX_EPT_MISCONFIG_WX_VALUE
);
5647 #define VMX_XSS_EXIT_BITMAP 0
5649 * Sets up the vmcs for emulated real mode.
5651 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5653 #ifdef CONFIG_X86_64
5659 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5660 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5662 if (enable_shadow_vmcs
) {
5663 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5664 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5666 if (cpu_has_vmx_msr_bitmap())
5667 vmcs_write64(MSR_BITMAP
, __pa(vmx
->vmcs01
.msr_bitmap
));
5669 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5672 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5673 vmx
->hv_deadline_tsc
= -1;
5675 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5677 if (cpu_has_secondary_exec_ctrls()) {
5678 vmx_compute_secondary_exec_control(vmx
);
5679 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5680 vmx
->secondary_exec_control
);
5683 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5684 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5685 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5686 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5687 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5689 vmcs_write16(GUEST_INTR_STATUS
, 0);
5691 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5692 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5696 vmcs_write32(PLE_GAP
, ple_gap
);
5697 vmx
->ple_window
= ple_window
;
5698 vmx
->ple_window_dirty
= true;
5701 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5702 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5703 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5705 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5706 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5707 vmx_set_constant_host_state(vmx
);
5708 #ifdef CONFIG_X86_64
5709 rdmsrl(MSR_FS_BASE
, a
);
5710 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5711 rdmsrl(MSR_GS_BASE
, a
);
5712 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5714 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5715 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5718 if (cpu_has_vmx_vmfunc())
5719 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5721 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5722 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5723 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5724 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5725 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5727 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5728 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5730 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5731 u32 index
= vmx_msr_index
[i
];
5732 u32 data_low
, data_high
;
5735 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5737 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5739 vmx
->guest_msrs
[j
].index
= i
;
5740 vmx
->guest_msrs
[j
].data
= 0;
5741 vmx
->guest_msrs
[j
].mask
= -1ull;
5745 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
5746 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, vmx
->arch_capabilities
);
5748 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5750 /* 22.2.1, 20.8.1 */
5751 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5753 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5754 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5756 set_cr4_guest_host_mask(vmx
);
5758 if (vmx_xsaves_supported())
5759 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5762 ASSERT(vmx
->pml_pg
);
5763 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5764 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5768 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5770 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5771 struct msr_data apic_base_msr
;
5774 vmx
->rmode
.vm86_active
= 0;
5777 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5778 kvm_set_cr8(vcpu
, 0);
5781 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5782 MSR_IA32_APICBASE_ENABLE
;
5783 if (kvm_vcpu_is_reset_bsp(vcpu
))
5784 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5785 apic_base_msr
.host_initiated
= true;
5786 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5789 vmx_segment_cache_clear(vmx
);
5791 seg_setup(VCPU_SREG_CS
);
5792 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5793 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5795 seg_setup(VCPU_SREG_DS
);
5796 seg_setup(VCPU_SREG_ES
);
5797 seg_setup(VCPU_SREG_FS
);
5798 seg_setup(VCPU_SREG_GS
);
5799 seg_setup(VCPU_SREG_SS
);
5801 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5802 vmcs_writel(GUEST_TR_BASE
, 0);
5803 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5804 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5806 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5807 vmcs_writel(GUEST_LDTR_BASE
, 0);
5808 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5809 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5812 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5813 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5814 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5815 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5818 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
5819 kvm_rip_write(vcpu
, 0xfff0);
5821 vmcs_writel(GUEST_GDTR_BASE
, 0);
5822 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5824 vmcs_writel(GUEST_IDTR_BASE
, 0);
5825 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5827 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5828 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5829 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5830 if (kvm_mpx_supported())
5831 vmcs_write64(GUEST_BNDCFGS
, 0);
5835 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5837 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5838 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5839 if (cpu_need_tpr_shadow(vcpu
))
5840 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5841 __pa(vcpu
->arch
.apic
->regs
));
5842 vmcs_write32(TPR_THRESHOLD
, 0);
5845 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5848 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5850 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5851 vmx
->vcpu
.arch
.cr0
= cr0
;
5852 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5853 vmx_set_cr4(vcpu
, 0);
5854 vmx_set_efer(vcpu
, 0);
5856 update_exception_bitmap(vcpu
);
5858 vpid_sync_context(vmx
->vpid
);
5862 * In nested virtualization, check if L1 asked to exit on external interrupts.
5863 * For most existing hypervisors, this will always return true.
5865 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5867 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5868 PIN_BASED_EXT_INTR_MASK
;
5872 * In nested virtualization, check if L1 has set
5873 * VM_EXIT_ACK_INTR_ON_EXIT
5875 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5877 return get_vmcs12(vcpu
)->vm_exit_controls
&
5878 VM_EXIT_ACK_INTR_ON_EXIT
;
5881 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5883 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5884 PIN_BASED_NMI_EXITING
;
5887 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5889 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5890 CPU_BASED_VIRTUAL_INTR_PENDING
);
5893 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5896 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5897 enable_irq_window(vcpu
);
5901 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5902 CPU_BASED_VIRTUAL_NMI_PENDING
);
5905 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5907 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5909 int irq
= vcpu
->arch
.interrupt
.nr
;
5911 trace_kvm_inj_virq(irq
);
5913 ++vcpu
->stat
.irq_injections
;
5914 if (vmx
->rmode
.vm86_active
) {
5916 if (vcpu
->arch
.interrupt
.soft
)
5917 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5918 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5919 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5922 intr
= irq
| INTR_INFO_VALID_MASK
;
5923 if (vcpu
->arch
.interrupt
.soft
) {
5924 intr
|= INTR_TYPE_SOFT_INTR
;
5925 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5926 vmx
->vcpu
.arch
.event_exit_inst_len
);
5928 intr
|= INTR_TYPE_EXT_INTR
;
5929 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5932 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5934 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5938 * Tracking the NMI-blocked state in software is built upon
5939 * finding the next open IRQ window. This, in turn, depends on
5940 * well-behaving guests: They have to keep IRQs disabled at
5941 * least as long as the NMI handler runs. Otherwise we may
5942 * cause NMI nesting, maybe breaking the guest. But as this is
5943 * highly unlikely, we can live with the residual risk.
5945 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5946 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5949 ++vcpu
->stat
.nmi_injections
;
5950 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5952 if (vmx
->rmode
.vm86_active
) {
5953 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5954 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5958 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5959 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5962 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5968 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5969 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5971 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5972 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5976 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5978 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5981 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5982 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5983 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5986 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5988 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5989 GUEST_INTR_STATE_NMI
);
5991 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5992 GUEST_INTR_STATE_NMI
);
5996 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5998 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
6002 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
6005 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6006 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
6007 | GUEST_INTR_STATE_NMI
));
6010 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
6012 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
6013 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
6014 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6015 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
6018 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
6022 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
6026 kvm
->arch
.tss_addr
= addr
;
6027 return init_rmode_tss(kvm
);
6030 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
6035 * Update instruction length as we may reinject the exception
6036 * from user space while in guest debugging mode.
6038 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
6039 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6040 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
6044 if (vcpu
->guest_debug
&
6045 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
6062 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
6063 int vec
, u32 err_code
)
6066 * Instruction with address size override prefix opcode 0x67
6067 * Cause the #SS fault with 0 error code in VM86 mode.
6069 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
6070 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
6071 if (vcpu
->arch
.halt_request
) {
6072 vcpu
->arch
.halt_request
= 0;
6073 return kvm_vcpu_halt(vcpu
);
6081 * Forward all other exceptions that are valid in real mode.
6082 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6083 * the required debugging infrastructure rework.
6085 kvm_queue_exception(vcpu
, vec
);
6090 * Trigger machine check on the host. We assume all the MSRs are already set up
6091 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6092 * We pass a fake environment to the machine check handler because we want
6093 * the guest to be always treated like user space, no matter what context
6094 * it used internally.
6096 static void kvm_machine_check(void)
6098 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6099 struct pt_regs regs
= {
6100 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
6101 .flags
= X86_EFLAGS_IF
,
6104 do_machine_check(®s
, 0);
6108 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
6110 /* already handled by vcpu_run */
6114 static int handle_exception(struct kvm_vcpu
*vcpu
)
6116 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6117 struct kvm_run
*kvm_run
= vcpu
->run
;
6118 u32 intr_info
, ex_no
, error_code
;
6119 unsigned long cr2
, rip
, dr6
;
6121 enum emulation_result er
;
6123 vect_info
= vmx
->idt_vectoring_info
;
6124 intr_info
= vmx
->exit_intr_info
;
6126 if (is_machine_check(intr_info
))
6127 return handle_machine_check(vcpu
);
6129 if (is_nmi(intr_info
))
6130 return 1; /* already handled by vmx_vcpu_run() */
6132 if (is_invalid_opcode(intr_info
)) {
6133 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
6134 if (er
== EMULATE_USER_EXIT
)
6136 if (er
!= EMULATE_DONE
)
6137 kvm_queue_exception(vcpu
, UD_VECTOR
);
6142 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
6143 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
6146 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6147 * MMIO, it is better to report an internal error.
6148 * See the comments in vmx_handle_exit.
6150 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
6151 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
6152 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6153 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
6154 vcpu
->run
->internal
.ndata
= 3;
6155 vcpu
->run
->internal
.data
[0] = vect_info
;
6156 vcpu
->run
->internal
.data
[1] = intr_info
;
6157 vcpu
->run
->internal
.data
[2] = error_code
;
6161 if (is_page_fault(intr_info
)) {
6162 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
6163 /* EPT won't cause page fault directly */
6164 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
6165 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
6168 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
6170 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
6171 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
6175 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
6178 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
6179 if (!(vcpu
->guest_debug
&
6180 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
6181 vcpu
->arch
.dr6
&= ~15;
6182 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
6183 if (is_icebp(intr_info
))
6184 skip_emulated_instruction(vcpu
);
6186 kvm_queue_exception(vcpu
, DB_VECTOR
);
6189 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
6190 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
6194 * Update instruction length as we may reinject #BP from
6195 * user space while in guest debugging mode. Reading it for
6196 * #DB as well causes no harm, it is not used in that case.
6198 vmx
->vcpu
.arch
.event_exit_inst_len
=
6199 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6200 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
6201 rip
= kvm_rip_read(vcpu
);
6202 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
6203 kvm_run
->debug
.arch
.exception
= ex_no
;
6206 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
6207 kvm_run
->ex
.exception
= ex_no
;
6208 kvm_run
->ex
.error_code
= error_code
;
6214 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
6216 ++vcpu
->stat
.irq_exits
;
6220 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
6222 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
6223 vcpu
->mmio_needed
= 0;
6227 static int handle_io(struct kvm_vcpu
*vcpu
)
6229 unsigned long exit_qualification
;
6230 int size
, in
, string
, ret
;
6233 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6234 string
= (exit_qualification
& 16) != 0;
6235 in
= (exit_qualification
& 8) != 0;
6237 ++vcpu
->stat
.io_exits
;
6240 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6242 port
= exit_qualification
>> 16;
6243 size
= (exit_qualification
& 7) + 1;
6245 ret
= kvm_skip_emulated_instruction(vcpu
);
6248 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6249 * KVM_EXIT_DEBUG here.
6251 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6255 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6258 * Patch in the VMCALL instruction:
6260 hypercall
[0] = 0x0f;
6261 hypercall
[1] = 0x01;
6262 hypercall
[2] = 0xc1;
6265 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6266 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6268 if (is_guest_mode(vcpu
)) {
6269 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6270 unsigned long orig_val
= val
;
6273 * We get here when L2 changed cr0 in a way that did not change
6274 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6275 * but did change L0 shadowed bits. So we first calculate the
6276 * effective cr0 value that L1 would like to write into the
6277 * hardware. It consists of the L2-owned bits from the new
6278 * value combined with the L1-owned bits from L1's guest_cr0.
6280 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6281 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6283 if (!nested_guest_cr0_valid(vcpu
, val
))
6286 if (kvm_set_cr0(vcpu
, val
))
6288 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6291 if (to_vmx(vcpu
)->nested
.vmxon
&&
6292 !nested_host_cr0_valid(vcpu
, val
))
6295 return kvm_set_cr0(vcpu
, val
);
6299 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6301 if (is_guest_mode(vcpu
)) {
6302 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6303 unsigned long orig_val
= val
;
6305 /* analogously to handle_set_cr0 */
6306 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6307 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6308 if (kvm_set_cr4(vcpu
, val
))
6310 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6313 return kvm_set_cr4(vcpu
, val
);
6316 static int handle_cr(struct kvm_vcpu
*vcpu
)
6318 unsigned long exit_qualification
, val
;
6324 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6325 cr
= exit_qualification
& 15;
6326 reg
= (exit_qualification
>> 8) & 15;
6327 switch ((exit_qualification
>> 4) & 3) {
6328 case 0: /* mov to cr */
6329 val
= kvm_register_readl(vcpu
, reg
);
6330 trace_kvm_cr_write(cr
, val
);
6333 err
= handle_set_cr0(vcpu
, val
);
6334 return kvm_complete_insn_gp(vcpu
, err
);
6336 err
= kvm_set_cr3(vcpu
, val
);
6337 return kvm_complete_insn_gp(vcpu
, err
);
6339 err
= handle_set_cr4(vcpu
, val
);
6340 return kvm_complete_insn_gp(vcpu
, err
);
6342 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6344 err
= kvm_set_cr8(vcpu
, cr8
);
6345 ret
= kvm_complete_insn_gp(vcpu
, err
);
6346 if (lapic_in_kernel(vcpu
))
6348 if (cr8_prev
<= cr8
)
6351 * TODO: we might be squashing a
6352 * KVM_GUESTDBG_SINGLESTEP-triggered
6353 * KVM_EXIT_DEBUG here.
6355 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6361 WARN_ONCE(1, "Guest should always own CR0.TS");
6362 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6363 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6364 return kvm_skip_emulated_instruction(vcpu
);
6365 case 1: /*mov from cr*/
6368 val
= kvm_read_cr3(vcpu
);
6369 kvm_register_write(vcpu
, reg
, val
);
6370 trace_kvm_cr_read(cr
, val
);
6371 return kvm_skip_emulated_instruction(vcpu
);
6373 val
= kvm_get_cr8(vcpu
);
6374 kvm_register_write(vcpu
, reg
, val
);
6375 trace_kvm_cr_read(cr
, val
);
6376 return kvm_skip_emulated_instruction(vcpu
);
6380 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6381 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6382 kvm_lmsw(vcpu
, val
);
6384 return kvm_skip_emulated_instruction(vcpu
);
6388 vcpu
->run
->exit_reason
= 0;
6389 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6390 (int)(exit_qualification
>> 4) & 3, cr
);
6394 static int handle_dr(struct kvm_vcpu
*vcpu
)
6396 unsigned long exit_qualification
;
6399 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6400 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6402 /* First, if DR does not exist, trigger UD */
6403 if (!kvm_require_dr(vcpu
, dr
))
6406 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6407 if (!kvm_require_cpl(vcpu
, 0))
6409 dr7
= vmcs_readl(GUEST_DR7
);
6412 * As the vm-exit takes precedence over the debug trap, we
6413 * need to emulate the latter, either for the host or the
6414 * guest debugging itself.
6416 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6417 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6418 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6419 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6420 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6421 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6424 vcpu
->arch
.dr6
&= ~15;
6425 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6426 kvm_queue_exception(vcpu
, DB_VECTOR
);
6431 if (vcpu
->guest_debug
== 0) {
6432 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6433 CPU_BASED_MOV_DR_EXITING
);
6436 * No more DR vmexits; force a reload of the debug registers
6437 * and reenter on this instruction. The next vmexit will
6438 * retrieve the full state of the debug registers.
6440 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6444 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6445 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6448 if (kvm_get_dr(vcpu
, dr
, &val
))
6450 kvm_register_write(vcpu
, reg
, val
);
6452 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6455 return kvm_skip_emulated_instruction(vcpu
);
6458 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6460 return vcpu
->arch
.dr6
;
6463 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6467 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6469 get_debugreg(vcpu
->arch
.db
[0], 0);
6470 get_debugreg(vcpu
->arch
.db
[1], 1);
6471 get_debugreg(vcpu
->arch
.db
[2], 2);
6472 get_debugreg(vcpu
->arch
.db
[3], 3);
6473 get_debugreg(vcpu
->arch
.dr6
, 6);
6474 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6476 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6477 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6480 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6482 vmcs_writel(GUEST_DR7
, val
);
6485 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6487 return kvm_emulate_cpuid(vcpu
);
6490 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6492 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6493 struct msr_data msr_info
;
6495 msr_info
.index
= ecx
;
6496 msr_info
.host_initiated
= false;
6497 if (vmx_get_msr(vcpu
, &msr_info
)) {
6498 trace_kvm_msr_read_ex(ecx
);
6499 kvm_inject_gp(vcpu
, 0);
6503 trace_kvm_msr_read(ecx
, msr_info
.data
);
6505 /* FIXME: handling of bits 32:63 of rax, rdx */
6506 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6507 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6508 return kvm_skip_emulated_instruction(vcpu
);
6511 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6513 struct msr_data msr
;
6514 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6515 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6516 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6520 msr
.host_initiated
= false;
6521 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6522 trace_kvm_msr_write_ex(ecx
, data
);
6523 kvm_inject_gp(vcpu
, 0);
6527 trace_kvm_msr_write(ecx
, data
);
6528 return kvm_skip_emulated_instruction(vcpu
);
6531 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6533 kvm_apic_update_ppr(vcpu
);
6537 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6539 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6540 CPU_BASED_VIRTUAL_INTR_PENDING
);
6542 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6544 ++vcpu
->stat
.irq_window_exits
;
6548 static int handle_halt(struct kvm_vcpu
*vcpu
)
6550 return kvm_emulate_halt(vcpu
);
6553 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6555 return kvm_emulate_hypercall(vcpu
);
6558 static int handle_invd(struct kvm_vcpu
*vcpu
)
6560 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6563 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6565 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6567 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6568 return kvm_skip_emulated_instruction(vcpu
);
6571 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6575 err
= kvm_rdpmc(vcpu
);
6576 return kvm_complete_insn_gp(vcpu
, err
);
6579 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6581 return kvm_emulate_wbinvd(vcpu
);
6584 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6586 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6587 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6589 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6590 return kvm_skip_emulated_instruction(vcpu
);
6594 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6596 kvm_skip_emulated_instruction(vcpu
);
6597 WARN(1, "this should never happen\n");
6601 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6603 kvm_skip_emulated_instruction(vcpu
);
6604 WARN(1, "this should never happen\n");
6608 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6610 if (likely(fasteoi
)) {
6611 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6612 int access_type
, offset
;
6614 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6615 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6617 * Sane guest uses MOV to write EOI, with written value
6618 * not cared. So make a short-circuit here by avoiding
6619 * heavy instruction emulation.
6621 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6622 (offset
== APIC_EOI
)) {
6623 kvm_lapic_set_eoi(vcpu
);
6624 return kvm_skip_emulated_instruction(vcpu
);
6627 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6630 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6632 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6633 int vector
= exit_qualification
& 0xff;
6635 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6636 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6640 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6642 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6643 u32 offset
= exit_qualification
& 0xfff;
6645 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6646 kvm_apic_write_nodecode(vcpu
, offset
);
6650 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6652 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6653 unsigned long exit_qualification
;
6654 bool has_error_code
= false;
6657 int reason
, type
, idt_v
, idt_index
;
6659 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6660 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6661 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6663 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6665 reason
= (u32
)exit_qualification
>> 30;
6666 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6668 case INTR_TYPE_NMI_INTR
:
6669 vcpu
->arch
.nmi_injected
= false;
6670 vmx_set_nmi_mask(vcpu
, true);
6672 case INTR_TYPE_EXT_INTR
:
6673 case INTR_TYPE_SOFT_INTR
:
6674 kvm_clear_interrupt_queue(vcpu
);
6676 case INTR_TYPE_HARD_EXCEPTION
:
6677 if (vmx
->idt_vectoring_info
&
6678 VECTORING_INFO_DELIVER_CODE_MASK
) {
6679 has_error_code
= true;
6681 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6684 case INTR_TYPE_SOFT_EXCEPTION
:
6685 kvm_clear_exception_queue(vcpu
);
6691 tss_selector
= exit_qualification
;
6693 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6694 type
!= INTR_TYPE_EXT_INTR
&&
6695 type
!= INTR_TYPE_NMI_INTR
))
6696 skip_emulated_instruction(vcpu
);
6698 if (kvm_task_switch(vcpu
, tss_selector
,
6699 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6700 has_error_code
, error_code
) == EMULATE_FAIL
) {
6701 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6702 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6703 vcpu
->run
->internal
.ndata
= 0;
6708 * TODO: What about debug traps on tss switch?
6709 * Are we supposed to inject them and update dr6?
6715 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6717 unsigned long exit_qualification
;
6721 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6724 * EPT violation happened while executing iret from NMI,
6725 * "blocked by NMI" bit has to be set before next VM entry.
6726 * There are errata that may cause this bit to not be set:
6729 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6731 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6732 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6734 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6735 trace_kvm_page_fault(gpa
, exit_qualification
);
6737 /* Is it a read fault? */
6738 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6739 ? PFERR_USER_MASK
: 0;
6740 /* Is it a write fault? */
6741 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6742 ? PFERR_WRITE_MASK
: 0;
6743 /* Is it a fetch fault? */
6744 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6745 ? PFERR_FETCH_MASK
: 0;
6746 /* ept page table entry is present? */
6747 error_code
|= (exit_qualification
&
6748 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6749 EPT_VIOLATION_EXECUTABLE
))
6750 ? PFERR_PRESENT_MASK
: 0;
6752 error_code
|= (exit_qualification
& 0x100) != 0 ?
6753 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6755 vcpu
->arch
.exit_qualification
= exit_qualification
;
6756 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6759 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6765 * A nested guest cannot optimize MMIO vmexits, because we have an
6766 * nGPA here instead of the required GPA.
6768 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6769 if (!is_guest_mode(vcpu
) &&
6770 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6771 trace_kvm_fast_mmio(gpa
);
6773 * Doing kvm_skip_emulated_instruction() depends on undefined
6774 * behavior: Intel's manual doesn't mandate
6775 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6776 * occurs and while on real hardware it was observed to be set,
6777 * other hypervisors (namely Hyper-V) don't set it, we end up
6778 * advancing IP with some random value. Disable fast mmio when
6779 * running nested and keep it for real hardware in hope that
6780 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6782 if (!static_cpu_has(X86_FEATURE_HYPERVISOR
))
6783 return kvm_skip_emulated_instruction(vcpu
);
6785 return x86_emulate_instruction(vcpu
, gpa
, EMULTYPE_SKIP
,
6786 NULL
, 0) == EMULATE_DONE
;
6789 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6793 /* It is the real ept misconfig */
6796 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6797 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6802 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6804 WARN_ON_ONCE(!enable_vnmi
);
6805 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6806 CPU_BASED_VIRTUAL_NMI_PENDING
);
6807 ++vcpu
->stat
.nmi_window_exits
;
6808 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6813 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6815 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6816 enum emulation_result err
= EMULATE_DONE
;
6819 bool intr_window_requested
;
6820 unsigned count
= 130;
6822 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6823 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6825 while (vmx
->emulation_required
&& count
-- != 0) {
6826 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6827 return handle_interrupt_window(&vmx
->vcpu
);
6829 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6832 err
= emulate_instruction(vcpu
, 0);
6834 if (err
== EMULATE_USER_EXIT
) {
6835 ++vcpu
->stat
.mmio_exits
;
6840 if (err
!= EMULATE_DONE
) {
6841 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6842 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6843 vcpu
->run
->internal
.ndata
= 0;
6847 if (vcpu
->arch
.halt_request
) {
6848 vcpu
->arch
.halt_request
= 0;
6849 ret
= kvm_vcpu_halt(vcpu
);
6853 if (signal_pending(current
))
6863 static int __grow_ple_window(int val
)
6865 if (ple_window_grow
< 1)
6868 val
= min(val
, ple_window_actual_max
);
6870 if (ple_window_grow
< ple_window
)
6871 val
*= ple_window_grow
;
6873 val
+= ple_window_grow
;
6878 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6883 if (modifier
< ple_window
)
6888 return max(val
, minimum
);
6891 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6894 int old
= vmx
->ple_window
;
6896 vmx
->ple_window
= __grow_ple_window(old
);
6898 if (vmx
->ple_window
!= old
)
6899 vmx
->ple_window_dirty
= true;
6901 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6904 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6906 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6907 int old
= vmx
->ple_window
;
6909 vmx
->ple_window
= __shrink_ple_window(old
,
6910 ple_window_shrink
, ple_window
);
6912 if (vmx
->ple_window
!= old
)
6913 vmx
->ple_window_dirty
= true;
6915 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6919 * ple_window_actual_max is computed to be one grow_ple_window() below
6920 * ple_window_max. (See __grow_ple_window for the reason.)
6921 * This prevents overflows, because ple_window_max is int.
6922 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6924 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6926 static void update_ple_window_actual_max(void)
6928 ple_window_actual_max
=
6929 __shrink_ple_window(max(ple_window_max
, ple_window
),
6930 ple_window_grow
, INT_MIN
);
6934 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6936 static void wakeup_handler(void)
6938 struct kvm_vcpu
*vcpu
;
6939 int cpu
= smp_processor_id();
6941 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6942 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6943 blocked_vcpu_list
) {
6944 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6946 if (pi_test_on(pi_desc
) == 1)
6947 kvm_vcpu_kick(vcpu
);
6949 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6952 void vmx_enable_tdp(void)
6954 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6955 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6956 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6957 0ull, VMX_EPT_EXECUTABLE_MASK
,
6958 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6959 VMX_EPT_RWX_MASK
, 0ull);
6961 ept_set_mmio_spte_mask();
6965 static __init
int hardware_setup(void)
6969 rdmsrl_safe(MSR_EFER
, &host_efer
);
6971 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6972 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6974 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6975 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6980 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6981 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6983 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6985 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6987 if (setup_vmcs_config(&vmcs_config
) < 0) {
6992 if (boot_cpu_has(X86_FEATURE_NX
))
6993 kvm_enable_efer_bits(EFER_NX
);
6995 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6996 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6999 if (!cpu_has_vmx_shadow_vmcs())
7000 enable_shadow_vmcs
= 0;
7001 if (enable_shadow_vmcs
)
7002 init_vmcs_shadow_fields();
7004 if (!cpu_has_vmx_ept() ||
7005 !cpu_has_vmx_ept_4levels() ||
7006 !cpu_has_vmx_ept_mt_wb() ||
7007 !cpu_has_vmx_invept_global())
7010 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
7011 enable_ept_ad_bits
= 0;
7013 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
7014 enable_unrestricted_guest
= 0;
7016 if (!cpu_has_vmx_flexpriority())
7017 flexpriority_enabled
= 0;
7019 if (!cpu_has_virtual_nmis())
7023 * set_apic_access_page_addr() is used to reload apic access
7024 * page upon invalidation. No need to do anything if not
7025 * using the APIC_ACCESS_ADDR VMCS field.
7027 if (!flexpriority_enabled
)
7028 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
7030 if (!cpu_has_vmx_tpr_shadow())
7031 kvm_x86_ops
->update_cr8_intercept
= NULL
;
7033 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
7034 kvm_disable_largepages();
7036 if (!cpu_has_vmx_ple()) {
7039 ple_window_grow
= 0;
7041 ple_window_shrink
= 0;
7044 if (!cpu_has_vmx_apicv()) {
7046 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
7049 if (cpu_has_vmx_tsc_scaling()) {
7050 kvm_has_tsc_control
= true;
7051 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
7052 kvm_tsc_scaling_ratio_frac_bits
= 48;
7055 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7062 update_ple_window_actual_max();
7065 * Only enable PML when hardware supports PML feature, and both EPT
7066 * and EPT A/D bit features are enabled -- PML depends on them to work.
7068 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
7072 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
7073 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
7074 kvm_x86_ops
->flush_log_dirty
= NULL
;
7075 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
7078 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
7081 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
7082 cpu_preemption_timer_multi
=
7083 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
7085 kvm_x86_ops
->set_hv_timer
= NULL
;
7086 kvm_x86_ops
->cancel_hv_timer
= NULL
;
7089 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
7091 kvm_mce_cap_supported
|= MCG_LMCE_P
;
7093 return alloc_kvm_area();
7096 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
7097 free_page((unsigned long)vmx_bitmap
[i
]);
7102 static __exit
void hardware_unsetup(void)
7106 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
7107 free_page((unsigned long)vmx_bitmap
[i
]);
7113 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7114 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7116 static int handle_pause(struct kvm_vcpu
*vcpu
)
7119 grow_ple_window(vcpu
);
7122 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7123 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7124 * never set PAUSE_EXITING and just set PLE if supported,
7125 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7127 kvm_vcpu_on_spin(vcpu
, true);
7128 return kvm_skip_emulated_instruction(vcpu
);
7131 static int handle_nop(struct kvm_vcpu
*vcpu
)
7133 return kvm_skip_emulated_instruction(vcpu
);
7136 static int handle_mwait(struct kvm_vcpu
*vcpu
)
7138 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
7139 return handle_nop(vcpu
);
7142 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
7144 kvm_queue_exception(vcpu
, UD_VECTOR
);
7148 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
7153 static int handle_monitor(struct kvm_vcpu
*vcpu
)
7155 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
7156 return handle_nop(vcpu
);
7160 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7161 * set the success or error code of an emulated VMX instruction, as specified
7162 * by Vol 2B, VMX Instruction Reference, "Conventions".
7164 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7166 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7167 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7168 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7171 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7173 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7174 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7175 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7179 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7180 u32 vm_instruction_error
)
7182 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7184 * failValid writes the error number to the current VMCS, which
7185 * can't be done there isn't a current VMCS.
7187 nested_vmx_failInvalid(vcpu
);
7190 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7191 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7192 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7194 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7196 * We don't need to force a shadow sync because
7197 * VM_INSTRUCTION_ERROR is not shadowed
7201 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7203 /* TODO: not to reset guest simply here. */
7204 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7205 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7208 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7210 struct vcpu_vmx
*vmx
=
7211 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7213 vmx
->nested
.preemption_timer_expired
= true;
7214 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7215 kvm_vcpu_kick(&vmx
->vcpu
);
7217 return HRTIMER_NORESTART
;
7221 * Decode the memory-address operand of a vmx instruction, as recorded on an
7222 * exit caused by such an instruction (run by a guest hypervisor).
7223 * On success, returns 0. When the operand is invalid, returns 1 and throws
7226 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7227 unsigned long exit_qualification
,
7228 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7232 struct kvm_segment s
;
7235 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7236 * Execution", on an exit, vmx_instruction_info holds most of the
7237 * addressing components of the operand. Only the displacement part
7238 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7239 * For how an actual address is calculated from all these components,
7240 * refer to Vol. 1, "Operand Addressing".
7242 int scaling
= vmx_instruction_info
& 3;
7243 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7244 bool is_reg
= vmx_instruction_info
& (1u << 10);
7245 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7246 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7247 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7248 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7249 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7252 kvm_queue_exception(vcpu
, UD_VECTOR
);
7256 /* Addr = segment_base + offset */
7257 /* offset = base + [index * scale] + displacement */
7258 off
= exit_qualification
; /* holds the displacement */
7260 off
+= kvm_register_read(vcpu
, base_reg
);
7262 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7263 vmx_get_segment(vcpu
, &s
, seg_reg
);
7264 *ret
= s
.base
+ off
;
7266 if (addr_size
== 1) /* 32 bit */
7269 /* Checks for #GP/#SS exceptions. */
7271 if (is_long_mode(vcpu
)) {
7272 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7273 * non-canonical form. This is the only check on the memory
7274 * destination for long mode!
7276 exn
= is_noncanonical_address(*ret
, vcpu
);
7277 } else if (is_protmode(vcpu
)) {
7278 /* Protected mode: apply checks for segment validity in the
7280 * - segment type check (#GP(0) may be thrown)
7281 * - usability check (#GP(0)/#SS(0))
7282 * - limit check (#GP(0)/#SS(0))
7285 /* #GP(0) if the destination operand is located in a
7286 * read-only data segment or any code segment.
7288 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7290 /* #GP(0) if the source operand is located in an
7291 * execute-only code segment
7293 exn
= ((s
.type
& 0xa) == 8);
7295 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7298 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7300 exn
= (s
.unusable
!= 0);
7301 /* Protected mode: #GP(0)/#SS(0) if the memory
7302 * operand is outside the segment limit.
7304 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7307 kvm_queue_exception_e(vcpu
,
7308 seg_reg
== VCPU_SREG_SS
?
7309 SS_VECTOR
: GP_VECTOR
,
7317 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7320 struct x86_exception e
;
7322 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7323 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7326 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7327 sizeof(*vmpointer
), &e
)) {
7328 kvm_inject_page_fault(vcpu
, &e
);
7335 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7337 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7338 struct vmcs
*shadow_vmcs
;
7341 r
= alloc_loaded_vmcs(&vmx
->nested
.vmcs02
);
7345 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7346 if (!vmx
->nested
.cached_vmcs12
)
7347 goto out_cached_vmcs12
;
7349 if (enable_shadow_vmcs
) {
7350 shadow_vmcs
= alloc_vmcs();
7352 goto out_shadow_vmcs
;
7353 /* mark vmcs as shadow */
7354 shadow_vmcs
->revision_id
|= (1u << 31);
7355 /* init shadow vmcs */
7356 vmcs_clear(shadow_vmcs
);
7357 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7360 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7361 HRTIMER_MODE_REL_PINNED
);
7362 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7364 vmx
->nested
.vmxon
= true;
7368 kfree(vmx
->nested
.cached_vmcs12
);
7371 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7378 * Emulate the VMXON instruction.
7379 * Currently, we just remember that VMX is active, and do not save or even
7380 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7381 * do not currently need to store anything in that guest-allocated memory
7382 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7383 * argument is different from the VMXON pointer (which the spec says they do).
7385 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7390 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7391 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7392 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7395 * The Intel VMX Instruction Reference lists a bunch of bits that are
7396 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7397 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7398 * Otherwise, we should fail with #UD. But most faulting conditions
7399 * have already been checked by hardware, prior to the VM-exit for
7400 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7401 * that bit set to 1 in non-root mode.
7403 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7404 kvm_queue_exception(vcpu
, UD_VECTOR
);
7408 if (vmx
->nested
.vmxon
) {
7409 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7410 return kvm_skip_emulated_instruction(vcpu
);
7413 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7414 != VMXON_NEEDED_FEATURES
) {
7415 kvm_inject_gp(vcpu
, 0);
7419 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7424 * The first 4 bytes of VMXON region contain the supported
7425 * VMCS revision identifier
7427 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7428 * which replaces physical address width with 32
7430 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7431 nested_vmx_failInvalid(vcpu
);
7432 return kvm_skip_emulated_instruction(vcpu
);
7435 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7436 if (is_error_page(page
)) {
7437 nested_vmx_failInvalid(vcpu
);
7438 return kvm_skip_emulated_instruction(vcpu
);
7440 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7442 kvm_release_page_clean(page
);
7443 nested_vmx_failInvalid(vcpu
);
7444 return kvm_skip_emulated_instruction(vcpu
);
7447 kvm_release_page_clean(page
);
7449 vmx
->nested
.vmxon_ptr
= vmptr
;
7450 ret
= enter_vmx_operation(vcpu
);
7454 nested_vmx_succeed(vcpu
);
7455 return kvm_skip_emulated_instruction(vcpu
);
7459 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7460 * for running VMX instructions (except VMXON, whose prerequisites are
7461 * slightly different). It also specifies what exception to inject otherwise.
7462 * Note that many of these exceptions have priority over VM exits, so they
7463 * don't have to be checked again here.
7465 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7467 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7468 kvm_queue_exception(vcpu
, UD_VECTOR
);
7474 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7476 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7477 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7480 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7482 if (vmx
->nested
.current_vmptr
== -1ull)
7485 if (enable_shadow_vmcs
) {
7486 /* copy to memory all shadowed fields in case
7487 they were modified */
7488 copy_shadow_to_vmcs12(vmx
);
7489 vmx
->nested
.sync_shadow_vmcs
= false;
7490 vmx_disable_shadow_vmcs(vmx
);
7492 vmx
->nested
.posted_intr_nv
= -1;
7494 /* Flush VMCS12 to guest memory */
7495 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7496 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7497 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7499 vmx
->nested
.current_vmptr
= -1ull;
7503 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7504 * just stops using VMX.
7506 static void free_nested(struct vcpu_vmx
*vmx
)
7508 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
7511 vmx
->nested
.vmxon
= false;
7512 vmx
->nested
.smm
.vmxon
= false;
7513 free_vpid(vmx
->nested
.vpid02
);
7514 vmx
->nested
.posted_intr_nv
= -1;
7515 vmx
->nested
.current_vmptr
= -1ull;
7516 if (enable_shadow_vmcs
) {
7517 vmx_disable_shadow_vmcs(vmx
);
7518 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7519 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7520 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7522 kfree(vmx
->nested
.cached_vmcs12
);
7523 /* Unpin physical memory we referred to in the vmcs02 */
7524 if (vmx
->nested
.apic_access_page
) {
7525 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7526 vmx
->nested
.apic_access_page
= NULL
;
7528 if (vmx
->nested
.virtual_apic_page
) {
7529 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7530 vmx
->nested
.virtual_apic_page
= NULL
;
7532 if (vmx
->nested
.pi_desc_page
) {
7533 kunmap(vmx
->nested
.pi_desc_page
);
7534 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7535 vmx
->nested
.pi_desc_page
= NULL
;
7536 vmx
->nested
.pi_desc
= NULL
;
7539 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7542 /* Emulate the VMXOFF instruction */
7543 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7545 if (!nested_vmx_check_permission(vcpu
))
7547 free_nested(to_vmx(vcpu
));
7548 nested_vmx_succeed(vcpu
);
7549 return kvm_skip_emulated_instruction(vcpu
);
7552 /* Emulate the VMCLEAR instruction */
7553 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7555 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7559 if (!nested_vmx_check_permission(vcpu
))
7562 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7565 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7566 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7567 return kvm_skip_emulated_instruction(vcpu
);
7570 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7571 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7572 return kvm_skip_emulated_instruction(vcpu
);
7575 if (vmptr
== vmx
->nested
.current_vmptr
)
7576 nested_release_vmcs12(vmx
);
7578 kvm_vcpu_write_guest(vcpu
,
7579 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7580 &zero
, sizeof(zero
));
7582 nested_vmx_succeed(vcpu
);
7583 return kvm_skip_emulated_instruction(vcpu
);
7586 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7588 /* Emulate the VMLAUNCH instruction */
7589 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7591 return nested_vmx_run(vcpu
, true);
7594 /* Emulate the VMRESUME instruction */
7595 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7598 return nested_vmx_run(vcpu
, false);
7602 * Read a vmcs12 field. Since these can have varying lengths and we return
7603 * one type, we chose the biggest type (u64) and zero-extend the return value
7604 * to that size. Note that the caller, handle_vmread, might need to use only
7605 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7606 * 64-bit fields are to be returned).
7608 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7609 unsigned long field
, u64
*ret
)
7611 short offset
= vmcs_field_to_offset(field
);
7617 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7619 switch (vmcs_field_type(field
)) {
7620 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7621 *ret
= *((natural_width
*)p
);
7623 case VMCS_FIELD_TYPE_U16
:
7626 case VMCS_FIELD_TYPE_U32
:
7629 case VMCS_FIELD_TYPE_U64
:
7639 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7640 unsigned long field
, u64 field_value
){
7641 short offset
= vmcs_field_to_offset(field
);
7642 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7646 switch (vmcs_field_type(field
)) {
7647 case VMCS_FIELD_TYPE_U16
:
7648 *(u16
*)p
= field_value
;
7650 case VMCS_FIELD_TYPE_U32
:
7651 *(u32
*)p
= field_value
;
7653 case VMCS_FIELD_TYPE_U64
:
7654 *(u64
*)p
= field_value
;
7656 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7657 *(natural_width
*)p
= field_value
;
7666 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7669 unsigned long field
;
7671 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7672 const unsigned long *fields
= shadow_read_write_fields
;
7673 const int num_fields
= max_shadow_read_write_fields
;
7677 vmcs_load(shadow_vmcs
);
7679 for (i
= 0; i
< num_fields
; i
++) {
7681 switch (vmcs_field_type(field
)) {
7682 case VMCS_FIELD_TYPE_U16
:
7683 field_value
= vmcs_read16(field
);
7685 case VMCS_FIELD_TYPE_U32
:
7686 field_value
= vmcs_read32(field
);
7688 case VMCS_FIELD_TYPE_U64
:
7689 field_value
= vmcs_read64(field
);
7691 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7692 field_value
= vmcs_readl(field
);
7698 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7701 vmcs_clear(shadow_vmcs
);
7702 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7707 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7709 const unsigned long *fields
[] = {
7710 shadow_read_write_fields
,
7711 shadow_read_only_fields
7713 const int max_fields
[] = {
7714 max_shadow_read_write_fields
,
7715 max_shadow_read_only_fields
7718 unsigned long field
;
7719 u64 field_value
= 0;
7720 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7722 vmcs_load(shadow_vmcs
);
7724 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7725 for (i
= 0; i
< max_fields
[q
]; i
++) {
7726 field
= fields
[q
][i
];
7727 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7729 switch (vmcs_field_type(field
)) {
7730 case VMCS_FIELD_TYPE_U16
:
7731 vmcs_write16(field
, (u16
)field_value
);
7733 case VMCS_FIELD_TYPE_U32
:
7734 vmcs_write32(field
, (u32
)field_value
);
7736 case VMCS_FIELD_TYPE_U64
:
7737 vmcs_write64(field
, (u64
)field_value
);
7739 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7740 vmcs_writel(field
, (long)field_value
);
7749 vmcs_clear(shadow_vmcs
);
7750 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7754 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7755 * used before) all generate the same failure when it is missing.
7757 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7759 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7760 if (vmx
->nested
.current_vmptr
== -1ull) {
7761 nested_vmx_failInvalid(vcpu
);
7767 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7769 unsigned long field
;
7771 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7772 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7775 if (!nested_vmx_check_permission(vcpu
))
7778 if (!nested_vmx_check_vmcs12(vcpu
))
7779 return kvm_skip_emulated_instruction(vcpu
);
7781 /* Decode instruction info and find the field to read */
7782 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7783 /* Read the field, zero-extended to a u64 field_value */
7784 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7785 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7786 return kvm_skip_emulated_instruction(vcpu
);
7789 * Now copy part of this value to register or memory, as requested.
7790 * Note that the number of bits actually copied is 32 or 64 depending
7791 * on the guest's mode (32 or 64 bit), not on the given field's length.
7793 if (vmx_instruction_info
& (1u << 10)) {
7794 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7797 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7798 vmx_instruction_info
, true, &gva
))
7800 /* _system ok, as hardware has verified cpl=0 */
7801 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7802 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7805 nested_vmx_succeed(vcpu
);
7806 return kvm_skip_emulated_instruction(vcpu
);
7810 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7812 unsigned long field
;
7814 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7815 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7816 /* The value to write might be 32 or 64 bits, depending on L1's long
7817 * mode, and eventually we need to write that into a field of several
7818 * possible lengths. The code below first zero-extends the value to 64
7819 * bit (field_value), and then copies only the appropriate number of
7820 * bits into the vmcs12 field.
7822 u64 field_value
= 0;
7823 struct x86_exception e
;
7825 if (!nested_vmx_check_permission(vcpu
))
7828 if (!nested_vmx_check_vmcs12(vcpu
))
7829 return kvm_skip_emulated_instruction(vcpu
);
7831 if (vmx_instruction_info
& (1u << 10))
7832 field_value
= kvm_register_readl(vcpu
,
7833 (((vmx_instruction_info
) >> 3) & 0xf));
7835 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7836 vmx_instruction_info
, false, &gva
))
7838 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7839 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7840 kvm_inject_page_fault(vcpu
, &e
);
7846 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7847 if (vmcs_field_readonly(field
)) {
7848 nested_vmx_failValid(vcpu
,
7849 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7850 return kvm_skip_emulated_instruction(vcpu
);
7853 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7854 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7855 return kvm_skip_emulated_instruction(vcpu
);
7858 nested_vmx_succeed(vcpu
);
7859 return kvm_skip_emulated_instruction(vcpu
);
7862 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7864 vmx
->nested
.current_vmptr
= vmptr
;
7865 if (enable_shadow_vmcs
) {
7866 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7867 SECONDARY_EXEC_SHADOW_VMCS
);
7868 vmcs_write64(VMCS_LINK_POINTER
,
7869 __pa(vmx
->vmcs01
.shadow_vmcs
));
7870 vmx
->nested
.sync_shadow_vmcs
= true;
7874 /* Emulate the VMPTRLD instruction */
7875 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7877 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7880 if (!nested_vmx_check_permission(vcpu
))
7883 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7886 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7887 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7888 return kvm_skip_emulated_instruction(vcpu
);
7891 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7892 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7893 return kvm_skip_emulated_instruction(vcpu
);
7896 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7897 struct vmcs12
*new_vmcs12
;
7899 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7900 if (is_error_page(page
)) {
7901 nested_vmx_failInvalid(vcpu
);
7902 return kvm_skip_emulated_instruction(vcpu
);
7904 new_vmcs12
= kmap(page
);
7905 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7907 kvm_release_page_clean(page
);
7908 nested_vmx_failValid(vcpu
,
7909 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7910 return kvm_skip_emulated_instruction(vcpu
);
7913 nested_release_vmcs12(vmx
);
7915 * Load VMCS12 from guest memory since it is not already
7918 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7920 kvm_release_page_clean(page
);
7922 set_current_vmptr(vmx
, vmptr
);
7925 nested_vmx_succeed(vcpu
);
7926 return kvm_skip_emulated_instruction(vcpu
);
7929 /* Emulate the VMPTRST instruction */
7930 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7932 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7933 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7935 struct x86_exception e
;
7937 if (!nested_vmx_check_permission(vcpu
))
7940 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7941 vmx_instruction_info
, true, &vmcs_gva
))
7943 /* ok to use *_system, as hardware has verified cpl=0 */
7944 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7945 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7947 kvm_inject_page_fault(vcpu
, &e
);
7950 nested_vmx_succeed(vcpu
);
7951 return kvm_skip_emulated_instruction(vcpu
);
7954 /* Emulate the INVEPT instruction */
7955 static int handle_invept(struct kvm_vcpu
*vcpu
)
7957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7958 u32 vmx_instruction_info
, types
;
7961 struct x86_exception e
;
7966 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7967 SECONDARY_EXEC_ENABLE_EPT
) ||
7968 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7969 kvm_queue_exception(vcpu
, UD_VECTOR
);
7973 if (!nested_vmx_check_permission(vcpu
))
7976 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7977 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7979 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7981 if (type
>= 32 || !(types
& (1 << type
))) {
7982 nested_vmx_failValid(vcpu
,
7983 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7984 return kvm_skip_emulated_instruction(vcpu
);
7987 /* According to the Intel VMX instruction reference, the memory
7988 * operand is read even if it isn't needed (e.g., for type==global)
7990 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7991 vmx_instruction_info
, false, &gva
))
7993 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7994 sizeof(operand
), &e
)) {
7995 kvm_inject_page_fault(vcpu
, &e
);
8000 case VMX_EPT_EXTENT_GLOBAL
:
8002 * TODO: track mappings and invalidate
8003 * single context requests appropriately
8005 case VMX_EPT_EXTENT_CONTEXT
:
8006 kvm_mmu_sync_roots(vcpu
);
8007 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
8008 nested_vmx_succeed(vcpu
);
8015 return kvm_skip_emulated_instruction(vcpu
);
8018 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
8020 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8021 u32 vmx_instruction_info
;
8022 unsigned long type
, types
;
8024 struct x86_exception e
;
8030 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
8031 SECONDARY_EXEC_ENABLE_VPID
) ||
8032 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
8033 kvm_queue_exception(vcpu
, UD_VECTOR
);
8037 if (!nested_vmx_check_permission(vcpu
))
8040 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8041 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
8043 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
8044 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
8046 if (type
>= 32 || !(types
& (1 << type
))) {
8047 nested_vmx_failValid(vcpu
,
8048 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8049 return kvm_skip_emulated_instruction(vcpu
);
8052 /* according to the intel vmx instruction reference, the memory
8053 * operand is read even if it isn't needed (e.g., for type==global)
8055 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
8056 vmx_instruction_info
, false, &gva
))
8058 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
8059 sizeof(operand
), &e
)) {
8060 kvm_inject_page_fault(vcpu
, &e
);
8063 if (operand
.vpid
>> 16) {
8064 nested_vmx_failValid(vcpu
,
8065 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8066 return kvm_skip_emulated_instruction(vcpu
);
8070 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
8071 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
8072 nested_vmx_failValid(vcpu
,
8073 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8074 return kvm_skip_emulated_instruction(vcpu
);
8077 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
8078 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
8079 if (!operand
.vpid
) {
8080 nested_vmx_failValid(vcpu
,
8081 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8082 return kvm_skip_emulated_instruction(vcpu
);
8085 case VMX_VPID_EXTENT_ALL_CONTEXT
:
8089 return kvm_skip_emulated_instruction(vcpu
);
8092 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
8093 nested_vmx_succeed(vcpu
);
8095 return kvm_skip_emulated_instruction(vcpu
);
8098 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
8100 unsigned long exit_qualification
;
8102 trace_kvm_pml_full(vcpu
->vcpu_id
);
8104 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8107 * PML buffer FULL happened while executing iret from NMI,
8108 * "blocked by NMI" bit has to be set before next VM entry.
8110 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8112 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
8113 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8114 GUEST_INTR_STATE_NMI
);
8117 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8118 * here.., and there's no userspace involvement needed for PML.
8123 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
8125 kvm_lapic_expired_hv_timer(vcpu
);
8129 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8131 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8132 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8134 /* Check for memory type validity */
8135 switch (address
& VMX_EPTP_MT_MASK
) {
8136 case VMX_EPTP_MT_UC
:
8137 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8140 case VMX_EPTP_MT_WB
:
8141 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8148 /* only 4 levels page-walk length are valid */
8149 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8152 /* Reserved bits should not be set */
8153 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8156 /* AD, if set, should be supported */
8157 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8158 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8165 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8166 struct vmcs12
*vmcs12
)
8168 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8170 bool accessed_dirty
;
8171 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8173 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8174 !nested_cpu_has_ept(vmcs12
))
8177 if (index
>= VMFUNC_EPTP_ENTRIES
)
8181 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8182 &address
, index
* 8, 8))
8185 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8188 * If the (L2) guest does a vmfunc to the currently
8189 * active ept pointer, we don't have to do anything else
8191 if (vmcs12
->ept_pointer
!= address
) {
8192 if (!valid_ept_address(vcpu
, address
))
8195 kvm_mmu_unload(vcpu
);
8196 mmu
->ept_ad
= accessed_dirty
;
8197 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8198 vmcs12
->ept_pointer
= address
;
8200 * TODO: Check what's the correct approach in case
8201 * mmu reload fails. Currently, we just let the next
8202 * reload potentially fail
8204 kvm_mmu_reload(vcpu
);
8210 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8212 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8213 struct vmcs12
*vmcs12
;
8214 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8217 * VMFUNC is only supported for nested guests, but we always enable the
8218 * secondary control for simplicity; for non-nested mode, fake that we
8219 * didn't by injecting #UD.
8221 if (!is_guest_mode(vcpu
)) {
8222 kvm_queue_exception(vcpu
, UD_VECTOR
);
8226 vmcs12
= get_vmcs12(vcpu
);
8227 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8232 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8238 return kvm_skip_emulated_instruction(vcpu
);
8241 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8242 vmcs_read32(VM_EXIT_INTR_INFO
),
8243 vmcs_readl(EXIT_QUALIFICATION
));
8248 * The exit handlers return 1 if the exit was handled fully and guest execution
8249 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8250 * to be done to userspace and return 0.
8252 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8253 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8254 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8255 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8256 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8257 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8258 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8259 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8260 [EXIT_REASON_CPUID
] = handle_cpuid
,
8261 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8262 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8263 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8264 [EXIT_REASON_HLT
] = handle_halt
,
8265 [EXIT_REASON_INVD
] = handle_invd
,
8266 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8267 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8268 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8269 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8270 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8271 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8272 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8273 [EXIT_REASON_VMREAD
] = handle_vmread
,
8274 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8275 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8276 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8277 [EXIT_REASON_VMON
] = handle_vmon
,
8278 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8279 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8280 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8281 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8282 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8283 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8284 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8285 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8286 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8287 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8288 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8289 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8290 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8291 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8292 [EXIT_REASON_INVEPT
] = handle_invept
,
8293 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8294 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8295 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8296 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8297 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8298 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8299 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8300 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8303 static const int kvm_vmx_max_exit_handlers
=
8304 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8306 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8307 struct vmcs12
*vmcs12
)
8309 unsigned long exit_qualification
;
8310 gpa_t bitmap
, last_bitmap
;
8315 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8316 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8318 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8320 port
= exit_qualification
>> 16;
8321 size
= (exit_qualification
& 7) + 1;
8323 last_bitmap
= (gpa_t
)-1;
8328 bitmap
= vmcs12
->io_bitmap_a
;
8329 else if (port
< 0x10000)
8330 bitmap
= vmcs12
->io_bitmap_b
;
8333 bitmap
+= (port
& 0x7fff) / 8;
8335 if (last_bitmap
!= bitmap
)
8336 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8338 if (b
& (1 << (port
& 7)))
8343 last_bitmap
= bitmap
;
8350 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8351 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8352 * disinterest in the current event (read or write a specific MSR) by using an
8353 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8355 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8356 struct vmcs12
*vmcs12
, u32 exit_reason
)
8358 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8361 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8365 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8366 * for the four combinations of read/write and low/high MSR numbers.
8367 * First we need to figure out which of the four to use:
8369 bitmap
= vmcs12
->msr_bitmap
;
8370 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8372 if (msr_index
>= 0xc0000000) {
8373 msr_index
-= 0xc0000000;
8377 /* Then read the msr_index'th bit from this bitmap: */
8378 if (msr_index
< 1024*8) {
8380 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8382 return 1 & (b
>> (msr_index
& 7));
8384 return true; /* let L1 handle the wrong parameter */
8388 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8389 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8390 * intercept (via guest_host_mask etc.) the current event.
8392 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8393 struct vmcs12
*vmcs12
)
8395 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8396 int cr
= exit_qualification
& 15;
8400 switch ((exit_qualification
>> 4) & 3) {
8401 case 0: /* mov to cr */
8402 reg
= (exit_qualification
>> 8) & 15;
8403 val
= kvm_register_readl(vcpu
, reg
);
8406 if (vmcs12
->cr0_guest_host_mask
&
8407 (val
^ vmcs12
->cr0_read_shadow
))
8411 if ((vmcs12
->cr3_target_count
>= 1 &&
8412 vmcs12
->cr3_target_value0
== val
) ||
8413 (vmcs12
->cr3_target_count
>= 2 &&
8414 vmcs12
->cr3_target_value1
== val
) ||
8415 (vmcs12
->cr3_target_count
>= 3 &&
8416 vmcs12
->cr3_target_value2
== val
) ||
8417 (vmcs12
->cr3_target_count
>= 4 &&
8418 vmcs12
->cr3_target_value3
== val
))
8420 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8424 if (vmcs12
->cr4_guest_host_mask
&
8425 (vmcs12
->cr4_read_shadow
^ val
))
8429 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8435 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8436 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8439 case 1: /* mov from cr */
8442 if (vmcs12
->cpu_based_vm_exec_control
&
8443 CPU_BASED_CR3_STORE_EXITING
)
8447 if (vmcs12
->cpu_based_vm_exec_control
&
8448 CPU_BASED_CR8_STORE_EXITING
)
8455 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8456 * cr0. Other attempted changes are ignored, with no exit.
8458 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8459 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8460 (val
^ vmcs12
->cr0_read_shadow
))
8462 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8463 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8472 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8473 * should handle it ourselves in L0 (and then continue L2). Only call this
8474 * when in is_guest_mode (L2).
8476 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8478 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8479 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8480 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8482 if (vmx
->nested
.nested_run_pending
)
8485 if (unlikely(vmx
->fail
)) {
8486 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8487 vmcs_read32(VM_INSTRUCTION_ERROR
));
8492 * The host physical addresses of some pages of guest memory
8493 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8494 * Page). The CPU may write to these pages via their host
8495 * physical address while L2 is running, bypassing any
8496 * address-translation-based dirty tracking (e.g. EPT write
8499 * Mark them dirty on every exit from L2 to prevent them from
8500 * getting out of sync with dirty tracking.
8502 nested_mark_vmcs12_pages_dirty(vcpu
);
8504 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8505 vmcs_readl(EXIT_QUALIFICATION
),
8506 vmx
->idt_vectoring_info
,
8508 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8511 switch (exit_reason
) {
8512 case EXIT_REASON_EXCEPTION_NMI
:
8513 if (is_nmi(intr_info
))
8515 else if (is_page_fault(intr_info
))
8516 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8517 else if (is_no_device(intr_info
) &&
8518 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8520 else if (is_debug(intr_info
) &&
8522 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8524 else if (is_breakpoint(intr_info
) &&
8525 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8527 return vmcs12
->exception_bitmap
&
8528 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8529 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8531 case EXIT_REASON_TRIPLE_FAULT
:
8533 case EXIT_REASON_PENDING_INTERRUPT
:
8534 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8535 case EXIT_REASON_NMI_WINDOW
:
8536 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8537 case EXIT_REASON_TASK_SWITCH
:
8539 case EXIT_REASON_CPUID
:
8541 case EXIT_REASON_HLT
:
8542 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8543 case EXIT_REASON_INVD
:
8545 case EXIT_REASON_INVLPG
:
8546 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8547 case EXIT_REASON_RDPMC
:
8548 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8549 case EXIT_REASON_RDRAND
:
8550 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8551 case EXIT_REASON_RDSEED
:
8552 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8553 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8554 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8555 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8556 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8557 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8558 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8559 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8560 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8562 * VMX instructions trap unconditionally. This allows L1 to
8563 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8566 case EXIT_REASON_CR_ACCESS
:
8567 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8568 case EXIT_REASON_DR_ACCESS
:
8569 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8570 case EXIT_REASON_IO_INSTRUCTION
:
8571 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8572 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8573 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8574 case EXIT_REASON_MSR_READ
:
8575 case EXIT_REASON_MSR_WRITE
:
8576 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8577 case EXIT_REASON_INVALID_STATE
:
8579 case EXIT_REASON_MWAIT_INSTRUCTION
:
8580 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8581 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8582 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8583 case EXIT_REASON_MONITOR_INSTRUCTION
:
8584 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8585 case EXIT_REASON_PAUSE_INSTRUCTION
:
8586 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8587 nested_cpu_has2(vmcs12
,
8588 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8589 case EXIT_REASON_MCE_DURING_VMENTRY
:
8591 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8592 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8593 case EXIT_REASON_APIC_ACCESS
:
8594 return nested_cpu_has2(vmcs12
,
8595 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8596 case EXIT_REASON_APIC_WRITE
:
8597 case EXIT_REASON_EOI_INDUCED
:
8598 /* apic_write and eoi_induced should exit unconditionally. */
8600 case EXIT_REASON_EPT_VIOLATION
:
8602 * L0 always deals with the EPT violation. If nested EPT is
8603 * used, and the nested mmu code discovers that the address is
8604 * missing in the guest EPT table (EPT12), the EPT violation
8605 * will be injected with nested_ept_inject_page_fault()
8608 case EXIT_REASON_EPT_MISCONFIG
:
8610 * L2 never uses directly L1's EPT, but rather L0's own EPT
8611 * table (shadow on EPT) or a merged EPT table that L0 built
8612 * (EPT on EPT). So any problems with the structure of the
8613 * table is L0's fault.
8616 case EXIT_REASON_INVPCID
:
8618 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8619 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8620 case EXIT_REASON_WBINVD
:
8621 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8622 case EXIT_REASON_XSETBV
:
8624 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8626 * This should never happen, since it is not possible to
8627 * set XSS to a non-zero value---neither in L1 nor in L2.
8628 * If if it were, XSS would have to be checked against
8629 * the XSS exit bitmap in vmcs12.
8631 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8632 case EXIT_REASON_PREEMPTION_TIMER
:
8634 case EXIT_REASON_PML_FULL
:
8635 /* We emulate PML support to L1. */
8637 case EXIT_REASON_VMFUNC
:
8638 /* VM functions are emulated through L2->L0 vmexits. */
8645 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8647 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8650 * At this point, the exit interruption info in exit_intr_info
8651 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8652 * we need to query the in-kernel LAPIC.
8654 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8655 if ((exit_intr_info
&
8656 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8657 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8658 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8659 vmcs12
->vm_exit_intr_error_code
=
8660 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8663 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8664 vmcs_readl(EXIT_QUALIFICATION
));
8668 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8670 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8671 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8674 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8677 __free_page(vmx
->pml_pg
);
8682 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8684 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8688 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8690 /* Do nothing if PML buffer is empty */
8691 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8694 /* PML index always points to next available PML buffer entity */
8695 if (pml_idx
>= PML_ENTITY_NUM
)
8700 pml_buf
= page_address(vmx
->pml_pg
);
8701 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8704 gpa
= pml_buf
[pml_idx
];
8705 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8706 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8709 /* reset PML index */
8710 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8714 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8715 * Called before reporting dirty_bitmap to userspace.
8717 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8720 struct kvm_vcpu
*vcpu
;
8722 * We only need to kick vcpu out of guest mode here, as PML buffer
8723 * is flushed at beginning of all VMEXITs, and it's obvious that only
8724 * vcpus running in guest are possible to have unflushed GPAs in PML
8727 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8728 kvm_vcpu_kick(vcpu
);
8731 static void vmx_dump_sel(char *name
, uint32_t sel
)
8733 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8734 name
, vmcs_read16(sel
),
8735 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8736 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8737 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8740 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8742 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8743 name
, vmcs_read32(limit
),
8744 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8747 static void dump_vmcs(void)
8749 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8750 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8751 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8752 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8753 u32 secondary_exec_control
= 0;
8754 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8755 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8758 if (cpu_has_secondary_exec_ctrls())
8759 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8761 pr_err("*** Guest State ***\n");
8762 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8763 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8764 vmcs_readl(CR0_GUEST_HOST_MASK
));
8765 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8766 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8767 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8768 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8769 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8771 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8772 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8773 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8774 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8776 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8777 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8778 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8779 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8780 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8781 vmcs_readl(GUEST_SYSENTER_ESP
),
8782 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8783 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8784 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8785 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8786 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8787 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8788 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8789 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8790 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8791 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8792 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8793 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8794 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8795 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8796 efer
, vmcs_read64(GUEST_IA32_PAT
));
8797 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8798 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8799 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8800 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8801 pr_err("PerfGlobCtl = 0x%016llx\n",
8802 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8803 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8804 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8805 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8806 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8807 vmcs_read32(GUEST_ACTIVITY_STATE
));
8808 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8809 pr_err("InterruptStatus = %04x\n",
8810 vmcs_read16(GUEST_INTR_STATUS
));
8812 pr_err("*** Host State ***\n");
8813 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8814 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8815 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8816 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8817 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8818 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8819 vmcs_read16(HOST_TR_SELECTOR
));
8820 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8821 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8822 vmcs_readl(HOST_TR_BASE
));
8823 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8824 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8825 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8826 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8827 vmcs_readl(HOST_CR4
));
8828 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8829 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8830 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8831 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8832 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8833 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8834 vmcs_read64(HOST_IA32_EFER
),
8835 vmcs_read64(HOST_IA32_PAT
));
8836 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8837 pr_err("PerfGlobCtl = 0x%016llx\n",
8838 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8840 pr_err("*** Control State ***\n");
8841 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8842 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8843 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8844 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8845 vmcs_read32(EXCEPTION_BITMAP
),
8846 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8847 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8848 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8849 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8850 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8851 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8852 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8853 vmcs_read32(VM_EXIT_INTR_INFO
),
8854 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8855 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8856 pr_err(" reason=%08x qualification=%016lx\n",
8857 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8858 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8859 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8860 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8861 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8862 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8863 pr_err("TSC Multiplier = 0x%016llx\n",
8864 vmcs_read64(TSC_MULTIPLIER
));
8865 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8866 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8867 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8868 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8869 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8870 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8871 n
= vmcs_read32(CR3_TARGET_COUNT
);
8872 for (i
= 0; i
+ 1 < n
; i
+= 4)
8873 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8874 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8875 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8877 pr_err("CR3 target%u=%016lx\n",
8878 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8879 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8880 pr_err("PLE Gap=%08x Window=%08x\n",
8881 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8882 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8883 pr_err("Virtual processor ID = 0x%04x\n",
8884 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8888 * The guest has exited. See if we can fix it or if we need userspace
8891 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8894 u32 exit_reason
= vmx
->exit_reason
;
8895 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8897 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8900 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8901 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8902 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8903 * mode as if vcpus is in root mode, the PML buffer must has been
8907 vmx_flush_pml_buffer(vcpu
);
8909 /* If guest state is invalid, start emulating */
8910 if (vmx
->emulation_required
)
8911 return handle_invalid_guest_state(vcpu
);
8913 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8914 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8916 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8918 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8919 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8924 if (unlikely(vmx
->fail
)) {
8925 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8926 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8927 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8933 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8934 * delivery event since it indicates guest is accessing MMIO.
8935 * The vm-exit can be triggered again after return to guest that
8936 * will cause infinite loop.
8938 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8939 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8940 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8941 exit_reason
!= EXIT_REASON_PML_FULL
&&
8942 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8943 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8944 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8945 vcpu
->run
->internal
.ndata
= 3;
8946 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8947 vcpu
->run
->internal
.data
[1] = exit_reason
;
8948 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8949 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8950 vcpu
->run
->internal
.ndata
++;
8951 vcpu
->run
->internal
.data
[3] =
8952 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8957 if (unlikely(!enable_vnmi
&&
8958 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8959 if (vmx_interrupt_allowed(vcpu
)) {
8960 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8961 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8962 vcpu
->arch
.nmi_pending
) {
8964 * This CPU don't support us in finding the end of an
8965 * NMI-blocked window if the guest runs with IRQs
8966 * disabled. So we pull the trigger after 1 s of
8967 * futile waiting, but inform the user about this.
8969 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8970 "state on VCPU %d after 1 s timeout\n",
8971 __func__
, vcpu
->vcpu_id
);
8972 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8976 if (exit_reason
< kvm_vmx_max_exit_handlers
8977 && kvm_vmx_exit_handlers
[exit_reason
])
8978 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8980 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8982 kvm_queue_exception(vcpu
, UD_VECTOR
);
8987 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8989 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8991 if (is_guest_mode(vcpu
) &&
8992 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8995 if (irr
== -1 || tpr
< irr
) {
8996 vmcs_write32(TPR_THRESHOLD
, 0);
9000 vmcs_write32(TPR_THRESHOLD
, irr
);
9003 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
9005 u32 sec_exec_control
;
9007 /* Postpone execution until vmcs01 is the current VMCS. */
9008 if (is_guest_mode(vcpu
)) {
9009 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
9013 if (!cpu_has_vmx_virtualize_x2apic_mode())
9016 if (!cpu_need_tpr_shadow(vcpu
))
9019 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9022 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9023 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
9025 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
9026 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9027 vmx_flush_tlb_ept_only(vcpu
);
9029 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
9031 vmx_update_msr_bitmap(vcpu
);
9034 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
9036 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9039 * Currently we do not handle the nested case where L2 has an
9040 * APIC access page of its own; that page is still pinned.
9041 * Hence, we skip the case where the VCPU is in guest mode _and_
9042 * L1 prepared an APIC access page for L2.
9044 * For the case where L1 and L2 share the same APIC access page
9045 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9046 * in the vmcs12), this function will only update either the vmcs01
9047 * or the vmcs02. If the former, the vmcs02 will be updated by
9048 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
9049 * the next L2->L1 exit.
9051 if (!is_guest_mode(vcpu
) ||
9052 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
9053 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9054 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9055 vmx_flush_tlb_ept_only(vcpu
);
9059 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
9067 status
= vmcs_read16(GUEST_INTR_STATUS
);
9069 if (max_isr
!= old
) {
9071 status
|= max_isr
<< 8;
9072 vmcs_write16(GUEST_INTR_STATUS
, status
);
9076 static void vmx_set_rvi(int vector
)
9084 status
= vmcs_read16(GUEST_INTR_STATUS
);
9085 old
= (u8
)status
& 0xff;
9086 if ((u8
)vector
!= old
) {
9088 status
|= (u8
)vector
;
9089 vmcs_write16(GUEST_INTR_STATUS
, status
);
9093 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
9095 if (!is_guest_mode(vcpu
)) {
9096 vmx_set_rvi(max_irr
);
9104 * In guest mode. If a vmexit is needed, vmx_check_nested_events
9107 if (nested_exit_on_intr(vcpu
))
9111 * Else, fall back to pre-APICv interrupt injection since L2
9112 * is run without virtual interrupt delivery.
9114 if (!kvm_event_needs_reinjection(vcpu
) &&
9115 vmx_interrupt_allowed(vcpu
)) {
9116 kvm_queue_interrupt(vcpu
, max_irr
, false);
9117 vmx_inject_irq(vcpu
);
9121 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
9123 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9126 WARN_ON(!vcpu
->arch
.apicv_active
);
9127 if (pi_test_on(&vmx
->pi_desc
)) {
9128 pi_clear_on(&vmx
->pi_desc
);
9130 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9131 * But on x86 this is just a compiler barrier anyway.
9133 smp_mb__after_atomic();
9134 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
9136 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
9138 vmx_hwapic_irr_update(vcpu
, max_irr
);
9142 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
9144 if (!kvm_vcpu_apicv_active(vcpu
))
9147 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
9148 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
9149 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9150 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9153 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9157 pi_clear_on(&vmx
->pi_desc
);
9158 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9161 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9163 u32 exit_intr_info
= 0;
9164 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9166 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9167 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9170 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9171 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9172 vmx
->exit_intr_info
= exit_intr_info
;
9174 /* if exit due to PF check for async PF */
9175 if (is_page_fault(exit_intr_info
))
9176 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9178 /* Handle machine checks before interrupts are enabled */
9179 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9180 is_machine_check(exit_intr_info
))
9181 kvm_machine_check();
9183 /* We need to handle NMIs before interrupts are enabled */
9184 if (is_nmi(exit_intr_info
)) {
9185 kvm_before_handle_nmi(&vmx
->vcpu
);
9187 kvm_after_handle_nmi(&vmx
->vcpu
);
9191 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9193 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9195 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9196 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9197 unsigned int vector
;
9198 unsigned long entry
;
9200 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9201 #ifdef CONFIG_X86_64
9205 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9206 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9207 entry
= gate_offset(desc
);
9209 #ifdef CONFIG_X86_64
9210 "mov %%" _ASM_SP
", %[sp]\n\t"
9211 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9216 __ASM_SIZE(push
) " $%c[cs]\n\t"
9219 #ifdef CONFIG_X86_64
9224 THUNK_TARGET(entry
),
9225 [ss
]"i"(__KERNEL_DS
),
9226 [cs
]"i"(__KERNEL_CS
)
9230 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9232 static bool vmx_has_emulated_msr(int index
)
9235 case MSR_IA32_SMBASE
:
9237 * We cannot do SMM unless we can run the guest in big
9240 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9241 case MSR_AMD64_VIRT_SPEC_CTRL
:
9242 /* This is AMD only. */
9249 static bool vmx_mpx_supported(void)
9251 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9252 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9255 static bool vmx_xsaves_supported(void)
9257 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9258 SECONDARY_EXEC_XSAVES
;
9261 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9266 bool idtv_info_valid
;
9268 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9271 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9274 * Can't use vmx->exit_intr_info since we're not sure what
9275 * the exit reason is.
9277 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9278 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9279 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9281 * SDM 3: 27.7.1.2 (September 2008)
9282 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9283 * a guest IRET fault.
9284 * SDM 3: 23.2.2 (September 2008)
9285 * Bit 12 is undefined in any of the following cases:
9286 * If the VM exit sets the valid bit in the IDT-vectoring
9287 * information field.
9288 * If the VM exit is due to a double fault.
9290 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9291 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9292 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9293 GUEST_INTR_STATE_NMI
);
9295 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9296 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9297 & GUEST_INTR_STATE_NMI
);
9298 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9299 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
9300 ktime_to_ns(ktime_sub(ktime_get(),
9301 vmx
->loaded_vmcs
->entry_time
));
9304 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9305 u32 idt_vectoring_info
,
9306 int instr_len_field
,
9307 int error_code_field
)
9311 bool idtv_info_valid
;
9313 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9315 vcpu
->arch
.nmi_injected
= false;
9316 kvm_clear_exception_queue(vcpu
);
9317 kvm_clear_interrupt_queue(vcpu
);
9319 if (!idtv_info_valid
)
9322 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9324 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9325 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9328 case INTR_TYPE_NMI_INTR
:
9329 vcpu
->arch
.nmi_injected
= true;
9331 * SDM 3: 27.7.1.2 (September 2008)
9332 * Clear bit "block by NMI" before VM entry if a NMI
9335 vmx_set_nmi_mask(vcpu
, false);
9337 case INTR_TYPE_SOFT_EXCEPTION
:
9338 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9340 case INTR_TYPE_HARD_EXCEPTION
:
9341 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9342 u32 err
= vmcs_read32(error_code_field
);
9343 kvm_requeue_exception_e(vcpu
, vector
, err
);
9345 kvm_requeue_exception(vcpu
, vector
);
9347 case INTR_TYPE_SOFT_INTR
:
9348 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9350 case INTR_TYPE_EXT_INTR
:
9351 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9358 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9360 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9361 VM_EXIT_INSTRUCTION_LEN
,
9362 IDT_VECTORING_ERROR_CODE
);
9365 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9367 __vmx_complete_interrupts(vcpu
,
9368 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9369 VM_ENTRY_INSTRUCTION_LEN
,
9370 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9372 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9375 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9378 struct perf_guest_switch_msr
*msrs
;
9380 msrs
= perf_guest_get_msrs(&nr_msrs
);
9385 for (i
= 0; i
< nr_msrs
; i
++)
9386 if (msrs
[i
].host
== msrs
[i
].guest
)
9387 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9389 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9393 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9395 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9399 if (vmx
->hv_deadline_tsc
== -1)
9403 if (vmx
->hv_deadline_tsc
> tscl
)
9404 /* sure to be 32 bit only because checked on set_hv_timer */
9405 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9406 cpu_preemption_timer_multi
);
9410 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9413 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9415 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9416 unsigned long debugctlmsr
, cr3
, cr4
;
9418 /* Record the guest's net vcpu time for enforced NMI injections. */
9419 if (unlikely(!enable_vnmi
&&
9420 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9421 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9423 /* Don't enter VMX if guest state is invalid, let the exit handler
9424 start emulation until we arrive back to a valid state */
9425 if (vmx
->emulation_required
)
9428 if (vmx
->ple_window_dirty
) {
9429 vmx
->ple_window_dirty
= false;
9430 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9433 if (vmx
->nested
.sync_shadow_vmcs
) {
9434 copy_vmcs12_to_shadow(vmx
);
9435 vmx
->nested
.sync_shadow_vmcs
= false;
9438 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9439 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9440 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9441 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9443 cr3
= __get_current_cr3_fast();
9444 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9445 vmcs_writel(HOST_CR3
, cr3
);
9446 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9449 cr4
= cr4_read_shadow();
9450 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9451 vmcs_writel(HOST_CR4
, cr4
);
9452 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9455 /* When single-stepping over STI and MOV SS, we must clear the
9456 * corresponding interruptibility bits in the guest state. Otherwise
9457 * vmentry fails as it then expects bit 14 (BS) in pending debug
9458 * exceptions being set, but that's not correct for the guest debugging
9460 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9461 vmx_set_interrupt_shadow(vcpu
, 0);
9463 if (static_cpu_has(X86_FEATURE_PKU
) &&
9464 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9465 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9466 __write_pkru(vcpu
->arch
.pkru
);
9468 atomic_switch_perf_msrs(vmx
);
9469 debugctlmsr
= get_debugctlmsr();
9471 vmx_arm_hv_timer(vcpu
);
9474 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9475 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9476 * is no need to worry about the conditional branch over the wrmsr
9477 * being speculatively taken.
9479 x86_spec_ctrl_set_guest(vmx
->spec_ctrl
, 0);
9481 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9483 /* Store host registers */
9484 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9485 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9486 "push %%" _ASM_CX
" \n\t"
9487 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9489 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9490 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9492 /* Reload cr2 if changed */
9493 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9494 "mov %%cr2, %%" _ASM_DX
" \n\t"
9495 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9497 "mov %%" _ASM_AX
", %%cr2 \n\t"
9499 /* Check if vmlaunch of vmresume is needed */
9500 "cmpl $0, %c[launched](%0) \n\t"
9501 /* Load guest registers. Don't clobber flags. */
9502 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9503 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9504 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9505 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9506 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9507 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9508 #ifdef CONFIG_X86_64
9509 "mov %c[r8](%0), %%r8 \n\t"
9510 "mov %c[r9](%0), %%r9 \n\t"
9511 "mov %c[r10](%0), %%r10 \n\t"
9512 "mov %c[r11](%0), %%r11 \n\t"
9513 "mov %c[r12](%0), %%r12 \n\t"
9514 "mov %c[r13](%0), %%r13 \n\t"
9515 "mov %c[r14](%0), %%r14 \n\t"
9516 "mov %c[r15](%0), %%r15 \n\t"
9518 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9520 /* Enter guest mode */
9522 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9524 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9526 /* Save guest registers, load host registers, keep flags */
9527 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9529 "setbe %c[fail](%0)\n\t"
9530 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9531 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9532 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9533 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9534 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9535 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9536 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9537 #ifdef CONFIG_X86_64
9538 "mov %%r8, %c[r8](%0) \n\t"
9539 "mov %%r9, %c[r9](%0) \n\t"
9540 "mov %%r10, %c[r10](%0) \n\t"
9541 "mov %%r11, %c[r11](%0) \n\t"
9542 "mov %%r12, %c[r12](%0) \n\t"
9543 "mov %%r13, %c[r13](%0) \n\t"
9544 "mov %%r14, %c[r14](%0) \n\t"
9545 "mov %%r15, %c[r15](%0) \n\t"
9546 "xor %%r8d, %%r8d \n\t"
9547 "xor %%r9d, %%r9d \n\t"
9548 "xor %%r10d, %%r10d \n\t"
9549 "xor %%r11d, %%r11d \n\t"
9550 "xor %%r12d, %%r12d \n\t"
9551 "xor %%r13d, %%r13d \n\t"
9552 "xor %%r14d, %%r14d \n\t"
9553 "xor %%r15d, %%r15d \n\t"
9555 "mov %%cr2, %%" _ASM_AX
" \n\t"
9556 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9558 "xor %%eax, %%eax \n\t"
9559 "xor %%ebx, %%ebx \n\t"
9560 "xor %%esi, %%esi \n\t"
9561 "xor %%edi, %%edi \n\t"
9562 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9563 ".pushsection .rodata \n\t"
9564 ".global vmx_return \n\t"
9565 "vmx_return: " _ASM_PTR
" 2b \n\t"
9567 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9568 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9569 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9570 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9571 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9572 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9573 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9574 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9575 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9576 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9577 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9578 #ifdef CONFIG_X86_64
9579 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9580 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9581 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9582 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9583 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9584 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9585 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9586 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9588 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9589 [wordsize
]"i"(sizeof(ulong
))
9591 #ifdef CONFIG_X86_64
9592 , "rax", "rbx", "rdi", "rsi"
9593 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9595 , "eax", "ebx", "edi", "esi"
9600 * We do not use IBRS in the kernel. If this vCPU has used the
9601 * SPEC_CTRL MSR it may have left it on; save the value and
9602 * turn it off. This is much more efficient than blindly adding
9603 * it to the atomic save/restore list. Especially as the former
9604 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9606 * For non-nested case:
9607 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9611 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9614 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
9615 vmx
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
9617 x86_spec_ctrl_restore_host(vmx
->spec_ctrl
, 0);
9619 /* Eliminate branch target predictions from guest mode */
9622 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9624 update_debugctlmsr(debugctlmsr
);
9626 #ifndef CONFIG_X86_64
9628 * The sysexit path does not restore ds/es, so we must set them to
9629 * a reasonable value ourselves.
9631 * We can't defer this to vmx_load_host_state() since that function
9632 * may be executed in interrupt context, which saves and restore segments
9633 * around it, nullifying its effect.
9635 loadsegment(ds
, __USER_DS
);
9636 loadsegment(es
, __USER_DS
);
9639 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9640 | (1 << VCPU_EXREG_RFLAGS
)
9641 | (1 << VCPU_EXREG_PDPTR
)
9642 | (1 << VCPU_EXREG_SEGMENTS
)
9643 | (1 << VCPU_EXREG_CR3
));
9644 vcpu
->arch
.regs_dirty
= 0;
9647 * eager fpu is enabled if PKEY is supported and CR4 is switched
9648 * back on host, so it is safe to read guest PKRU from current
9651 if (static_cpu_has(X86_FEATURE_PKU
) &&
9652 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9653 vcpu
->arch
.pkru
= __read_pkru();
9654 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9655 __write_pkru(vmx
->host_pkru
);
9659 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9660 * we did not inject a still-pending event to L1 now because of
9661 * nested_run_pending, we need to re-enable this bit.
9663 if (vmx
->nested
.nested_run_pending
)
9664 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9666 vmx
->nested
.nested_run_pending
= 0;
9667 vmx
->idt_vectoring_info
= 0;
9669 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9670 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9673 vmx
->loaded_vmcs
->launched
= 1;
9674 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9676 vmx_complete_atomic_exit(vmx
);
9677 vmx_recover_nmi_blocking(vmx
);
9678 vmx_complete_interrupts(vmx
);
9680 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9682 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9684 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9687 if (vmx
->loaded_vmcs
== vmcs
)
9691 vmx
->loaded_vmcs
= vmcs
;
9693 vmx_vcpu_load(vcpu
, cpu
);
9698 * Ensure that the current vmcs of the logical processor is the
9699 * vmcs01 of the vcpu before calling free_nested().
9701 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9703 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9706 r
= vcpu_load(vcpu
);
9708 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9713 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9715 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9718 vmx_destroy_pml_buffer(vmx
);
9719 free_vpid(vmx
->vpid
);
9720 leave_guest_mode(vcpu
);
9721 vmx_free_vcpu_nested(vcpu
);
9722 free_loaded_vmcs(vmx
->loaded_vmcs
);
9723 kfree(vmx
->guest_msrs
);
9724 kvm_vcpu_uninit(vcpu
);
9725 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9728 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9731 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9732 unsigned long *msr_bitmap
;
9736 return ERR_PTR(-ENOMEM
);
9738 vmx
->vpid
= allocate_vpid();
9740 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9747 * If PML is turned on, failure on enabling PML just results in failure
9748 * of creating the vcpu, therefore we can simplify PML logic (by
9749 * avoiding dealing with cases, such as enabling PML partially on vcpus
9750 * for the guest, etc.
9753 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9758 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9759 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9762 if (!vmx
->guest_msrs
)
9765 err
= alloc_loaded_vmcs(&vmx
->vmcs01
);
9769 msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
9770 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_FS_BASE
, MSR_TYPE_RW
);
9771 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_GS_BASE
, MSR_TYPE_RW
);
9772 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
);
9773 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_CS
, MSR_TYPE_RW
);
9774 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_ESP
, MSR_TYPE_RW
);
9775 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_EIP
, MSR_TYPE_RW
);
9776 vmx
->msr_bitmap_mode
= 0;
9778 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9780 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9781 vmx
->vcpu
.cpu
= cpu
;
9782 vmx_vcpu_setup(vmx
);
9783 vmx_vcpu_put(&vmx
->vcpu
);
9785 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9786 err
= alloc_apic_access_page(kvm
);
9792 err
= init_rmode_identity_map(kvm
);
9798 nested_vmx_setup_ctls_msrs(vmx
);
9799 vmx
->nested
.vpid02
= allocate_vpid();
9802 vmx
->nested
.posted_intr_nv
= -1;
9803 vmx
->nested
.current_vmptr
= -1ull;
9805 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9808 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9809 * or POSTED_INTR_WAKEUP_VECTOR.
9811 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9812 vmx
->pi_desc
.sn
= 1;
9817 free_vpid(vmx
->nested
.vpid02
);
9818 free_loaded_vmcs(vmx
->loaded_vmcs
);
9820 kfree(vmx
->guest_msrs
);
9822 vmx_destroy_pml_buffer(vmx
);
9824 kvm_vcpu_uninit(&vmx
->vcpu
);
9826 free_vpid(vmx
->vpid
);
9827 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9828 return ERR_PTR(err
);
9831 #define L1TF_MSG "SMT enabled with L1TF CPU bug present. Refer to CVE-2018-3620 for details.\n"
9833 static int vmx_vm_init(struct kvm
*kvm
)
9835 if (boot_cpu_has(X86_BUG_L1TF
) && cpu_smt_control
== CPU_SMT_ENABLED
) {
9845 static void __init
vmx_check_processor_compat(void *rtn
)
9847 struct vmcs_config vmcs_conf
;
9850 if (setup_vmcs_config(&vmcs_conf
) < 0)
9852 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9853 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9854 smp_processor_id());
9859 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9864 /* For VT-d and EPT combination
9865 * 1. MMIO: always map as UC
9867 * a. VT-d without snooping control feature: can't guarantee the
9868 * result, try to trust guest.
9869 * b. VT-d with snooping control feature: snooping control feature of
9870 * VT-d engine can guarantee the cache correctness. Just set it
9871 * to WB to keep consistent with host. So the same as item 3.
9872 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9873 * consistent with host MTRR
9876 cache
= MTRR_TYPE_UNCACHABLE
;
9880 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9881 ipat
= VMX_EPT_IPAT_BIT
;
9882 cache
= MTRR_TYPE_WRBACK
;
9886 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9887 ipat
= VMX_EPT_IPAT_BIT
;
9888 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9889 cache
= MTRR_TYPE_WRBACK
;
9891 cache
= MTRR_TYPE_UNCACHABLE
;
9895 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9898 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9901 static int vmx_get_lpage_level(void)
9903 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9904 return PT_DIRECTORY_LEVEL
;
9906 /* For shadow and EPT supported 1GB page */
9907 return PT_PDPE_LEVEL
;
9910 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9913 * These bits in the secondary execution controls field
9914 * are dynamic, the others are mostly based on the hypervisor
9915 * architecture and the guest's CPUID. Do not touch the
9919 SECONDARY_EXEC_SHADOW_VMCS
|
9920 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9921 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9923 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9925 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9926 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9930 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9931 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9933 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9935 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9936 struct kvm_cpuid_entry2
*entry
;
9938 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9939 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9941 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9942 if (entry && (entry->_reg & (_cpuid_mask))) \
9943 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9946 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9947 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9948 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9949 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9950 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9951 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9952 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9953 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9954 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9955 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9956 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9957 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9958 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9959 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9960 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9962 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9963 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9964 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9965 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9966 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9967 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
9969 #undef cr4_fixed1_update
9972 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9974 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9976 if (cpu_has_secondary_exec_ctrls()) {
9977 vmx_compute_secondary_exec_control(vmx
);
9978 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9981 if (nested_vmx_allowed(vcpu
))
9982 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9983 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9985 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9986 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9988 if (nested_vmx_allowed(vcpu
))
9989 nested_vmx_cr_fixed1_bits_update(vcpu
);
9992 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9994 if (func
== 1 && nested
)
9995 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9998 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9999 struct x86_exception
*fault
)
10001 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10002 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10004 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
10006 if (vmx
->nested
.pml_full
) {
10007 exit_reason
= EXIT_REASON_PML_FULL
;
10008 vmx
->nested
.pml_full
= false;
10009 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
10010 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
10011 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
10013 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
10015 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
10016 vmcs12
->guest_physical_address
= fault
->address
;
10019 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
10021 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
10024 /* Callbacks for nested_ept_init_mmu_context: */
10026 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
10028 /* return the page table to be shadowed - in our case, EPT12 */
10029 return get_vmcs12(vcpu
)->ept_pointer
;
10032 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
10034 WARN_ON(mmu_is_nested(vcpu
));
10035 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
10038 kvm_mmu_unload(vcpu
);
10039 kvm_init_shadow_ept_mmu(vcpu
,
10040 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
10041 VMX_EPT_EXECUTE_ONLY_BIT
,
10042 nested_ept_ad_enabled(vcpu
));
10043 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
10044 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
10045 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
10047 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
10051 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
10053 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
10056 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
10059 bool inequality
, bit
;
10061 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
10063 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
10064 vmcs12
->page_fault_error_code_match
;
10065 return inequality
^ bit
;
10068 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
10069 struct x86_exception
*fault
)
10071 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10073 WARN_ON(!is_guest_mode(vcpu
));
10075 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
10076 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
10077 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
10078 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10079 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
10080 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
10083 kvm_inject_page_fault(vcpu
, fault
);
10087 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10088 struct vmcs12
*vmcs12
);
10090 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
10091 struct vmcs12
*vmcs12
)
10093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10097 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10099 * Translate L1 physical address to host physical
10100 * address for vmcs02. Keep the page pinned, so this
10101 * physical address remains valid. We keep a reference
10102 * to it so we can release it later.
10104 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
10105 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
10106 vmx
->nested
.apic_access_page
= NULL
;
10108 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
10110 * If translation failed, no matter: This feature asks
10111 * to exit when accessing the given address, and if it
10112 * can never be accessed, this feature won't do
10115 if (!is_error_page(page
)) {
10116 vmx
->nested
.apic_access_page
= page
;
10117 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
10118 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
10120 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
10121 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
10123 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
10124 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
10125 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
10126 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
10127 kvm_vcpu_reload_apic_access_page(vcpu
);
10130 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
10131 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
10132 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
10133 vmx
->nested
.virtual_apic_page
= NULL
;
10135 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
10138 * If translation failed, VM entry will fail because
10139 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10140 * Failing the vm entry is _not_ what the processor
10141 * does but it's basically the only possibility we
10142 * have. We could still enter the guest if CR8 load
10143 * exits are enabled, CR8 store exits are enabled, and
10144 * virtualize APIC access is disabled; in this case
10145 * the processor would never use the TPR shadow and we
10146 * could simply clear the bit from the execution
10147 * control. But such a configuration is useless, so
10148 * let's keep the code simple.
10150 if (!is_error_page(page
)) {
10151 vmx
->nested
.virtual_apic_page
= page
;
10152 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
10153 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
10157 if (nested_cpu_has_posted_intr(vmcs12
)) {
10158 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
10159 kunmap(vmx
->nested
.pi_desc_page
);
10160 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
10161 vmx
->nested
.pi_desc_page
= NULL
;
10163 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
10164 if (is_error_page(page
))
10166 vmx
->nested
.pi_desc_page
= page
;
10167 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
10168 vmx
->nested
.pi_desc
=
10169 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
10170 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10172 vmcs_write64(POSTED_INTR_DESC_ADDR
,
10173 page_to_phys(vmx
->nested
.pi_desc_page
) +
10174 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10177 if (cpu_has_vmx_msr_bitmap() &&
10178 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
10179 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
10180 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
10181 CPU_BASED_USE_MSR_BITMAPS
);
10183 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
10184 CPU_BASED_USE_MSR_BITMAPS
);
10187 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
10189 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
10190 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10192 if (vcpu
->arch
.virtual_tsc_khz
== 0)
10195 /* Make sure short timeouts reliably trigger an immediate vmexit.
10196 * hrtimer_start does not guarantee this. */
10197 if (preemption_timeout
<= 1) {
10198 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
10202 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10203 preemption_timeout
*= 1000000;
10204 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
10205 hrtimer_start(&vmx
->nested
.preemption_timer
,
10206 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
10209 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
10210 struct vmcs12
*vmcs12
)
10212 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
10215 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
10216 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
10222 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
10223 struct vmcs12
*vmcs12
)
10225 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10228 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10234 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10235 struct vmcs12
*vmcs12
)
10237 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10240 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10247 * Merge L0's and L1's MSR bitmap, return false to indicate that
10248 * we do not use the hardware.
10250 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10251 struct vmcs12
*vmcs12
)
10255 unsigned long *msr_bitmap_l1
;
10256 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.vmcs02
.msr_bitmap
;
10258 * pred_cmd & spec_ctrl are trying to verify two things:
10260 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10261 * ensures that we do not accidentally generate an L02 MSR bitmap
10262 * from the L12 MSR bitmap that is too permissive.
10263 * 2. That L1 or L2s have actually used the MSR. This avoids
10264 * unnecessarily merging of the bitmap if the MSR is unused. This
10265 * works properly because we only update the L01 MSR bitmap lazily.
10266 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10267 * updated to reflect this when L1 (or its L2s) actually write to
10270 bool pred_cmd
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_PRED_CMD
);
10271 bool spec_ctrl
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_SPEC_CTRL
);
10273 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10274 !pred_cmd
&& !spec_ctrl
)
10277 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10278 if (is_error_page(page
))
10280 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10282 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10284 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10285 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10286 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10287 nested_vmx_disable_intercept_for_msr(
10288 msr_bitmap_l1
, msr_bitmap_l0
,
10291 nested_vmx_disable_intercept_for_msr(
10292 msr_bitmap_l1
, msr_bitmap_l0
,
10293 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10294 MSR_TYPE_R
| MSR_TYPE_W
);
10296 if (nested_cpu_has_vid(vmcs12
)) {
10297 nested_vmx_disable_intercept_for_msr(
10298 msr_bitmap_l1
, msr_bitmap_l0
,
10299 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10301 nested_vmx_disable_intercept_for_msr(
10302 msr_bitmap_l1
, msr_bitmap_l0
,
10303 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10309 nested_vmx_disable_intercept_for_msr(
10310 msr_bitmap_l1
, msr_bitmap_l0
,
10311 MSR_IA32_SPEC_CTRL
,
10312 MSR_TYPE_R
| MSR_TYPE_W
);
10315 nested_vmx_disable_intercept_for_msr(
10316 msr_bitmap_l1
, msr_bitmap_l0
,
10321 kvm_release_page_clean(page
);
10326 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10327 struct vmcs12
*vmcs12
)
10329 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10330 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10331 !nested_cpu_has_vid(vmcs12
) &&
10332 !nested_cpu_has_posted_intr(vmcs12
))
10336 * If virtualize x2apic mode is enabled,
10337 * virtualize apic access must be disabled.
10339 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10340 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10344 * If virtual interrupt delivery is enabled,
10345 * we must exit on external interrupts.
10347 if (nested_cpu_has_vid(vmcs12
) &&
10348 !nested_exit_on_intr(vcpu
))
10352 * bits 15:8 should be zero in posted_intr_nv,
10353 * the descriptor address has been already checked
10354 * in nested_get_vmcs12_pages.
10356 if (nested_cpu_has_posted_intr(vmcs12
) &&
10357 (!nested_cpu_has_vid(vmcs12
) ||
10358 !nested_exit_intr_ack_set(vcpu
) ||
10359 vmcs12
->posted_intr_nv
& 0xff00))
10362 /* tpr shadow is needed by all apicv features. */
10363 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10369 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10370 unsigned long count_field
,
10371 unsigned long addr_field
)
10376 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10377 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10383 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10384 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10385 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10386 pr_debug_ratelimited(
10387 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10388 addr_field
, maxphyaddr
, count
, addr
);
10394 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10395 struct vmcs12
*vmcs12
)
10397 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10398 vmcs12
->vm_exit_msr_store_count
== 0 &&
10399 vmcs12
->vm_entry_msr_load_count
== 0)
10400 return 0; /* Fast path */
10401 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10402 VM_EXIT_MSR_LOAD_ADDR
) ||
10403 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10404 VM_EXIT_MSR_STORE_ADDR
) ||
10405 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10406 VM_ENTRY_MSR_LOAD_ADDR
))
10411 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10412 struct vmcs12
*vmcs12
)
10414 u64 address
= vmcs12
->pml_address
;
10415 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10417 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10418 if (!nested_cpu_has_ept(vmcs12
) ||
10419 !IS_ALIGNED(address
, 4096) ||
10420 address
>> maxphyaddr
)
10427 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10428 struct vmx_msr_entry
*e
)
10430 /* x2APIC MSR accesses are not allowed */
10431 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10433 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10434 e
->index
== MSR_IA32_UCODE_REV
)
10436 if (e
->reserved
!= 0)
10441 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10442 struct vmx_msr_entry
*e
)
10444 if (e
->index
== MSR_FS_BASE
||
10445 e
->index
== MSR_GS_BASE
||
10446 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10447 nested_vmx_msr_check_common(vcpu
, e
))
10452 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10453 struct vmx_msr_entry
*e
)
10455 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10456 nested_vmx_msr_check_common(vcpu
, e
))
10462 * Load guest's/host's msr at nested entry/exit.
10463 * return 0 for success, entry index for failure.
10465 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10468 struct vmx_msr_entry e
;
10469 struct msr_data msr
;
10471 msr
.host_initiated
= false;
10472 for (i
= 0; i
< count
; i
++) {
10473 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10475 pr_debug_ratelimited(
10476 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10477 __func__
, i
, gpa
+ i
* sizeof(e
));
10480 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10481 pr_debug_ratelimited(
10482 "%s check failed (%u, 0x%x, 0x%x)\n",
10483 __func__
, i
, e
.index
, e
.reserved
);
10486 msr
.index
= e
.index
;
10487 msr
.data
= e
.value
;
10488 if (kvm_set_msr(vcpu
, &msr
)) {
10489 pr_debug_ratelimited(
10490 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10491 __func__
, i
, e
.index
, e
.value
);
10500 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10503 struct vmx_msr_entry e
;
10505 for (i
= 0; i
< count
; i
++) {
10506 struct msr_data msr_info
;
10507 if (kvm_vcpu_read_guest(vcpu
,
10508 gpa
+ i
* sizeof(e
),
10509 &e
, 2 * sizeof(u32
))) {
10510 pr_debug_ratelimited(
10511 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10512 __func__
, i
, gpa
+ i
* sizeof(e
));
10515 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10516 pr_debug_ratelimited(
10517 "%s check failed (%u, 0x%x, 0x%x)\n",
10518 __func__
, i
, e
.index
, e
.reserved
);
10521 msr_info
.host_initiated
= false;
10522 msr_info
.index
= e
.index
;
10523 if (kvm_get_msr(vcpu
, &msr_info
)) {
10524 pr_debug_ratelimited(
10525 "%s cannot read MSR (%u, 0x%x)\n",
10526 __func__
, i
, e
.index
);
10529 if (kvm_vcpu_write_guest(vcpu
,
10530 gpa
+ i
* sizeof(e
) +
10531 offsetof(struct vmx_msr_entry
, value
),
10532 &msr_info
.data
, sizeof(msr_info
.data
))) {
10533 pr_debug_ratelimited(
10534 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10535 __func__
, i
, e
.index
, msr_info
.data
);
10542 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10544 unsigned long invalid_mask
;
10546 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10547 return (val
& invalid_mask
) == 0;
10551 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10552 * emulating VM entry into a guest with EPT enabled.
10553 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10554 * is assigned to entry_failure_code on failure.
10556 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10557 u32
*entry_failure_code
)
10559 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10560 if (!nested_cr3_valid(vcpu
, cr3
)) {
10561 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10566 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10567 * must not be dereferenced.
10569 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10571 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10572 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10577 vcpu
->arch
.cr3
= cr3
;
10578 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10581 kvm_mmu_reset_context(vcpu
);
10586 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10587 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10588 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10589 * guest in a way that will both be appropriate to L1's requests, and our
10590 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10591 * function also has additional necessary side-effects, like setting various
10592 * vcpu->arch fields.
10593 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10594 * is assigned to entry_failure_code on failure.
10596 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10597 bool from_vmentry
, u32
*entry_failure_code
)
10599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10600 u32 exec_control
, vmcs12_exec_ctrl
;
10602 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10603 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10604 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10605 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10606 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10607 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10608 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10609 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10610 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10611 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10612 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10613 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10614 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10615 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10616 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10617 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10618 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10619 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10620 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10621 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10622 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10623 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10624 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10625 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10626 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10627 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10628 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10629 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10630 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10631 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10632 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10633 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10634 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10635 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10636 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10637 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10639 if (from_vmentry
&&
10640 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10641 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10642 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10644 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10645 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10647 if (from_vmentry
) {
10648 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10649 vmcs12
->vm_entry_intr_info_field
);
10650 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10651 vmcs12
->vm_entry_exception_error_code
);
10652 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10653 vmcs12
->vm_entry_instruction_len
);
10654 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10655 vmcs12
->guest_interruptibility_info
);
10656 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10657 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10659 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10661 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10662 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10663 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10664 vmcs12
->guest_pending_dbg_exceptions
);
10665 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10666 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10668 if (nested_cpu_has_xsaves(vmcs12
))
10669 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10670 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10672 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10674 /* Preemption timer setting is only taken from vmcs01. */
10675 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10676 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10677 if (vmx
->hv_deadline_tsc
== -1)
10678 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10680 /* Posted interrupts setting is only taken from vmcs12. */
10681 if (nested_cpu_has_posted_intr(vmcs12
)) {
10682 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10683 vmx
->nested
.pi_pending
= false;
10684 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10686 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10689 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10691 vmx
->nested
.preemption_timer_expired
= false;
10692 if (nested_cpu_has_preemption_timer(vmcs12
))
10693 vmx_start_preemption_timer(vcpu
);
10696 * Whether page-faults are trapped is determined by a combination of
10697 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10698 * If enable_ept, L0 doesn't care about page faults and we should
10699 * set all of these to L1's desires. However, if !enable_ept, L0 does
10700 * care about (at least some) page faults, and because it is not easy
10701 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10702 * to exit on each and every L2 page fault. This is done by setting
10703 * MASK=MATCH=0 and (see below) EB.PF=1.
10704 * Note that below we don't need special code to set EB.PF beyond the
10705 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10706 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10707 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10709 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10710 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10711 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10712 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10714 if (cpu_has_secondary_exec_ctrls()) {
10715 exec_control
= vmx
->secondary_exec_control
;
10717 /* Take the following fields only from vmcs12 */
10718 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10719 SECONDARY_EXEC_ENABLE_INVPCID
|
10720 SECONDARY_EXEC_RDTSCP
|
10721 SECONDARY_EXEC_XSAVES
|
10722 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10723 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10724 SECONDARY_EXEC_ENABLE_VMFUNC
);
10725 if (nested_cpu_has(vmcs12
,
10726 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10727 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10728 ~SECONDARY_EXEC_ENABLE_PML
;
10729 exec_control
|= vmcs12_exec_ctrl
;
10732 /* All VMFUNCs are currently emulated through L0 vmexits. */
10733 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10734 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10736 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10737 vmcs_write64(EOI_EXIT_BITMAP0
,
10738 vmcs12
->eoi_exit_bitmap0
);
10739 vmcs_write64(EOI_EXIT_BITMAP1
,
10740 vmcs12
->eoi_exit_bitmap1
);
10741 vmcs_write64(EOI_EXIT_BITMAP2
,
10742 vmcs12
->eoi_exit_bitmap2
);
10743 vmcs_write64(EOI_EXIT_BITMAP3
,
10744 vmcs12
->eoi_exit_bitmap3
);
10745 vmcs_write16(GUEST_INTR_STATUS
,
10746 vmcs12
->guest_intr_status
);
10750 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10751 * nested_get_vmcs12_pages will either fix it up or
10752 * remove the VM execution control.
10754 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10755 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10757 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10762 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10763 * Some constant fields are set here by vmx_set_constant_host_state().
10764 * Other fields are different per CPU, and will be set later when
10765 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10767 vmx_set_constant_host_state(vmx
);
10770 * Set the MSR load/store lists to match L0's settings.
10772 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10773 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10774 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10775 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10776 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10779 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10780 * entry, but only if the current (host) sp changed from the value
10781 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10782 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10783 * here we just force the write to happen on entry.
10787 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10788 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10789 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10790 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10791 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10794 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10795 * nested_get_vmcs12_pages can't fix it up, the illegal value
10796 * will result in a VM entry failure.
10798 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10799 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10800 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10802 #ifdef CONFIG_X86_64
10803 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10804 CPU_BASED_CR8_STORE_EXITING
;
10809 * Merging of IO bitmap not currently supported.
10810 * Rather, exit every time.
10812 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10813 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10815 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10817 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10818 * bitwise-or of what L1 wants to trap for L2, and what we want to
10819 * trap. Note that CR0.TS also needs updating - we do this later.
10821 update_exception_bitmap(vcpu
);
10822 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10823 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10825 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10826 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10827 * bits are further modified by vmx_set_efer() below.
10829 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10831 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10832 * emulated by vmx_set_efer(), below.
10834 vm_entry_controls_init(vmx
,
10835 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10836 ~VM_ENTRY_IA32E_MODE
) |
10837 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10839 if (from_vmentry
&&
10840 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10841 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10842 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10843 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10844 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10847 set_cr4_guest_host_mask(vmx
);
10849 if (from_vmentry
&&
10850 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10851 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10853 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10854 vmcs_write64(TSC_OFFSET
,
10855 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10857 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10858 if (kvm_has_tsc_control
)
10859 decache_tsc_multiplier(vmx
);
10861 if (cpu_has_vmx_msr_bitmap())
10862 vmcs_write64(MSR_BITMAP
, __pa(vmx
->nested
.vmcs02
.msr_bitmap
));
10866 * There is no direct mapping between vpid02 and vpid12, the
10867 * vpid02 is per-vCPU for L0 and reused while the value of
10868 * vpid12 is changed w/ one invvpid during nested vmentry.
10869 * The vpid12 is allocated by L1 for L2, so it will not
10870 * influence global bitmap(for vpid01 and vpid02 allocation)
10871 * even if spawn a lot of nested vCPUs.
10873 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10874 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10875 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10876 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10877 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10880 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10881 vmx_flush_tlb(vcpu
);
10888 * Conceptually we want to copy the PML address and index from
10889 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10890 * since we always flush the log on each vmexit, this happens
10891 * to be equivalent to simply resetting the fields in vmcs02.
10893 ASSERT(vmx
->pml_pg
);
10894 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10895 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10898 if (nested_cpu_has_ept(vmcs12
)) {
10899 if (nested_ept_init_mmu_context(vcpu
)) {
10900 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10903 } else if (nested_cpu_has2(vmcs12
,
10904 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10905 vmx_flush_tlb_ept_only(vcpu
);
10909 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10910 * bits which we consider mandatory enabled.
10911 * The CR0_READ_SHADOW is what L2 should have expected to read given
10912 * the specifications by L1; It's not enough to take
10913 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10914 * have more bits than L1 expected.
10916 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10917 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10919 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10920 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10922 if (from_vmentry
&&
10923 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10924 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10925 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10926 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10928 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10929 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10930 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10932 /* Shadow page tables on either EPT or shadow page tables. */
10933 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10934 entry_failure_code
))
10938 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10941 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10944 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10945 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10946 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10947 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10950 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10951 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10955 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10959 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10960 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10961 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10963 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10964 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10966 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10967 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10969 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10970 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10972 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10973 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10975 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10976 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10978 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10979 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10981 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10982 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10983 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10984 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10985 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10986 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10987 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10988 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10989 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10990 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10991 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10992 vmx
->nested
.nested_vmx_exit_ctls_low
,
10993 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10994 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10995 vmx
->nested
.nested_vmx_entry_ctls_low
,
10996 vmx
->nested
.nested_vmx_entry_ctls_high
))
10997 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10999 if (nested_cpu_has_vmfunc(vmcs12
)) {
11000 if (vmcs12
->vm_function_control
&
11001 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
11002 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11004 if (nested_cpu_has_eptp_switching(vmcs12
)) {
11005 if (!nested_cpu_has_ept(vmcs12
) ||
11006 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
11007 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11011 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
11012 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11014 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
11015 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
11016 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
11017 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
11022 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11027 *exit_qual
= ENTRY_FAIL_DEFAULT
;
11029 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
11030 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
11033 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
11034 vmcs12
->vmcs_link_pointer
!= -1ull) {
11035 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
11040 * If the load IA32_EFER VM-entry control is 1, the following checks
11041 * are performed on the field for the IA32_EFER MSR:
11042 * - Bits reserved in the IA32_EFER MSR must be 0.
11043 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11044 * the IA-32e mode guest VM-exit control. It must also be identical
11045 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11048 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
11049 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
11050 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
11051 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
11052 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
11053 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
11054 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
11059 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11060 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11061 * the values of the LMA and LME bits in the field must each be that of
11062 * the host address-space size VM-exit control.
11064 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
11065 ia32e
= (vmcs12
->vm_exit_controls
&
11066 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
11067 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
11068 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
11069 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
11073 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
11074 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
11075 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
11081 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
11083 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11084 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11088 enter_guest_mode(vcpu
);
11090 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
11091 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11093 vmx_switch_vmcs(vcpu
, &vmx
->nested
.vmcs02
);
11094 vmx_segment_cache_clear(vmx
);
11096 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
11097 leave_guest_mode(vcpu
);
11098 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11099 nested_vmx_entry_failure(vcpu
, vmcs12
,
11100 EXIT_REASON_INVALID_STATE
, exit_qual
);
11104 nested_get_vmcs12_pages(vcpu
, vmcs12
);
11106 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
11107 vmcs12
->vm_entry_msr_load_addr
,
11108 vmcs12
->vm_entry_msr_load_count
);
11109 if (msr_entry_idx
) {
11110 leave_guest_mode(vcpu
);
11111 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11112 nested_vmx_entry_failure(vcpu
, vmcs12
,
11113 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
11118 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11119 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11120 * returned as far as L1 is concerned. It will only return (and set
11121 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11127 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11128 * for running an L2 nested guest.
11130 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
11132 struct vmcs12
*vmcs12
;
11133 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11134 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
11138 if (!nested_vmx_check_permission(vcpu
))
11141 if (!nested_vmx_check_vmcs12(vcpu
))
11144 vmcs12
= get_vmcs12(vcpu
);
11146 if (enable_shadow_vmcs
)
11147 copy_shadow_to_vmcs12(vmx
);
11150 * The nested entry process starts with enforcing various prerequisites
11151 * on vmcs12 as required by the Intel SDM, and act appropriately when
11152 * they fail: As the SDM explains, some conditions should cause the
11153 * instruction to fail, while others will cause the instruction to seem
11154 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11155 * To speed up the normal (success) code path, we should avoid checking
11156 * for misconfigurations which will anyway be caught by the processor
11157 * when using the merged vmcs02.
11159 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
11160 nested_vmx_failValid(vcpu
,
11161 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
11165 if (vmcs12
->launch_state
== launch
) {
11166 nested_vmx_failValid(vcpu
,
11167 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11168 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
11172 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
11174 nested_vmx_failValid(vcpu
, ret
);
11179 * After this point, the trap flag no longer triggers a singlestep trap
11180 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11181 * This is not 100% correct; for performance reasons, we delegate most
11182 * of the checks on host state to the processor. If those fail,
11183 * the singlestep trap is missed.
11185 skip_emulated_instruction(vcpu
);
11187 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
11189 nested_vmx_entry_failure(vcpu
, vmcs12
,
11190 EXIT_REASON_INVALID_STATE
, exit_qual
);
11195 * We're finally done with prerequisite checking, and can start with
11196 * the nested entry.
11199 ret
= enter_vmx_non_root_mode(vcpu
, true);
11203 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
11204 return kvm_vcpu_halt(vcpu
);
11206 vmx
->nested
.nested_run_pending
= 1;
11211 return kvm_skip_emulated_instruction(vcpu
);
11215 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11216 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11217 * This function returns the new value we should put in vmcs12.guest_cr0.
11218 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11219 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11220 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11221 * didn't trap the bit, because if L1 did, so would L0).
11222 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11223 * been modified by L2, and L1 knows it. So just leave the old value of
11224 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11225 * isn't relevant, because if L0 traps this bit it can set it to anything.
11226 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11227 * changed these bits, and therefore they need to be updated, but L0
11228 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11229 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11231 static inline unsigned long
11232 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11235 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
11236 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
11237 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
11238 vcpu
->arch
.cr0_guest_owned_bits
));
11241 static inline unsigned long
11242 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11245 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
11246 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
11247 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
11248 vcpu
->arch
.cr4_guest_owned_bits
));
11251 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
11252 struct vmcs12
*vmcs12
)
11257 if (vcpu
->arch
.exception
.injected
) {
11258 nr
= vcpu
->arch
.exception
.nr
;
11259 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11261 if (kvm_exception_is_soft(nr
)) {
11262 vmcs12
->vm_exit_instruction_len
=
11263 vcpu
->arch
.event_exit_inst_len
;
11264 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11266 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11268 if (vcpu
->arch
.exception
.has_error_code
) {
11269 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11270 vmcs12
->idt_vectoring_error_code
=
11271 vcpu
->arch
.exception
.error_code
;
11274 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11275 } else if (vcpu
->arch
.nmi_injected
) {
11276 vmcs12
->idt_vectoring_info_field
=
11277 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11278 } else if (vcpu
->arch
.interrupt
.pending
) {
11279 nr
= vcpu
->arch
.interrupt
.nr
;
11280 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11282 if (vcpu
->arch
.interrupt
.soft
) {
11283 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11284 vmcs12
->vm_entry_instruction_len
=
11285 vcpu
->arch
.event_exit_inst_len
;
11287 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11289 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11293 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11295 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11296 unsigned long exit_qual
;
11297 bool block_nested_events
=
11298 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
11300 if (vcpu
->arch
.exception
.pending
&&
11301 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11302 if (block_nested_events
)
11304 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11308 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11309 vmx
->nested
.preemption_timer_expired
) {
11310 if (block_nested_events
)
11312 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11316 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11317 if (block_nested_events
)
11319 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11320 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11321 INTR_INFO_VALID_MASK
, 0);
11323 * The NMI-triggered VM exit counts as injection:
11324 * clear this one and block further NMIs.
11326 vcpu
->arch
.nmi_pending
= 0;
11327 vmx_set_nmi_mask(vcpu
, true);
11331 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11332 nested_exit_on_intr(vcpu
)) {
11333 if (block_nested_events
)
11335 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11339 vmx_complete_nested_posted_interrupt(vcpu
);
11343 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11345 ktime_t remaining
=
11346 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11349 if (ktime_to_ns(remaining
) <= 0)
11352 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11353 do_div(value
, 1000000);
11354 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11358 * Update the guest state fields of vmcs12 to reflect changes that
11359 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11360 * VM-entry controls is also updated, since this is really a guest
11363 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11365 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11366 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11368 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11369 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11370 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11372 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11373 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11374 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11375 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11376 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11377 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11378 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11379 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11380 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11381 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11382 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11383 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11384 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11385 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11386 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11387 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11388 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11389 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11390 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11391 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11392 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11393 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11394 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11395 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11396 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11397 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11398 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11399 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11400 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11401 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11402 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11403 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11404 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11405 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11406 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11407 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11409 vmcs12
->guest_interruptibility_info
=
11410 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11411 vmcs12
->guest_pending_dbg_exceptions
=
11412 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11413 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11414 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11416 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11418 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11419 if (vmcs12
->vm_exit_controls
&
11420 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11421 vmcs12
->vmx_preemption_timer_value
=
11422 vmx_get_preemption_timer_value(vcpu
);
11423 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11427 * In some cases (usually, nested EPT), L2 is allowed to change its
11428 * own CR3 without exiting. If it has changed it, we must keep it.
11429 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11430 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11432 * Additionally, restore L2's PDPTR to vmcs12.
11435 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11436 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11437 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11438 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11439 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11442 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11444 if (nested_cpu_has_vid(vmcs12
))
11445 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11447 vmcs12
->vm_entry_controls
=
11448 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11449 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11451 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11452 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11453 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11456 /* TODO: These cannot have changed unless we have MSR bitmaps and
11457 * the relevant bit asks not to trap the change */
11458 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11459 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11460 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11461 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11462 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11463 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11464 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11465 if (kvm_mpx_supported())
11466 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11470 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11471 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11472 * and this function updates it to reflect the changes to the guest state while
11473 * L2 was running (and perhaps made some exits which were handled directly by L0
11474 * without going back to L1), and to reflect the exit reason.
11475 * Note that we do not have to copy here all VMCS fields, just those that
11476 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11477 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11478 * which already writes to vmcs12 directly.
11480 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11481 u32 exit_reason
, u32 exit_intr_info
,
11482 unsigned long exit_qualification
)
11484 /* update guest state fields: */
11485 sync_vmcs12(vcpu
, vmcs12
);
11487 /* update exit information fields: */
11489 vmcs12
->vm_exit_reason
= exit_reason
;
11490 vmcs12
->exit_qualification
= exit_qualification
;
11491 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11493 vmcs12
->idt_vectoring_info_field
= 0;
11494 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11495 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11497 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11498 vmcs12
->launch_state
= 1;
11500 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11501 * instead of reading the real value. */
11502 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11505 * Transfer the event that L0 or L1 may wanted to inject into
11506 * L2 to IDT_VECTORING_INFO_FIELD.
11508 vmcs12_save_pending_event(vcpu
, vmcs12
);
11512 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11513 * preserved above and would only end up incorrectly in L1.
11515 vcpu
->arch
.nmi_injected
= false;
11516 kvm_clear_exception_queue(vcpu
);
11517 kvm_clear_interrupt_queue(vcpu
);
11520 static void load_vmcs12_mmu_host_state(struct kvm_vcpu
*vcpu
,
11521 struct vmcs12
*vmcs12
)
11523 u32 entry_failure_code
;
11525 nested_ept_uninit_mmu_context(vcpu
);
11528 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11529 * couldn't have changed.
11531 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11532 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11535 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11539 * A part of what we need to when the nested L2 guest exits and we want to
11540 * run its L1 parent, is to reset L1's guest state to the host state specified
11542 * This function is to be called not only on normal nested exit, but also on
11543 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11544 * Failures During or After Loading Guest State").
11545 * This function should be called when the active VMCS is L1's (vmcs01).
11547 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11548 struct vmcs12
*vmcs12
)
11550 struct kvm_segment seg
;
11552 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11553 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11554 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11555 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11557 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11558 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11560 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11561 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11562 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11564 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11565 * actually changed, because vmx_set_cr0 refers to efer set above.
11567 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11568 * (KVM doesn't change it);
11570 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11571 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11573 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11574 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11575 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11577 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11581 * Trivially support vpid by letting L2s share their parent
11582 * L1's vpid. TODO: move to a more elaborate solution, giving
11583 * each L2 its own vpid and exposing the vpid feature to L1.
11585 vmx_flush_tlb(vcpu
);
11587 /* Restore posted intr vector. */
11588 if (nested_cpu_has_posted_intr(vmcs12
))
11589 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11591 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11592 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11593 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11594 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11595 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11596 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11597 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11599 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11600 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11601 vmcs_write64(GUEST_BNDCFGS
, 0);
11603 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11604 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11605 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11607 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11608 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11609 vmcs12
->host_ia32_perf_global_ctrl
);
11611 /* Set L1 segment info according to Intel SDM
11612 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11613 seg
= (struct kvm_segment
) {
11615 .limit
= 0xFFFFFFFF,
11616 .selector
= vmcs12
->host_cs_selector
,
11622 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11626 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11627 seg
= (struct kvm_segment
) {
11629 .limit
= 0xFFFFFFFF,
11636 seg
.selector
= vmcs12
->host_ds_selector
;
11637 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11638 seg
.selector
= vmcs12
->host_es_selector
;
11639 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11640 seg
.selector
= vmcs12
->host_ss_selector
;
11641 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11642 seg
.selector
= vmcs12
->host_fs_selector
;
11643 seg
.base
= vmcs12
->host_fs_base
;
11644 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11645 seg
.selector
= vmcs12
->host_gs_selector
;
11646 seg
.base
= vmcs12
->host_gs_base
;
11647 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11648 seg
= (struct kvm_segment
) {
11649 .base
= vmcs12
->host_tr_base
,
11651 .selector
= vmcs12
->host_tr_selector
,
11655 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11657 kvm_set_dr(vcpu
, 7, 0x400);
11658 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11660 if (cpu_has_vmx_msr_bitmap())
11661 vmx_update_msr_bitmap(vcpu
);
11663 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11664 vmcs12
->vm_exit_msr_load_count
))
11665 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11669 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11670 * and modify vmcs12 to make it see what it would expect to see there if
11671 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11673 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11674 u32 exit_intr_info
,
11675 unsigned long exit_qualification
)
11677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11678 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11680 /* trying to cancel vmlaunch/vmresume is a bug */
11681 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11684 * The only expected VM-instruction error is "VM entry with
11685 * invalid control field(s)." Anything else indicates a
11688 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11689 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11691 leave_guest_mode(vcpu
);
11693 if (likely(!vmx
->fail
)) {
11694 if (exit_reason
== -1)
11695 sync_vmcs12(vcpu
, vmcs12
);
11697 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11698 exit_qualification
);
11700 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11701 vmcs12
->vm_exit_msr_store_count
))
11702 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11705 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11706 vm_entry_controls_reset_shadow(vmx
);
11707 vm_exit_controls_reset_shadow(vmx
);
11708 vmx_segment_cache_clear(vmx
);
11710 /* Update any VMCS fields that might have changed while L2 ran */
11711 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11712 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11713 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11714 if (vmx
->hv_deadline_tsc
== -1)
11715 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11716 PIN_BASED_VMX_PREEMPTION_TIMER
);
11718 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11719 PIN_BASED_VMX_PREEMPTION_TIMER
);
11720 if (kvm_has_tsc_control
)
11721 decache_tsc_multiplier(vmx
);
11723 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11724 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11725 vmx_set_virtual_x2apic_mode(vcpu
,
11726 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11727 } else if (!nested_cpu_has_ept(vmcs12
) &&
11728 nested_cpu_has2(vmcs12
,
11729 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11730 vmx_flush_tlb_ept_only(vcpu
);
11733 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11736 /* Unpin physical memory we referred to in vmcs02 */
11737 if (vmx
->nested
.apic_access_page
) {
11738 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11739 vmx
->nested
.apic_access_page
= NULL
;
11741 if (vmx
->nested
.virtual_apic_page
) {
11742 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11743 vmx
->nested
.virtual_apic_page
= NULL
;
11745 if (vmx
->nested
.pi_desc_page
) {
11746 kunmap(vmx
->nested
.pi_desc_page
);
11747 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11748 vmx
->nested
.pi_desc_page
= NULL
;
11749 vmx
->nested
.pi_desc
= NULL
;
11753 * We are now running in L2, mmu_notifier will force to reload the
11754 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11756 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11758 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11759 vmx
->nested
.sync_shadow_vmcs
= true;
11761 /* in case we halted in L2 */
11762 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11764 if (likely(!vmx
->fail
)) {
11766 * TODO: SDM says that with acknowledge interrupt on
11767 * exit, bit 31 of the VM-exit interrupt information
11768 * (valid interrupt) is always set to 1 on
11769 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11770 * need kvm_cpu_has_interrupt(). See the commit
11771 * message for details.
11773 if (nested_exit_intr_ack_set(vcpu
) &&
11774 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11775 kvm_cpu_has_interrupt(vcpu
)) {
11776 int irq
= kvm_cpu_get_interrupt(vcpu
);
11778 vmcs12
->vm_exit_intr_info
= irq
|
11779 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11782 if (exit_reason
!= -1)
11783 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11784 vmcs12
->exit_qualification
,
11785 vmcs12
->idt_vectoring_info_field
,
11786 vmcs12
->vm_exit_intr_info
,
11787 vmcs12
->vm_exit_intr_error_code
,
11790 load_vmcs12_host_state(vcpu
, vmcs12
);
11796 * After an early L2 VM-entry failure, we're now back
11797 * in L1 which thinks it just finished a VMLAUNCH or
11798 * VMRESUME instruction, so we need to set the failure
11799 * flag and the VM-instruction error field of the VMCS
11802 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11804 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11807 * The emulated instruction was already skipped in
11808 * nested_vmx_run, but the updated RIP was never
11809 * written back to the vmcs01.
11811 skip_emulated_instruction(vcpu
);
11816 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11818 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11820 if (is_guest_mode(vcpu
)) {
11821 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11822 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11824 free_nested(to_vmx(vcpu
));
11828 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11829 * 23.7 "VM-entry failures during or after loading guest state" (this also
11830 * lists the acceptable exit-reason and exit-qualification parameters).
11831 * It should only be called before L2 actually succeeded to run, and when
11832 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11834 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11835 struct vmcs12
*vmcs12
,
11836 u32 reason
, unsigned long qualification
)
11838 load_vmcs12_host_state(vcpu
, vmcs12
);
11839 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11840 vmcs12
->exit_qualification
= qualification
;
11841 nested_vmx_succeed(vcpu
);
11842 if (enable_shadow_vmcs
)
11843 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11846 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11847 struct x86_instruction_info
*info
,
11848 enum x86_intercept_stage stage
)
11850 return X86EMUL_CONTINUE
;
11853 #ifdef CONFIG_X86_64
11854 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11855 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11856 u64 divisor
, u64
*result
)
11858 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11860 /* To avoid the overflow on divq */
11861 if (high
>= divisor
)
11864 /* Low hold the result, high hold rem which is discarded */
11865 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11866 "rm" (divisor
), "0" (low
), "1" (high
));
11872 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11874 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11875 u64 tscl
= rdtsc();
11876 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11877 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11879 /* Convert to host delta tsc if tsc scaling is enabled */
11880 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11881 u64_shl_div_u64(delta_tsc
,
11882 kvm_tsc_scaling_ratio_frac_bits
,
11883 vcpu
->arch
.tsc_scaling_ratio
,
11888 * If the delta tsc can't fit in the 32 bit after the multi shift,
11889 * we can't use the preemption timer.
11890 * It's possible that it fits on later vmentries, but checking
11891 * on every vmentry is costly so we just use an hrtimer.
11893 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11896 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11897 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11898 PIN_BASED_VMX_PREEMPTION_TIMER
);
11900 return delta_tsc
== 0;
11903 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11905 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11906 vmx
->hv_deadline_tsc
= -1;
11907 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11908 PIN_BASED_VMX_PREEMPTION_TIMER
);
11912 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11915 shrink_ple_window(vcpu
);
11918 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11919 struct kvm_memory_slot
*slot
)
11921 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11922 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11925 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11926 struct kvm_memory_slot
*slot
)
11928 kvm_mmu_slot_set_dirty(kvm
, slot
);
11931 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11933 kvm_flush_pml_buffers(kvm
);
11936 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11938 struct vmcs12
*vmcs12
;
11939 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11941 struct page
*page
= NULL
;
11944 if (is_guest_mode(vcpu
)) {
11945 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11948 * Check if PML is enabled for the nested guest.
11949 * Whether eptp bit 6 is set is already checked
11950 * as part of A/D emulation.
11952 vmcs12
= get_vmcs12(vcpu
);
11953 if (!nested_cpu_has_pml(vmcs12
))
11956 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11957 vmx
->nested
.pml_full
= true;
11961 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11963 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11964 if (is_error_page(page
))
11967 pml_address
= kmap(page
);
11968 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11970 kvm_release_page_clean(page
);
11976 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11977 struct kvm_memory_slot
*memslot
,
11978 gfn_t offset
, unsigned long mask
)
11980 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11983 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11985 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11986 struct pi_desc old
, new;
11990 old
.control
= new.control
= pi_desc
->control
;
11991 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11992 "Wakeup handler not enabled while the VCPU is blocked\n");
11994 dest
= cpu_physical_id(vcpu
->cpu
);
11996 if (x2apic_enabled())
11999 new.ndst
= (dest
<< 8) & 0xFF00;
12001 /* set 'NV' to 'notification vector' */
12002 new.nv
= POSTED_INTR_VECTOR
;
12003 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12004 new.control
) != old
.control
);
12006 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
12007 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12008 list_del(&vcpu
->blocked_vcpu_list
);
12009 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12010 vcpu
->pre_pcpu
= -1;
12015 * This routine does the following things for vCPU which is going
12016 * to be blocked if VT-d PI is enabled.
12017 * - Store the vCPU to the wakeup list, so when interrupts happen
12018 * we can find the right vCPU to wake up.
12019 * - Change the Posted-interrupt descriptor as below:
12020 * 'NDST' <-- vcpu->pre_pcpu
12021 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12022 * - If 'ON' is set during this process, which means at least one
12023 * interrupt is posted for this vCPU, we cannot block it, in
12024 * this case, return 1, otherwise, return 0.
12027 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
12030 struct pi_desc old
, new;
12031 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
12033 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
12034 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12035 !kvm_vcpu_apicv_active(vcpu
))
12038 WARN_ON(irqs_disabled());
12039 local_irq_disable();
12040 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
12041 vcpu
->pre_pcpu
= vcpu
->cpu
;
12042 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12043 list_add_tail(&vcpu
->blocked_vcpu_list
,
12044 &per_cpu(blocked_vcpu_on_cpu
,
12046 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12050 old
.control
= new.control
= pi_desc
->control
;
12052 WARN((pi_desc
->sn
== 1),
12053 "Warning: SN field of posted-interrupts "
12054 "is set before blocking\n");
12057 * Since vCPU can be preempted during this process,
12058 * vcpu->cpu could be different with pre_pcpu, we
12059 * need to set pre_pcpu as the destination of wakeup
12060 * notification event, then we can find the right vCPU
12061 * to wakeup in wakeup handler if interrupts happen
12062 * when the vCPU is in blocked state.
12064 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
12066 if (x2apic_enabled())
12069 new.ndst
= (dest
<< 8) & 0xFF00;
12071 /* set 'NV' to 'wakeup vector' */
12072 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
12073 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12074 new.control
) != old
.control
);
12076 /* We should not block the vCPU if an interrupt is posted for it. */
12077 if (pi_test_on(pi_desc
) == 1)
12078 __pi_post_block(vcpu
);
12080 local_irq_enable();
12081 return (vcpu
->pre_pcpu
== -1);
12084 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
12086 if (pi_pre_block(vcpu
))
12089 if (kvm_lapic_hv_timer_in_use(vcpu
))
12090 kvm_lapic_switch_to_sw_timer(vcpu
);
12095 static void pi_post_block(struct kvm_vcpu
*vcpu
)
12097 if (vcpu
->pre_pcpu
== -1)
12100 WARN_ON(irqs_disabled());
12101 local_irq_disable();
12102 __pi_post_block(vcpu
);
12103 local_irq_enable();
12106 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
12108 if (kvm_x86_ops
->set_hv_timer
)
12109 kvm_lapic_switch_to_hv_timer(vcpu
);
12111 pi_post_block(vcpu
);
12115 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12118 * @host_irq: host irq of the interrupt
12119 * @guest_irq: gsi of the interrupt
12120 * @set: set or unset PI
12121 * returns 0 on success, < 0 on failure
12123 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
12124 uint32_t guest_irq
, bool set
)
12126 struct kvm_kernel_irq_routing_entry
*e
;
12127 struct kvm_irq_routing_table
*irq_rt
;
12128 struct kvm_lapic_irq irq
;
12129 struct kvm_vcpu
*vcpu
;
12130 struct vcpu_data vcpu_info
;
12133 if (!kvm_arch_has_assigned_device(kvm
) ||
12134 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12135 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
12138 idx
= srcu_read_lock(&kvm
->irq_srcu
);
12139 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
12140 if (guest_irq
>= irq_rt
->nr_rt_entries
||
12141 hlist_empty(&irq_rt
->map
[guest_irq
])) {
12142 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12143 guest_irq
, irq_rt
->nr_rt_entries
);
12147 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
12148 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
12151 * VT-d PI cannot support posting multicast/broadcast
12152 * interrupts to a vCPU, we still use interrupt remapping
12153 * for these kind of interrupts.
12155 * For lowest-priority interrupts, we only support
12156 * those with single CPU as the destination, e.g. user
12157 * configures the interrupts via /proc/irq or uses
12158 * irqbalance to make the interrupts single-CPU.
12160 * We will support full lowest-priority interrupt later.
12163 kvm_set_msi_irq(kvm
, e
, &irq
);
12164 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
12166 * Make sure the IRTE is in remapped mode if
12167 * we don't handle it in posted mode.
12169 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12172 "failed to back to remapped mode, irq: %u\n",
12180 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
12181 vcpu_info
.vector
= irq
.vector
;
12183 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
12184 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
12187 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
12189 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12192 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
12200 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
12204 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
12206 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
12207 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
12208 FEATURE_CONTROL_LMCE
;
12210 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
12211 ~FEATURE_CONTROL_LMCE
;
12214 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
12216 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12217 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
12222 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
12224 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12226 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
12227 if (vmx
->nested
.smm
.guest_mode
)
12228 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12230 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
12231 vmx
->nested
.vmxon
= false;
12235 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
12237 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12240 if (vmx
->nested
.smm
.vmxon
) {
12241 vmx
->nested
.vmxon
= true;
12242 vmx
->nested
.smm
.vmxon
= false;
12245 if (vmx
->nested
.smm
.guest_mode
) {
12246 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
12247 ret
= enter_vmx_non_root_mode(vcpu
, false);
12248 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
12252 vmx
->nested
.smm
.guest_mode
= false;
12257 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
12262 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
12263 .cpu_has_kvm_support
= cpu_has_kvm_support
,
12264 .disabled_by_bios
= vmx_disabled_by_bios
,
12265 .hardware_setup
= hardware_setup
,
12266 .hardware_unsetup
= hardware_unsetup
,
12267 .check_processor_compatibility
= vmx_check_processor_compat
,
12268 .hardware_enable
= hardware_enable
,
12269 .hardware_disable
= hardware_disable
,
12270 .cpu_has_accelerated_tpr
= report_flexpriority
,
12271 .has_emulated_msr
= vmx_has_emulated_msr
,
12273 .vm_init
= vmx_vm_init
,
12275 .vcpu_create
= vmx_create_vcpu
,
12276 .vcpu_free
= vmx_free_vcpu
,
12277 .vcpu_reset
= vmx_vcpu_reset
,
12279 .prepare_guest_switch
= vmx_save_host_state
,
12280 .vcpu_load
= vmx_vcpu_load
,
12281 .vcpu_put
= vmx_vcpu_put
,
12283 .update_bp_intercept
= update_exception_bitmap
,
12284 .get_msr
= vmx_get_msr
,
12285 .set_msr
= vmx_set_msr
,
12286 .get_segment_base
= vmx_get_segment_base
,
12287 .get_segment
= vmx_get_segment
,
12288 .set_segment
= vmx_set_segment
,
12289 .get_cpl
= vmx_get_cpl
,
12290 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12291 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12292 .decache_cr3
= vmx_decache_cr3
,
12293 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12294 .set_cr0
= vmx_set_cr0
,
12295 .set_cr3
= vmx_set_cr3
,
12296 .set_cr4
= vmx_set_cr4
,
12297 .set_efer
= vmx_set_efer
,
12298 .get_idt
= vmx_get_idt
,
12299 .set_idt
= vmx_set_idt
,
12300 .get_gdt
= vmx_get_gdt
,
12301 .set_gdt
= vmx_set_gdt
,
12302 .get_dr6
= vmx_get_dr6
,
12303 .set_dr6
= vmx_set_dr6
,
12304 .set_dr7
= vmx_set_dr7
,
12305 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12306 .cache_reg
= vmx_cache_reg
,
12307 .get_rflags
= vmx_get_rflags
,
12308 .set_rflags
= vmx_set_rflags
,
12310 .tlb_flush
= vmx_flush_tlb
,
12312 .run
= vmx_vcpu_run
,
12313 .handle_exit
= vmx_handle_exit
,
12314 .skip_emulated_instruction
= skip_emulated_instruction
,
12315 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12316 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12317 .patch_hypercall
= vmx_patch_hypercall
,
12318 .set_irq
= vmx_inject_irq
,
12319 .set_nmi
= vmx_inject_nmi
,
12320 .queue_exception
= vmx_queue_exception
,
12321 .cancel_injection
= vmx_cancel_injection
,
12322 .interrupt_allowed
= vmx_interrupt_allowed
,
12323 .nmi_allowed
= vmx_nmi_allowed
,
12324 .get_nmi_mask
= vmx_get_nmi_mask
,
12325 .set_nmi_mask
= vmx_set_nmi_mask
,
12326 .enable_nmi_window
= enable_nmi_window
,
12327 .enable_irq_window
= enable_irq_window
,
12328 .update_cr8_intercept
= update_cr8_intercept
,
12329 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12330 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12331 .get_enable_apicv
= vmx_get_enable_apicv
,
12332 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12333 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12334 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12335 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12336 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12337 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12338 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12340 .set_tss_addr
= vmx_set_tss_addr
,
12341 .get_tdp_level
= get_ept_level
,
12342 .get_mt_mask
= vmx_get_mt_mask
,
12344 .get_exit_info
= vmx_get_exit_info
,
12346 .get_lpage_level
= vmx_get_lpage_level
,
12348 .cpuid_update
= vmx_cpuid_update
,
12350 .rdtscp_supported
= vmx_rdtscp_supported
,
12351 .invpcid_supported
= vmx_invpcid_supported
,
12353 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12355 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12357 .write_tsc_offset
= vmx_write_tsc_offset
,
12359 .set_tdp_cr3
= vmx_set_cr3
,
12361 .check_intercept
= vmx_check_intercept
,
12362 .handle_external_intr
= vmx_handle_external_intr
,
12363 .mpx_supported
= vmx_mpx_supported
,
12364 .xsaves_supported
= vmx_xsaves_supported
,
12366 .check_nested_events
= vmx_check_nested_events
,
12368 .sched_in
= vmx_sched_in
,
12370 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12371 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12372 .flush_log_dirty
= vmx_flush_log_dirty
,
12373 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12374 .write_log_dirty
= vmx_write_pml_buffer
,
12376 .pre_block
= vmx_pre_block
,
12377 .post_block
= vmx_post_block
,
12379 .pmu_ops
= &intel_pmu_ops
,
12381 .update_pi_irte
= vmx_update_pi_irte
,
12383 #ifdef CONFIG_X86_64
12384 .set_hv_timer
= vmx_set_hv_timer
,
12385 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12388 .setup_mce
= vmx_setup_mce
,
12390 .smi_allowed
= vmx_smi_allowed
,
12391 .pre_enter_smm
= vmx_pre_enter_smm
,
12392 .pre_leave_smm
= vmx_pre_leave_smm
,
12393 .enable_smi_window
= enable_smi_window
,
12396 static int __init
vmx_init(void)
12398 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12399 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12403 #ifdef CONFIG_KEXEC_CORE
12404 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12405 crash_vmclear_local_loaded_vmcss
);
12411 static void __exit
vmx_exit(void)
12413 #ifdef CONFIG_KEXEC_CORE
12414 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12421 module_init(vmx_init
)
12422 module_exit(vmx_exit
)