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[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define CREATE_TRACE_POINTS
72 #include "trace.h"
73
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
82 /* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86 #ifdef CONFIG_X86_64
87 static
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 #else
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
91 #endif
92
93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void enter_smm(struct kvm_vcpu *vcpu);
102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103
104 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
105 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106
107 static bool __read_mostly ignore_msrs = 0;
108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109
110 static bool __read_mostly report_ignored_msrs = true;
111 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
113 unsigned int min_timer_period_us = 200;
114 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
116 static bool __read_mostly kvmclock_periodic_sync = true;
117 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
119 bool __read_mostly kvm_has_tsc_control;
120 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
121 u32 __read_mostly kvm_max_guest_tsc_khz;
122 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
123 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125 u64 __read_mostly kvm_max_tsc_scaling_ratio;
126 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
127 u64 __read_mostly kvm_default_tsc_scaling_ratio;
128 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
129
130 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
131 static u32 __read_mostly tsc_tolerance_ppm = 250;
132 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
134 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
135 unsigned int __read_mostly lapic_timer_advance_ns = 0;
136 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
138 static bool __read_mostly vector_hashing = true;
139 module_param(vector_hashing, bool, S_IRUGO);
140
141 #define KVM_NR_SHARED_MSRS 16
142
143 struct kvm_shared_msrs_global {
144 int nr;
145 u32 msrs[KVM_NR_SHARED_MSRS];
146 };
147
148 struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
155 };
156
157 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
158 static struct kvm_shared_msrs __percpu *shared_msrs;
159
160 struct kvm_stats_debugfs_item debugfs_entries[] = {
161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
171 { "halt_exits", VCPU_STAT(halt_exits) },
172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
176 { "hypercalls", VCPU_STAT(hypercalls) },
177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
184 { "irq_injections", VCPU_STAT(irq_injections) },
185 { "nmi_injections", VCPU_STAT(nmi_injections) },
186 { "req_event", VCPU_STAT(req_event) },
187 { "l1d_flush", VCPU_STAT(l1d_flush) },
188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
195 { "mmu_unsync", VM_STAT(mmu_unsync) },
196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
197 { "largepages", VM_STAT(lpages) },
198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
200 { NULL }
201 };
202
203 u64 __read_mostly host_xcr0;
204
205 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
206
207 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208 {
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212 }
213
214 static void kvm_on_user_return(struct user_return_notifier *urn)
215 {
216 unsigned slot;
217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
219 struct kvm_shared_msr_values *values;
220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
237 }
238 }
239 }
240
241 static void shared_msr_update(unsigned slot, u32 msr)
242 {
243 u64 value;
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246
247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256 }
257
258 void kvm_define_shared_msr(unsigned slot, u32 msr)
259 {
260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
261 shared_msrs_global.msrs[slot] = msr;
262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
264 }
265 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267 static void kvm_shared_msr_cpu_online(void)
268 {
269 unsigned i;
270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
272 shared_msr_update(i, shared_msrs_global.msrs[i]);
273 }
274
275 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
276 {
277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
279 int err;
280
281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
282 return 0;
283 smsr->values[slot].curr = value;
284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
293 return 0;
294 }
295 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
297 static void drop_user_return_notifiers(void)
298 {
299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304 }
305
306 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307 {
308 return vcpu->arch.apic_base;
309 }
310 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
312 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313 {
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
320
321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
323 if (!msr_info->host_initiated &&
324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
332 }
333 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
335 asmlinkage __visible void kvm_spurious_fault(void)
336 {
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339 }
340 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
342 #define EXCPT_BENIGN 0
343 #define EXCPT_CONTRIBUTORY 1
344 #define EXCPT_PF 2
345
346 static int exception_class(int vector)
347 {
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361 }
362
363 #define EXCPT_FAULT 0
364 #define EXCPT_TRAP 1
365 #define EXCPT_ABORT 2
366 #define EXCPT_INTERRUPT 3
367
368 static int exception_type(int vector)
369 {
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386 }
387
388 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
391 {
392 u32 prev_nr;
393 int class1, class2;
394
395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
398 queue:
399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
438 vcpu->arch.exception.pending = true;
439 vcpu->arch.exception.injected = false;
440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448 }
449
450 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451 {
452 kvm_multiple_exception(vcpu, nr, false, 0, false);
453 }
454 EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
456 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457 {
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459 }
460 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
462 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
463 {
464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
470 }
471 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
472
473 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
474 {
475 ++vcpu->stat.pf_guest;
476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
483 }
484 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
485
486 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
487 {
488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
490 else
491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
492
493 return fault->nested_page_fault;
494 }
495
496 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497 {
498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
500 }
501 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
503 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504 {
505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
506 }
507 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
509 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510 {
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512 }
513 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
515 /*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
520 {
521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
525 }
526 EXPORT_SYMBOL_GPL(kvm_require_cpl);
527
528 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529 {
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535 }
536 EXPORT_SYMBOL_GPL(kvm_require_dr);
537
538 /*
539 * This function will be used to read from the physical memory of the currently
540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
541 * can read from guest physical or from the guest's guest physical memory.
542 */
543 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546 {
547 struct x86_exception exception;
548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
559 }
560 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
562 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
563 void *data, int offset, int len, u32 access)
564 {
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567 }
568
569 /*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
572 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
573 {
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
579
580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
588 if ((pdpte[i] & PT_PRESENT_MASK) &&
589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
602 out:
603
604 return ret;
605 }
606 EXPORT_SYMBOL_GPL(load_pdptrs);
607
608 bool pdptrs_changed(struct kvm_vcpu *vcpu)
609 {
610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
611 bool changed = true;
612 int offset;
613 gfn_t gfn;
614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
627 if (r < 0)
628 goto out;
629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
630 out:
631
632 return changed;
633 }
634 EXPORT_SYMBOL_GPL(pdptrs_changed);
635
636 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
637 {
638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
640
641 cr0 |= X86_CR0_ET;
642
643 #ifdef CONFIG_X86_64
644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
646 #endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
649
650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
652
653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657 #ifdef CONFIG_X86_64
658 if ((vcpu->arch.efer & EFER_LME)) {
659 int cs_db, cs_l;
660
661 if (!is_pae(vcpu))
662 return 1;
663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
664 if (cs_l)
665 return 1;
666 } else
667 #endif
668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
670 return 1;
671 }
672
673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
676 kvm_x86_ops->set_cr0(vcpu, cr0);
677
678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
679 kvm_clear_async_pf_completion_queue(vcpu);
680 kvm_async_pf_hash_reset(vcpu);
681 }
682
683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
685
686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
691 return 0;
692 }
693 EXPORT_SYMBOL_GPL(kvm_set_cr0);
694
695 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
696 {
697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
698 }
699 EXPORT_SYMBOL_GPL(kvm_lmsw);
700
701 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702 {
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709 }
710
711 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712 {
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718 }
719
720 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
721 {
722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
724 u64 valid_bits;
725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
729 if (!(xcr0 & XFEATURE_MASK_FP))
730 return 1;
731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
732 return 1;
733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
740 if (xcr0 & ~valid_bits)
741 return 1;
742
743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
745 return 1;
746
747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
749 return 1;
750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
751 return 1;
752 }
753 vcpu->arch.xcr0 = xcr0;
754
755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
756 kvm_update_cpuid(vcpu);
757 return 0;
758 }
759
760 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761 {
762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768 }
769 EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
771 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
772 {
773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
776
777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
779
780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
781 return 1;
782
783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
784 return 1;
785
786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
787 return 1;
788
789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
790 return 1;
791
792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
793 return 1;
794
795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
796 return 1;
797
798 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
799 return 1;
800
801 if (is_long_mode(vcpu)) {
802 if (!(cr4 & X86_CR4_PAE))
803 return 1;
804 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
805 && ((cr4 ^ old_cr4) & pdptr_bits)
806 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
807 kvm_read_cr3(vcpu)))
808 return 1;
809
810 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
811 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
812 return 1;
813
814 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
815 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
816 return 1;
817 }
818
819 if (kvm_x86_ops->set_cr4(vcpu, cr4))
820 return 1;
821
822 if (((cr4 ^ old_cr4) & pdptr_bits) ||
823 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
824 kvm_mmu_reset_context(vcpu);
825
826 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
827 kvm_update_cpuid(vcpu);
828
829 return 0;
830 }
831 EXPORT_SYMBOL_GPL(kvm_set_cr4);
832
833 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
834 {
835 #ifdef CONFIG_X86_64
836 cr3 &= ~CR3_PCID_INVD;
837 #endif
838
839 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
840 kvm_mmu_sync_roots(vcpu);
841 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
842 return 0;
843 }
844
845 if (is_long_mode(vcpu) &&
846 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
847 return 1;
848 else if (is_pae(vcpu) && is_paging(vcpu) &&
849 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
850 return 1;
851
852 vcpu->arch.cr3 = cr3;
853 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
854 kvm_mmu_new_cr3(vcpu);
855 return 0;
856 }
857 EXPORT_SYMBOL_GPL(kvm_set_cr3);
858
859 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
860 {
861 if (cr8 & CR8_RESERVED_BITS)
862 return 1;
863 if (lapic_in_kernel(vcpu))
864 kvm_lapic_set_tpr(vcpu, cr8);
865 else
866 vcpu->arch.cr8 = cr8;
867 return 0;
868 }
869 EXPORT_SYMBOL_GPL(kvm_set_cr8);
870
871 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
872 {
873 if (lapic_in_kernel(vcpu))
874 return kvm_lapic_get_cr8(vcpu);
875 else
876 return vcpu->arch.cr8;
877 }
878 EXPORT_SYMBOL_GPL(kvm_get_cr8);
879
880 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
881 {
882 int i;
883
884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
885 for (i = 0; i < KVM_NR_DB_REGS; i++)
886 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
887 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
888 }
889 }
890
891 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
892 {
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
895 }
896
897 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
898 {
899 unsigned long dr7;
900
901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 dr7 = vcpu->arch.guest_debug_dr7;
903 else
904 dr7 = vcpu->arch.dr7;
905 kvm_x86_ops->set_dr7(vcpu, dr7);
906 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
907 if (dr7 & DR7_BP_EN_MASK)
908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
909 }
910
911 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
912 {
913 u64 fixed = DR6_FIXED_1;
914
915 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
916 fixed |= DR6_RTM;
917 return fixed;
918 }
919
920 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921 {
922 switch (dr) {
923 case 0 ... 3:
924 vcpu->arch.db[dr] = val;
925 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
926 vcpu->arch.eff_db[dr] = val;
927 break;
928 case 4:
929 /* fall through */
930 case 6:
931 if (val & 0xffffffff00000000ULL)
932 return -1; /* #GP */
933 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
934 kvm_update_dr6(vcpu);
935 break;
936 case 5:
937 /* fall through */
938 default: /* 7 */
939 if (val & 0xffffffff00000000ULL)
940 return -1; /* #GP */
941 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
942 kvm_update_dr7(vcpu);
943 break;
944 }
945
946 return 0;
947 }
948
949 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
950 {
951 if (__kvm_set_dr(vcpu, dr, val)) {
952 kvm_inject_gp(vcpu, 0);
953 return 1;
954 }
955 return 0;
956 }
957 EXPORT_SYMBOL_GPL(kvm_set_dr);
958
959 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
960 {
961 switch (dr) {
962 case 0 ... 3:
963 *val = vcpu->arch.db[dr];
964 break;
965 case 4:
966 /* fall through */
967 case 6:
968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
969 *val = vcpu->arch.dr6;
970 else
971 *val = kvm_x86_ops->get_dr6(vcpu);
972 break;
973 case 5:
974 /* fall through */
975 default: /* 7 */
976 *val = vcpu->arch.dr7;
977 break;
978 }
979 return 0;
980 }
981 EXPORT_SYMBOL_GPL(kvm_get_dr);
982
983 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
984 {
985 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
986 u64 data;
987 int err;
988
989 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
990 if (err)
991 return err;
992 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
993 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
994 return err;
995 }
996 EXPORT_SYMBOL_GPL(kvm_rdpmc);
997
998 /*
999 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1000 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1001 *
1002 * This list is modified at module load time to reflect the
1003 * capabilities of the host cpu. This capabilities test skips MSRs that are
1004 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1005 * may depend on host virtualization features rather than host cpu features.
1006 */
1007
1008 static u32 msrs_to_save[] = {
1009 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1010 MSR_STAR,
1011 #ifdef CONFIG_X86_64
1012 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1013 #endif
1014 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1015 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1016 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1017 };
1018
1019 static unsigned num_msrs_to_save;
1020
1021 static u32 emulated_msrs[] = {
1022 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1023 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1024 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1025 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1026 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1027 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1028 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1029 HV_X64_MSR_RESET,
1030 HV_X64_MSR_VP_INDEX,
1031 HV_X64_MSR_VP_RUNTIME,
1032 HV_X64_MSR_SCONTROL,
1033 HV_X64_MSR_STIMER0_CONFIG,
1034 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1035 MSR_KVM_PV_EOI_EN,
1036
1037 MSR_IA32_TSC_ADJUST,
1038 MSR_IA32_TSCDEADLINE,
1039 MSR_IA32_MISC_ENABLE,
1040 MSR_IA32_MCG_STATUS,
1041 MSR_IA32_MCG_CTL,
1042 MSR_IA32_MCG_EXT_CTL,
1043 MSR_IA32_SMBASE,
1044 MSR_PLATFORM_INFO,
1045 MSR_MISC_FEATURES_ENABLES,
1046 MSR_AMD64_VIRT_SPEC_CTRL,
1047 };
1048
1049 static unsigned num_emulated_msrs;
1050
1051 /*
1052 * List of msr numbers which are used to expose MSR-based features that
1053 * can be used by a hypervisor to validate requested CPU features.
1054 */
1055 static u32 msr_based_features[] = {
1056 MSR_IA32_ARCH_CAPABILITIES,
1057 };
1058
1059 static unsigned int num_msr_based_features;
1060
1061 u64 kvm_get_arch_capabilities(void)
1062 {
1063 u64 data;
1064
1065 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1066
1067 /*
1068 * If we're doing cache flushes (either "always" or "cond")
1069 * we will do one whenever the guest does a vmlaunch/vmresume.
1070 * If an outer hypervisor is doing the cache flush for us
1071 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1072 * capability to the guest too, and if EPT is disabled we're not
1073 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1074 * require a nested hypervisor to do a flush of its own.
1075 */
1076 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1077 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1078
1079 return data;
1080 }
1081 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1082
1083 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1084 {
1085 switch (msr->index) {
1086 case MSR_IA32_ARCH_CAPABILITIES:
1087 msr->data = kvm_get_arch_capabilities();
1088 break;
1089 default:
1090 if (kvm_x86_ops->get_msr_feature(msr))
1091 return 1;
1092 }
1093 return 0;
1094 }
1095
1096 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1097 {
1098 struct kvm_msr_entry msr;
1099 int r;
1100
1101 msr.index = index;
1102 r = kvm_get_msr_feature(&msr);
1103 if (r)
1104 return r;
1105
1106 *data = msr.data;
1107
1108 return 0;
1109 }
1110
1111 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1112 {
1113 if (efer & efer_reserved_bits)
1114 return false;
1115
1116 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1117 return false;
1118
1119 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1120 return false;
1121
1122 return true;
1123 }
1124 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1125
1126 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1127 {
1128 u64 old_efer = vcpu->arch.efer;
1129
1130 if (!kvm_valid_efer(vcpu, efer))
1131 return 1;
1132
1133 if (is_paging(vcpu)
1134 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1135 return 1;
1136
1137 efer &= ~EFER_LMA;
1138 efer |= vcpu->arch.efer & EFER_LMA;
1139
1140 kvm_x86_ops->set_efer(vcpu, efer);
1141
1142 /* Update reserved bits */
1143 if ((efer ^ old_efer) & EFER_NX)
1144 kvm_mmu_reset_context(vcpu);
1145
1146 return 0;
1147 }
1148
1149 void kvm_enable_efer_bits(u64 mask)
1150 {
1151 efer_reserved_bits &= ~mask;
1152 }
1153 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1154
1155 /*
1156 * Writes msr value into into the appropriate "register".
1157 * Returns 0 on success, non-0 otherwise.
1158 * Assumes vcpu_load() was already called.
1159 */
1160 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1161 {
1162 switch (msr->index) {
1163 case MSR_FS_BASE:
1164 case MSR_GS_BASE:
1165 case MSR_KERNEL_GS_BASE:
1166 case MSR_CSTAR:
1167 case MSR_LSTAR:
1168 if (is_noncanonical_address(msr->data, vcpu))
1169 return 1;
1170 break;
1171 case MSR_IA32_SYSENTER_EIP:
1172 case MSR_IA32_SYSENTER_ESP:
1173 /*
1174 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1175 * non-canonical address is written on Intel but not on
1176 * AMD (which ignores the top 32-bits, because it does
1177 * not implement 64-bit SYSENTER).
1178 *
1179 * 64-bit code should hence be able to write a non-canonical
1180 * value on AMD. Making the address canonical ensures that
1181 * vmentry does not fail on Intel after writing a non-canonical
1182 * value, and that something deterministic happens if the guest
1183 * invokes 64-bit SYSENTER.
1184 */
1185 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1186 }
1187 return kvm_x86_ops->set_msr(vcpu, msr);
1188 }
1189 EXPORT_SYMBOL_GPL(kvm_set_msr);
1190
1191 /*
1192 * Adapt set_msr() to msr_io()'s calling convention
1193 */
1194 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1195 {
1196 struct msr_data msr;
1197 int r;
1198
1199 msr.index = index;
1200 msr.host_initiated = true;
1201 r = kvm_get_msr(vcpu, &msr);
1202 if (r)
1203 return r;
1204
1205 *data = msr.data;
1206 return 0;
1207 }
1208
1209 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1210 {
1211 struct msr_data msr;
1212
1213 msr.data = *data;
1214 msr.index = index;
1215 msr.host_initiated = true;
1216 return kvm_set_msr(vcpu, &msr);
1217 }
1218
1219 #ifdef CONFIG_X86_64
1220 struct pvclock_gtod_data {
1221 seqcount_t seq;
1222
1223 struct { /* extract of a clocksource struct */
1224 int vclock_mode;
1225 u64 cycle_last;
1226 u64 mask;
1227 u32 mult;
1228 u32 shift;
1229 } clock;
1230
1231 u64 boot_ns;
1232 u64 nsec_base;
1233 u64 wall_time_sec;
1234 };
1235
1236 static struct pvclock_gtod_data pvclock_gtod_data;
1237
1238 static void update_pvclock_gtod(struct timekeeper *tk)
1239 {
1240 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1241 u64 boot_ns;
1242
1243 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1244
1245 write_seqcount_begin(&vdata->seq);
1246
1247 /* copy pvclock gtod data */
1248 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1249 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1250 vdata->clock.mask = tk->tkr_mono.mask;
1251 vdata->clock.mult = tk->tkr_mono.mult;
1252 vdata->clock.shift = tk->tkr_mono.shift;
1253
1254 vdata->boot_ns = boot_ns;
1255 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1256
1257 vdata->wall_time_sec = tk->xtime_sec;
1258
1259 write_seqcount_end(&vdata->seq);
1260 }
1261 #endif
1262
1263 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1264 {
1265 /*
1266 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1267 * vcpu_enter_guest. This function is only called from
1268 * the physical CPU that is running vcpu.
1269 */
1270 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1271 }
1272
1273 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1274 {
1275 int version;
1276 int r;
1277 struct pvclock_wall_clock wc;
1278 struct timespec64 boot;
1279
1280 if (!wall_clock)
1281 return;
1282
1283 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1284 if (r)
1285 return;
1286
1287 if (version & 1)
1288 ++version; /* first time write, random junk */
1289
1290 ++version;
1291
1292 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1293 return;
1294
1295 /*
1296 * The guest calculates current wall clock time by adding
1297 * system time (updated by kvm_guest_time_update below) to the
1298 * wall clock specified here. guest system time equals host
1299 * system time for us, thus we must fill in host boot time here.
1300 */
1301 getboottime64(&boot);
1302
1303 if (kvm->arch.kvmclock_offset) {
1304 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1305 boot = timespec64_sub(boot, ts);
1306 }
1307 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1308 wc.nsec = boot.tv_nsec;
1309 wc.version = version;
1310
1311 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1312
1313 version++;
1314 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1315 }
1316
1317 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1318 {
1319 do_shl32_div32(dividend, divisor);
1320 return dividend;
1321 }
1322
1323 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1324 s8 *pshift, u32 *pmultiplier)
1325 {
1326 uint64_t scaled64;
1327 int32_t shift = 0;
1328 uint64_t tps64;
1329 uint32_t tps32;
1330
1331 tps64 = base_hz;
1332 scaled64 = scaled_hz;
1333 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1334 tps64 >>= 1;
1335 shift--;
1336 }
1337
1338 tps32 = (uint32_t)tps64;
1339 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1340 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1341 scaled64 >>= 1;
1342 else
1343 tps32 <<= 1;
1344 shift++;
1345 }
1346
1347 *pshift = shift;
1348 *pmultiplier = div_frac(scaled64, tps32);
1349
1350 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1351 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1352 }
1353
1354 #ifdef CONFIG_X86_64
1355 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1356 #endif
1357
1358 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1359 static unsigned long max_tsc_khz;
1360
1361 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1362 {
1363 u64 v = (u64)khz * (1000000 + ppm);
1364 do_div(v, 1000000);
1365 return v;
1366 }
1367
1368 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1369 {
1370 u64 ratio;
1371
1372 /* Guest TSC same frequency as host TSC? */
1373 if (!scale) {
1374 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1375 return 0;
1376 }
1377
1378 /* TSC scaling supported? */
1379 if (!kvm_has_tsc_control) {
1380 if (user_tsc_khz > tsc_khz) {
1381 vcpu->arch.tsc_catchup = 1;
1382 vcpu->arch.tsc_always_catchup = 1;
1383 return 0;
1384 } else {
1385 WARN(1, "user requested TSC rate below hardware speed\n");
1386 return -1;
1387 }
1388 }
1389
1390 /* TSC scaling required - calculate ratio */
1391 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1392 user_tsc_khz, tsc_khz);
1393
1394 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1395 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1396 user_tsc_khz);
1397 return -1;
1398 }
1399
1400 vcpu->arch.tsc_scaling_ratio = ratio;
1401 return 0;
1402 }
1403
1404 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1405 {
1406 u32 thresh_lo, thresh_hi;
1407 int use_scaling = 0;
1408
1409 /* tsc_khz can be zero if TSC calibration fails */
1410 if (user_tsc_khz == 0) {
1411 /* set tsc_scaling_ratio to a safe value */
1412 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1413 return -1;
1414 }
1415
1416 /* Compute a scale to convert nanoseconds in TSC cycles */
1417 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1418 &vcpu->arch.virtual_tsc_shift,
1419 &vcpu->arch.virtual_tsc_mult);
1420 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1421
1422 /*
1423 * Compute the variation in TSC rate which is acceptable
1424 * within the range of tolerance and decide if the
1425 * rate being applied is within that bounds of the hardware
1426 * rate. If so, no scaling or compensation need be done.
1427 */
1428 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1429 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1430 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1431 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1432 use_scaling = 1;
1433 }
1434 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1435 }
1436
1437 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1438 {
1439 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1440 vcpu->arch.virtual_tsc_mult,
1441 vcpu->arch.virtual_tsc_shift);
1442 tsc += vcpu->arch.this_tsc_write;
1443 return tsc;
1444 }
1445
1446 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1447 {
1448 #ifdef CONFIG_X86_64
1449 bool vcpus_matched;
1450 struct kvm_arch *ka = &vcpu->kvm->arch;
1451 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1452
1453 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1454 atomic_read(&vcpu->kvm->online_vcpus));
1455
1456 /*
1457 * Once the masterclock is enabled, always perform request in
1458 * order to update it.
1459 *
1460 * In order to enable masterclock, the host clocksource must be TSC
1461 * and the vcpus need to have matched TSCs. When that happens,
1462 * perform request to enable masterclock.
1463 */
1464 if (ka->use_master_clock ||
1465 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1466 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1467
1468 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1469 atomic_read(&vcpu->kvm->online_vcpus),
1470 ka->use_master_clock, gtod->clock.vclock_mode);
1471 #endif
1472 }
1473
1474 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1475 {
1476 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1477 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1478 }
1479
1480 /*
1481 * Multiply tsc by a fixed point number represented by ratio.
1482 *
1483 * The most significant 64-N bits (mult) of ratio represent the
1484 * integral part of the fixed point number; the remaining N bits
1485 * (frac) represent the fractional part, ie. ratio represents a fixed
1486 * point number (mult + frac * 2^(-N)).
1487 *
1488 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1489 */
1490 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1491 {
1492 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1493 }
1494
1495 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1496 {
1497 u64 _tsc = tsc;
1498 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1499
1500 if (ratio != kvm_default_tsc_scaling_ratio)
1501 _tsc = __scale_tsc(ratio, tsc);
1502
1503 return _tsc;
1504 }
1505 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1506
1507 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1508 {
1509 u64 tsc;
1510
1511 tsc = kvm_scale_tsc(vcpu, rdtsc());
1512
1513 return target_tsc - tsc;
1514 }
1515
1516 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1517 {
1518 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1519
1520 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1521 }
1522 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1523
1524 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1525 {
1526 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1527 vcpu->arch.tsc_offset = offset;
1528 }
1529
1530 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1531 {
1532 struct kvm *kvm = vcpu->kvm;
1533 u64 offset, ns, elapsed;
1534 unsigned long flags;
1535 bool matched;
1536 bool already_matched;
1537 u64 data = msr->data;
1538 bool synchronizing = false;
1539
1540 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1541 offset = kvm_compute_tsc_offset(vcpu, data);
1542 ns = ktime_get_boot_ns();
1543 elapsed = ns - kvm->arch.last_tsc_nsec;
1544
1545 if (vcpu->arch.virtual_tsc_khz) {
1546 if (data == 0 && msr->host_initiated) {
1547 /*
1548 * detection of vcpu initialization -- need to sync
1549 * with other vCPUs. This particularly helps to keep
1550 * kvm_clock stable after CPU hotplug
1551 */
1552 synchronizing = true;
1553 } else {
1554 u64 tsc_exp = kvm->arch.last_tsc_write +
1555 nsec_to_cycles(vcpu, elapsed);
1556 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1557 /*
1558 * Special case: TSC write with a small delta (1 second)
1559 * of virtual cycle time against real time is
1560 * interpreted as an attempt to synchronize the CPU.
1561 */
1562 synchronizing = data < tsc_exp + tsc_hz &&
1563 data + tsc_hz > tsc_exp;
1564 }
1565 }
1566
1567 /*
1568 * For a reliable TSC, we can match TSC offsets, and for an unstable
1569 * TSC, we add elapsed time in this computation. We could let the
1570 * compensation code attempt to catch up if we fall behind, but
1571 * it's better to try to match offsets from the beginning.
1572 */
1573 if (synchronizing &&
1574 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1575 if (!check_tsc_unstable()) {
1576 offset = kvm->arch.cur_tsc_offset;
1577 pr_debug("kvm: matched tsc offset for %llu\n", data);
1578 } else {
1579 u64 delta = nsec_to_cycles(vcpu, elapsed);
1580 data += delta;
1581 offset = kvm_compute_tsc_offset(vcpu, data);
1582 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1583 }
1584 matched = true;
1585 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1586 } else {
1587 /*
1588 * We split periods of matched TSC writes into generations.
1589 * For each generation, we track the original measured
1590 * nanosecond time, offset, and write, so if TSCs are in
1591 * sync, we can match exact offset, and if not, we can match
1592 * exact software computation in compute_guest_tsc()
1593 *
1594 * These values are tracked in kvm->arch.cur_xxx variables.
1595 */
1596 kvm->arch.cur_tsc_generation++;
1597 kvm->arch.cur_tsc_nsec = ns;
1598 kvm->arch.cur_tsc_write = data;
1599 kvm->arch.cur_tsc_offset = offset;
1600 matched = false;
1601 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1602 kvm->arch.cur_tsc_generation, data);
1603 }
1604
1605 /*
1606 * We also track th most recent recorded KHZ, write and time to
1607 * allow the matching interval to be extended at each write.
1608 */
1609 kvm->arch.last_tsc_nsec = ns;
1610 kvm->arch.last_tsc_write = data;
1611 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1612
1613 vcpu->arch.last_guest_tsc = data;
1614
1615 /* Keep track of which generation this VCPU has synchronized to */
1616 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1617 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1618 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1619
1620 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1621 update_ia32_tsc_adjust_msr(vcpu, offset);
1622
1623 kvm_vcpu_write_tsc_offset(vcpu, offset);
1624 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1625
1626 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1627 if (!matched) {
1628 kvm->arch.nr_vcpus_matched_tsc = 0;
1629 } else if (!already_matched) {
1630 kvm->arch.nr_vcpus_matched_tsc++;
1631 }
1632
1633 kvm_track_tsc_matching(vcpu);
1634 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1635 }
1636
1637 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1638
1639 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1640 s64 adjustment)
1641 {
1642 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1643 }
1644
1645 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1646 {
1647 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1648 WARN_ON(adjustment < 0);
1649 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1650 adjust_tsc_offset_guest(vcpu, adjustment);
1651 }
1652
1653 #ifdef CONFIG_X86_64
1654
1655 static u64 read_tsc(void)
1656 {
1657 u64 ret = (u64)rdtsc_ordered();
1658 u64 last = pvclock_gtod_data.clock.cycle_last;
1659
1660 if (likely(ret >= last))
1661 return ret;
1662
1663 /*
1664 * GCC likes to generate cmov here, but this branch is extremely
1665 * predictable (it's just a function of time and the likely is
1666 * very likely) and there's a data dependence, so force GCC
1667 * to generate a branch instead. I don't barrier() because
1668 * we don't actually need a barrier, and if this function
1669 * ever gets inlined it will generate worse code.
1670 */
1671 asm volatile ("");
1672 return last;
1673 }
1674
1675 static inline u64 vgettsc(u64 *cycle_now)
1676 {
1677 long v;
1678 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1679
1680 *cycle_now = read_tsc();
1681
1682 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1683 return v * gtod->clock.mult;
1684 }
1685
1686 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1687 {
1688 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1689 unsigned long seq;
1690 int mode;
1691 u64 ns;
1692
1693 do {
1694 seq = read_seqcount_begin(&gtod->seq);
1695 mode = gtod->clock.vclock_mode;
1696 ns = gtod->nsec_base;
1697 ns += vgettsc(cycle_now);
1698 ns >>= gtod->clock.shift;
1699 ns += gtod->boot_ns;
1700 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1701 *t = ns;
1702
1703 return mode;
1704 }
1705
1706 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1707 {
1708 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1709 unsigned long seq;
1710 int mode;
1711 u64 ns;
1712
1713 do {
1714 seq = read_seqcount_begin(&gtod->seq);
1715 mode = gtod->clock.vclock_mode;
1716 ts->tv_sec = gtod->wall_time_sec;
1717 ns = gtod->nsec_base;
1718 ns += vgettsc(cycle_now);
1719 ns >>= gtod->clock.shift;
1720 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1721
1722 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1723 ts->tv_nsec = ns;
1724
1725 return mode;
1726 }
1727
1728 /* returns true if host is using tsc clocksource */
1729 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1730 {
1731 /* checked again under seqlock below */
1732 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1733 return false;
1734
1735 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1736 }
1737
1738 /* returns true if host is using tsc clocksource */
1739 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1740 u64 *cycle_now)
1741 {
1742 /* checked again under seqlock below */
1743 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1744 return false;
1745
1746 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1747 }
1748 #endif
1749
1750 /*
1751 *
1752 * Assuming a stable TSC across physical CPUS, and a stable TSC
1753 * across virtual CPUs, the following condition is possible.
1754 * Each numbered line represents an event visible to both
1755 * CPUs at the next numbered event.
1756 *
1757 * "timespecX" represents host monotonic time. "tscX" represents
1758 * RDTSC value.
1759 *
1760 * VCPU0 on CPU0 | VCPU1 on CPU1
1761 *
1762 * 1. read timespec0,tsc0
1763 * 2. | timespec1 = timespec0 + N
1764 * | tsc1 = tsc0 + M
1765 * 3. transition to guest | transition to guest
1766 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1767 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1768 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1769 *
1770 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1771 *
1772 * - ret0 < ret1
1773 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1774 * ...
1775 * - 0 < N - M => M < N
1776 *
1777 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1778 * always the case (the difference between two distinct xtime instances
1779 * might be smaller then the difference between corresponding TSC reads,
1780 * when updating guest vcpus pvclock areas).
1781 *
1782 * To avoid that problem, do not allow visibility of distinct
1783 * system_timestamp/tsc_timestamp values simultaneously: use a master
1784 * copy of host monotonic time values. Update that master copy
1785 * in lockstep.
1786 *
1787 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1788 *
1789 */
1790
1791 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1792 {
1793 #ifdef CONFIG_X86_64
1794 struct kvm_arch *ka = &kvm->arch;
1795 int vclock_mode;
1796 bool host_tsc_clocksource, vcpus_matched;
1797
1798 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1799 atomic_read(&kvm->online_vcpus));
1800
1801 /*
1802 * If the host uses TSC clock, then passthrough TSC as stable
1803 * to the guest.
1804 */
1805 host_tsc_clocksource = kvm_get_time_and_clockread(
1806 &ka->master_kernel_ns,
1807 &ka->master_cycle_now);
1808
1809 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1810 && !ka->backwards_tsc_observed
1811 && !ka->boot_vcpu_runs_old_kvmclock;
1812
1813 if (ka->use_master_clock)
1814 atomic_set(&kvm_guest_has_master_clock, 1);
1815
1816 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1817 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1818 vcpus_matched);
1819 #endif
1820 }
1821
1822 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1823 {
1824 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1825 }
1826
1827 static void kvm_gen_update_masterclock(struct kvm *kvm)
1828 {
1829 #ifdef CONFIG_X86_64
1830 int i;
1831 struct kvm_vcpu *vcpu;
1832 struct kvm_arch *ka = &kvm->arch;
1833
1834 spin_lock(&ka->pvclock_gtod_sync_lock);
1835 kvm_make_mclock_inprogress_request(kvm);
1836 /* no guest entries from this point */
1837 pvclock_update_vm_gtod_copy(kvm);
1838
1839 kvm_for_each_vcpu(i, vcpu, kvm)
1840 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1841
1842 /* guest entries allowed */
1843 kvm_for_each_vcpu(i, vcpu, kvm)
1844 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1845
1846 spin_unlock(&ka->pvclock_gtod_sync_lock);
1847 #endif
1848 }
1849
1850 u64 get_kvmclock_ns(struct kvm *kvm)
1851 {
1852 struct kvm_arch *ka = &kvm->arch;
1853 struct pvclock_vcpu_time_info hv_clock;
1854 u64 ret;
1855
1856 spin_lock(&ka->pvclock_gtod_sync_lock);
1857 if (!ka->use_master_clock) {
1858 spin_unlock(&ka->pvclock_gtod_sync_lock);
1859 return ktime_get_boot_ns() + ka->kvmclock_offset;
1860 }
1861
1862 hv_clock.tsc_timestamp = ka->master_cycle_now;
1863 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1864 spin_unlock(&ka->pvclock_gtod_sync_lock);
1865
1866 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1867 get_cpu();
1868
1869 if (__this_cpu_read(cpu_tsc_khz)) {
1870 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1871 &hv_clock.tsc_shift,
1872 &hv_clock.tsc_to_system_mul);
1873 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1874 } else
1875 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1876
1877 put_cpu();
1878
1879 return ret;
1880 }
1881
1882 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1883 {
1884 struct kvm_vcpu_arch *vcpu = &v->arch;
1885 struct pvclock_vcpu_time_info guest_hv_clock;
1886
1887 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1888 &guest_hv_clock, sizeof(guest_hv_clock))))
1889 return;
1890
1891 /* This VCPU is paused, but it's legal for a guest to read another
1892 * VCPU's kvmclock, so we really have to follow the specification where
1893 * it says that version is odd if data is being modified, and even after
1894 * it is consistent.
1895 *
1896 * Version field updates must be kept separate. This is because
1897 * kvm_write_guest_cached might use a "rep movs" instruction, and
1898 * writes within a string instruction are weakly ordered. So there
1899 * are three writes overall.
1900 *
1901 * As a small optimization, only write the version field in the first
1902 * and third write. The vcpu->pv_time cache is still valid, because the
1903 * version field is the first in the struct.
1904 */
1905 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1906
1907 if (guest_hv_clock.version & 1)
1908 ++guest_hv_clock.version; /* first time write, random junk */
1909
1910 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1911 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1912 &vcpu->hv_clock,
1913 sizeof(vcpu->hv_clock.version));
1914
1915 smp_wmb();
1916
1917 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1918 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1919
1920 if (vcpu->pvclock_set_guest_stopped_request) {
1921 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1922 vcpu->pvclock_set_guest_stopped_request = false;
1923 }
1924
1925 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1926
1927 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1928 &vcpu->hv_clock,
1929 sizeof(vcpu->hv_clock));
1930
1931 smp_wmb();
1932
1933 vcpu->hv_clock.version++;
1934 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1935 &vcpu->hv_clock,
1936 sizeof(vcpu->hv_clock.version));
1937 }
1938
1939 static int kvm_guest_time_update(struct kvm_vcpu *v)
1940 {
1941 unsigned long flags, tgt_tsc_khz;
1942 struct kvm_vcpu_arch *vcpu = &v->arch;
1943 struct kvm_arch *ka = &v->kvm->arch;
1944 s64 kernel_ns;
1945 u64 tsc_timestamp, host_tsc;
1946 u8 pvclock_flags;
1947 bool use_master_clock;
1948
1949 kernel_ns = 0;
1950 host_tsc = 0;
1951
1952 /*
1953 * If the host uses TSC clock, then passthrough TSC as stable
1954 * to the guest.
1955 */
1956 spin_lock(&ka->pvclock_gtod_sync_lock);
1957 use_master_clock = ka->use_master_clock;
1958 if (use_master_clock) {
1959 host_tsc = ka->master_cycle_now;
1960 kernel_ns = ka->master_kernel_ns;
1961 }
1962 spin_unlock(&ka->pvclock_gtod_sync_lock);
1963
1964 /* Keep irq disabled to prevent changes to the clock */
1965 local_irq_save(flags);
1966 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1967 if (unlikely(tgt_tsc_khz == 0)) {
1968 local_irq_restore(flags);
1969 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1970 return 1;
1971 }
1972 if (!use_master_clock) {
1973 host_tsc = rdtsc();
1974 kernel_ns = ktime_get_boot_ns();
1975 }
1976
1977 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1978
1979 /*
1980 * We may have to catch up the TSC to match elapsed wall clock
1981 * time for two reasons, even if kvmclock is used.
1982 * 1) CPU could have been running below the maximum TSC rate
1983 * 2) Broken TSC compensation resets the base at each VCPU
1984 * entry to avoid unknown leaps of TSC even when running
1985 * again on the same CPU. This may cause apparent elapsed
1986 * time to disappear, and the guest to stand still or run
1987 * very slowly.
1988 */
1989 if (vcpu->tsc_catchup) {
1990 u64 tsc = compute_guest_tsc(v, kernel_ns);
1991 if (tsc > tsc_timestamp) {
1992 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1993 tsc_timestamp = tsc;
1994 }
1995 }
1996
1997 local_irq_restore(flags);
1998
1999 /* With all the info we got, fill in the values */
2000
2001 if (kvm_has_tsc_control)
2002 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2003
2004 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2005 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2006 &vcpu->hv_clock.tsc_shift,
2007 &vcpu->hv_clock.tsc_to_system_mul);
2008 vcpu->hw_tsc_khz = tgt_tsc_khz;
2009 }
2010
2011 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2012 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2013 vcpu->last_guest_tsc = tsc_timestamp;
2014
2015 /* If the host uses TSC clocksource, then it is stable */
2016 pvclock_flags = 0;
2017 if (use_master_clock)
2018 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2019
2020 vcpu->hv_clock.flags = pvclock_flags;
2021
2022 if (vcpu->pv_time_enabled)
2023 kvm_setup_pvclock_page(v);
2024 if (v == kvm_get_vcpu(v->kvm, 0))
2025 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2026 return 0;
2027 }
2028
2029 /*
2030 * kvmclock updates which are isolated to a given vcpu, such as
2031 * vcpu->cpu migration, should not allow system_timestamp from
2032 * the rest of the vcpus to remain static. Otherwise ntp frequency
2033 * correction applies to one vcpu's system_timestamp but not
2034 * the others.
2035 *
2036 * So in those cases, request a kvmclock update for all vcpus.
2037 * We need to rate-limit these requests though, as they can
2038 * considerably slow guests that have a large number of vcpus.
2039 * The time for a remote vcpu to update its kvmclock is bound
2040 * by the delay we use to rate-limit the updates.
2041 */
2042
2043 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2044
2045 static void kvmclock_update_fn(struct work_struct *work)
2046 {
2047 int i;
2048 struct delayed_work *dwork = to_delayed_work(work);
2049 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2050 kvmclock_update_work);
2051 struct kvm *kvm = container_of(ka, struct kvm, arch);
2052 struct kvm_vcpu *vcpu;
2053
2054 kvm_for_each_vcpu(i, vcpu, kvm) {
2055 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2056 kvm_vcpu_kick(vcpu);
2057 }
2058 }
2059
2060 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2061 {
2062 struct kvm *kvm = v->kvm;
2063
2064 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2065 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2066 KVMCLOCK_UPDATE_DELAY);
2067 }
2068
2069 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2070
2071 static void kvmclock_sync_fn(struct work_struct *work)
2072 {
2073 struct delayed_work *dwork = to_delayed_work(work);
2074 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2075 kvmclock_sync_work);
2076 struct kvm *kvm = container_of(ka, struct kvm, arch);
2077
2078 if (!kvmclock_periodic_sync)
2079 return;
2080
2081 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2082 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2083 KVMCLOCK_SYNC_PERIOD);
2084 }
2085
2086 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2087 {
2088 u64 mcg_cap = vcpu->arch.mcg_cap;
2089 unsigned bank_num = mcg_cap & 0xff;
2090 u32 msr = msr_info->index;
2091 u64 data = msr_info->data;
2092
2093 switch (msr) {
2094 case MSR_IA32_MCG_STATUS:
2095 vcpu->arch.mcg_status = data;
2096 break;
2097 case MSR_IA32_MCG_CTL:
2098 if (!(mcg_cap & MCG_CTL_P))
2099 return 1;
2100 if (data != 0 && data != ~(u64)0)
2101 return -1;
2102 vcpu->arch.mcg_ctl = data;
2103 break;
2104 default:
2105 if (msr >= MSR_IA32_MC0_CTL &&
2106 msr < MSR_IA32_MCx_CTL(bank_num)) {
2107 u32 offset = msr - MSR_IA32_MC0_CTL;
2108 /* only 0 or all 1s can be written to IA32_MCi_CTL
2109 * some Linux kernels though clear bit 10 in bank 4 to
2110 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2111 * this to avoid an uncatched #GP in the guest
2112 */
2113 if ((offset & 0x3) == 0 &&
2114 data != 0 && (data | (1 << 10)) != ~(u64)0)
2115 return -1;
2116 if (!msr_info->host_initiated &&
2117 (offset & 0x3) == 1 && data != 0)
2118 return -1;
2119 vcpu->arch.mce_banks[offset] = data;
2120 break;
2121 }
2122 return 1;
2123 }
2124 return 0;
2125 }
2126
2127 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2128 {
2129 struct kvm *kvm = vcpu->kvm;
2130 int lm = is_long_mode(vcpu);
2131 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2132 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2133 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2134 : kvm->arch.xen_hvm_config.blob_size_32;
2135 u32 page_num = data & ~PAGE_MASK;
2136 u64 page_addr = data & PAGE_MASK;
2137 u8 *page;
2138 int r;
2139
2140 r = -E2BIG;
2141 if (page_num >= blob_size)
2142 goto out;
2143 r = -ENOMEM;
2144 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2145 if (IS_ERR(page)) {
2146 r = PTR_ERR(page);
2147 goto out;
2148 }
2149 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2150 goto out_free;
2151 r = 0;
2152 out_free:
2153 kfree(page);
2154 out:
2155 return r;
2156 }
2157
2158 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2159 {
2160 gpa_t gpa = data & ~0x3f;
2161
2162 /* Bits 3:5 are reserved, Should be zero */
2163 if (data & 0x38)
2164 return 1;
2165
2166 vcpu->arch.apf.msr_val = data;
2167
2168 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2169 kvm_clear_async_pf_completion_queue(vcpu);
2170 kvm_async_pf_hash_reset(vcpu);
2171 return 0;
2172 }
2173
2174 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2175 sizeof(u32)))
2176 return 1;
2177
2178 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2179 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2180 kvm_async_pf_wakeup_all(vcpu);
2181 return 0;
2182 }
2183
2184 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2185 {
2186 vcpu->arch.pv_time_enabled = false;
2187 }
2188
2189 static void record_steal_time(struct kvm_vcpu *vcpu)
2190 {
2191 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2192 return;
2193
2194 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2195 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2196 return;
2197
2198 vcpu->arch.st.steal.preempted = 0;
2199
2200 if (vcpu->arch.st.steal.version & 1)
2201 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2202
2203 vcpu->arch.st.steal.version += 1;
2204
2205 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2206 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2207
2208 smp_wmb();
2209
2210 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2211 vcpu->arch.st.last_steal;
2212 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2213
2214 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2215 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2216
2217 smp_wmb();
2218
2219 vcpu->arch.st.steal.version += 1;
2220
2221 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2222 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2223 }
2224
2225 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2226 {
2227 bool pr = false;
2228 u32 msr = msr_info->index;
2229 u64 data = msr_info->data;
2230
2231 switch (msr) {
2232 case MSR_AMD64_NB_CFG:
2233 case MSR_IA32_UCODE_REV:
2234 case MSR_IA32_UCODE_WRITE:
2235 case MSR_VM_HSAVE_PA:
2236 case MSR_AMD64_PATCH_LOADER:
2237 case MSR_AMD64_BU_CFG2:
2238 case MSR_AMD64_DC_CFG:
2239 break;
2240
2241 case MSR_EFER:
2242 return set_efer(vcpu, data);
2243 case MSR_K7_HWCR:
2244 data &= ~(u64)0x40; /* ignore flush filter disable */
2245 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2246 data &= ~(u64)0x8; /* ignore TLB cache disable */
2247 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2248 if (data != 0) {
2249 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2250 data);
2251 return 1;
2252 }
2253 break;
2254 case MSR_FAM10H_MMIO_CONF_BASE:
2255 if (data != 0) {
2256 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2257 "0x%llx\n", data);
2258 return 1;
2259 }
2260 break;
2261 case MSR_IA32_DEBUGCTLMSR:
2262 if (!data) {
2263 /* We support the non-activated case already */
2264 break;
2265 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2266 /* Values other than LBR and BTF are vendor-specific,
2267 thus reserved and should throw a #GP */
2268 return 1;
2269 }
2270 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2271 __func__, data);
2272 break;
2273 case 0x200 ... 0x2ff:
2274 return kvm_mtrr_set_msr(vcpu, msr, data);
2275 case MSR_IA32_APICBASE:
2276 return kvm_set_apic_base(vcpu, msr_info);
2277 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2278 return kvm_x2apic_msr_write(vcpu, msr, data);
2279 case MSR_IA32_TSCDEADLINE:
2280 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2281 break;
2282 case MSR_IA32_TSC_ADJUST:
2283 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2284 if (!msr_info->host_initiated) {
2285 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2286 adjust_tsc_offset_guest(vcpu, adj);
2287 }
2288 vcpu->arch.ia32_tsc_adjust_msr = data;
2289 }
2290 break;
2291 case MSR_IA32_MISC_ENABLE:
2292 vcpu->arch.ia32_misc_enable_msr = data;
2293 break;
2294 case MSR_IA32_SMBASE:
2295 if (!msr_info->host_initiated)
2296 return 1;
2297 vcpu->arch.smbase = data;
2298 break;
2299 case MSR_IA32_TSC:
2300 kvm_write_tsc(vcpu, msr_info);
2301 break;
2302 case MSR_KVM_WALL_CLOCK_NEW:
2303 case MSR_KVM_WALL_CLOCK:
2304 vcpu->kvm->arch.wall_clock = data;
2305 kvm_write_wall_clock(vcpu->kvm, data);
2306 break;
2307 case MSR_KVM_SYSTEM_TIME_NEW:
2308 case MSR_KVM_SYSTEM_TIME: {
2309 struct kvm_arch *ka = &vcpu->kvm->arch;
2310
2311 kvmclock_reset(vcpu);
2312
2313 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2314 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2315
2316 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2317 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2318
2319 ka->boot_vcpu_runs_old_kvmclock = tmp;
2320 }
2321
2322 vcpu->arch.time = data;
2323 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2324
2325 /* we verify if the enable bit is set... */
2326 if (!(data & 1))
2327 break;
2328
2329 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2330 &vcpu->arch.pv_time, data & ~1ULL,
2331 sizeof(struct pvclock_vcpu_time_info)))
2332 vcpu->arch.pv_time_enabled = false;
2333 else
2334 vcpu->arch.pv_time_enabled = true;
2335
2336 break;
2337 }
2338 case MSR_KVM_ASYNC_PF_EN:
2339 if (kvm_pv_enable_async_pf(vcpu, data))
2340 return 1;
2341 break;
2342 case MSR_KVM_STEAL_TIME:
2343
2344 if (unlikely(!sched_info_on()))
2345 return 1;
2346
2347 if (data & KVM_STEAL_RESERVED_MASK)
2348 return 1;
2349
2350 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2351 data & KVM_STEAL_VALID_BITS,
2352 sizeof(struct kvm_steal_time)))
2353 return 1;
2354
2355 vcpu->arch.st.msr_val = data;
2356
2357 if (!(data & KVM_MSR_ENABLED))
2358 break;
2359
2360 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2361
2362 break;
2363 case MSR_KVM_PV_EOI_EN:
2364 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2365 return 1;
2366 break;
2367
2368 case MSR_IA32_MCG_CTL:
2369 case MSR_IA32_MCG_STATUS:
2370 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2371 return set_msr_mce(vcpu, msr_info);
2372
2373 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2374 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2375 pr = true; /* fall through */
2376 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2377 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2378 if (kvm_pmu_is_valid_msr(vcpu, msr))
2379 return kvm_pmu_set_msr(vcpu, msr_info);
2380
2381 if (pr || data != 0)
2382 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2383 "0x%x data 0x%llx\n", msr, data);
2384 break;
2385 case MSR_K7_CLK_CTL:
2386 /*
2387 * Ignore all writes to this no longer documented MSR.
2388 * Writes are only relevant for old K7 processors,
2389 * all pre-dating SVM, but a recommended workaround from
2390 * AMD for these chips. It is possible to specify the
2391 * affected processor models on the command line, hence
2392 * the need to ignore the workaround.
2393 */
2394 break;
2395 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2396 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2397 case HV_X64_MSR_CRASH_CTL:
2398 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2399 return kvm_hv_set_msr_common(vcpu, msr, data,
2400 msr_info->host_initiated);
2401 case MSR_IA32_BBL_CR_CTL3:
2402 /* Drop writes to this legacy MSR -- see rdmsr
2403 * counterpart for further detail.
2404 */
2405 if (report_ignored_msrs)
2406 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2407 msr, data);
2408 break;
2409 case MSR_AMD64_OSVW_ID_LENGTH:
2410 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2411 return 1;
2412 vcpu->arch.osvw.length = data;
2413 break;
2414 case MSR_AMD64_OSVW_STATUS:
2415 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2416 return 1;
2417 vcpu->arch.osvw.status = data;
2418 break;
2419 case MSR_PLATFORM_INFO:
2420 if (!msr_info->host_initiated ||
2421 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2422 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2423 cpuid_fault_enabled(vcpu)))
2424 return 1;
2425 vcpu->arch.msr_platform_info = data;
2426 break;
2427 case MSR_MISC_FEATURES_ENABLES:
2428 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2429 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2430 !supports_cpuid_fault(vcpu)))
2431 return 1;
2432 vcpu->arch.msr_misc_features_enables = data;
2433 break;
2434 default:
2435 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2436 return xen_hvm_config(vcpu, data);
2437 if (kvm_pmu_is_valid_msr(vcpu, msr))
2438 return kvm_pmu_set_msr(vcpu, msr_info);
2439 if (!ignore_msrs) {
2440 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2441 msr, data);
2442 return 1;
2443 } else {
2444 if (report_ignored_msrs)
2445 vcpu_unimpl(vcpu,
2446 "ignored wrmsr: 0x%x data 0x%llx\n",
2447 msr, data);
2448 break;
2449 }
2450 }
2451 return 0;
2452 }
2453 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2454
2455
2456 /*
2457 * Reads an msr value (of 'msr_index') into 'pdata'.
2458 * Returns 0 on success, non-0 otherwise.
2459 * Assumes vcpu_load() was already called.
2460 */
2461 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2462 {
2463 return kvm_x86_ops->get_msr(vcpu, msr);
2464 }
2465 EXPORT_SYMBOL_GPL(kvm_get_msr);
2466
2467 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2468 {
2469 u64 data;
2470 u64 mcg_cap = vcpu->arch.mcg_cap;
2471 unsigned bank_num = mcg_cap & 0xff;
2472
2473 switch (msr) {
2474 case MSR_IA32_P5_MC_ADDR:
2475 case MSR_IA32_P5_MC_TYPE:
2476 data = 0;
2477 break;
2478 case MSR_IA32_MCG_CAP:
2479 data = vcpu->arch.mcg_cap;
2480 break;
2481 case MSR_IA32_MCG_CTL:
2482 if (!(mcg_cap & MCG_CTL_P))
2483 return 1;
2484 data = vcpu->arch.mcg_ctl;
2485 break;
2486 case MSR_IA32_MCG_STATUS:
2487 data = vcpu->arch.mcg_status;
2488 break;
2489 default:
2490 if (msr >= MSR_IA32_MC0_CTL &&
2491 msr < MSR_IA32_MCx_CTL(bank_num)) {
2492 u32 offset = msr - MSR_IA32_MC0_CTL;
2493 data = vcpu->arch.mce_banks[offset];
2494 break;
2495 }
2496 return 1;
2497 }
2498 *pdata = data;
2499 return 0;
2500 }
2501
2502 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2503 {
2504 switch (msr_info->index) {
2505 case MSR_IA32_PLATFORM_ID:
2506 case MSR_IA32_EBL_CR_POWERON:
2507 case MSR_IA32_DEBUGCTLMSR:
2508 case MSR_IA32_LASTBRANCHFROMIP:
2509 case MSR_IA32_LASTBRANCHTOIP:
2510 case MSR_IA32_LASTINTFROMIP:
2511 case MSR_IA32_LASTINTTOIP:
2512 case MSR_K8_SYSCFG:
2513 case MSR_K8_TSEG_ADDR:
2514 case MSR_K8_TSEG_MASK:
2515 case MSR_K7_HWCR:
2516 case MSR_VM_HSAVE_PA:
2517 case MSR_K8_INT_PENDING_MSG:
2518 case MSR_AMD64_NB_CFG:
2519 case MSR_FAM10H_MMIO_CONF_BASE:
2520 case MSR_AMD64_BU_CFG2:
2521 case MSR_IA32_PERF_CTL:
2522 case MSR_AMD64_DC_CFG:
2523 msr_info->data = 0;
2524 break;
2525 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2526 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2527 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2528 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2529 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2530 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2531 msr_info->data = 0;
2532 break;
2533 case MSR_IA32_UCODE_REV:
2534 msr_info->data = 0x100000000ULL;
2535 break;
2536 case MSR_IA32_TSC:
2537 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2538 break;
2539 case MSR_MTRRcap:
2540 case 0x200 ... 0x2ff:
2541 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2542 case 0xcd: /* fsb frequency */
2543 msr_info->data = 3;
2544 break;
2545 /*
2546 * MSR_EBC_FREQUENCY_ID
2547 * Conservative value valid for even the basic CPU models.
2548 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2549 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2550 * and 266MHz for model 3, or 4. Set Core Clock
2551 * Frequency to System Bus Frequency Ratio to 1 (bits
2552 * 31:24) even though these are only valid for CPU
2553 * models > 2, however guests may end up dividing or
2554 * multiplying by zero otherwise.
2555 */
2556 case MSR_EBC_FREQUENCY_ID:
2557 msr_info->data = 1 << 24;
2558 break;
2559 case MSR_IA32_APICBASE:
2560 msr_info->data = kvm_get_apic_base(vcpu);
2561 break;
2562 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2563 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2564 break;
2565 case MSR_IA32_TSCDEADLINE:
2566 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2567 break;
2568 case MSR_IA32_TSC_ADJUST:
2569 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2570 break;
2571 case MSR_IA32_MISC_ENABLE:
2572 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2573 break;
2574 case MSR_IA32_SMBASE:
2575 if (!msr_info->host_initiated)
2576 return 1;
2577 msr_info->data = vcpu->arch.smbase;
2578 break;
2579 case MSR_IA32_PERF_STATUS:
2580 /* TSC increment by tick */
2581 msr_info->data = 1000ULL;
2582 /* CPU multiplier */
2583 msr_info->data |= (((uint64_t)4ULL) << 40);
2584 break;
2585 case MSR_EFER:
2586 msr_info->data = vcpu->arch.efer;
2587 break;
2588 case MSR_KVM_WALL_CLOCK:
2589 case MSR_KVM_WALL_CLOCK_NEW:
2590 msr_info->data = vcpu->kvm->arch.wall_clock;
2591 break;
2592 case MSR_KVM_SYSTEM_TIME:
2593 case MSR_KVM_SYSTEM_TIME_NEW:
2594 msr_info->data = vcpu->arch.time;
2595 break;
2596 case MSR_KVM_ASYNC_PF_EN:
2597 msr_info->data = vcpu->arch.apf.msr_val;
2598 break;
2599 case MSR_KVM_STEAL_TIME:
2600 msr_info->data = vcpu->arch.st.msr_val;
2601 break;
2602 case MSR_KVM_PV_EOI_EN:
2603 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2604 break;
2605 case MSR_IA32_P5_MC_ADDR:
2606 case MSR_IA32_P5_MC_TYPE:
2607 case MSR_IA32_MCG_CAP:
2608 case MSR_IA32_MCG_CTL:
2609 case MSR_IA32_MCG_STATUS:
2610 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2611 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2612 case MSR_K7_CLK_CTL:
2613 /*
2614 * Provide expected ramp-up count for K7. All other
2615 * are set to zero, indicating minimum divisors for
2616 * every field.
2617 *
2618 * This prevents guest kernels on AMD host with CPU
2619 * type 6, model 8 and higher from exploding due to
2620 * the rdmsr failing.
2621 */
2622 msr_info->data = 0x20000000;
2623 break;
2624 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2625 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2626 case HV_X64_MSR_CRASH_CTL:
2627 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2628 return kvm_hv_get_msr_common(vcpu,
2629 msr_info->index, &msr_info->data);
2630 break;
2631 case MSR_IA32_BBL_CR_CTL3:
2632 /* This legacy MSR exists but isn't fully documented in current
2633 * silicon. It is however accessed by winxp in very narrow
2634 * scenarios where it sets bit #19, itself documented as
2635 * a "reserved" bit. Best effort attempt to source coherent
2636 * read data here should the balance of the register be
2637 * interpreted by the guest:
2638 *
2639 * L2 cache control register 3: 64GB range, 256KB size,
2640 * enabled, latency 0x1, configured
2641 */
2642 msr_info->data = 0xbe702111;
2643 break;
2644 case MSR_AMD64_OSVW_ID_LENGTH:
2645 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2646 return 1;
2647 msr_info->data = vcpu->arch.osvw.length;
2648 break;
2649 case MSR_AMD64_OSVW_STATUS:
2650 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2651 return 1;
2652 msr_info->data = vcpu->arch.osvw.status;
2653 break;
2654 case MSR_PLATFORM_INFO:
2655 msr_info->data = vcpu->arch.msr_platform_info;
2656 break;
2657 case MSR_MISC_FEATURES_ENABLES:
2658 msr_info->data = vcpu->arch.msr_misc_features_enables;
2659 break;
2660 default:
2661 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2662 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2663 if (!ignore_msrs) {
2664 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2665 msr_info->index);
2666 return 1;
2667 } else {
2668 if (report_ignored_msrs)
2669 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2670 msr_info->index);
2671 msr_info->data = 0;
2672 }
2673 break;
2674 }
2675 return 0;
2676 }
2677 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2678
2679 /*
2680 * Read or write a bunch of msrs. All parameters are kernel addresses.
2681 *
2682 * @return number of msrs set successfully.
2683 */
2684 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2685 struct kvm_msr_entry *entries,
2686 int (*do_msr)(struct kvm_vcpu *vcpu,
2687 unsigned index, u64 *data))
2688 {
2689 int i;
2690
2691 for (i = 0; i < msrs->nmsrs; ++i)
2692 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2693 break;
2694
2695 return i;
2696 }
2697
2698 /*
2699 * Read or write a bunch of msrs. Parameters are user addresses.
2700 *
2701 * @return number of msrs set successfully.
2702 */
2703 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2704 int (*do_msr)(struct kvm_vcpu *vcpu,
2705 unsigned index, u64 *data),
2706 int writeback)
2707 {
2708 struct kvm_msrs msrs;
2709 struct kvm_msr_entry *entries;
2710 int r, n;
2711 unsigned size;
2712
2713 r = -EFAULT;
2714 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2715 goto out;
2716
2717 r = -E2BIG;
2718 if (msrs.nmsrs >= MAX_IO_MSRS)
2719 goto out;
2720
2721 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2722 entries = memdup_user(user_msrs->entries, size);
2723 if (IS_ERR(entries)) {
2724 r = PTR_ERR(entries);
2725 goto out;
2726 }
2727
2728 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2729 if (r < 0)
2730 goto out_free;
2731
2732 r = -EFAULT;
2733 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2734 goto out_free;
2735
2736 r = n;
2737
2738 out_free:
2739 kfree(entries);
2740 out:
2741 return r;
2742 }
2743
2744 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2745 {
2746 int r;
2747
2748 switch (ext) {
2749 case KVM_CAP_IRQCHIP:
2750 case KVM_CAP_HLT:
2751 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2752 case KVM_CAP_SET_TSS_ADDR:
2753 case KVM_CAP_EXT_CPUID:
2754 case KVM_CAP_EXT_EMUL_CPUID:
2755 case KVM_CAP_CLOCKSOURCE:
2756 case KVM_CAP_PIT:
2757 case KVM_CAP_NOP_IO_DELAY:
2758 case KVM_CAP_MP_STATE:
2759 case KVM_CAP_SYNC_MMU:
2760 case KVM_CAP_USER_NMI:
2761 case KVM_CAP_REINJECT_CONTROL:
2762 case KVM_CAP_IRQ_INJECT_STATUS:
2763 case KVM_CAP_IOEVENTFD:
2764 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2765 case KVM_CAP_PIT2:
2766 case KVM_CAP_PIT_STATE2:
2767 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2768 case KVM_CAP_XEN_HVM:
2769 case KVM_CAP_VCPU_EVENTS:
2770 case KVM_CAP_HYPERV:
2771 case KVM_CAP_HYPERV_VAPIC:
2772 case KVM_CAP_HYPERV_SPIN:
2773 case KVM_CAP_HYPERV_SYNIC:
2774 case KVM_CAP_HYPERV_SYNIC2:
2775 case KVM_CAP_HYPERV_VP_INDEX:
2776 case KVM_CAP_PCI_SEGMENT:
2777 case KVM_CAP_DEBUGREGS:
2778 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2779 case KVM_CAP_XSAVE:
2780 case KVM_CAP_ASYNC_PF:
2781 case KVM_CAP_GET_TSC_KHZ:
2782 case KVM_CAP_KVMCLOCK_CTRL:
2783 case KVM_CAP_READONLY_MEM:
2784 case KVM_CAP_HYPERV_TIME:
2785 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2786 case KVM_CAP_TSC_DEADLINE_TIMER:
2787 case KVM_CAP_ENABLE_CAP_VM:
2788 case KVM_CAP_DISABLE_QUIRKS:
2789 case KVM_CAP_SET_BOOT_CPU_ID:
2790 case KVM_CAP_SPLIT_IRQCHIP:
2791 case KVM_CAP_IMMEDIATE_EXIT:
2792 case KVM_CAP_GET_MSR_FEATURES:
2793 r = 1;
2794 break;
2795 case KVM_CAP_ADJUST_CLOCK:
2796 r = KVM_CLOCK_TSC_STABLE;
2797 break;
2798 case KVM_CAP_X86_GUEST_MWAIT:
2799 r = kvm_mwait_in_guest();
2800 break;
2801 case KVM_CAP_X86_SMM:
2802 /* SMBASE is usually relocated above 1M on modern chipsets,
2803 * and SMM handlers might indeed rely on 4G segment limits,
2804 * so do not report SMM to be available if real mode is
2805 * emulated via vm86 mode. Still, do not go to great lengths
2806 * to avoid userspace's usage of the feature, because it is a
2807 * fringe case that is not enabled except via specific settings
2808 * of the module parameters.
2809 */
2810 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2811 break;
2812 case KVM_CAP_VAPIC:
2813 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2814 break;
2815 case KVM_CAP_NR_VCPUS:
2816 r = KVM_SOFT_MAX_VCPUS;
2817 break;
2818 case KVM_CAP_MAX_VCPUS:
2819 r = KVM_MAX_VCPUS;
2820 break;
2821 case KVM_CAP_NR_MEMSLOTS:
2822 r = KVM_USER_MEM_SLOTS;
2823 break;
2824 case KVM_CAP_PV_MMU: /* obsolete */
2825 r = 0;
2826 break;
2827 case KVM_CAP_MCE:
2828 r = KVM_MAX_MCE_BANKS;
2829 break;
2830 case KVM_CAP_XCRS:
2831 r = boot_cpu_has(X86_FEATURE_XSAVE);
2832 break;
2833 case KVM_CAP_TSC_CONTROL:
2834 r = kvm_has_tsc_control;
2835 break;
2836 case KVM_CAP_X2APIC_API:
2837 r = KVM_X2APIC_API_VALID_FLAGS;
2838 break;
2839 default:
2840 r = 0;
2841 break;
2842 }
2843 return r;
2844
2845 }
2846
2847 long kvm_arch_dev_ioctl(struct file *filp,
2848 unsigned int ioctl, unsigned long arg)
2849 {
2850 void __user *argp = (void __user *)arg;
2851 long r;
2852
2853 switch (ioctl) {
2854 case KVM_GET_MSR_INDEX_LIST: {
2855 struct kvm_msr_list __user *user_msr_list = argp;
2856 struct kvm_msr_list msr_list;
2857 unsigned n;
2858
2859 r = -EFAULT;
2860 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2861 goto out;
2862 n = msr_list.nmsrs;
2863 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2864 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2865 goto out;
2866 r = -E2BIG;
2867 if (n < msr_list.nmsrs)
2868 goto out;
2869 r = -EFAULT;
2870 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2871 num_msrs_to_save * sizeof(u32)))
2872 goto out;
2873 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2874 &emulated_msrs,
2875 num_emulated_msrs * sizeof(u32)))
2876 goto out;
2877 r = 0;
2878 break;
2879 }
2880 case KVM_GET_SUPPORTED_CPUID:
2881 case KVM_GET_EMULATED_CPUID: {
2882 struct kvm_cpuid2 __user *cpuid_arg = argp;
2883 struct kvm_cpuid2 cpuid;
2884
2885 r = -EFAULT;
2886 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2887 goto out;
2888
2889 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2890 ioctl);
2891 if (r)
2892 goto out;
2893
2894 r = -EFAULT;
2895 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2896 goto out;
2897 r = 0;
2898 break;
2899 }
2900 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2901 r = -EFAULT;
2902 if (copy_to_user(argp, &kvm_mce_cap_supported,
2903 sizeof(kvm_mce_cap_supported)))
2904 goto out;
2905 r = 0;
2906 break;
2907 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2908 struct kvm_msr_list __user *user_msr_list = argp;
2909 struct kvm_msr_list msr_list;
2910 unsigned int n;
2911
2912 r = -EFAULT;
2913 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2914 goto out;
2915 n = msr_list.nmsrs;
2916 msr_list.nmsrs = num_msr_based_features;
2917 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2918 goto out;
2919 r = -E2BIG;
2920 if (n < msr_list.nmsrs)
2921 goto out;
2922 r = -EFAULT;
2923 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2924 num_msr_based_features * sizeof(u32)))
2925 goto out;
2926 r = 0;
2927 break;
2928 }
2929 case KVM_GET_MSRS:
2930 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2931 break;
2932 }
2933 default:
2934 r = -EINVAL;
2935 }
2936 out:
2937 return r;
2938 }
2939
2940 static void wbinvd_ipi(void *garbage)
2941 {
2942 wbinvd();
2943 }
2944
2945 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2946 {
2947 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2948 }
2949
2950 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2951 {
2952 /* Address WBINVD may be executed by guest */
2953 if (need_emulate_wbinvd(vcpu)) {
2954 if (kvm_x86_ops->has_wbinvd_exit())
2955 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2956 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2957 smp_call_function_single(vcpu->cpu,
2958 wbinvd_ipi, NULL, 1);
2959 }
2960
2961 kvm_x86_ops->vcpu_load(vcpu, cpu);
2962
2963 /* Apply any externally detected TSC adjustments (due to suspend) */
2964 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2965 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2966 vcpu->arch.tsc_offset_adjustment = 0;
2967 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2968 }
2969
2970 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2971 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2972 rdtsc() - vcpu->arch.last_host_tsc;
2973 if (tsc_delta < 0)
2974 mark_tsc_unstable("KVM discovered backwards TSC");
2975
2976 if (check_tsc_unstable()) {
2977 u64 offset = kvm_compute_tsc_offset(vcpu,
2978 vcpu->arch.last_guest_tsc);
2979 kvm_vcpu_write_tsc_offset(vcpu, offset);
2980 vcpu->arch.tsc_catchup = 1;
2981 }
2982
2983 if (kvm_lapic_hv_timer_in_use(vcpu))
2984 kvm_lapic_restart_hv_timer(vcpu);
2985
2986 /*
2987 * On a host with synchronized TSC, there is no need to update
2988 * kvmclock on vcpu->cpu migration
2989 */
2990 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2991 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2992 if (vcpu->cpu != cpu)
2993 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2994 vcpu->cpu = cpu;
2995 }
2996
2997 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2998 }
2999
3000 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3001 {
3002 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3003 return;
3004
3005 vcpu->arch.st.steal.preempted = 1;
3006
3007 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3008 &vcpu->arch.st.steal.preempted,
3009 offsetof(struct kvm_steal_time, preempted),
3010 sizeof(vcpu->arch.st.steal.preempted));
3011 }
3012
3013 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3014 {
3015 int idx;
3016
3017 if (vcpu->preempted)
3018 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3019
3020 /*
3021 * Disable page faults because we're in atomic context here.
3022 * kvm_write_guest_offset_cached() would call might_fault()
3023 * that relies on pagefault_disable() to tell if there's a
3024 * bug. NOTE: the write to guest memory may not go through if
3025 * during postcopy live migration or if there's heavy guest
3026 * paging.
3027 */
3028 pagefault_disable();
3029 /*
3030 * kvm_memslots() will be called by
3031 * kvm_write_guest_offset_cached() so take the srcu lock.
3032 */
3033 idx = srcu_read_lock(&vcpu->kvm->srcu);
3034 kvm_steal_time_set_preempted(vcpu);
3035 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3036 pagefault_enable();
3037 kvm_x86_ops->vcpu_put(vcpu);
3038 vcpu->arch.last_host_tsc = rdtsc();
3039 /*
3040 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3041 * on every vmexit, but if not, we might have a stale dr6 from the
3042 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3043 */
3044 set_debugreg(0, 6);
3045 }
3046
3047 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3048 struct kvm_lapic_state *s)
3049 {
3050 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
3051 kvm_x86_ops->sync_pir_to_irr(vcpu);
3052
3053 return kvm_apic_get_state(vcpu, s);
3054 }
3055
3056 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3057 struct kvm_lapic_state *s)
3058 {
3059 int r;
3060
3061 r = kvm_apic_set_state(vcpu, s);
3062 if (r)
3063 return r;
3064 update_cr8_intercept(vcpu);
3065
3066 return 0;
3067 }
3068
3069 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3070 {
3071 return (!lapic_in_kernel(vcpu) ||
3072 kvm_apic_accept_pic_intr(vcpu));
3073 }
3074
3075 /*
3076 * if userspace requested an interrupt window, check that the
3077 * interrupt window is open.
3078 *
3079 * No need to exit to userspace if we already have an interrupt queued.
3080 */
3081 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3082 {
3083 return kvm_arch_interrupt_allowed(vcpu) &&
3084 !kvm_cpu_has_interrupt(vcpu) &&
3085 !kvm_event_needs_reinjection(vcpu) &&
3086 kvm_cpu_accept_dm_intr(vcpu);
3087 }
3088
3089 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3090 struct kvm_interrupt *irq)
3091 {
3092 if (irq->irq >= KVM_NR_INTERRUPTS)
3093 return -EINVAL;
3094
3095 if (!irqchip_in_kernel(vcpu->kvm)) {
3096 kvm_queue_interrupt(vcpu, irq->irq, false);
3097 kvm_make_request(KVM_REQ_EVENT, vcpu);
3098 return 0;
3099 }
3100
3101 /*
3102 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3103 * fail for in-kernel 8259.
3104 */
3105 if (pic_in_kernel(vcpu->kvm))
3106 return -ENXIO;
3107
3108 if (vcpu->arch.pending_external_vector != -1)
3109 return -EEXIST;
3110
3111 vcpu->arch.pending_external_vector = irq->irq;
3112 kvm_make_request(KVM_REQ_EVENT, vcpu);
3113 return 0;
3114 }
3115
3116 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3117 {
3118 kvm_inject_nmi(vcpu);
3119
3120 return 0;
3121 }
3122
3123 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3124 {
3125 kvm_make_request(KVM_REQ_SMI, vcpu);
3126
3127 return 0;
3128 }
3129
3130 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3131 struct kvm_tpr_access_ctl *tac)
3132 {
3133 if (tac->flags)
3134 return -EINVAL;
3135 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3136 return 0;
3137 }
3138
3139 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3140 u64 mcg_cap)
3141 {
3142 int r;
3143 unsigned bank_num = mcg_cap & 0xff, bank;
3144
3145 r = -EINVAL;
3146 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3147 goto out;
3148 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3149 goto out;
3150 r = 0;
3151 vcpu->arch.mcg_cap = mcg_cap;
3152 /* Init IA32_MCG_CTL to all 1s */
3153 if (mcg_cap & MCG_CTL_P)
3154 vcpu->arch.mcg_ctl = ~(u64)0;
3155 /* Init IA32_MCi_CTL to all 1s */
3156 for (bank = 0; bank < bank_num; bank++)
3157 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3158
3159 if (kvm_x86_ops->setup_mce)
3160 kvm_x86_ops->setup_mce(vcpu);
3161 out:
3162 return r;
3163 }
3164
3165 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3166 struct kvm_x86_mce *mce)
3167 {
3168 u64 mcg_cap = vcpu->arch.mcg_cap;
3169 unsigned bank_num = mcg_cap & 0xff;
3170 u64 *banks = vcpu->arch.mce_banks;
3171
3172 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3173 return -EINVAL;
3174 /*
3175 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3176 * reporting is disabled
3177 */
3178 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3179 vcpu->arch.mcg_ctl != ~(u64)0)
3180 return 0;
3181 banks += 4 * mce->bank;
3182 /*
3183 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3184 * reporting is disabled for the bank
3185 */
3186 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3187 return 0;
3188 if (mce->status & MCI_STATUS_UC) {
3189 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3190 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3191 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3192 return 0;
3193 }
3194 if (banks[1] & MCI_STATUS_VAL)
3195 mce->status |= MCI_STATUS_OVER;
3196 banks[2] = mce->addr;
3197 banks[3] = mce->misc;
3198 vcpu->arch.mcg_status = mce->mcg_status;
3199 banks[1] = mce->status;
3200 kvm_queue_exception(vcpu, MC_VECTOR);
3201 } else if (!(banks[1] & MCI_STATUS_VAL)
3202 || !(banks[1] & MCI_STATUS_UC)) {
3203 if (banks[1] & MCI_STATUS_VAL)
3204 mce->status |= MCI_STATUS_OVER;
3205 banks[2] = mce->addr;
3206 banks[3] = mce->misc;
3207 banks[1] = mce->status;
3208 } else
3209 banks[1] |= MCI_STATUS_OVER;
3210 return 0;
3211 }
3212
3213 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3214 struct kvm_vcpu_events *events)
3215 {
3216 process_nmi(vcpu);
3217 /*
3218 * FIXME: pass injected and pending separately. This is only
3219 * needed for nested virtualization, whose state cannot be
3220 * migrated yet. For now we can combine them.
3221 */
3222 events->exception.injected =
3223 (vcpu->arch.exception.pending ||
3224 vcpu->arch.exception.injected) &&
3225 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3226 events->exception.nr = vcpu->arch.exception.nr;
3227 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3228 events->exception.pad = 0;
3229 events->exception.error_code = vcpu->arch.exception.error_code;
3230
3231 events->interrupt.injected =
3232 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3233 events->interrupt.nr = vcpu->arch.interrupt.nr;
3234 events->interrupt.soft = 0;
3235 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3236
3237 events->nmi.injected = vcpu->arch.nmi_injected;
3238 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3239 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3240 events->nmi.pad = 0;
3241
3242 events->sipi_vector = 0; /* never valid when reporting to user space */
3243
3244 events->smi.smm = is_smm(vcpu);
3245 events->smi.pending = vcpu->arch.smi_pending;
3246 events->smi.smm_inside_nmi =
3247 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3248 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3249
3250 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3251 | KVM_VCPUEVENT_VALID_SHADOW
3252 | KVM_VCPUEVENT_VALID_SMM);
3253 memset(&events->reserved, 0, sizeof(events->reserved));
3254 }
3255
3256 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3257
3258 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3259 struct kvm_vcpu_events *events)
3260 {
3261 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3262 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3263 | KVM_VCPUEVENT_VALID_SHADOW
3264 | KVM_VCPUEVENT_VALID_SMM))
3265 return -EINVAL;
3266
3267 if (events->exception.injected &&
3268 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3269 is_guest_mode(vcpu)))
3270 return -EINVAL;
3271
3272 /* INITs are latched while in SMM */
3273 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3274 (events->smi.smm || events->smi.pending) &&
3275 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3276 return -EINVAL;
3277
3278 process_nmi(vcpu);
3279 vcpu->arch.exception.injected = false;
3280 vcpu->arch.exception.pending = events->exception.injected;
3281 vcpu->arch.exception.nr = events->exception.nr;
3282 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3283 vcpu->arch.exception.error_code = events->exception.error_code;
3284
3285 vcpu->arch.interrupt.pending = events->interrupt.injected;
3286 vcpu->arch.interrupt.nr = events->interrupt.nr;
3287 vcpu->arch.interrupt.soft = events->interrupt.soft;
3288 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3289 kvm_x86_ops->set_interrupt_shadow(vcpu,
3290 events->interrupt.shadow);
3291
3292 vcpu->arch.nmi_injected = events->nmi.injected;
3293 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3294 vcpu->arch.nmi_pending = events->nmi.pending;
3295 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3296
3297 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3298 lapic_in_kernel(vcpu))
3299 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3300
3301 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3302 u32 hflags = vcpu->arch.hflags;
3303 if (events->smi.smm)
3304 hflags |= HF_SMM_MASK;
3305 else
3306 hflags &= ~HF_SMM_MASK;
3307 kvm_set_hflags(vcpu, hflags);
3308
3309 vcpu->arch.smi_pending = events->smi.pending;
3310
3311 if (events->smi.smm) {
3312 if (events->smi.smm_inside_nmi)
3313 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3314 else
3315 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3316 if (lapic_in_kernel(vcpu)) {
3317 if (events->smi.latched_init)
3318 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3319 else
3320 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3321 }
3322 }
3323 }
3324
3325 kvm_make_request(KVM_REQ_EVENT, vcpu);
3326
3327 return 0;
3328 }
3329
3330 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3331 struct kvm_debugregs *dbgregs)
3332 {
3333 unsigned long val;
3334
3335 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3336 kvm_get_dr(vcpu, 6, &val);
3337 dbgregs->dr6 = val;
3338 dbgregs->dr7 = vcpu->arch.dr7;
3339 dbgregs->flags = 0;
3340 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3341 }
3342
3343 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3344 struct kvm_debugregs *dbgregs)
3345 {
3346 if (dbgregs->flags)
3347 return -EINVAL;
3348
3349 if (dbgregs->dr6 & ~0xffffffffull)
3350 return -EINVAL;
3351 if (dbgregs->dr7 & ~0xffffffffull)
3352 return -EINVAL;
3353
3354 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3355 kvm_update_dr0123(vcpu);
3356 vcpu->arch.dr6 = dbgregs->dr6;
3357 kvm_update_dr6(vcpu);
3358 vcpu->arch.dr7 = dbgregs->dr7;
3359 kvm_update_dr7(vcpu);
3360
3361 return 0;
3362 }
3363
3364 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3365
3366 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3367 {
3368 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3369 u64 xstate_bv = xsave->header.xfeatures;
3370 u64 valid;
3371
3372 /*
3373 * Copy legacy XSAVE area, to avoid complications with CPUID
3374 * leaves 0 and 1 in the loop below.
3375 */
3376 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3377
3378 /* Set XSTATE_BV */
3379 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3380 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3381
3382 /*
3383 * Copy each region from the possibly compacted offset to the
3384 * non-compacted offset.
3385 */
3386 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3387 while (valid) {
3388 u64 feature = valid & -valid;
3389 int index = fls64(feature) - 1;
3390 void *src = get_xsave_addr(xsave, feature);
3391
3392 if (src) {
3393 u32 size, offset, ecx, edx;
3394 cpuid_count(XSTATE_CPUID, index,
3395 &size, &offset, &ecx, &edx);
3396 if (feature == XFEATURE_MASK_PKRU)
3397 memcpy(dest + offset, &vcpu->arch.pkru,
3398 sizeof(vcpu->arch.pkru));
3399 else
3400 memcpy(dest + offset, src, size);
3401
3402 }
3403
3404 valid -= feature;
3405 }
3406 }
3407
3408 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3409 {
3410 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3411 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3412 u64 valid;
3413
3414 /*
3415 * Copy legacy XSAVE area, to avoid complications with CPUID
3416 * leaves 0 and 1 in the loop below.
3417 */
3418 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3419
3420 /* Set XSTATE_BV and possibly XCOMP_BV. */
3421 xsave->header.xfeatures = xstate_bv;
3422 if (boot_cpu_has(X86_FEATURE_XSAVES))
3423 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3424
3425 /*
3426 * Copy each region from the non-compacted offset to the
3427 * possibly compacted offset.
3428 */
3429 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3430 while (valid) {
3431 u64 feature = valid & -valid;
3432 int index = fls64(feature) - 1;
3433 void *dest = get_xsave_addr(xsave, feature);
3434
3435 if (dest) {
3436 u32 size, offset, ecx, edx;
3437 cpuid_count(XSTATE_CPUID, index,
3438 &size, &offset, &ecx, &edx);
3439 if (feature == XFEATURE_MASK_PKRU)
3440 memcpy(&vcpu->arch.pkru, src + offset,
3441 sizeof(vcpu->arch.pkru));
3442 else
3443 memcpy(dest, src + offset, size);
3444 }
3445
3446 valid -= feature;
3447 }
3448 }
3449
3450 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3451 struct kvm_xsave *guest_xsave)
3452 {
3453 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3454 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3455 fill_xsave((u8 *) guest_xsave->region, vcpu);
3456 } else {
3457 memcpy(guest_xsave->region,
3458 &vcpu->arch.guest_fpu.state.fxsave,
3459 sizeof(struct fxregs_state));
3460 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3461 XFEATURE_MASK_FPSSE;
3462 }
3463 }
3464
3465 #define XSAVE_MXCSR_OFFSET 24
3466
3467 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3468 struct kvm_xsave *guest_xsave)
3469 {
3470 u64 xstate_bv =
3471 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3472 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3473
3474 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3475 /*
3476 * Here we allow setting states that are not present in
3477 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3478 * with old userspace.
3479 */
3480 if (xstate_bv & ~kvm_supported_xcr0() ||
3481 mxcsr & ~mxcsr_feature_mask)
3482 return -EINVAL;
3483 load_xsave(vcpu, (u8 *)guest_xsave->region);
3484 } else {
3485 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3486 mxcsr & ~mxcsr_feature_mask)
3487 return -EINVAL;
3488 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3489 guest_xsave->region, sizeof(struct fxregs_state));
3490 }
3491 return 0;
3492 }
3493
3494 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3495 struct kvm_xcrs *guest_xcrs)
3496 {
3497 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3498 guest_xcrs->nr_xcrs = 0;
3499 return;
3500 }
3501
3502 guest_xcrs->nr_xcrs = 1;
3503 guest_xcrs->flags = 0;
3504 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3505 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3506 }
3507
3508 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3509 struct kvm_xcrs *guest_xcrs)
3510 {
3511 int i, r = 0;
3512
3513 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3514 return -EINVAL;
3515
3516 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3517 return -EINVAL;
3518
3519 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3520 /* Only support XCR0 currently */
3521 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3522 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3523 guest_xcrs->xcrs[i].value);
3524 break;
3525 }
3526 if (r)
3527 r = -EINVAL;
3528 return r;
3529 }
3530
3531 /*
3532 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3533 * stopped by the hypervisor. This function will be called from the host only.
3534 * EINVAL is returned when the host attempts to set the flag for a guest that
3535 * does not support pv clocks.
3536 */
3537 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3538 {
3539 if (!vcpu->arch.pv_time_enabled)
3540 return -EINVAL;
3541 vcpu->arch.pvclock_set_guest_stopped_request = true;
3542 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3543 return 0;
3544 }
3545
3546 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3547 struct kvm_enable_cap *cap)
3548 {
3549 if (cap->flags)
3550 return -EINVAL;
3551
3552 switch (cap->cap) {
3553 case KVM_CAP_HYPERV_SYNIC2:
3554 if (cap->args[0])
3555 return -EINVAL;
3556 case KVM_CAP_HYPERV_SYNIC:
3557 if (!irqchip_in_kernel(vcpu->kvm))
3558 return -EINVAL;
3559 return kvm_hv_activate_synic(vcpu, cap->cap ==
3560 KVM_CAP_HYPERV_SYNIC2);
3561 default:
3562 return -EINVAL;
3563 }
3564 }
3565
3566 long kvm_arch_vcpu_ioctl(struct file *filp,
3567 unsigned int ioctl, unsigned long arg)
3568 {
3569 struct kvm_vcpu *vcpu = filp->private_data;
3570 void __user *argp = (void __user *)arg;
3571 int r;
3572 union {
3573 struct kvm_lapic_state *lapic;
3574 struct kvm_xsave *xsave;
3575 struct kvm_xcrs *xcrs;
3576 void *buffer;
3577 } u;
3578
3579 u.buffer = NULL;
3580 switch (ioctl) {
3581 case KVM_GET_LAPIC: {
3582 r = -EINVAL;
3583 if (!lapic_in_kernel(vcpu))
3584 goto out;
3585 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3586
3587 r = -ENOMEM;
3588 if (!u.lapic)
3589 goto out;
3590 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3591 if (r)
3592 goto out;
3593 r = -EFAULT;
3594 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3595 goto out;
3596 r = 0;
3597 break;
3598 }
3599 case KVM_SET_LAPIC: {
3600 r = -EINVAL;
3601 if (!lapic_in_kernel(vcpu))
3602 goto out;
3603 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3604 if (IS_ERR(u.lapic))
3605 return PTR_ERR(u.lapic);
3606
3607 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3608 break;
3609 }
3610 case KVM_INTERRUPT: {
3611 struct kvm_interrupt irq;
3612
3613 r = -EFAULT;
3614 if (copy_from_user(&irq, argp, sizeof irq))
3615 goto out;
3616 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3617 break;
3618 }
3619 case KVM_NMI: {
3620 r = kvm_vcpu_ioctl_nmi(vcpu);
3621 break;
3622 }
3623 case KVM_SMI: {
3624 r = kvm_vcpu_ioctl_smi(vcpu);
3625 break;
3626 }
3627 case KVM_SET_CPUID: {
3628 struct kvm_cpuid __user *cpuid_arg = argp;
3629 struct kvm_cpuid cpuid;
3630
3631 r = -EFAULT;
3632 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3633 goto out;
3634 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3635 break;
3636 }
3637 case KVM_SET_CPUID2: {
3638 struct kvm_cpuid2 __user *cpuid_arg = argp;
3639 struct kvm_cpuid2 cpuid;
3640
3641 r = -EFAULT;
3642 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3643 goto out;
3644 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3645 cpuid_arg->entries);
3646 break;
3647 }
3648 case KVM_GET_CPUID2: {
3649 struct kvm_cpuid2 __user *cpuid_arg = argp;
3650 struct kvm_cpuid2 cpuid;
3651
3652 r = -EFAULT;
3653 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3654 goto out;
3655 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3656 cpuid_arg->entries);
3657 if (r)
3658 goto out;
3659 r = -EFAULT;
3660 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3661 goto out;
3662 r = 0;
3663 break;
3664 }
3665 case KVM_GET_MSRS: {
3666 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3667 r = msr_io(vcpu, argp, do_get_msr, 1);
3668 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3669 break;
3670 }
3671 case KVM_SET_MSRS: {
3672 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3673 r = msr_io(vcpu, argp, do_set_msr, 0);
3674 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3675 break;
3676 }
3677 case KVM_TPR_ACCESS_REPORTING: {
3678 struct kvm_tpr_access_ctl tac;
3679
3680 r = -EFAULT;
3681 if (copy_from_user(&tac, argp, sizeof tac))
3682 goto out;
3683 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3684 if (r)
3685 goto out;
3686 r = -EFAULT;
3687 if (copy_to_user(argp, &tac, sizeof tac))
3688 goto out;
3689 r = 0;
3690 break;
3691 };
3692 case KVM_SET_VAPIC_ADDR: {
3693 struct kvm_vapic_addr va;
3694 int idx;
3695
3696 r = -EINVAL;
3697 if (!lapic_in_kernel(vcpu))
3698 goto out;
3699 r = -EFAULT;
3700 if (copy_from_user(&va, argp, sizeof va))
3701 goto out;
3702 idx = srcu_read_lock(&vcpu->kvm->srcu);
3703 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3704 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3705 break;
3706 }
3707 case KVM_X86_SETUP_MCE: {
3708 u64 mcg_cap;
3709
3710 r = -EFAULT;
3711 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3712 goto out;
3713 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3714 break;
3715 }
3716 case KVM_X86_SET_MCE: {
3717 struct kvm_x86_mce mce;
3718
3719 r = -EFAULT;
3720 if (copy_from_user(&mce, argp, sizeof mce))
3721 goto out;
3722 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3723 break;
3724 }
3725 case KVM_GET_VCPU_EVENTS: {
3726 struct kvm_vcpu_events events;
3727
3728 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3729
3730 r = -EFAULT;
3731 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3732 break;
3733 r = 0;
3734 break;
3735 }
3736 case KVM_SET_VCPU_EVENTS: {
3737 struct kvm_vcpu_events events;
3738
3739 r = -EFAULT;
3740 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3741 break;
3742
3743 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3744 break;
3745 }
3746 case KVM_GET_DEBUGREGS: {
3747 struct kvm_debugregs dbgregs;
3748
3749 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3750
3751 r = -EFAULT;
3752 if (copy_to_user(argp, &dbgregs,
3753 sizeof(struct kvm_debugregs)))
3754 break;
3755 r = 0;
3756 break;
3757 }
3758 case KVM_SET_DEBUGREGS: {
3759 struct kvm_debugregs dbgregs;
3760
3761 r = -EFAULT;
3762 if (copy_from_user(&dbgregs, argp,
3763 sizeof(struct kvm_debugregs)))
3764 break;
3765
3766 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3767 break;
3768 }
3769 case KVM_GET_XSAVE: {
3770 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3771 r = -ENOMEM;
3772 if (!u.xsave)
3773 break;
3774
3775 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3776
3777 r = -EFAULT;
3778 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3779 break;
3780 r = 0;
3781 break;
3782 }
3783 case KVM_SET_XSAVE: {
3784 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3785 if (IS_ERR(u.xsave))
3786 return PTR_ERR(u.xsave);
3787
3788 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3789 break;
3790 }
3791 case KVM_GET_XCRS: {
3792 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3793 r = -ENOMEM;
3794 if (!u.xcrs)
3795 break;
3796
3797 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3798
3799 r = -EFAULT;
3800 if (copy_to_user(argp, u.xcrs,
3801 sizeof(struct kvm_xcrs)))
3802 break;
3803 r = 0;
3804 break;
3805 }
3806 case KVM_SET_XCRS: {
3807 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3808 if (IS_ERR(u.xcrs))
3809 return PTR_ERR(u.xcrs);
3810
3811 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3812 break;
3813 }
3814 case KVM_SET_TSC_KHZ: {
3815 u32 user_tsc_khz;
3816
3817 r = -EINVAL;
3818 user_tsc_khz = (u32)arg;
3819
3820 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3821 goto out;
3822
3823 if (user_tsc_khz == 0)
3824 user_tsc_khz = tsc_khz;
3825
3826 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3827 r = 0;
3828
3829 goto out;
3830 }
3831 case KVM_GET_TSC_KHZ: {
3832 r = vcpu->arch.virtual_tsc_khz;
3833 goto out;
3834 }
3835 case KVM_KVMCLOCK_CTRL: {
3836 r = kvm_set_guest_paused(vcpu);
3837 goto out;
3838 }
3839 case KVM_ENABLE_CAP: {
3840 struct kvm_enable_cap cap;
3841
3842 r = -EFAULT;
3843 if (copy_from_user(&cap, argp, sizeof(cap)))
3844 goto out;
3845 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3846 break;
3847 }
3848 default:
3849 r = -EINVAL;
3850 }
3851 out:
3852 kfree(u.buffer);
3853 return r;
3854 }
3855
3856 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3857 {
3858 return VM_FAULT_SIGBUS;
3859 }
3860
3861 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3862 {
3863 int ret;
3864
3865 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3866 return -EINVAL;
3867 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3868 return ret;
3869 }
3870
3871 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3872 u64 ident_addr)
3873 {
3874 kvm->arch.ept_identity_map_addr = ident_addr;
3875 return 0;
3876 }
3877
3878 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3879 u32 kvm_nr_mmu_pages)
3880 {
3881 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3882 return -EINVAL;
3883
3884 mutex_lock(&kvm->slots_lock);
3885
3886 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3887 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3888
3889 mutex_unlock(&kvm->slots_lock);
3890 return 0;
3891 }
3892
3893 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3894 {
3895 return kvm->arch.n_max_mmu_pages;
3896 }
3897
3898 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3899 {
3900 struct kvm_pic *pic = kvm->arch.vpic;
3901 int r;
3902
3903 r = 0;
3904 switch (chip->chip_id) {
3905 case KVM_IRQCHIP_PIC_MASTER:
3906 memcpy(&chip->chip.pic, &pic->pics[0],
3907 sizeof(struct kvm_pic_state));
3908 break;
3909 case KVM_IRQCHIP_PIC_SLAVE:
3910 memcpy(&chip->chip.pic, &pic->pics[1],
3911 sizeof(struct kvm_pic_state));
3912 break;
3913 case KVM_IRQCHIP_IOAPIC:
3914 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3915 break;
3916 default:
3917 r = -EINVAL;
3918 break;
3919 }
3920 return r;
3921 }
3922
3923 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3924 {
3925 struct kvm_pic *pic = kvm->arch.vpic;
3926 int r;
3927
3928 r = 0;
3929 switch (chip->chip_id) {
3930 case KVM_IRQCHIP_PIC_MASTER:
3931 spin_lock(&pic->lock);
3932 memcpy(&pic->pics[0], &chip->chip.pic,
3933 sizeof(struct kvm_pic_state));
3934 spin_unlock(&pic->lock);
3935 break;
3936 case KVM_IRQCHIP_PIC_SLAVE:
3937 spin_lock(&pic->lock);
3938 memcpy(&pic->pics[1], &chip->chip.pic,
3939 sizeof(struct kvm_pic_state));
3940 spin_unlock(&pic->lock);
3941 break;
3942 case KVM_IRQCHIP_IOAPIC:
3943 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3944 break;
3945 default:
3946 r = -EINVAL;
3947 break;
3948 }
3949 kvm_pic_update_irq(pic);
3950 return r;
3951 }
3952
3953 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3954 {
3955 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3956
3957 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3958
3959 mutex_lock(&kps->lock);
3960 memcpy(ps, &kps->channels, sizeof(*ps));
3961 mutex_unlock(&kps->lock);
3962 return 0;
3963 }
3964
3965 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3966 {
3967 int i;
3968 struct kvm_pit *pit = kvm->arch.vpit;
3969
3970 mutex_lock(&pit->pit_state.lock);
3971 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3972 for (i = 0; i < 3; i++)
3973 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3974 mutex_unlock(&pit->pit_state.lock);
3975 return 0;
3976 }
3977
3978 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3979 {
3980 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3981 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3982 sizeof(ps->channels));
3983 ps->flags = kvm->arch.vpit->pit_state.flags;
3984 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3985 memset(&ps->reserved, 0, sizeof(ps->reserved));
3986 return 0;
3987 }
3988
3989 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3990 {
3991 int start = 0;
3992 int i;
3993 u32 prev_legacy, cur_legacy;
3994 struct kvm_pit *pit = kvm->arch.vpit;
3995
3996 mutex_lock(&pit->pit_state.lock);
3997 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3998 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3999 if (!prev_legacy && cur_legacy)
4000 start = 1;
4001 memcpy(&pit->pit_state.channels, &ps->channels,
4002 sizeof(pit->pit_state.channels));
4003 pit->pit_state.flags = ps->flags;
4004 for (i = 0; i < 3; i++)
4005 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4006 start && i == 0);
4007 mutex_unlock(&pit->pit_state.lock);
4008 return 0;
4009 }
4010
4011 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4012 struct kvm_reinject_control *control)
4013 {
4014 struct kvm_pit *pit = kvm->arch.vpit;
4015
4016 if (!pit)
4017 return -ENXIO;
4018
4019 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4020 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4021 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4022 */
4023 mutex_lock(&pit->pit_state.lock);
4024 kvm_pit_set_reinject(pit, control->pit_reinject);
4025 mutex_unlock(&pit->pit_state.lock);
4026
4027 return 0;
4028 }
4029
4030 /**
4031 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4032 * @kvm: kvm instance
4033 * @log: slot id and address to which we copy the log
4034 *
4035 * Steps 1-4 below provide general overview of dirty page logging. See
4036 * kvm_get_dirty_log_protect() function description for additional details.
4037 *
4038 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4039 * always flush the TLB (step 4) even if previous step failed and the dirty
4040 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4041 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4042 * writes will be marked dirty for next log read.
4043 *
4044 * 1. Take a snapshot of the bit and clear it if needed.
4045 * 2. Write protect the corresponding page.
4046 * 3. Copy the snapshot to the userspace.
4047 * 4. Flush TLB's if needed.
4048 */
4049 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4050 {
4051 bool is_dirty = false;
4052 int r;
4053
4054 mutex_lock(&kvm->slots_lock);
4055
4056 /*
4057 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4058 */
4059 if (kvm_x86_ops->flush_log_dirty)
4060 kvm_x86_ops->flush_log_dirty(kvm);
4061
4062 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4063
4064 /*
4065 * All the TLBs can be flushed out of mmu lock, see the comments in
4066 * kvm_mmu_slot_remove_write_access().
4067 */
4068 lockdep_assert_held(&kvm->slots_lock);
4069 if (is_dirty)
4070 kvm_flush_remote_tlbs(kvm);
4071
4072 mutex_unlock(&kvm->slots_lock);
4073 return r;
4074 }
4075
4076 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4077 bool line_status)
4078 {
4079 if (!irqchip_in_kernel(kvm))
4080 return -ENXIO;
4081
4082 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4083 irq_event->irq, irq_event->level,
4084 line_status);
4085 return 0;
4086 }
4087
4088 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4089 struct kvm_enable_cap *cap)
4090 {
4091 int r;
4092
4093 if (cap->flags)
4094 return -EINVAL;
4095
4096 switch (cap->cap) {
4097 case KVM_CAP_DISABLE_QUIRKS:
4098 kvm->arch.disabled_quirks = cap->args[0];
4099 r = 0;
4100 break;
4101 case KVM_CAP_SPLIT_IRQCHIP: {
4102 mutex_lock(&kvm->lock);
4103 r = -EINVAL;
4104 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4105 goto split_irqchip_unlock;
4106 r = -EEXIST;
4107 if (irqchip_in_kernel(kvm))
4108 goto split_irqchip_unlock;
4109 if (kvm->created_vcpus)
4110 goto split_irqchip_unlock;
4111 r = kvm_setup_empty_irq_routing(kvm);
4112 if (r)
4113 goto split_irqchip_unlock;
4114 /* Pairs with irqchip_in_kernel. */
4115 smp_wmb();
4116 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4117 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4118 r = 0;
4119 split_irqchip_unlock:
4120 mutex_unlock(&kvm->lock);
4121 break;
4122 }
4123 case KVM_CAP_X2APIC_API:
4124 r = -EINVAL;
4125 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4126 break;
4127
4128 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4129 kvm->arch.x2apic_format = true;
4130 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4131 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4132
4133 r = 0;
4134 break;
4135 default:
4136 r = -EINVAL;
4137 break;
4138 }
4139 return r;
4140 }
4141
4142 long kvm_arch_vm_ioctl(struct file *filp,
4143 unsigned int ioctl, unsigned long arg)
4144 {
4145 struct kvm *kvm = filp->private_data;
4146 void __user *argp = (void __user *)arg;
4147 int r = -ENOTTY;
4148 /*
4149 * This union makes it completely explicit to gcc-3.x
4150 * that these two variables' stack usage should be
4151 * combined, not added together.
4152 */
4153 union {
4154 struct kvm_pit_state ps;
4155 struct kvm_pit_state2 ps2;
4156 struct kvm_pit_config pit_config;
4157 } u;
4158
4159 switch (ioctl) {
4160 case KVM_SET_TSS_ADDR:
4161 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4162 break;
4163 case KVM_SET_IDENTITY_MAP_ADDR: {
4164 u64 ident_addr;
4165
4166 mutex_lock(&kvm->lock);
4167 r = -EINVAL;
4168 if (kvm->created_vcpus)
4169 goto set_identity_unlock;
4170 r = -EFAULT;
4171 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4172 goto set_identity_unlock;
4173 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4174 set_identity_unlock:
4175 mutex_unlock(&kvm->lock);
4176 break;
4177 }
4178 case KVM_SET_NR_MMU_PAGES:
4179 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4180 break;
4181 case KVM_GET_NR_MMU_PAGES:
4182 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4183 break;
4184 case KVM_CREATE_IRQCHIP: {
4185 mutex_lock(&kvm->lock);
4186
4187 r = -EEXIST;
4188 if (irqchip_in_kernel(kvm))
4189 goto create_irqchip_unlock;
4190
4191 r = -EINVAL;
4192 if (kvm->created_vcpus)
4193 goto create_irqchip_unlock;
4194
4195 r = kvm_pic_init(kvm);
4196 if (r)
4197 goto create_irqchip_unlock;
4198
4199 r = kvm_ioapic_init(kvm);
4200 if (r) {
4201 kvm_pic_destroy(kvm);
4202 goto create_irqchip_unlock;
4203 }
4204
4205 r = kvm_setup_default_irq_routing(kvm);
4206 if (r) {
4207 kvm_ioapic_destroy(kvm);
4208 kvm_pic_destroy(kvm);
4209 goto create_irqchip_unlock;
4210 }
4211 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4212 smp_wmb();
4213 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4214 create_irqchip_unlock:
4215 mutex_unlock(&kvm->lock);
4216 break;
4217 }
4218 case KVM_CREATE_PIT:
4219 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4220 goto create_pit;
4221 case KVM_CREATE_PIT2:
4222 r = -EFAULT;
4223 if (copy_from_user(&u.pit_config, argp,
4224 sizeof(struct kvm_pit_config)))
4225 goto out;
4226 create_pit:
4227 mutex_lock(&kvm->lock);
4228 r = -EEXIST;
4229 if (kvm->arch.vpit)
4230 goto create_pit_unlock;
4231 r = -ENOMEM;
4232 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4233 if (kvm->arch.vpit)
4234 r = 0;
4235 create_pit_unlock:
4236 mutex_unlock(&kvm->lock);
4237 break;
4238 case KVM_GET_IRQCHIP: {
4239 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4240 struct kvm_irqchip *chip;
4241
4242 chip = memdup_user(argp, sizeof(*chip));
4243 if (IS_ERR(chip)) {
4244 r = PTR_ERR(chip);
4245 goto out;
4246 }
4247
4248 r = -ENXIO;
4249 if (!irqchip_kernel(kvm))
4250 goto get_irqchip_out;
4251 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4252 if (r)
4253 goto get_irqchip_out;
4254 r = -EFAULT;
4255 if (copy_to_user(argp, chip, sizeof *chip))
4256 goto get_irqchip_out;
4257 r = 0;
4258 get_irqchip_out:
4259 kfree(chip);
4260 break;
4261 }
4262 case KVM_SET_IRQCHIP: {
4263 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4264 struct kvm_irqchip *chip;
4265
4266 chip = memdup_user(argp, sizeof(*chip));
4267 if (IS_ERR(chip)) {
4268 r = PTR_ERR(chip);
4269 goto out;
4270 }
4271
4272 r = -ENXIO;
4273 if (!irqchip_kernel(kvm))
4274 goto set_irqchip_out;
4275 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4276 if (r)
4277 goto set_irqchip_out;
4278 r = 0;
4279 set_irqchip_out:
4280 kfree(chip);
4281 break;
4282 }
4283 case KVM_GET_PIT: {
4284 r = -EFAULT;
4285 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4286 goto out;
4287 r = -ENXIO;
4288 if (!kvm->arch.vpit)
4289 goto out;
4290 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4291 if (r)
4292 goto out;
4293 r = -EFAULT;
4294 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4295 goto out;
4296 r = 0;
4297 break;
4298 }
4299 case KVM_SET_PIT: {
4300 r = -EFAULT;
4301 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4302 goto out;
4303 r = -ENXIO;
4304 if (!kvm->arch.vpit)
4305 goto out;
4306 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4307 break;
4308 }
4309 case KVM_GET_PIT2: {
4310 r = -ENXIO;
4311 if (!kvm->arch.vpit)
4312 goto out;
4313 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4314 if (r)
4315 goto out;
4316 r = -EFAULT;
4317 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4318 goto out;
4319 r = 0;
4320 break;
4321 }
4322 case KVM_SET_PIT2: {
4323 r = -EFAULT;
4324 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4325 goto out;
4326 r = -ENXIO;
4327 if (!kvm->arch.vpit)
4328 goto out;
4329 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4330 break;
4331 }
4332 case KVM_REINJECT_CONTROL: {
4333 struct kvm_reinject_control control;
4334 r = -EFAULT;
4335 if (copy_from_user(&control, argp, sizeof(control)))
4336 goto out;
4337 r = kvm_vm_ioctl_reinject(kvm, &control);
4338 break;
4339 }
4340 case KVM_SET_BOOT_CPU_ID:
4341 r = 0;
4342 mutex_lock(&kvm->lock);
4343 if (kvm->created_vcpus)
4344 r = -EBUSY;
4345 else
4346 kvm->arch.bsp_vcpu_id = arg;
4347 mutex_unlock(&kvm->lock);
4348 break;
4349 case KVM_XEN_HVM_CONFIG: {
4350 struct kvm_xen_hvm_config xhc;
4351 r = -EFAULT;
4352 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4353 goto out;
4354 r = -EINVAL;
4355 if (xhc.flags)
4356 goto out;
4357 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4358 r = 0;
4359 break;
4360 }
4361 case KVM_SET_CLOCK: {
4362 struct kvm_clock_data user_ns;
4363 u64 now_ns;
4364
4365 r = -EFAULT;
4366 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4367 goto out;
4368
4369 r = -EINVAL;
4370 if (user_ns.flags)
4371 goto out;
4372
4373 r = 0;
4374 /*
4375 * TODO: userspace has to take care of races with VCPU_RUN, so
4376 * kvm_gen_update_masterclock() can be cut down to locked
4377 * pvclock_update_vm_gtod_copy().
4378 */
4379 kvm_gen_update_masterclock(kvm);
4380 now_ns = get_kvmclock_ns(kvm);
4381 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4382 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4383 break;
4384 }
4385 case KVM_GET_CLOCK: {
4386 struct kvm_clock_data user_ns;
4387 u64 now_ns;
4388
4389 now_ns = get_kvmclock_ns(kvm);
4390 user_ns.clock = now_ns;
4391 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4392 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4393
4394 r = -EFAULT;
4395 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4396 goto out;
4397 r = 0;
4398 break;
4399 }
4400 case KVM_ENABLE_CAP: {
4401 struct kvm_enable_cap cap;
4402
4403 r = -EFAULT;
4404 if (copy_from_user(&cap, argp, sizeof(cap)))
4405 goto out;
4406 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4407 break;
4408 }
4409 default:
4410 r = -ENOTTY;
4411 }
4412 out:
4413 return r;
4414 }
4415
4416 static void kvm_init_msr_list(void)
4417 {
4418 u32 dummy[2];
4419 unsigned i, j;
4420
4421 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4422 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4423 continue;
4424
4425 /*
4426 * Even MSRs that are valid in the host may not be exposed
4427 * to the guests in some cases.
4428 */
4429 switch (msrs_to_save[i]) {
4430 case MSR_IA32_BNDCFGS:
4431 if (!kvm_x86_ops->mpx_supported())
4432 continue;
4433 break;
4434 case MSR_TSC_AUX:
4435 if (!kvm_x86_ops->rdtscp_supported())
4436 continue;
4437 break;
4438 default:
4439 break;
4440 }
4441
4442 if (j < i)
4443 msrs_to_save[j] = msrs_to_save[i];
4444 j++;
4445 }
4446 num_msrs_to_save = j;
4447
4448 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4449 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4450 continue;
4451
4452 if (j < i)
4453 emulated_msrs[j] = emulated_msrs[i];
4454 j++;
4455 }
4456 num_emulated_msrs = j;
4457
4458 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4459 struct kvm_msr_entry msr;
4460
4461 msr.index = msr_based_features[i];
4462 if (kvm_get_msr_feature(&msr))
4463 continue;
4464
4465 if (j < i)
4466 msr_based_features[j] = msr_based_features[i];
4467 j++;
4468 }
4469 num_msr_based_features = j;
4470 }
4471
4472 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4473 const void *v)
4474 {
4475 int handled = 0;
4476 int n;
4477
4478 do {
4479 n = min(len, 8);
4480 if (!(lapic_in_kernel(vcpu) &&
4481 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4482 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4483 break;
4484 handled += n;
4485 addr += n;
4486 len -= n;
4487 v += n;
4488 } while (len);
4489
4490 return handled;
4491 }
4492
4493 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4494 {
4495 int handled = 0;
4496 int n;
4497
4498 do {
4499 n = min(len, 8);
4500 if (!(lapic_in_kernel(vcpu) &&
4501 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4502 addr, n, v))
4503 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4504 break;
4505 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4506 handled += n;
4507 addr += n;
4508 len -= n;
4509 v += n;
4510 } while (len);
4511
4512 return handled;
4513 }
4514
4515 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4516 struct kvm_segment *var, int seg)
4517 {
4518 kvm_x86_ops->set_segment(vcpu, var, seg);
4519 }
4520
4521 void kvm_get_segment(struct kvm_vcpu *vcpu,
4522 struct kvm_segment *var, int seg)
4523 {
4524 kvm_x86_ops->get_segment(vcpu, var, seg);
4525 }
4526
4527 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4528 struct x86_exception *exception)
4529 {
4530 gpa_t t_gpa;
4531
4532 BUG_ON(!mmu_is_nested(vcpu));
4533
4534 /* NPT walks are always user-walks */
4535 access |= PFERR_USER_MASK;
4536 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4537
4538 return t_gpa;
4539 }
4540
4541 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4542 struct x86_exception *exception)
4543 {
4544 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4545 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4546 }
4547
4548 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4549 struct x86_exception *exception)
4550 {
4551 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4552 access |= PFERR_FETCH_MASK;
4553 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4554 }
4555
4556 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4557 struct x86_exception *exception)
4558 {
4559 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4560 access |= PFERR_WRITE_MASK;
4561 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4562 }
4563
4564 /* uses this to access any guest's mapped memory without checking CPL */
4565 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4566 struct x86_exception *exception)
4567 {
4568 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4569 }
4570
4571 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4572 struct kvm_vcpu *vcpu, u32 access,
4573 struct x86_exception *exception)
4574 {
4575 void *data = val;
4576 int r = X86EMUL_CONTINUE;
4577
4578 while (bytes) {
4579 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4580 exception);
4581 unsigned offset = addr & (PAGE_SIZE-1);
4582 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4583 int ret;
4584
4585 if (gpa == UNMAPPED_GVA)
4586 return X86EMUL_PROPAGATE_FAULT;
4587 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4588 offset, toread);
4589 if (ret < 0) {
4590 r = X86EMUL_IO_NEEDED;
4591 goto out;
4592 }
4593
4594 bytes -= toread;
4595 data += toread;
4596 addr += toread;
4597 }
4598 out:
4599 return r;
4600 }
4601
4602 /* used for instruction fetching */
4603 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4604 gva_t addr, void *val, unsigned int bytes,
4605 struct x86_exception *exception)
4606 {
4607 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4608 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4609 unsigned offset;
4610 int ret;
4611
4612 /* Inline kvm_read_guest_virt_helper for speed. */
4613 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4614 exception);
4615 if (unlikely(gpa == UNMAPPED_GVA))
4616 return X86EMUL_PROPAGATE_FAULT;
4617
4618 offset = addr & (PAGE_SIZE-1);
4619 if (WARN_ON(offset + bytes > PAGE_SIZE))
4620 bytes = (unsigned)PAGE_SIZE - offset;
4621 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4622 offset, bytes);
4623 if (unlikely(ret < 0))
4624 return X86EMUL_IO_NEEDED;
4625
4626 return X86EMUL_CONTINUE;
4627 }
4628
4629 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
4630 gva_t addr, void *val, unsigned int bytes,
4631 struct x86_exception *exception)
4632 {
4633 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4634
4635 /*
4636 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
4637 * is returned, but our callers are not ready for that and they blindly
4638 * call kvm_inject_page_fault. Ensure that they at least do not leak
4639 * uninitialized kernel stack memory into cr2 and error code.
4640 */
4641 memset(exception, 0, sizeof(*exception));
4642 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4643 exception);
4644 }
4645 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4646
4647 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4648 gva_t addr, void *val, unsigned int bytes,
4649 struct x86_exception *exception, bool system)
4650 {
4651 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4652 u32 access = 0;
4653
4654 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4655 access |= PFERR_USER_MASK;
4656
4657 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
4658 }
4659
4660 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4661 unsigned long addr, void *val, unsigned int bytes)
4662 {
4663 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4664 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4665
4666 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4667 }
4668
4669 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4670 struct kvm_vcpu *vcpu, u32 access,
4671 struct x86_exception *exception)
4672 {
4673 void *data = val;
4674 int r = X86EMUL_CONTINUE;
4675
4676 /* kvm_write_guest_virt_system can pull in tons of pages. */
4677 vcpu->arch.l1tf_flush_l1d = true;
4678
4679 while (bytes) {
4680 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4681 access,
4682 exception);
4683 unsigned offset = addr & (PAGE_SIZE-1);
4684 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4685 int ret;
4686
4687 if (gpa == UNMAPPED_GVA)
4688 return X86EMUL_PROPAGATE_FAULT;
4689 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4690 if (ret < 0) {
4691 r = X86EMUL_IO_NEEDED;
4692 goto out;
4693 }
4694
4695 bytes -= towrite;
4696 data += towrite;
4697 addr += towrite;
4698 }
4699 out:
4700 return r;
4701 }
4702
4703 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
4704 unsigned int bytes, struct x86_exception *exception,
4705 bool system)
4706 {
4707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4708 u32 access = PFERR_WRITE_MASK;
4709
4710 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4711 access |= PFERR_USER_MASK;
4712
4713 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4714 access, exception);
4715 }
4716
4717 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4718 unsigned int bytes, struct x86_exception *exception)
4719 {
4720 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4721 PFERR_WRITE_MASK, exception);
4722 }
4723 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4724
4725 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4726 gpa_t gpa, bool write)
4727 {
4728 /* For APIC access vmexit */
4729 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4730 return 1;
4731
4732 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4733 trace_vcpu_match_mmio(gva, gpa, write, true);
4734 return 1;
4735 }
4736
4737 return 0;
4738 }
4739
4740 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4741 gpa_t *gpa, struct x86_exception *exception,
4742 bool write)
4743 {
4744 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4745 | (write ? PFERR_WRITE_MASK : 0);
4746
4747 /*
4748 * currently PKRU is only applied to ept enabled guest so
4749 * there is no pkey in EPT page table for L1 guest or EPT
4750 * shadow page table for L2 guest.
4751 */
4752 if (vcpu_match_mmio_gva(vcpu, gva)
4753 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4754 vcpu->arch.access, 0, access)) {
4755 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4756 (gva & (PAGE_SIZE - 1));
4757 trace_vcpu_match_mmio(gva, *gpa, write, false);
4758 return 1;
4759 }
4760
4761 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4762
4763 if (*gpa == UNMAPPED_GVA)
4764 return -1;
4765
4766 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4767 }
4768
4769 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4770 const void *val, int bytes)
4771 {
4772 int ret;
4773
4774 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4775 if (ret < 0)
4776 return 0;
4777 kvm_page_track_write(vcpu, gpa, val, bytes);
4778 return 1;
4779 }
4780
4781 struct read_write_emulator_ops {
4782 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4783 int bytes);
4784 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4785 void *val, int bytes);
4786 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4787 int bytes, void *val);
4788 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4789 void *val, int bytes);
4790 bool write;
4791 };
4792
4793 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4794 {
4795 if (vcpu->mmio_read_completed) {
4796 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4797 vcpu->mmio_fragments[0].gpa, val);
4798 vcpu->mmio_read_completed = 0;
4799 return 1;
4800 }
4801
4802 return 0;
4803 }
4804
4805 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4806 void *val, int bytes)
4807 {
4808 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4809 }
4810
4811 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4812 void *val, int bytes)
4813 {
4814 return emulator_write_phys(vcpu, gpa, val, bytes);
4815 }
4816
4817 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4818 {
4819 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4820 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4821 }
4822
4823 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4824 void *val, int bytes)
4825 {
4826 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4827 return X86EMUL_IO_NEEDED;
4828 }
4829
4830 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4831 void *val, int bytes)
4832 {
4833 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4834
4835 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4836 return X86EMUL_CONTINUE;
4837 }
4838
4839 static const struct read_write_emulator_ops read_emultor = {
4840 .read_write_prepare = read_prepare,
4841 .read_write_emulate = read_emulate,
4842 .read_write_mmio = vcpu_mmio_read,
4843 .read_write_exit_mmio = read_exit_mmio,
4844 };
4845
4846 static const struct read_write_emulator_ops write_emultor = {
4847 .read_write_emulate = write_emulate,
4848 .read_write_mmio = write_mmio,
4849 .read_write_exit_mmio = write_exit_mmio,
4850 .write = true,
4851 };
4852
4853 static int emulator_read_write_onepage(unsigned long addr, void *val,
4854 unsigned int bytes,
4855 struct x86_exception *exception,
4856 struct kvm_vcpu *vcpu,
4857 const struct read_write_emulator_ops *ops)
4858 {
4859 gpa_t gpa;
4860 int handled, ret;
4861 bool write = ops->write;
4862 struct kvm_mmio_fragment *frag;
4863 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4864
4865 /*
4866 * If the exit was due to a NPF we may already have a GPA.
4867 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4868 * Note, this cannot be used on string operations since string
4869 * operation using rep will only have the initial GPA from the NPF
4870 * occurred.
4871 */
4872 if (vcpu->arch.gpa_available &&
4873 emulator_can_use_gpa(ctxt) &&
4874 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4875 gpa = vcpu->arch.gpa_val;
4876 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4877 } else {
4878 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4879 if (ret < 0)
4880 return X86EMUL_PROPAGATE_FAULT;
4881 }
4882
4883 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
4884 return X86EMUL_CONTINUE;
4885
4886 /*
4887 * Is this MMIO handled locally?
4888 */
4889 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4890 if (handled == bytes)
4891 return X86EMUL_CONTINUE;
4892
4893 gpa += handled;
4894 bytes -= handled;
4895 val += handled;
4896
4897 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4898 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4899 frag->gpa = gpa;
4900 frag->data = val;
4901 frag->len = bytes;
4902 return X86EMUL_CONTINUE;
4903 }
4904
4905 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4906 unsigned long addr,
4907 void *val, unsigned int bytes,
4908 struct x86_exception *exception,
4909 const struct read_write_emulator_ops *ops)
4910 {
4911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4912 gpa_t gpa;
4913 int rc;
4914
4915 if (ops->read_write_prepare &&
4916 ops->read_write_prepare(vcpu, val, bytes))
4917 return X86EMUL_CONTINUE;
4918
4919 vcpu->mmio_nr_fragments = 0;
4920
4921 /* Crossing a page boundary? */
4922 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4923 int now;
4924
4925 now = -addr & ~PAGE_MASK;
4926 rc = emulator_read_write_onepage(addr, val, now, exception,
4927 vcpu, ops);
4928
4929 if (rc != X86EMUL_CONTINUE)
4930 return rc;
4931 addr += now;
4932 if (ctxt->mode != X86EMUL_MODE_PROT64)
4933 addr = (u32)addr;
4934 val += now;
4935 bytes -= now;
4936 }
4937
4938 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4939 vcpu, ops);
4940 if (rc != X86EMUL_CONTINUE)
4941 return rc;
4942
4943 if (!vcpu->mmio_nr_fragments)
4944 return rc;
4945
4946 gpa = vcpu->mmio_fragments[0].gpa;
4947
4948 vcpu->mmio_needed = 1;
4949 vcpu->mmio_cur_fragment = 0;
4950
4951 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4952 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4953 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4954 vcpu->run->mmio.phys_addr = gpa;
4955
4956 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4957 }
4958
4959 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4960 unsigned long addr,
4961 void *val,
4962 unsigned int bytes,
4963 struct x86_exception *exception)
4964 {
4965 return emulator_read_write(ctxt, addr, val, bytes,
4966 exception, &read_emultor);
4967 }
4968
4969 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4970 unsigned long addr,
4971 const void *val,
4972 unsigned int bytes,
4973 struct x86_exception *exception)
4974 {
4975 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4976 exception, &write_emultor);
4977 }
4978
4979 #define CMPXCHG_TYPE(t, ptr, old, new) \
4980 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4981
4982 #ifdef CONFIG_X86_64
4983 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4984 #else
4985 # define CMPXCHG64(ptr, old, new) \
4986 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4987 #endif
4988
4989 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4990 unsigned long addr,
4991 const void *old,
4992 const void *new,
4993 unsigned int bytes,
4994 struct x86_exception *exception)
4995 {
4996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4997 gpa_t gpa;
4998 struct page *page;
4999 char *kaddr;
5000 bool exchanged;
5001
5002 /* guests cmpxchg8b have to be emulated atomically */
5003 if (bytes > 8 || (bytes & (bytes - 1)))
5004 goto emul_write;
5005
5006 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5007
5008 if (gpa == UNMAPPED_GVA ||
5009 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5010 goto emul_write;
5011
5012 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5013 goto emul_write;
5014
5015 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5016 if (is_error_page(page))
5017 goto emul_write;
5018
5019 kaddr = kmap_atomic(page);
5020 kaddr += offset_in_page(gpa);
5021 switch (bytes) {
5022 case 1:
5023 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5024 break;
5025 case 2:
5026 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5027 break;
5028 case 4:
5029 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5030 break;
5031 case 8:
5032 exchanged = CMPXCHG64(kaddr, old, new);
5033 break;
5034 default:
5035 BUG();
5036 }
5037 kunmap_atomic(kaddr);
5038 kvm_release_page_dirty(page);
5039
5040 if (!exchanged)
5041 return X86EMUL_CMPXCHG_FAILED;
5042
5043 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5044 kvm_page_track_write(vcpu, gpa, new, bytes);
5045
5046 return X86EMUL_CONTINUE;
5047
5048 emul_write:
5049 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5050
5051 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5052 }
5053
5054 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5055 {
5056 int r = 0, i;
5057
5058 for (i = 0; i < vcpu->arch.pio.count; i++) {
5059 if (vcpu->arch.pio.in)
5060 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5061 vcpu->arch.pio.size, pd);
5062 else
5063 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5064 vcpu->arch.pio.port, vcpu->arch.pio.size,
5065 pd);
5066 if (r)
5067 break;
5068 pd += vcpu->arch.pio.size;
5069 }
5070 return r;
5071 }
5072
5073 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5074 unsigned short port, void *val,
5075 unsigned int count, bool in)
5076 {
5077 vcpu->arch.pio.port = port;
5078 vcpu->arch.pio.in = in;
5079 vcpu->arch.pio.count = count;
5080 vcpu->arch.pio.size = size;
5081
5082 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5083 vcpu->arch.pio.count = 0;
5084 return 1;
5085 }
5086
5087 vcpu->run->exit_reason = KVM_EXIT_IO;
5088 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5089 vcpu->run->io.size = size;
5090 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5091 vcpu->run->io.count = count;
5092 vcpu->run->io.port = port;
5093
5094 return 0;
5095 }
5096
5097 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5098 int size, unsigned short port, void *val,
5099 unsigned int count)
5100 {
5101 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5102 int ret;
5103
5104 if (vcpu->arch.pio.count)
5105 goto data_avail;
5106
5107 memset(vcpu->arch.pio_data, 0, size * count);
5108
5109 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5110 if (ret) {
5111 data_avail:
5112 memcpy(val, vcpu->arch.pio_data, size * count);
5113 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5114 vcpu->arch.pio.count = 0;
5115 return 1;
5116 }
5117
5118 return 0;
5119 }
5120
5121 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5122 int size, unsigned short port,
5123 const void *val, unsigned int count)
5124 {
5125 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5126
5127 memcpy(vcpu->arch.pio_data, val, size * count);
5128 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5129 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5130 }
5131
5132 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5133 {
5134 return kvm_x86_ops->get_segment_base(vcpu, seg);
5135 }
5136
5137 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5138 {
5139 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5140 }
5141
5142 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5143 {
5144 if (!need_emulate_wbinvd(vcpu))
5145 return X86EMUL_CONTINUE;
5146
5147 if (kvm_x86_ops->has_wbinvd_exit()) {
5148 int cpu = get_cpu();
5149
5150 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5151 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5152 wbinvd_ipi, NULL, 1);
5153 put_cpu();
5154 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5155 } else
5156 wbinvd();
5157 return X86EMUL_CONTINUE;
5158 }
5159
5160 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5161 {
5162 kvm_emulate_wbinvd_noskip(vcpu);
5163 return kvm_skip_emulated_instruction(vcpu);
5164 }
5165 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5166
5167
5168
5169 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5170 {
5171 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5172 }
5173
5174 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5175 unsigned long *dest)
5176 {
5177 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5178 }
5179
5180 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5181 unsigned long value)
5182 {
5183
5184 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5185 }
5186
5187 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5188 {
5189 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5190 }
5191
5192 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5193 {
5194 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5195 unsigned long value;
5196
5197 switch (cr) {
5198 case 0:
5199 value = kvm_read_cr0(vcpu);
5200 break;
5201 case 2:
5202 value = vcpu->arch.cr2;
5203 break;
5204 case 3:
5205 value = kvm_read_cr3(vcpu);
5206 break;
5207 case 4:
5208 value = kvm_read_cr4(vcpu);
5209 break;
5210 case 8:
5211 value = kvm_get_cr8(vcpu);
5212 break;
5213 default:
5214 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5215 return 0;
5216 }
5217
5218 return value;
5219 }
5220
5221 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5222 {
5223 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5224 int res = 0;
5225
5226 switch (cr) {
5227 case 0:
5228 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5229 break;
5230 case 2:
5231 vcpu->arch.cr2 = val;
5232 break;
5233 case 3:
5234 res = kvm_set_cr3(vcpu, val);
5235 break;
5236 case 4:
5237 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5238 break;
5239 case 8:
5240 res = kvm_set_cr8(vcpu, val);
5241 break;
5242 default:
5243 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5244 res = -1;
5245 }
5246
5247 return res;
5248 }
5249
5250 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5251 {
5252 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5253 }
5254
5255 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5256 {
5257 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5258 }
5259
5260 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5261 {
5262 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5263 }
5264
5265 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5266 {
5267 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5268 }
5269
5270 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5271 {
5272 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5273 }
5274
5275 static unsigned long emulator_get_cached_segment_base(
5276 struct x86_emulate_ctxt *ctxt, int seg)
5277 {
5278 return get_segment_base(emul_to_vcpu(ctxt), seg);
5279 }
5280
5281 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5282 struct desc_struct *desc, u32 *base3,
5283 int seg)
5284 {
5285 struct kvm_segment var;
5286
5287 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5288 *selector = var.selector;
5289
5290 if (var.unusable) {
5291 memset(desc, 0, sizeof(*desc));
5292 if (base3)
5293 *base3 = 0;
5294 return false;
5295 }
5296
5297 if (var.g)
5298 var.limit >>= 12;
5299 set_desc_limit(desc, var.limit);
5300 set_desc_base(desc, (unsigned long)var.base);
5301 #ifdef CONFIG_X86_64
5302 if (base3)
5303 *base3 = var.base >> 32;
5304 #endif
5305 desc->type = var.type;
5306 desc->s = var.s;
5307 desc->dpl = var.dpl;
5308 desc->p = var.present;
5309 desc->avl = var.avl;
5310 desc->l = var.l;
5311 desc->d = var.db;
5312 desc->g = var.g;
5313
5314 return true;
5315 }
5316
5317 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5318 struct desc_struct *desc, u32 base3,
5319 int seg)
5320 {
5321 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5322 struct kvm_segment var;
5323
5324 var.selector = selector;
5325 var.base = get_desc_base(desc);
5326 #ifdef CONFIG_X86_64
5327 var.base |= ((u64)base3) << 32;
5328 #endif
5329 var.limit = get_desc_limit(desc);
5330 if (desc->g)
5331 var.limit = (var.limit << 12) | 0xfff;
5332 var.type = desc->type;
5333 var.dpl = desc->dpl;
5334 var.db = desc->d;
5335 var.s = desc->s;
5336 var.l = desc->l;
5337 var.g = desc->g;
5338 var.avl = desc->avl;
5339 var.present = desc->p;
5340 var.unusable = !var.present;
5341 var.padding = 0;
5342
5343 kvm_set_segment(vcpu, &var, seg);
5344 return;
5345 }
5346
5347 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5348 u32 msr_index, u64 *pdata)
5349 {
5350 struct msr_data msr;
5351 int r;
5352
5353 msr.index = msr_index;
5354 msr.host_initiated = false;
5355 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5356 if (r)
5357 return r;
5358
5359 *pdata = msr.data;
5360 return 0;
5361 }
5362
5363 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5364 u32 msr_index, u64 data)
5365 {
5366 struct msr_data msr;
5367
5368 msr.data = data;
5369 msr.index = msr_index;
5370 msr.host_initiated = false;
5371 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5372 }
5373
5374 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5375 {
5376 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5377
5378 return vcpu->arch.smbase;
5379 }
5380
5381 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5382 {
5383 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5384
5385 vcpu->arch.smbase = smbase;
5386 }
5387
5388 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5389 u32 pmc)
5390 {
5391 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5392 }
5393
5394 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5395 u32 pmc, u64 *pdata)
5396 {
5397 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5398 }
5399
5400 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5401 {
5402 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5403 }
5404
5405 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5406 struct x86_instruction_info *info,
5407 enum x86_intercept_stage stage)
5408 {
5409 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5410 }
5411
5412 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5413 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5414 {
5415 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5416 }
5417
5418 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5419 {
5420 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5421 }
5422
5423 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5424 {
5425 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5426 }
5427
5428 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5429 {
5430 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5431 }
5432
5433 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5434 {
5435 return emul_to_vcpu(ctxt)->arch.hflags;
5436 }
5437
5438 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5439 {
5440 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5441 }
5442
5443 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5444 {
5445 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5446 }
5447
5448 static const struct x86_emulate_ops emulate_ops = {
5449 .read_gpr = emulator_read_gpr,
5450 .write_gpr = emulator_write_gpr,
5451 .read_std = emulator_read_std,
5452 .write_std = emulator_write_std,
5453 .read_phys = kvm_read_guest_phys_system,
5454 .fetch = kvm_fetch_guest_virt,
5455 .read_emulated = emulator_read_emulated,
5456 .write_emulated = emulator_write_emulated,
5457 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5458 .invlpg = emulator_invlpg,
5459 .pio_in_emulated = emulator_pio_in_emulated,
5460 .pio_out_emulated = emulator_pio_out_emulated,
5461 .get_segment = emulator_get_segment,
5462 .set_segment = emulator_set_segment,
5463 .get_cached_segment_base = emulator_get_cached_segment_base,
5464 .get_gdt = emulator_get_gdt,
5465 .get_idt = emulator_get_idt,
5466 .set_gdt = emulator_set_gdt,
5467 .set_idt = emulator_set_idt,
5468 .get_cr = emulator_get_cr,
5469 .set_cr = emulator_set_cr,
5470 .cpl = emulator_get_cpl,
5471 .get_dr = emulator_get_dr,
5472 .set_dr = emulator_set_dr,
5473 .get_smbase = emulator_get_smbase,
5474 .set_smbase = emulator_set_smbase,
5475 .set_msr = emulator_set_msr,
5476 .get_msr = emulator_get_msr,
5477 .check_pmc = emulator_check_pmc,
5478 .read_pmc = emulator_read_pmc,
5479 .halt = emulator_halt,
5480 .wbinvd = emulator_wbinvd,
5481 .fix_hypercall = emulator_fix_hypercall,
5482 .intercept = emulator_intercept,
5483 .get_cpuid = emulator_get_cpuid,
5484 .set_nmi_mask = emulator_set_nmi_mask,
5485 .get_hflags = emulator_get_hflags,
5486 .set_hflags = emulator_set_hflags,
5487 .pre_leave_smm = emulator_pre_leave_smm,
5488 };
5489
5490 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5491 {
5492 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5493 /*
5494 * an sti; sti; sequence only disable interrupts for the first
5495 * instruction. So, if the last instruction, be it emulated or
5496 * not, left the system with the INT_STI flag enabled, it
5497 * means that the last instruction is an sti. We should not
5498 * leave the flag on in this case. The same goes for mov ss
5499 */
5500 if (int_shadow & mask)
5501 mask = 0;
5502 if (unlikely(int_shadow || mask)) {
5503 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5504 if (!mask)
5505 kvm_make_request(KVM_REQ_EVENT, vcpu);
5506 }
5507 }
5508
5509 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5510 {
5511 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5512 if (ctxt->exception.vector == PF_VECTOR)
5513 return kvm_propagate_fault(vcpu, &ctxt->exception);
5514
5515 if (ctxt->exception.error_code_valid)
5516 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5517 ctxt->exception.error_code);
5518 else
5519 kvm_queue_exception(vcpu, ctxt->exception.vector);
5520 return false;
5521 }
5522
5523 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5524 {
5525 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5526 int cs_db, cs_l;
5527
5528 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5529
5530 ctxt->eflags = kvm_get_rflags(vcpu);
5531 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5532
5533 ctxt->eip = kvm_rip_read(vcpu);
5534 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5535 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5536 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5537 cs_db ? X86EMUL_MODE_PROT32 :
5538 X86EMUL_MODE_PROT16;
5539 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5540 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5541 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5542
5543 init_decode_cache(ctxt);
5544 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5545 }
5546
5547 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5548 {
5549 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5550 int ret;
5551
5552 init_emulate_ctxt(vcpu);
5553
5554 ctxt->op_bytes = 2;
5555 ctxt->ad_bytes = 2;
5556 ctxt->_eip = ctxt->eip + inc_eip;
5557 ret = emulate_int_real(ctxt, irq);
5558
5559 if (ret != X86EMUL_CONTINUE)
5560 return EMULATE_FAIL;
5561
5562 ctxt->eip = ctxt->_eip;
5563 kvm_rip_write(vcpu, ctxt->eip);
5564 kvm_set_rflags(vcpu, ctxt->eflags);
5565
5566 if (irq == NMI_VECTOR)
5567 vcpu->arch.nmi_pending = 0;
5568 else
5569 vcpu->arch.interrupt.pending = false;
5570
5571 return EMULATE_DONE;
5572 }
5573 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5574
5575 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5576 {
5577 int r = EMULATE_DONE;
5578
5579 ++vcpu->stat.insn_emulation_fail;
5580 trace_kvm_emulate_insn_failed(vcpu);
5581 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5582 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5583 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5584 vcpu->run->internal.ndata = 0;
5585 r = EMULATE_USER_EXIT;
5586 }
5587 kvm_queue_exception(vcpu, UD_VECTOR);
5588
5589 return r;
5590 }
5591
5592 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5593 bool write_fault_to_shadow_pgtable,
5594 int emulation_type)
5595 {
5596 gpa_t gpa = cr2;
5597 kvm_pfn_t pfn;
5598
5599 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5600 return false;
5601
5602 if (!vcpu->arch.mmu.direct_map) {
5603 /*
5604 * Write permission should be allowed since only
5605 * write access need to be emulated.
5606 */
5607 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5608
5609 /*
5610 * If the mapping is invalid in guest, let cpu retry
5611 * it to generate fault.
5612 */
5613 if (gpa == UNMAPPED_GVA)
5614 return true;
5615 }
5616
5617 /*
5618 * Do not retry the unhandleable instruction if it faults on the
5619 * readonly host memory, otherwise it will goto a infinite loop:
5620 * retry instruction -> write #PF -> emulation fail -> retry
5621 * instruction -> ...
5622 */
5623 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5624
5625 /*
5626 * If the instruction failed on the error pfn, it can not be fixed,
5627 * report the error to userspace.
5628 */
5629 if (is_error_noslot_pfn(pfn))
5630 return false;
5631
5632 kvm_release_pfn_clean(pfn);
5633
5634 /* The instructions are well-emulated on direct mmu. */
5635 if (vcpu->arch.mmu.direct_map) {
5636 unsigned int indirect_shadow_pages;
5637
5638 spin_lock(&vcpu->kvm->mmu_lock);
5639 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5640 spin_unlock(&vcpu->kvm->mmu_lock);
5641
5642 if (indirect_shadow_pages)
5643 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5644
5645 return true;
5646 }
5647
5648 /*
5649 * if emulation was due to access to shadowed page table
5650 * and it failed try to unshadow page and re-enter the
5651 * guest to let CPU execute the instruction.
5652 */
5653 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5654
5655 /*
5656 * If the access faults on its page table, it can not
5657 * be fixed by unprotecting shadow page and it should
5658 * be reported to userspace.
5659 */
5660 return !write_fault_to_shadow_pgtable;
5661 }
5662
5663 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5664 unsigned long cr2, int emulation_type)
5665 {
5666 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5667 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5668
5669 last_retry_eip = vcpu->arch.last_retry_eip;
5670 last_retry_addr = vcpu->arch.last_retry_addr;
5671
5672 /*
5673 * If the emulation is caused by #PF and it is non-page_table
5674 * writing instruction, it means the VM-EXIT is caused by shadow
5675 * page protected, we can zap the shadow page and retry this
5676 * instruction directly.
5677 *
5678 * Note: if the guest uses a non-page-table modifying instruction
5679 * on the PDE that points to the instruction, then we will unmap
5680 * the instruction and go to an infinite loop. So, we cache the
5681 * last retried eip and the last fault address, if we meet the eip
5682 * and the address again, we can break out of the potential infinite
5683 * loop.
5684 */
5685 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5686
5687 if (!(emulation_type & EMULTYPE_RETRY))
5688 return false;
5689
5690 if (x86_page_table_writing_insn(ctxt))
5691 return false;
5692
5693 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5694 return false;
5695
5696 vcpu->arch.last_retry_eip = ctxt->eip;
5697 vcpu->arch.last_retry_addr = cr2;
5698
5699 if (!vcpu->arch.mmu.direct_map)
5700 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5701
5702 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5703
5704 return true;
5705 }
5706
5707 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5708 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5709
5710 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5711 {
5712 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5713 /* This is a good place to trace that we are exiting SMM. */
5714 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5715
5716 /* Process a latched INIT or SMI, if any. */
5717 kvm_make_request(KVM_REQ_EVENT, vcpu);
5718 }
5719
5720 kvm_mmu_reset_context(vcpu);
5721 }
5722
5723 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5724 {
5725 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5726
5727 vcpu->arch.hflags = emul_flags;
5728
5729 if (changed & HF_SMM_MASK)
5730 kvm_smm_changed(vcpu);
5731 }
5732
5733 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5734 unsigned long *db)
5735 {
5736 u32 dr6 = 0;
5737 int i;
5738 u32 enable, rwlen;
5739
5740 enable = dr7;
5741 rwlen = dr7 >> 16;
5742 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5743 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5744 dr6 |= (1 << i);
5745 return dr6;
5746 }
5747
5748 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5749 {
5750 struct kvm_run *kvm_run = vcpu->run;
5751
5752 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5753 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5754 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5755 kvm_run->debug.arch.exception = DB_VECTOR;
5756 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5757 *r = EMULATE_USER_EXIT;
5758 } else {
5759 /*
5760 * "Certain debug exceptions may clear bit 0-3. The
5761 * remaining contents of the DR6 register are never
5762 * cleared by the processor".
5763 */
5764 vcpu->arch.dr6 &= ~15;
5765 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5766 kvm_queue_exception(vcpu, DB_VECTOR);
5767 }
5768 }
5769
5770 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5771 {
5772 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5773 int r = EMULATE_DONE;
5774
5775 kvm_x86_ops->skip_emulated_instruction(vcpu);
5776
5777 /*
5778 * rflags is the old, "raw" value of the flags. The new value has
5779 * not been saved yet.
5780 *
5781 * This is correct even for TF set by the guest, because "the
5782 * processor will not generate this exception after the instruction
5783 * that sets the TF flag".
5784 */
5785 if (unlikely(rflags & X86_EFLAGS_TF))
5786 kvm_vcpu_do_singlestep(vcpu, &r);
5787 return r == EMULATE_DONE;
5788 }
5789 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5790
5791 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5792 {
5793 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5794 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5795 struct kvm_run *kvm_run = vcpu->run;
5796 unsigned long eip = kvm_get_linear_rip(vcpu);
5797 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5798 vcpu->arch.guest_debug_dr7,
5799 vcpu->arch.eff_db);
5800
5801 if (dr6 != 0) {
5802 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5803 kvm_run->debug.arch.pc = eip;
5804 kvm_run->debug.arch.exception = DB_VECTOR;
5805 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5806 *r = EMULATE_USER_EXIT;
5807 return true;
5808 }
5809 }
5810
5811 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5812 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5813 unsigned long eip = kvm_get_linear_rip(vcpu);
5814 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5815 vcpu->arch.dr7,
5816 vcpu->arch.db);
5817
5818 if (dr6 != 0) {
5819 vcpu->arch.dr6 &= ~15;
5820 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5821 kvm_queue_exception(vcpu, DB_VECTOR);
5822 *r = EMULATE_DONE;
5823 return true;
5824 }
5825 }
5826
5827 return false;
5828 }
5829
5830 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5831 unsigned long cr2,
5832 int emulation_type,
5833 void *insn,
5834 int insn_len)
5835 {
5836 int r;
5837 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5838 bool writeback = true;
5839 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5840
5841 vcpu->arch.l1tf_flush_l1d = true;
5842
5843 /*
5844 * Clear write_fault_to_shadow_pgtable here to ensure it is
5845 * never reused.
5846 */
5847 vcpu->arch.write_fault_to_shadow_pgtable = false;
5848 kvm_clear_exception_queue(vcpu);
5849
5850 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5851 init_emulate_ctxt(vcpu);
5852
5853 /*
5854 * We will reenter on the same instruction since
5855 * we do not set complete_userspace_io. This does not
5856 * handle watchpoints yet, those would be handled in
5857 * the emulate_ops.
5858 */
5859 if (!(emulation_type & EMULTYPE_SKIP) &&
5860 kvm_vcpu_check_breakpoint(vcpu, &r))
5861 return r;
5862
5863 ctxt->interruptibility = 0;
5864 ctxt->have_exception = false;
5865 ctxt->exception.vector = -1;
5866 ctxt->perm_ok = false;
5867
5868 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5869
5870 r = x86_decode_insn(ctxt, insn, insn_len);
5871
5872 trace_kvm_emulate_insn_start(vcpu);
5873 ++vcpu->stat.insn_emulation;
5874 if (r != EMULATION_OK) {
5875 if (emulation_type & EMULTYPE_TRAP_UD)
5876 return EMULATE_FAIL;
5877 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5878 emulation_type))
5879 return EMULATE_DONE;
5880 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5881 return EMULATE_DONE;
5882 if (emulation_type & EMULTYPE_SKIP)
5883 return EMULATE_FAIL;
5884 return handle_emulation_failure(vcpu);
5885 }
5886 }
5887
5888 if (emulation_type & EMULTYPE_SKIP) {
5889 kvm_rip_write(vcpu, ctxt->_eip);
5890 if (ctxt->eflags & X86_EFLAGS_RF)
5891 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5892 return EMULATE_DONE;
5893 }
5894
5895 if (retry_instruction(ctxt, cr2, emulation_type))
5896 return EMULATE_DONE;
5897
5898 /* this is needed for vmware backdoor interface to work since it
5899 changes registers values during IO operation */
5900 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5901 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5902 emulator_invalidate_register_cache(ctxt);
5903 }
5904
5905 restart:
5906 /* Save the faulting GPA (cr2) in the address field */
5907 ctxt->exception.address = cr2;
5908
5909 r = x86_emulate_insn(ctxt);
5910
5911 if (r == EMULATION_INTERCEPTED)
5912 return EMULATE_DONE;
5913
5914 if (r == EMULATION_FAILED) {
5915 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5916 emulation_type))
5917 return EMULATE_DONE;
5918
5919 return handle_emulation_failure(vcpu);
5920 }
5921
5922 if (ctxt->have_exception) {
5923 r = EMULATE_DONE;
5924 if (inject_emulated_exception(vcpu))
5925 return r;
5926 } else if (vcpu->arch.pio.count) {
5927 if (!vcpu->arch.pio.in) {
5928 /* FIXME: return into emulator if single-stepping. */
5929 vcpu->arch.pio.count = 0;
5930 } else {
5931 writeback = false;
5932 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5933 }
5934 r = EMULATE_USER_EXIT;
5935 } else if (vcpu->mmio_needed) {
5936 if (!vcpu->mmio_is_write)
5937 writeback = false;
5938 r = EMULATE_USER_EXIT;
5939 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5940 } else if (r == EMULATION_RESTART)
5941 goto restart;
5942 else
5943 r = EMULATE_DONE;
5944
5945 if (writeback) {
5946 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5947 toggle_interruptibility(vcpu, ctxt->interruptibility);
5948 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5949 kvm_rip_write(vcpu, ctxt->eip);
5950 if (r == EMULATE_DONE &&
5951 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5952 kvm_vcpu_do_singlestep(vcpu, &r);
5953 if (!ctxt->have_exception ||
5954 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5955 __kvm_set_rflags(vcpu, ctxt->eflags);
5956
5957 /*
5958 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5959 * do nothing, and it will be requested again as soon as
5960 * the shadow expires. But we still need to check here,
5961 * because POPF has no interrupt shadow.
5962 */
5963 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5964 kvm_make_request(KVM_REQ_EVENT, vcpu);
5965 } else
5966 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5967
5968 return r;
5969 }
5970 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5971
5972 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5973 {
5974 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5975 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5976 size, port, &val, 1);
5977 /* do not return to emulator after return from userspace */
5978 vcpu->arch.pio.count = 0;
5979 return ret;
5980 }
5981 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5982
5983 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5984 {
5985 unsigned long val;
5986
5987 /* We should only ever be called with arch.pio.count equal to 1 */
5988 BUG_ON(vcpu->arch.pio.count != 1);
5989
5990 /* For size less than 4 we merge, else we zero extend */
5991 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5992 : 0;
5993
5994 /*
5995 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5996 * the copy and tracing
5997 */
5998 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5999 vcpu->arch.pio.port, &val, 1);
6000 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6001
6002 return 1;
6003 }
6004
6005 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6006 {
6007 unsigned long val;
6008 int ret;
6009
6010 /* For size less than 4 we merge, else we zero extend */
6011 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6012
6013 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6014 &val, 1);
6015 if (ret) {
6016 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6017 return ret;
6018 }
6019
6020 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6021
6022 return 0;
6023 }
6024 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6025
6026 static int kvmclock_cpu_down_prep(unsigned int cpu)
6027 {
6028 __this_cpu_write(cpu_tsc_khz, 0);
6029 return 0;
6030 }
6031
6032 static void tsc_khz_changed(void *data)
6033 {
6034 struct cpufreq_freqs *freq = data;
6035 unsigned long khz = 0;
6036
6037 if (data)
6038 khz = freq->new;
6039 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6040 khz = cpufreq_quick_get(raw_smp_processor_id());
6041 if (!khz)
6042 khz = tsc_khz;
6043 __this_cpu_write(cpu_tsc_khz, khz);
6044 }
6045
6046 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6047 void *data)
6048 {
6049 struct cpufreq_freqs *freq = data;
6050 struct kvm *kvm;
6051 struct kvm_vcpu *vcpu;
6052 int i, send_ipi = 0;
6053
6054 /*
6055 * We allow guests to temporarily run on slowing clocks,
6056 * provided we notify them after, or to run on accelerating
6057 * clocks, provided we notify them before. Thus time never
6058 * goes backwards.
6059 *
6060 * However, we have a problem. We can't atomically update
6061 * the frequency of a given CPU from this function; it is
6062 * merely a notifier, which can be called from any CPU.
6063 * Changing the TSC frequency at arbitrary points in time
6064 * requires a recomputation of local variables related to
6065 * the TSC for each VCPU. We must flag these local variables
6066 * to be updated and be sure the update takes place with the
6067 * new frequency before any guests proceed.
6068 *
6069 * Unfortunately, the combination of hotplug CPU and frequency
6070 * change creates an intractable locking scenario; the order
6071 * of when these callouts happen is undefined with respect to
6072 * CPU hotplug, and they can race with each other. As such,
6073 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6074 * undefined; you can actually have a CPU frequency change take
6075 * place in between the computation of X and the setting of the
6076 * variable. To protect against this problem, all updates of
6077 * the per_cpu tsc_khz variable are done in an interrupt
6078 * protected IPI, and all callers wishing to update the value
6079 * must wait for a synchronous IPI to complete (which is trivial
6080 * if the caller is on the CPU already). This establishes the
6081 * necessary total order on variable updates.
6082 *
6083 * Note that because a guest time update may take place
6084 * anytime after the setting of the VCPU's request bit, the
6085 * correct TSC value must be set before the request. However,
6086 * to ensure the update actually makes it to any guest which
6087 * starts running in hardware virtualization between the set
6088 * and the acquisition of the spinlock, we must also ping the
6089 * CPU after setting the request bit.
6090 *
6091 */
6092
6093 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6094 return 0;
6095 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6096 return 0;
6097
6098 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6099
6100 spin_lock(&kvm_lock);
6101 list_for_each_entry(kvm, &vm_list, vm_list) {
6102 kvm_for_each_vcpu(i, vcpu, kvm) {
6103 if (vcpu->cpu != freq->cpu)
6104 continue;
6105 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6106 if (vcpu->cpu != smp_processor_id())
6107 send_ipi = 1;
6108 }
6109 }
6110 spin_unlock(&kvm_lock);
6111
6112 if (freq->old < freq->new && send_ipi) {
6113 /*
6114 * We upscale the frequency. Must make the guest
6115 * doesn't see old kvmclock values while running with
6116 * the new frequency, otherwise we risk the guest sees
6117 * time go backwards.
6118 *
6119 * In case we update the frequency for another cpu
6120 * (which might be in guest context) send an interrupt
6121 * to kick the cpu out of guest context. Next time
6122 * guest context is entered kvmclock will be updated,
6123 * so the guest will not see stale values.
6124 */
6125 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6126 }
6127 return 0;
6128 }
6129
6130 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6131 .notifier_call = kvmclock_cpufreq_notifier
6132 };
6133
6134 static int kvmclock_cpu_online(unsigned int cpu)
6135 {
6136 tsc_khz_changed(NULL);
6137 return 0;
6138 }
6139
6140 static void kvm_timer_init(void)
6141 {
6142 max_tsc_khz = tsc_khz;
6143
6144 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6145 #ifdef CONFIG_CPU_FREQ
6146 struct cpufreq_policy policy;
6147 int cpu;
6148
6149 memset(&policy, 0, sizeof(policy));
6150 cpu = get_cpu();
6151 cpufreq_get_policy(&policy, cpu);
6152 if (policy.cpuinfo.max_freq)
6153 max_tsc_khz = policy.cpuinfo.max_freq;
6154 put_cpu();
6155 #endif
6156 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6157 CPUFREQ_TRANSITION_NOTIFIER);
6158 }
6159 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6160
6161 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6162 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6163 }
6164
6165 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6166
6167 int kvm_is_in_guest(void)
6168 {
6169 return __this_cpu_read(current_vcpu) != NULL;
6170 }
6171
6172 static int kvm_is_user_mode(void)
6173 {
6174 int user_mode = 3;
6175
6176 if (__this_cpu_read(current_vcpu))
6177 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6178
6179 return user_mode != 0;
6180 }
6181
6182 static unsigned long kvm_get_guest_ip(void)
6183 {
6184 unsigned long ip = 0;
6185
6186 if (__this_cpu_read(current_vcpu))
6187 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6188
6189 return ip;
6190 }
6191
6192 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6193 .is_in_guest = kvm_is_in_guest,
6194 .is_user_mode = kvm_is_user_mode,
6195 .get_guest_ip = kvm_get_guest_ip,
6196 };
6197
6198 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6199 {
6200 __this_cpu_write(current_vcpu, vcpu);
6201 }
6202 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6203
6204 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6205 {
6206 __this_cpu_write(current_vcpu, NULL);
6207 }
6208 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6209
6210 static void kvm_set_mmio_spte_mask(void)
6211 {
6212 u64 mask;
6213 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6214
6215 /*
6216 * Set the reserved bits and the present bit of an paging-structure
6217 * entry to generate page fault with PFER.RSV = 1.
6218 */
6219 /* Mask the reserved physical address bits. */
6220 mask = rsvd_bits(maxphyaddr, 51);
6221
6222 /* Set the present bit. */
6223 mask |= 1ull;
6224
6225 #ifdef CONFIG_X86_64
6226 /*
6227 * If reserved bit is not supported, clear the present bit to disable
6228 * mmio page fault.
6229 */
6230 if (maxphyaddr == 52)
6231 mask &= ~1ull;
6232 #endif
6233
6234 kvm_mmu_set_mmio_spte_mask(mask, mask);
6235 }
6236
6237 #ifdef CONFIG_X86_64
6238 static void pvclock_gtod_update_fn(struct work_struct *work)
6239 {
6240 struct kvm *kvm;
6241
6242 struct kvm_vcpu *vcpu;
6243 int i;
6244
6245 spin_lock(&kvm_lock);
6246 list_for_each_entry(kvm, &vm_list, vm_list)
6247 kvm_for_each_vcpu(i, vcpu, kvm)
6248 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6249 atomic_set(&kvm_guest_has_master_clock, 0);
6250 spin_unlock(&kvm_lock);
6251 }
6252
6253 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6254
6255 /*
6256 * Notification about pvclock gtod data update.
6257 */
6258 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6259 void *priv)
6260 {
6261 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6262 struct timekeeper *tk = priv;
6263
6264 update_pvclock_gtod(tk);
6265
6266 /* disable master clock if host does not trust, or does not
6267 * use, TSC clocksource
6268 */
6269 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6270 atomic_read(&kvm_guest_has_master_clock) != 0)
6271 queue_work(system_long_wq, &pvclock_gtod_work);
6272
6273 return 0;
6274 }
6275
6276 static struct notifier_block pvclock_gtod_notifier = {
6277 .notifier_call = pvclock_gtod_notify,
6278 };
6279 #endif
6280
6281 int kvm_arch_init(void *opaque)
6282 {
6283 int r;
6284 struct kvm_x86_ops *ops = opaque;
6285
6286 if (kvm_x86_ops) {
6287 printk(KERN_ERR "kvm: already loaded the other module\n");
6288 r = -EEXIST;
6289 goto out;
6290 }
6291
6292 if (!ops->cpu_has_kvm_support()) {
6293 printk(KERN_ERR "kvm: no hardware support\n");
6294 r = -EOPNOTSUPP;
6295 goto out;
6296 }
6297 if (ops->disabled_by_bios()) {
6298 printk(KERN_WARNING "kvm: disabled by bios\n");
6299 r = -EOPNOTSUPP;
6300 goto out;
6301 }
6302
6303 r = -ENOMEM;
6304 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6305 if (!shared_msrs) {
6306 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6307 goto out;
6308 }
6309
6310 r = kvm_mmu_module_init();
6311 if (r)
6312 goto out_free_percpu;
6313
6314 kvm_set_mmio_spte_mask();
6315
6316 kvm_x86_ops = ops;
6317
6318 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6319 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6320 PT_PRESENT_MASK, 0, sme_me_mask);
6321 kvm_timer_init();
6322
6323 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6324
6325 if (boot_cpu_has(X86_FEATURE_XSAVE))
6326 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6327
6328 kvm_lapic_init();
6329 #ifdef CONFIG_X86_64
6330 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6331 #endif
6332
6333 return 0;
6334
6335 out_free_percpu:
6336 free_percpu(shared_msrs);
6337 out:
6338 return r;
6339 }
6340
6341 void kvm_arch_exit(void)
6342 {
6343 kvm_lapic_exit();
6344 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6345
6346 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6347 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6348 CPUFREQ_TRANSITION_NOTIFIER);
6349 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6350 #ifdef CONFIG_X86_64
6351 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6352 #endif
6353 kvm_x86_ops = NULL;
6354 kvm_mmu_module_exit();
6355 free_percpu(shared_msrs);
6356 }
6357
6358 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6359 {
6360 ++vcpu->stat.halt_exits;
6361 if (lapic_in_kernel(vcpu)) {
6362 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6363 return 1;
6364 } else {
6365 vcpu->run->exit_reason = KVM_EXIT_HLT;
6366 return 0;
6367 }
6368 }
6369 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6370
6371 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6372 {
6373 int ret = kvm_skip_emulated_instruction(vcpu);
6374 /*
6375 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6376 * KVM_EXIT_DEBUG here.
6377 */
6378 return kvm_vcpu_halt(vcpu) && ret;
6379 }
6380 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6381
6382 #ifdef CONFIG_X86_64
6383 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6384 unsigned long clock_type)
6385 {
6386 struct kvm_clock_pairing clock_pairing;
6387 struct timespec ts;
6388 u64 cycle;
6389 int ret;
6390
6391 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6392 return -KVM_EOPNOTSUPP;
6393
6394 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6395 return -KVM_EOPNOTSUPP;
6396
6397 clock_pairing.sec = ts.tv_sec;
6398 clock_pairing.nsec = ts.tv_nsec;
6399 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6400 clock_pairing.flags = 0;
6401
6402 ret = 0;
6403 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6404 sizeof(struct kvm_clock_pairing)))
6405 ret = -KVM_EFAULT;
6406
6407 return ret;
6408 }
6409 #endif
6410
6411 /*
6412 * kvm_pv_kick_cpu_op: Kick a vcpu.
6413 *
6414 * @apicid - apicid of vcpu to be kicked.
6415 */
6416 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6417 {
6418 struct kvm_lapic_irq lapic_irq;
6419
6420 lapic_irq.shorthand = 0;
6421 lapic_irq.dest_mode = 0;
6422 lapic_irq.level = 0;
6423 lapic_irq.dest_id = apicid;
6424 lapic_irq.msi_redir_hint = false;
6425
6426 lapic_irq.delivery_mode = APIC_DM_REMRD;
6427 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6428 }
6429
6430 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6431 {
6432 vcpu->arch.apicv_active = false;
6433 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6434 }
6435
6436 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6437 {
6438 unsigned long nr, a0, a1, a2, a3, ret;
6439 int op_64_bit;
6440
6441 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6442 if (!kvm_hv_hypercall(vcpu))
6443 return 0;
6444 goto out;
6445 }
6446
6447 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6448 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6449 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6450 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6451 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6452
6453 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6454
6455 op_64_bit = is_64_bit_mode(vcpu);
6456 if (!op_64_bit) {
6457 nr &= 0xFFFFFFFF;
6458 a0 &= 0xFFFFFFFF;
6459 a1 &= 0xFFFFFFFF;
6460 a2 &= 0xFFFFFFFF;
6461 a3 &= 0xFFFFFFFF;
6462 }
6463
6464 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6465 ret = -KVM_EPERM;
6466 goto out_error;
6467 }
6468
6469 switch (nr) {
6470 case KVM_HC_VAPIC_POLL_IRQ:
6471 ret = 0;
6472 break;
6473 case KVM_HC_KICK_CPU:
6474 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6475 ret = 0;
6476 break;
6477 #ifdef CONFIG_X86_64
6478 case KVM_HC_CLOCK_PAIRING:
6479 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6480 break;
6481 #endif
6482 default:
6483 ret = -KVM_ENOSYS;
6484 break;
6485 }
6486 out_error:
6487 if (!op_64_bit)
6488 ret = (u32)ret;
6489 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6490
6491 out:
6492 ++vcpu->stat.hypercalls;
6493 return kvm_skip_emulated_instruction(vcpu);
6494 }
6495 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6496
6497 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6498 {
6499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6500 char instruction[3];
6501 unsigned long rip = kvm_rip_read(vcpu);
6502
6503 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6504
6505 return emulator_write_emulated(ctxt, rip, instruction, 3,
6506 &ctxt->exception);
6507 }
6508
6509 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6510 {
6511 return vcpu->run->request_interrupt_window &&
6512 likely(!pic_in_kernel(vcpu->kvm));
6513 }
6514
6515 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6516 {
6517 struct kvm_run *kvm_run = vcpu->run;
6518
6519 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6520 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6521 kvm_run->cr8 = kvm_get_cr8(vcpu);
6522 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6523 kvm_run->ready_for_interrupt_injection =
6524 pic_in_kernel(vcpu->kvm) ||
6525 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6526 }
6527
6528 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6529 {
6530 int max_irr, tpr;
6531
6532 if (!kvm_x86_ops->update_cr8_intercept)
6533 return;
6534
6535 if (!lapic_in_kernel(vcpu))
6536 return;
6537
6538 if (vcpu->arch.apicv_active)
6539 return;
6540
6541 if (!vcpu->arch.apic->vapic_addr)
6542 max_irr = kvm_lapic_find_highest_irr(vcpu);
6543 else
6544 max_irr = -1;
6545
6546 if (max_irr != -1)
6547 max_irr >>= 4;
6548
6549 tpr = kvm_lapic_get_cr8(vcpu);
6550
6551 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6552 }
6553
6554 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6555 {
6556 int r;
6557
6558 /* try to reinject previous events if any */
6559 if (vcpu->arch.exception.injected) {
6560 kvm_x86_ops->queue_exception(vcpu);
6561 return 0;
6562 }
6563
6564 /*
6565 * Exceptions must be injected immediately, or the exception
6566 * frame will have the address of the NMI or interrupt handler.
6567 */
6568 if (!vcpu->arch.exception.pending) {
6569 if (vcpu->arch.nmi_injected) {
6570 kvm_x86_ops->set_nmi(vcpu);
6571 return 0;
6572 }
6573
6574 if (vcpu->arch.interrupt.pending) {
6575 kvm_x86_ops->set_irq(vcpu);
6576 return 0;
6577 }
6578 }
6579
6580 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6581 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6582 if (r != 0)
6583 return r;
6584 }
6585
6586 /* try to inject new event if pending */
6587 if (vcpu->arch.exception.pending) {
6588 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6589 vcpu->arch.exception.has_error_code,
6590 vcpu->arch.exception.error_code);
6591
6592 vcpu->arch.exception.pending = false;
6593 vcpu->arch.exception.injected = true;
6594
6595 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6596 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6597 X86_EFLAGS_RF);
6598
6599 if (vcpu->arch.exception.nr == DB_VECTOR &&
6600 (vcpu->arch.dr7 & DR7_GD)) {
6601 vcpu->arch.dr7 &= ~DR7_GD;
6602 kvm_update_dr7(vcpu);
6603 }
6604
6605 kvm_x86_ops->queue_exception(vcpu);
6606 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
6607 vcpu->arch.smi_pending = false;
6608 enter_smm(vcpu);
6609 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6610 --vcpu->arch.nmi_pending;
6611 vcpu->arch.nmi_injected = true;
6612 kvm_x86_ops->set_nmi(vcpu);
6613 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6614 /*
6615 * Because interrupts can be injected asynchronously, we are
6616 * calling check_nested_events again here to avoid a race condition.
6617 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6618 * proposal and current concerns. Perhaps we should be setting
6619 * KVM_REQ_EVENT only on certain events and not unconditionally?
6620 */
6621 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6622 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6623 if (r != 0)
6624 return r;
6625 }
6626 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6627 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6628 false);
6629 kvm_x86_ops->set_irq(vcpu);
6630 }
6631 }
6632
6633 return 0;
6634 }
6635
6636 static void process_nmi(struct kvm_vcpu *vcpu)
6637 {
6638 unsigned limit = 2;
6639
6640 /*
6641 * x86 is limited to one NMI running, and one NMI pending after it.
6642 * If an NMI is already in progress, limit further NMIs to just one.
6643 * Otherwise, allow two (and we'll inject the first one immediately).
6644 */
6645 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6646 limit = 1;
6647
6648 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6649 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6650 kvm_make_request(KVM_REQ_EVENT, vcpu);
6651 }
6652
6653 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6654 {
6655 u32 flags = 0;
6656 flags |= seg->g << 23;
6657 flags |= seg->db << 22;
6658 flags |= seg->l << 21;
6659 flags |= seg->avl << 20;
6660 flags |= seg->present << 15;
6661 flags |= seg->dpl << 13;
6662 flags |= seg->s << 12;
6663 flags |= seg->type << 8;
6664 return flags;
6665 }
6666
6667 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6668 {
6669 struct kvm_segment seg;
6670 int offset;
6671
6672 kvm_get_segment(vcpu, &seg, n);
6673 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6674
6675 if (n < 3)
6676 offset = 0x7f84 + n * 12;
6677 else
6678 offset = 0x7f2c + (n - 3) * 12;
6679
6680 put_smstate(u32, buf, offset + 8, seg.base);
6681 put_smstate(u32, buf, offset + 4, seg.limit);
6682 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6683 }
6684
6685 #ifdef CONFIG_X86_64
6686 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6687 {
6688 struct kvm_segment seg;
6689 int offset;
6690 u16 flags;
6691
6692 kvm_get_segment(vcpu, &seg, n);
6693 offset = 0x7e00 + n * 16;
6694
6695 flags = enter_smm_get_segment_flags(&seg) >> 8;
6696 put_smstate(u16, buf, offset, seg.selector);
6697 put_smstate(u16, buf, offset + 2, flags);
6698 put_smstate(u32, buf, offset + 4, seg.limit);
6699 put_smstate(u64, buf, offset + 8, seg.base);
6700 }
6701 #endif
6702
6703 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6704 {
6705 struct desc_ptr dt;
6706 struct kvm_segment seg;
6707 unsigned long val;
6708 int i;
6709
6710 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6711 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6712 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6713 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6714
6715 for (i = 0; i < 8; i++)
6716 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6717
6718 kvm_get_dr(vcpu, 6, &val);
6719 put_smstate(u32, buf, 0x7fcc, (u32)val);
6720 kvm_get_dr(vcpu, 7, &val);
6721 put_smstate(u32, buf, 0x7fc8, (u32)val);
6722
6723 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6724 put_smstate(u32, buf, 0x7fc4, seg.selector);
6725 put_smstate(u32, buf, 0x7f64, seg.base);
6726 put_smstate(u32, buf, 0x7f60, seg.limit);
6727 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6728
6729 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6730 put_smstate(u32, buf, 0x7fc0, seg.selector);
6731 put_smstate(u32, buf, 0x7f80, seg.base);
6732 put_smstate(u32, buf, 0x7f7c, seg.limit);
6733 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6734
6735 kvm_x86_ops->get_gdt(vcpu, &dt);
6736 put_smstate(u32, buf, 0x7f74, dt.address);
6737 put_smstate(u32, buf, 0x7f70, dt.size);
6738
6739 kvm_x86_ops->get_idt(vcpu, &dt);
6740 put_smstate(u32, buf, 0x7f58, dt.address);
6741 put_smstate(u32, buf, 0x7f54, dt.size);
6742
6743 for (i = 0; i < 6; i++)
6744 enter_smm_save_seg_32(vcpu, buf, i);
6745
6746 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6747
6748 /* revision id */
6749 put_smstate(u32, buf, 0x7efc, 0x00020000);
6750 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6751 }
6752
6753 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6754 {
6755 #ifdef CONFIG_X86_64
6756 struct desc_ptr dt;
6757 struct kvm_segment seg;
6758 unsigned long val;
6759 int i;
6760
6761 for (i = 0; i < 16; i++)
6762 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6763
6764 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6765 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6766
6767 kvm_get_dr(vcpu, 6, &val);
6768 put_smstate(u64, buf, 0x7f68, val);
6769 kvm_get_dr(vcpu, 7, &val);
6770 put_smstate(u64, buf, 0x7f60, val);
6771
6772 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6773 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6774 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6775
6776 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6777
6778 /* revision id */
6779 put_smstate(u32, buf, 0x7efc, 0x00020064);
6780
6781 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6782
6783 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6784 put_smstate(u16, buf, 0x7e90, seg.selector);
6785 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6786 put_smstate(u32, buf, 0x7e94, seg.limit);
6787 put_smstate(u64, buf, 0x7e98, seg.base);
6788
6789 kvm_x86_ops->get_idt(vcpu, &dt);
6790 put_smstate(u32, buf, 0x7e84, dt.size);
6791 put_smstate(u64, buf, 0x7e88, dt.address);
6792
6793 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6794 put_smstate(u16, buf, 0x7e70, seg.selector);
6795 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6796 put_smstate(u32, buf, 0x7e74, seg.limit);
6797 put_smstate(u64, buf, 0x7e78, seg.base);
6798
6799 kvm_x86_ops->get_gdt(vcpu, &dt);
6800 put_smstate(u32, buf, 0x7e64, dt.size);
6801 put_smstate(u64, buf, 0x7e68, dt.address);
6802
6803 for (i = 0; i < 6; i++)
6804 enter_smm_save_seg_64(vcpu, buf, i);
6805 #else
6806 WARN_ON_ONCE(1);
6807 #endif
6808 }
6809
6810 static void enter_smm(struct kvm_vcpu *vcpu)
6811 {
6812 struct kvm_segment cs, ds;
6813 struct desc_ptr dt;
6814 char buf[512];
6815 u32 cr0;
6816
6817 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6818 memset(buf, 0, 512);
6819 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6820 enter_smm_save_state_64(vcpu, buf);
6821 else
6822 enter_smm_save_state_32(vcpu, buf);
6823
6824 /*
6825 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6826 * vCPU state (e.g. leave guest mode) after we've saved the state into
6827 * the SMM state-save area.
6828 */
6829 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6830
6831 vcpu->arch.hflags |= HF_SMM_MASK;
6832 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6833
6834 if (kvm_x86_ops->get_nmi_mask(vcpu))
6835 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6836 else
6837 kvm_x86_ops->set_nmi_mask(vcpu, true);
6838
6839 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6840 kvm_rip_write(vcpu, 0x8000);
6841
6842 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6843 kvm_x86_ops->set_cr0(vcpu, cr0);
6844 vcpu->arch.cr0 = cr0;
6845
6846 kvm_x86_ops->set_cr4(vcpu, 0);
6847
6848 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6849 dt.address = dt.size = 0;
6850 kvm_x86_ops->set_idt(vcpu, &dt);
6851
6852 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6853
6854 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6855 cs.base = vcpu->arch.smbase;
6856
6857 ds.selector = 0;
6858 ds.base = 0;
6859
6860 cs.limit = ds.limit = 0xffffffff;
6861 cs.type = ds.type = 0x3;
6862 cs.dpl = ds.dpl = 0;
6863 cs.db = ds.db = 0;
6864 cs.s = ds.s = 1;
6865 cs.l = ds.l = 0;
6866 cs.g = ds.g = 1;
6867 cs.avl = ds.avl = 0;
6868 cs.present = ds.present = 1;
6869 cs.unusable = ds.unusable = 0;
6870 cs.padding = ds.padding = 0;
6871
6872 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6873 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6874 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6875 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6876 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6877 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6878
6879 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6880 kvm_x86_ops->set_efer(vcpu, 0);
6881
6882 kvm_update_cpuid(vcpu);
6883 kvm_mmu_reset_context(vcpu);
6884 }
6885
6886 static void process_smi(struct kvm_vcpu *vcpu)
6887 {
6888 vcpu->arch.smi_pending = true;
6889 kvm_make_request(KVM_REQ_EVENT, vcpu);
6890 }
6891
6892 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6893 {
6894 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6895 }
6896
6897 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6898 {
6899 u64 eoi_exit_bitmap[4];
6900
6901 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6902 return;
6903
6904 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6905
6906 if (irqchip_split(vcpu->kvm))
6907 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6908 else {
6909 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6910 kvm_x86_ops->sync_pir_to_irr(vcpu);
6911 if (ioapic_in_kernel(vcpu->kvm))
6912 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6913 }
6914 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6915 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6916 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6917 }
6918
6919 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6920 {
6921 ++vcpu->stat.tlb_flush;
6922 kvm_x86_ops->tlb_flush(vcpu);
6923 }
6924
6925 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6926 unsigned long start, unsigned long end)
6927 {
6928 unsigned long apic_address;
6929
6930 /*
6931 * The physical address of apic access page is stored in the VMCS.
6932 * Update it when it becomes invalid.
6933 */
6934 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6935 if (start <= apic_address && apic_address < end)
6936 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6937 }
6938
6939 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6940 {
6941 struct page *page = NULL;
6942
6943 if (!lapic_in_kernel(vcpu))
6944 return;
6945
6946 if (!kvm_x86_ops->set_apic_access_page_addr)
6947 return;
6948
6949 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6950 if (is_error_page(page))
6951 return;
6952 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6953
6954 /*
6955 * Do not pin apic access page in memory, the MMU notifier
6956 * will call us again if it is migrated or swapped out.
6957 */
6958 put_page(page);
6959 }
6960 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6961
6962 /*
6963 * Returns 1 to let vcpu_run() continue the guest execution loop without
6964 * exiting to the userspace. Otherwise, the value will be returned to the
6965 * userspace.
6966 */
6967 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6968 {
6969 int r;
6970 bool req_int_win =
6971 dm_request_for_irq_injection(vcpu) &&
6972 kvm_cpu_accept_dm_intr(vcpu);
6973
6974 bool req_immediate_exit = false;
6975
6976 if (kvm_request_pending(vcpu)) {
6977 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6978 kvm_mmu_unload(vcpu);
6979 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6980 __kvm_migrate_timers(vcpu);
6981 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6982 kvm_gen_update_masterclock(vcpu->kvm);
6983 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6984 kvm_gen_kvmclock_update(vcpu);
6985 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6986 r = kvm_guest_time_update(vcpu);
6987 if (unlikely(r))
6988 goto out;
6989 }
6990 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6991 kvm_mmu_sync_roots(vcpu);
6992 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6993 kvm_vcpu_flush_tlb(vcpu);
6994 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6995 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6996 r = 0;
6997 goto out;
6998 }
6999 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7000 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7001 vcpu->mmio_needed = 0;
7002 r = 0;
7003 goto out;
7004 }
7005 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7006 /* Page is swapped out. Do synthetic halt */
7007 vcpu->arch.apf.halted = true;
7008 r = 1;
7009 goto out;
7010 }
7011 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7012 record_steal_time(vcpu);
7013 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7014 process_smi(vcpu);
7015 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7016 process_nmi(vcpu);
7017 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7018 kvm_pmu_handle_event(vcpu);
7019 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7020 kvm_pmu_deliver_pmi(vcpu);
7021 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7022 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7023 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7024 vcpu->arch.ioapic_handled_vectors)) {
7025 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7026 vcpu->run->eoi.vector =
7027 vcpu->arch.pending_ioapic_eoi;
7028 r = 0;
7029 goto out;
7030 }
7031 }
7032 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7033 vcpu_scan_ioapic(vcpu);
7034 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7035 kvm_vcpu_reload_apic_access_page(vcpu);
7036 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7037 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7038 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7039 r = 0;
7040 goto out;
7041 }
7042 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7043 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7044 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7045 r = 0;
7046 goto out;
7047 }
7048 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7049 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7050 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7051 r = 0;
7052 goto out;
7053 }
7054
7055 /*
7056 * KVM_REQ_HV_STIMER has to be processed after
7057 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7058 * depend on the guest clock being up-to-date
7059 */
7060 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7061 kvm_hv_process_stimers(vcpu);
7062 }
7063
7064 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7065 ++vcpu->stat.req_event;
7066 kvm_apic_accept_events(vcpu);
7067 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7068 r = 1;
7069 goto out;
7070 }
7071
7072 if (inject_pending_event(vcpu, req_int_win) != 0)
7073 req_immediate_exit = true;
7074 else {
7075 /* Enable SMI/NMI/IRQ window open exits if needed.
7076 *
7077 * SMIs have three cases:
7078 * 1) They can be nested, and then there is nothing to
7079 * do here because RSM will cause a vmexit anyway.
7080 * 2) There is an ISA-specific reason why SMI cannot be
7081 * injected, and the moment when this changes can be
7082 * intercepted.
7083 * 3) Or the SMI can be pending because
7084 * inject_pending_event has completed the injection
7085 * of an IRQ or NMI from the previous vmexit, and
7086 * then we request an immediate exit to inject the
7087 * SMI.
7088 */
7089 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7090 if (!kvm_x86_ops->enable_smi_window(vcpu))
7091 req_immediate_exit = true;
7092 if (vcpu->arch.nmi_pending)
7093 kvm_x86_ops->enable_nmi_window(vcpu);
7094 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7095 kvm_x86_ops->enable_irq_window(vcpu);
7096 WARN_ON(vcpu->arch.exception.pending);
7097 }
7098
7099 if (kvm_lapic_enabled(vcpu)) {
7100 update_cr8_intercept(vcpu);
7101 kvm_lapic_sync_to_vapic(vcpu);
7102 }
7103 }
7104
7105 r = kvm_mmu_reload(vcpu);
7106 if (unlikely(r)) {
7107 goto cancel_injection;
7108 }
7109
7110 preempt_disable();
7111
7112 kvm_x86_ops->prepare_guest_switch(vcpu);
7113
7114 /*
7115 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7116 * IPI are then delayed after guest entry, which ensures that they
7117 * result in virtual interrupt delivery.
7118 */
7119 local_irq_disable();
7120 vcpu->mode = IN_GUEST_MODE;
7121
7122 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7123
7124 /*
7125 * 1) We should set ->mode before checking ->requests. Please see
7126 * the comment in kvm_vcpu_exiting_guest_mode().
7127 *
7128 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7129 * pairs with the memory barrier implicit in pi_test_and_set_on
7130 * (see vmx_deliver_posted_interrupt).
7131 *
7132 * 3) This also orders the write to mode from any reads to the page
7133 * tables done while the VCPU is running. Please see the comment
7134 * in kvm_flush_remote_tlbs.
7135 */
7136 smp_mb__after_srcu_read_unlock();
7137
7138 /*
7139 * This handles the case where a posted interrupt was
7140 * notified with kvm_vcpu_kick.
7141 */
7142 if (kvm_lapic_enabled(vcpu)) {
7143 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7144 kvm_x86_ops->sync_pir_to_irr(vcpu);
7145 }
7146
7147 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7148 || need_resched() || signal_pending(current)) {
7149 vcpu->mode = OUTSIDE_GUEST_MODE;
7150 smp_wmb();
7151 local_irq_enable();
7152 preempt_enable();
7153 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7154 r = 1;
7155 goto cancel_injection;
7156 }
7157
7158 kvm_load_guest_xcr0(vcpu);
7159
7160 if (req_immediate_exit) {
7161 kvm_make_request(KVM_REQ_EVENT, vcpu);
7162 smp_send_reschedule(vcpu->cpu);
7163 }
7164
7165 trace_kvm_entry(vcpu->vcpu_id);
7166 wait_lapic_expire(vcpu);
7167 guest_enter_irqoff();
7168
7169 if (unlikely(vcpu->arch.switch_db_regs)) {
7170 set_debugreg(0, 7);
7171 set_debugreg(vcpu->arch.eff_db[0], 0);
7172 set_debugreg(vcpu->arch.eff_db[1], 1);
7173 set_debugreg(vcpu->arch.eff_db[2], 2);
7174 set_debugreg(vcpu->arch.eff_db[3], 3);
7175 set_debugreg(vcpu->arch.dr6, 6);
7176 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7177 }
7178
7179 kvm_x86_ops->run(vcpu);
7180
7181 /*
7182 * Do this here before restoring debug registers on the host. And
7183 * since we do this before handling the vmexit, a DR access vmexit
7184 * can (a) read the correct value of the debug registers, (b) set
7185 * KVM_DEBUGREG_WONT_EXIT again.
7186 */
7187 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7188 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7189 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7190 kvm_update_dr0123(vcpu);
7191 kvm_update_dr6(vcpu);
7192 kvm_update_dr7(vcpu);
7193 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7194 }
7195
7196 /*
7197 * If the guest has used debug registers, at least dr7
7198 * will be disabled while returning to the host.
7199 * If we don't have active breakpoints in the host, we don't
7200 * care about the messed up debug address registers. But if
7201 * we have some of them active, restore the old state.
7202 */
7203 if (hw_breakpoint_active())
7204 hw_breakpoint_restore();
7205
7206 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7207
7208 vcpu->mode = OUTSIDE_GUEST_MODE;
7209 smp_wmb();
7210
7211 kvm_put_guest_xcr0(vcpu);
7212
7213 kvm_x86_ops->handle_external_intr(vcpu);
7214
7215 ++vcpu->stat.exits;
7216
7217 guest_exit_irqoff();
7218
7219 local_irq_enable();
7220 preempt_enable();
7221
7222 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7223
7224 /*
7225 * Profile KVM exit RIPs:
7226 */
7227 if (unlikely(prof_on == KVM_PROFILING)) {
7228 unsigned long rip = kvm_rip_read(vcpu);
7229 profile_hit(KVM_PROFILING, (void *)rip);
7230 }
7231
7232 if (unlikely(vcpu->arch.tsc_always_catchup))
7233 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7234
7235 if (vcpu->arch.apic_attention)
7236 kvm_lapic_sync_from_vapic(vcpu);
7237
7238 vcpu->arch.gpa_available = false;
7239 r = kvm_x86_ops->handle_exit(vcpu);
7240 return r;
7241
7242 cancel_injection:
7243 kvm_x86_ops->cancel_injection(vcpu);
7244 if (unlikely(vcpu->arch.apic_attention))
7245 kvm_lapic_sync_from_vapic(vcpu);
7246 out:
7247 return r;
7248 }
7249
7250 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7251 {
7252 if (!kvm_arch_vcpu_runnable(vcpu) &&
7253 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7254 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7255 kvm_vcpu_block(vcpu);
7256 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7257
7258 if (kvm_x86_ops->post_block)
7259 kvm_x86_ops->post_block(vcpu);
7260
7261 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7262 return 1;
7263 }
7264
7265 kvm_apic_accept_events(vcpu);
7266 switch(vcpu->arch.mp_state) {
7267 case KVM_MP_STATE_HALTED:
7268 vcpu->arch.pv.pv_unhalted = false;
7269 vcpu->arch.mp_state =
7270 KVM_MP_STATE_RUNNABLE;
7271 case KVM_MP_STATE_RUNNABLE:
7272 vcpu->arch.apf.halted = false;
7273 break;
7274 case KVM_MP_STATE_INIT_RECEIVED:
7275 break;
7276 default:
7277 return -EINTR;
7278 break;
7279 }
7280 return 1;
7281 }
7282
7283 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7284 {
7285 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7286 kvm_x86_ops->check_nested_events(vcpu, false);
7287
7288 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7289 !vcpu->arch.apf.halted);
7290 }
7291
7292 static int vcpu_run(struct kvm_vcpu *vcpu)
7293 {
7294 int r;
7295 struct kvm *kvm = vcpu->kvm;
7296
7297 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7298 vcpu->arch.l1tf_flush_l1d = true;
7299
7300 for (;;) {
7301 if (kvm_vcpu_running(vcpu)) {
7302 r = vcpu_enter_guest(vcpu);
7303 } else {
7304 r = vcpu_block(kvm, vcpu);
7305 }
7306
7307 if (r <= 0)
7308 break;
7309
7310 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7311 if (kvm_cpu_has_pending_timer(vcpu))
7312 kvm_inject_pending_timer_irqs(vcpu);
7313
7314 if (dm_request_for_irq_injection(vcpu) &&
7315 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7316 r = 0;
7317 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7318 ++vcpu->stat.request_irq_exits;
7319 break;
7320 }
7321
7322 kvm_check_async_pf_completion(vcpu);
7323
7324 if (signal_pending(current)) {
7325 r = -EINTR;
7326 vcpu->run->exit_reason = KVM_EXIT_INTR;
7327 ++vcpu->stat.signal_exits;
7328 break;
7329 }
7330 if (need_resched()) {
7331 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7332 cond_resched();
7333 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7334 }
7335 }
7336
7337 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7338
7339 return r;
7340 }
7341
7342 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7343 {
7344 int r;
7345 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7346 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7347 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7348 if (r != EMULATE_DONE)
7349 return 0;
7350 return 1;
7351 }
7352
7353 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7354 {
7355 BUG_ON(!vcpu->arch.pio.count);
7356
7357 return complete_emulated_io(vcpu);
7358 }
7359
7360 /*
7361 * Implements the following, as a state machine:
7362 *
7363 * read:
7364 * for each fragment
7365 * for each mmio piece in the fragment
7366 * write gpa, len
7367 * exit
7368 * copy data
7369 * execute insn
7370 *
7371 * write:
7372 * for each fragment
7373 * for each mmio piece in the fragment
7374 * write gpa, len
7375 * copy data
7376 * exit
7377 */
7378 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7379 {
7380 struct kvm_run *run = vcpu->run;
7381 struct kvm_mmio_fragment *frag;
7382 unsigned len;
7383
7384 BUG_ON(!vcpu->mmio_needed);
7385
7386 /* Complete previous fragment */
7387 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7388 len = min(8u, frag->len);
7389 if (!vcpu->mmio_is_write)
7390 memcpy(frag->data, run->mmio.data, len);
7391
7392 if (frag->len <= 8) {
7393 /* Switch to the next fragment. */
7394 frag++;
7395 vcpu->mmio_cur_fragment++;
7396 } else {
7397 /* Go forward to the next mmio piece. */
7398 frag->data += len;
7399 frag->gpa += len;
7400 frag->len -= len;
7401 }
7402
7403 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7404 vcpu->mmio_needed = 0;
7405
7406 /* FIXME: return into emulator if single-stepping. */
7407 if (vcpu->mmio_is_write)
7408 return 1;
7409 vcpu->mmio_read_completed = 1;
7410 return complete_emulated_io(vcpu);
7411 }
7412
7413 run->exit_reason = KVM_EXIT_MMIO;
7414 run->mmio.phys_addr = frag->gpa;
7415 if (vcpu->mmio_is_write)
7416 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7417 run->mmio.len = min(8u, frag->len);
7418 run->mmio.is_write = vcpu->mmio_is_write;
7419 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7420 return 0;
7421 }
7422
7423
7424 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7425 {
7426 int r;
7427
7428 kvm_sigset_activate(vcpu);
7429
7430 kvm_load_guest_fpu(vcpu);
7431
7432 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7433 if (kvm_run->immediate_exit) {
7434 r = -EINTR;
7435 goto out;
7436 }
7437 kvm_vcpu_block(vcpu);
7438 kvm_apic_accept_events(vcpu);
7439 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7440 r = -EAGAIN;
7441 if (signal_pending(current)) {
7442 r = -EINTR;
7443 vcpu->run->exit_reason = KVM_EXIT_INTR;
7444 ++vcpu->stat.signal_exits;
7445 }
7446 goto out;
7447 }
7448
7449 /* re-sync apic's tpr */
7450 if (!lapic_in_kernel(vcpu)) {
7451 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7452 r = -EINVAL;
7453 goto out;
7454 }
7455 }
7456
7457 if (unlikely(vcpu->arch.complete_userspace_io)) {
7458 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7459 vcpu->arch.complete_userspace_io = NULL;
7460 r = cui(vcpu);
7461 if (r <= 0)
7462 goto out;
7463 } else
7464 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7465
7466 if (kvm_run->immediate_exit)
7467 r = -EINTR;
7468 else
7469 r = vcpu_run(vcpu);
7470
7471 out:
7472 kvm_put_guest_fpu(vcpu);
7473 post_kvm_run_save(vcpu);
7474 kvm_sigset_deactivate(vcpu);
7475
7476 return r;
7477 }
7478
7479 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7480 {
7481 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7482 /*
7483 * We are here if userspace calls get_regs() in the middle of
7484 * instruction emulation. Registers state needs to be copied
7485 * back from emulation context to vcpu. Userspace shouldn't do
7486 * that usually, but some bad designed PV devices (vmware
7487 * backdoor interface) need this to work
7488 */
7489 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7490 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7491 }
7492 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7493 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7494 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7495 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7496 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7497 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7498 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7499 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7500 #ifdef CONFIG_X86_64
7501 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7502 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7503 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7504 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7505 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7506 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7507 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7508 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7509 #endif
7510
7511 regs->rip = kvm_rip_read(vcpu);
7512 regs->rflags = kvm_get_rflags(vcpu);
7513
7514 return 0;
7515 }
7516
7517 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7518 {
7519 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7520 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7521
7522 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7523 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7524 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7525 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7526 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7527 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7528 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7529 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7530 #ifdef CONFIG_X86_64
7531 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7532 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7533 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7534 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7535 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7536 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7537 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7538 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7539 #endif
7540
7541 kvm_rip_write(vcpu, regs->rip);
7542 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7543
7544 vcpu->arch.exception.pending = false;
7545
7546 kvm_make_request(KVM_REQ_EVENT, vcpu);
7547
7548 return 0;
7549 }
7550
7551 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7552 {
7553 struct kvm_segment cs;
7554
7555 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7556 *db = cs.db;
7557 *l = cs.l;
7558 }
7559 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7560
7561 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7562 struct kvm_sregs *sregs)
7563 {
7564 struct desc_ptr dt;
7565
7566 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7567 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7568 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7569 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7570 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7571 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7572
7573 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7574 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7575
7576 kvm_x86_ops->get_idt(vcpu, &dt);
7577 sregs->idt.limit = dt.size;
7578 sregs->idt.base = dt.address;
7579 kvm_x86_ops->get_gdt(vcpu, &dt);
7580 sregs->gdt.limit = dt.size;
7581 sregs->gdt.base = dt.address;
7582
7583 sregs->cr0 = kvm_read_cr0(vcpu);
7584 sregs->cr2 = vcpu->arch.cr2;
7585 sregs->cr3 = kvm_read_cr3(vcpu);
7586 sregs->cr4 = kvm_read_cr4(vcpu);
7587 sregs->cr8 = kvm_get_cr8(vcpu);
7588 sregs->efer = vcpu->arch.efer;
7589 sregs->apic_base = kvm_get_apic_base(vcpu);
7590
7591 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7592
7593 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7594 set_bit(vcpu->arch.interrupt.nr,
7595 (unsigned long *)sregs->interrupt_bitmap);
7596
7597 return 0;
7598 }
7599
7600 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7601 struct kvm_mp_state *mp_state)
7602 {
7603 kvm_apic_accept_events(vcpu);
7604 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7605 vcpu->arch.pv.pv_unhalted)
7606 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7607 else
7608 mp_state->mp_state = vcpu->arch.mp_state;
7609
7610 return 0;
7611 }
7612
7613 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7614 struct kvm_mp_state *mp_state)
7615 {
7616 if (!lapic_in_kernel(vcpu) &&
7617 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7618 return -EINVAL;
7619
7620 /* INITs are latched while in SMM */
7621 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7622 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7623 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7624 return -EINVAL;
7625
7626 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7627 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7628 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7629 } else
7630 vcpu->arch.mp_state = mp_state->mp_state;
7631 kvm_make_request(KVM_REQ_EVENT, vcpu);
7632 return 0;
7633 }
7634
7635 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7636 int reason, bool has_error_code, u32 error_code)
7637 {
7638 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7639 int ret;
7640
7641 init_emulate_ctxt(vcpu);
7642
7643 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7644 has_error_code, error_code);
7645
7646 if (ret)
7647 return EMULATE_FAIL;
7648
7649 kvm_rip_write(vcpu, ctxt->eip);
7650 kvm_set_rflags(vcpu, ctxt->eflags);
7651 kvm_make_request(KVM_REQ_EVENT, vcpu);
7652 return EMULATE_DONE;
7653 }
7654 EXPORT_SYMBOL_GPL(kvm_task_switch);
7655
7656 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7657 {
7658 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7659 /*
7660 * When EFER.LME and CR0.PG are set, the processor is in
7661 * 64-bit mode (though maybe in a 32-bit code segment).
7662 * CR4.PAE and EFER.LMA must be set.
7663 */
7664 if (!(sregs->cr4 & X86_CR4_PAE)
7665 || !(sregs->efer & EFER_LMA))
7666 return -EINVAL;
7667 } else {
7668 /*
7669 * Not in 64-bit mode: EFER.LMA is clear and the code
7670 * segment cannot be 64-bit.
7671 */
7672 if (sregs->efer & EFER_LMA || sregs->cs.l)
7673 return -EINVAL;
7674 }
7675
7676 return 0;
7677 }
7678
7679 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7680 struct kvm_sregs *sregs)
7681 {
7682 struct msr_data apic_base_msr;
7683 int mmu_reset_needed = 0;
7684 int cpuid_update_needed = 0;
7685 int pending_vec, max_bits, idx;
7686 struct desc_ptr dt;
7687
7688 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7689 (sregs->cr4 & X86_CR4_OSXSAVE))
7690 return -EINVAL;
7691
7692 if (kvm_valid_sregs(vcpu, sregs))
7693 return -EINVAL;
7694
7695 apic_base_msr.data = sregs->apic_base;
7696 apic_base_msr.host_initiated = true;
7697 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7698 return -EINVAL;
7699
7700 dt.size = sregs->idt.limit;
7701 dt.address = sregs->idt.base;
7702 kvm_x86_ops->set_idt(vcpu, &dt);
7703 dt.size = sregs->gdt.limit;
7704 dt.address = sregs->gdt.base;
7705 kvm_x86_ops->set_gdt(vcpu, &dt);
7706
7707 vcpu->arch.cr2 = sregs->cr2;
7708 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7709 vcpu->arch.cr3 = sregs->cr3;
7710 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7711
7712 kvm_set_cr8(vcpu, sregs->cr8);
7713
7714 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7715 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7716
7717 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7718 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7719 vcpu->arch.cr0 = sregs->cr0;
7720
7721 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7722 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
7723 (X86_CR4_OSXSAVE | X86_CR4_PKE));
7724 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7725 if (cpuid_update_needed)
7726 kvm_update_cpuid(vcpu);
7727
7728 idx = srcu_read_lock(&vcpu->kvm->srcu);
7729 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7730 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7731 mmu_reset_needed = 1;
7732 }
7733 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7734
7735 if (mmu_reset_needed)
7736 kvm_mmu_reset_context(vcpu);
7737
7738 max_bits = KVM_NR_INTERRUPTS;
7739 pending_vec = find_first_bit(
7740 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7741 if (pending_vec < max_bits) {
7742 kvm_queue_interrupt(vcpu, pending_vec, false);
7743 pr_debug("Set back pending irq %d\n", pending_vec);
7744 }
7745
7746 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7747 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7748 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7749 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7750 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7751 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7752
7753 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7754 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7755
7756 update_cr8_intercept(vcpu);
7757
7758 /* Older userspace won't unhalt the vcpu on reset. */
7759 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7760 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7761 !is_protmode(vcpu))
7762 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7763
7764 kvm_make_request(KVM_REQ_EVENT, vcpu);
7765
7766 return 0;
7767 }
7768
7769 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7770 struct kvm_guest_debug *dbg)
7771 {
7772 unsigned long rflags;
7773 int i, r;
7774
7775 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7776 r = -EBUSY;
7777 if (vcpu->arch.exception.pending)
7778 goto out;
7779 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7780 kvm_queue_exception(vcpu, DB_VECTOR);
7781 else
7782 kvm_queue_exception(vcpu, BP_VECTOR);
7783 }
7784
7785 /*
7786 * Read rflags as long as potentially injected trace flags are still
7787 * filtered out.
7788 */
7789 rflags = kvm_get_rflags(vcpu);
7790
7791 vcpu->guest_debug = dbg->control;
7792 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7793 vcpu->guest_debug = 0;
7794
7795 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7796 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7797 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7798 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7799 } else {
7800 for (i = 0; i < KVM_NR_DB_REGS; i++)
7801 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7802 }
7803 kvm_update_dr7(vcpu);
7804
7805 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7806 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7807 get_segment_base(vcpu, VCPU_SREG_CS);
7808
7809 /*
7810 * Trigger an rflags update that will inject or remove the trace
7811 * flags.
7812 */
7813 kvm_set_rflags(vcpu, rflags);
7814
7815 kvm_x86_ops->update_bp_intercept(vcpu);
7816
7817 r = 0;
7818
7819 out:
7820
7821 return r;
7822 }
7823
7824 /*
7825 * Translate a guest virtual address to a guest physical address.
7826 */
7827 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7828 struct kvm_translation *tr)
7829 {
7830 unsigned long vaddr = tr->linear_address;
7831 gpa_t gpa;
7832 int idx;
7833
7834 idx = srcu_read_lock(&vcpu->kvm->srcu);
7835 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7836 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7837 tr->physical_address = gpa;
7838 tr->valid = gpa != UNMAPPED_GVA;
7839 tr->writeable = 1;
7840 tr->usermode = 0;
7841
7842 return 0;
7843 }
7844
7845 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7846 {
7847 struct fxregs_state *fxsave =
7848 &vcpu->arch.guest_fpu.state.fxsave;
7849
7850 memcpy(fpu->fpr, fxsave->st_space, 128);
7851 fpu->fcw = fxsave->cwd;
7852 fpu->fsw = fxsave->swd;
7853 fpu->ftwx = fxsave->twd;
7854 fpu->last_opcode = fxsave->fop;
7855 fpu->last_ip = fxsave->rip;
7856 fpu->last_dp = fxsave->rdp;
7857 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7858
7859 return 0;
7860 }
7861
7862 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7863 {
7864 struct fxregs_state *fxsave =
7865 &vcpu->arch.guest_fpu.state.fxsave;
7866
7867 memcpy(fxsave->st_space, fpu->fpr, 128);
7868 fxsave->cwd = fpu->fcw;
7869 fxsave->swd = fpu->fsw;
7870 fxsave->twd = fpu->ftwx;
7871 fxsave->fop = fpu->last_opcode;
7872 fxsave->rip = fpu->last_ip;
7873 fxsave->rdp = fpu->last_dp;
7874 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7875
7876 return 0;
7877 }
7878
7879 static void fx_init(struct kvm_vcpu *vcpu)
7880 {
7881 fpstate_init(&vcpu->arch.guest_fpu.state);
7882 if (boot_cpu_has(X86_FEATURE_XSAVES))
7883 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7884 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7885
7886 /*
7887 * Ensure guest xcr0 is valid for loading
7888 */
7889 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7890
7891 vcpu->arch.cr0 |= X86_CR0_ET;
7892 }
7893
7894 /* Swap (qemu) user FPU context for the guest FPU context. */
7895 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7896 {
7897 preempt_disable();
7898 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7899 /* PKRU is separately restored in kvm_x86_ops->run. */
7900 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7901 ~XFEATURE_MASK_PKRU);
7902 preempt_enable();
7903 trace_kvm_fpu(1);
7904 }
7905
7906 /* When vcpu_run ends, restore user space FPU context. */
7907 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7908 {
7909 preempt_disable();
7910 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7911 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7912 preempt_enable();
7913 ++vcpu->stat.fpu_reload;
7914 trace_kvm_fpu(0);
7915 }
7916
7917 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7918 {
7919 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7920
7921 kvmclock_reset(vcpu);
7922
7923 kvm_x86_ops->vcpu_free(vcpu);
7924 free_cpumask_var(wbinvd_dirty_mask);
7925 }
7926
7927 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7928 unsigned int id)
7929 {
7930 struct kvm_vcpu *vcpu;
7931
7932 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7933 printk_once(KERN_WARNING
7934 "kvm: SMP vm created on host with unstable TSC; "
7935 "guest TSC will not be reliable\n");
7936
7937 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7938
7939 return vcpu;
7940 }
7941
7942 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7943 {
7944 int r;
7945
7946 kvm_vcpu_mtrr_init(vcpu);
7947 r = vcpu_load(vcpu);
7948 if (r)
7949 return r;
7950 kvm_vcpu_reset(vcpu, false);
7951 kvm_mmu_setup(vcpu);
7952 vcpu_put(vcpu);
7953 return r;
7954 }
7955
7956 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7957 {
7958 struct msr_data msr;
7959 struct kvm *kvm = vcpu->kvm;
7960
7961 kvm_hv_vcpu_postcreate(vcpu);
7962
7963 if (vcpu_load(vcpu))
7964 return;
7965 msr.data = 0x0;
7966 msr.index = MSR_IA32_TSC;
7967 msr.host_initiated = true;
7968 kvm_write_tsc(vcpu, &msr);
7969 vcpu_put(vcpu);
7970
7971 if (!kvmclock_periodic_sync)
7972 return;
7973
7974 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7975 KVMCLOCK_SYNC_PERIOD);
7976 }
7977
7978 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7979 {
7980 int r;
7981 vcpu->arch.apf.msr_val = 0;
7982
7983 r = vcpu_load(vcpu);
7984 BUG_ON(r);
7985 kvm_mmu_unload(vcpu);
7986 vcpu_put(vcpu);
7987
7988 kvm_x86_ops->vcpu_free(vcpu);
7989 }
7990
7991 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7992 {
7993 kvm_lapic_reset(vcpu, init_event);
7994
7995 vcpu->arch.hflags = 0;
7996
7997 vcpu->arch.smi_pending = 0;
7998 atomic_set(&vcpu->arch.nmi_queued, 0);
7999 vcpu->arch.nmi_pending = 0;
8000 vcpu->arch.nmi_injected = false;
8001 kvm_clear_interrupt_queue(vcpu);
8002 kvm_clear_exception_queue(vcpu);
8003 vcpu->arch.exception.pending = false;
8004
8005 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8006 kvm_update_dr0123(vcpu);
8007 vcpu->arch.dr6 = DR6_INIT;
8008 kvm_update_dr6(vcpu);
8009 vcpu->arch.dr7 = DR7_FIXED_1;
8010 kvm_update_dr7(vcpu);
8011
8012 vcpu->arch.cr2 = 0;
8013
8014 kvm_make_request(KVM_REQ_EVENT, vcpu);
8015 vcpu->arch.apf.msr_val = 0;
8016 vcpu->arch.st.msr_val = 0;
8017
8018 kvmclock_reset(vcpu);
8019
8020 kvm_clear_async_pf_completion_queue(vcpu);
8021 kvm_async_pf_hash_reset(vcpu);
8022 vcpu->arch.apf.halted = false;
8023
8024 if (kvm_mpx_supported()) {
8025 void *mpx_state_buffer;
8026
8027 /*
8028 * To avoid have the INIT path from kvm_apic_has_events() that be
8029 * called with loaded FPU and does not let userspace fix the state.
8030 */
8031 if (init_event)
8032 kvm_put_guest_fpu(vcpu);
8033 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8034 XFEATURE_MASK_BNDREGS);
8035 if (mpx_state_buffer)
8036 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8037 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8038 XFEATURE_MASK_BNDCSR);
8039 if (mpx_state_buffer)
8040 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8041 if (init_event)
8042 kvm_load_guest_fpu(vcpu);
8043 }
8044
8045 if (!init_event) {
8046 kvm_pmu_reset(vcpu);
8047 vcpu->arch.smbase = 0x30000;
8048
8049 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8050 vcpu->arch.msr_misc_features_enables = 0;
8051
8052 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8053 }
8054
8055 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8056 vcpu->arch.regs_avail = ~0;
8057 vcpu->arch.regs_dirty = ~0;
8058
8059 vcpu->arch.ia32_xss = 0;
8060
8061 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8062 }
8063
8064 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8065 {
8066 struct kvm_segment cs;
8067
8068 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8069 cs.selector = vector << 8;
8070 cs.base = vector << 12;
8071 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8072 kvm_rip_write(vcpu, 0);
8073 }
8074
8075 int kvm_arch_hardware_enable(void)
8076 {
8077 struct kvm *kvm;
8078 struct kvm_vcpu *vcpu;
8079 int i;
8080 int ret;
8081 u64 local_tsc;
8082 u64 max_tsc = 0;
8083 bool stable, backwards_tsc = false;
8084
8085 kvm_shared_msr_cpu_online();
8086 ret = kvm_x86_ops->hardware_enable();
8087 if (ret != 0)
8088 return ret;
8089
8090 local_tsc = rdtsc();
8091 stable = !check_tsc_unstable();
8092 list_for_each_entry(kvm, &vm_list, vm_list) {
8093 kvm_for_each_vcpu(i, vcpu, kvm) {
8094 if (!stable && vcpu->cpu == smp_processor_id())
8095 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8096 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8097 backwards_tsc = true;
8098 if (vcpu->arch.last_host_tsc > max_tsc)
8099 max_tsc = vcpu->arch.last_host_tsc;
8100 }
8101 }
8102 }
8103
8104 /*
8105 * Sometimes, even reliable TSCs go backwards. This happens on
8106 * platforms that reset TSC during suspend or hibernate actions, but
8107 * maintain synchronization. We must compensate. Fortunately, we can
8108 * detect that condition here, which happens early in CPU bringup,
8109 * before any KVM threads can be running. Unfortunately, we can't
8110 * bring the TSCs fully up to date with real time, as we aren't yet far
8111 * enough into CPU bringup that we know how much real time has actually
8112 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8113 * variables that haven't been updated yet.
8114 *
8115 * So we simply find the maximum observed TSC above, then record the
8116 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8117 * the adjustment will be applied. Note that we accumulate
8118 * adjustments, in case multiple suspend cycles happen before some VCPU
8119 * gets a chance to run again. In the event that no KVM threads get a
8120 * chance to run, we will miss the entire elapsed period, as we'll have
8121 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8122 * loose cycle time. This isn't too big a deal, since the loss will be
8123 * uniform across all VCPUs (not to mention the scenario is extremely
8124 * unlikely). It is possible that a second hibernate recovery happens
8125 * much faster than a first, causing the observed TSC here to be
8126 * smaller; this would require additional padding adjustment, which is
8127 * why we set last_host_tsc to the local tsc observed here.
8128 *
8129 * N.B. - this code below runs only on platforms with reliable TSC,
8130 * as that is the only way backwards_tsc is set above. Also note
8131 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8132 * have the same delta_cyc adjustment applied if backwards_tsc
8133 * is detected. Note further, this adjustment is only done once,
8134 * as we reset last_host_tsc on all VCPUs to stop this from being
8135 * called multiple times (one for each physical CPU bringup).
8136 *
8137 * Platforms with unreliable TSCs don't have to deal with this, they
8138 * will be compensated by the logic in vcpu_load, which sets the TSC to
8139 * catchup mode. This will catchup all VCPUs to real time, but cannot
8140 * guarantee that they stay in perfect synchronization.
8141 */
8142 if (backwards_tsc) {
8143 u64 delta_cyc = max_tsc - local_tsc;
8144 list_for_each_entry(kvm, &vm_list, vm_list) {
8145 kvm->arch.backwards_tsc_observed = true;
8146 kvm_for_each_vcpu(i, vcpu, kvm) {
8147 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8148 vcpu->arch.last_host_tsc = local_tsc;
8149 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8150 }
8151
8152 /*
8153 * We have to disable TSC offset matching.. if you were
8154 * booting a VM while issuing an S4 host suspend....
8155 * you may have some problem. Solving this issue is
8156 * left as an exercise to the reader.
8157 */
8158 kvm->arch.last_tsc_nsec = 0;
8159 kvm->arch.last_tsc_write = 0;
8160 }
8161
8162 }
8163 return 0;
8164 }
8165
8166 void kvm_arch_hardware_disable(void)
8167 {
8168 kvm_x86_ops->hardware_disable();
8169 drop_user_return_notifiers();
8170 }
8171
8172 int kvm_arch_hardware_setup(void)
8173 {
8174 int r;
8175
8176 r = kvm_x86_ops->hardware_setup();
8177 if (r != 0)
8178 return r;
8179
8180 if (kvm_has_tsc_control) {
8181 /*
8182 * Make sure the user can only configure tsc_khz values that
8183 * fit into a signed integer.
8184 * A min value is not calculated needed because it will always
8185 * be 1 on all machines.
8186 */
8187 u64 max = min(0x7fffffffULL,
8188 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8189 kvm_max_guest_tsc_khz = max;
8190
8191 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8192 }
8193
8194 kvm_init_msr_list();
8195 return 0;
8196 }
8197
8198 void kvm_arch_hardware_unsetup(void)
8199 {
8200 kvm_x86_ops->hardware_unsetup();
8201 }
8202
8203 void kvm_arch_check_processor_compat(void *rtn)
8204 {
8205 kvm_x86_ops->check_processor_compatibility(rtn);
8206 }
8207
8208 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8209 {
8210 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8211 }
8212 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8213
8214 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8215 {
8216 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8217 }
8218
8219 struct static_key kvm_no_apic_vcpu __read_mostly;
8220 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8221
8222 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8223 {
8224 struct page *page;
8225 int r;
8226
8227 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8228 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8229 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8230 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8231 else
8232 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8233
8234 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8235 if (!page) {
8236 r = -ENOMEM;
8237 goto fail;
8238 }
8239 vcpu->arch.pio_data = page_address(page);
8240
8241 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8242
8243 r = kvm_mmu_create(vcpu);
8244 if (r < 0)
8245 goto fail_free_pio_data;
8246
8247 if (irqchip_in_kernel(vcpu->kvm)) {
8248 r = kvm_create_lapic(vcpu);
8249 if (r < 0)
8250 goto fail_mmu_destroy;
8251 } else
8252 static_key_slow_inc(&kvm_no_apic_vcpu);
8253
8254 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8255 GFP_KERNEL);
8256 if (!vcpu->arch.mce_banks) {
8257 r = -ENOMEM;
8258 goto fail_free_lapic;
8259 }
8260 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8261
8262 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8263 r = -ENOMEM;
8264 goto fail_free_mce_banks;
8265 }
8266
8267 fx_init(vcpu);
8268
8269 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8270
8271 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8272
8273 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8274
8275 kvm_async_pf_hash_reset(vcpu);
8276 kvm_pmu_init(vcpu);
8277
8278 vcpu->arch.pending_external_vector = -1;
8279 vcpu->arch.preempted_in_kernel = false;
8280
8281 kvm_hv_vcpu_init(vcpu);
8282
8283 return 0;
8284
8285 fail_free_mce_banks:
8286 kfree(vcpu->arch.mce_banks);
8287 fail_free_lapic:
8288 kvm_free_lapic(vcpu);
8289 fail_mmu_destroy:
8290 kvm_mmu_destroy(vcpu);
8291 fail_free_pio_data:
8292 free_page((unsigned long)vcpu->arch.pio_data);
8293 fail:
8294 return r;
8295 }
8296
8297 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8298 {
8299 int idx;
8300
8301 kvm_hv_vcpu_uninit(vcpu);
8302 kvm_pmu_destroy(vcpu);
8303 kfree(vcpu->arch.mce_banks);
8304 kvm_free_lapic(vcpu);
8305 idx = srcu_read_lock(&vcpu->kvm->srcu);
8306 kvm_mmu_destroy(vcpu);
8307 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8308 free_page((unsigned long)vcpu->arch.pio_data);
8309 if (!lapic_in_kernel(vcpu))
8310 static_key_slow_dec(&kvm_no_apic_vcpu);
8311 }
8312
8313 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8314 {
8315 vcpu->arch.l1tf_flush_l1d = true;
8316 kvm_x86_ops->sched_in(vcpu, cpu);
8317 }
8318
8319 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8320 {
8321 if (type)
8322 return -EINVAL;
8323
8324 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8325 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8326 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8327 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8328 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8329
8330 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8331 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8332 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8333 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8334 &kvm->arch.irq_sources_bitmap);
8335
8336 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8337 mutex_init(&kvm->arch.apic_map_lock);
8338 mutex_init(&kvm->arch.hyperv.hv_lock);
8339 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8340
8341 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8342 pvclock_update_vm_gtod_copy(kvm);
8343
8344 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8345 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8346
8347 kvm_page_track_init(kvm);
8348 kvm_mmu_init_vm(kvm);
8349
8350 if (kvm_x86_ops->vm_init)
8351 return kvm_x86_ops->vm_init(kvm);
8352
8353 return 0;
8354 }
8355
8356 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8357 {
8358 int r;
8359 r = vcpu_load(vcpu);
8360 BUG_ON(r);
8361 kvm_mmu_unload(vcpu);
8362 vcpu_put(vcpu);
8363 }
8364
8365 static void kvm_free_vcpus(struct kvm *kvm)
8366 {
8367 unsigned int i;
8368 struct kvm_vcpu *vcpu;
8369
8370 /*
8371 * Unpin any mmu pages first.
8372 */
8373 kvm_for_each_vcpu(i, vcpu, kvm) {
8374 kvm_clear_async_pf_completion_queue(vcpu);
8375 kvm_unload_vcpu_mmu(vcpu);
8376 }
8377 kvm_for_each_vcpu(i, vcpu, kvm)
8378 kvm_arch_vcpu_free(vcpu);
8379
8380 mutex_lock(&kvm->lock);
8381 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8382 kvm->vcpus[i] = NULL;
8383
8384 atomic_set(&kvm->online_vcpus, 0);
8385 mutex_unlock(&kvm->lock);
8386 }
8387
8388 void kvm_arch_sync_events(struct kvm *kvm)
8389 {
8390 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8391 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8392 kvm_free_pit(kvm);
8393 }
8394
8395 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8396 {
8397 int i, r;
8398 unsigned long hva;
8399 struct kvm_memslots *slots = kvm_memslots(kvm);
8400 struct kvm_memory_slot *slot, old;
8401
8402 /* Called with kvm->slots_lock held. */
8403 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8404 return -EINVAL;
8405
8406 slot = id_to_memslot(slots, id);
8407 if (size) {
8408 if (slot->npages)
8409 return -EEXIST;
8410
8411 /*
8412 * MAP_SHARED to prevent internal slot pages from being moved
8413 * by fork()/COW.
8414 */
8415 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8416 MAP_SHARED | MAP_ANONYMOUS, 0);
8417 if (IS_ERR((void *)hva))
8418 return PTR_ERR((void *)hva);
8419 } else {
8420 if (!slot->npages)
8421 return 0;
8422
8423 hva = 0;
8424 }
8425
8426 old = *slot;
8427 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8428 struct kvm_userspace_memory_region m;
8429
8430 m.slot = id | (i << 16);
8431 m.flags = 0;
8432 m.guest_phys_addr = gpa;
8433 m.userspace_addr = hva;
8434 m.memory_size = size;
8435 r = __kvm_set_memory_region(kvm, &m);
8436 if (r < 0)
8437 return r;
8438 }
8439
8440 if (!size)
8441 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8442
8443 return 0;
8444 }
8445 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8446
8447 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8448 {
8449 int r;
8450
8451 mutex_lock(&kvm->slots_lock);
8452 r = __x86_set_memory_region(kvm, id, gpa, size);
8453 mutex_unlock(&kvm->slots_lock);
8454
8455 return r;
8456 }
8457 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8458
8459 void kvm_arch_destroy_vm(struct kvm *kvm)
8460 {
8461 if (current->mm == kvm->mm) {
8462 /*
8463 * Free memory regions allocated on behalf of userspace,
8464 * unless the the memory map has changed due to process exit
8465 * or fd copying.
8466 */
8467 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8468 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8469 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8470 }
8471 if (kvm_x86_ops->vm_destroy)
8472 kvm_x86_ops->vm_destroy(kvm);
8473 kvm_pic_destroy(kvm);
8474 kvm_ioapic_destroy(kvm);
8475 kvm_free_vcpus(kvm);
8476 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8477 kvm_mmu_uninit_vm(kvm);
8478 kvm_page_track_cleanup(kvm);
8479 }
8480
8481 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8482 struct kvm_memory_slot *dont)
8483 {
8484 int i;
8485
8486 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8487 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8488 kvfree(free->arch.rmap[i]);
8489 free->arch.rmap[i] = NULL;
8490 }
8491 if (i == 0)
8492 continue;
8493
8494 if (!dont || free->arch.lpage_info[i - 1] !=
8495 dont->arch.lpage_info[i - 1]) {
8496 kvfree(free->arch.lpage_info[i - 1]);
8497 free->arch.lpage_info[i - 1] = NULL;
8498 }
8499 }
8500
8501 kvm_page_track_free_memslot(free, dont);
8502 }
8503
8504 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8505 unsigned long npages)
8506 {
8507 int i;
8508
8509 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8510 struct kvm_lpage_info *linfo;
8511 unsigned long ugfn;
8512 int lpages;
8513 int level = i + 1;
8514
8515 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8516 slot->base_gfn, level) + 1;
8517
8518 slot->arch.rmap[i] =
8519 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8520 if (!slot->arch.rmap[i])
8521 goto out_free;
8522 if (i == 0)
8523 continue;
8524
8525 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8526 if (!linfo)
8527 goto out_free;
8528
8529 slot->arch.lpage_info[i - 1] = linfo;
8530
8531 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8532 linfo[0].disallow_lpage = 1;
8533 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8534 linfo[lpages - 1].disallow_lpage = 1;
8535 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8536 /*
8537 * If the gfn and userspace address are not aligned wrt each
8538 * other, or if explicitly asked to, disable large page
8539 * support for this slot
8540 */
8541 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8542 !kvm_largepages_enabled()) {
8543 unsigned long j;
8544
8545 for (j = 0; j < lpages; ++j)
8546 linfo[j].disallow_lpage = 1;
8547 }
8548 }
8549
8550 if (kvm_page_track_create_memslot(slot, npages))
8551 goto out_free;
8552
8553 return 0;
8554
8555 out_free:
8556 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8557 kvfree(slot->arch.rmap[i]);
8558 slot->arch.rmap[i] = NULL;
8559 if (i == 0)
8560 continue;
8561
8562 kvfree(slot->arch.lpage_info[i - 1]);
8563 slot->arch.lpage_info[i - 1] = NULL;
8564 }
8565 return -ENOMEM;
8566 }
8567
8568 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8569 {
8570 /*
8571 * memslots->generation has been incremented.
8572 * mmio generation may have reached its maximum value.
8573 */
8574 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8575 }
8576
8577 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8578 struct kvm_memory_slot *memslot,
8579 const struct kvm_userspace_memory_region *mem,
8580 enum kvm_mr_change change)
8581 {
8582 return 0;
8583 }
8584
8585 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8586 struct kvm_memory_slot *new)
8587 {
8588 /* Still write protect RO slot */
8589 if (new->flags & KVM_MEM_READONLY) {
8590 kvm_mmu_slot_remove_write_access(kvm, new);
8591 return;
8592 }
8593
8594 /*
8595 * Call kvm_x86_ops dirty logging hooks when they are valid.
8596 *
8597 * kvm_x86_ops->slot_disable_log_dirty is called when:
8598 *
8599 * - KVM_MR_CREATE with dirty logging is disabled
8600 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8601 *
8602 * The reason is, in case of PML, we need to set D-bit for any slots
8603 * with dirty logging disabled in order to eliminate unnecessary GPA
8604 * logging in PML buffer (and potential PML buffer full VMEXT). This
8605 * guarantees leaving PML enabled during guest's lifetime won't have
8606 * any additonal overhead from PML when guest is running with dirty
8607 * logging disabled for memory slots.
8608 *
8609 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8610 * to dirty logging mode.
8611 *
8612 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8613 *
8614 * In case of write protect:
8615 *
8616 * Write protect all pages for dirty logging.
8617 *
8618 * All the sptes including the large sptes which point to this
8619 * slot are set to readonly. We can not create any new large
8620 * spte on this slot until the end of the logging.
8621 *
8622 * See the comments in fast_page_fault().
8623 */
8624 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8625 if (kvm_x86_ops->slot_enable_log_dirty)
8626 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8627 else
8628 kvm_mmu_slot_remove_write_access(kvm, new);
8629 } else {
8630 if (kvm_x86_ops->slot_disable_log_dirty)
8631 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8632 }
8633 }
8634
8635 void kvm_arch_commit_memory_region(struct kvm *kvm,
8636 const struct kvm_userspace_memory_region *mem,
8637 const struct kvm_memory_slot *old,
8638 const struct kvm_memory_slot *new,
8639 enum kvm_mr_change change)
8640 {
8641 int nr_mmu_pages = 0;
8642
8643 if (!kvm->arch.n_requested_mmu_pages)
8644 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8645
8646 if (nr_mmu_pages)
8647 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8648
8649 /*
8650 * Dirty logging tracks sptes in 4k granularity, meaning that large
8651 * sptes have to be split. If live migration is successful, the guest
8652 * in the source machine will be destroyed and large sptes will be
8653 * created in the destination. However, if the guest continues to run
8654 * in the source machine (for example if live migration fails), small
8655 * sptes will remain around and cause bad performance.
8656 *
8657 * Scan sptes if dirty logging has been stopped, dropping those
8658 * which can be collapsed into a single large-page spte. Later
8659 * page faults will create the large-page sptes.
8660 */
8661 if ((change != KVM_MR_DELETE) &&
8662 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8663 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8664 kvm_mmu_zap_collapsible_sptes(kvm, new);
8665
8666 /*
8667 * Set up write protection and/or dirty logging for the new slot.
8668 *
8669 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8670 * been zapped so no dirty logging staff is needed for old slot. For
8671 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8672 * new and it's also covered when dealing with the new slot.
8673 *
8674 * FIXME: const-ify all uses of struct kvm_memory_slot.
8675 */
8676 if (change != KVM_MR_DELETE)
8677 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8678 }
8679
8680 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8681 {
8682 kvm_mmu_invalidate_zap_all_pages(kvm);
8683 }
8684
8685 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8686 struct kvm_memory_slot *slot)
8687 {
8688 kvm_page_track_flush_slot(kvm, slot);
8689 }
8690
8691 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8692 {
8693 if (!list_empty_careful(&vcpu->async_pf.done))
8694 return true;
8695
8696 if (kvm_apic_has_events(vcpu))
8697 return true;
8698
8699 if (vcpu->arch.pv.pv_unhalted)
8700 return true;
8701
8702 if (vcpu->arch.exception.pending)
8703 return true;
8704
8705 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8706 (vcpu->arch.nmi_pending &&
8707 kvm_x86_ops->nmi_allowed(vcpu)))
8708 return true;
8709
8710 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8711 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8712 return true;
8713
8714 if (kvm_arch_interrupt_allowed(vcpu) &&
8715 kvm_cpu_has_interrupt(vcpu))
8716 return true;
8717
8718 if (kvm_hv_has_stimer_pending(vcpu))
8719 return true;
8720
8721 return false;
8722 }
8723
8724 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8725 {
8726 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8727 }
8728
8729 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8730 {
8731 return vcpu->arch.preempted_in_kernel;
8732 }
8733
8734 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8735 {
8736 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8737 }
8738
8739 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8740 {
8741 return kvm_x86_ops->interrupt_allowed(vcpu);
8742 }
8743
8744 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8745 {
8746 if (is_64_bit_mode(vcpu))
8747 return kvm_rip_read(vcpu);
8748 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8749 kvm_rip_read(vcpu));
8750 }
8751 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8752
8753 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8754 {
8755 return kvm_get_linear_rip(vcpu) == linear_rip;
8756 }
8757 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8758
8759 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8760 {
8761 unsigned long rflags;
8762
8763 rflags = kvm_x86_ops->get_rflags(vcpu);
8764 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8765 rflags &= ~X86_EFLAGS_TF;
8766 return rflags;
8767 }
8768 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8769
8770 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8771 {
8772 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8773 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8774 rflags |= X86_EFLAGS_TF;
8775 kvm_x86_ops->set_rflags(vcpu, rflags);
8776 }
8777
8778 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8779 {
8780 __kvm_set_rflags(vcpu, rflags);
8781 kvm_make_request(KVM_REQ_EVENT, vcpu);
8782 }
8783 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8784
8785 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8786 {
8787 int r;
8788
8789 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8790 work->wakeup_all)
8791 return;
8792
8793 r = kvm_mmu_reload(vcpu);
8794 if (unlikely(r))
8795 return;
8796
8797 if (!vcpu->arch.mmu.direct_map &&
8798 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8799 return;
8800
8801 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8802 }
8803
8804 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8805 {
8806 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8807 }
8808
8809 static inline u32 kvm_async_pf_next_probe(u32 key)
8810 {
8811 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8812 }
8813
8814 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8815 {
8816 u32 key = kvm_async_pf_hash_fn(gfn);
8817
8818 while (vcpu->arch.apf.gfns[key] != ~0)
8819 key = kvm_async_pf_next_probe(key);
8820
8821 vcpu->arch.apf.gfns[key] = gfn;
8822 }
8823
8824 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8825 {
8826 int i;
8827 u32 key = kvm_async_pf_hash_fn(gfn);
8828
8829 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8830 (vcpu->arch.apf.gfns[key] != gfn &&
8831 vcpu->arch.apf.gfns[key] != ~0); i++)
8832 key = kvm_async_pf_next_probe(key);
8833
8834 return key;
8835 }
8836
8837 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8838 {
8839 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8840 }
8841
8842 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8843 {
8844 u32 i, j, k;
8845
8846 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8847 while (true) {
8848 vcpu->arch.apf.gfns[i] = ~0;
8849 do {
8850 j = kvm_async_pf_next_probe(j);
8851 if (vcpu->arch.apf.gfns[j] == ~0)
8852 return;
8853 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8854 /*
8855 * k lies cyclically in ]i,j]
8856 * | i.k.j |
8857 * |....j i.k.| or |.k..j i...|
8858 */
8859 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8860 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8861 i = j;
8862 }
8863 }
8864
8865 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8866 {
8867
8868 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8869 sizeof(val));
8870 }
8871
8872 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8873 {
8874
8875 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8876 sizeof(u32));
8877 }
8878
8879 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8880 struct kvm_async_pf *work)
8881 {
8882 struct x86_exception fault;
8883
8884 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8885 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8886
8887 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8888 (vcpu->arch.apf.send_user_only &&
8889 kvm_x86_ops->get_cpl(vcpu) == 0))
8890 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8891 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8892 fault.vector = PF_VECTOR;
8893 fault.error_code_valid = true;
8894 fault.error_code = 0;
8895 fault.nested_page_fault = false;
8896 fault.address = work->arch.token;
8897 fault.async_page_fault = true;
8898 kvm_inject_page_fault(vcpu, &fault);
8899 }
8900 }
8901
8902 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8903 struct kvm_async_pf *work)
8904 {
8905 struct x86_exception fault;
8906 u32 val;
8907
8908 if (work->wakeup_all)
8909 work->arch.token = ~0; /* broadcast wakeup */
8910 else
8911 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8912 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8913
8914 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8915 !apf_get_user(vcpu, &val)) {
8916 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8917 vcpu->arch.exception.pending &&
8918 vcpu->arch.exception.nr == PF_VECTOR &&
8919 !apf_put_user(vcpu, 0)) {
8920 vcpu->arch.exception.injected = false;
8921 vcpu->arch.exception.pending = false;
8922 vcpu->arch.exception.nr = 0;
8923 vcpu->arch.exception.has_error_code = false;
8924 vcpu->arch.exception.error_code = 0;
8925 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8926 fault.vector = PF_VECTOR;
8927 fault.error_code_valid = true;
8928 fault.error_code = 0;
8929 fault.nested_page_fault = false;
8930 fault.address = work->arch.token;
8931 fault.async_page_fault = true;
8932 kvm_inject_page_fault(vcpu, &fault);
8933 }
8934 }
8935 vcpu->arch.apf.halted = false;
8936 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8937 }
8938
8939 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8940 {
8941 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8942 return true;
8943 else
8944 return kvm_can_do_async_pf(vcpu);
8945 }
8946
8947 void kvm_arch_start_assignment(struct kvm *kvm)
8948 {
8949 atomic_inc(&kvm->arch.assigned_device_count);
8950 }
8951 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8952
8953 void kvm_arch_end_assignment(struct kvm *kvm)
8954 {
8955 atomic_dec(&kvm->arch.assigned_device_count);
8956 }
8957 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8958
8959 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8960 {
8961 return atomic_read(&kvm->arch.assigned_device_count);
8962 }
8963 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8964
8965 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8966 {
8967 atomic_inc(&kvm->arch.noncoherent_dma_count);
8968 }
8969 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8970
8971 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8972 {
8973 atomic_dec(&kvm->arch.noncoherent_dma_count);
8974 }
8975 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8976
8977 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8978 {
8979 return atomic_read(&kvm->arch.noncoherent_dma_count);
8980 }
8981 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8982
8983 bool kvm_arch_has_irq_bypass(void)
8984 {
8985 return kvm_x86_ops->update_pi_irte != NULL;
8986 }
8987
8988 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8989 struct irq_bypass_producer *prod)
8990 {
8991 struct kvm_kernel_irqfd *irqfd =
8992 container_of(cons, struct kvm_kernel_irqfd, consumer);
8993
8994 irqfd->producer = prod;
8995
8996 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8997 prod->irq, irqfd->gsi, 1);
8998 }
8999
9000 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9001 struct irq_bypass_producer *prod)
9002 {
9003 int ret;
9004 struct kvm_kernel_irqfd *irqfd =
9005 container_of(cons, struct kvm_kernel_irqfd, consumer);
9006
9007 WARN_ON(irqfd->producer != prod);
9008 irqfd->producer = NULL;
9009
9010 /*
9011 * When producer of consumer is unregistered, we change back to
9012 * remapped mode, so we can re-use the current implementation
9013 * when the irq is masked/disabled or the consumer side (KVM
9014 * int this case doesn't want to receive the interrupts.
9015 */
9016 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9017 if (ret)
9018 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9019 " fails: %d\n", irqfd->consumer.token, ret);
9020 }
9021
9022 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9023 uint32_t guest_irq, bool set)
9024 {
9025 if (!kvm_x86_ops->update_pi_irte)
9026 return -EINVAL;
9027
9028 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9029 }
9030
9031 bool kvm_vector_hashing_enabled(void)
9032 {
9033 return vector_hashing;
9034 }
9035 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9036
9037 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9038 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9039 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9040 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9041 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9042 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9043 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9044 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9045 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9046 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9047 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9048 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9049 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9050 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9051 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9052 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9053 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9054 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9055 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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