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[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define CREATE_TRACE_POINTS
72 #include "trace.h"
73
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
82 /* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86 #ifdef CONFIG_X86_64
87 static
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 #else
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
91 #endif
92
93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void enter_smm(struct kvm_vcpu *vcpu);
102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103
104 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
105 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106
107 static bool __read_mostly ignore_msrs = 0;
108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109
110 static bool __read_mostly report_ignored_msrs = true;
111 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
113 unsigned int min_timer_period_us = 500;
114 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
116 static bool __read_mostly kvmclock_periodic_sync = true;
117 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
119 bool __read_mostly kvm_has_tsc_control;
120 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
121 u32 __read_mostly kvm_max_guest_tsc_khz;
122 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
123 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125 u64 __read_mostly kvm_max_tsc_scaling_ratio;
126 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
127 u64 __read_mostly kvm_default_tsc_scaling_ratio;
128 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
129
130 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
131 static u32 __read_mostly tsc_tolerance_ppm = 250;
132 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
134 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
135 unsigned int __read_mostly lapic_timer_advance_ns = 0;
136 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
138 static bool __read_mostly vector_hashing = true;
139 module_param(vector_hashing, bool, S_IRUGO);
140
141 #define KVM_NR_SHARED_MSRS 16
142
143 struct kvm_shared_msrs_global {
144 int nr;
145 u32 msrs[KVM_NR_SHARED_MSRS];
146 };
147
148 struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
155 };
156
157 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
158 static struct kvm_shared_msrs __percpu *shared_msrs;
159
160 struct kvm_stats_debugfs_item debugfs_entries[] = {
161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
171 { "halt_exits", VCPU_STAT(halt_exits) },
172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
176 { "hypercalls", VCPU_STAT(hypercalls) },
177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
184 { "irq_injections", VCPU_STAT(irq_injections) },
185 { "nmi_injections", VCPU_STAT(nmi_injections) },
186 { "req_event", VCPU_STAT(req_event) },
187 { "l1d_flush", VCPU_STAT(l1d_flush) },
188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
195 { "mmu_unsync", VM_STAT(mmu_unsync) },
196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
197 { "largepages", VM_STAT(lpages) },
198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
200 { NULL }
201 };
202
203 u64 __read_mostly host_xcr0;
204
205 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
206
207 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208 {
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212 }
213
214 static void kvm_on_user_return(struct user_return_notifier *urn)
215 {
216 unsigned slot;
217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
219 struct kvm_shared_msr_values *values;
220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
237 }
238 }
239 }
240
241 static void shared_msr_update(unsigned slot, u32 msr)
242 {
243 u64 value;
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246
247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256 }
257
258 void kvm_define_shared_msr(unsigned slot, u32 msr)
259 {
260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
261 shared_msrs_global.msrs[slot] = msr;
262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
264 }
265 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267 static void kvm_shared_msr_cpu_online(void)
268 {
269 unsigned i;
270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
272 shared_msr_update(i, shared_msrs_global.msrs[i]);
273 }
274
275 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
276 {
277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
279 int err;
280
281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
282 return 0;
283 smsr->values[slot].curr = value;
284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
293 return 0;
294 }
295 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
297 static void drop_user_return_notifiers(void)
298 {
299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304 }
305
306 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307 {
308 return vcpu->arch.apic_base;
309 }
310 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
312 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313 {
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
320
321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
323 if (!msr_info->host_initiated &&
324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
332 }
333 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
335 asmlinkage __visible void kvm_spurious_fault(void)
336 {
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339 }
340 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
342 #define EXCPT_BENIGN 0
343 #define EXCPT_CONTRIBUTORY 1
344 #define EXCPT_PF 2
345
346 static int exception_class(int vector)
347 {
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361 }
362
363 #define EXCPT_FAULT 0
364 #define EXCPT_TRAP 1
365 #define EXCPT_ABORT 2
366 #define EXCPT_INTERRUPT 3
367
368 static int exception_type(int vector)
369 {
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386 }
387
388 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
391 {
392 u32 prev_nr;
393 int class1, class2;
394
395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
398 queue:
399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
438 vcpu->arch.exception.pending = true;
439 vcpu->arch.exception.injected = false;
440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448 }
449
450 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451 {
452 kvm_multiple_exception(vcpu, nr, false, 0, false);
453 }
454 EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
456 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457 {
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459 }
460 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
462 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
463 {
464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
470 }
471 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
472
473 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
474 {
475 ++vcpu->stat.pf_guest;
476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
483 }
484 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
485
486 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
487 {
488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
490 else
491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
492
493 return fault->nested_page_fault;
494 }
495
496 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497 {
498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
500 }
501 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
503 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504 {
505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
506 }
507 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
509 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510 {
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512 }
513 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
515 /*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
520 {
521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
525 }
526 EXPORT_SYMBOL_GPL(kvm_require_cpl);
527
528 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529 {
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535 }
536 EXPORT_SYMBOL_GPL(kvm_require_dr);
537
538 /*
539 * This function will be used to read from the physical memory of the currently
540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
541 * can read from guest physical or from the guest's guest physical memory.
542 */
543 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546 {
547 struct x86_exception exception;
548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
559 }
560 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
562 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
563 void *data, int offset, int len, u32 access)
564 {
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567 }
568
569 /*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
572 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
573 {
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
579
580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
588 if ((pdpte[i] & PT_PRESENT_MASK) &&
589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
602 out:
603
604 return ret;
605 }
606 EXPORT_SYMBOL_GPL(load_pdptrs);
607
608 bool pdptrs_changed(struct kvm_vcpu *vcpu)
609 {
610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
611 bool changed = true;
612 int offset;
613 gfn_t gfn;
614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
627 if (r < 0)
628 goto out;
629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
630 out:
631
632 return changed;
633 }
634 EXPORT_SYMBOL_GPL(pdptrs_changed);
635
636 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
637 {
638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
640
641 cr0 |= X86_CR0_ET;
642
643 #ifdef CONFIG_X86_64
644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
646 #endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
649
650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
652
653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657 #ifdef CONFIG_X86_64
658 if ((vcpu->arch.efer & EFER_LME)) {
659 int cs_db, cs_l;
660
661 if (!is_pae(vcpu))
662 return 1;
663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
664 if (cs_l)
665 return 1;
666 } else
667 #endif
668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
670 return 1;
671 }
672
673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
676 kvm_x86_ops->set_cr0(vcpu, cr0);
677
678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
679 kvm_clear_async_pf_completion_queue(vcpu);
680 kvm_async_pf_hash_reset(vcpu);
681 }
682
683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
685
686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
691 return 0;
692 }
693 EXPORT_SYMBOL_GPL(kvm_set_cr0);
694
695 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
696 {
697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
698 }
699 EXPORT_SYMBOL_GPL(kvm_lmsw);
700
701 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702 {
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709 }
710
711 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712 {
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718 }
719
720 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
721 {
722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
724 u64 valid_bits;
725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
729 if (!(xcr0 & XFEATURE_MASK_FP))
730 return 1;
731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
732 return 1;
733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
740 if (xcr0 & ~valid_bits)
741 return 1;
742
743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
745 return 1;
746
747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
749 return 1;
750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
751 return 1;
752 }
753 vcpu->arch.xcr0 = xcr0;
754
755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
756 kvm_update_cpuid(vcpu);
757 return 0;
758 }
759
760 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761 {
762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768 }
769 EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
771 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
772 {
773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
776
777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
779
780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
781 return 1;
782
783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
784 return 1;
785
786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
787 return 1;
788
789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
790 return 1;
791
792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
793 return 1;
794
795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
796 return 1;
797
798 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
799 return 1;
800
801 if (is_long_mode(vcpu)) {
802 if (!(cr4 & X86_CR4_PAE))
803 return 1;
804 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
805 && ((cr4 ^ old_cr4) & pdptr_bits)
806 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
807 kvm_read_cr3(vcpu)))
808 return 1;
809
810 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
811 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
812 return 1;
813
814 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
815 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
816 return 1;
817 }
818
819 if (kvm_x86_ops->set_cr4(vcpu, cr4))
820 return 1;
821
822 if (((cr4 ^ old_cr4) & pdptr_bits) ||
823 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
824 kvm_mmu_reset_context(vcpu);
825
826 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
827 kvm_update_cpuid(vcpu);
828
829 return 0;
830 }
831 EXPORT_SYMBOL_GPL(kvm_set_cr4);
832
833 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
834 {
835 #ifdef CONFIG_X86_64
836 cr3 &= ~CR3_PCID_INVD;
837 #endif
838
839 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
840 kvm_mmu_sync_roots(vcpu);
841 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
842 return 0;
843 }
844
845 if (is_long_mode(vcpu) &&
846 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
847 return 1;
848 else if (is_pae(vcpu) && is_paging(vcpu) &&
849 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
850 return 1;
851
852 vcpu->arch.cr3 = cr3;
853 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
854 kvm_mmu_new_cr3(vcpu);
855 return 0;
856 }
857 EXPORT_SYMBOL_GPL(kvm_set_cr3);
858
859 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
860 {
861 if (cr8 & CR8_RESERVED_BITS)
862 return 1;
863 if (lapic_in_kernel(vcpu))
864 kvm_lapic_set_tpr(vcpu, cr8);
865 else
866 vcpu->arch.cr8 = cr8;
867 return 0;
868 }
869 EXPORT_SYMBOL_GPL(kvm_set_cr8);
870
871 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
872 {
873 if (lapic_in_kernel(vcpu))
874 return kvm_lapic_get_cr8(vcpu);
875 else
876 return vcpu->arch.cr8;
877 }
878 EXPORT_SYMBOL_GPL(kvm_get_cr8);
879
880 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
881 {
882 int i;
883
884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
885 for (i = 0; i < KVM_NR_DB_REGS; i++)
886 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
887 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
888 }
889 }
890
891 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
892 {
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
895 }
896
897 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
898 {
899 unsigned long dr7;
900
901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 dr7 = vcpu->arch.guest_debug_dr7;
903 else
904 dr7 = vcpu->arch.dr7;
905 kvm_x86_ops->set_dr7(vcpu, dr7);
906 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
907 if (dr7 & DR7_BP_EN_MASK)
908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
909 }
910
911 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
912 {
913 u64 fixed = DR6_FIXED_1;
914
915 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
916 fixed |= DR6_RTM;
917 return fixed;
918 }
919
920 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921 {
922 switch (dr) {
923 case 0 ... 3:
924 vcpu->arch.db[dr] = val;
925 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
926 vcpu->arch.eff_db[dr] = val;
927 break;
928 case 4:
929 /* fall through */
930 case 6:
931 if (val & 0xffffffff00000000ULL)
932 return -1; /* #GP */
933 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
934 kvm_update_dr6(vcpu);
935 break;
936 case 5:
937 /* fall through */
938 default: /* 7 */
939 if (val & 0xffffffff00000000ULL)
940 return -1; /* #GP */
941 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
942 kvm_update_dr7(vcpu);
943 break;
944 }
945
946 return 0;
947 }
948
949 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
950 {
951 if (__kvm_set_dr(vcpu, dr, val)) {
952 kvm_inject_gp(vcpu, 0);
953 return 1;
954 }
955 return 0;
956 }
957 EXPORT_SYMBOL_GPL(kvm_set_dr);
958
959 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
960 {
961 switch (dr) {
962 case 0 ... 3:
963 *val = vcpu->arch.db[dr];
964 break;
965 case 4:
966 /* fall through */
967 case 6:
968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
969 *val = vcpu->arch.dr6;
970 else
971 *val = kvm_x86_ops->get_dr6(vcpu);
972 break;
973 case 5:
974 /* fall through */
975 default: /* 7 */
976 *val = vcpu->arch.dr7;
977 break;
978 }
979 return 0;
980 }
981 EXPORT_SYMBOL_GPL(kvm_get_dr);
982
983 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
984 {
985 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
986 u64 data;
987 int err;
988
989 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
990 if (err)
991 return err;
992 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
993 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
994 return err;
995 }
996 EXPORT_SYMBOL_GPL(kvm_rdpmc);
997
998 /*
999 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1000 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1001 *
1002 * This list is modified at module load time to reflect the
1003 * capabilities of the host cpu. This capabilities test skips MSRs that are
1004 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1005 * may depend on host virtualization features rather than host cpu features.
1006 */
1007
1008 static u32 msrs_to_save[] = {
1009 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1010 MSR_STAR,
1011 #ifdef CONFIG_X86_64
1012 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1013 #endif
1014 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1015 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1016 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1017 };
1018
1019 static unsigned num_msrs_to_save;
1020
1021 static u32 emulated_msrs[] = {
1022 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1023 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1024 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1025 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1026 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1027 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1028 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1029 HV_X64_MSR_RESET,
1030 HV_X64_MSR_VP_INDEX,
1031 HV_X64_MSR_VP_RUNTIME,
1032 HV_X64_MSR_SCONTROL,
1033 HV_X64_MSR_STIMER0_CONFIG,
1034 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1035 MSR_KVM_PV_EOI_EN,
1036
1037 MSR_IA32_TSC_ADJUST,
1038 MSR_IA32_TSCDEADLINE,
1039 MSR_IA32_MISC_ENABLE,
1040 MSR_IA32_MCG_STATUS,
1041 MSR_IA32_MCG_CTL,
1042 MSR_IA32_MCG_EXT_CTL,
1043 MSR_IA32_SMBASE,
1044 MSR_PLATFORM_INFO,
1045 MSR_MISC_FEATURES_ENABLES,
1046 MSR_AMD64_VIRT_SPEC_CTRL,
1047 };
1048
1049 static unsigned num_emulated_msrs;
1050
1051 /*
1052 * List of msr numbers which are used to expose MSR-based features that
1053 * can be used by a hypervisor to validate requested CPU features.
1054 */
1055 static u32 msr_based_features[] = {
1056 };
1057
1058 static unsigned int num_msr_based_features;
1059
1060 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1061 {
1062 switch (msr->index) {
1063 default:
1064 if (kvm_x86_ops->get_msr_feature(msr))
1065 return 1;
1066 }
1067 return 0;
1068 }
1069
1070 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1071 {
1072 struct kvm_msr_entry msr;
1073 int r;
1074
1075 msr.index = index;
1076 r = kvm_get_msr_feature(&msr);
1077 if (r)
1078 return r;
1079
1080 *data = msr.data;
1081
1082 return 0;
1083 }
1084
1085 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1086 {
1087 if (efer & efer_reserved_bits)
1088 return false;
1089
1090 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1091 return false;
1092
1093 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1094 return false;
1095
1096 return true;
1097 }
1098 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1099
1100 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1101 {
1102 u64 old_efer = vcpu->arch.efer;
1103
1104 if (!kvm_valid_efer(vcpu, efer))
1105 return 1;
1106
1107 if (is_paging(vcpu)
1108 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1109 return 1;
1110
1111 efer &= ~EFER_LMA;
1112 efer |= vcpu->arch.efer & EFER_LMA;
1113
1114 kvm_x86_ops->set_efer(vcpu, efer);
1115
1116 /* Update reserved bits */
1117 if ((efer ^ old_efer) & EFER_NX)
1118 kvm_mmu_reset_context(vcpu);
1119
1120 return 0;
1121 }
1122
1123 void kvm_enable_efer_bits(u64 mask)
1124 {
1125 efer_reserved_bits &= ~mask;
1126 }
1127 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1128
1129 /*
1130 * Writes msr value into into the appropriate "register".
1131 * Returns 0 on success, non-0 otherwise.
1132 * Assumes vcpu_load() was already called.
1133 */
1134 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1135 {
1136 switch (msr->index) {
1137 case MSR_FS_BASE:
1138 case MSR_GS_BASE:
1139 case MSR_KERNEL_GS_BASE:
1140 case MSR_CSTAR:
1141 case MSR_LSTAR:
1142 if (is_noncanonical_address(msr->data, vcpu))
1143 return 1;
1144 break;
1145 case MSR_IA32_SYSENTER_EIP:
1146 case MSR_IA32_SYSENTER_ESP:
1147 /*
1148 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1149 * non-canonical address is written on Intel but not on
1150 * AMD (which ignores the top 32-bits, because it does
1151 * not implement 64-bit SYSENTER).
1152 *
1153 * 64-bit code should hence be able to write a non-canonical
1154 * value on AMD. Making the address canonical ensures that
1155 * vmentry does not fail on Intel after writing a non-canonical
1156 * value, and that something deterministic happens if the guest
1157 * invokes 64-bit SYSENTER.
1158 */
1159 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1160 }
1161 return kvm_x86_ops->set_msr(vcpu, msr);
1162 }
1163 EXPORT_SYMBOL_GPL(kvm_set_msr);
1164
1165 /*
1166 * Adapt set_msr() to msr_io()'s calling convention
1167 */
1168 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1169 {
1170 struct msr_data msr;
1171 int r;
1172
1173 msr.index = index;
1174 msr.host_initiated = true;
1175 r = kvm_get_msr(vcpu, &msr);
1176 if (r)
1177 return r;
1178
1179 *data = msr.data;
1180 return 0;
1181 }
1182
1183 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1184 {
1185 struct msr_data msr;
1186
1187 msr.data = *data;
1188 msr.index = index;
1189 msr.host_initiated = true;
1190 return kvm_set_msr(vcpu, &msr);
1191 }
1192
1193 #ifdef CONFIG_X86_64
1194 struct pvclock_gtod_data {
1195 seqcount_t seq;
1196
1197 struct { /* extract of a clocksource struct */
1198 int vclock_mode;
1199 u64 cycle_last;
1200 u64 mask;
1201 u32 mult;
1202 u32 shift;
1203 } clock;
1204
1205 u64 boot_ns;
1206 u64 nsec_base;
1207 u64 wall_time_sec;
1208 };
1209
1210 static struct pvclock_gtod_data pvclock_gtod_data;
1211
1212 static void update_pvclock_gtod(struct timekeeper *tk)
1213 {
1214 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1215 u64 boot_ns;
1216
1217 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1218
1219 write_seqcount_begin(&vdata->seq);
1220
1221 /* copy pvclock gtod data */
1222 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1223 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1224 vdata->clock.mask = tk->tkr_mono.mask;
1225 vdata->clock.mult = tk->tkr_mono.mult;
1226 vdata->clock.shift = tk->tkr_mono.shift;
1227
1228 vdata->boot_ns = boot_ns;
1229 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1230
1231 vdata->wall_time_sec = tk->xtime_sec;
1232
1233 write_seqcount_end(&vdata->seq);
1234 }
1235 #endif
1236
1237 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1238 {
1239 /*
1240 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1241 * vcpu_enter_guest. This function is only called from
1242 * the physical CPU that is running vcpu.
1243 */
1244 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1245 }
1246
1247 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1248 {
1249 int version;
1250 int r;
1251 struct pvclock_wall_clock wc;
1252 struct timespec64 boot;
1253
1254 if (!wall_clock)
1255 return;
1256
1257 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1258 if (r)
1259 return;
1260
1261 if (version & 1)
1262 ++version; /* first time write, random junk */
1263
1264 ++version;
1265
1266 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1267 return;
1268
1269 /*
1270 * The guest calculates current wall clock time by adding
1271 * system time (updated by kvm_guest_time_update below) to the
1272 * wall clock specified here. guest system time equals host
1273 * system time for us, thus we must fill in host boot time here.
1274 */
1275 getboottime64(&boot);
1276
1277 if (kvm->arch.kvmclock_offset) {
1278 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1279 boot = timespec64_sub(boot, ts);
1280 }
1281 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1282 wc.nsec = boot.tv_nsec;
1283 wc.version = version;
1284
1285 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1286
1287 version++;
1288 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1289 }
1290
1291 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1292 {
1293 do_shl32_div32(dividend, divisor);
1294 return dividend;
1295 }
1296
1297 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1298 s8 *pshift, u32 *pmultiplier)
1299 {
1300 uint64_t scaled64;
1301 int32_t shift = 0;
1302 uint64_t tps64;
1303 uint32_t tps32;
1304
1305 tps64 = base_hz;
1306 scaled64 = scaled_hz;
1307 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1308 tps64 >>= 1;
1309 shift--;
1310 }
1311
1312 tps32 = (uint32_t)tps64;
1313 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1314 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1315 scaled64 >>= 1;
1316 else
1317 tps32 <<= 1;
1318 shift++;
1319 }
1320
1321 *pshift = shift;
1322 *pmultiplier = div_frac(scaled64, tps32);
1323
1324 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1325 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1326 }
1327
1328 #ifdef CONFIG_X86_64
1329 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1330 #endif
1331
1332 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1333 static unsigned long max_tsc_khz;
1334
1335 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1336 {
1337 u64 v = (u64)khz * (1000000 + ppm);
1338 do_div(v, 1000000);
1339 return v;
1340 }
1341
1342 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1343 {
1344 u64 ratio;
1345
1346 /* Guest TSC same frequency as host TSC? */
1347 if (!scale) {
1348 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1349 return 0;
1350 }
1351
1352 /* TSC scaling supported? */
1353 if (!kvm_has_tsc_control) {
1354 if (user_tsc_khz > tsc_khz) {
1355 vcpu->arch.tsc_catchup = 1;
1356 vcpu->arch.tsc_always_catchup = 1;
1357 return 0;
1358 } else {
1359 WARN(1, "user requested TSC rate below hardware speed\n");
1360 return -1;
1361 }
1362 }
1363
1364 /* TSC scaling required - calculate ratio */
1365 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1366 user_tsc_khz, tsc_khz);
1367
1368 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1369 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1370 user_tsc_khz);
1371 return -1;
1372 }
1373
1374 vcpu->arch.tsc_scaling_ratio = ratio;
1375 return 0;
1376 }
1377
1378 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1379 {
1380 u32 thresh_lo, thresh_hi;
1381 int use_scaling = 0;
1382
1383 /* tsc_khz can be zero if TSC calibration fails */
1384 if (user_tsc_khz == 0) {
1385 /* set tsc_scaling_ratio to a safe value */
1386 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1387 return -1;
1388 }
1389
1390 /* Compute a scale to convert nanoseconds in TSC cycles */
1391 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1392 &vcpu->arch.virtual_tsc_shift,
1393 &vcpu->arch.virtual_tsc_mult);
1394 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1395
1396 /*
1397 * Compute the variation in TSC rate which is acceptable
1398 * within the range of tolerance and decide if the
1399 * rate being applied is within that bounds of the hardware
1400 * rate. If so, no scaling or compensation need be done.
1401 */
1402 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1403 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1404 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1405 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1406 use_scaling = 1;
1407 }
1408 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1409 }
1410
1411 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1412 {
1413 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1414 vcpu->arch.virtual_tsc_mult,
1415 vcpu->arch.virtual_tsc_shift);
1416 tsc += vcpu->arch.this_tsc_write;
1417 return tsc;
1418 }
1419
1420 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1421 {
1422 #ifdef CONFIG_X86_64
1423 bool vcpus_matched;
1424 struct kvm_arch *ka = &vcpu->kvm->arch;
1425 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1426
1427 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1428 atomic_read(&vcpu->kvm->online_vcpus));
1429
1430 /*
1431 * Once the masterclock is enabled, always perform request in
1432 * order to update it.
1433 *
1434 * In order to enable masterclock, the host clocksource must be TSC
1435 * and the vcpus need to have matched TSCs. When that happens,
1436 * perform request to enable masterclock.
1437 */
1438 if (ka->use_master_clock ||
1439 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1440 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1441
1442 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1443 atomic_read(&vcpu->kvm->online_vcpus),
1444 ka->use_master_clock, gtod->clock.vclock_mode);
1445 #endif
1446 }
1447
1448 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1449 {
1450 u64 curr_offset = vcpu->arch.tsc_offset;
1451 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1452 }
1453
1454 /*
1455 * Multiply tsc by a fixed point number represented by ratio.
1456 *
1457 * The most significant 64-N bits (mult) of ratio represent the
1458 * integral part of the fixed point number; the remaining N bits
1459 * (frac) represent the fractional part, ie. ratio represents a fixed
1460 * point number (mult + frac * 2^(-N)).
1461 *
1462 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1463 */
1464 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1465 {
1466 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1467 }
1468
1469 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1470 {
1471 u64 _tsc = tsc;
1472 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1473
1474 if (ratio != kvm_default_tsc_scaling_ratio)
1475 _tsc = __scale_tsc(ratio, tsc);
1476
1477 return _tsc;
1478 }
1479 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1480
1481 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1482 {
1483 u64 tsc;
1484
1485 tsc = kvm_scale_tsc(vcpu, rdtsc());
1486
1487 return target_tsc - tsc;
1488 }
1489
1490 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1491 {
1492 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1493 }
1494 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1495
1496 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1497 {
1498 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1499 vcpu->arch.tsc_offset = offset;
1500 }
1501
1502 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1503 {
1504 struct kvm *kvm = vcpu->kvm;
1505 u64 offset, ns, elapsed;
1506 unsigned long flags;
1507 bool matched;
1508 bool already_matched;
1509 u64 data = msr->data;
1510 bool synchronizing = false;
1511
1512 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1513 offset = kvm_compute_tsc_offset(vcpu, data);
1514 ns = ktime_get_boot_ns();
1515 elapsed = ns - kvm->arch.last_tsc_nsec;
1516
1517 if (vcpu->arch.virtual_tsc_khz) {
1518 if (data == 0 && msr->host_initiated) {
1519 /*
1520 * detection of vcpu initialization -- need to sync
1521 * with other vCPUs. This particularly helps to keep
1522 * kvm_clock stable after CPU hotplug
1523 */
1524 synchronizing = true;
1525 } else {
1526 u64 tsc_exp = kvm->arch.last_tsc_write +
1527 nsec_to_cycles(vcpu, elapsed);
1528 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1529 /*
1530 * Special case: TSC write with a small delta (1 second)
1531 * of virtual cycle time against real time is
1532 * interpreted as an attempt to synchronize the CPU.
1533 */
1534 synchronizing = data < tsc_exp + tsc_hz &&
1535 data + tsc_hz > tsc_exp;
1536 }
1537 }
1538
1539 /*
1540 * For a reliable TSC, we can match TSC offsets, and for an unstable
1541 * TSC, we add elapsed time in this computation. We could let the
1542 * compensation code attempt to catch up if we fall behind, but
1543 * it's better to try to match offsets from the beginning.
1544 */
1545 if (synchronizing &&
1546 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1547 if (!check_tsc_unstable()) {
1548 offset = kvm->arch.cur_tsc_offset;
1549 pr_debug("kvm: matched tsc offset for %llu\n", data);
1550 } else {
1551 u64 delta = nsec_to_cycles(vcpu, elapsed);
1552 data += delta;
1553 offset = kvm_compute_tsc_offset(vcpu, data);
1554 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1555 }
1556 matched = true;
1557 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1558 } else {
1559 /*
1560 * We split periods of matched TSC writes into generations.
1561 * For each generation, we track the original measured
1562 * nanosecond time, offset, and write, so if TSCs are in
1563 * sync, we can match exact offset, and if not, we can match
1564 * exact software computation in compute_guest_tsc()
1565 *
1566 * These values are tracked in kvm->arch.cur_xxx variables.
1567 */
1568 kvm->arch.cur_tsc_generation++;
1569 kvm->arch.cur_tsc_nsec = ns;
1570 kvm->arch.cur_tsc_write = data;
1571 kvm->arch.cur_tsc_offset = offset;
1572 matched = false;
1573 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1574 kvm->arch.cur_tsc_generation, data);
1575 }
1576
1577 /*
1578 * We also track th most recent recorded KHZ, write and time to
1579 * allow the matching interval to be extended at each write.
1580 */
1581 kvm->arch.last_tsc_nsec = ns;
1582 kvm->arch.last_tsc_write = data;
1583 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1584
1585 vcpu->arch.last_guest_tsc = data;
1586
1587 /* Keep track of which generation this VCPU has synchronized to */
1588 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1589 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1590 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1591
1592 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1593 update_ia32_tsc_adjust_msr(vcpu, offset);
1594
1595 kvm_vcpu_write_tsc_offset(vcpu, offset);
1596 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1597
1598 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1599 if (!matched) {
1600 kvm->arch.nr_vcpus_matched_tsc = 0;
1601 } else if (!already_matched) {
1602 kvm->arch.nr_vcpus_matched_tsc++;
1603 }
1604
1605 kvm_track_tsc_matching(vcpu);
1606 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1607 }
1608
1609 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1610
1611 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1612 s64 adjustment)
1613 {
1614 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1615 }
1616
1617 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1618 {
1619 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1620 WARN_ON(adjustment < 0);
1621 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1622 adjust_tsc_offset_guest(vcpu, adjustment);
1623 }
1624
1625 #ifdef CONFIG_X86_64
1626
1627 static u64 read_tsc(void)
1628 {
1629 u64 ret = (u64)rdtsc_ordered();
1630 u64 last = pvclock_gtod_data.clock.cycle_last;
1631
1632 if (likely(ret >= last))
1633 return ret;
1634
1635 /*
1636 * GCC likes to generate cmov here, but this branch is extremely
1637 * predictable (it's just a function of time and the likely is
1638 * very likely) and there's a data dependence, so force GCC
1639 * to generate a branch instead. I don't barrier() because
1640 * we don't actually need a barrier, and if this function
1641 * ever gets inlined it will generate worse code.
1642 */
1643 asm volatile ("");
1644 return last;
1645 }
1646
1647 static inline u64 vgettsc(u64 *cycle_now)
1648 {
1649 long v;
1650 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1651
1652 *cycle_now = read_tsc();
1653
1654 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1655 return v * gtod->clock.mult;
1656 }
1657
1658 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1659 {
1660 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1661 unsigned long seq;
1662 int mode;
1663 u64 ns;
1664
1665 do {
1666 seq = read_seqcount_begin(&gtod->seq);
1667 mode = gtod->clock.vclock_mode;
1668 ns = gtod->nsec_base;
1669 ns += vgettsc(cycle_now);
1670 ns >>= gtod->clock.shift;
1671 ns += gtod->boot_ns;
1672 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1673 *t = ns;
1674
1675 return mode;
1676 }
1677
1678 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1679 {
1680 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1681 unsigned long seq;
1682 int mode;
1683 u64 ns;
1684
1685 do {
1686 seq = read_seqcount_begin(&gtod->seq);
1687 mode = gtod->clock.vclock_mode;
1688 ts->tv_sec = gtod->wall_time_sec;
1689 ns = gtod->nsec_base;
1690 ns += vgettsc(cycle_now);
1691 ns >>= gtod->clock.shift;
1692 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1693
1694 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1695 ts->tv_nsec = ns;
1696
1697 return mode;
1698 }
1699
1700 /* returns true if host is using tsc clocksource */
1701 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1702 {
1703 /* checked again under seqlock below */
1704 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1705 return false;
1706
1707 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1708 }
1709
1710 /* returns true if host is using tsc clocksource */
1711 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1712 u64 *cycle_now)
1713 {
1714 /* checked again under seqlock below */
1715 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1716 return false;
1717
1718 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1719 }
1720 #endif
1721
1722 /*
1723 *
1724 * Assuming a stable TSC across physical CPUS, and a stable TSC
1725 * across virtual CPUs, the following condition is possible.
1726 * Each numbered line represents an event visible to both
1727 * CPUs at the next numbered event.
1728 *
1729 * "timespecX" represents host monotonic time. "tscX" represents
1730 * RDTSC value.
1731 *
1732 * VCPU0 on CPU0 | VCPU1 on CPU1
1733 *
1734 * 1. read timespec0,tsc0
1735 * 2. | timespec1 = timespec0 + N
1736 * | tsc1 = tsc0 + M
1737 * 3. transition to guest | transition to guest
1738 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1739 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1740 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1741 *
1742 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1743 *
1744 * - ret0 < ret1
1745 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1746 * ...
1747 * - 0 < N - M => M < N
1748 *
1749 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1750 * always the case (the difference between two distinct xtime instances
1751 * might be smaller then the difference between corresponding TSC reads,
1752 * when updating guest vcpus pvclock areas).
1753 *
1754 * To avoid that problem, do not allow visibility of distinct
1755 * system_timestamp/tsc_timestamp values simultaneously: use a master
1756 * copy of host monotonic time values. Update that master copy
1757 * in lockstep.
1758 *
1759 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1760 *
1761 */
1762
1763 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1764 {
1765 #ifdef CONFIG_X86_64
1766 struct kvm_arch *ka = &kvm->arch;
1767 int vclock_mode;
1768 bool host_tsc_clocksource, vcpus_matched;
1769
1770 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1771 atomic_read(&kvm->online_vcpus));
1772
1773 /*
1774 * If the host uses TSC clock, then passthrough TSC as stable
1775 * to the guest.
1776 */
1777 host_tsc_clocksource = kvm_get_time_and_clockread(
1778 &ka->master_kernel_ns,
1779 &ka->master_cycle_now);
1780
1781 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1782 && !ka->backwards_tsc_observed
1783 && !ka->boot_vcpu_runs_old_kvmclock;
1784
1785 if (ka->use_master_clock)
1786 atomic_set(&kvm_guest_has_master_clock, 1);
1787
1788 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1789 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1790 vcpus_matched);
1791 #endif
1792 }
1793
1794 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1795 {
1796 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1797 }
1798
1799 static void kvm_gen_update_masterclock(struct kvm *kvm)
1800 {
1801 #ifdef CONFIG_X86_64
1802 int i;
1803 struct kvm_vcpu *vcpu;
1804 struct kvm_arch *ka = &kvm->arch;
1805
1806 spin_lock(&ka->pvclock_gtod_sync_lock);
1807 kvm_make_mclock_inprogress_request(kvm);
1808 /* no guest entries from this point */
1809 pvclock_update_vm_gtod_copy(kvm);
1810
1811 kvm_for_each_vcpu(i, vcpu, kvm)
1812 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1813
1814 /* guest entries allowed */
1815 kvm_for_each_vcpu(i, vcpu, kvm)
1816 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1817
1818 spin_unlock(&ka->pvclock_gtod_sync_lock);
1819 #endif
1820 }
1821
1822 u64 get_kvmclock_ns(struct kvm *kvm)
1823 {
1824 struct kvm_arch *ka = &kvm->arch;
1825 struct pvclock_vcpu_time_info hv_clock;
1826 u64 ret;
1827
1828 spin_lock(&ka->pvclock_gtod_sync_lock);
1829 if (!ka->use_master_clock) {
1830 spin_unlock(&ka->pvclock_gtod_sync_lock);
1831 return ktime_get_boot_ns() + ka->kvmclock_offset;
1832 }
1833
1834 hv_clock.tsc_timestamp = ka->master_cycle_now;
1835 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1836 spin_unlock(&ka->pvclock_gtod_sync_lock);
1837
1838 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1839 get_cpu();
1840
1841 if (__this_cpu_read(cpu_tsc_khz)) {
1842 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1843 &hv_clock.tsc_shift,
1844 &hv_clock.tsc_to_system_mul);
1845 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1846 } else
1847 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1848
1849 put_cpu();
1850
1851 return ret;
1852 }
1853
1854 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1855 {
1856 struct kvm_vcpu_arch *vcpu = &v->arch;
1857 struct pvclock_vcpu_time_info guest_hv_clock;
1858
1859 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1860 &guest_hv_clock, sizeof(guest_hv_clock))))
1861 return;
1862
1863 /* This VCPU is paused, but it's legal for a guest to read another
1864 * VCPU's kvmclock, so we really have to follow the specification where
1865 * it says that version is odd if data is being modified, and even after
1866 * it is consistent.
1867 *
1868 * Version field updates must be kept separate. This is because
1869 * kvm_write_guest_cached might use a "rep movs" instruction, and
1870 * writes within a string instruction are weakly ordered. So there
1871 * are three writes overall.
1872 *
1873 * As a small optimization, only write the version field in the first
1874 * and third write. The vcpu->pv_time cache is still valid, because the
1875 * version field is the first in the struct.
1876 */
1877 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1878
1879 if (guest_hv_clock.version & 1)
1880 ++guest_hv_clock.version; /* first time write, random junk */
1881
1882 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1883 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1884 &vcpu->hv_clock,
1885 sizeof(vcpu->hv_clock.version));
1886
1887 smp_wmb();
1888
1889 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1890 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1891
1892 if (vcpu->pvclock_set_guest_stopped_request) {
1893 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1894 vcpu->pvclock_set_guest_stopped_request = false;
1895 }
1896
1897 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1898
1899 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1900 &vcpu->hv_clock,
1901 sizeof(vcpu->hv_clock));
1902
1903 smp_wmb();
1904
1905 vcpu->hv_clock.version++;
1906 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1907 &vcpu->hv_clock,
1908 sizeof(vcpu->hv_clock.version));
1909 }
1910
1911 static int kvm_guest_time_update(struct kvm_vcpu *v)
1912 {
1913 unsigned long flags, tgt_tsc_khz;
1914 struct kvm_vcpu_arch *vcpu = &v->arch;
1915 struct kvm_arch *ka = &v->kvm->arch;
1916 s64 kernel_ns;
1917 u64 tsc_timestamp, host_tsc;
1918 u8 pvclock_flags;
1919 bool use_master_clock;
1920
1921 kernel_ns = 0;
1922 host_tsc = 0;
1923
1924 /*
1925 * If the host uses TSC clock, then passthrough TSC as stable
1926 * to the guest.
1927 */
1928 spin_lock(&ka->pvclock_gtod_sync_lock);
1929 use_master_clock = ka->use_master_clock;
1930 if (use_master_clock) {
1931 host_tsc = ka->master_cycle_now;
1932 kernel_ns = ka->master_kernel_ns;
1933 }
1934 spin_unlock(&ka->pvclock_gtod_sync_lock);
1935
1936 /* Keep irq disabled to prevent changes to the clock */
1937 local_irq_save(flags);
1938 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1939 if (unlikely(tgt_tsc_khz == 0)) {
1940 local_irq_restore(flags);
1941 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1942 return 1;
1943 }
1944 if (!use_master_clock) {
1945 host_tsc = rdtsc();
1946 kernel_ns = ktime_get_boot_ns();
1947 }
1948
1949 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1950
1951 /*
1952 * We may have to catch up the TSC to match elapsed wall clock
1953 * time for two reasons, even if kvmclock is used.
1954 * 1) CPU could have been running below the maximum TSC rate
1955 * 2) Broken TSC compensation resets the base at each VCPU
1956 * entry to avoid unknown leaps of TSC even when running
1957 * again on the same CPU. This may cause apparent elapsed
1958 * time to disappear, and the guest to stand still or run
1959 * very slowly.
1960 */
1961 if (vcpu->tsc_catchup) {
1962 u64 tsc = compute_guest_tsc(v, kernel_ns);
1963 if (tsc > tsc_timestamp) {
1964 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1965 tsc_timestamp = tsc;
1966 }
1967 }
1968
1969 local_irq_restore(flags);
1970
1971 /* With all the info we got, fill in the values */
1972
1973 if (kvm_has_tsc_control)
1974 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1975
1976 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1977 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1978 &vcpu->hv_clock.tsc_shift,
1979 &vcpu->hv_clock.tsc_to_system_mul);
1980 vcpu->hw_tsc_khz = tgt_tsc_khz;
1981 }
1982
1983 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1984 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1985 vcpu->last_guest_tsc = tsc_timestamp;
1986
1987 /* If the host uses TSC clocksource, then it is stable */
1988 pvclock_flags = 0;
1989 if (use_master_clock)
1990 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1991
1992 vcpu->hv_clock.flags = pvclock_flags;
1993
1994 if (vcpu->pv_time_enabled)
1995 kvm_setup_pvclock_page(v);
1996 if (v == kvm_get_vcpu(v->kvm, 0))
1997 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1998 return 0;
1999 }
2000
2001 /*
2002 * kvmclock updates which are isolated to a given vcpu, such as
2003 * vcpu->cpu migration, should not allow system_timestamp from
2004 * the rest of the vcpus to remain static. Otherwise ntp frequency
2005 * correction applies to one vcpu's system_timestamp but not
2006 * the others.
2007 *
2008 * So in those cases, request a kvmclock update for all vcpus.
2009 * We need to rate-limit these requests though, as they can
2010 * considerably slow guests that have a large number of vcpus.
2011 * The time for a remote vcpu to update its kvmclock is bound
2012 * by the delay we use to rate-limit the updates.
2013 */
2014
2015 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2016
2017 static void kvmclock_update_fn(struct work_struct *work)
2018 {
2019 int i;
2020 struct delayed_work *dwork = to_delayed_work(work);
2021 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2022 kvmclock_update_work);
2023 struct kvm *kvm = container_of(ka, struct kvm, arch);
2024 struct kvm_vcpu *vcpu;
2025
2026 kvm_for_each_vcpu(i, vcpu, kvm) {
2027 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2028 kvm_vcpu_kick(vcpu);
2029 }
2030 }
2031
2032 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2033 {
2034 struct kvm *kvm = v->kvm;
2035
2036 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2037 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2038 KVMCLOCK_UPDATE_DELAY);
2039 }
2040
2041 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2042
2043 static void kvmclock_sync_fn(struct work_struct *work)
2044 {
2045 struct delayed_work *dwork = to_delayed_work(work);
2046 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2047 kvmclock_sync_work);
2048 struct kvm *kvm = container_of(ka, struct kvm, arch);
2049
2050 if (!kvmclock_periodic_sync)
2051 return;
2052
2053 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2054 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2055 KVMCLOCK_SYNC_PERIOD);
2056 }
2057
2058 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2059 {
2060 u64 mcg_cap = vcpu->arch.mcg_cap;
2061 unsigned bank_num = mcg_cap & 0xff;
2062 u32 msr = msr_info->index;
2063 u64 data = msr_info->data;
2064
2065 switch (msr) {
2066 case MSR_IA32_MCG_STATUS:
2067 vcpu->arch.mcg_status = data;
2068 break;
2069 case MSR_IA32_MCG_CTL:
2070 if (!(mcg_cap & MCG_CTL_P))
2071 return 1;
2072 if (data != 0 && data != ~(u64)0)
2073 return -1;
2074 vcpu->arch.mcg_ctl = data;
2075 break;
2076 default:
2077 if (msr >= MSR_IA32_MC0_CTL &&
2078 msr < MSR_IA32_MCx_CTL(bank_num)) {
2079 u32 offset = msr - MSR_IA32_MC0_CTL;
2080 /* only 0 or all 1s can be written to IA32_MCi_CTL
2081 * some Linux kernels though clear bit 10 in bank 4 to
2082 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2083 * this to avoid an uncatched #GP in the guest
2084 */
2085 if ((offset & 0x3) == 0 &&
2086 data != 0 && (data | (1 << 10)) != ~(u64)0)
2087 return -1;
2088 if (!msr_info->host_initiated &&
2089 (offset & 0x3) == 1 && data != 0)
2090 return -1;
2091 vcpu->arch.mce_banks[offset] = data;
2092 break;
2093 }
2094 return 1;
2095 }
2096 return 0;
2097 }
2098
2099 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2100 {
2101 struct kvm *kvm = vcpu->kvm;
2102 int lm = is_long_mode(vcpu);
2103 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2104 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2105 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2106 : kvm->arch.xen_hvm_config.blob_size_32;
2107 u32 page_num = data & ~PAGE_MASK;
2108 u64 page_addr = data & PAGE_MASK;
2109 u8 *page;
2110 int r;
2111
2112 r = -E2BIG;
2113 if (page_num >= blob_size)
2114 goto out;
2115 r = -ENOMEM;
2116 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2117 if (IS_ERR(page)) {
2118 r = PTR_ERR(page);
2119 goto out;
2120 }
2121 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2122 goto out_free;
2123 r = 0;
2124 out_free:
2125 kfree(page);
2126 out:
2127 return r;
2128 }
2129
2130 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2131 {
2132 gpa_t gpa = data & ~0x3f;
2133
2134 /* Bits 3:5 are reserved, Should be zero */
2135 if (data & 0x38)
2136 return 1;
2137
2138 vcpu->arch.apf.msr_val = data;
2139
2140 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2141 kvm_clear_async_pf_completion_queue(vcpu);
2142 kvm_async_pf_hash_reset(vcpu);
2143 return 0;
2144 }
2145
2146 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2147 sizeof(u32)))
2148 return 1;
2149
2150 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2151 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2152 kvm_async_pf_wakeup_all(vcpu);
2153 return 0;
2154 }
2155
2156 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2157 {
2158 vcpu->arch.pv_time_enabled = false;
2159 }
2160
2161 static void record_steal_time(struct kvm_vcpu *vcpu)
2162 {
2163 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2164 return;
2165
2166 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2167 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2168 return;
2169
2170 vcpu->arch.st.steal.preempted = 0;
2171
2172 if (vcpu->arch.st.steal.version & 1)
2173 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2174
2175 vcpu->arch.st.steal.version += 1;
2176
2177 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2178 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2179
2180 smp_wmb();
2181
2182 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2183 vcpu->arch.st.last_steal;
2184 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2185
2186 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2187 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2188
2189 smp_wmb();
2190
2191 vcpu->arch.st.steal.version += 1;
2192
2193 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2194 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2195 }
2196
2197 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2198 {
2199 bool pr = false;
2200 u32 msr = msr_info->index;
2201 u64 data = msr_info->data;
2202
2203 switch (msr) {
2204 case MSR_AMD64_NB_CFG:
2205 case MSR_IA32_UCODE_REV:
2206 case MSR_IA32_UCODE_WRITE:
2207 case MSR_VM_HSAVE_PA:
2208 case MSR_AMD64_PATCH_LOADER:
2209 case MSR_AMD64_BU_CFG2:
2210 case MSR_AMD64_DC_CFG:
2211 break;
2212
2213 case MSR_EFER:
2214 return set_efer(vcpu, data);
2215 case MSR_K7_HWCR:
2216 data &= ~(u64)0x40; /* ignore flush filter disable */
2217 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2218 data &= ~(u64)0x8; /* ignore TLB cache disable */
2219 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2220 if (data != 0) {
2221 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2222 data);
2223 return 1;
2224 }
2225 break;
2226 case MSR_FAM10H_MMIO_CONF_BASE:
2227 if (data != 0) {
2228 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2229 "0x%llx\n", data);
2230 return 1;
2231 }
2232 break;
2233 case MSR_IA32_DEBUGCTLMSR:
2234 if (!data) {
2235 /* We support the non-activated case already */
2236 break;
2237 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2238 /* Values other than LBR and BTF are vendor-specific,
2239 thus reserved and should throw a #GP */
2240 return 1;
2241 }
2242 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2243 __func__, data);
2244 break;
2245 case 0x200 ... 0x2ff:
2246 return kvm_mtrr_set_msr(vcpu, msr, data);
2247 case MSR_IA32_APICBASE:
2248 return kvm_set_apic_base(vcpu, msr_info);
2249 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2250 return kvm_x2apic_msr_write(vcpu, msr, data);
2251 case MSR_IA32_TSCDEADLINE:
2252 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2253 break;
2254 case MSR_IA32_TSC_ADJUST:
2255 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2256 if (!msr_info->host_initiated) {
2257 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2258 adjust_tsc_offset_guest(vcpu, adj);
2259 }
2260 vcpu->arch.ia32_tsc_adjust_msr = data;
2261 }
2262 break;
2263 case MSR_IA32_MISC_ENABLE:
2264 vcpu->arch.ia32_misc_enable_msr = data;
2265 break;
2266 case MSR_IA32_SMBASE:
2267 if (!msr_info->host_initiated)
2268 return 1;
2269 vcpu->arch.smbase = data;
2270 break;
2271 case MSR_KVM_WALL_CLOCK_NEW:
2272 case MSR_KVM_WALL_CLOCK:
2273 vcpu->kvm->arch.wall_clock = data;
2274 kvm_write_wall_clock(vcpu->kvm, data);
2275 break;
2276 case MSR_KVM_SYSTEM_TIME_NEW:
2277 case MSR_KVM_SYSTEM_TIME: {
2278 struct kvm_arch *ka = &vcpu->kvm->arch;
2279
2280 kvmclock_reset(vcpu);
2281
2282 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2283 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2284
2285 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2286 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2287
2288 ka->boot_vcpu_runs_old_kvmclock = tmp;
2289 }
2290
2291 vcpu->arch.time = data;
2292 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2293
2294 /* we verify if the enable bit is set... */
2295 if (!(data & 1))
2296 break;
2297
2298 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2299 &vcpu->arch.pv_time, data & ~1ULL,
2300 sizeof(struct pvclock_vcpu_time_info)))
2301 vcpu->arch.pv_time_enabled = false;
2302 else
2303 vcpu->arch.pv_time_enabled = true;
2304
2305 break;
2306 }
2307 case MSR_KVM_ASYNC_PF_EN:
2308 if (kvm_pv_enable_async_pf(vcpu, data))
2309 return 1;
2310 break;
2311 case MSR_KVM_STEAL_TIME:
2312
2313 if (unlikely(!sched_info_on()))
2314 return 1;
2315
2316 if (data & KVM_STEAL_RESERVED_MASK)
2317 return 1;
2318
2319 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2320 data & KVM_STEAL_VALID_BITS,
2321 sizeof(struct kvm_steal_time)))
2322 return 1;
2323
2324 vcpu->arch.st.msr_val = data;
2325
2326 if (!(data & KVM_MSR_ENABLED))
2327 break;
2328
2329 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2330
2331 break;
2332 case MSR_KVM_PV_EOI_EN:
2333 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2334 return 1;
2335 break;
2336
2337 case MSR_IA32_MCG_CTL:
2338 case MSR_IA32_MCG_STATUS:
2339 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2340 return set_msr_mce(vcpu, msr_info);
2341
2342 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2343 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2344 pr = true; /* fall through */
2345 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2346 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2347 if (kvm_pmu_is_valid_msr(vcpu, msr))
2348 return kvm_pmu_set_msr(vcpu, msr_info);
2349
2350 if (pr || data != 0)
2351 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2352 "0x%x data 0x%llx\n", msr, data);
2353 break;
2354 case MSR_K7_CLK_CTL:
2355 /*
2356 * Ignore all writes to this no longer documented MSR.
2357 * Writes are only relevant for old K7 processors,
2358 * all pre-dating SVM, but a recommended workaround from
2359 * AMD for these chips. It is possible to specify the
2360 * affected processor models on the command line, hence
2361 * the need to ignore the workaround.
2362 */
2363 break;
2364 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2365 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2366 case HV_X64_MSR_CRASH_CTL:
2367 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2368 return kvm_hv_set_msr_common(vcpu, msr, data,
2369 msr_info->host_initiated);
2370 case MSR_IA32_BBL_CR_CTL3:
2371 /* Drop writes to this legacy MSR -- see rdmsr
2372 * counterpart for further detail.
2373 */
2374 if (report_ignored_msrs)
2375 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2376 msr, data);
2377 break;
2378 case MSR_AMD64_OSVW_ID_LENGTH:
2379 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2380 return 1;
2381 vcpu->arch.osvw.length = data;
2382 break;
2383 case MSR_AMD64_OSVW_STATUS:
2384 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2385 return 1;
2386 vcpu->arch.osvw.status = data;
2387 break;
2388 case MSR_PLATFORM_INFO:
2389 if (!msr_info->host_initiated ||
2390 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2391 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2392 cpuid_fault_enabled(vcpu)))
2393 return 1;
2394 vcpu->arch.msr_platform_info = data;
2395 break;
2396 case MSR_MISC_FEATURES_ENABLES:
2397 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2398 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2399 !supports_cpuid_fault(vcpu)))
2400 return 1;
2401 vcpu->arch.msr_misc_features_enables = data;
2402 break;
2403 default:
2404 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2405 return xen_hvm_config(vcpu, data);
2406 if (kvm_pmu_is_valid_msr(vcpu, msr))
2407 return kvm_pmu_set_msr(vcpu, msr_info);
2408 if (!ignore_msrs) {
2409 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2410 msr, data);
2411 return 1;
2412 } else {
2413 if (report_ignored_msrs)
2414 vcpu_unimpl(vcpu,
2415 "ignored wrmsr: 0x%x data 0x%llx\n",
2416 msr, data);
2417 break;
2418 }
2419 }
2420 return 0;
2421 }
2422 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2423
2424
2425 /*
2426 * Reads an msr value (of 'msr_index') into 'pdata'.
2427 * Returns 0 on success, non-0 otherwise.
2428 * Assumes vcpu_load() was already called.
2429 */
2430 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2431 {
2432 return kvm_x86_ops->get_msr(vcpu, msr);
2433 }
2434 EXPORT_SYMBOL_GPL(kvm_get_msr);
2435
2436 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2437 {
2438 u64 data;
2439 u64 mcg_cap = vcpu->arch.mcg_cap;
2440 unsigned bank_num = mcg_cap & 0xff;
2441
2442 switch (msr) {
2443 case MSR_IA32_P5_MC_ADDR:
2444 case MSR_IA32_P5_MC_TYPE:
2445 data = 0;
2446 break;
2447 case MSR_IA32_MCG_CAP:
2448 data = vcpu->arch.mcg_cap;
2449 break;
2450 case MSR_IA32_MCG_CTL:
2451 if (!(mcg_cap & MCG_CTL_P))
2452 return 1;
2453 data = vcpu->arch.mcg_ctl;
2454 break;
2455 case MSR_IA32_MCG_STATUS:
2456 data = vcpu->arch.mcg_status;
2457 break;
2458 default:
2459 if (msr >= MSR_IA32_MC0_CTL &&
2460 msr < MSR_IA32_MCx_CTL(bank_num)) {
2461 u32 offset = msr - MSR_IA32_MC0_CTL;
2462 data = vcpu->arch.mce_banks[offset];
2463 break;
2464 }
2465 return 1;
2466 }
2467 *pdata = data;
2468 return 0;
2469 }
2470
2471 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2472 {
2473 switch (msr_info->index) {
2474 case MSR_IA32_PLATFORM_ID:
2475 case MSR_IA32_EBL_CR_POWERON:
2476 case MSR_IA32_DEBUGCTLMSR:
2477 case MSR_IA32_LASTBRANCHFROMIP:
2478 case MSR_IA32_LASTBRANCHTOIP:
2479 case MSR_IA32_LASTINTFROMIP:
2480 case MSR_IA32_LASTINTTOIP:
2481 case MSR_K8_SYSCFG:
2482 case MSR_K8_TSEG_ADDR:
2483 case MSR_K8_TSEG_MASK:
2484 case MSR_K7_HWCR:
2485 case MSR_VM_HSAVE_PA:
2486 case MSR_K8_INT_PENDING_MSG:
2487 case MSR_AMD64_NB_CFG:
2488 case MSR_FAM10H_MMIO_CONF_BASE:
2489 case MSR_AMD64_BU_CFG2:
2490 case MSR_IA32_PERF_CTL:
2491 case MSR_AMD64_DC_CFG:
2492 msr_info->data = 0;
2493 break;
2494 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2495 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2496 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2497 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2498 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2499 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2500 msr_info->data = 0;
2501 break;
2502 case MSR_IA32_UCODE_REV:
2503 msr_info->data = 0x100000000ULL;
2504 break;
2505 case MSR_MTRRcap:
2506 case 0x200 ... 0x2ff:
2507 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2508 case 0xcd: /* fsb frequency */
2509 msr_info->data = 3;
2510 break;
2511 /*
2512 * MSR_EBC_FREQUENCY_ID
2513 * Conservative value valid for even the basic CPU models.
2514 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2515 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2516 * and 266MHz for model 3, or 4. Set Core Clock
2517 * Frequency to System Bus Frequency Ratio to 1 (bits
2518 * 31:24) even though these are only valid for CPU
2519 * models > 2, however guests may end up dividing or
2520 * multiplying by zero otherwise.
2521 */
2522 case MSR_EBC_FREQUENCY_ID:
2523 msr_info->data = 1 << 24;
2524 break;
2525 case MSR_IA32_APICBASE:
2526 msr_info->data = kvm_get_apic_base(vcpu);
2527 break;
2528 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2529 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2530 break;
2531 case MSR_IA32_TSCDEADLINE:
2532 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2533 break;
2534 case MSR_IA32_TSC_ADJUST:
2535 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2536 break;
2537 case MSR_IA32_MISC_ENABLE:
2538 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2539 break;
2540 case MSR_IA32_SMBASE:
2541 if (!msr_info->host_initiated)
2542 return 1;
2543 msr_info->data = vcpu->arch.smbase;
2544 break;
2545 case MSR_IA32_PERF_STATUS:
2546 /* TSC increment by tick */
2547 msr_info->data = 1000ULL;
2548 /* CPU multiplier */
2549 msr_info->data |= (((uint64_t)4ULL) << 40);
2550 break;
2551 case MSR_EFER:
2552 msr_info->data = vcpu->arch.efer;
2553 break;
2554 case MSR_KVM_WALL_CLOCK:
2555 case MSR_KVM_WALL_CLOCK_NEW:
2556 msr_info->data = vcpu->kvm->arch.wall_clock;
2557 break;
2558 case MSR_KVM_SYSTEM_TIME:
2559 case MSR_KVM_SYSTEM_TIME_NEW:
2560 msr_info->data = vcpu->arch.time;
2561 break;
2562 case MSR_KVM_ASYNC_PF_EN:
2563 msr_info->data = vcpu->arch.apf.msr_val;
2564 break;
2565 case MSR_KVM_STEAL_TIME:
2566 msr_info->data = vcpu->arch.st.msr_val;
2567 break;
2568 case MSR_KVM_PV_EOI_EN:
2569 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2570 break;
2571 case MSR_IA32_P5_MC_ADDR:
2572 case MSR_IA32_P5_MC_TYPE:
2573 case MSR_IA32_MCG_CAP:
2574 case MSR_IA32_MCG_CTL:
2575 case MSR_IA32_MCG_STATUS:
2576 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2577 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2578 case MSR_K7_CLK_CTL:
2579 /*
2580 * Provide expected ramp-up count for K7. All other
2581 * are set to zero, indicating minimum divisors for
2582 * every field.
2583 *
2584 * This prevents guest kernels on AMD host with CPU
2585 * type 6, model 8 and higher from exploding due to
2586 * the rdmsr failing.
2587 */
2588 msr_info->data = 0x20000000;
2589 break;
2590 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2591 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2592 case HV_X64_MSR_CRASH_CTL:
2593 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2594 return kvm_hv_get_msr_common(vcpu,
2595 msr_info->index, &msr_info->data);
2596 break;
2597 case MSR_IA32_BBL_CR_CTL3:
2598 /* This legacy MSR exists but isn't fully documented in current
2599 * silicon. It is however accessed by winxp in very narrow
2600 * scenarios where it sets bit #19, itself documented as
2601 * a "reserved" bit. Best effort attempt to source coherent
2602 * read data here should the balance of the register be
2603 * interpreted by the guest:
2604 *
2605 * L2 cache control register 3: 64GB range, 256KB size,
2606 * enabled, latency 0x1, configured
2607 */
2608 msr_info->data = 0xbe702111;
2609 break;
2610 case MSR_AMD64_OSVW_ID_LENGTH:
2611 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2612 return 1;
2613 msr_info->data = vcpu->arch.osvw.length;
2614 break;
2615 case MSR_AMD64_OSVW_STATUS:
2616 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2617 return 1;
2618 msr_info->data = vcpu->arch.osvw.status;
2619 break;
2620 case MSR_PLATFORM_INFO:
2621 msr_info->data = vcpu->arch.msr_platform_info;
2622 break;
2623 case MSR_MISC_FEATURES_ENABLES:
2624 msr_info->data = vcpu->arch.msr_misc_features_enables;
2625 break;
2626 default:
2627 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2628 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2629 if (!ignore_msrs) {
2630 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2631 msr_info->index);
2632 return 1;
2633 } else {
2634 if (report_ignored_msrs)
2635 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2636 msr_info->index);
2637 msr_info->data = 0;
2638 }
2639 break;
2640 }
2641 return 0;
2642 }
2643 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2644
2645 /*
2646 * Read or write a bunch of msrs. All parameters are kernel addresses.
2647 *
2648 * @return number of msrs set successfully.
2649 */
2650 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2651 struct kvm_msr_entry *entries,
2652 int (*do_msr)(struct kvm_vcpu *vcpu,
2653 unsigned index, u64 *data))
2654 {
2655 int i;
2656
2657 for (i = 0; i < msrs->nmsrs; ++i)
2658 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2659 break;
2660
2661 return i;
2662 }
2663
2664 /*
2665 * Read or write a bunch of msrs. Parameters are user addresses.
2666 *
2667 * @return number of msrs set successfully.
2668 */
2669 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2670 int (*do_msr)(struct kvm_vcpu *vcpu,
2671 unsigned index, u64 *data),
2672 int writeback)
2673 {
2674 struct kvm_msrs msrs;
2675 struct kvm_msr_entry *entries;
2676 int r, n;
2677 unsigned size;
2678
2679 r = -EFAULT;
2680 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2681 goto out;
2682
2683 r = -E2BIG;
2684 if (msrs.nmsrs >= MAX_IO_MSRS)
2685 goto out;
2686
2687 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2688 entries = memdup_user(user_msrs->entries, size);
2689 if (IS_ERR(entries)) {
2690 r = PTR_ERR(entries);
2691 goto out;
2692 }
2693
2694 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2695 if (r < 0)
2696 goto out_free;
2697
2698 r = -EFAULT;
2699 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2700 goto out_free;
2701
2702 r = n;
2703
2704 out_free:
2705 kfree(entries);
2706 out:
2707 return r;
2708 }
2709
2710 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2711 {
2712 int r;
2713
2714 switch (ext) {
2715 case KVM_CAP_IRQCHIP:
2716 case KVM_CAP_HLT:
2717 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2718 case KVM_CAP_SET_TSS_ADDR:
2719 case KVM_CAP_EXT_CPUID:
2720 case KVM_CAP_EXT_EMUL_CPUID:
2721 case KVM_CAP_CLOCKSOURCE:
2722 case KVM_CAP_PIT:
2723 case KVM_CAP_NOP_IO_DELAY:
2724 case KVM_CAP_MP_STATE:
2725 case KVM_CAP_SYNC_MMU:
2726 case KVM_CAP_USER_NMI:
2727 case KVM_CAP_REINJECT_CONTROL:
2728 case KVM_CAP_IRQ_INJECT_STATUS:
2729 case KVM_CAP_IOEVENTFD:
2730 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2731 case KVM_CAP_PIT2:
2732 case KVM_CAP_PIT_STATE2:
2733 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2734 case KVM_CAP_XEN_HVM:
2735 case KVM_CAP_VCPU_EVENTS:
2736 case KVM_CAP_HYPERV:
2737 case KVM_CAP_HYPERV_VAPIC:
2738 case KVM_CAP_HYPERV_SPIN:
2739 case KVM_CAP_HYPERV_SYNIC:
2740 case KVM_CAP_HYPERV_SYNIC2:
2741 case KVM_CAP_HYPERV_VP_INDEX:
2742 case KVM_CAP_PCI_SEGMENT:
2743 case KVM_CAP_DEBUGREGS:
2744 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2745 case KVM_CAP_XSAVE:
2746 case KVM_CAP_ASYNC_PF:
2747 case KVM_CAP_GET_TSC_KHZ:
2748 case KVM_CAP_KVMCLOCK_CTRL:
2749 case KVM_CAP_READONLY_MEM:
2750 case KVM_CAP_HYPERV_TIME:
2751 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2752 case KVM_CAP_TSC_DEADLINE_TIMER:
2753 case KVM_CAP_ENABLE_CAP_VM:
2754 case KVM_CAP_DISABLE_QUIRKS:
2755 case KVM_CAP_SET_BOOT_CPU_ID:
2756 case KVM_CAP_SPLIT_IRQCHIP:
2757 case KVM_CAP_IMMEDIATE_EXIT:
2758 case KVM_CAP_GET_MSR_FEATURES:
2759 r = 1;
2760 break;
2761 case KVM_CAP_ADJUST_CLOCK:
2762 r = KVM_CLOCK_TSC_STABLE;
2763 break;
2764 case KVM_CAP_X86_GUEST_MWAIT:
2765 r = kvm_mwait_in_guest();
2766 break;
2767 case KVM_CAP_X86_SMM:
2768 /* SMBASE is usually relocated above 1M on modern chipsets,
2769 * and SMM handlers might indeed rely on 4G segment limits,
2770 * so do not report SMM to be available if real mode is
2771 * emulated via vm86 mode. Still, do not go to great lengths
2772 * to avoid userspace's usage of the feature, because it is a
2773 * fringe case that is not enabled except via specific settings
2774 * of the module parameters.
2775 */
2776 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2777 break;
2778 case KVM_CAP_VAPIC:
2779 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2780 break;
2781 case KVM_CAP_NR_VCPUS:
2782 r = KVM_SOFT_MAX_VCPUS;
2783 break;
2784 case KVM_CAP_MAX_VCPUS:
2785 r = KVM_MAX_VCPUS;
2786 break;
2787 case KVM_CAP_NR_MEMSLOTS:
2788 r = KVM_USER_MEM_SLOTS;
2789 break;
2790 case KVM_CAP_PV_MMU: /* obsolete */
2791 r = 0;
2792 break;
2793 case KVM_CAP_MCE:
2794 r = KVM_MAX_MCE_BANKS;
2795 break;
2796 case KVM_CAP_XCRS:
2797 r = boot_cpu_has(X86_FEATURE_XSAVE);
2798 break;
2799 case KVM_CAP_TSC_CONTROL:
2800 r = kvm_has_tsc_control;
2801 break;
2802 case KVM_CAP_X2APIC_API:
2803 r = KVM_X2APIC_API_VALID_FLAGS;
2804 break;
2805 default:
2806 r = 0;
2807 break;
2808 }
2809 return r;
2810
2811 }
2812
2813 long kvm_arch_dev_ioctl(struct file *filp,
2814 unsigned int ioctl, unsigned long arg)
2815 {
2816 void __user *argp = (void __user *)arg;
2817 long r;
2818
2819 switch (ioctl) {
2820 case KVM_GET_MSR_INDEX_LIST: {
2821 struct kvm_msr_list __user *user_msr_list = argp;
2822 struct kvm_msr_list msr_list;
2823 unsigned n;
2824
2825 r = -EFAULT;
2826 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2827 goto out;
2828 n = msr_list.nmsrs;
2829 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2830 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2831 goto out;
2832 r = -E2BIG;
2833 if (n < msr_list.nmsrs)
2834 goto out;
2835 r = -EFAULT;
2836 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2837 num_msrs_to_save * sizeof(u32)))
2838 goto out;
2839 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2840 &emulated_msrs,
2841 num_emulated_msrs * sizeof(u32)))
2842 goto out;
2843 r = 0;
2844 break;
2845 }
2846 case KVM_GET_SUPPORTED_CPUID:
2847 case KVM_GET_EMULATED_CPUID: {
2848 struct kvm_cpuid2 __user *cpuid_arg = argp;
2849 struct kvm_cpuid2 cpuid;
2850
2851 r = -EFAULT;
2852 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2853 goto out;
2854
2855 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2856 ioctl);
2857 if (r)
2858 goto out;
2859
2860 r = -EFAULT;
2861 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2862 goto out;
2863 r = 0;
2864 break;
2865 }
2866 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2867 r = -EFAULT;
2868 if (copy_to_user(argp, &kvm_mce_cap_supported,
2869 sizeof(kvm_mce_cap_supported)))
2870 goto out;
2871 r = 0;
2872 break;
2873 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2874 struct kvm_msr_list __user *user_msr_list = argp;
2875 struct kvm_msr_list msr_list;
2876 unsigned int n;
2877
2878 r = -EFAULT;
2879 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2880 goto out;
2881 n = msr_list.nmsrs;
2882 msr_list.nmsrs = num_msr_based_features;
2883 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2884 goto out;
2885 r = -E2BIG;
2886 if (n < msr_list.nmsrs)
2887 goto out;
2888 r = -EFAULT;
2889 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2890 num_msr_based_features * sizeof(u32)))
2891 goto out;
2892 r = 0;
2893 break;
2894 }
2895 case KVM_GET_MSRS:
2896 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2897 break;
2898 }
2899 default:
2900 r = -EINVAL;
2901 }
2902 out:
2903 return r;
2904 }
2905
2906 static void wbinvd_ipi(void *garbage)
2907 {
2908 wbinvd();
2909 }
2910
2911 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2912 {
2913 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2914 }
2915
2916 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2917 {
2918 /* Address WBINVD may be executed by guest */
2919 if (need_emulate_wbinvd(vcpu)) {
2920 if (kvm_x86_ops->has_wbinvd_exit())
2921 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2922 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2923 smp_call_function_single(vcpu->cpu,
2924 wbinvd_ipi, NULL, 1);
2925 }
2926
2927 kvm_x86_ops->vcpu_load(vcpu, cpu);
2928
2929 /* Apply any externally detected TSC adjustments (due to suspend) */
2930 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2931 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2932 vcpu->arch.tsc_offset_adjustment = 0;
2933 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2934 }
2935
2936 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2937 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2938 rdtsc() - vcpu->arch.last_host_tsc;
2939 if (tsc_delta < 0)
2940 mark_tsc_unstable("KVM discovered backwards TSC");
2941
2942 if (check_tsc_unstable()) {
2943 u64 offset = kvm_compute_tsc_offset(vcpu,
2944 vcpu->arch.last_guest_tsc);
2945 kvm_vcpu_write_tsc_offset(vcpu, offset);
2946 vcpu->arch.tsc_catchup = 1;
2947 }
2948
2949 if (kvm_lapic_hv_timer_in_use(vcpu))
2950 kvm_lapic_restart_hv_timer(vcpu);
2951
2952 /*
2953 * On a host with synchronized TSC, there is no need to update
2954 * kvmclock on vcpu->cpu migration
2955 */
2956 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2957 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2958 if (vcpu->cpu != cpu)
2959 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2960 vcpu->cpu = cpu;
2961 }
2962
2963 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2964 }
2965
2966 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2967 {
2968 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2969 return;
2970
2971 vcpu->arch.st.steal.preempted = 1;
2972
2973 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2974 &vcpu->arch.st.steal.preempted,
2975 offsetof(struct kvm_steal_time, preempted),
2976 sizeof(vcpu->arch.st.steal.preempted));
2977 }
2978
2979 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2980 {
2981 int idx;
2982
2983 if (vcpu->preempted)
2984 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2985
2986 /*
2987 * Disable page faults because we're in atomic context here.
2988 * kvm_write_guest_offset_cached() would call might_fault()
2989 * that relies on pagefault_disable() to tell if there's a
2990 * bug. NOTE: the write to guest memory may not go through if
2991 * during postcopy live migration or if there's heavy guest
2992 * paging.
2993 */
2994 pagefault_disable();
2995 /*
2996 * kvm_memslots() will be called by
2997 * kvm_write_guest_offset_cached() so take the srcu lock.
2998 */
2999 idx = srcu_read_lock(&vcpu->kvm->srcu);
3000 kvm_steal_time_set_preempted(vcpu);
3001 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3002 pagefault_enable();
3003 kvm_x86_ops->vcpu_put(vcpu);
3004 vcpu->arch.last_host_tsc = rdtsc();
3005 /*
3006 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3007 * on every vmexit, but if not, we might have a stale dr6 from the
3008 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3009 */
3010 set_debugreg(0, 6);
3011 }
3012
3013 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3014 struct kvm_lapic_state *s)
3015 {
3016 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
3017 kvm_x86_ops->sync_pir_to_irr(vcpu);
3018
3019 return kvm_apic_get_state(vcpu, s);
3020 }
3021
3022 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3023 struct kvm_lapic_state *s)
3024 {
3025 int r;
3026
3027 r = kvm_apic_set_state(vcpu, s);
3028 if (r)
3029 return r;
3030 update_cr8_intercept(vcpu);
3031
3032 return 0;
3033 }
3034
3035 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3036 {
3037 return (!lapic_in_kernel(vcpu) ||
3038 kvm_apic_accept_pic_intr(vcpu));
3039 }
3040
3041 /*
3042 * if userspace requested an interrupt window, check that the
3043 * interrupt window is open.
3044 *
3045 * No need to exit to userspace if we already have an interrupt queued.
3046 */
3047 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3048 {
3049 return kvm_arch_interrupt_allowed(vcpu) &&
3050 !kvm_cpu_has_interrupt(vcpu) &&
3051 !kvm_event_needs_reinjection(vcpu) &&
3052 kvm_cpu_accept_dm_intr(vcpu);
3053 }
3054
3055 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3056 struct kvm_interrupt *irq)
3057 {
3058 if (irq->irq >= KVM_NR_INTERRUPTS)
3059 return -EINVAL;
3060
3061 if (!irqchip_in_kernel(vcpu->kvm)) {
3062 kvm_queue_interrupt(vcpu, irq->irq, false);
3063 kvm_make_request(KVM_REQ_EVENT, vcpu);
3064 return 0;
3065 }
3066
3067 /*
3068 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3069 * fail for in-kernel 8259.
3070 */
3071 if (pic_in_kernel(vcpu->kvm))
3072 return -ENXIO;
3073
3074 if (vcpu->arch.pending_external_vector != -1)
3075 return -EEXIST;
3076
3077 vcpu->arch.pending_external_vector = irq->irq;
3078 kvm_make_request(KVM_REQ_EVENT, vcpu);
3079 return 0;
3080 }
3081
3082 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3083 {
3084 kvm_inject_nmi(vcpu);
3085
3086 return 0;
3087 }
3088
3089 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3090 {
3091 kvm_make_request(KVM_REQ_SMI, vcpu);
3092
3093 return 0;
3094 }
3095
3096 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3097 struct kvm_tpr_access_ctl *tac)
3098 {
3099 if (tac->flags)
3100 return -EINVAL;
3101 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3102 return 0;
3103 }
3104
3105 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3106 u64 mcg_cap)
3107 {
3108 int r;
3109 unsigned bank_num = mcg_cap & 0xff, bank;
3110
3111 r = -EINVAL;
3112 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3113 goto out;
3114 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3115 goto out;
3116 r = 0;
3117 vcpu->arch.mcg_cap = mcg_cap;
3118 /* Init IA32_MCG_CTL to all 1s */
3119 if (mcg_cap & MCG_CTL_P)
3120 vcpu->arch.mcg_ctl = ~(u64)0;
3121 /* Init IA32_MCi_CTL to all 1s */
3122 for (bank = 0; bank < bank_num; bank++)
3123 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3124
3125 if (kvm_x86_ops->setup_mce)
3126 kvm_x86_ops->setup_mce(vcpu);
3127 out:
3128 return r;
3129 }
3130
3131 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3132 struct kvm_x86_mce *mce)
3133 {
3134 u64 mcg_cap = vcpu->arch.mcg_cap;
3135 unsigned bank_num = mcg_cap & 0xff;
3136 u64 *banks = vcpu->arch.mce_banks;
3137
3138 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3139 return -EINVAL;
3140 /*
3141 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3142 * reporting is disabled
3143 */
3144 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3145 vcpu->arch.mcg_ctl != ~(u64)0)
3146 return 0;
3147 banks += 4 * mce->bank;
3148 /*
3149 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3150 * reporting is disabled for the bank
3151 */
3152 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3153 return 0;
3154 if (mce->status & MCI_STATUS_UC) {
3155 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3156 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3157 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3158 return 0;
3159 }
3160 if (banks[1] & MCI_STATUS_VAL)
3161 mce->status |= MCI_STATUS_OVER;
3162 banks[2] = mce->addr;
3163 banks[3] = mce->misc;
3164 vcpu->arch.mcg_status = mce->mcg_status;
3165 banks[1] = mce->status;
3166 kvm_queue_exception(vcpu, MC_VECTOR);
3167 } else if (!(banks[1] & MCI_STATUS_VAL)
3168 || !(banks[1] & MCI_STATUS_UC)) {
3169 if (banks[1] & MCI_STATUS_VAL)
3170 mce->status |= MCI_STATUS_OVER;
3171 banks[2] = mce->addr;
3172 banks[3] = mce->misc;
3173 banks[1] = mce->status;
3174 } else
3175 banks[1] |= MCI_STATUS_OVER;
3176 return 0;
3177 }
3178
3179 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3180 struct kvm_vcpu_events *events)
3181 {
3182 process_nmi(vcpu);
3183 /*
3184 * FIXME: pass injected and pending separately. This is only
3185 * needed for nested virtualization, whose state cannot be
3186 * migrated yet. For now we can combine them.
3187 */
3188 events->exception.injected =
3189 (vcpu->arch.exception.pending ||
3190 vcpu->arch.exception.injected) &&
3191 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3192 events->exception.nr = vcpu->arch.exception.nr;
3193 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3194 events->exception.pad = 0;
3195 events->exception.error_code = vcpu->arch.exception.error_code;
3196
3197 events->interrupt.injected =
3198 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3199 events->interrupt.nr = vcpu->arch.interrupt.nr;
3200 events->interrupt.soft = 0;
3201 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3202
3203 events->nmi.injected = vcpu->arch.nmi_injected;
3204 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3205 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3206 events->nmi.pad = 0;
3207
3208 events->sipi_vector = 0; /* never valid when reporting to user space */
3209
3210 events->smi.smm = is_smm(vcpu);
3211 events->smi.pending = vcpu->arch.smi_pending;
3212 events->smi.smm_inside_nmi =
3213 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3214 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3215
3216 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3217 | KVM_VCPUEVENT_VALID_SHADOW
3218 | KVM_VCPUEVENT_VALID_SMM);
3219 memset(&events->reserved, 0, sizeof(events->reserved));
3220 }
3221
3222 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3223
3224 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3225 struct kvm_vcpu_events *events)
3226 {
3227 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3228 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3229 | KVM_VCPUEVENT_VALID_SHADOW
3230 | KVM_VCPUEVENT_VALID_SMM))
3231 return -EINVAL;
3232
3233 if (events->exception.injected &&
3234 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3235 is_guest_mode(vcpu)))
3236 return -EINVAL;
3237
3238 /* INITs are latched while in SMM */
3239 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3240 (events->smi.smm || events->smi.pending) &&
3241 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3242 return -EINVAL;
3243
3244 process_nmi(vcpu);
3245 vcpu->arch.exception.injected = false;
3246 vcpu->arch.exception.pending = events->exception.injected;
3247 vcpu->arch.exception.nr = events->exception.nr;
3248 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3249 vcpu->arch.exception.error_code = events->exception.error_code;
3250
3251 vcpu->arch.interrupt.pending = events->interrupt.injected;
3252 vcpu->arch.interrupt.nr = events->interrupt.nr;
3253 vcpu->arch.interrupt.soft = events->interrupt.soft;
3254 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3255 kvm_x86_ops->set_interrupt_shadow(vcpu,
3256 events->interrupt.shadow);
3257
3258 vcpu->arch.nmi_injected = events->nmi.injected;
3259 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3260 vcpu->arch.nmi_pending = events->nmi.pending;
3261 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3262
3263 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3264 lapic_in_kernel(vcpu))
3265 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3266
3267 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3268 u32 hflags = vcpu->arch.hflags;
3269 if (events->smi.smm)
3270 hflags |= HF_SMM_MASK;
3271 else
3272 hflags &= ~HF_SMM_MASK;
3273 kvm_set_hflags(vcpu, hflags);
3274
3275 vcpu->arch.smi_pending = events->smi.pending;
3276
3277 if (events->smi.smm) {
3278 if (events->smi.smm_inside_nmi)
3279 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3280 else
3281 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3282 if (lapic_in_kernel(vcpu)) {
3283 if (events->smi.latched_init)
3284 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3285 else
3286 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3287 }
3288 }
3289 }
3290
3291 kvm_make_request(KVM_REQ_EVENT, vcpu);
3292
3293 return 0;
3294 }
3295
3296 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3297 struct kvm_debugregs *dbgregs)
3298 {
3299 unsigned long val;
3300
3301 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3302 kvm_get_dr(vcpu, 6, &val);
3303 dbgregs->dr6 = val;
3304 dbgregs->dr7 = vcpu->arch.dr7;
3305 dbgregs->flags = 0;
3306 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3307 }
3308
3309 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3310 struct kvm_debugregs *dbgregs)
3311 {
3312 if (dbgregs->flags)
3313 return -EINVAL;
3314
3315 if (dbgregs->dr6 & ~0xffffffffull)
3316 return -EINVAL;
3317 if (dbgregs->dr7 & ~0xffffffffull)
3318 return -EINVAL;
3319
3320 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3321 kvm_update_dr0123(vcpu);
3322 vcpu->arch.dr6 = dbgregs->dr6;
3323 kvm_update_dr6(vcpu);
3324 vcpu->arch.dr7 = dbgregs->dr7;
3325 kvm_update_dr7(vcpu);
3326
3327 return 0;
3328 }
3329
3330 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3331
3332 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3333 {
3334 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3335 u64 xstate_bv = xsave->header.xfeatures;
3336 u64 valid;
3337
3338 /*
3339 * Copy legacy XSAVE area, to avoid complications with CPUID
3340 * leaves 0 and 1 in the loop below.
3341 */
3342 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3343
3344 /* Set XSTATE_BV */
3345 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3346 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3347
3348 /*
3349 * Copy each region from the possibly compacted offset to the
3350 * non-compacted offset.
3351 */
3352 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3353 while (valid) {
3354 u64 feature = valid & -valid;
3355 int index = fls64(feature) - 1;
3356 void *src = get_xsave_addr(xsave, feature);
3357
3358 if (src) {
3359 u32 size, offset, ecx, edx;
3360 cpuid_count(XSTATE_CPUID, index,
3361 &size, &offset, &ecx, &edx);
3362 if (feature == XFEATURE_MASK_PKRU)
3363 memcpy(dest + offset, &vcpu->arch.pkru,
3364 sizeof(vcpu->arch.pkru));
3365 else
3366 memcpy(dest + offset, src, size);
3367
3368 }
3369
3370 valid -= feature;
3371 }
3372 }
3373
3374 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3375 {
3376 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3377 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3378 u64 valid;
3379
3380 /*
3381 * Copy legacy XSAVE area, to avoid complications with CPUID
3382 * leaves 0 and 1 in the loop below.
3383 */
3384 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3385
3386 /* Set XSTATE_BV and possibly XCOMP_BV. */
3387 xsave->header.xfeatures = xstate_bv;
3388 if (boot_cpu_has(X86_FEATURE_XSAVES))
3389 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3390
3391 /*
3392 * Copy each region from the non-compacted offset to the
3393 * possibly compacted offset.
3394 */
3395 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3396 while (valid) {
3397 u64 feature = valid & -valid;
3398 int index = fls64(feature) - 1;
3399 void *dest = get_xsave_addr(xsave, feature);
3400
3401 if (dest) {
3402 u32 size, offset, ecx, edx;
3403 cpuid_count(XSTATE_CPUID, index,
3404 &size, &offset, &ecx, &edx);
3405 if (feature == XFEATURE_MASK_PKRU)
3406 memcpy(&vcpu->arch.pkru, src + offset,
3407 sizeof(vcpu->arch.pkru));
3408 else
3409 memcpy(dest, src + offset, size);
3410 }
3411
3412 valid -= feature;
3413 }
3414 }
3415
3416 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3417 struct kvm_xsave *guest_xsave)
3418 {
3419 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3420 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3421 fill_xsave((u8 *) guest_xsave->region, vcpu);
3422 } else {
3423 memcpy(guest_xsave->region,
3424 &vcpu->arch.guest_fpu.state.fxsave,
3425 sizeof(struct fxregs_state));
3426 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3427 XFEATURE_MASK_FPSSE;
3428 }
3429 }
3430
3431 #define XSAVE_MXCSR_OFFSET 24
3432
3433 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3434 struct kvm_xsave *guest_xsave)
3435 {
3436 u64 xstate_bv =
3437 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3438 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3439
3440 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3441 /*
3442 * Here we allow setting states that are not present in
3443 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3444 * with old userspace.
3445 */
3446 if (xstate_bv & ~kvm_supported_xcr0() ||
3447 mxcsr & ~mxcsr_feature_mask)
3448 return -EINVAL;
3449 load_xsave(vcpu, (u8 *)guest_xsave->region);
3450 } else {
3451 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3452 mxcsr & ~mxcsr_feature_mask)
3453 return -EINVAL;
3454 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3455 guest_xsave->region, sizeof(struct fxregs_state));
3456 }
3457 return 0;
3458 }
3459
3460 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3461 struct kvm_xcrs *guest_xcrs)
3462 {
3463 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3464 guest_xcrs->nr_xcrs = 0;
3465 return;
3466 }
3467
3468 guest_xcrs->nr_xcrs = 1;
3469 guest_xcrs->flags = 0;
3470 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3471 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3472 }
3473
3474 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3475 struct kvm_xcrs *guest_xcrs)
3476 {
3477 int i, r = 0;
3478
3479 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3480 return -EINVAL;
3481
3482 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3483 return -EINVAL;
3484
3485 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3486 /* Only support XCR0 currently */
3487 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3488 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3489 guest_xcrs->xcrs[i].value);
3490 break;
3491 }
3492 if (r)
3493 r = -EINVAL;
3494 return r;
3495 }
3496
3497 /*
3498 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3499 * stopped by the hypervisor. This function will be called from the host only.
3500 * EINVAL is returned when the host attempts to set the flag for a guest that
3501 * does not support pv clocks.
3502 */
3503 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3504 {
3505 if (!vcpu->arch.pv_time_enabled)
3506 return -EINVAL;
3507 vcpu->arch.pvclock_set_guest_stopped_request = true;
3508 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3509 return 0;
3510 }
3511
3512 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3513 struct kvm_enable_cap *cap)
3514 {
3515 if (cap->flags)
3516 return -EINVAL;
3517
3518 switch (cap->cap) {
3519 case KVM_CAP_HYPERV_SYNIC2:
3520 if (cap->args[0])
3521 return -EINVAL;
3522 case KVM_CAP_HYPERV_SYNIC:
3523 if (!irqchip_in_kernel(vcpu->kvm))
3524 return -EINVAL;
3525 return kvm_hv_activate_synic(vcpu, cap->cap ==
3526 KVM_CAP_HYPERV_SYNIC2);
3527 default:
3528 return -EINVAL;
3529 }
3530 }
3531
3532 long kvm_arch_vcpu_ioctl(struct file *filp,
3533 unsigned int ioctl, unsigned long arg)
3534 {
3535 struct kvm_vcpu *vcpu = filp->private_data;
3536 void __user *argp = (void __user *)arg;
3537 int r;
3538 union {
3539 struct kvm_lapic_state *lapic;
3540 struct kvm_xsave *xsave;
3541 struct kvm_xcrs *xcrs;
3542 void *buffer;
3543 } u;
3544
3545 u.buffer = NULL;
3546 switch (ioctl) {
3547 case KVM_GET_LAPIC: {
3548 r = -EINVAL;
3549 if (!lapic_in_kernel(vcpu))
3550 goto out;
3551 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3552
3553 r = -ENOMEM;
3554 if (!u.lapic)
3555 goto out;
3556 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3557 if (r)
3558 goto out;
3559 r = -EFAULT;
3560 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3561 goto out;
3562 r = 0;
3563 break;
3564 }
3565 case KVM_SET_LAPIC: {
3566 r = -EINVAL;
3567 if (!lapic_in_kernel(vcpu))
3568 goto out;
3569 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3570 if (IS_ERR(u.lapic))
3571 return PTR_ERR(u.lapic);
3572
3573 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3574 break;
3575 }
3576 case KVM_INTERRUPT: {
3577 struct kvm_interrupt irq;
3578
3579 r = -EFAULT;
3580 if (copy_from_user(&irq, argp, sizeof irq))
3581 goto out;
3582 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3583 break;
3584 }
3585 case KVM_NMI: {
3586 r = kvm_vcpu_ioctl_nmi(vcpu);
3587 break;
3588 }
3589 case KVM_SMI: {
3590 r = kvm_vcpu_ioctl_smi(vcpu);
3591 break;
3592 }
3593 case KVM_SET_CPUID: {
3594 struct kvm_cpuid __user *cpuid_arg = argp;
3595 struct kvm_cpuid cpuid;
3596
3597 r = -EFAULT;
3598 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3599 goto out;
3600 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3601 break;
3602 }
3603 case KVM_SET_CPUID2: {
3604 struct kvm_cpuid2 __user *cpuid_arg = argp;
3605 struct kvm_cpuid2 cpuid;
3606
3607 r = -EFAULT;
3608 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3609 goto out;
3610 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3611 cpuid_arg->entries);
3612 break;
3613 }
3614 case KVM_GET_CPUID2: {
3615 struct kvm_cpuid2 __user *cpuid_arg = argp;
3616 struct kvm_cpuid2 cpuid;
3617
3618 r = -EFAULT;
3619 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3620 goto out;
3621 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3622 cpuid_arg->entries);
3623 if (r)
3624 goto out;
3625 r = -EFAULT;
3626 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3627 goto out;
3628 r = 0;
3629 break;
3630 }
3631 case KVM_GET_MSRS: {
3632 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3633 r = msr_io(vcpu, argp, do_get_msr, 1);
3634 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3635 break;
3636 }
3637 case KVM_SET_MSRS: {
3638 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3639 r = msr_io(vcpu, argp, do_set_msr, 0);
3640 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3641 break;
3642 }
3643 case KVM_TPR_ACCESS_REPORTING: {
3644 struct kvm_tpr_access_ctl tac;
3645
3646 r = -EFAULT;
3647 if (copy_from_user(&tac, argp, sizeof tac))
3648 goto out;
3649 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3650 if (r)
3651 goto out;
3652 r = -EFAULT;
3653 if (copy_to_user(argp, &tac, sizeof tac))
3654 goto out;
3655 r = 0;
3656 break;
3657 };
3658 case KVM_SET_VAPIC_ADDR: {
3659 struct kvm_vapic_addr va;
3660 int idx;
3661
3662 r = -EINVAL;
3663 if (!lapic_in_kernel(vcpu))
3664 goto out;
3665 r = -EFAULT;
3666 if (copy_from_user(&va, argp, sizeof va))
3667 goto out;
3668 idx = srcu_read_lock(&vcpu->kvm->srcu);
3669 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3670 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3671 break;
3672 }
3673 case KVM_X86_SETUP_MCE: {
3674 u64 mcg_cap;
3675
3676 r = -EFAULT;
3677 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3678 goto out;
3679 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3680 break;
3681 }
3682 case KVM_X86_SET_MCE: {
3683 struct kvm_x86_mce mce;
3684
3685 r = -EFAULT;
3686 if (copy_from_user(&mce, argp, sizeof mce))
3687 goto out;
3688 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3689 break;
3690 }
3691 case KVM_GET_VCPU_EVENTS: {
3692 struct kvm_vcpu_events events;
3693
3694 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3695
3696 r = -EFAULT;
3697 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3698 break;
3699 r = 0;
3700 break;
3701 }
3702 case KVM_SET_VCPU_EVENTS: {
3703 struct kvm_vcpu_events events;
3704
3705 r = -EFAULT;
3706 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3707 break;
3708
3709 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3710 break;
3711 }
3712 case KVM_GET_DEBUGREGS: {
3713 struct kvm_debugregs dbgregs;
3714
3715 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3716
3717 r = -EFAULT;
3718 if (copy_to_user(argp, &dbgregs,
3719 sizeof(struct kvm_debugregs)))
3720 break;
3721 r = 0;
3722 break;
3723 }
3724 case KVM_SET_DEBUGREGS: {
3725 struct kvm_debugregs dbgregs;
3726
3727 r = -EFAULT;
3728 if (copy_from_user(&dbgregs, argp,
3729 sizeof(struct kvm_debugregs)))
3730 break;
3731
3732 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3733 break;
3734 }
3735 case KVM_GET_XSAVE: {
3736 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3737 r = -ENOMEM;
3738 if (!u.xsave)
3739 break;
3740
3741 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3742
3743 r = -EFAULT;
3744 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3745 break;
3746 r = 0;
3747 break;
3748 }
3749 case KVM_SET_XSAVE: {
3750 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3751 if (IS_ERR(u.xsave))
3752 return PTR_ERR(u.xsave);
3753
3754 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3755 break;
3756 }
3757 case KVM_GET_XCRS: {
3758 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3759 r = -ENOMEM;
3760 if (!u.xcrs)
3761 break;
3762
3763 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3764
3765 r = -EFAULT;
3766 if (copy_to_user(argp, u.xcrs,
3767 sizeof(struct kvm_xcrs)))
3768 break;
3769 r = 0;
3770 break;
3771 }
3772 case KVM_SET_XCRS: {
3773 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3774 if (IS_ERR(u.xcrs))
3775 return PTR_ERR(u.xcrs);
3776
3777 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3778 break;
3779 }
3780 case KVM_SET_TSC_KHZ: {
3781 u32 user_tsc_khz;
3782
3783 r = -EINVAL;
3784 user_tsc_khz = (u32)arg;
3785
3786 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3787 goto out;
3788
3789 if (user_tsc_khz == 0)
3790 user_tsc_khz = tsc_khz;
3791
3792 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3793 r = 0;
3794
3795 goto out;
3796 }
3797 case KVM_GET_TSC_KHZ: {
3798 r = vcpu->arch.virtual_tsc_khz;
3799 goto out;
3800 }
3801 case KVM_KVMCLOCK_CTRL: {
3802 r = kvm_set_guest_paused(vcpu);
3803 goto out;
3804 }
3805 case KVM_ENABLE_CAP: {
3806 struct kvm_enable_cap cap;
3807
3808 r = -EFAULT;
3809 if (copy_from_user(&cap, argp, sizeof(cap)))
3810 goto out;
3811 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3812 break;
3813 }
3814 default:
3815 r = -EINVAL;
3816 }
3817 out:
3818 kfree(u.buffer);
3819 return r;
3820 }
3821
3822 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3823 {
3824 return VM_FAULT_SIGBUS;
3825 }
3826
3827 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3828 {
3829 int ret;
3830
3831 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3832 return -EINVAL;
3833 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3834 return ret;
3835 }
3836
3837 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3838 u64 ident_addr)
3839 {
3840 kvm->arch.ept_identity_map_addr = ident_addr;
3841 return 0;
3842 }
3843
3844 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3845 u32 kvm_nr_mmu_pages)
3846 {
3847 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3848 return -EINVAL;
3849
3850 mutex_lock(&kvm->slots_lock);
3851
3852 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3853 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3854
3855 mutex_unlock(&kvm->slots_lock);
3856 return 0;
3857 }
3858
3859 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3860 {
3861 return kvm->arch.n_max_mmu_pages;
3862 }
3863
3864 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3865 {
3866 struct kvm_pic *pic = kvm->arch.vpic;
3867 int r;
3868
3869 r = 0;
3870 switch (chip->chip_id) {
3871 case KVM_IRQCHIP_PIC_MASTER:
3872 memcpy(&chip->chip.pic, &pic->pics[0],
3873 sizeof(struct kvm_pic_state));
3874 break;
3875 case KVM_IRQCHIP_PIC_SLAVE:
3876 memcpy(&chip->chip.pic, &pic->pics[1],
3877 sizeof(struct kvm_pic_state));
3878 break;
3879 case KVM_IRQCHIP_IOAPIC:
3880 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3881 break;
3882 default:
3883 r = -EINVAL;
3884 break;
3885 }
3886 return r;
3887 }
3888
3889 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3890 {
3891 struct kvm_pic *pic = kvm->arch.vpic;
3892 int r;
3893
3894 r = 0;
3895 switch (chip->chip_id) {
3896 case KVM_IRQCHIP_PIC_MASTER:
3897 spin_lock(&pic->lock);
3898 memcpy(&pic->pics[0], &chip->chip.pic,
3899 sizeof(struct kvm_pic_state));
3900 spin_unlock(&pic->lock);
3901 break;
3902 case KVM_IRQCHIP_PIC_SLAVE:
3903 spin_lock(&pic->lock);
3904 memcpy(&pic->pics[1], &chip->chip.pic,
3905 sizeof(struct kvm_pic_state));
3906 spin_unlock(&pic->lock);
3907 break;
3908 case KVM_IRQCHIP_IOAPIC:
3909 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3910 break;
3911 default:
3912 r = -EINVAL;
3913 break;
3914 }
3915 kvm_pic_update_irq(pic);
3916 return r;
3917 }
3918
3919 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3920 {
3921 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3922
3923 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3924
3925 mutex_lock(&kps->lock);
3926 memcpy(ps, &kps->channels, sizeof(*ps));
3927 mutex_unlock(&kps->lock);
3928 return 0;
3929 }
3930
3931 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3932 {
3933 int i;
3934 struct kvm_pit *pit = kvm->arch.vpit;
3935
3936 mutex_lock(&pit->pit_state.lock);
3937 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3938 for (i = 0; i < 3; i++)
3939 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3940 mutex_unlock(&pit->pit_state.lock);
3941 return 0;
3942 }
3943
3944 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3945 {
3946 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3947 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3948 sizeof(ps->channels));
3949 ps->flags = kvm->arch.vpit->pit_state.flags;
3950 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3951 memset(&ps->reserved, 0, sizeof(ps->reserved));
3952 return 0;
3953 }
3954
3955 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3956 {
3957 int start = 0;
3958 int i;
3959 u32 prev_legacy, cur_legacy;
3960 struct kvm_pit *pit = kvm->arch.vpit;
3961
3962 mutex_lock(&pit->pit_state.lock);
3963 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3964 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3965 if (!prev_legacy && cur_legacy)
3966 start = 1;
3967 memcpy(&pit->pit_state.channels, &ps->channels,
3968 sizeof(pit->pit_state.channels));
3969 pit->pit_state.flags = ps->flags;
3970 for (i = 0; i < 3; i++)
3971 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3972 start && i == 0);
3973 mutex_unlock(&pit->pit_state.lock);
3974 return 0;
3975 }
3976
3977 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3978 struct kvm_reinject_control *control)
3979 {
3980 struct kvm_pit *pit = kvm->arch.vpit;
3981
3982 if (!pit)
3983 return -ENXIO;
3984
3985 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3986 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3987 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3988 */
3989 mutex_lock(&pit->pit_state.lock);
3990 kvm_pit_set_reinject(pit, control->pit_reinject);
3991 mutex_unlock(&pit->pit_state.lock);
3992
3993 return 0;
3994 }
3995
3996 /**
3997 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3998 * @kvm: kvm instance
3999 * @log: slot id and address to which we copy the log
4000 *
4001 * Steps 1-4 below provide general overview of dirty page logging. See
4002 * kvm_get_dirty_log_protect() function description for additional details.
4003 *
4004 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4005 * always flush the TLB (step 4) even if previous step failed and the dirty
4006 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4007 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4008 * writes will be marked dirty for next log read.
4009 *
4010 * 1. Take a snapshot of the bit and clear it if needed.
4011 * 2. Write protect the corresponding page.
4012 * 3. Copy the snapshot to the userspace.
4013 * 4. Flush TLB's if needed.
4014 */
4015 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4016 {
4017 bool is_dirty = false;
4018 int r;
4019
4020 mutex_lock(&kvm->slots_lock);
4021
4022 /*
4023 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4024 */
4025 if (kvm_x86_ops->flush_log_dirty)
4026 kvm_x86_ops->flush_log_dirty(kvm);
4027
4028 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4029
4030 /*
4031 * All the TLBs can be flushed out of mmu lock, see the comments in
4032 * kvm_mmu_slot_remove_write_access().
4033 */
4034 lockdep_assert_held(&kvm->slots_lock);
4035 if (is_dirty)
4036 kvm_flush_remote_tlbs(kvm);
4037
4038 mutex_unlock(&kvm->slots_lock);
4039 return r;
4040 }
4041
4042 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4043 bool line_status)
4044 {
4045 if (!irqchip_in_kernel(kvm))
4046 return -ENXIO;
4047
4048 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4049 irq_event->irq, irq_event->level,
4050 line_status);
4051 return 0;
4052 }
4053
4054 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4055 struct kvm_enable_cap *cap)
4056 {
4057 int r;
4058
4059 if (cap->flags)
4060 return -EINVAL;
4061
4062 switch (cap->cap) {
4063 case KVM_CAP_DISABLE_QUIRKS:
4064 kvm->arch.disabled_quirks = cap->args[0];
4065 r = 0;
4066 break;
4067 case KVM_CAP_SPLIT_IRQCHIP: {
4068 mutex_lock(&kvm->lock);
4069 r = -EINVAL;
4070 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4071 goto split_irqchip_unlock;
4072 r = -EEXIST;
4073 if (irqchip_in_kernel(kvm))
4074 goto split_irqchip_unlock;
4075 if (kvm->created_vcpus)
4076 goto split_irqchip_unlock;
4077 r = kvm_setup_empty_irq_routing(kvm);
4078 if (r)
4079 goto split_irqchip_unlock;
4080 /* Pairs with irqchip_in_kernel. */
4081 smp_wmb();
4082 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4083 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4084 r = 0;
4085 split_irqchip_unlock:
4086 mutex_unlock(&kvm->lock);
4087 break;
4088 }
4089 case KVM_CAP_X2APIC_API:
4090 r = -EINVAL;
4091 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4092 break;
4093
4094 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4095 kvm->arch.x2apic_format = true;
4096 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4097 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4098
4099 r = 0;
4100 break;
4101 default:
4102 r = -EINVAL;
4103 break;
4104 }
4105 return r;
4106 }
4107
4108 long kvm_arch_vm_ioctl(struct file *filp,
4109 unsigned int ioctl, unsigned long arg)
4110 {
4111 struct kvm *kvm = filp->private_data;
4112 void __user *argp = (void __user *)arg;
4113 int r = -ENOTTY;
4114 /*
4115 * This union makes it completely explicit to gcc-3.x
4116 * that these two variables' stack usage should be
4117 * combined, not added together.
4118 */
4119 union {
4120 struct kvm_pit_state ps;
4121 struct kvm_pit_state2 ps2;
4122 struct kvm_pit_config pit_config;
4123 } u;
4124
4125 switch (ioctl) {
4126 case KVM_SET_TSS_ADDR:
4127 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4128 break;
4129 case KVM_SET_IDENTITY_MAP_ADDR: {
4130 u64 ident_addr;
4131
4132 mutex_lock(&kvm->lock);
4133 r = -EINVAL;
4134 if (kvm->created_vcpus)
4135 goto set_identity_unlock;
4136 r = -EFAULT;
4137 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4138 goto set_identity_unlock;
4139 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4140 set_identity_unlock:
4141 mutex_unlock(&kvm->lock);
4142 break;
4143 }
4144 case KVM_SET_NR_MMU_PAGES:
4145 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4146 break;
4147 case KVM_GET_NR_MMU_PAGES:
4148 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4149 break;
4150 case KVM_CREATE_IRQCHIP: {
4151 mutex_lock(&kvm->lock);
4152
4153 r = -EEXIST;
4154 if (irqchip_in_kernel(kvm))
4155 goto create_irqchip_unlock;
4156
4157 r = -EINVAL;
4158 if (kvm->created_vcpus)
4159 goto create_irqchip_unlock;
4160
4161 r = kvm_pic_init(kvm);
4162 if (r)
4163 goto create_irqchip_unlock;
4164
4165 r = kvm_ioapic_init(kvm);
4166 if (r) {
4167 kvm_pic_destroy(kvm);
4168 goto create_irqchip_unlock;
4169 }
4170
4171 r = kvm_setup_default_irq_routing(kvm);
4172 if (r) {
4173 kvm_ioapic_destroy(kvm);
4174 kvm_pic_destroy(kvm);
4175 goto create_irqchip_unlock;
4176 }
4177 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4178 smp_wmb();
4179 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4180 create_irqchip_unlock:
4181 mutex_unlock(&kvm->lock);
4182 break;
4183 }
4184 case KVM_CREATE_PIT:
4185 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4186 goto create_pit;
4187 case KVM_CREATE_PIT2:
4188 r = -EFAULT;
4189 if (copy_from_user(&u.pit_config, argp,
4190 sizeof(struct kvm_pit_config)))
4191 goto out;
4192 create_pit:
4193 mutex_lock(&kvm->lock);
4194 r = -EEXIST;
4195 if (kvm->arch.vpit)
4196 goto create_pit_unlock;
4197 r = -ENOMEM;
4198 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4199 if (kvm->arch.vpit)
4200 r = 0;
4201 create_pit_unlock:
4202 mutex_unlock(&kvm->lock);
4203 break;
4204 case KVM_GET_IRQCHIP: {
4205 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4206 struct kvm_irqchip *chip;
4207
4208 chip = memdup_user(argp, sizeof(*chip));
4209 if (IS_ERR(chip)) {
4210 r = PTR_ERR(chip);
4211 goto out;
4212 }
4213
4214 r = -ENXIO;
4215 if (!irqchip_kernel(kvm))
4216 goto get_irqchip_out;
4217 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4218 if (r)
4219 goto get_irqchip_out;
4220 r = -EFAULT;
4221 if (copy_to_user(argp, chip, sizeof *chip))
4222 goto get_irqchip_out;
4223 r = 0;
4224 get_irqchip_out:
4225 kfree(chip);
4226 break;
4227 }
4228 case KVM_SET_IRQCHIP: {
4229 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4230 struct kvm_irqchip *chip;
4231
4232 chip = memdup_user(argp, sizeof(*chip));
4233 if (IS_ERR(chip)) {
4234 r = PTR_ERR(chip);
4235 goto out;
4236 }
4237
4238 r = -ENXIO;
4239 if (!irqchip_kernel(kvm))
4240 goto set_irqchip_out;
4241 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4242 if (r)
4243 goto set_irqchip_out;
4244 r = 0;
4245 set_irqchip_out:
4246 kfree(chip);
4247 break;
4248 }
4249 case KVM_GET_PIT: {
4250 r = -EFAULT;
4251 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4252 goto out;
4253 r = -ENXIO;
4254 if (!kvm->arch.vpit)
4255 goto out;
4256 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4257 if (r)
4258 goto out;
4259 r = -EFAULT;
4260 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4261 goto out;
4262 r = 0;
4263 break;
4264 }
4265 case KVM_SET_PIT: {
4266 r = -EFAULT;
4267 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4268 goto out;
4269 r = -ENXIO;
4270 if (!kvm->arch.vpit)
4271 goto out;
4272 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4273 break;
4274 }
4275 case KVM_GET_PIT2: {
4276 r = -ENXIO;
4277 if (!kvm->arch.vpit)
4278 goto out;
4279 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4280 if (r)
4281 goto out;
4282 r = -EFAULT;
4283 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4284 goto out;
4285 r = 0;
4286 break;
4287 }
4288 case KVM_SET_PIT2: {
4289 r = -EFAULT;
4290 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4291 goto out;
4292 r = -ENXIO;
4293 if (!kvm->arch.vpit)
4294 goto out;
4295 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4296 break;
4297 }
4298 case KVM_REINJECT_CONTROL: {
4299 struct kvm_reinject_control control;
4300 r = -EFAULT;
4301 if (copy_from_user(&control, argp, sizeof(control)))
4302 goto out;
4303 r = kvm_vm_ioctl_reinject(kvm, &control);
4304 break;
4305 }
4306 case KVM_SET_BOOT_CPU_ID:
4307 r = 0;
4308 mutex_lock(&kvm->lock);
4309 if (kvm->created_vcpus)
4310 r = -EBUSY;
4311 else
4312 kvm->arch.bsp_vcpu_id = arg;
4313 mutex_unlock(&kvm->lock);
4314 break;
4315 case KVM_XEN_HVM_CONFIG: {
4316 struct kvm_xen_hvm_config xhc;
4317 r = -EFAULT;
4318 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4319 goto out;
4320 r = -EINVAL;
4321 if (xhc.flags)
4322 goto out;
4323 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4324 r = 0;
4325 break;
4326 }
4327 case KVM_SET_CLOCK: {
4328 struct kvm_clock_data user_ns;
4329 u64 now_ns;
4330
4331 r = -EFAULT;
4332 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4333 goto out;
4334
4335 r = -EINVAL;
4336 if (user_ns.flags)
4337 goto out;
4338
4339 r = 0;
4340 /*
4341 * TODO: userspace has to take care of races with VCPU_RUN, so
4342 * kvm_gen_update_masterclock() can be cut down to locked
4343 * pvclock_update_vm_gtod_copy().
4344 */
4345 kvm_gen_update_masterclock(kvm);
4346 now_ns = get_kvmclock_ns(kvm);
4347 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4348 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4349 break;
4350 }
4351 case KVM_GET_CLOCK: {
4352 struct kvm_clock_data user_ns;
4353 u64 now_ns;
4354
4355 now_ns = get_kvmclock_ns(kvm);
4356 user_ns.clock = now_ns;
4357 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4358 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4359
4360 r = -EFAULT;
4361 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4362 goto out;
4363 r = 0;
4364 break;
4365 }
4366 case KVM_ENABLE_CAP: {
4367 struct kvm_enable_cap cap;
4368
4369 r = -EFAULT;
4370 if (copy_from_user(&cap, argp, sizeof(cap)))
4371 goto out;
4372 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4373 break;
4374 }
4375 default:
4376 r = -ENOTTY;
4377 }
4378 out:
4379 return r;
4380 }
4381
4382 static void kvm_init_msr_list(void)
4383 {
4384 u32 dummy[2];
4385 unsigned i, j;
4386
4387 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4388 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4389 continue;
4390
4391 /*
4392 * Even MSRs that are valid in the host may not be exposed
4393 * to the guests in some cases.
4394 */
4395 switch (msrs_to_save[i]) {
4396 case MSR_IA32_BNDCFGS:
4397 if (!kvm_x86_ops->mpx_supported())
4398 continue;
4399 break;
4400 case MSR_TSC_AUX:
4401 if (!kvm_x86_ops->rdtscp_supported())
4402 continue;
4403 break;
4404 default:
4405 break;
4406 }
4407
4408 if (j < i)
4409 msrs_to_save[j] = msrs_to_save[i];
4410 j++;
4411 }
4412 num_msrs_to_save = j;
4413
4414 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4415 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4416 continue;
4417
4418 if (j < i)
4419 emulated_msrs[j] = emulated_msrs[i];
4420 j++;
4421 }
4422 num_emulated_msrs = j;
4423
4424 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4425 struct kvm_msr_entry msr;
4426
4427 msr.index = msr_based_features[i];
4428 if (kvm_get_msr_feature(&msr))
4429 continue;
4430
4431 if (j < i)
4432 msr_based_features[j] = msr_based_features[i];
4433 j++;
4434 }
4435 num_msr_based_features = j;
4436 }
4437
4438 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4439 const void *v)
4440 {
4441 int handled = 0;
4442 int n;
4443
4444 do {
4445 n = min(len, 8);
4446 if (!(lapic_in_kernel(vcpu) &&
4447 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4448 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4449 break;
4450 handled += n;
4451 addr += n;
4452 len -= n;
4453 v += n;
4454 } while (len);
4455
4456 return handled;
4457 }
4458
4459 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4460 {
4461 int handled = 0;
4462 int n;
4463
4464 do {
4465 n = min(len, 8);
4466 if (!(lapic_in_kernel(vcpu) &&
4467 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4468 addr, n, v))
4469 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4470 break;
4471 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4472 handled += n;
4473 addr += n;
4474 len -= n;
4475 v += n;
4476 } while (len);
4477
4478 return handled;
4479 }
4480
4481 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4482 struct kvm_segment *var, int seg)
4483 {
4484 kvm_x86_ops->set_segment(vcpu, var, seg);
4485 }
4486
4487 void kvm_get_segment(struct kvm_vcpu *vcpu,
4488 struct kvm_segment *var, int seg)
4489 {
4490 kvm_x86_ops->get_segment(vcpu, var, seg);
4491 }
4492
4493 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4494 struct x86_exception *exception)
4495 {
4496 gpa_t t_gpa;
4497
4498 BUG_ON(!mmu_is_nested(vcpu));
4499
4500 /* NPT walks are always user-walks */
4501 access |= PFERR_USER_MASK;
4502 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4503
4504 return t_gpa;
4505 }
4506
4507 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4508 struct x86_exception *exception)
4509 {
4510 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4511 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4512 }
4513
4514 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4515 struct x86_exception *exception)
4516 {
4517 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4518 access |= PFERR_FETCH_MASK;
4519 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4520 }
4521
4522 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4523 struct x86_exception *exception)
4524 {
4525 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4526 access |= PFERR_WRITE_MASK;
4527 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4528 }
4529
4530 /* uses this to access any guest's mapped memory without checking CPL */
4531 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4532 struct x86_exception *exception)
4533 {
4534 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4535 }
4536
4537 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4538 struct kvm_vcpu *vcpu, u32 access,
4539 struct x86_exception *exception)
4540 {
4541 void *data = val;
4542 int r = X86EMUL_CONTINUE;
4543
4544 while (bytes) {
4545 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4546 exception);
4547 unsigned offset = addr & (PAGE_SIZE-1);
4548 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4549 int ret;
4550
4551 if (gpa == UNMAPPED_GVA)
4552 return X86EMUL_PROPAGATE_FAULT;
4553 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4554 offset, toread);
4555 if (ret < 0) {
4556 r = X86EMUL_IO_NEEDED;
4557 goto out;
4558 }
4559
4560 bytes -= toread;
4561 data += toread;
4562 addr += toread;
4563 }
4564 out:
4565 return r;
4566 }
4567
4568 /* used for instruction fetching */
4569 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4570 gva_t addr, void *val, unsigned int bytes,
4571 struct x86_exception *exception)
4572 {
4573 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4574 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4575 unsigned offset;
4576 int ret;
4577
4578 /* Inline kvm_read_guest_virt_helper for speed. */
4579 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4580 exception);
4581 if (unlikely(gpa == UNMAPPED_GVA))
4582 return X86EMUL_PROPAGATE_FAULT;
4583
4584 offset = addr & (PAGE_SIZE-1);
4585 if (WARN_ON(offset + bytes > PAGE_SIZE))
4586 bytes = (unsigned)PAGE_SIZE - offset;
4587 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4588 offset, bytes);
4589 if (unlikely(ret < 0))
4590 return X86EMUL_IO_NEEDED;
4591
4592 return X86EMUL_CONTINUE;
4593 }
4594
4595 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4596 gva_t addr, void *val, unsigned int bytes,
4597 struct x86_exception *exception)
4598 {
4599 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4600 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4601
4602 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4603 exception);
4604 }
4605 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4606
4607 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4608 gva_t addr, void *val, unsigned int bytes,
4609 struct x86_exception *exception)
4610 {
4611 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4612 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4613 }
4614
4615 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4616 unsigned long addr, void *val, unsigned int bytes)
4617 {
4618 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4619 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4620
4621 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4622 }
4623
4624 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4625 gva_t addr, void *val,
4626 unsigned int bytes,
4627 struct x86_exception *exception)
4628 {
4629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4630 void *data = val;
4631 int r = X86EMUL_CONTINUE;
4632
4633 /* kvm_write_guest_virt_system can pull in tons of pages. */
4634 vcpu->arch.l1tf_flush_l1d = true;
4635
4636 while (bytes) {
4637 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4638 PFERR_WRITE_MASK,
4639 exception);
4640 unsigned offset = addr & (PAGE_SIZE-1);
4641 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4642 int ret;
4643
4644 if (gpa == UNMAPPED_GVA)
4645 return X86EMUL_PROPAGATE_FAULT;
4646 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4647 if (ret < 0) {
4648 r = X86EMUL_IO_NEEDED;
4649 goto out;
4650 }
4651
4652 bytes -= towrite;
4653 data += towrite;
4654 addr += towrite;
4655 }
4656 out:
4657 return r;
4658 }
4659 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4660
4661 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4662 gpa_t gpa, bool write)
4663 {
4664 /* For APIC access vmexit */
4665 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4666 return 1;
4667
4668 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4669 trace_vcpu_match_mmio(gva, gpa, write, true);
4670 return 1;
4671 }
4672
4673 return 0;
4674 }
4675
4676 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4677 gpa_t *gpa, struct x86_exception *exception,
4678 bool write)
4679 {
4680 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4681 | (write ? PFERR_WRITE_MASK : 0);
4682
4683 /*
4684 * currently PKRU is only applied to ept enabled guest so
4685 * there is no pkey in EPT page table for L1 guest or EPT
4686 * shadow page table for L2 guest.
4687 */
4688 if (vcpu_match_mmio_gva(vcpu, gva)
4689 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4690 vcpu->arch.access, 0, access)) {
4691 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4692 (gva & (PAGE_SIZE - 1));
4693 trace_vcpu_match_mmio(gva, *gpa, write, false);
4694 return 1;
4695 }
4696
4697 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4698
4699 if (*gpa == UNMAPPED_GVA)
4700 return -1;
4701
4702 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4703 }
4704
4705 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4706 const void *val, int bytes)
4707 {
4708 int ret;
4709
4710 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4711 if (ret < 0)
4712 return 0;
4713 kvm_page_track_write(vcpu, gpa, val, bytes);
4714 return 1;
4715 }
4716
4717 struct read_write_emulator_ops {
4718 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4719 int bytes);
4720 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4721 void *val, int bytes);
4722 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4723 int bytes, void *val);
4724 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4725 void *val, int bytes);
4726 bool write;
4727 };
4728
4729 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4730 {
4731 if (vcpu->mmio_read_completed) {
4732 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4733 vcpu->mmio_fragments[0].gpa, val);
4734 vcpu->mmio_read_completed = 0;
4735 return 1;
4736 }
4737
4738 return 0;
4739 }
4740
4741 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4742 void *val, int bytes)
4743 {
4744 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4745 }
4746
4747 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4748 void *val, int bytes)
4749 {
4750 return emulator_write_phys(vcpu, gpa, val, bytes);
4751 }
4752
4753 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4754 {
4755 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4756 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4757 }
4758
4759 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4760 void *val, int bytes)
4761 {
4762 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4763 return X86EMUL_IO_NEEDED;
4764 }
4765
4766 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4767 void *val, int bytes)
4768 {
4769 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4770
4771 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4772 return X86EMUL_CONTINUE;
4773 }
4774
4775 static const struct read_write_emulator_ops read_emultor = {
4776 .read_write_prepare = read_prepare,
4777 .read_write_emulate = read_emulate,
4778 .read_write_mmio = vcpu_mmio_read,
4779 .read_write_exit_mmio = read_exit_mmio,
4780 };
4781
4782 static const struct read_write_emulator_ops write_emultor = {
4783 .read_write_emulate = write_emulate,
4784 .read_write_mmio = write_mmio,
4785 .read_write_exit_mmio = write_exit_mmio,
4786 .write = true,
4787 };
4788
4789 static int emulator_read_write_onepage(unsigned long addr, void *val,
4790 unsigned int bytes,
4791 struct x86_exception *exception,
4792 struct kvm_vcpu *vcpu,
4793 const struct read_write_emulator_ops *ops)
4794 {
4795 gpa_t gpa;
4796 int handled, ret;
4797 bool write = ops->write;
4798 struct kvm_mmio_fragment *frag;
4799 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4800
4801 /*
4802 * If the exit was due to a NPF we may already have a GPA.
4803 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4804 * Note, this cannot be used on string operations since string
4805 * operation using rep will only have the initial GPA from the NPF
4806 * occurred.
4807 */
4808 if (vcpu->arch.gpa_available &&
4809 emulator_can_use_gpa(ctxt) &&
4810 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4811 gpa = vcpu->arch.gpa_val;
4812 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4813 } else {
4814 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4815 if (ret < 0)
4816 return X86EMUL_PROPAGATE_FAULT;
4817 }
4818
4819 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
4820 return X86EMUL_CONTINUE;
4821
4822 /*
4823 * Is this MMIO handled locally?
4824 */
4825 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4826 if (handled == bytes)
4827 return X86EMUL_CONTINUE;
4828
4829 gpa += handled;
4830 bytes -= handled;
4831 val += handled;
4832
4833 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4834 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4835 frag->gpa = gpa;
4836 frag->data = val;
4837 frag->len = bytes;
4838 return X86EMUL_CONTINUE;
4839 }
4840
4841 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4842 unsigned long addr,
4843 void *val, unsigned int bytes,
4844 struct x86_exception *exception,
4845 const struct read_write_emulator_ops *ops)
4846 {
4847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4848 gpa_t gpa;
4849 int rc;
4850
4851 if (ops->read_write_prepare &&
4852 ops->read_write_prepare(vcpu, val, bytes))
4853 return X86EMUL_CONTINUE;
4854
4855 vcpu->mmio_nr_fragments = 0;
4856
4857 /* Crossing a page boundary? */
4858 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4859 int now;
4860
4861 now = -addr & ~PAGE_MASK;
4862 rc = emulator_read_write_onepage(addr, val, now, exception,
4863 vcpu, ops);
4864
4865 if (rc != X86EMUL_CONTINUE)
4866 return rc;
4867 addr += now;
4868 if (ctxt->mode != X86EMUL_MODE_PROT64)
4869 addr = (u32)addr;
4870 val += now;
4871 bytes -= now;
4872 }
4873
4874 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4875 vcpu, ops);
4876 if (rc != X86EMUL_CONTINUE)
4877 return rc;
4878
4879 if (!vcpu->mmio_nr_fragments)
4880 return rc;
4881
4882 gpa = vcpu->mmio_fragments[0].gpa;
4883
4884 vcpu->mmio_needed = 1;
4885 vcpu->mmio_cur_fragment = 0;
4886
4887 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4888 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4889 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4890 vcpu->run->mmio.phys_addr = gpa;
4891
4892 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4893 }
4894
4895 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4896 unsigned long addr,
4897 void *val,
4898 unsigned int bytes,
4899 struct x86_exception *exception)
4900 {
4901 return emulator_read_write(ctxt, addr, val, bytes,
4902 exception, &read_emultor);
4903 }
4904
4905 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4906 unsigned long addr,
4907 const void *val,
4908 unsigned int bytes,
4909 struct x86_exception *exception)
4910 {
4911 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4912 exception, &write_emultor);
4913 }
4914
4915 #define CMPXCHG_TYPE(t, ptr, old, new) \
4916 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4917
4918 #ifdef CONFIG_X86_64
4919 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4920 #else
4921 # define CMPXCHG64(ptr, old, new) \
4922 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4923 #endif
4924
4925 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4926 unsigned long addr,
4927 const void *old,
4928 const void *new,
4929 unsigned int bytes,
4930 struct x86_exception *exception)
4931 {
4932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4933 gpa_t gpa;
4934 struct page *page;
4935 char *kaddr;
4936 bool exchanged;
4937
4938 /* guests cmpxchg8b have to be emulated atomically */
4939 if (bytes > 8 || (bytes & (bytes - 1)))
4940 goto emul_write;
4941
4942 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4943
4944 if (gpa == UNMAPPED_GVA ||
4945 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4946 goto emul_write;
4947
4948 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4949 goto emul_write;
4950
4951 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4952 if (is_error_page(page))
4953 goto emul_write;
4954
4955 kaddr = kmap_atomic(page);
4956 kaddr += offset_in_page(gpa);
4957 switch (bytes) {
4958 case 1:
4959 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4960 break;
4961 case 2:
4962 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4963 break;
4964 case 4:
4965 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4966 break;
4967 case 8:
4968 exchanged = CMPXCHG64(kaddr, old, new);
4969 break;
4970 default:
4971 BUG();
4972 }
4973 kunmap_atomic(kaddr);
4974 kvm_release_page_dirty(page);
4975
4976 if (!exchanged)
4977 return X86EMUL_CMPXCHG_FAILED;
4978
4979 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4980 kvm_page_track_write(vcpu, gpa, new, bytes);
4981
4982 return X86EMUL_CONTINUE;
4983
4984 emul_write:
4985 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4986
4987 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4988 }
4989
4990 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4991 {
4992 int r = 0, i;
4993
4994 for (i = 0; i < vcpu->arch.pio.count; i++) {
4995 if (vcpu->arch.pio.in)
4996 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4997 vcpu->arch.pio.size, pd);
4998 else
4999 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5000 vcpu->arch.pio.port, vcpu->arch.pio.size,
5001 pd);
5002 if (r)
5003 break;
5004 pd += vcpu->arch.pio.size;
5005 }
5006 return r;
5007 }
5008
5009 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5010 unsigned short port, void *val,
5011 unsigned int count, bool in)
5012 {
5013 vcpu->arch.pio.port = port;
5014 vcpu->arch.pio.in = in;
5015 vcpu->arch.pio.count = count;
5016 vcpu->arch.pio.size = size;
5017
5018 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5019 vcpu->arch.pio.count = 0;
5020 return 1;
5021 }
5022
5023 vcpu->run->exit_reason = KVM_EXIT_IO;
5024 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5025 vcpu->run->io.size = size;
5026 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5027 vcpu->run->io.count = count;
5028 vcpu->run->io.port = port;
5029
5030 return 0;
5031 }
5032
5033 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5034 int size, unsigned short port, void *val,
5035 unsigned int count)
5036 {
5037 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5038 int ret;
5039
5040 if (vcpu->arch.pio.count)
5041 goto data_avail;
5042
5043 memset(vcpu->arch.pio_data, 0, size * count);
5044
5045 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5046 if (ret) {
5047 data_avail:
5048 memcpy(val, vcpu->arch.pio_data, size * count);
5049 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5050 vcpu->arch.pio.count = 0;
5051 return 1;
5052 }
5053
5054 return 0;
5055 }
5056
5057 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5058 int size, unsigned short port,
5059 const void *val, unsigned int count)
5060 {
5061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5062
5063 memcpy(vcpu->arch.pio_data, val, size * count);
5064 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5065 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5066 }
5067
5068 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5069 {
5070 return kvm_x86_ops->get_segment_base(vcpu, seg);
5071 }
5072
5073 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5074 {
5075 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5076 }
5077
5078 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5079 {
5080 if (!need_emulate_wbinvd(vcpu))
5081 return X86EMUL_CONTINUE;
5082
5083 if (kvm_x86_ops->has_wbinvd_exit()) {
5084 int cpu = get_cpu();
5085
5086 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5087 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5088 wbinvd_ipi, NULL, 1);
5089 put_cpu();
5090 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5091 } else
5092 wbinvd();
5093 return X86EMUL_CONTINUE;
5094 }
5095
5096 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5097 {
5098 kvm_emulate_wbinvd_noskip(vcpu);
5099 return kvm_skip_emulated_instruction(vcpu);
5100 }
5101 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5102
5103
5104
5105 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5106 {
5107 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5108 }
5109
5110 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5111 unsigned long *dest)
5112 {
5113 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5114 }
5115
5116 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5117 unsigned long value)
5118 {
5119
5120 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5121 }
5122
5123 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5124 {
5125 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5126 }
5127
5128 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5129 {
5130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5131 unsigned long value;
5132
5133 switch (cr) {
5134 case 0:
5135 value = kvm_read_cr0(vcpu);
5136 break;
5137 case 2:
5138 value = vcpu->arch.cr2;
5139 break;
5140 case 3:
5141 value = kvm_read_cr3(vcpu);
5142 break;
5143 case 4:
5144 value = kvm_read_cr4(vcpu);
5145 break;
5146 case 8:
5147 value = kvm_get_cr8(vcpu);
5148 break;
5149 default:
5150 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5151 return 0;
5152 }
5153
5154 return value;
5155 }
5156
5157 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5158 {
5159 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5160 int res = 0;
5161
5162 switch (cr) {
5163 case 0:
5164 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5165 break;
5166 case 2:
5167 vcpu->arch.cr2 = val;
5168 break;
5169 case 3:
5170 res = kvm_set_cr3(vcpu, val);
5171 break;
5172 case 4:
5173 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5174 break;
5175 case 8:
5176 res = kvm_set_cr8(vcpu, val);
5177 break;
5178 default:
5179 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5180 res = -1;
5181 }
5182
5183 return res;
5184 }
5185
5186 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5187 {
5188 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5189 }
5190
5191 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5192 {
5193 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5194 }
5195
5196 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5197 {
5198 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5199 }
5200
5201 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5202 {
5203 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5204 }
5205
5206 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5207 {
5208 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5209 }
5210
5211 static unsigned long emulator_get_cached_segment_base(
5212 struct x86_emulate_ctxt *ctxt, int seg)
5213 {
5214 return get_segment_base(emul_to_vcpu(ctxt), seg);
5215 }
5216
5217 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5218 struct desc_struct *desc, u32 *base3,
5219 int seg)
5220 {
5221 struct kvm_segment var;
5222
5223 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5224 *selector = var.selector;
5225
5226 if (var.unusable) {
5227 memset(desc, 0, sizeof(*desc));
5228 if (base3)
5229 *base3 = 0;
5230 return false;
5231 }
5232
5233 if (var.g)
5234 var.limit >>= 12;
5235 set_desc_limit(desc, var.limit);
5236 set_desc_base(desc, (unsigned long)var.base);
5237 #ifdef CONFIG_X86_64
5238 if (base3)
5239 *base3 = var.base >> 32;
5240 #endif
5241 desc->type = var.type;
5242 desc->s = var.s;
5243 desc->dpl = var.dpl;
5244 desc->p = var.present;
5245 desc->avl = var.avl;
5246 desc->l = var.l;
5247 desc->d = var.db;
5248 desc->g = var.g;
5249
5250 return true;
5251 }
5252
5253 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5254 struct desc_struct *desc, u32 base3,
5255 int seg)
5256 {
5257 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5258 struct kvm_segment var;
5259
5260 var.selector = selector;
5261 var.base = get_desc_base(desc);
5262 #ifdef CONFIG_X86_64
5263 var.base |= ((u64)base3) << 32;
5264 #endif
5265 var.limit = get_desc_limit(desc);
5266 if (desc->g)
5267 var.limit = (var.limit << 12) | 0xfff;
5268 var.type = desc->type;
5269 var.dpl = desc->dpl;
5270 var.db = desc->d;
5271 var.s = desc->s;
5272 var.l = desc->l;
5273 var.g = desc->g;
5274 var.avl = desc->avl;
5275 var.present = desc->p;
5276 var.unusable = !var.present;
5277 var.padding = 0;
5278
5279 kvm_set_segment(vcpu, &var, seg);
5280 return;
5281 }
5282
5283 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5284 u32 msr_index, u64 *pdata)
5285 {
5286 struct msr_data msr;
5287 int r;
5288
5289 msr.index = msr_index;
5290 msr.host_initiated = false;
5291 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5292 if (r)
5293 return r;
5294
5295 *pdata = msr.data;
5296 return 0;
5297 }
5298
5299 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5300 u32 msr_index, u64 data)
5301 {
5302 struct msr_data msr;
5303
5304 msr.data = data;
5305 msr.index = msr_index;
5306 msr.host_initiated = false;
5307 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5308 }
5309
5310 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5311 {
5312 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5313
5314 return vcpu->arch.smbase;
5315 }
5316
5317 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5318 {
5319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5320
5321 vcpu->arch.smbase = smbase;
5322 }
5323
5324 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5325 u32 pmc)
5326 {
5327 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5328 }
5329
5330 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5331 u32 pmc, u64 *pdata)
5332 {
5333 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5334 }
5335
5336 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5337 {
5338 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5339 }
5340
5341 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5342 struct x86_instruction_info *info,
5343 enum x86_intercept_stage stage)
5344 {
5345 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5346 }
5347
5348 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5349 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5350 {
5351 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5352 }
5353
5354 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5355 {
5356 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5357 }
5358
5359 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5360 {
5361 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5362 }
5363
5364 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5365 {
5366 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5367 }
5368
5369 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5370 {
5371 return emul_to_vcpu(ctxt)->arch.hflags;
5372 }
5373
5374 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5375 {
5376 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5377 }
5378
5379 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5380 {
5381 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5382 }
5383
5384 static const struct x86_emulate_ops emulate_ops = {
5385 .read_gpr = emulator_read_gpr,
5386 .write_gpr = emulator_write_gpr,
5387 .read_std = kvm_read_guest_virt_system,
5388 .write_std = kvm_write_guest_virt_system,
5389 .read_phys = kvm_read_guest_phys_system,
5390 .fetch = kvm_fetch_guest_virt,
5391 .read_emulated = emulator_read_emulated,
5392 .write_emulated = emulator_write_emulated,
5393 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5394 .invlpg = emulator_invlpg,
5395 .pio_in_emulated = emulator_pio_in_emulated,
5396 .pio_out_emulated = emulator_pio_out_emulated,
5397 .get_segment = emulator_get_segment,
5398 .set_segment = emulator_set_segment,
5399 .get_cached_segment_base = emulator_get_cached_segment_base,
5400 .get_gdt = emulator_get_gdt,
5401 .get_idt = emulator_get_idt,
5402 .set_gdt = emulator_set_gdt,
5403 .set_idt = emulator_set_idt,
5404 .get_cr = emulator_get_cr,
5405 .set_cr = emulator_set_cr,
5406 .cpl = emulator_get_cpl,
5407 .get_dr = emulator_get_dr,
5408 .set_dr = emulator_set_dr,
5409 .get_smbase = emulator_get_smbase,
5410 .set_smbase = emulator_set_smbase,
5411 .set_msr = emulator_set_msr,
5412 .get_msr = emulator_get_msr,
5413 .check_pmc = emulator_check_pmc,
5414 .read_pmc = emulator_read_pmc,
5415 .halt = emulator_halt,
5416 .wbinvd = emulator_wbinvd,
5417 .fix_hypercall = emulator_fix_hypercall,
5418 .intercept = emulator_intercept,
5419 .get_cpuid = emulator_get_cpuid,
5420 .set_nmi_mask = emulator_set_nmi_mask,
5421 .get_hflags = emulator_get_hflags,
5422 .set_hflags = emulator_set_hflags,
5423 .pre_leave_smm = emulator_pre_leave_smm,
5424 };
5425
5426 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5427 {
5428 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5429 /*
5430 * an sti; sti; sequence only disable interrupts for the first
5431 * instruction. So, if the last instruction, be it emulated or
5432 * not, left the system with the INT_STI flag enabled, it
5433 * means that the last instruction is an sti. We should not
5434 * leave the flag on in this case. The same goes for mov ss
5435 */
5436 if (int_shadow & mask)
5437 mask = 0;
5438 if (unlikely(int_shadow || mask)) {
5439 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5440 if (!mask)
5441 kvm_make_request(KVM_REQ_EVENT, vcpu);
5442 }
5443 }
5444
5445 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5446 {
5447 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5448 if (ctxt->exception.vector == PF_VECTOR)
5449 return kvm_propagate_fault(vcpu, &ctxt->exception);
5450
5451 if (ctxt->exception.error_code_valid)
5452 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5453 ctxt->exception.error_code);
5454 else
5455 kvm_queue_exception(vcpu, ctxt->exception.vector);
5456 return false;
5457 }
5458
5459 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5460 {
5461 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5462 int cs_db, cs_l;
5463
5464 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5465
5466 ctxt->eflags = kvm_get_rflags(vcpu);
5467 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5468
5469 ctxt->eip = kvm_rip_read(vcpu);
5470 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5471 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5472 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5473 cs_db ? X86EMUL_MODE_PROT32 :
5474 X86EMUL_MODE_PROT16;
5475 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5476 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5477 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5478
5479 init_decode_cache(ctxt);
5480 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5481 }
5482
5483 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5484 {
5485 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5486 int ret;
5487
5488 init_emulate_ctxt(vcpu);
5489
5490 ctxt->op_bytes = 2;
5491 ctxt->ad_bytes = 2;
5492 ctxt->_eip = ctxt->eip + inc_eip;
5493 ret = emulate_int_real(ctxt, irq);
5494
5495 if (ret != X86EMUL_CONTINUE)
5496 return EMULATE_FAIL;
5497
5498 ctxt->eip = ctxt->_eip;
5499 kvm_rip_write(vcpu, ctxt->eip);
5500 kvm_set_rflags(vcpu, ctxt->eflags);
5501
5502 if (irq == NMI_VECTOR)
5503 vcpu->arch.nmi_pending = 0;
5504 else
5505 vcpu->arch.interrupt.pending = false;
5506
5507 return EMULATE_DONE;
5508 }
5509 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5510
5511 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5512 {
5513 int r = EMULATE_DONE;
5514
5515 ++vcpu->stat.insn_emulation_fail;
5516 trace_kvm_emulate_insn_failed(vcpu);
5517 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5518 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5519 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5520 vcpu->run->internal.ndata = 0;
5521 r = EMULATE_USER_EXIT;
5522 }
5523 kvm_queue_exception(vcpu, UD_VECTOR);
5524
5525 return r;
5526 }
5527
5528 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5529 bool write_fault_to_shadow_pgtable,
5530 int emulation_type)
5531 {
5532 gpa_t gpa = cr2;
5533 kvm_pfn_t pfn;
5534
5535 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5536 return false;
5537
5538 if (!vcpu->arch.mmu.direct_map) {
5539 /*
5540 * Write permission should be allowed since only
5541 * write access need to be emulated.
5542 */
5543 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5544
5545 /*
5546 * If the mapping is invalid in guest, let cpu retry
5547 * it to generate fault.
5548 */
5549 if (gpa == UNMAPPED_GVA)
5550 return true;
5551 }
5552
5553 /*
5554 * Do not retry the unhandleable instruction if it faults on the
5555 * readonly host memory, otherwise it will goto a infinite loop:
5556 * retry instruction -> write #PF -> emulation fail -> retry
5557 * instruction -> ...
5558 */
5559 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5560
5561 /*
5562 * If the instruction failed on the error pfn, it can not be fixed,
5563 * report the error to userspace.
5564 */
5565 if (is_error_noslot_pfn(pfn))
5566 return false;
5567
5568 kvm_release_pfn_clean(pfn);
5569
5570 /* The instructions are well-emulated on direct mmu. */
5571 if (vcpu->arch.mmu.direct_map) {
5572 unsigned int indirect_shadow_pages;
5573
5574 spin_lock(&vcpu->kvm->mmu_lock);
5575 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5576 spin_unlock(&vcpu->kvm->mmu_lock);
5577
5578 if (indirect_shadow_pages)
5579 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5580
5581 return true;
5582 }
5583
5584 /*
5585 * if emulation was due to access to shadowed page table
5586 * and it failed try to unshadow page and re-enter the
5587 * guest to let CPU execute the instruction.
5588 */
5589 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5590
5591 /*
5592 * If the access faults on its page table, it can not
5593 * be fixed by unprotecting shadow page and it should
5594 * be reported to userspace.
5595 */
5596 return !write_fault_to_shadow_pgtable;
5597 }
5598
5599 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5600 unsigned long cr2, int emulation_type)
5601 {
5602 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5603 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5604
5605 last_retry_eip = vcpu->arch.last_retry_eip;
5606 last_retry_addr = vcpu->arch.last_retry_addr;
5607
5608 /*
5609 * If the emulation is caused by #PF and it is non-page_table
5610 * writing instruction, it means the VM-EXIT is caused by shadow
5611 * page protected, we can zap the shadow page and retry this
5612 * instruction directly.
5613 *
5614 * Note: if the guest uses a non-page-table modifying instruction
5615 * on the PDE that points to the instruction, then we will unmap
5616 * the instruction and go to an infinite loop. So, we cache the
5617 * last retried eip and the last fault address, if we meet the eip
5618 * and the address again, we can break out of the potential infinite
5619 * loop.
5620 */
5621 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5622
5623 if (!(emulation_type & EMULTYPE_RETRY))
5624 return false;
5625
5626 if (x86_page_table_writing_insn(ctxt))
5627 return false;
5628
5629 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5630 return false;
5631
5632 vcpu->arch.last_retry_eip = ctxt->eip;
5633 vcpu->arch.last_retry_addr = cr2;
5634
5635 if (!vcpu->arch.mmu.direct_map)
5636 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5637
5638 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5639
5640 return true;
5641 }
5642
5643 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5644 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5645
5646 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5647 {
5648 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5649 /* This is a good place to trace that we are exiting SMM. */
5650 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5651
5652 /* Process a latched INIT or SMI, if any. */
5653 kvm_make_request(KVM_REQ_EVENT, vcpu);
5654 }
5655
5656 kvm_mmu_reset_context(vcpu);
5657 }
5658
5659 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5660 {
5661 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5662
5663 vcpu->arch.hflags = emul_flags;
5664
5665 if (changed & HF_SMM_MASK)
5666 kvm_smm_changed(vcpu);
5667 }
5668
5669 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5670 unsigned long *db)
5671 {
5672 u32 dr6 = 0;
5673 int i;
5674 u32 enable, rwlen;
5675
5676 enable = dr7;
5677 rwlen = dr7 >> 16;
5678 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5679 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5680 dr6 |= (1 << i);
5681 return dr6;
5682 }
5683
5684 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5685 {
5686 struct kvm_run *kvm_run = vcpu->run;
5687
5688 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5689 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5690 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5691 kvm_run->debug.arch.exception = DB_VECTOR;
5692 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5693 *r = EMULATE_USER_EXIT;
5694 } else {
5695 /*
5696 * "Certain debug exceptions may clear bit 0-3. The
5697 * remaining contents of the DR6 register are never
5698 * cleared by the processor".
5699 */
5700 vcpu->arch.dr6 &= ~15;
5701 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5702 kvm_queue_exception(vcpu, DB_VECTOR);
5703 }
5704 }
5705
5706 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5707 {
5708 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5709 int r = EMULATE_DONE;
5710
5711 kvm_x86_ops->skip_emulated_instruction(vcpu);
5712
5713 /*
5714 * rflags is the old, "raw" value of the flags. The new value has
5715 * not been saved yet.
5716 *
5717 * This is correct even for TF set by the guest, because "the
5718 * processor will not generate this exception after the instruction
5719 * that sets the TF flag".
5720 */
5721 if (unlikely(rflags & X86_EFLAGS_TF))
5722 kvm_vcpu_do_singlestep(vcpu, &r);
5723 return r == EMULATE_DONE;
5724 }
5725 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5726
5727 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5728 {
5729 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5730 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5731 struct kvm_run *kvm_run = vcpu->run;
5732 unsigned long eip = kvm_get_linear_rip(vcpu);
5733 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5734 vcpu->arch.guest_debug_dr7,
5735 vcpu->arch.eff_db);
5736
5737 if (dr6 != 0) {
5738 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5739 kvm_run->debug.arch.pc = eip;
5740 kvm_run->debug.arch.exception = DB_VECTOR;
5741 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5742 *r = EMULATE_USER_EXIT;
5743 return true;
5744 }
5745 }
5746
5747 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5748 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5749 unsigned long eip = kvm_get_linear_rip(vcpu);
5750 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5751 vcpu->arch.dr7,
5752 vcpu->arch.db);
5753
5754 if (dr6 != 0) {
5755 vcpu->arch.dr6 &= ~15;
5756 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5757 kvm_queue_exception(vcpu, DB_VECTOR);
5758 *r = EMULATE_DONE;
5759 return true;
5760 }
5761 }
5762
5763 return false;
5764 }
5765
5766 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5767 unsigned long cr2,
5768 int emulation_type,
5769 void *insn,
5770 int insn_len)
5771 {
5772 int r;
5773 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5774 bool writeback = true;
5775 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5776
5777 vcpu->arch.l1tf_flush_l1d = true;
5778
5779 /*
5780 * Clear write_fault_to_shadow_pgtable here to ensure it is
5781 * never reused.
5782 */
5783 vcpu->arch.write_fault_to_shadow_pgtable = false;
5784 kvm_clear_exception_queue(vcpu);
5785
5786 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5787 init_emulate_ctxt(vcpu);
5788
5789 /*
5790 * We will reenter on the same instruction since
5791 * we do not set complete_userspace_io. This does not
5792 * handle watchpoints yet, those would be handled in
5793 * the emulate_ops.
5794 */
5795 if (!(emulation_type & EMULTYPE_SKIP) &&
5796 kvm_vcpu_check_breakpoint(vcpu, &r))
5797 return r;
5798
5799 ctxt->interruptibility = 0;
5800 ctxt->have_exception = false;
5801 ctxt->exception.vector = -1;
5802 ctxt->perm_ok = false;
5803
5804 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5805
5806 r = x86_decode_insn(ctxt, insn, insn_len);
5807
5808 trace_kvm_emulate_insn_start(vcpu);
5809 ++vcpu->stat.insn_emulation;
5810 if (r != EMULATION_OK) {
5811 if (emulation_type & EMULTYPE_TRAP_UD)
5812 return EMULATE_FAIL;
5813 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5814 emulation_type))
5815 return EMULATE_DONE;
5816 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5817 return EMULATE_DONE;
5818 if (emulation_type & EMULTYPE_SKIP)
5819 return EMULATE_FAIL;
5820 return handle_emulation_failure(vcpu);
5821 }
5822 }
5823
5824 if (emulation_type & EMULTYPE_SKIP) {
5825 kvm_rip_write(vcpu, ctxt->_eip);
5826 if (ctxt->eflags & X86_EFLAGS_RF)
5827 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5828 return EMULATE_DONE;
5829 }
5830
5831 if (retry_instruction(ctxt, cr2, emulation_type))
5832 return EMULATE_DONE;
5833
5834 /* this is needed for vmware backdoor interface to work since it
5835 changes registers values during IO operation */
5836 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5837 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5838 emulator_invalidate_register_cache(ctxt);
5839 }
5840
5841 restart:
5842 /* Save the faulting GPA (cr2) in the address field */
5843 ctxt->exception.address = cr2;
5844
5845 r = x86_emulate_insn(ctxt);
5846
5847 if (r == EMULATION_INTERCEPTED)
5848 return EMULATE_DONE;
5849
5850 if (r == EMULATION_FAILED) {
5851 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5852 emulation_type))
5853 return EMULATE_DONE;
5854
5855 return handle_emulation_failure(vcpu);
5856 }
5857
5858 if (ctxt->have_exception) {
5859 r = EMULATE_DONE;
5860 if (inject_emulated_exception(vcpu))
5861 return r;
5862 } else if (vcpu->arch.pio.count) {
5863 if (!vcpu->arch.pio.in) {
5864 /* FIXME: return into emulator if single-stepping. */
5865 vcpu->arch.pio.count = 0;
5866 } else {
5867 writeback = false;
5868 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5869 }
5870 r = EMULATE_USER_EXIT;
5871 } else if (vcpu->mmio_needed) {
5872 if (!vcpu->mmio_is_write)
5873 writeback = false;
5874 r = EMULATE_USER_EXIT;
5875 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5876 } else if (r == EMULATION_RESTART)
5877 goto restart;
5878 else
5879 r = EMULATE_DONE;
5880
5881 if (writeback) {
5882 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5883 toggle_interruptibility(vcpu, ctxt->interruptibility);
5884 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5885 kvm_rip_write(vcpu, ctxt->eip);
5886 if (r == EMULATE_DONE &&
5887 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5888 kvm_vcpu_do_singlestep(vcpu, &r);
5889 if (!ctxt->have_exception ||
5890 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5891 __kvm_set_rflags(vcpu, ctxt->eflags);
5892
5893 /*
5894 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5895 * do nothing, and it will be requested again as soon as
5896 * the shadow expires. But we still need to check here,
5897 * because POPF has no interrupt shadow.
5898 */
5899 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5900 kvm_make_request(KVM_REQ_EVENT, vcpu);
5901 } else
5902 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5903
5904 return r;
5905 }
5906 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5907
5908 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5909 {
5910 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5911 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5912 size, port, &val, 1);
5913 /* do not return to emulator after return from userspace */
5914 vcpu->arch.pio.count = 0;
5915 return ret;
5916 }
5917 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5918
5919 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5920 {
5921 unsigned long val;
5922
5923 /* We should only ever be called with arch.pio.count equal to 1 */
5924 BUG_ON(vcpu->arch.pio.count != 1);
5925
5926 /* For size less than 4 we merge, else we zero extend */
5927 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5928 : 0;
5929
5930 /*
5931 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5932 * the copy and tracing
5933 */
5934 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5935 vcpu->arch.pio.port, &val, 1);
5936 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5937
5938 return 1;
5939 }
5940
5941 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5942 {
5943 unsigned long val;
5944 int ret;
5945
5946 /* For size less than 4 we merge, else we zero extend */
5947 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5948
5949 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5950 &val, 1);
5951 if (ret) {
5952 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5953 return ret;
5954 }
5955
5956 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5957
5958 return 0;
5959 }
5960 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5961
5962 static int kvmclock_cpu_down_prep(unsigned int cpu)
5963 {
5964 __this_cpu_write(cpu_tsc_khz, 0);
5965 return 0;
5966 }
5967
5968 static void tsc_khz_changed(void *data)
5969 {
5970 struct cpufreq_freqs *freq = data;
5971 unsigned long khz = 0;
5972
5973 if (data)
5974 khz = freq->new;
5975 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5976 khz = cpufreq_quick_get(raw_smp_processor_id());
5977 if (!khz)
5978 khz = tsc_khz;
5979 __this_cpu_write(cpu_tsc_khz, khz);
5980 }
5981
5982 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5983 void *data)
5984 {
5985 struct cpufreq_freqs *freq = data;
5986 struct kvm *kvm;
5987 struct kvm_vcpu *vcpu;
5988 int i, send_ipi = 0;
5989
5990 /*
5991 * We allow guests to temporarily run on slowing clocks,
5992 * provided we notify them after, or to run on accelerating
5993 * clocks, provided we notify them before. Thus time never
5994 * goes backwards.
5995 *
5996 * However, we have a problem. We can't atomically update
5997 * the frequency of a given CPU from this function; it is
5998 * merely a notifier, which can be called from any CPU.
5999 * Changing the TSC frequency at arbitrary points in time
6000 * requires a recomputation of local variables related to
6001 * the TSC for each VCPU. We must flag these local variables
6002 * to be updated and be sure the update takes place with the
6003 * new frequency before any guests proceed.
6004 *
6005 * Unfortunately, the combination of hotplug CPU and frequency
6006 * change creates an intractable locking scenario; the order
6007 * of when these callouts happen is undefined with respect to
6008 * CPU hotplug, and they can race with each other. As such,
6009 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6010 * undefined; you can actually have a CPU frequency change take
6011 * place in between the computation of X and the setting of the
6012 * variable. To protect against this problem, all updates of
6013 * the per_cpu tsc_khz variable are done in an interrupt
6014 * protected IPI, and all callers wishing to update the value
6015 * must wait for a synchronous IPI to complete (which is trivial
6016 * if the caller is on the CPU already). This establishes the
6017 * necessary total order on variable updates.
6018 *
6019 * Note that because a guest time update may take place
6020 * anytime after the setting of the VCPU's request bit, the
6021 * correct TSC value must be set before the request. However,
6022 * to ensure the update actually makes it to any guest which
6023 * starts running in hardware virtualization between the set
6024 * and the acquisition of the spinlock, we must also ping the
6025 * CPU after setting the request bit.
6026 *
6027 */
6028
6029 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6030 return 0;
6031 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6032 return 0;
6033
6034 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6035
6036 spin_lock(&kvm_lock);
6037 list_for_each_entry(kvm, &vm_list, vm_list) {
6038 kvm_for_each_vcpu(i, vcpu, kvm) {
6039 if (vcpu->cpu != freq->cpu)
6040 continue;
6041 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6042 if (vcpu->cpu != smp_processor_id())
6043 send_ipi = 1;
6044 }
6045 }
6046 spin_unlock(&kvm_lock);
6047
6048 if (freq->old < freq->new && send_ipi) {
6049 /*
6050 * We upscale the frequency. Must make the guest
6051 * doesn't see old kvmclock values while running with
6052 * the new frequency, otherwise we risk the guest sees
6053 * time go backwards.
6054 *
6055 * In case we update the frequency for another cpu
6056 * (which might be in guest context) send an interrupt
6057 * to kick the cpu out of guest context. Next time
6058 * guest context is entered kvmclock will be updated,
6059 * so the guest will not see stale values.
6060 */
6061 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6062 }
6063 return 0;
6064 }
6065
6066 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6067 .notifier_call = kvmclock_cpufreq_notifier
6068 };
6069
6070 static int kvmclock_cpu_online(unsigned int cpu)
6071 {
6072 tsc_khz_changed(NULL);
6073 return 0;
6074 }
6075
6076 static void kvm_timer_init(void)
6077 {
6078 max_tsc_khz = tsc_khz;
6079
6080 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6081 #ifdef CONFIG_CPU_FREQ
6082 struct cpufreq_policy policy;
6083 int cpu;
6084
6085 memset(&policy, 0, sizeof(policy));
6086 cpu = get_cpu();
6087 cpufreq_get_policy(&policy, cpu);
6088 if (policy.cpuinfo.max_freq)
6089 max_tsc_khz = policy.cpuinfo.max_freq;
6090 put_cpu();
6091 #endif
6092 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6093 CPUFREQ_TRANSITION_NOTIFIER);
6094 }
6095 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6096
6097 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6098 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6099 }
6100
6101 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6102
6103 int kvm_is_in_guest(void)
6104 {
6105 return __this_cpu_read(current_vcpu) != NULL;
6106 }
6107
6108 static int kvm_is_user_mode(void)
6109 {
6110 int user_mode = 3;
6111
6112 if (__this_cpu_read(current_vcpu))
6113 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6114
6115 return user_mode != 0;
6116 }
6117
6118 static unsigned long kvm_get_guest_ip(void)
6119 {
6120 unsigned long ip = 0;
6121
6122 if (__this_cpu_read(current_vcpu))
6123 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6124
6125 return ip;
6126 }
6127
6128 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6129 .is_in_guest = kvm_is_in_guest,
6130 .is_user_mode = kvm_is_user_mode,
6131 .get_guest_ip = kvm_get_guest_ip,
6132 };
6133
6134 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6135 {
6136 __this_cpu_write(current_vcpu, vcpu);
6137 }
6138 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6139
6140 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6141 {
6142 __this_cpu_write(current_vcpu, NULL);
6143 }
6144 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6145
6146 static void kvm_set_mmio_spte_mask(void)
6147 {
6148 u64 mask;
6149 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6150
6151 /*
6152 * Set the reserved bits and the present bit of an paging-structure
6153 * entry to generate page fault with PFER.RSV = 1.
6154 */
6155 /* Mask the reserved physical address bits. */
6156 mask = rsvd_bits(maxphyaddr, 51);
6157
6158 /* Set the present bit. */
6159 mask |= 1ull;
6160
6161 #ifdef CONFIG_X86_64
6162 /*
6163 * If reserved bit is not supported, clear the present bit to disable
6164 * mmio page fault.
6165 */
6166 if (maxphyaddr == 52)
6167 mask &= ~1ull;
6168 #endif
6169
6170 kvm_mmu_set_mmio_spte_mask(mask, mask);
6171 }
6172
6173 #ifdef CONFIG_X86_64
6174 static void pvclock_gtod_update_fn(struct work_struct *work)
6175 {
6176 struct kvm *kvm;
6177
6178 struct kvm_vcpu *vcpu;
6179 int i;
6180
6181 spin_lock(&kvm_lock);
6182 list_for_each_entry(kvm, &vm_list, vm_list)
6183 kvm_for_each_vcpu(i, vcpu, kvm)
6184 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6185 atomic_set(&kvm_guest_has_master_clock, 0);
6186 spin_unlock(&kvm_lock);
6187 }
6188
6189 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6190
6191 /*
6192 * Notification about pvclock gtod data update.
6193 */
6194 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6195 void *priv)
6196 {
6197 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6198 struct timekeeper *tk = priv;
6199
6200 update_pvclock_gtod(tk);
6201
6202 /* disable master clock if host does not trust, or does not
6203 * use, TSC clocksource
6204 */
6205 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6206 atomic_read(&kvm_guest_has_master_clock) != 0)
6207 queue_work(system_long_wq, &pvclock_gtod_work);
6208
6209 return 0;
6210 }
6211
6212 static struct notifier_block pvclock_gtod_notifier = {
6213 .notifier_call = pvclock_gtod_notify,
6214 };
6215 #endif
6216
6217 int kvm_arch_init(void *opaque)
6218 {
6219 int r;
6220 struct kvm_x86_ops *ops = opaque;
6221
6222 if (kvm_x86_ops) {
6223 printk(KERN_ERR "kvm: already loaded the other module\n");
6224 r = -EEXIST;
6225 goto out;
6226 }
6227
6228 if (!ops->cpu_has_kvm_support()) {
6229 printk(KERN_ERR "kvm: no hardware support\n");
6230 r = -EOPNOTSUPP;
6231 goto out;
6232 }
6233 if (ops->disabled_by_bios()) {
6234 printk(KERN_WARNING "kvm: disabled by bios\n");
6235 r = -EOPNOTSUPP;
6236 goto out;
6237 }
6238
6239 r = -ENOMEM;
6240 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6241 if (!shared_msrs) {
6242 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6243 goto out;
6244 }
6245
6246 r = kvm_mmu_module_init();
6247 if (r)
6248 goto out_free_percpu;
6249
6250 kvm_set_mmio_spte_mask();
6251
6252 kvm_x86_ops = ops;
6253
6254 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6255 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6256 PT_PRESENT_MASK, 0, sme_me_mask);
6257 kvm_timer_init();
6258
6259 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6260
6261 if (boot_cpu_has(X86_FEATURE_XSAVE))
6262 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6263
6264 kvm_lapic_init();
6265 #ifdef CONFIG_X86_64
6266 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6267 #endif
6268
6269 return 0;
6270
6271 out_free_percpu:
6272 free_percpu(shared_msrs);
6273 out:
6274 return r;
6275 }
6276
6277 void kvm_arch_exit(void)
6278 {
6279 kvm_lapic_exit();
6280 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6281
6282 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6283 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6284 CPUFREQ_TRANSITION_NOTIFIER);
6285 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6286 #ifdef CONFIG_X86_64
6287 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6288 #endif
6289 kvm_x86_ops = NULL;
6290 kvm_mmu_module_exit();
6291 free_percpu(shared_msrs);
6292 }
6293
6294 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6295 {
6296 ++vcpu->stat.halt_exits;
6297 if (lapic_in_kernel(vcpu)) {
6298 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6299 return 1;
6300 } else {
6301 vcpu->run->exit_reason = KVM_EXIT_HLT;
6302 return 0;
6303 }
6304 }
6305 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6306
6307 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6308 {
6309 int ret = kvm_skip_emulated_instruction(vcpu);
6310 /*
6311 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6312 * KVM_EXIT_DEBUG here.
6313 */
6314 return kvm_vcpu_halt(vcpu) && ret;
6315 }
6316 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6317
6318 #ifdef CONFIG_X86_64
6319 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6320 unsigned long clock_type)
6321 {
6322 struct kvm_clock_pairing clock_pairing;
6323 struct timespec ts;
6324 u64 cycle;
6325 int ret;
6326
6327 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6328 return -KVM_EOPNOTSUPP;
6329
6330 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6331 return -KVM_EOPNOTSUPP;
6332
6333 clock_pairing.sec = ts.tv_sec;
6334 clock_pairing.nsec = ts.tv_nsec;
6335 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6336 clock_pairing.flags = 0;
6337
6338 ret = 0;
6339 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6340 sizeof(struct kvm_clock_pairing)))
6341 ret = -KVM_EFAULT;
6342
6343 return ret;
6344 }
6345 #endif
6346
6347 /*
6348 * kvm_pv_kick_cpu_op: Kick a vcpu.
6349 *
6350 * @apicid - apicid of vcpu to be kicked.
6351 */
6352 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6353 {
6354 struct kvm_lapic_irq lapic_irq;
6355
6356 lapic_irq.shorthand = 0;
6357 lapic_irq.dest_mode = 0;
6358 lapic_irq.level = 0;
6359 lapic_irq.dest_id = apicid;
6360 lapic_irq.msi_redir_hint = false;
6361
6362 lapic_irq.delivery_mode = APIC_DM_REMRD;
6363 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6364 }
6365
6366 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6367 {
6368 vcpu->arch.apicv_active = false;
6369 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6370 }
6371
6372 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6373 {
6374 unsigned long nr, a0, a1, a2, a3, ret;
6375 int op_64_bit, r;
6376
6377 r = kvm_skip_emulated_instruction(vcpu);
6378
6379 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6380 return kvm_hv_hypercall(vcpu);
6381
6382 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6383 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6384 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6385 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6386 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6387
6388 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6389
6390 op_64_bit = is_64_bit_mode(vcpu);
6391 if (!op_64_bit) {
6392 nr &= 0xFFFFFFFF;
6393 a0 &= 0xFFFFFFFF;
6394 a1 &= 0xFFFFFFFF;
6395 a2 &= 0xFFFFFFFF;
6396 a3 &= 0xFFFFFFFF;
6397 }
6398
6399 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6400 ret = -KVM_EPERM;
6401 goto out;
6402 }
6403
6404 switch (nr) {
6405 case KVM_HC_VAPIC_POLL_IRQ:
6406 ret = 0;
6407 break;
6408 case KVM_HC_KICK_CPU:
6409 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6410 ret = 0;
6411 break;
6412 #ifdef CONFIG_X86_64
6413 case KVM_HC_CLOCK_PAIRING:
6414 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6415 break;
6416 #endif
6417 default:
6418 ret = -KVM_ENOSYS;
6419 break;
6420 }
6421 out:
6422 if (!op_64_bit)
6423 ret = (u32)ret;
6424 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6425 ++vcpu->stat.hypercalls;
6426 return r;
6427 }
6428 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6429
6430 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6431 {
6432 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6433 char instruction[3];
6434 unsigned long rip = kvm_rip_read(vcpu);
6435
6436 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6437
6438 return emulator_write_emulated(ctxt, rip, instruction, 3,
6439 &ctxt->exception);
6440 }
6441
6442 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6443 {
6444 return vcpu->run->request_interrupt_window &&
6445 likely(!pic_in_kernel(vcpu->kvm));
6446 }
6447
6448 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6449 {
6450 struct kvm_run *kvm_run = vcpu->run;
6451
6452 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6453 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6454 kvm_run->cr8 = kvm_get_cr8(vcpu);
6455 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6456 kvm_run->ready_for_interrupt_injection =
6457 pic_in_kernel(vcpu->kvm) ||
6458 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6459 }
6460
6461 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6462 {
6463 int max_irr, tpr;
6464
6465 if (!kvm_x86_ops->update_cr8_intercept)
6466 return;
6467
6468 if (!lapic_in_kernel(vcpu))
6469 return;
6470
6471 if (vcpu->arch.apicv_active)
6472 return;
6473
6474 if (!vcpu->arch.apic->vapic_addr)
6475 max_irr = kvm_lapic_find_highest_irr(vcpu);
6476 else
6477 max_irr = -1;
6478
6479 if (max_irr != -1)
6480 max_irr >>= 4;
6481
6482 tpr = kvm_lapic_get_cr8(vcpu);
6483
6484 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6485 }
6486
6487 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6488 {
6489 int r;
6490
6491 /* try to reinject previous events if any */
6492 if (vcpu->arch.exception.injected) {
6493 kvm_x86_ops->queue_exception(vcpu);
6494 return 0;
6495 }
6496
6497 /*
6498 * Exceptions must be injected immediately, or the exception
6499 * frame will have the address of the NMI or interrupt handler.
6500 */
6501 if (!vcpu->arch.exception.pending) {
6502 if (vcpu->arch.nmi_injected) {
6503 kvm_x86_ops->set_nmi(vcpu);
6504 return 0;
6505 }
6506
6507 if (vcpu->arch.interrupt.pending) {
6508 kvm_x86_ops->set_irq(vcpu);
6509 return 0;
6510 }
6511 }
6512
6513 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6514 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6515 if (r != 0)
6516 return r;
6517 }
6518
6519 /* try to inject new event if pending */
6520 if (vcpu->arch.exception.pending) {
6521 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6522 vcpu->arch.exception.has_error_code,
6523 vcpu->arch.exception.error_code);
6524
6525 vcpu->arch.exception.pending = false;
6526 vcpu->arch.exception.injected = true;
6527
6528 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6529 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6530 X86_EFLAGS_RF);
6531
6532 if (vcpu->arch.exception.nr == DB_VECTOR &&
6533 (vcpu->arch.dr7 & DR7_GD)) {
6534 vcpu->arch.dr7 &= ~DR7_GD;
6535 kvm_update_dr7(vcpu);
6536 }
6537
6538 kvm_x86_ops->queue_exception(vcpu);
6539 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
6540 vcpu->arch.smi_pending = false;
6541 enter_smm(vcpu);
6542 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6543 --vcpu->arch.nmi_pending;
6544 vcpu->arch.nmi_injected = true;
6545 kvm_x86_ops->set_nmi(vcpu);
6546 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6547 /*
6548 * Because interrupts can be injected asynchronously, we are
6549 * calling check_nested_events again here to avoid a race condition.
6550 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6551 * proposal and current concerns. Perhaps we should be setting
6552 * KVM_REQ_EVENT only on certain events and not unconditionally?
6553 */
6554 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6555 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6556 if (r != 0)
6557 return r;
6558 }
6559 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6560 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6561 false);
6562 kvm_x86_ops->set_irq(vcpu);
6563 }
6564 }
6565
6566 return 0;
6567 }
6568
6569 static void process_nmi(struct kvm_vcpu *vcpu)
6570 {
6571 unsigned limit = 2;
6572
6573 /*
6574 * x86 is limited to one NMI running, and one NMI pending after it.
6575 * If an NMI is already in progress, limit further NMIs to just one.
6576 * Otherwise, allow two (and we'll inject the first one immediately).
6577 */
6578 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6579 limit = 1;
6580
6581 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6582 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6583 kvm_make_request(KVM_REQ_EVENT, vcpu);
6584 }
6585
6586 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6587 {
6588 u32 flags = 0;
6589 flags |= seg->g << 23;
6590 flags |= seg->db << 22;
6591 flags |= seg->l << 21;
6592 flags |= seg->avl << 20;
6593 flags |= seg->present << 15;
6594 flags |= seg->dpl << 13;
6595 flags |= seg->s << 12;
6596 flags |= seg->type << 8;
6597 return flags;
6598 }
6599
6600 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6601 {
6602 struct kvm_segment seg;
6603 int offset;
6604
6605 kvm_get_segment(vcpu, &seg, n);
6606 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6607
6608 if (n < 3)
6609 offset = 0x7f84 + n * 12;
6610 else
6611 offset = 0x7f2c + (n - 3) * 12;
6612
6613 put_smstate(u32, buf, offset + 8, seg.base);
6614 put_smstate(u32, buf, offset + 4, seg.limit);
6615 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6616 }
6617
6618 #ifdef CONFIG_X86_64
6619 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6620 {
6621 struct kvm_segment seg;
6622 int offset;
6623 u16 flags;
6624
6625 kvm_get_segment(vcpu, &seg, n);
6626 offset = 0x7e00 + n * 16;
6627
6628 flags = enter_smm_get_segment_flags(&seg) >> 8;
6629 put_smstate(u16, buf, offset, seg.selector);
6630 put_smstate(u16, buf, offset + 2, flags);
6631 put_smstate(u32, buf, offset + 4, seg.limit);
6632 put_smstate(u64, buf, offset + 8, seg.base);
6633 }
6634 #endif
6635
6636 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6637 {
6638 struct desc_ptr dt;
6639 struct kvm_segment seg;
6640 unsigned long val;
6641 int i;
6642
6643 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6644 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6645 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6646 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6647
6648 for (i = 0; i < 8; i++)
6649 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6650
6651 kvm_get_dr(vcpu, 6, &val);
6652 put_smstate(u32, buf, 0x7fcc, (u32)val);
6653 kvm_get_dr(vcpu, 7, &val);
6654 put_smstate(u32, buf, 0x7fc8, (u32)val);
6655
6656 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6657 put_smstate(u32, buf, 0x7fc4, seg.selector);
6658 put_smstate(u32, buf, 0x7f64, seg.base);
6659 put_smstate(u32, buf, 0x7f60, seg.limit);
6660 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6661
6662 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6663 put_smstate(u32, buf, 0x7fc0, seg.selector);
6664 put_smstate(u32, buf, 0x7f80, seg.base);
6665 put_smstate(u32, buf, 0x7f7c, seg.limit);
6666 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6667
6668 kvm_x86_ops->get_gdt(vcpu, &dt);
6669 put_smstate(u32, buf, 0x7f74, dt.address);
6670 put_smstate(u32, buf, 0x7f70, dt.size);
6671
6672 kvm_x86_ops->get_idt(vcpu, &dt);
6673 put_smstate(u32, buf, 0x7f58, dt.address);
6674 put_smstate(u32, buf, 0x7f54, dt.size);
6675
6676 for (i = 0; i < 6; i++)
6677 enter_smm_save_seg_32(vcpu, buf, i);
6678
6679 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6680
6681 /* revision id */
6682 put_smstate(u32, buf, 0x7efc, 0x00020000);
6683 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6684 }
6685
6686 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6687 {
6688 #ifdef CONFIG_X86_64
6689 struct desc_ptr dt;
6690 struct kvm_segment seg;
6691 unsigned long val;
6692 int i;
6693
6694 for (i = 0; i < 16; i++)
6695 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6696
6697 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6698 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6699
6700 kvm_get_dr(vcpu, 6, &val);
6701 put_smstate(u64, buf, 0x7f68, val);
6702 kvm_get_dr(vcpu, 7, &val);
6703 put_smstate(u64, buf, 0x7f60, val);
6704
6705 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6706 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6707 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6708
6709 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6710
6711 /* revision id */
6712 put_smstate(u32, buf, 0x7efc, 0x00020064);
6713
6714 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6715
6716 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6717 put_smstate(u16, buf, 0x7e90, seg.selector);
6718 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6719 put_smstate(u32, buf, 0x7e94, seg.limit);
6720 put_smstate(u64, buf, 0x7e98, seg.base);
6721
6722 kvm_x86_ops->get_idt(vcpu, &dt);
6723 put_smstate(u32, buf, 0x7e84, dt.size);
6724 put_smstate(u64, buf, 0x7e88, dt.address);
6725
6726 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6727 put_smstate(u16, buf, 0x7e70, seg.selector);
6728 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6729 put_smstate(u32, buf, 0x7e74, seg.limit);
6730 put_smstate(u64, buf, 0x7e78, seg.base);
6731
6732 kvm_x86_ops->get_gdt(vcpu, &dt);
6733 put_smstate(u32, buf, 0x7e64, dt.size);
6734 put_smstate(u64, buf, 0x7e68, dt.address);
6735
6736 for (i = 0; i < 6; i++)
6737 enter_smm_save_seg_64(vcpu, buf, i);
6738 #else
6739 WARN_ON_ONCE(1);
6740 #endif
6741 }
6742
6743 static void enter_smm(struct kvm_vcpu *vcpu)
6744 {
6745 struct kvm_segment cs, ds;
6746 struct desc_ptr dt;
6747 char buf[512];
6748 u32 cr0;
6749
6750 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6751 memset(buf, 0, 512);
6752 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6753 enter_smm_save_state_64(vcpu, buf);
6754 else
6755 enter_smm_save_state_32(vcpu, buf);
6756
6757 /*
6758 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6759 * vCPU state (e.g. leave guest mode) after we've saved the state into
6760 * the SMM state-save area.
6761 */
6762 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6763
6764 vcpu->arch.hflags |= HF_SMM_MASK;
6765 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6766
6767 if (kvm_x86_ops->get_nmi_mask(vcpu))
6768 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6769 else
6770 kvm_x86_ops->set_nmi_mask(vcpu, true);
6771
6772 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6773 kvm_rip_write(vcpu, 0x8000);
6774
6775 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6776 kvm_x86_ops->set_cr0(vcpu, cr0);
6777 vcpu->arch.cr0 = cr0;
6778
6779 kvm_x86_ops->set_cr4(vcpu, 0);
6780
6781 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6782 dt.address = dt.size = 0;
6783 kvm_x86_ops->set_idt(vcpu, &dt);
6784
6785 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6786
6787 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6788 cs.base = vcpu->arch.smbase;
6789
6790 ds.selector = 0;
6791 ds.base = 0;
6792
6793 cs.limit = ds.limit = 0xffffffff;
6794 cs.type = ds.type = 0x3;
6795 cs.dpl = ds.dpl = 0;
6796 cs.db = ds.db = 0;
6797 cs.s = ds.s = 1;
6798 cs.l = ds.l = 0;
6799 cs.g = ds.g = 1;
6800 cs.avl = ds.avl = 0;
6801 cs.present = ds.present = 1;
6802 cs.unusable = ds.unusable = 0;
6803 cs.padding = ds.padding = 0;
6804
6805 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6806 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6807 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6808 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6809 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6810 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6811
6812 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6813 kvm_x86_ops->set_efer(vcpu, 0);
6814
6815 kvm_update_cpuid(vcpu);
6816 kvm_mmu_reset_context(vcpu);
6817 }
6818
6819 static void process_smi(struct kvm_vcpu *vcpu)
6820 {
6821 vcpu->arch.smi_pending = true;
6822 kvm_make_request(KVM_REQ_EVENT, vcpu);
6823 }
6824
6825 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6826 {
6827 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6828 }
6829
6830 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6831 {
6832 u64 eoi_exit_bitmap[4];
6833
6834 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6835 return;
6836
6837 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6838
6839 if (irqchip_split(vcpu->kvm))
6840 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6841 else {
6842 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6843 kvm_x86_ops->sync_pir_to_irr(vcpu);
6844 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6845 }
6846 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6847 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6848 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6849 }
6850
6851 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6852 {
6853 ++vcpu->stat.tlb_flush;
6854 kvm_x86_ops->tlb_flush(vcpu);
6855 }
6856
6857 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6858 unsigned long start, unsigned long end)
6859 {
6860 unsigned long apic_address;
6861
6862 /*
6863 * The physical address of apic access page is stored in the VMCS.
6864 * Update it when it becomes invalid.
6865 */
6866 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6867 if (start <= apic_address && apic_address < end)
6868 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6869 }
6870
6871 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6872 {
6873 struct page *page = NULL;
6874
6875 if (!lapic_in_kernel(vcpu))
6876 return;
6877
6878 if (!kvm_x86_ops->set_apic_access_page_addr)
6879 return;
6880
6881 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6882 if (is_error_page(page))
6883 return;
6884 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6885
6886 /*
6887 * Do not pin apic access page in memory, the MMU notifier
6888 * will call us again if it is migrated or swapped out.
6889 */
6890 put_page(page);
6891 }
6892 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6893
6894 /*
6895 * Returns 1 to let vcpu_run() continue the guest execution loop without
6896 * exiting to the userspace. Otherwise, the value will be returned to the
6897 * userspace.
6898 */
6899 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6900 {
6901 int r;
6902 bool req_int_win =
6903 dm_request_for_irq_injection(vcpu) &&
6904 kvm_cpu_accept_dm_intr(vcpu);
6905
6906 bool req_immediate_exit = false;
6907
6908 if (kvm_request_pending(vcpu)) {
6909 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6910 kvm_mmu_unload(vcpu);
6911 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6912 __kvm_migrate_timers(vcpu);
6913 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6914 kvm_gen_update_masterclock(vcpu->kvm);
6915 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6916 kvm_gen_kvmclock_update(vcpu);
6917 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6918 r = kvm_guest_time_update(vcpu);
6919 if (unlikely(r))
6920 goto out;
6921 }
6922 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6923 kvm_mmu_sync_roots(vcpu);
6924 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6925 kvm_vcpu_flush_tlb(vcpu);
6926 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6927 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6928 r = 0;
6929 goto out;
6930 }
6931 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6932 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6933 vcpu->mmio_needed = 0;
6934 r = 0;
6935 goto out;
6936 }
6937 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6938 /* Page is swapped out. Do synthetic halt */
6939 vcpu->arch.apf.halted = true;
6940 r = 1;
6941 goto out;
6942 }
6943 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6944 record_steal_time(vcpu);
6945 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6946 process_smi(vcpu);
6947 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6948 process_nmi(vcpu);
6949 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6950 kvm_pmu_handle_event(vcpu);
6951 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6952 kvm_pmu_deliver_pmi(vcpu);
6953 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6954 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6955 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6956 vcpu->arch.ioapic_handled_vectors)) {
6957 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6958 vcpu->run->eoi.vector =
6959 vcpu->arch.pending_ioapic_eoi;
6960 r = 0;
6961 goto out;
6962 }
6963 }
6964 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6965 vcpu_scan_ioapic(vcpu);
6966 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6967 kvm_vcpu_reload_apic_access_page(vcpu);
6968 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6969 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6970 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6971 r = 0;
6972 goto out;
6973 }
6974 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6975 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6976 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6977 r = 0;
6978 goto out;
6979 }
6980 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6981 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6982 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6983 r = 0;
6984 goto out;
6985 }
6986
6987 /*
6988 * KVM_REQ_HV_STIMER has to be processed after
6989 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6990 * depend on the guest clock being up-to-date
6991 */
6992 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6993 kvm_hv_process_stimers(vcpu);
6994 }
6995
6996 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6997 ++vcpu->stat.req_event;
6998 kvm_apic_accept_events(vcpu);
6999 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7000 r = 1;
7001 goto out;
7002 }
7003
7004 if (inject_pending_event(vcpu, req_int_win) != 0)
7005 req_immediate_exit = true;
7006 else {
7007 /* Enable SMI/NMI/IRQ window open exits if needed.
7008 *
7009 * SMIs have three cases:
7010 * 1) They can be nested, and then there is nothing to
7011 * do here because RSM will cause a vmexit anyway.
7012 * 2) There is an ISA-specific reason why SMI cannot be
7013 * injected, and the moment when this changes can be
7014 * intercepted.
7015 * 3) Or the SMI can be pending because
7016 * inject_pending_event has completed the injection
7017 * of an IRQ or NMI from the previous vmexit, and
7018 * then we request an immediate exit to inject the
7019 * SMI.
7020 */
7021 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7022 if (!kvm_x86_ops->enable_smi_window(vcpu))
7023 req_immediate_exit = true;
7024 if (vcpu->arch.nmi_pending)
7025 kvm_x86_ops->enable_nmi_window(vcpu);
7026 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7027 kvm_x86_ops->enable_irq_window(vcpu);
7028 WARN_ON(vcpu->arch.exception.pending);
7029 }
7030
7031 if (kvm_lapic_enabled(vcpu)) {
7032 update_cr8_intercept(vcpu);
7033 kvm_lapic_sync_to_vapic(vcpu);
7034 }
7035 }
7036
7037 r = kvm_mmu_reload(vcpu);
7038 if (unlikely(r)) {
7039 goto cancel_injection;
7040 }
7041
7042 preempt_disable();
7043
7044 kvm_x86_ops->prepare_guest_switch(vcpu);
7045
7046 /*
7047 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7048 * IPI are then delayed after guest entry, which ensures that they
7049 * result in virtual interrupt delivery.
7050 */
7051 local_irq_disable();
7052 vcpu->mode = IN_GUEST_MODE;
7053
7054 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7055
7056 /*
7057 * 1) We should set ->mode before checking ->requests. Please see
7058 * the comment in kvm_vcpu_exiting_guest_mode().
7059 *
7060 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7061 * pairs with the memory barrier implicit in pi_test_and_set_on
7062 * (see vmx_deliver_posted_interrupt).
7063 *
7064 * 3) This also orders the write to mode from any reads to the page
7065 * tables done while the VCPU is running. Please see the comment
7066 * in kvm_flush_remote_tlbs.
7067 */
7068 smp_mb__after_srcu_read_unlock();
7069
7070 /*
7071 * This handles the case where a posted interrupt was
7072 * notified with kvm_vcpu_kick.
7073 */
7074 if (kvm_lapic_enabled(vcpu)) {
7075 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7076 kvm_x86_ops->sync_pir_to_irr(vcpu);
7077 }
7078
7079 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7080 || need_resched() || signal_pending(current)) {
7081 vcpu->mode = OUTSIDE_GUEST_MODE;
7082 smp_wmb();
7083 local_irq_enable();
7084 preempt_enable();
7085 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7086 r = 1;
7087 goto cancel_injection;
7088 }
7089
7090 kvm_load_guest_xcr0(vcpu);
7091
7092 if (req_immediate_exit) {
7093 kvm_make_request(KVM_REQ_EVENT, vcpu);
7094 smp_send_reschedule(vcpu->cpu);
7095 }
7096
7097 trace_kvm_entry(vcpu->vcpu_id);
7098 wait_lapic_expire(vcpu);
7099 guest_enter_irqoff();
7100
7101 if (unlikely(vcpu->arch.switch_db_regs)) {
7102 set_debugreg(0, 7);
7103 set_debugreg(vcpu->arch.eff_db[0], 0);
7104 set_debugreg(vcpu->arch.eff_db[1], 1);
7105 set_debugreg(vcpu->arch.eff_db[2], 2);
7106 set_debugreg(vcpu->arch.eff_db[3], 3);
7107 set_debugreg(vcpu->arch.dr6, 6);
7108 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7109 }
7110
7111 kvm_x86_ops->run(vcpu);
7112
7113 /*
7114 * Do this here before restoring debug registers on the host. And
7115 * since we do this before handling the vmexit, a DR access vmexit
7116 * can (a) read the correct value of the debug registers, (b) set
7117 * KVM_DEBUGREG_WONT_EXIT again.
7118 */
7119 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7120 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7121 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7122 kvm_update_dr0123(vcpu);
7123 kvm_update_dr6(vcpu);
7124 kvm_update_dr7(vcpu);
7125 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7126 }
7127
7128 /*
7129 * If the guest has used debug registers, at least dr7
7130 * will be disabled while returning to the host.
7131 * If we don't have active breakpoints in the host, we don't
7132 * care about the messed up debug address registers. But if
7133 * we have some of them active, restore the old state.
7134 */
7135 if (hw_breakpoint_active())
7136 hw_breakpoint_restore();
7137
7138 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7139
7140 vcpu->mode = OUTSIDE_GUEST_MODE;
7141 smp_wmb();
7142
7143 kvm_put_guest_xcr0(vcpu);
7144
7145 kvm_x86_ops->handle_external_intr(vcpu);
7146
7147 ++vcpu->stat.exits;
7148
7149 guest_exit_irqoff();
7150
7151 local_irq_enable();
7152 preempt_enable();
7153
7154 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7155
7156 /*
7157 * Profile KVM exit RIPs:
7158 */
7159 if (unlikely(prof_on == KVM_PROFILING)) {
7160 unsigned long rip = kvm_rip_read(vcpu);
7161 profile_hit(KVM_PROFILING, (void *)rip);
7162 }
7163
7164 if (unlikely(vcpu->arch.tsc_always_catchup))
7165 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7166
7167 if (vcpu->arch.apic_attention)
7168 kvm_lapic_sync_from_vapic(vcpu);
7169
7170 vcpu->arch.gpa_available = false;
7171 r = kvm_x86_ops->handle_exit(vcpu);
7172 return r;
7173
7174 cancel_injection:
7175 kvm_x86_ops->cancel_injection(vcpu);
7176 if (unlikely(vcpu->arch.apic_attention))
7177 kvm_lapic_sync_from_vapic(vcpu);
7178 out:
7179 return r;
7180 }
7181
7182 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7183 {
7184 if (!kvm_arch_vcpu_runnable(vcpu) &&
7185 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7186 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7187 kvm_vcpu_block(vcpu);
7188 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7189
7190 if (kvm_x86_ops->post_block)
7191 kvm_x86_ops->post_block(vcpu);
7192
7193 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7194 return 1;
7195 }
7196
7197 kvm_apic_accept_events(vcpu);
7198 switch(vcpu->arch.mp_state) {
7199 case KVM_MP_STATE_HALTED:
7200 vcpu->arch.pv.pv_unhalted = false;
7201 vcpu->arch.mp_state =
7202 KVM_MP_STATE_RUNNABLE;
7203 case KVM_MP_STATE_RUNNABLE:
7204 vcpu->arch.apf.halted = false;
7205 break;
7206 case KVM_MP_STATE_INIT_RECEIVED:
7207 break;
7208 default:
7209 return -EINTR;
7210 break;
7211 }
7212 return 1;
7213 }
7214
7215 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7216 {
7217 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7218 kvm_x86_ops->check_nested_events(vcpu, false);
7219
7220 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7221 !vcpu->arch.apf.halted);
7222 }
7223
7224 static int vcpu_run(struct kvm_vcpu *vcpu)
7225 {
7226 int r;
7227 struct kvm *kvm = vcpu->kvm;
7228
7229 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7230 vcpu->arch.l1tf_flush_l1d = true;
7231
7232 for (;;) {
7233 if (kvm_vcpu_running(vcpu)) {
7234 r = vcpu_enter_guest(vcpu);
7235 } else {
7236 r = vcpu_block(kvm, vcpu);
7237 }
7238
7239 if (r <= 0)
7240 break;
7241
7242 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7243 if (kvm_cpu_has_pending_timer(vcpu))
7244 kvm_inject_pending_timer_irqs(vcpu);
7245
7246 if (dm_request_for_irq_injection(vcpu) &&
7247 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7248 r = 0;
7249 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7250 ++vcpu->stat.request_irq_exits;
7251 break;
7252 }
7253
7254 kvm_check_async_pf_completion(vcpu);
7255
7256 if (signal_pending(current)) {
7257 r = -EINTR;
7258 vcpu->run->exit_reason = KVM_EXIT_INTR;
7259 ++vcpu->stat.signal_exits;
7260 break;
7261 }
7262 if (need_resched()) {
7263 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7264 cond_resched();
7265 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7266 }
7267 }
7268
7269 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7270
7271 return r;
7272 }
7273
7274 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7275 {
7276 int r;
7277 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7278 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7279 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7280 if (r != EMULATE_DONE)
7281 return 0;
7282 return 1;
7283 }
7284
7285 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7286 {
7287 BUG_ON(!vcpu->arch.pio.count);
7288
7289 return complete_emulated_io(vcpu);
7290 }
7291
7292 /*
7293 * Implements the following, as a state machine:
7294 *
7295 * read:
7296 * for each fragment
7297 * for each mmio piece in the fragment
7298 * write gpa, len
7299 * exit
7300 * copy data
7301 * execute insn
7302 *
7303 * write:
7304 * for each fragment
7305 * for each mmio piece in the fragment
7306 * write gpa, len
7307 * copy data
7308 * exit
7309 */
7310 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7311 {
7312 struct kvm_run *run = vcpu->run;
7313 struct kvm_mmio_fragment *frag;
7314 unsigned len;
7315
7316 BUG_ON(!vcpu->mmio_needed);
7317
7318 /* Complete previous fragment */
7319 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7320 len = min(8u, frag->len);
7321 if (!vcpu->mmio_is_write)
7322 memcpy(frag->data, run->mmio.data, len);
7323
7324 if (frag->len <= 8) {
7325 /* Switch to the next fragment. */
7326 frag++;
7327 vcpu->mmio_cur_fragment++;
7328 } else {
7329 /* Go forward to the next mmio piece. */
7330 frag->data += len;
7331 frag->gpa += len;
7332 frag->len -= len;
7333 }
7334
7335 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7336 vcpu->mmio_needed = 0;
7337
7338 /* FIXME: return into emulator if single-stepping. */
7339 if (vcpu->mmio_is_write)
7340 return 1;
7341 vcpu->mmio_read_completed = 1;
7342 return complete_emulated_io(vcpu);
7343 }
7344
7345 run->exit_reason = KVM_EXIT_MMIO;
7346 run->mmio.phys_addr = frag->gpa;
7347 if (vcpu->mmio_is_write)
7348 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7349 run->mmio.len = min(8u, frag->len);
7350 run->mmio.is_write = vcpu->mmio_is_write;
7351 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7352 return 0;
7353 }
7354
7355
7356 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7357 {
7358 int r;
7359
7360 kvm_sigset_activate(vcpu);
7361
7362 kvm_load_guest_fpu(vcpu);
7363
7364 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7365 if (kvm_run->immediate_exit) {
7366 r = -EINTR;
7367 goto out;
7368 }
7369 kvm_vcpu_block(vcpu);
7370 kvm_apic_accept_events(vcpu);
7371 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7372 r = -EAGAIN;
7373 if (signal_pending(current)) {
7374 r = -EINTR;
7375 vcpu->run->exit_reason = KVM_EXIT_INTR;
7376 ++vcpu->stat.signal_exits;
7377 }
7378 goto out;
7379 }
7380
7381 /* re-sync apic's tpr */
7382 if (!lapic_in_kernel(vcpu)) {
7383 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7384 r = -EINVAL;
7385 goto out;
7386 }
7387 }
7388
7389 if (unlikely(vcpu->arch.complete_userspace_io)) {
7390 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7391 vcpu->arch.complete_userspace_io = NULL;
7392 r = cui(vcpu);
7393 if (r <= 0)
7394 goto out;
7395 } else
7396 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7397
7398 if (kvm_run->immediate_exit)
7399 r = -EINTR;
7400 else
7401 r = vcpu_run(vcpu);
7402
7403 out:
7404 kvm_put_guest_fpu(vcpu);
7405 post_kvm_run_save(vcpu);
7406 kvm_sigset_deactivate(vcpu);
7407
7408 return r;
7409 }
7410
7411 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7412 {
7413 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7414 /*
7415 * We are here if userspace calls get_regs() in the middle of
7416 * instruction emulation. Registers state needs to be copied
7417 * back from emulation context to vcpu. Userspace shouldn't do
7418 * that usually, but some bad designed PV devices (vmware
7419 * backdoor interface) need this to work
7420 */
7421 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7422 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7423 }
7424 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7425 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7426 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7427 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7428 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7429 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7430 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7431 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7432 #ifdef CONFIG_X86_64
7433 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7434 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7435 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7436 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7437 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7438 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7439 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7440 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7441 #endif
7442
7443 regs->rip = kvm_rip_read(vcpu);
7444 regs->rflags = kvm_get_rflags(vcpu);
7445
7446 return 0;
7447 }
7448
7449 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7450 {
7451 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7452 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7453
7454 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7455 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7456 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7457 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7458 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7459 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7460 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7461 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7462 #ifdef CONFIG_X86_64
7463 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7464 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7465 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7466 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7467 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7468 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7469 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7470 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7471 #endif
7472
7473 kvm_rip_write(vcpu, regs->rip);
7474 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7475
7476 vcpu->arch.exception.pending = false;
7477
7478 kvm_make_request(KVM_REQ_EVENT, vcpu);
7479
7480 return 0;
7481 }
7482
7483 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7484 {
7485 struct kvm_segment cs;
7486
7487 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7488 *db = cs.db;
7489 *l = cs.l;
7490 }
7491 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7492
7493 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7494 struct kvm_sregs *sregs)
7495 {
7496 struct desc_ptr dt;
7497
7498 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7499 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7500 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7501 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7502 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7503 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7504
7505 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7506 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7507
7508 kvm_x86_ops->get_idt(vcpu, &dt);
7509 sregs->idt.limit = dt.size;
7510 sregs->idt.base = dt.address;
7511 kvm_x86_ops->get_gdt(vcpu, &dt);
7512 sregs->gdt.limit = dt.size;
7513 sregs->gdt.base = dt.address;
7514
7515 sregs->cr0 = kvm_read_cr0(vcpu);
7516 sregs->cr2 = vcpu->arch.cr2;
7517 sregs->cr3 = kvm_read_cr3(vcpu);
7518 sregs->cr4 = kvm_read_cr4(vcpu);
7519 sregs->cr8 = kvm_get_cr8(vcpu);
7520 sregs->efer = vcpu->arch.efer;
7521 sregs->apic_base = kvm_get_apic_base(vcpu);
7522
7523 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7524
7525 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7526 set_bit(vcpu->arch.interrupt.nr,
7527 (unsigned long *)sregs->interrupt_bitmap);
7528
7529 return 0;
7530 }
7531
7532 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7533 struct kvm_mp_state *mp_state)
7534 {
7535 kvm_apic_accept_events(vcpu);
7536 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7537 vcpu->arch.pv.pv_unhalted)
7538 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7539 else
7540 mp_state->mp_state = vcpu->arch.mp_state;
7541
7542 return 0;
7543 }
7544
7545 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7546 struct kvm_mp_state *mp_state)
7547 {
7548 if (!lapic_in_kernel(vcpu) &&
7549 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7550 return -EINVAL;
7551
7552 /* INITs are latched while in SMM */
7553 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7554 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7555 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7556 return -EINVAL;
7557
7558 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7559 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7560 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7561 } else
7562 vcpu->arch.mp_state = mp_state->mp_state;
7563 kvm_make_request(KVM_REQ_EVENT, vcpu);
7564 return 0;
7565 }
7566
7567 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7568 int reason, bool has_error_code, u32 error_code)
7569 {
7570 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7571 int ret;
7572
7573 init_emulate_ctxt(vcpu);
7574
7575 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7576 has_error_code, error_code);
7577
7578 if (ret)
7579 return EMULATE_FAIL;
7580
7581 kvm_rip_write(vcpu, ctxt->eip);
7582 kvm_set_rflags(vcpu, ctxt->eflags);
7583 kvm_make_request(KVM_REQ_EVENT, vcpu);
7584 return EMULATE_DONE;
7585 }
7586 EXPORT_SYMBOL_GPL(kvm_task_switch);
7587
7588 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7589 {
7590 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7591 /*
7592 * When EFER.LME and CR0.PG are set, the processor is in
7593 * 64-bit mode (though maybe in a 32-bit code segment).
7594 * CR4.PAE and EFER.LMA must be set.
7595 */
7596 if (!(sregs->cr4 & X86_CR4_PAE)
7597 || !(sregs->efer & EFER_LMA))
7598 return -EINVAL;
7599 } else {
7600 /*
7601 * Not in 64-bit mode: EFER.LMA is clear and the code
7602 * segment cannot be 64-bit.
7603 */
7604 if (sregs->efer & EFER_LMA || sregs->cs.l)
7605 return -EINVAL;
7606 }
7607
7608 return 0;
7609 }
7610
7611 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7612 struct kvm_sregs *sregs)
7613 {
7614 struct msr_data apic_base_msr;
7615 int mmu_reset_needed = 0;
7616 int pending_vec, max_bits, idx;
7617 struct desc_ptr dt;
7618
7619 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7620 (sregs->cr4 & X86_CR4_OSXSAVE))
7621 return -EINVAL;
7622
7623 if (kvm_valid_sregs(vcpu, sregs))
7624 return -EINVAL;
7625
7626 apic_base_msr.data = sregs->apic_base;
7627 apic_base_msr.host_initiated = true;
7628 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7629 return -EINVAL;
7630
7631 dt.size = sregs->idt.limit;
7632 dt.address = sregs->idt.base;
7633 kvm_x86_ops->set_idt(vcpu, &dt);
7634 dt.size = sregs->gdt.limit;
7635 dt.address = sregs->gdt.base;
7636 kvm_x86_ops->set_gdt(vcpu, &dt);
7637
7638 vcpu->arch.cr2 = sregs->cr2;
7639 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7640 vcpu->arch.cr3 = sregs->cr3;
7641 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7642
7643 kvm_set_cr8(vcpu, sregs->cr8);
7644
7645 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7646 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7647
7648 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7649 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7650 vcpu->arch.cr0 = sregs->cr0;
7651
7652 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7653 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7654 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7655 kvm_update_cpuid(vcpu);
7656
7657 idx = srcu_read_lock(&vcpu->kvm->srcu);
7658 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7659 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7660 mmu_reset_needed = 1;
7661 }
7662 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7663
7664 if (mmu_reset_needed)
7665 kvm_mmu_reset_context(vcpu);
7666
7667 max_bits = KVM_NR_INTERRUPTS;
7668 pending_vec = find_first_bit(
7669 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7670 if (pending_vec < max_bits) {
7671 kvm_queue_interrupt(vcpu, pending_vec, false);
7672 pr_debug("Set back pending irq %d\n", pending_vec);
7673 }
7674
7675 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7676 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7677 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7678 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7679 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7680 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7681
7682 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7683 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7684
7685 update_cr8_intercept(vcpu);
7686
7687 /* Older userspace won't unhalt the vcpu on reset. */
7688 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7689 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7690 !is_protmode(vcpu))
7691 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7692
7693 kvm_make_request(KVM_REQ_EVENT, vcpu);
7694
7695 return 0;
7696 }
7697
7698 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7699 struct kvm_guest_debug *dbg)
7700 {
7701 unsigned long rflags;
7702 int i, r;
7703
7704 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7705 r = -EBUSY;
7706 if (vcpu->arch.exception.pending)
7707 goto out;
7708 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7709 kvm_queue_exception(vcpu, DB_VECTOR);
7710 else
7711 kvm_queue_exception(vcpu, BP_VECTOR);
7712 }
7713
7714 /*
7715 * Read rflags as long as potentially injected trace flags are still
7716 * filtered out.
7717 */
7718 rflags = kvm_get_rflags(vcpu);
7719
7720 vcpu->guest_debug = dbg->control;
7721 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7722 vcpu->guest_debug = 0;
7723
7724 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7725 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7726 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7727 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7728 } else {
7729 for (i = 0; i < KVM_NR_DB_REGS; i++)
7730 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7731 }
7732 kvm_update_dr7(vcpu);
7733
7734 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7735 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7736 get_segment_base(vcpu, VCPU_SREG_CS);
7737
7738 /*
7739 * Trigger an rflags update that will inject or remove the trace
7740 * flags.
7741 */
7742 kvm_set_rflags(vcpu, rflags);
7743
7744 kvm_x86_ops->update_bp_intercept(vcpu);
7745
7746 r = 0;
7747
7748 out:
7749
7750 return r;
7751 }
7752
7753 /*
7754 * Translate a guest virtual address to a guest physical address.
7755 */
7756 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7757 struct kvm_translation *tr)
7758 {
7759 unsigned long vaddr = tr->linear_address;
7760 gpa_t gpa;
7761 int idx;
7762
7763 idx = srcu_read_lock(&vcpu->kvm->srcu);
7764 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7766 tr->physical_address = gpa;
7767 tr->valid = gpa != UNMAPPED_GVA;
7768 tr->writeable = 1;
7769 tr->usermode = 0;
7770
7771 return 0;
7772 }
7773
7774 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7775 {
7776 struct fxregs_state *fxsave =
7777 &vcpu->arch.guest_fpu.state.fxsave;
7778
7779 memcpy(fpu->fpr, fxsave->st_space, 128);
7780 fpu->fcw = fxsave->cwd;
7781 fpu->fsw = fxsave->swd;
7782 fpu->ftwx = fxsave->twd;
7783 fpu->last_opcode = fxsave->fop;
7784 fpu->last_ip = fxsave->rip;
7785 fpu->last_dp = fxsave->rdp;
7786 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7787
7788 return 0;
7789 }
7790
7791 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7792 {
7793 struct fxregs_state *fxsave =
7794 &vcpu->arch.guest_fpu.state.fxsave;
7795
7796 memcpy(fxsave->st_space, fpu->fpr, 128);
7797 fxsave->cwd = fpu->fcw;
7798 fxsave->swd = fpu->fsw;
7799 fxsave->twd = fpu->ftwx;
7800 fxsave->fop = fpu->last_opcode;
7801 fxsave->rip = fpu->last_ip;
7802 fxsave->rdp = fpu->last_dp;
7803 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7804
7805 return 0;
7806 }
7807
7808 static void fx_init(struct kvm_vcpu *vcpu)
7809 {
7810 fpstate_init(&vcpu->arch.guest_fpu.state);
7811 if (boot_cpu_has(X86_FEATURE_XSAVES))
7812 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7813 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7814
7815 /*
7816 * Ensure guest xcr0 is valid for loading
7817 */
7818 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7819
7820 vcpu->arch.cr0 |= X86_CR0_ET;
7821 }
7822
7823 /* Swap (qemu) user FPU context for the guest FPU context. */
7824 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7825 {
7826 preempt_disable();
7827 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7828 /* PKRU is separately restored in kvm_x86_ops->run. */
7829 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7830 ~XFEATURE_MASK_PKRU);
7831 preempt_enable();
7832 trace_kvm_fpu(1);
7833 }
7834
7835 /* When vcpu_run ends, restore user space FPU context. */
7836 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7837 {
7838 preempt_disable();
7839 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7840 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7841 preempt_enable();
7842 ++vcpu->stat.fpu_reload;
7843 trace_kvm_fpu(0);
7844 }
7845
7846 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7847 {
7848 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7849
7850 kvmclock_reset(vcpu);
7851
7852 kvm_x86_ops->vcpu_free(vcpu);
7853 free_cpumask_var(wbinvd_dirty_mask);
7854 }
7855
7856 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7857 unsigned int id)
7858 {
7859 struct kvm_vcpu *vcpu;
7860
7861 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7862 printk_once(KERN_WARNING
7863 "kvm: SMP vm created on host with unstable TSC; "
7864 "guest TSC will not be reliable\n");
7865
7866 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7867
7868 return vcpu;
7869 }
7870
7871 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7872 {
7873 int r;
7874
7875 kvm_vcpu_mtrr_init(vcpu);
7876 r = vcpu_load(vcpu);
7877 if (r)
7878 return r;
7879 kvm_vcpu_reset(vcpu, false);
7880 kvm_mmu_setup(vcpu);
7881 vcpu_put(vcpu);
7882 return r;
7883 }
7884
7885 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7886 {
7887 struct msr_data msr;
7888 struct kvm *kvm = vcpu->kvm;
7889
7890 kvm_hv_vcpu_postcreate(vcpu);
7891
7892 if (vcpu_load(vcpu))
7893 return;
7894 msr.data = 0x0;
7895 msr.index = MSR_IA32_TSC;
7896 msr.host_initiated = true;
7897 kvm_write_tsc(vcpu, &msr);
7898 vcpu_put(vcpu);
7899
7900 if (!kvmclock_periodic_sync)
7901 return;
7902
7903 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7904 KVMCLOCK_SYNC_PERIOD);
7905 }
7906
7907 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7908 {
7909 int r;
7910 vcpu->arch.apf.msr_val = 0;
7911
7912 r = vcpu_load(vcpu);
7913 BUG_ON(r);
7914 kvm_mmu_unload(vcpu);
7915 vcpu_put(vcpu);
7916
7917 kvm_x86_ops->vcpu_free(vcpu);
7918 }
7919
7920 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7921 {
7922 kvm_lapic_reset(vcpu, init_event);
7923
7924 vcpu->arch.hflags = 0;
7925
7926 vcpu->arch.smi_pending = 0;
7927 atomic_set(&vcpu->arch.nmi_queued, 0);
7928 vcpu->arch.nmi_pending = 0;
7929 vcpu->arch.nmi_injected = false;
7930 kvm_clear_interrupt_queue(vcpu);
7931 kvm_clear_exception_queue(vcpu);
7932 vcpu->arch.exception.pending = false;
7933
7934 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7935 kvm_update_dr0123(vcpu);
7936 vcpu->arch.dr6 = DR6_INIT;
7937 kvm_update_dr6(vcpu);
7938 vcpu->arch.dr7 = DR7_FIXED_1;
7939 kvm_update_dr7(vcpu);
7940
7941 vcpu->arch.cr2 = 0;
7942
7943 kvm_make_request(KVM_REQ_EVENT, vcpu);
7944 vcpu->arch.apf.msr_val = 0;
7945 vcpu->arch.st.msr_val = 0;
7946
7947 kvmclock_reset(vcpu);
7948
7949 kvm_clear_async_pf_completion_queue(vcpu);
7950 kvm_async_pf_hash_reset(vcpu);
7951 vcpu->arch.apf.halted = false;
7952
7953 if (kvm_mpx_supported()) {
7954 void *mpx_state_buffer;
7955
7956 /*
7957 * To avoid have the INIT path from kvm_apic_has_events() that be
7958 * called with loaded FPU and does not let userspace fix the state.
7959 */
7960 if (init_event)
7961 kvm_put_guest_fpu(vcpu);
7962 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7963 XFEATURE_MASK_BNDREGS);
7964 if (mpx_state_buffer)
7965 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7966 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7967 XFEATURE_MASK_BNDCSR);
7968 if (mpx_state_buffer)
7969 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7970 if (init_event)
7971 kvm_load_guest_fpu(vcpu);
7972 }
7973
7974 if (!init_event) {
7975 kvm_pmu_reset(vcpu);
7976 vcpu->arch.smbase = 0x30000;
7977
7978 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7979 vcpu->arch.msr_misc_features_enables = 0;
7980
7981 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7982 }
7983
7984 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7985 vcpu->arch.regs_avail = ~0;
7986 vcpu->arch.regs_dirty = ~0;
7987
7988 vcpu->arch.ia32_xss = 0;
7989
7990 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7991 }
7992
7993 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7994 {
7995 struct kvm_segment cs;
7996
7997 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7998 cs.selector = vector << 8;
7999 cs.base = vector << 12;
8000 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8001 kvm_rip_write(vcpu, 0);
8002 }
8003
8004 int kvm_arch_hardware_enable(void)
8005 {
8006 struct kvm *kvm;
8007 struct kvm_vcpu *vcpu;
8008 int i;
8009 int ret;
8010 u64 local_tsc;
8011 u64 max_tsc = 0;
8012 bool stable, backwards_tsc = false;
8013
8014 kvm_shared_msr_cpu_online();
8015 ret = kvm_x86_ops->hardware_enable();
8016 if (ret != 0)
8017 return ret;
8018
8019 local_tsc = rdtsc();
8020 stable = !check_tsc_unstable();
8021 list_for_each_entry(kvm, &vm_list, vm_list) {
8022 kvm_for_each_vcpu(i, vcpu, kvm) {
8023 if (!stable && vcpu->cpu == smp_processor_id())
8024 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8025 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8026 backwards_tsc = true;
8027 if (vcpu->arch.last_host_tsc > max_tsc)
8028 max_tsc = vcpu->arch.last_host_tsc;
8029 }
8030 }
8031 }
8032
8033 /*
8034 * Sometimes, even reliable TSCs go backwards. This happens on
8035 * platforms that reset TSC during suspend or hibernate actions, but
8036 * maintain synchronization. We must compensate. Fortunately, we can
8037 * detect that condition here, which happens early in CPU bringup,
8038 * before any KVM threads can be running. Unfortunately, we can't
8039 * bring the TSCs fully up to date with real time, as we aren't yet far
8040 * enough into CPU bringup that we know how much real time has actually
8041 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8042 * variables that haven't been updated yet.
8043 *
8044 * So we simply find the maximum observed TSC above, then record the
8045 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8046 * the adjustment will be applied. Note that we accumulate
8047 * adjustments, in case multiple suspend cycles happen before some VCPU
8048 * gets a chance to run again. In the event that no KVM threads get a
8049 * chance to run, we will miss the entire elapsed period, as we'll have
8050 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8051 * loose cycle time. This isn't too big a deal, since the loss will be
8052 * uniform across all VCPUs (not to mention the scenario is extremely
8053 * unlikely). It is possible that a second hibernate recovery happens
8054 * much faster than a first, causing the observed TSC here to be
8055 * smaller; this would require additional padding adjustment, which is
8056 * why we set last_host_tsc to the local tsc observed here.
8057 *
8058 * N.B. - this code below runs only on platforms with reliable TSC,
8059 * as that is the only way backwards_tsc is set above. Also note
8060 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8061 * have the same delta_cyc adjustment applied if backwards_tsc
8062 * is detected. Note further, this adjustment is only done once,
8063 * as we reset last_host_tsc on all VCPUs to stop this from being
8064 * called multiple times (one for each physical CPU bringup).
8065 *
8066 * Platforms with unreliable TSCs don't have to deal with this, they
8067 * will be compensated by the logic in vcpu_load, which sets the TSC to
8068 * catchup mode. This will catchup all VCPUs to real time, but cannot
8069 * guarantee that they stay in perfect synchronization.
8070 */
8071 if (backwards_tsc) {
8072 u64 delta_cyc = max_tsc - local_tsc;
8073 list_for_each_entry(kvm, &vm_list, vm_list) {
8074 kvm->arch.backwards_tsc_observed = true;
8075 kvm_for_each_vcpu(i, vcpu, kvm) {
8076 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8077 vcpu->arch.last_host_tsc = local_tsc;
8078 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8079 }
8080
8081 /*
8082 * We have to disable TSC offset matching.. if you were
8083 * booting a VM while issuing an S4 host suspend....
8084 * you may have some problem. Solving this issue is
8085 * left as an exercise to the reader.
8086 */
8087 kvm->arch.last_tsc_nsec = 0;
8088 kvm->arch.last_tsc_write = 0;
8089 }
8090
8091 }
8092 return 0;
8093 }
8094
8095 void kvm_arch_hardware_disable(void)
8096 {
8097 kvm_x86_ops->hardware_disable();
8098 drop_user_return_notifiers();
8099 }
8100
8101 int kvm_arch_hardware_setup(void)
8102 {
8103 int r;
8104
8105 r = kvm_x86_ops->hardware_setup();
8106 if (r != 0)
8107 return r;
8108
8109 if (kvm_has_tsc_control) {
8110 /*
8111 * Make sure the user can only configure tsc_khz values that
8112 * fit into a signed integer.
8113 * A min value is not calculated needed because it will always
8114 * be 1 on all machines.
8115 */
8116 u64 max = min(0x7fffffffULL,
8117 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8118 kvm_max_guest_tsc_khz = max;
8119
8120 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8121 }
8122
8123 kvm_init_msr_list();
8124 return 0;
8125 }
8126
8127 void kvm_arch_hardware_unsetup(void)
8128 {
8129 kvm_x86_ops->hardware_unsetup();
8130 }
8131
8132 void kvm_arch_check_processor_compat(void *rtn)
8133 {
8134 kvm_x86_ops->check_processor_compatibility(rtn);
8135 }
8136
8137 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8138 {
8139 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8140 }
8141 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8142
8143 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8144 {
8145 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8146 }
8147
8148 struct static_key kvm_no_apic_vcpu __read_mostly;
8149 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8150
8151 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8152 {
8153 struct page *page;
8154 int r;
8155
8156 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8157 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8158 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8159 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8160 else
8161 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8162
8163 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8164 if (!page) {
8165 r = -ENOMEM;
8166 goto fail;
8167 }
8168 vcpu->arch.pio_data = page_address(page);
8169
8170 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8171
8172 r = kvm_mmu_create(vcpu);
8173 if (r < 0)
8174 goto fail_free_pio_data;
8175
8176 if (irqchip_in_kernel(vcpu->kvm)) {
8177 r = kvm_create_lapic(vcpu);
8178 if (r < 0)
8179 goto fail_mmu_destroy;
8180 } else
8181 static_key_slow_inc(&kvm_no_apic_vcpu);
8182
8183 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8184 GFP_KERNEL);
8185 if (!vcpu->arch.mce_banks) {
8186 r = -ENOMEM;
8187 goto fail_free_lapic;
8188 }
8189 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8190
8191 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8192 r = -ENOMEM;
8193 goto fail_free_mce_banks;
8194 }
8195
8196 fx_init(vcpu);
8197
8198 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8199
8200 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8201
8202 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8203
8204 kvm_async_pf_hash_reset(vcpu);
8205 kvm_pmu_init(vcpu);
8206
8207 vcpu->arch.pending_external_vector = -1;
8208 vcpu->arch.preempted_in_kernel = false;
8209
8210 kvm_hv_vcpu_init(vcpu);
8211
8212 return 0;
8213
8214 fail_free_mce_banks:
8215 kfree(vcpu->arch.mce_banks);
8216 fail_free_lapic:
8217 kvm_free_lapic(vcpu);
8218 fail_mmu_destroy:
8219 kvm_mmu_destroy(vcpu);
8220 fail_free_pio_data:
8221 free_page((unsigned long)vcpu->arch.pio_data);
8222 fail:
8223 return r;
8224 }
8225
8226 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8227 {
8228 int idx;
8229
8230 kvm_hv_vcpu_uninit(vcpu);
8231 kvm_pmu_destroy(vcpu);
8232 kfree(vcpu->arch.mce_banks);
8233 kvm_free_lapic(vcpu);
8234 idx = srcu_read_lock(&vcpu->kvm->srcu);
8235 kvm_mmu_destroy(vcpu);
8236 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8237 free_page((unsigned long)vcpu->arch.pio_data);
8238 if (!lapic_in_kernel(vcpu))
8239 static_key_slow_dec(&kvm_no_apic_vcpu);
8240 }
8241
8242 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8243 {
8244 vcpu->arch.l1tf_flush_l1d = true;
8245 kvm_x86_ops->sched_in(vcpu, cpu);
8246 }
8247
8248 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8249 {
8250 if (type)
8251 return -EINVAL;
8252
8253 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8254 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8255 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8256 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8257 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8258
8259 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8260 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8261 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8262 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8263 &kvm->arch.irq_sources_bitmap);
8264
8265 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8266 mutex_init(&kvm->arch.apic_map_lock);
8267 mutex_init(&kvm->arch.hyperv.hv_lock);
8268 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8269
8270 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8271 pvclock_update_vm_gtod_copy(kvm);
8272
8273 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8274 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8275
8276 kvm_page_track_init(kvm);
8277 kvm_mmu_init_vm(kvm);
8278
8279 if (kvm_x86_ops->vm_init)
8280 return kvm_x86_ops->vm_init(kvm);
8281
8282 return 0;
8283 }
8284
8285 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8286 {
8287 int r;
8288 r = vcpu_load(vcpu);
8289 BUG_ON(r);
8290 kvm_mmu_unload(vcpu);
8291 vcpu_put(vcpu);
8292 }
8293
8294 static void kvm_free_vcpus(struct kvm *kvm)
8295 {
8296 unsigned int i;
8297 struct kvm_vcpu *vcpu;
8298
8299 /*
8300 * Unpin any mmu pages first.
8301 */
8302 kvm_for_each_vcpu(i, vcpu, kvm) {
8303 kvm_clear_async_pf_completion_queue(vcpu);
8304 kvm_unload_vcpu_mmu(vcpu);
8305 }
8306 kvm_for_each_vcpu(i, vcpu, kvm)
8307 kvm_arch_vcpu_free(vcpu);
8308
8309 mutex_lock(&kvm->lock);
8310 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8311 kvm->vcpus[i] = NULL;
8312
8313 atomic_set(&kvm->online_vcpus, 0);
8314 mutex_unlock(&kvm->lock);
8315 }
8316
8317 void kvm_arch_sync_events(struct kvm *kvm)
8318 {
8319 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8320 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8321 kvm_free_pit(kvm);
8322 }
8323
8324 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8325 {
8326 int i, r;
8327 unsigned long hva;
8328 struct kvm_memslots *slots = kvm_memslots(kvm);
8329 struct kvm_memory_slot *slot, old;
8330
8331 /* Called with kvm->slots_lock held. */
8332 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8333 return -EINVAL;
8334
8335 slot = id_to_memslot(slots, id);
8336 if (size) {
8337 if (slot->npages)
8338 return -EEXIST;
8339
8340 /*
8341 * MAP_SHARED to prevent internal slot pages from being moved
8342 * by fork()/COW.
8343 */
8344 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8345 MAP_SHARED | MAP_ANONYMOUS, 0);
8346 if (IS_ERR((void *)hva))
8347 return PTR_ERR((void *)hva);
8348 } else {
8349 if (!slot->npages)
8350 return 0;
8351
8352 hva = 0;
8353 }
8354
8355 old = *slot;
8356 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8357 struct kvm_userspace_memory_region m;
8358
8359 m.slot = id | (i << 16);
8360 m.flags = 0;
8361 m.guest_phys_addr = gpa;
8362 m.userspace_addr = hva;
8363 m.memory_size = size;
8364 r = __kvm_set_memory_region(kvm, &m);
8365 if (r < 0)
8366 return r;
8367 }
8368
8369 if (!size)
8370 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8371
8372 return 0;
8373 }
8374 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8375
8376 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8377 {
8378 int r;
8379
8380 mutex_lock(&kvm->slots_lock);
8381 r = __x86_set_memory_region(kvm, id, gpa, size);
8382 mutex_unlock(&kvm->slots_lock);
8383
8384 return r;
8385 }
8386 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8387
8388 void kvm_arch_destroy_vm(struct kvm *kvm)
8389 {
8390 if (current->mm == kvm->mm) {
8391 /*
8392 * Free memory regions allocated on behalf of userspace,
8393 * unless the the memory map has changed due to process exit
8394 * or fd copying.
8395 */
8396 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8397 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8398 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8399 }
8400 if (kvm_x86_ops->vm_destroy)
8401 kvm_x86_ops->vm_destroy(kvm);
8402 kvm_pic_destroy(kvm);
8403 kvm_ioapic_destroy(kvm);
8404 kvm_free_vcpus(kvm);
8405 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8406 kvm_mmu_uninit_vm(kvm);
8407 kvm_page_track_cleanup(kvm);
8408 }
8409
8410 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8411 struct kvm_memory_slot *dont)
8412 {
8413 int i;
8414
8415 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8416 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8417 kvfree(free->arch.rmap[i]);
8418 free->arch.rmap[i] = NULL;
8419 }
8420 if (i == 0)
8421 continue;
8422
8423 if (!dont || free->arch.lpage_info[i - 1] !=
8424 dont->arch.lpage_info[i - 1]) {
8425 kvfree(free->arch.lpage_info[i - 1]);
8426 free->arch.lpage_info[i - 1] = NULL;
8427 }
8428 }
8429
8430 kvm_page_track_free_memslot(free, dont);
8431 }
8432
8433 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8434 unsigned long npages)
8435 {
8436 int i;
8437
8438 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8439 struct kvm_lpage_info *linfo;
8440 unsigned long ugfn;
8441 int lpages;
8442 int level = i + 1;
8443
8444 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8445 slot->base_gfn, level) + 1;
8446
8447 slot->arch.rmap[i] =
8448 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8449 if (!slot->arch.rmap[i])
8450 goto out_free;
8451 if (i == 0)
8452 continue;
8453
8454 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8455 if (!linfo)
8456 goto out_free;
8457
8458 slot->arch.lpage_info[i - 1] = linfo;
8459
8460 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8461 linfo[0].disallow_lpage = 1;
8462 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8463 linfo[lpages - 1].disallow_lpage = 1;
8464 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8465 /*
8466 * If the gfn and userspace address are not aligned wrt each
8467 * other, or if explicitly asked to, disable large page
8468 * support for this slot
8469 */
8470 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8471 !kvm_largepages_enabled()) {
8472 unsigned long j;
8473
8474 for (j = 0; j < lpages; ++j)
8475 linfo[j].disallow_lpage = 1;
8476 }
8477 }
8478
8479 if (kvm_page_track_create_memslot(slot, npages))
8480 goto out_free;
8481
8482 return 0;
8483
8484 out_free:
8485 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8486 kvfree(slot->arch.rmap[i]);
8487 slot->arch.rmap[i] = NULL;
8488 if (i == 0)
8489 continue;
8490
8491 kvfree(slot->arch.lpage_info[i - 1]);
8492 slot->arch.lpage_info[i - 1] = NULL;
8493 }
8494 return -ENOMEM;
8495 }
8496
8497 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8498 {
8499 /*
8500 * memslots->generation has been incremented.
8501 * mmio generation may have reached its maximum value.
8502 */
8503 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8504 }
8505
8506 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8507 struct kvm_memory_slot *memslot,
8508 const struct kvm_userspace_memory_region *mem,
8509 enum kvm_mr_change change)
8510 {
8511 return 0;
8512 }
8513
8514 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8515 struct kvm_memory_slot *new)
8516 {
8517 /* Still write protect RO slot */
8518 if (new->flags & KVM_MEM_READONLY) {
8519 kvm_mmu_slot_remove_write_access(kvm, new);
8520 return;
8521 }
8522
8523 /*
8524 * Call kvm_x86_ops dirty logging hooks when they are valid.
8525 *
8526 * kvm_x86_ops->slot_disable_log_dirty is called when:
8527 *
8528 * - KVM_MR_CREATE with dirty logging is disabled
8529 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8530 *
8531 * The reason is, in case of PML, we need to set D-bit for any slots
8532 * with dirty logging disabled in order to eliminate unnecessary GPA
8533 * logging in PML buffer (and potential PML buffer full VMEXT). This
8534 * guarantees leaving PML enabled during guest's lifetime won't have
8535 * any additonal overhead from PML when guest is running with dirty
8536 * logging disabled for memory slots.
8537 *
8538 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8539 * to dirty logging mode.
8540 *
8541 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8542 *
8543 * In case of write protect:
8544 *
8545 * Write protect all pages for dirty logging.
8546 *
8547 * All the sptes including the large sptes which point to this
8548 * slot are set to readonly. We can not create any new large
8549 * spte on this slot until the end of the logging.
8550 *
8551 * See the comments in fast_page_fault().
8552 */
8553 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8554 if (kvm_x86_ops->slot_enable_log_dirty)
8555 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8556 else
8557 kvm_mmu_slot_remove_write_access(kvm, new);
8558 } else {
8559 if (kvm_x86_ops->slot_disable_log_dirty)
8560 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8561 }
8562 }
8563
8564 void kvm_arch_commit_memory_region(struct kvm *kvm,
8565 const struct kvm_userspace_memory_region *mem,
8566 const struct kvm_memory_slot *old,
8567 const struct kvm_memory_slot *new,
8568 enum kvm_mr_change change)
8569 {
8570 int nr_mmu_pages = 0;
8571
8572 if (!kvm->arch.n_requested_mmu_pages)
8573 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8574
8575 if (nr_mmu_pages)
8576 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8577
8578 /*
8579 * Dirty logging tracks sptes in 4k granularity, meaning that large
8580 * sptes have to be split. If live migration is successful, the guest
8581 * in the source machine will be destroyed and large sptes will be
8582 * created in the destination. However, if the guest continues to run
8583 * in the source machine (for example if live migration fails), small
8584 * sptes will remain around and cause bad performance.
8585 *
8586 * Scan sptes if dirty logging has been stopped, dropping those
8587 * which can be collapsed into a single large-page spte. Later
8588 * page faults will create the large-page sptes.
8589 */
8590 if ((change != KVM_MR_DELETE) &&
8591 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8592 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8593 kvm_mmu_zap_collapsible_sptes(kvm, new);
8594
8595 /*
8596 * Set up write protection and/or dirty logging for the new slot.
8597 *
8598 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8599 * been zapped so no dirty logging staff is needed for old slot. For
8600 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8601 * new and it's also covered when dealing with the new slot.
8602 *
8603 * FIXME: const-ify all uses of struct kvm_memory_slot.
8604 */
8605 if (change != KVM_MR_DELETE)
8606 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8607 }
8608
8609 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8610 {
8611 kvm_mmu_invalidate_zap_all_pages(kvm);
8612 }
8613
8614 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8615 struct kvm_memory_slot *slot)
8616 {
8617 kvm_page_track_flush_slot(kvm, slot);
8618 }
8619
8620 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8621 {
8622 if (!list_empty_careful(&vcpu->async_pf.done))
8623 return true;
8624
8625 if (kvm_apic_has_events(vcpu))
8626 return true;
8627
8628 if (vcpu->arch.pv.pv_unhalted)
8629 return true;
8630
8631 if (vcpu->arch.exception.pending)
8632 return true;
8633
8634 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8635 (vcpu->arch.nmi_pending &&
8636 kvm_x86_ops->nmi_allowed(vcpu)))
8637 return true;
8638
8639 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8640 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8641 return true;
8642
8643 if (kvm_arch_interrupt_allowed(vcpu) &&
8644 kvm_cpu_has_interrupt(vcpu))
8645 return true;
8646
8647 if (kvm_hv_has_stimer_pending(vcpu))
8648 return true;
8649
8650 return false;
8651 }
8652
8653 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8654 {
8655 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8656 }
8657
8658 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8659 {
8660 return vcpu->arch.preempted_in_kernel;
8661 }
8662
8663 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8664 {
8665 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8666 }
8667
8668 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8669 {
8670 return kvm_x86_ops->interrupt_allowed(vcpu);
8671 }
8672
8673 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8674 {
8675 if (is_64_bit_mode(vcpu))
8676 return kvm_rip_read(vcpu);
8677 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8678 kvm_rip_read(vcpu));
8679 }
8680 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8681
8682 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8683 {
8684 return kvm_get_linear_rip(vcpu) == linear_rip;
8685 }
8686 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8687
8688 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8689 {
8690 unsigned long rflags;
8691
8692 rflags = kvm_x86_ops->get_rflags(vcpu);
8693 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8694 rflags &= ~X86_EFLAGS_TF;
8695 return rflags;
8696 }
8697 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8698
8699 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8700 {
8701 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8702 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8703 rflags |= X86_EFLAGS_TF;
8704 kvm_x86_ops->set_rflags(vcpu, rflags);
8705 }
8706
8707 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8708 {
8709 __kvm_set_rflags(vcpu, rflags);
8710 kvm_make_request(KVM_REQ_EVENT, vcpu);
8711 }
8712 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8713
8714 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8715 {
8716 int r;
8717
8718 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8719 work->wakeup_all)
8720 return;
8721
8722 r = kvm_mmu_reload(vcpu);
8723 if (unlikely(r))
8724 return;
8725
8726 if (!vcpu->arch.mmu.direct_map &&
8727 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8728 return;
8729
8730 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8731 }
8732
8733 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8734 {
8735 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8736 }
8737
8738 static inline u32 kvm_async_pf_next_probe(u32 key)
8739 {
8740 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8741 }
8742
8743 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8744 {
8745 u32 key = kvm_async_pf_hash_fn(gfn);
8746
8747 while (vcpu->arch.apf.gfns[key] != ~0)
8748 key = kvm_async_pf_next_probe(key);
8749
8750 vcpu->arch.apf.gfns[key] = gfn;
8751 }
8752
8753 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8754 {
8755 int i;
8756 u32 key = kvm_async_pf_hash_fn(gfn);
8757
8758 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8759 (vcpu->arch.apf.gfns[key] != gfn &&
8760 vcpu->arch.apf.gfns[key] != ~0); i++)
8761 key = kvm_async_pf_next_probe(key);
8762
8763 return key;
8764 }
8765
8766 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8767 {
8768 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8769 }
8770
8771 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8772 {
8773 u32 i, j, k;
8774
8775 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8776 while (true) {
8777 vcpu->arch.apf.gfns[i] = ~0;
8778 do {
8779 j = kvm_async_pf_next_probe(j);
8780 if (vcpu->arch.apf.gfns[j] == ~0)
8781 return;
8782 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8783 /*
8784 * k lies cyclically in ]i,j]
8785 * | i.k.j |
8786 * |....j i.k.| or |.k..j i...|
8787 */
8788 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8789 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8790 i = j;
8791 }
8792 }
8793
8794 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8795 {
8796
8797 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8798 sizeof(val));
8799 }
8800
8801 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8802 {
8803
8804 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8805 sizeof(u32));
8806 }
8807
8808 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8809 struct kvm_async_pf *work)
8810 {
8811 struct x86_exception fault;
8812
8813 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8814 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8815
8816 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8817 (vcpu->arch.apf.send_user_only &&
8818 kvm_x86_ops->get_cpl(vcpu) == 0))
8819 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8820 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8821 fault.vector = PF_VECTOR;
8822 fault.error_code_valid = true;
8823 fault.error_code = 0;
8824 fault.nested_page_fault = false;
8825 fault.address = work->arch.token;
8826 fault.async_page_fault = true;
8827 kvm_inject_page_fault(vcpu, &fault);
8828 }
8829 }
8830
8831 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8832 struct kvm_async_pf *work)
8833 {
8834 struct x86_exception fault;
8835 u32 val;
8836
8837 if (work->wakeup_all)
8838 work->arch.token = ~0; /* broadcast wakeup */
8839 else
8840 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8841 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8842
8843 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8844 !apf_get_user(vcpu, &val)) {
8845 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8846 vcpu->arch.exception.pending &&
8847 vcpu->arch.exception.nr == PF_VECTOR &&
8848 !apf_put_user(vcpu, 0)) {
8849 vcpu->arch.exception.injected = false;
8850 vcpu->arch.exception.pending = false;
8851 vcpu->arch.exception.nr = 0;
8852 vcpu->arch.exception.has_error_code = false;
8853 vcpu->arch.exception.error_code = 0;
8854 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8855 fault.vector = PF_VECTOR;
8856 fault.error_code_valid = true;
8857 fault.error_code = 0;
8858 fault.nested_page_fault = false;
8859 fault.address = work->arch.token;
8860 fault.async_page_fault = true;
8861 kvm_inject_page_fault(vcpu, &fault);
8862 }
8863 }
8864 vcpu->arch.apf.halted = false;
8865 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8866 }
8867
8868 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8869 {
8870 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8871 return true;
8872 else
8873 return kvm_can_do_async_pf(vcpu);
8874 }
8875
8876 void kvm_arch_start_assignment(struct kvm *kvm)
8877 {
8878 atomic_inc(&kvm->arch.assigned_device_count);
8879 }
8880 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8881
8882 void kvm_arch_end_assignment(struct kvm *kvm)
8883 {
8884 atomic_dec(&kvm->arch.assigned_device_count);
8885 }
8886 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8887
8888 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8889 {
8890 return atomic_read(&kvm->arch.assigned_device_count);
8891 }
8892 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8893
8894 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8895 {
8896 atomic_inc(&kvm->arch.noncoherent_dma_count);
8897 }
8898 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8899
8900 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8901 {
8902 atomic_dec(&kvm->arch.noncoherent_dma_count);
8903 }
8904 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8905
8906 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8907 {
8908 return atomic_read(&kvm->arch.noncoherent_dma_count);
8909 }
8910 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8911
8912 bool kvm_arch_has_irq_bypass(void)
8913 {
8914 return kvm_x86_ops->update_pi_irte != NULL;
8915 }
8916
8917 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8918 struct irq_bypass_producer *prod)
8919 {
8920 struct kvm_kernel_irqfd *irqfd =
8921 container_of(cons, struct kvm_kernel_irqfd, consumer);
8922
8923 irqfd->producer = prod;
8924
8925 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8926 prod->irq, irqfd->gsi, 1);
8927 }
8928
8929 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8930 struct irq_bypass_producer *prod)
8931 {
8932 int ret;
8933 struct kvm_kernel_irqfd *irqfd =
8934 container_of(cons, struct kvm_kernel_irqfd, consumer);
8935
8936 WARN_ON(irqfd->producer != prod);
8937 irqfd->producer = NULL;
8938
8939 /*
8940 * When producer of consumer is unregistered, we change back to
8941 * remapped mode, so we can re-use the current implementation
8942 * when the irq is masked/disabled or the consumer side (KVM
8943 * int this case doesn't want to receive the interrupts.
8944 */
8945 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8946 if (ret)
8947 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8948 " fails: %d\n", irqfd->consumer.token, ret);
8949 }
8950
8951 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8952 uint32_t guest_irq, bool set)
8953 {
8954 if (!kvm_x86_ops->update_pi_irte)
8955 return -EINVAL;
8956
8957 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8958 }
8959
8960 bool kvm_vector_hashing_enabled(void)
8961 {
8962 return vector_hashing;
8963 }
8964 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8965
8966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8970 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8971 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8972 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8973 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8976 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8977 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8978 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8979 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8980 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8981 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8982 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8983 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8984 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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