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1 /*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41
42 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
44
45 #ifdef CONFIG_ACPI
46 #include <acpi/processor.h>
47 #include <acpi/cppc_acpi.h>
48 #endif
49
50 #define FRAC_BITS 8
51 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52 #define fp_toint(X) ((X) >> FRAC_BITS)
53
54 #define EXT_BITS 6
55 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
56 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
57 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
58
59 static inline int32_t mul_fp(int32_t x, int32_t y)
60 {
61 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
62 }
63
64 static inline int32_t div_fp(s64 x, s64 y)
65 {
66 return div64_s64((int64_t)x << FRAC_BITS, y);
67 }
68
69 static inline int ceiling_fp(int32_t x)
70 {
71 int mask, ret;
72
73 ret = fp_toint(x);
74 mask = (1 << FRAC_BITS) - 1;
75 if (x & mask)
76 ret += 1;
77 return ret;
78 }
79
80 static inline int32_t percent_fp(int percent)
81 {
82 return div_fp(percent, 100);
83 }
84
85 static inline u64 mul_ext_fp(u64 x, u64 y)
86 {
87 return (x * y) >> EXT_FRAC_BITS;
88 }
89
90 static inline u64 div_ext_fp(u64 x, u64 y)
91 {
92 return div64_u64(x << EXT_FRAC_BITS, y);
93 }
94
95 static inline int32_t percent_ext_fp(int percent)
96 {
97 return div_ext_fp(percent, 100);
98 }
99
100 /**
101 * struct sample - Store performance sample
102 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
103 * performance during last sample period
104 * @busy_scaled: Scaled busy value which is used to calculate next
105 * P state. This can be different than core_avg_perf
106 * to account for cpu idle period
107 * @aperf: Difference of actual performance frequency clock count
108 * read from APERF MSR between last and current sample
109 * @mperf: Difference of maximum performance frequency clock count
110 * read from MPERF MSR between last and current sample
111 * @tsc: Difference of time stamp counter between last and
112 * current sample
113 * @time: Current time from scheduler
114 *
115 * This structure is used in the cpudata structure to store performance sample
116 * data for choosing next P State.
117 */
118 struct sample {
119 int32_t core_avg_perf;
120 int32_t busy_scaled;
121 u64 aperf;
122 u64 mperf;
123 u64 tsc;
124 u64 time;
125 };
126
127 /**
128 * struct pstate_data - Store P state data
129 * @current_pstate: Current requested P state
130 * @min_pstate: Min P state possible for this platform
131 * @max_pstate: Max P state possible for this platform
132 * @max_pstate_physical:This is physical Max P state for a processor
133 * This can be higher than the max_pstate which can
134 * be limited by platform thermal design power limits
135 * @scaling: Scaling factor to convert frequency to cpufreq
136 * frequency units
137 * @turbo_pstate: Max Turbo P state possible for this platform
138 * @max_freq: @max_pstate frequency in cpufreq units
139 * @turbo_freq: @turbo_pstate frequency in cpufreq units
140 *
141 * Stores the per cpu model P state limits and current P state.
142 */
143 struct pstate_data {
144 int current_pstate;
145 int min_pstate;
146 int max_pstate;
147 int max_pstate_physical;
148 int scaling;
149 int turbo_pstate;
150 unsigned int max_freq;
151 unsigned int turbo_freq;
152 };
153
154 /**
155 * struct vid_data - Stores voltage information data
156 * @min: VID data for this platform corresponding to
157 * the lowest P state
158 * @max: VID data corresponding to the highest P State.
159 * @turbo: VID data for turbo P state
160 * @ratio: Ratio of (vid max - vid min) /
161 * (max P state - Min P State)
162 *
163 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
164 * This data is used in Atom platforms, where in addition to target P state,
165 * the voltage data needs to be specified to select next P State.
166 */
167 struct vid_data {
168 int min;
169 int max;
170 int turbo;
171 int32_t ratio;
172 };
173
174 /**
175 * struct global_params - Global parameters, mostly tunable via sysfs.
176 * @no_turbo: Whether or not to use turbo P-states.
177 * @turbo_disabled: Whethet or not turbo P-states are available at all,
178 * based on the MSR_IA32_MISC_ENABLE value and whether or
179 * not the maximum reported turbo P-state is different from
180 * the maximum reported non-turbo one.
181 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
182 * P-state capacity.
183 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
184 * P-state capacity.
185 */
186 struct global_params {
187 bool no_turbo;
188 bool turbo_disabled;
189 int max_perf_pct;
190 int min_perf_pct;
191 };
192
193 /**
194 * struct cpudata - Per CPU instance data storage
195 * @cpu: CPU number for this instance data
196 * @policy: CPUFreq policy value
197 * @update_util: CPUFreq utility callback information
198 * @update_util_set: CPUFreq utility callback is set
199 * @iowait_boost: iowait-related boost fraction
200 * @last_update: Time of the last update.
201 * @pstate: Stores P state limits for this CPU
202 * @vid: Stores VID limits for this CPU
203 * @last_sample_time: Last Sample time
204 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
205 * This shift is a multiplier to mperf delta to
206 * calculate CPU busy.
207 * @prev_aperf: Last APERF value read from APERF MSR
208 * @prev_mperf: Last MPERF value read from MPERF MSR
209 * @prev_tsc: Last timestamp counter (TSC) value
210 * @prev_cummulative_iowait: IO Wait time difference from last and
211 * current sample
212 * @sample: Storage for storing last Sample data
213 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
214 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
215 * @acpi_perf_data: Stores ACPI perf information read from _PSS
216 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
217 * @epp_powersave: Last saved HWP energy performance preference
218 * (EPP) or energy performance bias (EPB),
219 * when policy switched to performance
220 * @epp_policy: Last saved policy used to set EPP/EPB
221 * @epp_default: Power on default HWP energy performance
222 * preference/bias
223 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
224 * operation
225 *
226 * This structure stores per CPU instance data for all CPUs.
227 */
228 struct cpudata {
229 int cpu;
230
231 unsigned int policy;
232 struct update_util_data update_util;
233 bool update_util_set;
234
235 struct pstate_data pstate;
236 struct vid_data vid;
237
238 u64 last_update;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
241 u64 prev_aperf;
242 u64 prev_mperf;
243 u64 prev_tsc;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248 #ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251 #endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_saved;
257 };
258
259 static struct cpudata **all_cpu_data;
260
261 /**
262 * struct pstate_funcs - Per CPU model specific callbacks
263 * @get_max: Callback to get maximum non turbo effective P state
264 * @get_max_physical: Callback to get maximum non turbo physical P state
265 * @get_min: Callback to get minimum P state
266 * @get_turbo: Callback to get turbo P state
267 * @get_scaling: Callback to get frequency scaling factor
268 * @get_val: Callback to convert P state to actual MSR write value
269 * @get_vid: Callback to get VID data for Atom platforms
270 *
271 * Core and Atom CPU models have different way to get P State limits. This
272 * structure is used to store those callbacks.
273 */
274 struct pstate_funcs {
275 int (*get_max)(void);
276 int (*get_max_physical)(void);
277 int (*get_min)(void);
278 int (*get_turbo)(void);
279 int (*get_scaling)(void);
280 int (*get_aperf_mperf_shift)(void);
281 u64 (*get_val)(struct cpudata*, int pstate);
282 void (*get_vid)(struct cpudata *);
283 };
284
285 static struct pstate_funcs pstate_funcs __read_mostly;
286
287 static int hwp_active __read_mostly;
288 static int hwp_mode_bdw __read_mostly;
289 static bool per_cpu_limits __read_mostly;
290
291 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
292
293 #ifdef CONFIG_ACPI
294 static bool acpi_ppc;
295 #endif
296
297 static struct global_params global;
298
299 static DEFINE_MUTEX(intel_pstate_driver_lock);
300 static DEFINE_MUTEX(intel_pstate_limits_lock);
301
302 #ifdef CONFIG_ACPI
303
304 static bool intel_pstate_get_ppc_enable_status(void)
305 {
306 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
307 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
308 return true;
309
310 return acpi_ppc;
311 }
312
313 #ifdef CONFIG_ACPI_CPPC_LIB
314
315 /* The work item is needed to avoid CPU hotplug locking issues */
316 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
317 {
318 sched_set_itmt_support();
319 }
320
321 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
322
323 static void intel_pstate_set_itmt_prio(int cpu)
324 {
325 struct cppc_perf_caps cppc_perf;
326 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
327 int ret;
328
329 ret = cppc_get_perf_caps(cpu, &cppc_perf);
330 if (ret)
331 return;
332
333 /*
334 * The priorities can be set regardless of whether or not
335 * sched_set_itmt_support(true) has been called and it is valid to
336 * update them at any time after it has been called.
337 */
338 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
339
340 if (max_highest_perf <= min_highest_perf) {
341 if (cppc_perf.highest_perf > max_highest_perf)
342 max_highest_perf = cppc_perf.highest_perf;
343
344 if (cppc_perf.highest_perf < min_highest_perf)
345 min_highest_perf = cppc_perf.highest_perf;
346
347 if (max_highest_perf > min_highest_perf) {
348 /*
349 * This code can be run during CPU online under the
350 * CPU hotplug locks, so sched_set_itmt_support()
351 * cannot be called from here. Queue up a work item
352 * to invoke it.
353 */
354 schedule_work(&sched_itmt_work);
355 }
356 }
357 }
358 #else
359 static void intel_pstate_set_itmt_prio(int cpu)
360 {
361 }
362 #endif
363
364 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
365 {
366 struct cpudata *cpu;
367 int ret;
368 int i;
369
370 if (hwp_active) {
371 intel_pstate_set_itmt_prio(policy->cpu);
372 return;
373 }
374
375 if (!intel_pstate_get_ppc_enable_status())
376 return;
377
378 cpu = all_cpu_data[policy->cpu];
379
380 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
381 policy->cpu);
382 if (ret)
383 return;
384
385 /*
386 * Check if the control value in _PSS is for PERF_CTL MSR, which should
387 * guarantee that the states returned by it map to the states in our
388 * list directly.
389 */
390 if (cpu->acpi_perf_data.control_register.space_id !=
391 ACPI_ADR_SPACE_FIXED_HARDWARE)
392 goto err;
393
394 /*
395 * If there is only one entry _PSS, simply ignore _PSS and continue as
396 * usual without taking _PSS into account
397 */
398 if (cpu->acpi_perf_data.state_count < 2)
399 goto err;
400
401 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
402 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
403 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
404 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
405 (u32) cpu->acpi_perf_data.states[i].core_frequency,
406 (u32) cpu->acpi_perf_data.states[i].power,
407 (u32) cpu->acpi_perf_data.states[i].control);
408 }
409
410 /*
411 * The _PSS table doesn't contain whole turbo frequency range.
412 * This just contains +1 MHZ above the max non turbo frequency,
413 * with control value corresponding to max turbo ratio. But
414 * when cpufreq set policy is called, it will call with this
415 * max frequency, which will cause a reduced performance as
416 * this driver uses real max turbo frequency as the max
417 * frequency. So correct this frequency in _PSS table to
418 * correct max turbo frequency based on the turbo state.
419 * Also need to convert to MHz as _PSS freq is in MHz.
420 */
421 if (!global.turbo_disabled)
422 cpu->acpi_perf_data.states[0].core_frequency =
423 policy->cpuinfo.max_freq / 1000;
424 cpu->valid_pss_table = true;
425 pr_debug("_PPC limits will be enforced\n");
426
427 return;
428
429 err:
430 cpu->valid_pss_table = false;
431 acpi_processor_unregister_performance(policy->cpu);
432 }
433
434 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
435 {
436 struct cpudata *cpu;
437
438 cpu = all_cpu_data[policy->cpu];
439 if (!cpu->valid_pss_table)
440 return;
441
442 acpi_processor_unregister_performance(policy->cpu);
443 }
444 #else
445 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
446 {
447 }
448
449 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
450 {
451 }
452 #endif
453
454 static inline void update_turbo_state(void)
455 {
456 u64 misc_en;
457 struct cpudata *cpu;
458
459 cpu = all_cpu_data[0];
460 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
461 global.turbo_disabled =
462 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
463 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
464 }
465
466 static int min_perf_pct_min(void)
467 {
468 struct cpudata *cpu = all_cpu_data[0];
469 int turbo_pstate = cpu->pstate.turbo_pstate;
470
471 return turbo_pstate ?
472 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
473 }
474
475 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
476 {
477 u64 epb;
478 int ret;
479
480 if (!static_cpu_has(X86_FEATURE_EPB))
481 return -ENXIO;
482
483 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
484 if (ret)
485 return (s16)ret;
486
487 return (s16)(epb & 0x0f);
488 }
489
490 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
491 {
492 s16 epp;
493
494 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
495 /*
496 * When hwp_req_data is 0, means that caller didn't read
497 * MSR_HWP_REQUEST, so need to read and get EPP.
498 */
499 if (!hwp_req_data) {
500 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
501 &hwp_req_data);
502 if (epp)
503 return epp;
504 }
505 epp = (hwp_req_data >> 24) & 0xff;
506 } else {
507 /* When there is no EPP present, HWP uses EPB settings */
508 epp = intel_pstate_get_epb(cpu_data);
509 }
510
511 return epp;
512 }
513
514 static int intel_pstate_set_epb(int cpu, s16 pref)
515 {
516 u64 epb;
517 int ret;
518
519 if (!static_cpu_has(X86_FEATURE_EPB))
520 return -ENXIO;
521
522 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
523 if (ret)
524 return ret;
525
526 epb = (epb & ~0x0f) | pref;
527 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
528
529 return 0;
530 }
531
532 /*
533 * EPP/EPB display strings corresponding to EPP index in the
534 * energy_perf_strings[]
535 * index String
536 *-------------------------------------
537 * 0 default
538 * 1 performance
539 * 2 balance_performance
540 * 3 balance_power
541 * 4 power
542 */
543 static const char * const energy_perf_strings[] = {
544 "default",
545 "performance",
546 "balance_performance",
547 "balance_power",
548 "power",
549 NULL
550 };
551 static const unsigned int epp_values[] = {
552 HWP_EPP_PERFORMANCE,
553 HWP_EPP_BALANCE_PERFORMANCE,
554 HWP_EPP_BALANCE_POWERSAVE,
555 HWP_EPP_POWERSAVE
556 };
557
558 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
559 {
560 s16 epp;
561 int index = -EINVAL;
562
563 epp = intel_pstate_get_epp(cpu_data, 0);
564 if (epp < 0)
565 return epp;
566
567 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
568 if (epp == HWP_EPP_PERFORMANCE)
569 return 1;
570 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
571 return 2;
572 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
573 return 3;
574 else
575 return 4;
576 } else if (static_cpu_has(X86_FEATURE_EPB)) {
577 /*
578 * Range:
579 * 0x00-0x03 : Performance
580 * 0x04-0x07 : Balance performance
581 * 0x08-0x0B : Balance power
582 * 0x0C-0x0F : Power
583 * The EPB is a 4 bit value, but our ranges restrict the
584 * value which can be set. Here only using top two bits
585 * effectively.
586 */
587 index = (epp >> 2) + 1;
588 }
589
590 return index;
591 }
592
593 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
594 int pref_index)
595 {
596 int epp = -EINVAL;
597 int ret;
598
599 if (!pref_index)
600 epp = cpu_data->epp_default;
601
602 mutex_lock(&intel_pstate_limits_lock);
603
604 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
605 u64 value;
606
607 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
608 if (ret)
609 goto return_pref;
610
611 value &= ~GENMASK_ULL(31, 24);
612
613 if (epp == -EINVAL)
614 epp = epp_values[pref_index - 1];
615
616 value |= (u64)epp << 24;
617 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
618 } else {
619 if (epp == -EINVAL)
620 epp = (pref_index - 1) << 2;
621 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
622 }
623 return_pref:
624 mutex_unlock(&intel_pstate_limits_lock);
625
626 return ret;
627 }
628
629 static ssize_t show_energy_performance_available_preferences(
630 struct cpufreq_policy *policy, char *buf)
631 {
632 int i = 0;
633 int ret = 0;
634
635 while (energy_perf_strings[i] != NULL)
636 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
637
638 ret += sprintf(&buf[ret], "\n");
639
640 return ret;
641 }
642
643 cpufreq_freq_attr_ro(energy_performance_available_preferences);
644
645 static ssize_t store_energy_performance_preference(
646 struct cpufreq_policy *policy, const char *buf, size_t count)
647 {
648 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
649 char str_preference[21];
650 int ret, i = 0;
651
652 ret = sscanf(buf, "%20s", str_preference);
653 if (ret != 1)
654 return -EINVAL;
655
656 while (energy_perf_strings[i] != NULL) {
657 if (!strcmp(str_preference, energy_perf_strings[i])) {
658 intel_pstate_set_energy_pref_index(cpu_data, i);
659 return count;
660 }
661 ++i;
662 }
663
664 return -EINVAL;
665 }
666
667 static ssize_t show_energy_performance_preference(
668 struct cpufreq_policy *policy, char *buf)
669 {
670 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
671 int preference;
672
673 preference = intel_pstate_get_energy_pref_index(cpu_data);
674 if (preference < 0)
675 return preference;
676
677 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
678 }
679
680 cpufreq_freq_attr_rw(energy_performance_preference);
681
682 static struct freq_attr *hwp_cpufreq_attrs[] = {
683 &energy_performance_preference,
684 &energy_performance_available_preferences,
685 NULL,
686 };
687
688 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
689 int *current_max)
690 {
691 u64 cap;
692
693 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
694 if (global.no_turbo)
695 *current_max = HWP_GUARANTEED_PERF(cap);
696 else
697 *current_max = HWP_HIGHEST_PERF(cap);
698
699 *phy_max = HWP_HIGHEST_PERF(cap);
700 }
701
702 static void intel_pstate_hwp_set(unsigned int cpu)
703 {
704 struct cpudata *cpu_data = all_cpu_data[cpu];
705 int max, min;
706 u64 value;
707 s16 epp;
708
709 max = cpu_data->max_perf_ratio;
710 min = cpu_data->min_perf_ratio;
711
712 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
713 min = max;
714
715 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
716
717 value &= ~HWP_MIN_PERF(~0L);
718 value |= HWP_MIN_PERF(min);
719
720 value &= ~HWP_MAX_PERF(~0L);
721 value |= HWP_MAX_PERF(max);
722
723 if (cpu_data->epp_policy == cpu_data->policy)
724 goto skip_epp;
725
726 cpu_data->epp_policy = cpu_data->policy;
727
728 if (cpu_data->epp_saved >= 0) {
729 epp = cpu_data->epp_saved;
730 cpu_data->epp_saved = -EINVAL;
731 goto update_epp;
732 }
733
734 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
735 epp = intel_pstate_get_epp(cpu_data, value);
736 cpu_data->epp_powersave = epp;
737 /* If EPP read was failed, then don't try to write */
738 if (epp < 0)
739 goto skip_epp;
740
741 epp = 0;
742 } else {
743 /* skip setting EPP, when saved value is invalid */
744 if (cpu_data->epp_powersave < 0)
745 goto skip_epp;
746
747 /*
748 * No need to restore EPP when it is not zero. This
749 * means:
750 * - Policy is not changed
751 * - user has manually changed
752 * - Error reading EPB
753 */
754 epp = intel_pstate_get_epp(cpu_data, value);
755 if (epp)
756 goto skip_epp;
757
758 epp = cpu_data->epp_powersave;
759 }
760 update_epp:
761 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
762 value &= ~GENMASK_ULL(31, 24);
763 value |= (u64)epp << 24;
764 } else {
765 intel_pstate_set_epb(cpu, epp);
766 }
767 skip_epp:
768 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
769 }
770
771 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
772 {
773 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
774
775 if (!hwp_active)
776 return 0;
777
778 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
779
780 return 0;
781 }
782
783 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
784
785 static int intel_pstate_resume(struct cpufreq_policy *policy)
786 {
787 if (!hwp_active)
788 return 0;
789
790 mutex_lock(&intel_pstate_limits_lock);
791
792 if (policy->cpu == 0)
793 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
794
795 all_cpu_data[policy->cpu]->epp_policy = 0;
796 intel_pstate_hwp_set(policy->cpu);
797
798 mutex_unlock(&intel_pstate_limits_lock);
799
800 return 0;
801 }
802
803 static void intel_pstate_update_policies(void)
804 {
805 int cpu;
806
807 for_each_possible_cpu(cpu)
808 cpufreq_update_policy(cpu);
809 }
810
811 /************************** sysfs begin ************************/
812 #define show_one(file_name, object) \
813 static ssize_t show_##file_name \
814 (struct kobject *kobj, struct attribute *attr, char *buf) \
815 { \
816 return sprintf(buf, "%u\n", global.object); \
817 }
818
819 static ssize_t intel_pstate_show_status(char *buf);
820 static int intel_pstate_update_status(const char *buf, size_t size);
821
822 static ssize_t show_status(struct kobject *kobj,
823 struct attribute *attr, char *buf)
824 {
825 ssize_t ret;
826
827 mutex_lock(&intel_pstate_driver_lock);
828 ret = intel_pstate_show_status(buf);
829 mutex_unlock(&intel_pstate_driver_lock);
830
831 return ret;
832 }
833
834 static ssize_t store_status(struct kobject *a, struct attribute *b,
835 const char *buf, size_t count)
836 {
837 char *p = memchr(buf, '\n', count);
838 int ret;
839
840 mutex_lock(&intel_pstate_driver_lock);
841 ret = intel_pstate_update_status(buf, p ? p - buf : count);
842 mutex_unlock(&intel_pstate_driver_lock);
843
844 return ret < 0 ? ret : count;
845 }
846
847 static ssize_t show_turbo_pct(struct kobject *kobj,
848 struct attribute *attr, char *buf)
849 {
850 struct cpudata *cpu;
851 int total, no_turbo, turbo_pct;
852 uint32_t turbo_fp;
853
854 mutex_lock(&intel_pstate_driver_lock);
855
856 if (!intel_pstate_driver) {
857 mutex_unlock(&intel_pstate_driver_lock);
858 return -EAGAIN;
859 }
860
861 cpu = all_cpu_data[0];
862
863 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
864 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
865 turbo_fp = div_fp(no_turbo, total);
866 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
867
868 mutex_unlock(&intel_pstate_driver_lock);
869
870 return sprintf(buf, "%u\n", turbo_pct);
871 }
872
873 static ssize_t show_num_pstates(struct kobject *kobj,
874 struct attribute *attr, char *buf)
875 {
876 struct cpudata *cpu;
877 int total;
878
879 mutex_lock(&intel_pstate_driver_lock);
880
881 if (!intel_pstate_driver) {
882 mutex_unlock(&intel_pstate_driver_lock);
883 return -EAGAIN;
884 }
885
886 cpu = all_cpu_data[0];
887 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
888
889 mutex_unlock(&intel_pstate_driver_lock);
890
891 return sprintf(buf, "%u\n", total);
892 }
893
894 static ssize_t show_no_turbo(struct kobject *kobj,
895 struct attribute *attr, char *buf)
896 {
897 ssize_t ret;
898
899 mutex_lock(&intel_pstate_driver_lock);
900
901 if (!intel_pstate_driver) {
902 mutex_unlock(&intel_pstate_driver_lock);
903 return -EAGAIN;
904 }
905
906 update_turbo_state();
907 if (global.turbo_disabled)
908 ret = sprintf(buf, "%u\n", global.turbo_disabled);
909 else
910 ret = sprintf(buf, "%u\n", global.no_turbo);
911
912 mutex_unlock(&intel_pstate_driver_lock);
913
914 return ret;
915 }
916
917 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
918 const char *buf, size_t count)
919 {
920 unsigned int input;
921 int ret;
922
923 ret = sscanf(buf, "%u", &input);
924 if (ret != 1)
925 return -EINVAL;
926
927 mutex_lock(&intel_pstate_driver_lock);
928
929 if (!intel_pstate_driver) {
930 mutex_unlock(&intel_pstate_driver_lock);
931 return -EAGAIN;
932 }
933
934 mutex_lock(&intel_pstate_limits_lock);
935
936 update_turbo_state();
937 if (global.turbo_disabled) {
938 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
939 mutex_unlock(&intel_pstate_limits_lock);
940 mutex_unlock(&intel_pstate_driver_lock);
941 return -EPERM;
942 }
943
944 global.no_turbo = clamp_t(int, input, 0, 1);
945
946 if (global.no_turbo) {
947 struct cpudata *cpu = all_cpu_data[0];
948 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
949
950 /* Squash the global minimum into the permitted range. */
951 if (global.min_perf_pct > pct)
952 global.min_perf_pct = pct;
953 }
954
955 mutex_unlock(&intel_pstate_limits_lock);
956
957 intel_pstate_update_policies();
958
959 mutex_unlock(&intel_pstate_driver_lock);
960
961 return count;
962 }
963
964 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
965 const char *buf, size_t count)
966 {
967 unsigned int input;
968 int ret;
969
970 ret = sscanf(buf, "%u", &input);
971 if (ret != 1)
972 return -EINVAL;
973
974 mutex_lock(&intel_pstate_driver_lock);
975
976 if (!intel_pstate_driver) {
977 mutex_unlock(&intel_pstate_driver_lock);
978 return -EAGAIN;
979 }
980
981 mutex_lock(&intel_pstate_limits_lock);
982
983 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
984
985 mutex_unlock(&intel_pstate_limits_lock);
986
987 intel_pstate_update_policies();
988
989 mutex_unlock(&intel_pstate_driver_lock);
990
991 return count;
992 }
993
994 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
995 const char *buf, size_t count)
996 {
997 unsigned int input;
998 int ret;
999
1000 ret = sscanf(buf, "%u", &input);
1001 if (ret != 1)
1002 return -EINVAL;
1003
1004 mutex_lock(&intel_pstate_driver_lock);
1005
1006 if (!intel_pstate_driver) {
1007 mutex_unlock(&intel_pstate_driver_lock);
1008 return -EAGAIN;
1009 }
1010
1011 mutex_lock(&intel_pstate_limits_lock);
1012
1013 global.min_perf_pct = clamp_t(int, input,
1014 min_perf_pct_min(), global.max_perf_pct);
1015
1016 mutex_unlock(&intel_pstate_limits_lock);
1017
1018 intel_pstate_update_policies();
1019
1020 mutex_unlock(&intel_pstate_driver_lock);
1021
1022 return count;
1023 }
1024
1025 show_one(max_perf_pct, max_perf_pct);
1026 show_one(min_perf_pct, min_perf_pct);
1027
1028 define_one_global_rw(status);
1029 define_one_global_rw(no_turbo);
1030 define_one_global_rw(max_perf_pct);
1031 define_one_global_rw(min_perf_pct);
1032 define_one_global_ro(turbo_pct);
1033 define_one_global_ro(num_pstates);
1034
1035 static struct attribute *intel_pstate_attributes[] = {
1036 &status.attr,
1037 &no_turbo.attr,
1038 &turbo_pct.attr,
1039 &num_pstates.attr,
1040 NULL
1041 };
1042
1043 static const struct attribute_group intel_pstate_attr_group = {
1044 .attrs = intel_pstate_attributes,
1045 };
1046
1047 static void __init intel_pstate_sysfs_expose_params(void)
1048 {
1049 struct kobject *intel_pstate_kobject;
1050 int rc;
1051
1052 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1053 &cpu_subsys.dev_root->kobj);
1054 if (WARN_ON(!intel_pstate_kobject))
1055 return;
1056
1057 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1058 if (WARN_ON(rc))
1059 return;
1060
1061 /*
1062 * If per cpu limits are enforced there are no global limits, so
1063 * return without creating max/min_perf_pct attributes
1064 */
1065 if (per_cpu_limits)
1066 return;
1067
1068 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1069 WARN_ON(rc);
1070
1071 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1072 WARN_ON(rc);
1073
1074 }
1075 /************************** sysfs end ************************/
1076
1077 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1078 {
1079 /* First disable HWP notification interrupt as we don't process them */
1080 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1081 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1082
1083 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1084 cpudata->epp_policy = 0;
1085 if (cpudata->epp_default == -EINVAL)
1086 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1087 }
1088
1089 #define MSR_IA32_POWER_CTL_BIT_EE 19
1090
1091 /* Disable energy efficiency optimization */
1092 static void intel_pstate_disable_ee(int cpu)
1093 {
1094 u64 power_ctl;
1095 int ret;
1096
1097 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1098 if (ret)
1099 return;
1100
1101 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1102 pr_info("Disabling energy efficiency optimization\n");
1103 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1104 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1105 }
1106 }
1107
1108 static int atom_get_min_pstate(void)
1109 {
1110 u64 value;
1111
1112 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1113 return (value >> 8) & 0x7F;
1114 }
1115
1116 static int atom_get_max_pstate(void)
1117 {
1118 u64 value;
1119
1120 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1121 return (value >> 16) & 0x7F;
1122 }
1123
1124 static int atom_get_turbo_pstate(void)
1125 {
1126 u64 value;
1127
1128 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1129 return value & 0x7F;
1130 }
1131
1132 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1133 {
1134 u64 val;
1135 int32_t vid_fp;
1136 u32 vid;
1137
1138 val = (u64)pstate << 8;
1139 if (global.no_turbo && !global.turbo_disabled)
1140 val |= (u64)1 << 32;
1141
1142 vid_fp = cpudata->vid.min + mul_fp(
1143 int_tofp(pstate - cpudata->pstate.min_pstate),
1144 cpudata->vid.ratio);
1145
1146 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1147 vid = ceiling_fp(vid_fp);
1148
1149 if (pstate > cpudata->pstate.max_pstate)
1150 vid = cpudata->vid.turbo;
1151
1152 return val | vid;
1153 }
1154
1155 static int silvermont_get_scaling(void)
1156 {
1157 u64 value;
1158 int i;
1159 /* Defined in Table 35-6 from SDM (Sept 2015) */
1160 static int silvermont_freq_table[] = {
1161 83300, 100000, 133300, 116700, 80000};
1162
1163 rdmsrl(MSR_FSB_FREQ, value);
1164 i = value & 0x7;
1165 WARN_ON(i > 4);
1166
1167 return silvermont_freq_table[i];
1168 }
1169
1170 static int airmont_get_scaling(void)
1171 {
1172 u64 value;
1173 int i;
1174 /* Defined in Table 35-10 from SDM (Sept 2015) */
1175 static int airmont_freq_table[] = {
1176 83300, 100000, 133300, 116700, 80000,
1177 93300, 90000, 88900, 87500};
1178
1179 rdmsrl(MSR_FSB_FREQ, value);
1180 i = value & 0xF;
1181 WARN_ON(i > 8);
1182
1183 return airmont_freq_table[i];
1184 }
1185
1186 static void atom_get_vid(struct cpudata *cpudata)
1187 {
1188 u64 value;
1189
1190 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1191 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1192 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1193 cpudata->vid.ratio = div_fp(
1194 cpudata->vid.max - cpudata->vid.min,
1195 int_tofp(cpudata->pstate.max_pstate -
1196 cpudata->pstate.min_pstate));
1197
1198 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1199 cpudata->vid.turbo = value & 0x7f;
1200 }
1201
1202 static int core_get_min_pstate(void)
1203 {
1204 u64 value;
1205
1206 rdmsrl(MSR_PLATFORM_INFO, value);
1207 return (value >> 40) & 0xFF;
1208 }
1209
1210 static int core_get_max_pstate_physical(void)
1211 {
1212 u64 value;
1213
1214 rdmsrl(MSR_PLATFORM_INFO, value);
1215 return (value >> 8) & 0xFF;
1216 }
1217
1218 static int core_get_tdp_ratio(u64 plat_info)
1219 {
1220 /* Check how many TDP levels present */
1221 if (plat_info & 0x600000000) {
1222 u64 tdp_ctrl;
1223 u64 tdp_ratio;
1224 int tdp_msr;
1225 int err;
1226
1227 /* Get the TDP level (0, 1, 2) to get ratios */
1228 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1229 if (err)
1230 return err;
1231
1232 /* TDP MSR are continuous starting at 0x648 */
1233 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1234 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1235 if (err)
1236 return err;
1237
1238 /* For level 1 and 2, bits[23:16] contain the ratio */
1239 if (tdp_ctrl & 0x03)
1240 tdp_ratio >>= 16;
1241
1242 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1243 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1244
1245 return (int)tdp_ratio;
1246 }
1247
1248 return -ENXIO;
1249 }
1250
1251 static int core_get_max_pstate(void)
1252 {
1253 u64 tar;
1254 u64 plat_info;
1255 int max_pstate;
1256 int tdp_ratio;
1257 int err;
1258
1259 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1260 max_pstate = (plat_info >> 8) & 0xFF;
1261
1262 tdp_ratio = core_get_tdp_ratio(plat_info);
1263 if (tdp_ratio <= 0)
1264 return max_pstate;
1265
1266 if (hwp_active) {
1267 /* Turbo activation ratio is not used on HWP platforms */
1268 return tdp_ratio;
1269 }
1270
1271 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1272 if (!err) {
1273 int tar_levels;
1274
1275 /* Do some sanity checking for safety */
1276 tar_levels = tar & 0xff;
1277 if (tdp_ratio - 1 == tar_levels) {
1278 max_pstate = tar_levels;
1279 pr_debug("max_pstate=TAC %x\n", max_pstate);
1280 }
1281 }
1282
1283 return max_pstate;
1284 }
1285
1286 static int core_get_turbo_pstate(void)
1287 {
1288 u64 value;
1289 int nont, ret;
1290
1291 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1292 nont = core_get_max_pstate();
1293 ret = (value) & 255;
1294 if (ret <= nont)
1295 ret = nont;
1296 return ret;
1297 }
1298
1299 static inline int core_get_scaling(void)
1300 {
1301 return 100000;
1302 }
1303
1304 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1305 {
1306 u64 val;
1307
1308 val = (u64)pstate << 8;
1309 if (global.no_turbo && !global.turbo_disabled)
1310 val |= (u64)1 << 32;
1311
1312 return val;
1313 }
1314
1315 static int knl_get_aperf_mperf_shift(void)
1316 {
1317 return 10;
1318 }
1319
1320 static int knl_get_turbo_pstate(void)
1321 {
1322 u64 value;
1323 int nont, ret;
1324
1325 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1326 nont = core_get_max_pstate();
1327 ret = (((value) >> 8) & 0xFF);
1328 if (ret <= nont)
1329 ret = nont;
1330 return ret;
1331 }
1332
1333 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1334 {
1335 return global.no_turbo || global.turbo_disabled ?
1336 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1337 }
1338
1339 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1340 {
1341 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1342 cpu->pstate.current_pstate = pstate;
1343 /*
1344 * Generally, there is no guarantee that this code will always run on
1345 * the CPU being updated, so force the register update to run on the
1346 * right CPU.
1347 */
1348 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1349 pstate_funcs.get_val(cpu, pstate));
1350 }
1351
1352 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1353 {
1354 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1355 }
1356
1357 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1358 {
1359 int pstate;
1360
1361 update_turbo_state();
1362 pstate = intel_pstate_get_base_pstate(cpu);
1363 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1364 intel_pstate_set_pstate(cpu, pstate);
1365 }
1366
1367 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1368 {
1369 cpu->pstate.min_pstate = pstate_funcs.get_min();
1370 cpu->pstate.max_pstate = pstate_funcs.get_max();
1371 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1372 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1373 cpu->pstate.scaling = pstate_funcs.get_scaling();
1374 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1375
1376 if (hwp_active && !hwp_mode_bdw) {
1377 unsigned int phy_max, current_max;
1378
1379 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1380 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1381 } else {
1382 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1383 }
1384
1385 if (pstate_funcs.get_aperf_mperf_shift)
1386 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1387
1388 if (pstate_funcs.get_vid)
1389 pstate_funcs.get_vid(cpu);
1390
1391 intel_pstate_set_min_pstate(cpu);
1392 }
1393
1394 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1395 {
1396 struct sample *sample = &cpu->sample;
1397
1398 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1399 }
1400
1401 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1402 {
1403 u64 aperf, mperf;
1404 unsigned long flags;
1405 u64 tsc;
1406
1407 local_irq_save(flags);
1408 rdmsrl(MSR_IA32_APERF, aperf);
1409 rdmsrl(MSR_IA32_MPERF, mperf);
1410 tsc = rdtsc();
1411 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1412 local_irq_restore(flags);
1413 return false;
1414 }
1415 local_irq_restore(flags);
1416
1417 cpu->last_sample_time = cpu->sample.time;
1418 cpu->sample.time = time;
1419 cpu->sample.aperf = aperf;
1420 cpu->sample.mperf = mperf;
1421 cpu->sample.tsc = tsc;
1422 cpu->sample.aperf -= cpu->prev_aperf;
1423 cpu->sample.mperf -= cpu->prev_mperf;
1424 cpu->sample.tsc -= cpu->prev_tsc;
1425
1426 cpu->prev_aperf = aperf;
1427 cpu->prev_mperf = mperf;
1428 cpu->prev_tsc = tsc;
1429 /*
1430 * First time this function is invoked in a given cycle, all of the
1431 * previous sample data fields are equal to zero or stale and they must
1432 * be populated with meaningful numbers for things to work, so assume
1433 * that sample.time will always be reset before setting the utilization
1434 * update hook and make the caller skip the sample then.
1435 */
1436 if (cpu->last_sample_time) {
1437 intel_pstate_calc_avg_perf(cpu);
1438 return true;
1439 }
1440 return false;
1441 }
1442
1443 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1444 {
1445 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1446 }
1447
1448 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1449 {
1450 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1451 cpu->sample.core_avg_perf);
1452 }
1453
1454 static inline int32_t get_target_pstate(struct cpudata *cpu)
1455 {
1456 struct sample *sample = &cpu->sample;
1457 int32_t busy_frac, boost;
1458 int target, avg_pstate;
1459
1460 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1461 sample->tsc);
1462
1463 boost = cpu->iowait_boost;
1464 cpu->iowait_boost >>= 1;
1465
1466 if (busy_frac < boost)
1467 busy_frac = boost;
1468
1469 sample->busy_scaled = busy_frac * 100;
1470
1471 target = global.no_turbo || global.turbo_disabled ?
1472 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1473 target += target >> 2;
1474 target = mul_fp(target, busy_frac);
1475 if (target < cpu->pstate.min_pstate)
1476 target = cpu->pstate.min_pstate;
1477
1478 /*
1479 * If the average P-state during the previous cycle was higher than the
1480 * current target, add 50% of the difference to the target to reduce
1481 * possible performance oscillations and offset possible performance
1482 * loss related to moving the workload from one CPU to another within
1483 * a package/module.
1484 */
1485 avg_pstate = get_avg_pstate(cpu);
1486 if (avg_pstate > target)
1487 target += (avg_pstate - target) >> 1;
1488
1489 return target;
1490 }
1491
1492 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1493 {
1494 int max_pstate = intel_pstate_get_base_pstate(cpu);
1495 int min_pstate;
1496
1497 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1498 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1499 return clamp_t(int, pstate, min_pstate, max_pstate);
1500 }
1501
1502 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1503 {
1504 if (pstate == cpu->pstate.current_pstate)
1505 return;
1506
1507 cpu->pstate.current_pstate = pstate;
1508 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1509 }
1510
1511 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1512 {
1513 int from = cpu->pstate.current_pstate;
1514 struct sample *sample;
1515 int target_pstate;
1516
1517 update_turbo_state();
1518
1519 target_pstate = get_target_pstate(cpu);
1520 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1521 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1522 intel_pstate_update_pstate(cpu, target_pstate);
1523
1524 sample = &cpu->sample;
1525 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1526 fp_toint(sample->busy_scaled),
1527 from,
1528 cpu->pstate.current_pstate,
1529 sample->mperf,
1530 sample->aperf,
1531 sample->tsc,
1532 get_avg_frequency(cpu),
1533 fp_toint(cpu->iowait_boost * 100));
1534 }
1535
1536 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1537 unsigned int flags)
1538 {
1539 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1540 u64 delta_ns;
1541
1542 /* Don't allow remote callbacks */
1543 if (smp_processor_id() != cpu->cpu)
1544 return;
1545
1546 if (flags & SCHED_CPUFREQ_IOWAIT) {
1547 cpu->iowait_boost = int_tofp(1);
1548 cpu->last_update = time;
1549 /*
1550 * The last time the busy was 100% so P-state was max anyway
1551 * so avoid overhead of computation.
1552 */
1553 if (fp_toint(cpu->sample.busy_scaled) == 100)
1554 return;
1555
1556 goto set_pstate;
1557 } else if (cpu->iowait_boost) {
1558 /* Clear iowait_boost if the CPU may have been idle. */
1559 delta_ns = time - cpu->last_update;
1560 if (delta_ns > TICK_NSEC)
1561 cpu->iowait_boost = 0;
1562 }
1563 cpu->last_update = time;
1564 delta_ns = time - cpu->sample.time;
1565 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1566 return;
1567
1568 set_pstate:
1569 if (intel_pstate_sample(cpu, time))
1570 intel_pstate_adjust_pstate(cpu);
1571 }
1572
1573 static struct pstate_funcs core_funcs = {
1574 .get_max = core_get_max_pstate,
1575 .get_max_physical = core_get_max_pstate_physical,
1576 .get_min = core_get_min_pstate,
1577 .get_turbo = core_get_turbo_pstate,
1578 .get_scaling = core_get_scaling,
1579 .get_val = core_get_val,
1580 };
1581
1582 static const struct pstate_funcs silvermont_funcs = {
1583 .get_max = atom_get_max_pstate,
1584 .get_max_physical = atom_get_max_pstate,
1585 .get_min = atom_get_min_pstate,
1586 .get_turbo = atom_get_turbo_pstate,
1587 .get_val = atom_get_val,
1588 .get_scaling = silvermont_get_scaling,
1589 .get_vid = atom_get_vid,
1590 };
1591
1592 static const struct pstate_funcs airmont_funcs = {
1593 .get_max = atom_get_max_pstate,
1594 .get_max_physical = atom_get_max_pstate,
1595 .get_min = atom_get_min_pstate,
1596 .get_turbo = atom_get_turbo_pstate,
1597 .get_val = atom_get_val,
1598 .get_scaling = airmont_get_scaling,
1599 .get_vid = atom_get_vid,
1600 };
1601
1602 static const struct pstate_funcs knl_funcs = {
1603 .get_max = core_get_max_pstate,
1604 .get_max_physical = core_get_max_pstate_physical,
1605 .get_min = core_get_min_pstate,
1606 .get_turbo = knl_get_turbo_pstate,
1607 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1608 .get_scaling = core_get_scaling,
1609 .get_val = core_get_val,
1610 };
1611
1612 static const struct pstate_funcs bxt_funcs = {
1613 .get_max = core_get_max_pstate,
1614 .get_max_physical = core_get_max_pstate_physical,
1615 .get_min = core_get_min_pstate,
1616 .get_turbo = core_get_turbo_pstate,
1617 .get_scaling = core_get_scaling,
1618 .get_val = core_get_val,
1619 };
1620
1621 #define ICPU(model, policy) \
1622 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1623 (unsigned long)&policy }
1624
1625 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1626 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1627 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1628 ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
1629 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1630 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1631 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1632 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1633 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1634 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1635 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1636 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1637 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1638 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1639 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1640 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1641 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1642 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1643 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1644 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs),
1645 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, bxt_funcs),
1646 {}
1647 };
1648 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1649
1650 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1651 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1652 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1653 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1654 {}
1655 };
1656
1657 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1658 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1659 {}
1660 };
1661
1662 static int intel_pstate_init_cpu(unsigned int cpunum)
1663 {
1664 struct cpudata *cpu;
1665
1666 cpu = all_cpu_data[cpunum];
1667
1668 if (!cpu) {
1669 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1670 if (!cpu)
1671 return -ENOMEM;
1672
1673 all_cpu_data[cpunum] = cpu;
1674
1675 cpu->epp_default = -EINVAL;
1676 cpu->epp_powersave = -EINVAL;
1677 cpu->epp_saved = -EINVAL;
1678 }
1679
1680 cpu = all_cpu_data[cpunum];
1681
1682 cpu->cpu = cpunum;
1683
1684 if (hwp_active) {
1685 const struct x86_cpu_id *id;
1686
1687 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1688 if (id)
1689 intel_pstate_disable_ee(cpunum);
1690
1691 intel_pstate_hwp_enable(cpu);
1692 }
1693
1694 intel_pstate_get_cpu_pstates(cpu);
1695
1696 pr_debug("controlling: cpu %d\n", cpunum);
1697
1698 return 0;
1699 }
1700
1701 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1702 {
1703 struct cpudata *cpu = all_cpu_data[cpu_num];
1704
1705 if (hwp_active)
1706 return;
1707
1708 if (cpu->update_util_set)
1709 return;
1710
1711 /* Prevent intel_pstate_update_util() from using stale data. */
1712 cpu->sample.time = 0;
1713 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1714 intel_pstate_update_util);
1715 cpu->update_util_set = true;
1716 }
1717
1718 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1719 {
1720 struct cpudata *cpu_data = all_cpu_data[cpu];
1721
1722 if (!cpu_data->update_util_set)
1723 return;
1724
1725 cpufreq_remove_update_util_hook(cpu);
1726 cpu_data->update_util_set = false;
1727 synchronize_sched();
1728 }
1729
1730 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1731 {
1732 return global.turbo_disabled || global.no_turbo ?
1733 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1734 }
1735
1736 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1737 struct cpudata *cpu)
1738 {
1739 int max_freq = intel_pstate_get_max_freq(cpu);
1740 int32_t max_policy_perf, min_policy_perf;
1741 int max_state, turbo_max;
1742
1743 /*
1744 * HWP needs some special consideration, because on BDX the
1745 * HWP_REQUEST uses abstract value to represent performance
1746 * rather than pure ratios.
1747 */
1748 if (hwp_active) {
1749 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1750 } else {
1751 max_state = intel_pstate_get_base_pstate(cpu);
1752 turbo_max = cpu->pstate.turbo_pstate;
1753 }
1754
1755 max_policy_perf = max_state * policy->max / max_freq;
1756 if (policy->max == policy->min) {
1757 min_policy_perf = max_policy_perf;
1758 } else {
1759 min_policy_perf = max_state * policy->min / max_freq;
1760 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1761 0, max_policy_perf);
1762 }
1763
1764 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1765 policy->cpu, max_state,
1766 min_policy_perf, max_policy_perf);
1767
1768 /* Normalize user input to [min_perf, max_perf] */
1769 if (per_cpu_limits) {
1770 cpu->min_perf_ratio = min_policy_perf;
1771 cpu->max_perf_ratio = max_policy_perf;
1772 } else {
1773 int32_t global_min, global_max;
1774
1775 /* Global limits are in percent of the maximum turbo P-state. */
1776 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1777 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1778 global_min = clamp_t(int32_t, global_min, 0, global_max);
1779
1780 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1781 global_min, global_max);
1782
1783 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1784 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1785 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1786 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1787
1788 /* Make sure min_perf <= max_perf */
1789 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1790 cpu->max_perf_ratio);
1791
1792 }
1793 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1794 cpu->max_perf_ratio,
1795 cpu->min_perf_ratio);
1796 }
1797
1798 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1799 {
1800 struct cpudata *cpu;
1801
1802 if (!policy->cpuinfo.max_freq)
1803 return -ENODEV;
1804
1805 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1806 policy->cpuinfo.max_freq, policy->max);
1807
1808 cpu = all_cpu_data[policy->cpu];
1809 cpu->policy = policy->policy;
1810
1811 mutex_lock(&intel_pstate_limits_lock);
1812
1813 intel_pstate_update_perf_limits(policy, cpu);
1814
1815 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1816 /*
1817 * NOHZ_FULL CPUs need this as the governor callback may not
1818 * be invoked on them.
1819 */
1820 intel_pstate_clear_update_util_hook(policy->cpu);
1821 intel_pstate_max_within_limits(cpu);
1822 } else {
1823 intel_pstate_set_update_util_hook(policy->cpu);
1824 }
1825
1826 if (hwp_active)
1827 intel_pstate_hwp_set(policy->cpu);
1828
1829 mutex_unlock(&intel_pstate_limits_lock);
1830
1831 return 0;
1832 }
1833
1834 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1835 struct cpudata *cpu)
1836 {
1837 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1838 policy->max < policy->cpuinfo.max_freq &&
1839 policy->max > cpu->pstate.max_freq) {
1840 pr_debug("policy->max > max non turbo frequency\n");
1841 policy->max = policy->cpuinfo.max_freq;
1842 }
1843 }
1844
1845 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1846 {
1847 struct cpudata *cpu = all_cpu_data[policy->cpu];
1848
1849 update_turbo_state();
1850 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1851 intel_pstate_get_max_freq(cpu));
1852
1853 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1854 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1855 return -EINVAL;
1856
1857 intel_pstate_adjust_policy_max(policy, cpu);
1858
1859 return 0;
1860 }
1861
1862 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1863 {
1864 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
1865 }
1866
1867 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1868 {
1869 pr_debug("CPU %d exiting\n", policy->cpu);
1870
1871 intel_pstate_clear_update_util_hook(policy->cpu);
1872 if (hwp_active)
1873 intel_pstate_hwp_save_state(policy);
1874 else
1875 intel_cpufreq_stop_cpu(policy);
1876 }
1877
1878 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1879 {
1880 intel_pstate_exit_perf_limits(policy);
1881
1882 policy->fast_switch_possible = false;
1883
1884 return 0;
1885 }
1886
1887 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
1888 {
1889 struct cpudata *cpu;
1890 int rc;
1891
1892 rc = intel_pstate_init_cpu(policy->cpu);
1893 if (rc)
1894 return rc;
1895
1896 cpu = all_cpu_data[policy->cpu];
1897
1898 cpu->max_perf_ratio = 0xFF;
1899 cpu->min_perf_ratio = 0;
1900
1901 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1902 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1903
1904 /* cpuinfo and default policy values */
1905 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1906 update_turbo_state();
1907 policy->cpuinfo.max_freq = global.turbo_disabled ?
1908 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1909 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1910
1911 intel_pstate_init_acpi_perf_limits(policy);
1912
1913 policy->fast_switch_possible = true;
1914
1915 return 0;
1916 }
1917
1918 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1919 {
1920 int ret = __intel_pstate_cpu_init(policy);
1921
1922 if (ret)
1923 return ret;
1924
1925 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
1926 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1927 else
1928 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1929
1930 return 0;
1931 }
1932
1933 static struct cpufreq_driver intel_pstate = {
1934 .flags = CPUFREQ_CONST_LOOPS,
1935 .verify = intel_pstate_verify_policy,
1936 .setpolicy = intel_pstate_set_policy,
1937 .suspend = intel_pstate_hwp_save_state,
1938 .resume = intel_pstate_resume,
1939 .init = intel_pstate_cpu_init,
1940 .exit = intel_pstate_cpu_exit,
1941 .stop_cpu = intel_pstate_stop_cpu,
1942 .name = "intel_pstate",
1943 };
1944
1945 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
1946 {
1947 struct cpudata *cpu = all_cpu_data[policy->cpu];
1948
1949 update_turbo_state();
1950 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1951 intel_pstate_get_max_freq(cpu));
1952
1953 intel_pstate_adjust_policy_max(policy, cpu);
1954
1955 intel_pstate_update_perf_limits(policy, cpu);
1956
1957 return 0;
1958 }
1959
1960 static int intel_cpufreq_target(struct cpufreq_policy *policy,
1961 unsigned int target_freq,
1962 unsigned int relation)
1963 {
1964 struct cpudata *cpu = all_cpu_data[policy->cpu];
1965 struct cpufreq_freqs freqs;
1966 int target_pstate;
1967
1968 update_turbo_state();
1969
1970 freqs.old = policy->cur;
1971 freqs.new = target_freq;
1972
1973 cpufreq_freq_transition_begin(policy, &freqs);
1974 switch (relation) {
1975 case CPUFREQ_RELATION_L:
1976 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
1977 break;
1978 case CPUFREQ_RELATION_H:
1979 target_pstate = freqs.new / cpu->pstate.scaling;
1980 break;
1981 default:
1982 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
1983 break;
1984 }
1985 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1986 if (target_pstate != cpu->pstate.current_pstate) {
1987 cpu->pstate.current_pstate = target_pstate;
1988 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
1989 pstate_funcs.get_val(cpu, target_pstate));
1990 }
1991 freqs.new = target_pstate * cpu->pstate.scaling;
1992 cpufreq_freq_transition_end(policy, &freqs, false);
1993
1994 return 0;
1995 }
1996
1997 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
1998 unsigned int target_freq)
1999 {
2000 struct cpudata *cpu = all_cpu_data[policy->cpu];
2001 int target_pstate;
2002
2003 update_turbo_state();
2004
2005 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2006 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2007 intel_pstate_update_pstate(cpu, target_pstate);
2008 return target_pstate * cpu->pstate.scaling;
2009 }
2010
2011 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2012 {
2013 int ret = __intel_pstate_cpu_init(policy);
2014
2015 if (ret)
2016 return ret;
2017
2018 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2019 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2020 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2021 policy->cur = policy->cpuinfo.min_freq;
2022
2023 return 0;
2024 }
2025
2026 static struct cpufreq_driver intel_cpufreq = {
2027 .flags = CPUFREQ_CONST_LOOPS,
2028 .verify = intel_cpufreq_verify_policy,
2029 .target = intel_cpufreq_target,
2030 .fast_switch = intel_cpufreq_fast_switch,
2031 .init = intel_cpufreq_cpu_init,
2032 .exit = intel_pstate_cpu_exit,
2033 .stop_cpu = intel_cpufreq_stop_cpu,
2034 .name = "intel_cpufreq",
2035 };
2036
2037 static struct cpufreq_driver *default_driver = &intel_pstate;
2038
2039 static void intel_pstate_driver_cleanup(void)
2040 {
2041 unsigned int cpu;
2042
2043 get_online_cpus();
2044 for_each_online_cpu(cpu) {
2045 if (all_cpu_data[cpu]) {
2046 if (intel_pstate_driver == &intel_pstate)
2047 intel_pstate_clear_update_util_hook(cpu);
2048
2049 kfree(all_cpu_data[cpu]);
2050 all_cpu_data[cpu] = NULL;
2051 }
2052 }
2053 put_online_cpus();
2054 intel_pstate_driver = NULL;
2055 }
2056
2057 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2058 {
2059 int ret;
2060
2061 memset(&global, 0, sizeof(global));
2062 global.max_perf_pct = 100;
2063
2064 intel_pstate_driver = driver;
2065 ret = cpufreq_register_driver(intel_pstate_driver);
2066 if (ret) {
2067 intel_pstate_driver_cleanup();
2068 return ret;
2069 }
2070
2071 global.min_perf_pct = min_perf_pct_min();
2072
2073 return 0;
2074 }
2075
2076 static int intel_pstate_unregister_driver(void)
2077 {
2078 if (hwp_active)
2079 return -EBUSY;
2080
2081 cpufreq_unregister_driver(intel_pstate_driver);
2082 intel_pstate_driver_cleanup();
2083
2084 return 0;
2085 }
2086
2087 static ssize_t intel_pstate_show_status(char *buf)
2088 {
2089 if (!intel_pstate_driver)
2090 return sprintf(buf, "off\n");
2091
2092 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2093 "active" : "passive");
2094 }
2095
2096 static int intel_pstate_update_status(const char *buf, size_t size)
2097 {
2098 int ret;
2099
2100 if (size == 3 && !strncmp(buf, "off", size))
2101 return intel_pstate_driver ?
2102 intel_pstate_unregister_driver() : -EINVAL;
2103
2104 if (size == 6 && !strncmp(buf, "active", size)) {
2105 if (intel_pstate_driver) {
2106 if (intel_pstate_driver == &intel_pstate)
2107 return 0;
2108
2109 ret = intel_pstate_unregister_driver();
2110 if (ret)
2111 return ret;
2112 }
2113
2114 return intel_pstate_register_driver(&intel_pstate);
2115 }
2116
2117 if (size == 7 && !strncmp(buf, "passive", size)) {
2118 if (intel_pstate_driver) {
2119 if (intel_pstate_driver == &intel_cpufreq)
2120 return 0;
2121
2122 ret = intel_pstate_unregister_driver();
2123 if (ret)
2124 return ret;
2125 }
2126
2127 return intel_pstate_register_driver(&intel_cpufreq);
2128 }
2129
2130 return -EINVAL;
2131 }
2132
2133 static int no_load __initdata;
2134 static int no_hwp __initdata;
2135 static int hwp_only __initdata;
2136 static unsigned int force_load __initdata;
2137
2138 static int __init intel_pstate_msrs_not_valid(void)
2139 {
2140 if (!pstate_funcs.get_max() ||
2141 !pstate_funcs.get_min() ||
2142 !pstate_funcs.get_turbo())
2143 return -ENODEV;
2144
2145 return 0;
2146 }
2147
2148 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2149 {
2150 pstate_funcs.get_max = funcs->get_max;
2151 pstate_funcs.get_max_physical = funcs->get_max_physical;
2152 pstate_funcs.get_min = funcs->get_min;
2153 pstate_funcs.get_turbo = funcs->get_turbo;
2154 pstate_funcs.get_scaling = funcs->get_scaling;
2155 pstate_funcs.get_val = funcs->get_val;
2156 pstate_funcs.get_vid = funcs->get_vid;
2157 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2158 }
2159
2160 #ifdef CONFIG_ACPI
2161
2162 static bool __init intel_pstate_no_acpi_pss(void)
2163 {
2164 int i;
2165
2166 for_each_possible_cpu(i) {
2167 acpi_status status;
2168 union acpi_object *pss;
2169 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2170 struct acpi_processor *pr = per_cpu(processors, i);
2171
2172 if (!pr)
2173 continue;
2174
2175 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2176 if (ACPI_FAILURE(status))
2177 continue;
2178
2179 pss = buffer.pointer;
2180 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2181 kfree(pss);
2182 return false;
2183 }
2184
2185 kfree(pss);
2186 }
2187
2188 return true;
2189 }
2190
2191 static bool __init intel_pstate_no_acpi_pcch(void)
2192 {
2193 acpi_status status;
2194 acpi_handle handle;
2195
2196 status = acpi_get_handle(NULL, "\\_SB", &handle);
2197 if (ACPI_FAILURE(status))
2198 return true;
2199
2200 return !acpi_has_method(handle, "PCCH");
2201 }
2202
2203 static bool __init intel_pstate_has_acpi_ppc(void)
2204 {
2205 int i;
2206
2207 for_each_possible_cpu(i) {
2208 struct acpi_processor *pr = per_cpu(processors, i);
2209
2210 if (!pr)
2211 continue;
2212 if (acpi_has_method(pr->handle, "_PPC"))
2213 return true;
2214 }
2215 return false;
2216 }
2217
2218 enum {
2219 PSS,
2220 PPC,
2221 };
2222
2223 /* Hardware vendor-specific info that has its own power management modes */
2224 static struct acpi_platform_list plat_info[] __initdata = {
2225 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2226 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2227 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2228 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2229 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2230 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2231 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2232 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2233 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2234 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2235 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2236 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2237 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2238 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2239 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2240 { } /* End */
2241 };
2242
2243 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2244 {
2245 const struct x86_cpu_id *id;
2246 u64 misc_pwr;
2247 int idx;
2248
2249 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2250 if (id) {
2251 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2252 if ( misc_pwr & (1 << 8))
2253 return true;
2254 }
2255
2256 idx = acpi_match_platform_list(plat_info);
2257 if (idx < 0)
2258 return false;
2259
2260 switch (plat_info[idx].data) {
2261 case PSS:
2262 if (!intel_pstate_no_acpi_pss())
2263 return false;
2264
2265 return intel_pstate_no_acpi_pcch();
2266 case PPC:
2267 return intel_pstate_has_acpi_ppc() && !force_load;
2268 }
2269
2270 return false;
2271 }
2272
2273 static void intel_pstate_request_control_from_smm(void)
2274 {
2275 /*
2276 * It may be unsafe to request P-states control from SMM if _PPC support
2277 * has not been enabled.
2278 */
2279 if (acpi_ppc)
2280 acpi_processor_pstate_control();
2281 }
2282 #else /* CONFIG_ACPI not enabled */
2283 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2284 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2285 static inline void intel_pstate_request_control_from_smm(void) {}
2286 #endif /* CONFIG_ACPI */
2287
2288 #define INTEL_PSTATE_HWP_BROADWELL 0x01
2289
2290 #define ICPU_HWP(model, hwp_mode) \
2291 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2292
2293 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2294 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2295 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2296 ICPU_HWP(X86_MODEL_ANY, 0),
2297 {}
2298 };
2299
2300 static int __init intel_pstate_init(void)
2301 {
2302 const struct x86_cpu_id *id;
2303 int rc;
2304
2305 if (no_load)
2306 return -ENODEV;
2307
2308 id = x86_match_cpu(hwp_support_ids);
2309 if (id) {
2310 copy_cpu_funcs(&core_funcs);
2311 if (!no_hwp) {
2312 hwp_active++;
2313 hwp_mode_bdw = id->driver_data;
2314 intel_pstate.attr = hwp_cpufreq_attrs;
2315 goto hwp_cpu_matched;
2316 }
2317 } else {
2318 id = x86_match_cpu(intel_pstate_cpu_ids);
2319 if (!id)
2320 return -ENODEV;
2321
2322 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2323 }
2324
2325 if (intel_pstate_msrs_not_valid())
2326 return -ENODEV;
2327
2328 hwp_cpu_matched:
2329 /*
2330 * The Intel pstate driver will be ignored if the platform
2331 * firmware has its own power management modes.
2332 */
2333 if (intel_pstate_platform_pwr_mgmt_exists())
2334 return -ENODEV;
2335
2336 if (!hwp_active && hwp_only)
2337 return -ENOTSUPP;
2338
2339 pr_info("Intel P-state driver initializing\n");
2340
2341 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2342 if (!all_cpu_data)
2343 return -ENOMEM;
2344
2345 intel_pstate_request_control_from_smm();
2346
2347 intel_pstate_sysfs_expose_params();
2348
2349 mutex_lock(&intel_pstate_driver_lock);
2350 rc = intel_pstate_register_driver(default_driver);
2351 mutex_unlock(&intel_pstate_driver_lock);
2352 if (rc)
2353 return rc;
2354
2355 if (hwp_active)
2356 pr_info("HWP enabled\n");
2357
2358 return 0;
2359 }
2360 device_initcall(intel_pstate_init);
2361
2362 static int __init intel_pstate_setup(char *str)
2363 {
2364 if (!str)
2365 return -EINVAL;
2366
2367 if (!strcmp(str, "disable")) {
2368 no_load = 1;
2369 } else if (!strcmp(str, "passive")) {
2370 pr_info("Passive mode enabled\n");
2371 default_driver = &intel_cpufreq;
2372 no_hwp = 1;
2373 }
2374 if (!strcmp(str, "no_hwp")) {
2375 pr_info("HWP disabled\n");
2376 no_hwp = 1;
2377 }
2378 if (!strcmp(str, "force"))
2379 force_load = 1;
2380 if (!strcmp(str, "hwp_only"))
2381 hwp_only = 1;
2382 if (!strcmp(str, "per_cpu_perf_limits"))
2383 per_cpu_limits = true;
2384
2385 #ifdef CONFIG_ACPI
2386 if (!strcmp(str, "support_acpi_ppc"))
2387 acpi_ppc = true;
2388 #endif
2389
2390 return 0;
2391 }
2392 early_param("intel_pstate", intel_pstate_setup);
2393
2394 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2395 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2396 MODULE_LICENSE("GPL");
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