drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "dce/dce_11_0_d.h"
  29 #include "dce/dce_11_0_sh_mask.h"
  30 #include "gmc/gmc_8_2_sh_mask.h"
  31 #include "gmc/gmc_8_2_d.h"
  32
  33 #include "include/logger_interface.h"
  34
  35 #include "dce110_compressor.h"
  36
  37 #define DCP_REG(reg)\
  38         (reg + cp110->offsets.dcp_offset)
  39 #define DMIF_REG(reg)\
  40         (reg + cp110->offsets.dmif_offset)
  41
  42 static const struct dce110_compressor_reg_offsets reg_offsets[] = {
  43 {
  44         .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  45         .dmif_offset =
  46                 (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
  47                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  48 },
  49 {
  50         .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  51         .dmif_offset =
  52                 (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
  53                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  54 },
  55 {
  56         .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  57         .dmif_offset =
  58                 (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
  59                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  60 }
  61 };
  62
  63 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
  64
  65 enum fbc_idle_force {
  66         /* Bit 0 - Display registers updated */
  67         FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
  68
  69         /* Bit 2 - FBC_GRPH_COMP_EN register updated */
  70         FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
  71         /* Bit 3 - FBC_SRC_SEL register updated */
  72         FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
  73         /* Bit 4 - FBC_MIN_COMPRESSION register updated */
  74         FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
  75         /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
  76         FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
  77         /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
  78         FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
  79         /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
  80         FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
  81
  82         /* Bit 24 - Memory write to region 0 defined by MC registers. */
  83         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
  84         /* Bit 25 - Memory write to region 1 defined by MC registers */
  85         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
  86         /* Bit 26 - Memory write to region 2 defined by MC registers */
  87         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
  88         /* Bit 27 - Memory write to region 3 defined by MC registers. */
  89         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
  90
  91         /* Bit 28 - Memory write from any client other than MCIF */
  92         FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
  93         /* Bit 29 - CG statics screen signal is inactive */
  94         FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
  95 };
  96
  97
  98 static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
  99 {
 100         return 256 * ((pixels + 255) / 256);
 101 }
 102
 103 static void wait_for_fbc_state_changed(
 104         struct dce110_compressor *cp110,
 105         bool enabled)
 106 {
 107         uint16_t counter = 0;
 108         uint32_t addr = mmFBC_STATUS;
 109         uint32_t value;
 110
 111         while (counter < 10) {
 112                 value = dm_read_reg(cp110->base.ctx, addr);
 113                 if (get_reg_field_value(
 114                         value,
 115                         FBC_STATUS,
 116                         FBC_ENABLE_STATUS) == enabled)
 117                         break;
 118                 msleep(10);
 119                 counter++;
 120         }
 121
 122         if (counter == 10) {
 123                 dm_logger_write(
 124                         cp110->base.ctx->logger, LOG_WARNING,
 125                         "%s: wait counter exceeded, changes to HW not applied",
 126                         __func__);
 127         } else {
 128                 dm_logger_write(
 129                         cp110->base.ctx->logger, LOG_SYNC,
 130                         "FBC status changed to %d", enabled);
 131         }
 132
 133
 134 }
 135
 136 void dce110_compressor_power_up_fbc(struct compressor *compressor)
 137 {
 138         uint32_t value;
 139         uint32_t addr;
 140
 141         addr = mmFBC_CNTL;
 142         value = dm_read_reg(compressor->ctx, addr);
 143         set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 144         set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
 145         set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
 146         if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
 147                 /* HW needs to do power measurement comparison. */
 148                 set_reg_field_value(
 149                         value,
 150                         0,
 151                         FBC_CNTL,
 152                         FBC_COMP_CLK_GATE_EN);
 153         }
 154         dm_write_reg(compressor->ctx, addr, value);
 155
 156         addr = mmFBC_COMP_MODE;
 157         value = dm_read_reg(compressor->ctx, addr);
 158         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
 159         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
 160         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
 161         dm_write_reg(compressor->ctx, addr, value);
 162
 163         addr = mmFBC_COMP_CNTL;
 164         value = dm_read_reg(compressor->ctx, addr);
 165         set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
 166         dm_write_reg(compressor->ctx, addr, value);
 167         /*FBC_MIN_COMPRESSION 0 ==> 2:1 */
 168         /*                    1 ==> 4:1 */
 169         /*                    2 ==> 8:1 */
 170         /*                  0xF ==> 1:1 */
 171         set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
 172         dm_write_reg(compressor->ctx, addr, value);
 173         compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
 174
 175         value = 0;
 176         dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
 177
 178         value = 0xFFFFFF;
 179         dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
 180 }
 181
 182 void dce110_compressor_enable_fbc(
 183         struct compressor *compressor,
 184         struct compr_addr_and_pitch_params *params)
 185 {
 186         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 187
 188         if (compressor->options.bits.FBC_SUPPORT &&
 189                 (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) {
 190
 191                 uint32_t addr;
 192                 uint32_t value, misc_value;
 193
 194
 195                 addr = mmFBC_CNTL;
 196                 value = dm_read_reg(compressor->ctx, addr);
 197                 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
 198                 set_reg_field_value(
 199                         value,
 200                         params->inst,
 201                         FBC_CNTL, FBC_SRC_SEL);
 202                 dm_write_reg(compressor->ctx, addr, value);
 203
 204                 /* Keep track of enum controller_id FBC is attached to */
 205                 compressor->is_enabled = true;
 206                 compressor->attached_inst = params->inst;
 207                 cp110->offsets = reg_offsets[params->inst];
 208
 209                 /* Toggle it as there is bug in HW */
 210                 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 211                 dm_write_reg(compressor->ctx, addr, value);
 212
 213                 /* FBC usage with scatter & gather for dce110 */
 214                 misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC);
 215
 216                 set_reg_field_value(misc_value, 1,
 217                                 FBC_MISC, FBC_INVALIDATE_ON_ERROR);
 218                 set_reg_field_value(misc_value, 1,
 219                                 FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR);
 220                 set_reg_field_value(misc_value, 0x14,
 221                                 FBC_MISC, FBC_SLOW_REQ_INTERVAL);
 222
 223                 dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value);
 224
 225                 /* Enable FBC */
 226                 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
 227                 dm_write_reg(compressor->ctx, addr, value);
 228
 229                 wait_for_fbc_state_changed(cp110, true);
 230         }
 231 }
 232
 233 void dce110_compressor_disable_fbc(struct compressor *compressor)
 234 {
 235         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 236
 237         if (compressor->options.bits.FBC_SUPPORT &&
 238                 dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
 239                 uint32_t reg_data;
 240                 /* Turn off compression */
 241                 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
 242                 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 243                 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
 244
 245                 /* Reset enum controller_id to undefined */
 246                 compressor->attached_inst = 0;
 247                 compressor->is_enabled = false;
 248
 249                 wait_for_fbc_state_changed(cp110, false);
 250         }
 251 }
 252
 253 bool dce110_compressor_is_fbc_enabled_in_hw(
 254         struct compressor *compressor,
 255         uint32_t *inst)
 256 {
 257         /* Check the hardware register */
 258         uint32_t value;
 259
 260         value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
 261         if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
 262                 if (inst != NULL)
 263                         *inst = compressor->attached_inst;
 264                 return true;
 265         }
 266
 267         value = dm_read_reg(compressor->ctx, mmFBC_MISC);
 268         if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
 269                 value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
 270
 271                 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
 272                         if (inst != NULL)
 273                                 *inst =
 274                                         compressor->attached_inst;
 275                         return true;
 276                 }
 277         }
 278         return false;
 279 }
 280
 281
 282 void dce110_compressor_program_compressed_surface_address_and_pitch(
 283         struct compressor *compressor,
 284         struct compr_addr_and_pitch_params *params)
 285 {
 286         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 287         uint32_t value = 0;
 288         uint32_t fbc_pitch = 0;
 289         uint32_t compressed_surf_address_low_part =
 290                 compressor->compr_surface_address.addr.low_part;
 291
 292         /* Clear content first. */
 293         dm_write_reg(
 294                 compressor->ctx,
 295                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
 296                 0);
 297         dm_write_reg(compressor->ctx,
 298                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
 299
 300         /* Write address, HIGH has to be first. */
 301         dm_write_reg(compressor->ctx,
 302                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
 303                 compressor->compr_surface_address.addr.high_part);
 304         dm_write_reg(compressor->ctx,
 305                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
 306                 compressed_surf_address_low_part);
 307
 308         fbc_pitch = align_to_chunks_number_per_line(params->source_view_width);
 309
 310         if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
 311                 fbc_pitch = fbc_pitch / 8;
 312         else
 313                 dm_logger_write(
 314                         compressor->ctx->logger, LOG_WARNING,
 315                         "%s: Unexpected DCE11 compression ratio",
 316                         __func__);
 317
 318         /* Clear content first. */
 319         dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
 320
 321         /* Write FBC Pitch. */
 322         set_reg_field_value(
 323                 value,
 324                 fbc_pitch,
 325                 GRPH_COMPRESS_PITCH,
 326                 GRPH_COMPRESS_PITCH);
 327         dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
 328
 329 }
 330
 331 void dce110_compressor_set_fbc_invalidation_triggers(
 332         struct compressor *compressor,
 333         uint32_t fbc_trigger)
 334 {
 335         /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
 336          * for DCE 11 regions cannot be used - does not work with S/G
 337          */
 338         uint32_t addr = mmFBC_CLIENT_REGION_MASK;
 339         uint32_t value = dm_read_reg(compressor->ctx, addr);
 340
 341         set_reg_field_value(
 342                 value,
 343                 0,
 344                 FBC_CLIENT_REGION_MASK,
 345                 FBC_MEMORY_REGION_MASK);
 346         dm_write_reg(compressor->ctx, addr, value);
 347
 348         /* Setup events when to clear all CSM entries (effectively marking
 349          * current compressed data invalid)
 350          * For DCE 11 CSM metadata 11111 means - "Not Compressed"
 351          * Used as the initial value of the metadata sent to the compressor
 352          * after invalidation, to indicate that the compressor should attempt
 353          * to compress all chunks on the current pass.  Also used when the chunk
 354          * is not successfully written to memory.
 355          * When this CSM value is detected, FBC reads from the uncompressed
 356          * buffer. Set events according to passed in value, these events are
 357          * valid for DCE11:
 358          *     - bit  0 - display register updated
 359          *     - bit 28 - memory write from any client except from MCIF
 360          *     - bit 29 - CG static screen signal is inactive
 361          * In addition, DCE11.1 also needs to set new DCE11.1 specific events
 362          * that are used to trigger invalidation on certain register changes,
 363          * for example enabling of Alpha Compression may trigger invalidation of
 364          * FBC once bit is set. These events are as follows:
 365          *      - Bit 2 - FBC_GRPH_COMP_EN register updated
 366          *      - Bit 3 - FBC_SRC_SEL register updated
 367          *      - Bit 4 - FBC_MIN_COMPRESSION register updated
 368          *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
 369          *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
 370          *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
 371          */
 372         addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
 373         value = dm_read_reg(compressor->ctx, addr);
 374         set_reg_field_value(
 375                 value,
 376                 fbc_trigger |
 377                 FBC_IDLE_FORCE_GRPH_COMP_EN |
 378                 FBC_IDLE_FORCE_SRC_SEL_CHANGE |
 379                 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
 380                 FBC_IDLE_FORCE_ALPHA_COMP_EN |
 381                 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
 382                 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
 383                 FBC_IDLE_FORCE_CLEAR_MASK,
 384                 FBC_IDLE_FORCE_CLEAR_MASK);
 385         dm_write_reg(compressor->ctx, addr, value);
 386 }
 387
 388 struct compressor *dce110_compressor_create(struct dc_context *ctx)
 389 {
 390         struct dce110_compressor *cp110 =
 391                 kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL);
 392
 393         if (!cp110)
 394                 return NULL;
 395
 396         dce110_compressor_construct(cp110, ctx);
 397         return &cp110->base;
 398 }
 399
 400 void dce110_compressor_destroy(struct compressor **compressor)
 401 {
 402         kfree(TO_DCE110_COMPRESSOR(*compressor));
 403         *compressor = NULL;
 404 }
 405
 406 bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info,
 407                                                 struct fbc_requested_compressed_size size)
 408 {
 409         bool result = false;
 410
 411         unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
 412
 413         get_max_support_fbc_buffersize(&max_x, &max_y);
 414
 415         if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
 416                 /*
 417                  * For DCE11 here use Max HW supported size:  HW Support up to 3840x2400 resolution
 418                  * or 18000 chunks.
 419                  */
 420                 size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4;  /* (For FBC when LPT not supported). */
 421                 size.preferred_size_alignment = size.min_size_alignment = 0x100;       /* For FBC when LPT not supported */
 422                 size.bits.preferred_must_be_framebuffer_pool = 1;
 423                 size.bits.min_must_be_framebuffer_pool = 1;
 424
 425                 result = true;
 426         }
 427         /*
 428          * Maybe to add registry key support with optional size here to override above
 429          * for debugging purposes
 430          */
 431
 432         return result;
 433 }
 434
 435
 436 void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
 437 {
 438         *max_x = FBC_MAX_X;
 439         *max_y = FBC_MAX_Y;
 440
 441         /* if (m_smallLocalFrameBufferMemory == 1)
 442          * {
 443          *      *max_x = FBC_MAX_X_SG;
 444          *      *max_y = FBC_MAX_Y_SG;
 445          * }
 446          */
 447 }
 448
 449
 450 unsigned int controller_id_to_index(enum controller_id controller_id)
 451 {
 452         unsigned int index = 0;
 453
 454         switch (controller_id) {
 455         case CONTROLLER_ID_D0:
 456                 index = 0;
 457                 break;
 458         case CONTROLLER_ID_D1:
 459                 index = 1;
 460                 break;
 461         case CONTROLLER_ID_D2:
 462                 index = 2;
 463                 break;
 464         case CONTROLLER_ID_D3:
 465                 index = 3;
 466                 break;
 467         default:
 468                 break;
 469         }
 470         return index;
 471 }
 472
 473
 474 static const struct compressor_funcs dce110_compressor_funcs = {
 475         .power_up_fbc = dce110_compressor_power_up_fbc,
 476         .enable_fbc = dce110_compressor_enable_fbc,
 477         .disable_fbc = dce110_compressor_disable_fbc,
 478         .set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers,
 479         .surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch,
 480         .is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw
 481 };
 482
 483
 484 void dce110_compressor_construct(struct dce110_compressor *compressor,
 485         struct dc_context *ctx)
 486 {
 487
 488         compressor->base.options.raw = 0;
 489         compressor->base.options.bits.FBC_SUPPORT = true;
 490
 491         /* for dce 11 always use one dram channel for lpt */
 492         compressor->base.lpt_channels_num = 1;
 493         compressor->base.options.bits.DUMMY_BACKEND = false;
 494
 495         /*
 496          * check if this system has more than 1 dram channel; if only 1 then lpt
 497          * should not be supported
 498          */
 499
 500
 501         compressor->base.options.bits.CLK_GATING_DISABLED = false;
 502
 503         compressor->base.ctx = ctx;
 504         compressor->base.embedded_panel_h_size = 0;
 505         compressor->base.embedded_panel_v_size = 0;
 506         compressor->base.memory_bus_width = ctx->asic_id.vram_width;
 507         compressor->base.allocated_size = 0;
 508         compressor->base.preferred_requested_size = 0;
 509         compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
 510         compressor->base.banks_num = 0;
 511         compressor->base.raw_size = 0;
 512         compressor->base.channel_interleave_size = 0;
 513         compressor->base.dram_channels_num = 0;
 514         compressor->base.lpt_channels_num = 0;
 515         compressor->base.attached_inst = 0;
 516         compressor->base.is_enabled = false;
 517 #if defined(CONFIG_DRM_AMD_DC_FBC)
 518         compressor->base.funcs = &dce110_compressor_funcs;
 519
 520 #endif
 521 }
 522