]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/amd/display: eDP sequence BL off first then DP blank.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "resource.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35 #include "gpio_service_interface.h"
36
37 #if defined(CONFIG_DRM_AMD_DC_FBC)
38 #include "dce110_compressor.h"
39 #endif
40
41 #include "bios/bios_parser_helper.h"
42 #include "timing_generator.h"
43 #include "mem_input.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "transform.h"
47 #include "stream_encoder.h"
48 #include "link_encoder.h"
49 #include "link_hwss.h"
50 #include "clock_source.h"
51 #include "abm.h"
52 #include "audio.h"
53 #include "reg_helper.h"
54
55 /* include DCE11 register header files */
56 #include "dce/dce_11_0_d.h"
57 #include "dce/dce_11_0_sh_mask.h"
58 #include "custom_float.h"
59
60 /*
61 * All values are in milliseconds;
62 * For eDP, after power-up/power/down,
63 * 300/500 msec max. delay from LCDVCC to black video generation
64 */
65 #define PANEL_POWER_UP_TIMEOUT 300
66 #define PANEL_POWER_DOWN_TIMEOUT 500
67 #define HPD_CHECK_INTERVAL 10
68
69 #define CTX \
70 hws->ctx
71 #define REG(reg)\
72 hws->regs->reg
73
74 #undef FN
75 #define FN(reg_name, field_name) \
76 hws->shifts->field_name, hws->masks->field_name
77
78 struct dce110_hw_seq_reg_offsets {
79 uint32_t crtc;
80 };
81
82 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
83 {
84 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
85 },
86 {
87 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
88 },
89 {
90 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
91 },
92 {
93 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
94 }
95 };
96
97 #define HW_REG_BLND(reg, id)\
98 (reg + reg_offsets[id].blnd)
99
100 #define HW_REG_CRTC(reg, id)\
101 (reg + reg_offsets[id].crtc)
102
103 #define MAX_WATERMARK 0xFFFF
104 #define SAFE_NBP_MARK 0x7FFF
105
106 /*******************************************************************************
107 * Private definitions
108 ******************************************************************************/
109 /***************************PIPE_CONTROL***********************************/
110 static void dce110_init_pte(struct dc_context *ctx)
111 {
112 uint32_t addr;
113 uint32_t value = 0;
114 uint32_t chunk_int = 0;
115 uint32_t chunk_mul = 0;
116
117 addr = mmUNP_DVMM_PTE_CONTROL;
118 value = dm_read_reg(ctx, addr);
119
120 set_reg_field_value(
121 value,
122 0,
123 DVMM_PTE_CONTROL,
124 DVMM_USE_SINGLE_PTE);
125
126 set_reg_field_value(
127 value,
128 1,
129 DVMM_PTE_CONTROL,
130 DVMM_PTE_BUFFER_MODE0);
131
132 set_reg_field_value(
133 value,
134 1,
135 DVMM_PTE_CONTROL,
136 DVMM_PTE_BUFFER_MODE1);
137
138 dm_write_reg(ctx, addr, value);
139
140 addr = mmDVMM_PTE_REQ;
141 value = dm_read_reg(ctx, addr);
142
143 chunk_int = get_reg_field_value(
144 value,
145 DVMM_PTE_REQ,
146 HFLIP_PTEREQ_PER_CHUNK_INT);
147
148 chunk_mul = get_reg_field_value(
149 value,
150 DVMM_PTE_REQ,
151 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
152
153 if (chunk_int != 0x4 || chunk_mul != 0x4) {
154
155 set_reg_field_value(
156 value,
157 255,
158 DVMM_PTE_REQ,
159 MAX_PTEREQ_TO_ISSUE);
160
161 set_reg_field_value(
162 value,
163 4,
164 DVMM_PTE_REQ,
165 HFLIP_PTEREQ_PER_CHUNK_INT);
166
167 set_reg_field_value(
168 value,
169 4,
170 DVMM_PTE_REQ,
171 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
172
173 dm_write_reg(ctx, addr, value);
174 }
175 }
176 /**************************************************************************/
177
178 static void enable_display_pipe_clock_gating(
179 struct dc_context *ctx,
180 bool clock_gating)
181 {
182 /*TODO*/
183 }
184
185 static bool dce110_enable_display_power_gating(
186 struct dc *dc,
187 uint8_t controller_id,
188 struct dc_bios *dcb,
189 enum pipe_gating_control power_gating)
190 {
191 enum bp_result bp_result = BP_RESULT_OK;
192 enum bp_pipe_control_action cntl;
193 struct dc_context *ctx = dc->ctx;
194 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
195
196 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
197 return true;
198
199 if (power_gating == PIPE_GATING_CONTROL_INIT)
200 cntl = ASIC_PIPE_INIT;
201 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
202 cntl = ASIC_PIPE_ENABLE;
203 else
204 cntl = ASIC_PIPE_DISABLE;
205
206 if (controller_id == underlay_idx)
207 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
208
209 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
210
211 bp_result = dcb->funcs->enable_disp_power_gating(
212 dcb, controller_id + 1, cntl);
213
214 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
215 * by default when command table is called
216 *
217 * Bios parser accepts controller_id = 6 as indicative of
218 * underlay pipe in dce110. But we do not support more
219 * than 3.
220 */
221 if (controller_id < CONTROLLER_ID_MAX - 1)
222 dm_write_reg(ctx,
223 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
224 0);
225 }
226
227 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
228 dce110_init_pte(ctx);
229
230 if (bp_result == BP_RESULT_OK)
231 return true;
232 else
233 return false;
234 }
235
236 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
237 const struct dc_plane_state *plane_state)
238 {
239 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
240
241 switch (plane_state->format) {
242 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
243 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
244 prescale_params->scale = 0x2020;
245 break;
246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
248 prescale_params->scale = 0x2008;
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
251 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
252 prescale_params->scale = 0x2000;
253 break;
254 default:
255 ASSERT(false);
256 break;
257 }
258 }
259
260 static bool dce110_set_input_transfer_func(
261 struct pipe_ctx *pipe_ctx,
262 const struct dc_plane_state *plane_state)
263 {
264 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
265 const struct dc_transfer_func *tf = NULL;
266 struct ipp_prescale_params prescale_params = { 0 };
267 bool result = true;
268
269 if (ipp == NULL)
270 return false;
271
272 if (plane_state->in_transfer_func)
273 tf = plane_state->in_transfer_func;
274
275 build_prescale_params(&prescale_params, plane_state);
276 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
277
278 if (plane_state->gamma_correction && dce_use_lut(plane_state))
279 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
280
281 if (tf == NULL) {
282 /* Default case if no input transfer function specified */
283 ipp->funcs->ipp_set_degamma(ipp,
284 IPP_DEGAMMA_MODE_HW_sRGB);
285 } else if (tf->type == TF_TYPE_PREDEFINED) {
286 switch (tf->tf) {
287 case TRANSFER_FUNCTION_SRGB:
288 ipp->funcs->ipp_set_degamma(ipp,
289 IPP_DEGAMMA_MODE_HW_sRGB);
290 break;
291 case TRANSFER_FUNCTION_BT709:
292 ipp->funcs->ipp_set_degamma(ipp,
293 IPP_DEGAMMA_MODE_HW_xvYCC);
294 break;
295 case TRANSFER_FUNCTION_LINEAR:
296 ipp->funcs->ipp_set_degamma(ipp,
297 IPP_DEGAMMA_MODE_BYPASS);
298 break;
299 case TRANSFER_FUNCTION_PQ:
300 result = false;
301 break;
302 default:
303 result = false;
304 break;
305 }
306 } else if (tf->type == TF_TYPE_BYPASS) {
307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
308 } else {
309 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
310 result = false;
311 }
312
313 return result;
314 }
315
316 static bool convert_to_custom_float(
317 struct pwl_result_data *rgb_resulted,
318 struct curve_points *arr_points,
319 uint32_t hw_points_num)
320 {
321 struct custom_float_format fmt;
322
323 struct pwl_result_data *rgb = rgb_resulted;
324
325 uint32_t i = 0;
326
327 fmt.exponenta_bits = 6;
328 fmt.mantissa_bits = 12;
329 fmt.sign = true;
330
331 if (!convert_to_custom_float_format(
332 arr_points[0].x,
333 &fmt,
334 &arr_points[0].custom_float_x)) {
335 BREAK_TO_DEBUGGER();
336 return false;
337 }
338
339 if (!convert_to_custom_float_format(
340 arr_points[0].offset,
341 &fmt,
342 &arr_points[0].custom_float_offset)) {
343 BREAK_TO_DEBUGGER();
344 return false;
345 }
346
347 if (!convert_to_custom_float_format(
348 arr_points[0].slope,
349 &fmt,
350 &arr_points[0].custom_float_slope)) {
351 BREAK_TO_DEBUGGER();
352 return false;
353 }
354
355 fmt.mantissa_bits = 10;
356 fmt.sign = false;
357
358 if (!convert_to_custom_float_format(
359 arr_points[1].x,
360 &fmt,
361 &arr_points[1].custom_float_x)) {
362 BREAK_TO_DEBUGGER();
363 return false;
364 }
365
366 if (!convert_to_custom_float_format(
367 arr_points[1].y,
368 &fmt,
369 &arr_points[1].custom_float_y)) {
370 BREAK_TO_DEBUGGER();
371 return false;
372 }
373
374 if (!convert_to_custom_float_format(
375 arr_points[2].slope,
376 &fmt,
377 &arr_points[2].custom_float_slope)) {
378 BREAK_TO_DEBUGGER();
379 return false;
380 }
381
382 fmt.mantissa_bits = 12;
383 fmt.sign = true;
384
385 while (i != hw_points_num) {
386 if (!convert_to_custom_float_format(
387 rgb->red,
388 &fmt,
389 &rgb->red_reg)) {
390 BREAK_TO_DEBUGGER();
391 return false;
392 }
393
394 if (!convert_to_custom_float_format(
395 rgb->green,
396 &fmt,
397 &rgb->green_reg)) {
398 BREAK_TO_DEBUGGER();
399 return false;
400 }
401
402 if (!convert_to_custom_float_format(
403 rgb->blue,
404 &fmt,
405 &rgb->blue_reg)) {
406 BREAK_TO_DEBUGGER();
407 return false;
408 }
409
410 if (!convert_to_custom_float_format(
411 rgb->delta_red,
412 &fmt,
413 &rgb->delta_red_reg)) {
414 BREAK_TO_DEBUGGER();
415 return false;
416 }
417
418 if (!convert_to_custom_float_format(
419 rgb->delta_green,
420 &fmt,
421 &rgb->delta_green_reg)) {
422 BREAK_TO_DEBUGGER();
423 return false;
424 }
425
426 if (!convert_to_custom_float_format(
427 rgb->delta_blue,
428 &fmt,
429 &rgb->delta_blue_reg)) {
430 BREAK_TO_DEBUGGER();
431 return false;
432 }
433
434 ++rgb;
435 ++i;
436 }
437
438 return true;
439 }
440
441 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
442 *output_tf, struct pwl_params *regamma_params)
443 {
444 struct curve_points *arr_points;
445 struct pwl_result_data *rgb_resulted;
446 struct pwl_result_data *rgb;
447 struct pwl_result_data *rgb_plus_1;
448 struct fixed31_32 y_r;
449 struct fixed31_32 y_g;
450 struct fixed31_32 y_b;
451 struct fixed31_32 y1_min;
452 struct fixed31_32 y3_max;
453
454 int32_t segment_start, segment_end;
455 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
456
457 if (output_tf == NULL || regamma_params == NULL ||
458 output_tf->type == TF_TYPE_BYPASS)
459 return false;
460
461 arr_points = regamma_params->arr_points;
462 rgb_resulted = regamma_params->rgb_resulted;
463 hw_points = 0;
464
465 memset(regamma_params, 0, sizeof(struct pwl_params));
466
467 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
468 /* 16 segments
469 * segments are from 2^-11 to 2^5
470 */
471 segment_start = -11;
472 segment_end = 5;
473
474 seg_distr[0] = 2;
475 seg_distr[1] = 2;
476 seg_distr[2] = 2;
477 seg_distr[3] = 2;
478 seg_distr[4] = 2;
479 seg_distr[5] = 2;
480 seg_distr[6] = 3;
481 seg_distr[7] = 4;
482 seg_distr[8] = 4;
483 seg_distr[9] = 4;
484 seg_distr[10] = 4;
485 seg_distr[11] = 5;
486 seg_distr[12] = 5;
487 seg_distr[13] = 5;
488 seg_distr[14] = 5;
489 seg_distr[15] = 5;
490
491 } else {
492 /* 10 segments
493 * segment is from 2^-10 to 2^0
494 */
495 segment_start = -10;
496 segment_end = 0;
497
498 seg_distr[0] = 3;
499 seg_distr[1] = 4;
500 seg_distr[2] = 4;
501 seg_distr[3] = 4;
502 seg_distr[4] = 4;
503 seg_distr[5] = 4;
504 seg_distr[6] = 4;
505 seg_distr[7] = 4;
506 seg_distr[8] = 5;
507 seg_distr[9] = 5;
508 seg_distr[10] = -1;
509 seg_distr[11] = -1;
510 seg_distr[12] = -1;
511 seg_distr[13] = -1;
512 seg_distr[14] = -1;
513 seg_distr[15] = -1;
514 }
515
516 for (k = 0; k < 16; k++) {
517 if (seg_distr[k] != -1)
518 hw_points += (1 << seg_distr[k]);
519 }
520
521 j = 0;
522 for (k = 0; k < (segment_end - segment_start); k++) {
523 increment = 32 / (1 << seg_distr[k]);
524 start_index = (segment_start + k + 25) * 32;
525 for (i = start_index; i < start_index + 32; i += increment) {
526 if (j == hw_points - 1)
527 break;
528 rgb_resulted[j].red = output_tf->tf_pts.red[i];
529 rgb_resulted[j].green = output_tf->tf_pts.green[i];
530 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
531 j++;
532 }
533 }
534
535 /* last point */
536 start_index = (segment_end + 25) * 32;
537 rgb_resulted[hw_points - 1].red =
538 output_tf->tf_pts.red[start_index];
539 rgb_resulted[hw_points - 1].green =
540 output_tf->tf_pts.green[start_index];
541 rgb_resulted[hw_points - 1].blue =
542 output_tf->tf_pts.blue[start_index];
543
544 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
545 dal_fixed31_32_from_int(segment_start));
546 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
547 dal_fixed31_32_from_int(segment_end));
548 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
549 dal_fixed31_32_from_int(segment_end));
550
551 y_r = rgb_resulted[0].red;
552 y_g = rgb_resulted[0].green;
553 y_b = rgb_resulted[0].blue;
554
555 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
556
557 arr_points[0].y = y1_min;
558 arr_points[0].slope = dal_fixed31_32_div(
559 arr_points[0].y,
560 arr_points[0].x);
561
562 y_r = rgb_resulted[hw_points - 1].red;
563 y_g = rgb_resulted[hw_points - 1].green;
564 y_b = rgb_resulted[hw_points - 1].blue;
565
566 /* see comment above, m_arrPoints[1].y should be the Y value for the
567 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
568 */
569 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
570
571 arr_points[1].y = y3_max;
572 arr_points[2].y = y3_max;
573
574 arr_points[1].slope = dal_fixed31_32_zero;
575 arr_points[2].slope = dal_fixed31_32_zero;
576
577 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
578 /* for PQ, we want to have a straight line from last HW X point,
579 * and the slope to be such that we hit 1.0 at 10000 nits.
580 */
581 const struct fixed31_32 end_value =
582 dal_fixed31_32_from_int(125);
583
584 arr_points[1].slope = dal_fixed31_32_div(
585 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
586 dal_fixed31_32_sub(end_value, arr_points[1].x));
587 arr_points[2].slope = dal_fixed31_32_div(
588 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
589 dal_fixed31_32_sub(end_value, arr_points[1].x));
590 }
591
592 regamma_params->hw_points_num = hw_points;
593
594 i = 1;
595 for (k = 0; k < 16 && i < 16; k++) {
596 if (seg_distr[k] != -1) {
597 regamma_params->arr_curve_points[k].segments_num =
598 seg_distr[k];
599 regamma_params->arr_curve_points[i].offset =
600 regamma_params->arr_curve_points[k].
601 offset + (1 << seg_distr[k]);
602 }
603 i++;
604 }
605
606 if (seg_distr[k] != -1)
607 regamma_params->arr_curve_points[k].segments_num =
608 seg_distr[k];
609
610 rgb = rgb_resulted;
611 rgb_plus_1 = rgb_resulted + 1;
612
613 i = 1;
614
615 while (i != hw_points + 1) {
616 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
617 rgb_plus_1->red = rgb->red;
618 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
619 rgb_plus_1->green = rgb->green;
620 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
621 rgb_plus_1->blue = rgb->blue;
622
623 rgb->delta_red = dal_fixed31_32_sub(
624 rgb_plus_1->red,
625 rgb->red);
626 rgb->delta_green = dal_fixed31_32_sub(
627 rgb_plus_1->green,
628 rgb->green);
629 rgb->delta_blue = dal_fixed31_32_sub(
630 rgb_plus_1->blue,
631 rgb->blue);
632
633 ++rgb_plus_1;
634 ++rgb;
635 ++i;
636 }
637
638 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
639
640 return true;
641 }
642
643 static bool dce110_set_output_transfer_func(
644 struct pipe_ctx *pipe_ctx,
645 const struct dc_stream_state *stream)
646 {
647 struct transform *xfm = pipe_ctx->plane_res.xfm;
648
649 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
650 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
651
652 if (stream->out_transfer_func &&
653 stream->out_transfer_func->type ==
654 TF_TYPE_PREDEFINED &&
655 stream->out_transfer_func->tf ==
656 TRANSFER_FUNCTION_SRGB) {
657 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
658 } else if (dce110_translate_regamma_to_hw_format(
659 stream->out_transfer_func, &xfm->regamma_params)) {
660 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
661 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
662 } else {
663 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
664 }
665
666 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
667
668 return true;
669 }
670
671 static enum dc_status bios_parser_crtc_source_select(
672 struct pipe_ctx *pipe_ctx)
673 {
674 struct dc_bios *dcb;
675 /* call VBIOS table to set CRTC source for the HW
676 * encoder block
677 * note: video bios clears all FMT setting here. */
678 struct bp_crtc_source_select crtc_source_select = {0};
679 const struct dc_sink *sink = pipe_ctx->stream->sink;
680
681 crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
682 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
683 /*TODO: Need to un-hardcode color depth, dp_audio and account for
684 * the case where signal and sink signal is different (translator
685 * encoder)*/
686 crtc_source_select.signal = pipe_ctx->stream->signal;
687 crtc_source_select.enable_dp_audio = false;
688 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
689
690 switch (pipe_ctx->stream->timing.display_color_depth) {
691 case COLOR_DEPTH_666:
692 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
693 break;
694 case COLOR_DEPTH_888:
695 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
696 break;
697 case COLOR_DEPTH_101010:
698 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
699 break;
700 case COLOR_DEPTH_121212:
701 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
702 break;
703 default:
704 BREAK_TO_DEBUGGER();
705 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
706 break;
707 }
708
709 dcb = sink->ctx->dc_bios;
710
711 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
712 dcb,
713 &crtc_source_select)) {
714 return DC_ERROR_UNEXPECTED;
715 }
716
717 return DC_OK;
718 }
719
720 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
721 {
722 ASSERT(pipe_ctx->stream);
723
724 if (pipe_ctx->stream_res.stream_enc == NULL)
725 return; /* this is not root pipe */
726
727 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
728 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
729 pipe_ctx->stream_res.stream_enc,
730 &pipe_ctx->stream_res.encoder_info_frame);
731 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
732 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
733 pipe_ctx->stream_res.stream_enc,
734 &pipe_ctx->stream_res.encoder_info_frame);
735 }
736
737 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
738 {
739 enum dc_lane_count lane_count =
740 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
741
742 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
743 struct dc_link *link = pipe_ctx->stream->sink->link;
744
745 /* 1. update AVI info frame (HDMI, DP)
746 * we always need to update info frame
747 */
748 uint32_t active_total_with_borders;
749 uint32_t early_control = 0;
750 struct timing_generator *tg = pipe_ctx->stream_res.tg;
751
752 /* TODOFPGA may change to hwss.update_info_frame */
753 dce110_update_info_frame(pipe_ctx);
754 /* enable early control to avoid corruption on DP monitor*/
755 active_total_with_borders =
756 timing->h_addressable
757 + timing->h_border_left
758 + timing->h_border_right;
759
760 if (lane_count != 0)
761 early_control = active_total_with_borders % lane_count;
762
763 if (early_control == 0)
764 early_control = lane_count;
765
766 tg->funcs->set_early_control(tg, early_control);
767
768 /* enable audio only within mode set */
769 if (pipe_ctx->stream_res.audio != NULL) {
770 if (dc_is_dp_signal(pipe_ctx->stream->signal))
771 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
772 }
773
774 /* For MST, there are multiply stream go to only one link.
775 * connect DIG back_end to front_end while enable_stream and
776 * disconnect them during disable_stream
777 * BY this, it is logic clean to separate stream and link */
778 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
779 pipe_ctx->stream_res.stream_enc->id, true);
780
781 }
782
783 /*todo: cloned in stream enc, fix*/
784 static bool is_panel_backlight_on(struct dce_hwseq *hws)
785 {
786 uint32_t value;
787
788 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
789
790 return value;
791 }
792
793 static bool is_panel_powered_on(struct dce_hwseq *hws)
794 {
795 uint32_t value;
796
797 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value);
798 return value == 1;
799 }
800
801 static enum bp_result link_transmitter_control(
802 struct dc_bios *bios,
803 struct bp_transmitter_control *cntl)
804 {
805 enum bp_result result;
806
807 result = bios->funcs->transmitter_control(bios, cntl);
808
809 return result;
810 }
811
812 /*
813 * @brief
814 * eDP only.
815 */
816 void hwss_edp_wait_for_hpd_ready(
817 struct dc_link *link,
818 bool power_up)
819 {
820 struct dc_context *ctx = link->ctx;
821 struct graphics_object_id connector = link->link_enc->connector;
822 struct gpio *hpd;
823 bool edp_hpd_high = false;
824 uint32_t time_elapsed = 0;
825 uint32_t timeout = power_up ?
826 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
827
828 if (dal_graphics_object_id_get_connector_id(connector)
829 != CONNECTOR_ID_EDP) {
830 BREAK_TO_DEBUGGER();
831 return;
832 }
833
834 if (!power_up)
835 /*
836 * From KV, we will not HPD low after turning off VCC -
837 * instead, we will check the SW timer in power_up().
838 */
839 return;
840
841 /*
842 * When we power on/off the eDP panel,
843 * we need to wait until SENSE bit is high/low.
844 */
845
846 /* obtain HPD */
847 /* TODO what to do with this? */
848 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
849
850 if (!hpd) {
851 BREAK_TO_DEBUGGER();
852 return;
853 }
854
855 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
856
857 /* wait until timeout or panel detected */
858
859 do {
860 uint32_t detected = 0;
861
862 dal_gpio_get_value(hpd, &detected);
863
864 if (!(detected ^ power_up)) {
865 edp_hpd_high = true;
866 break;
867 }
868
869 msleep(HPD_CHECK_INTERVAL);
870
871 time_elapsed += HPD_CHECK_INTERVAL;
872 } while (time_elapsed < timeout);
873
874 dal_gpio_close(hpd);
875
876 dal_gpio_destroy_irq(&hpd);
877
878 if (false == edp_hpd_high) {
879 dm_logger_write(ctx->logger, LOG_ERROR,
880 "%s: wait timed out!\n", __func__);
881 }
882 }
883
884 void hwss_edp_power_control(
885 struct dc_link *link,
886 bool power_up)
887 {
888 struct dc_context *ctx = link->ctx;
889 struct dce_hwseq *hwseq = ctx->dc->hwseq;
890 struct bp_transmitter_control cntl = { 0 };
891 enum bp_result bp_result;
892
893
894 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
895 != CONNECTOR_ID_EDP) {
896 BREAK_TO_DEBUGGER();
897 return;
898 }
899
900 if (power_up != is_panel_powered_on(hwseq)) {
901 /* Send VBIOS command to prompt eDP panel power */
902
903 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
904 "%s: Panel Power action: %s\n",
905 __func__, (power_up ? "On":"Off"));
906
907 cntl.action = power_up ?
908 TRANSMITTER_CONTROL_POWER_ON :
909 TRANSMITTER_CONTROL_POWER_OFF;
910 cntl.transmitter = link->link_enc->transmitter;
911 cntl.connector_obj_id = link->link_enc->connector;
912 cntl.coherent = false;
913 cntl.lanes_number = LANE_COUNT_FOUR;
914 cntl.hpd_sel = link->link_enc->hpd_source;
915
916 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
917
918 if (bp_result != BP_RESULT_OK)
919 dm_logger_write(ctx->logger, LOG_ERROR,
920 "%s: Panel Power bp_result: %d\n",
921 __func__, bp_result);
922 } else {
923 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
924 "%s: Skipping Panel Power action: %s\n",
925 __func__, (power_up ? "On":"Off"));
926 }
927 }
928
929 /*todo: cloned in stream enc, fix*/
930 /*
931 * @brief
932 * eDP only. Control the backlight of the eDP panel
933 */
934 void hwss_edp_backlight_control(
935 struct dc_link *link,
936 bool enable)
937 {
938 struct dc_context *ctx = link->ctx;
939 struct dce_hwseq *hws = ctx->dc->hwseq;
940 struct bp_transmitter_control cntl = { 0 };
941
942 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
943 != CONNECTOR_ID_EDP) {
944 BREAK_TO_DEBUGGER();
945 return;
946 }
947
948 if (enable && is_panel_backlight_on(hws)) {
949 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
950 "%s: panel already powered up. Do nothing.\n",
951 __func__);
952 return;
953 }
954
955 /* Send VBIOS command to control eDP panel backlight */
956
957 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
958 "%s: backlight action: %s\n",
959 __func__, (enable ? "On":"Off"));
960
961 cntl.action = enable ?
962 TRANSMITTER_CONTROL_BACKLIGHT_ON :
963 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
964
965 /*cntl.engine_id = ctx->engine;*/
966 cntl.transmitter = link->link_enc->transmitter;
967 cntl.connector_obj_id = link->link_enc->connector;
968 /*todo: unhardcode*/
969 cntl.lanes_number = LANE_COUNT_FOUR;
970 cntl.hpd_sel = link->link_enc->hpd_source;
971
972 /* For eDP, the following delays might need to be considered
973 * after link training completed:
974 * idle period - min. accounts for required BS-Idle pattern,
975 * max. allows for source frame synchronization);
976 * 50 msec max. delay from valid video data from source
977 * to video on dislpay or backlight enable.
978 *
979 * Disable the delay for now.
980 * Enable it in the future if necessary.
981 */
982 /* dc_service_sleep_in_milliseconds(50); */
983 link_transmitter_control(ctx->dc_bios, &cntl);
984 }
985
986 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
987 {
988 struct dc_stream_state *stream = pipe_ctx->stream;
989 struct dc_link *link = stream->sink->link;
990 struct dc *dc = pipe_ctx->stream->ctx->dc;
991
992 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
993 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
994 pipe_ctx->stream_res.stream_enc);
995
996 if (dc_is_dp_signal(pipe_ctx->stream->signal))
997 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
998 pipe_ctx->stream_res.stream_enc);
999
1000 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1001 pipe_ctx->stream_res.stream_enc, true);
1002 if (pipe_ctx->stream_res.audio) {
1003 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1004
1005 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1006 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1007 pipe_ctx->stream_res.stream_enc);
1008 else
1009 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1010 pipe_ctx->stream_res.stream_enc);
1011 /*don't free audio if it is from retrain or internal disable stream*/
1012 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1013 /*we have to dynamic arbitrate the audio endpoints*/
1014 pipe_ctx->stream_res.audio = NULL;
1015 /*we free the resource, need reset is_audio_acquired*/
1016 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1017 }
1018
1019 /* TODO: notify audio driver for if audio modes list changed
1020 * add audio mode list change flag */
1021 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1022 * stream->stream_engine_id);
1023 */
1024 }
1025
1026 /* blank at encoder level */
1027 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1028 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1029
1030 link->link_enc->funcs->connect_dig_be_to_fe(
1031 link->link_enc,
1032 pipe_ctx->stream_res.stream_enc->id,
1033 false);
1034
1035 }
1036
1037 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1038 struct dc_link_settings *link_settings)
1039 {
1040 struct encoder_unblank_param params = { { 0 } };
1041 struct dc_stream_state *stream = pipe_ctx->stream;
1042 struct dc_link *link = stream->sink->link;
1043
1044 /* only 3 items below are used by unblank */
1045 params.pixel_clk_khz =
1046 pipe_ctx->stream->timing.pix_clk_khz;
1047 params.link_settings.link_rate = link_settings->link_rate;
1048
1049 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1050 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1051
1052 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1053 link->dc->hwss.edp_backlight_control(link, true);
1054 }
1055 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1056 {
1057 struct encoder_unblank_param params = { { 0 } };
1058 struct dc_stream_state *stream = pipe_ctx->stream;
1059 struct dc_link *link = stream->sink->link;
1060
1061 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1062 link->dc->hwss.edp_backlight_control(link, false);
1063
1064 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1065 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1066 }
1067
1068
1069 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1070 {
1071 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1072 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1073 }
1074
1075 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1076 {
1077 switch (crtc_id) {
1078 case CONTROLLER_ID_D0:
1079 return DTO_SOURCE_ID0;
1080 case CONTROLLER_ID_D1:
1081 return DTO_SOURCE_ID1;
1082 case CONTROLLER_ID_D2:
1083 return DTO_SOURCE_ID2;
1084 case CONTROLLER_ID_D3:
1085 return DTO_SOURCE_ID3;
1086 case CONTROLLER_ID_D4:
1087 return DTO_SOURCE_ID4;
1088 case CONTROLLER_ID_D5:
1089 return DTO_SOURCE_ID5;
1090 default:
1091 return DTO_SOURCE_UNKNOWN;
1092 }
1093 }
1094
1095 static void build_audio_output(
1096 struct dc_state *state,
1097 const struct pipe_ctx *pipe_ctx,
1098 struct audio_output *audio_output)
1099 {
1100 const struct dc_stream_state *stream = pipe_ctx->stream;
1101 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1102
1103 audio_output->signal = pipe_ctx->stream->signal;
1104
1105 /* audio_crtc_info */
1106
1107 audio_output->crtc_info.h_total =
1108 stream->timing.h_total;
1109
1110 /*
1111 * Audio packets are sent during actual CRTC blank physical signal, we
1112 * need to specify actual active signal portion
1113 */
1114 audio_output->crtc_info.h_active =
1115 stream->timing.h_addressable
1116 + stream->timing.h_border_left
1117 + stream->timing.h_border_right;
1118
1119 audio_output->crtc_info.v_active =
1120 stream->timing.v_addressable
1121 + stream->timing.v_border_top
1122 + stream->timing.v_border_bottom;
1123
1124 audio_output->crtc_info.pixel_repetition = 1;
1125
1126 audio_output->crtc_info.interlaced =
1127 stream->timing.flags.INTERLACE;
1128
1129 audio_output->crtc_info.refresh_rate =
1130 (stream->timing.pix_clk_khz*1000)/
1131 (stream->timing.h_total*stream->timing.v_total);
1132
1133 audio_output->crtc_info.color_depth =
1134 stream->timing.display_color_depth;
1135
1136 audio_output->crtc_info.requested_pixel_clock =
1137 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1138
1139 audio_output->crtc_info.calculated_pixel_clock =
1140 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1141
1142 /*for HDMI, audio ACR is with deep color ratio factor*/
1143 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1144 audio_output->crtc_info.requested_pixel_clock ==
1145 stream->timing.pix_clk_khz) {
1146 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1147 audio_output->crtc_info.requested_pixel_clock =
1148 audio_output->crtc_info.requested_pixel_clock/2;
1149 audio_output->crtc_info.calculated_pixel_clock =
1150 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1151
1152 }
1153 }
1154
1155 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1156 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1157 audio_output->pll_info.dp_dto_source_clock_in_khz =
1158 state->dis_clk->funcs->get_dp_ref_clk_frequency(
1159 state->dis_clk);
1160 }
1161
1162 audio_output->pll_info.feed_back_divider =
1163 pipe_ctx->pll_settings.feedback_divider;
1164
1165 audio_output->pll_info.dto_source =
1166 translate_to_dto_source(
1167 pipe_ctx->pipe_idx + 1);
1168
1169 /* TODO hard code to enable for now. Need get from stream */
1170 audio_output->pll_info.ss_enabled = true;
1171
1172 audio_output->pll_info.ss_percentage =
1173 pipe_ctx->pll_settings.ss_percentage;
1174 }
1175
1176 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1177 struct tg_color *color)
1178 {
1179 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
1180
1181 switch (pipe_ctx->plane_res.scl_data.format) {
1182 case PIXEL_FORMAT_ARGB8888:
1183 /* set boarder color to red */
1184 color->color_r_cr = color_value;
1185 break;
1186
1187 case PIXEL_FORMAT_ARGB2101010:
1188 /* set boarder color to blue */
1189 color->color_b_cb = color_value;
1190 break;
1191 case PIXEL_FORMAT_420BPP8:
1192 /* set boarder color to green */
1193 color->color_g_y = color_value;
1194 break;
1195 case PIXEL_FORMAT_420BPP10:
1196 /* set boarder color to yellow */
1197 color->color_g_y = color_value;
1198 color->color_r_cr = color_value;
1199 break;
1200 case PIXEL_FORMAT_FP16:
1201 /* set boarder color to white */
1202 color->color_r_cr = color_value;
1203 color->color_b_cb = color_value;
1204 color->color_g_y = color_value;
1205 break;
1206 default:
1207 break;
1208 }
1209 }
1210
1211 static void program_scaler(const struct dc *dc,
1212 const struct pipe_ctx *pipe_ctx)
1213 {
1214 struct tg_color color = {0};
1215
1216 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1217 /* TOFPGA */
1218 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1219 return;
1220 #endif
1221
1222 if (dc->debug.surface_visual_confirm)
1223 get_surface_visual_confirm_color(pipe_ctx, &color);
1224 else
1225 color_space_to_black_color(dc,
1226 pipe_ctx->stream->output_color_space,
1227 &color);
1228
1229 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1230 pipe_ctx->plane_res.xfm,
1231 pipe_ctx->plane_res.scl_data.lb_params.depth,
1232 &pipe_ctx->stream->bit_depth_params);
1233
1234 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
1235 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1236 pipe_ctx->stream_res.tg,
1237 &color);
1238
1239 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1240 &pipe_ctx->plane_res.scl_data);
1241 }
1242
1243 static enum dc_status dce110_prog_pixclk_crtc_otg(
1244 struct pipe_ctx *pipe_ctx,
1245 struct dc_state *context,
1246 struct dc *dc)
1247 {
1248 struct dc_stream_state *stream = pipe_ctx->stream;
1249 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1250 pipe_ctx[pipe_ctx->pipe_idx];
1251 struct tg_color black_color = {0};
1252
1253 if (!pipe_ctx_old->stream) {
1254
1255 /* program blank color */
1256 color_space_to_black_color(dc,
1257 stream->output_color_space, &black_color);
1258 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1259 pipe_ctx->stream_res.tg,
1260 &black_color);
1261
1262 /*
1263 * Must blank CRTC after disabling power gating and before any
1264 * programming, otherwise CRTC will be hung in bad state
1265 */
1266 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1267
1268 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1269 pipe_ctx->clock_source,
1270 &pipe_ctx->stream_res.pix_clk_params,
1271 &pipe_ctx->pll_settings)) {
1272 BREAK_TO_DEBUGGER();
1273 return DC_ERROR_UNEXPECTED;
1274 }
1275
1276 pipe_ctx->stream_res.tg->funcs->program_timing(
1277 pipe_ctx->stream_res.tg,
1278 &stream->timing,
1279 true);
1280
1281 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1282 pipe_ctx->stream_res.tg,
1283 0x182);
1284 }
1285
1286 if (!pipe_ctx_old->stream) {
1287 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1288 pipe_ctx->stream_res.tg)) {
1289 BREAK_TO_DEBUGGER();
1290 return DC_ERROR_UNEXPECTED;
1291 }
1292 }
1293
1294
1295
1296 return DC_OK;
1297 }
1298
1299 static enum dc_status apply_single_controller_ctx_to_hw(
1300 struct pipe_ctx *pipe_ctx,
1301 struct dc_state *context,
1302 struct dc *dc)
1303 {
1304 struct dc_stream_state *stream = pipe_ctx->stream;
1305 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1306 pipe_ctx[pipe_ctx->pipe_idx];
1307
1308 /* */
1309 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1310
1311 /* FPGA does not program backend */
1312 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1313 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1314 pipe_ctx->stream_res.opp,
1315 COLOR_SPACE_YCBCR601,
1316 stream->timing.display_color_depth,
1317 pipe_ctx->stream->signal);
1318
1319 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1320 pipe_ctx->stream_res.opp,
1321 &stream->bit_depth_params,
1322 &stream->clamping);
1323 return DC_OK;
1324 }
1325 /* TODO: move to stream encoder */
1326 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1327 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1328 BREAK_TO_DEBUGGER();
1329 return DC_ERROR_UNEXPECTED;
1330 }
1331 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1332 pipe_ctx->stream_res.opp,
1333 COLOR_SPACE_YCBCR601,
1334 stream->timing.display_color_depth,
1335 pipe_ctx->stream->signal);
1336
1337 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1338 stream->sink->link->link_enc->funcs->setup(
1339 stream->sink->link->link_enc,
1340 pipe_ctx->stream->signal);
1341
1342 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1343 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1344 pipe_ctx->stream_res.stream_enc,
1345 pipe_ctx->stream_res.tg->inst,
1346 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1347
1348
1349 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1350 pipe_ctx->stream_res.opp,
1351 &stream->bit_depth_params,
1352 &stream->clamping);
1353
1354 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1355 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1356 pipe_ctx->stream_res.stream_enc,
1357 &stream->timing,
1358 stream->output_color_space);
1359
1360 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1361 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1362 pipe_ctx->stream_res.stream_enc,
1363 &stream->timing,
1364 stream->phy_pix_clk,
1365 pipe_ctx->stream_res.audio != NULL);
1366
1367 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1368 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1369 pipe_ctx->stream_res.stream_enc,
1370 &stream->timing,
1371 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1372 true : false);
1373
1374 resource_build_info_frame(pipe_ctx);
1375 dce110_update_info_frame(pipe_ctx);
1376 if (!pipe_ctx_old->stream) {
1377 if (!pipe_ctx->stream->dpms_off)
1378 core_link_enable_stream(context, pipe_ctx);
1379 }
1380
1381 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1382
1383 pipe_ctx->stream->sink->link->psr_enabled = false;
1384
1385 return DC_OK;
1386 }
1387
1388 /******************************************************************************/
1389
1390 static void power_down_encoders(struct dc *dc)
1391 {
1392 int i;
1393 enum connector_id connector_id;
1394 enum signal_type signal = SIGNAL_TYPE_NONE;
1395
1396 /* do not know BIOS back-front mapping, simply blank all. It will not
1397 * hurt for non-DP
1398 */
1399 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1400 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1401 dc->res_pool->stream_enc[i]);
1402 }
1403
1404 for (i = 0; i < dc->link_count; i++) {
1405 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1406 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1407 (connector_id == CONNECTOR_ID_EDP)) {
1408
1409 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1410 dp_receiver_power_ctrl(dc->links[i], false);
1411 if (connector_id == CONNECTOR_ID_EDP)
1412 signal = SIGNAL_TYPE_EDP;
1413 }
1414
1415 dc->links[i]->link_enc->funcs->disable_output(
1416 dc->links[i]->link_enc, signal);
1417 }
1418 }
1419
1420 static void power_down_controllers(struct dc *dc)
1421 {
1422 int i;
1423
1424 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1425 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1426 dc->res_pool->timing_generators[i]);
1427 }
1428 }
1429
1430 static void power_down_clock_sources(struct dc *dc)
1431 {
1432 int i;
1433
1434 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1435 dc->res_pool->dp_clock_source) == false)
1436 dm_error("Failed to power down pll! (dp clk src)\n");
1437
1438 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1439 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1440 dc->res_pool->clock_sources[i]) == false)
1441 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1442 }
1443 }
1444
1445 static void power_down_all_hw_blocks(struct dc *dc)
1446 {
1447 power_down_encoders(dc);
1448
1449 power_down_controllers(dc);
1450
1451 power_down_clock_sources(dc);
1452
1453 #if defined(CONFIG_DRM_AMD_DC_FBC)
1454 if (dc->fbc_compressor)
1455 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1456 #endif
1457 }
1458
1459 static void disable_vga_and_power_gate_all_controllers(
1460 struct dc *dc)
1461 {
1462 int i;
1463 struct timing_generator *tg;
1464 struct dc_context *ctx = dc->ctx;
1465
1466 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1467 tg = dc->res_pool->timing_generators[i];
1468
1469 if (tg->funcs->disable_vga)
1470 tg->funcs->disable_vga(tg);
1471
1472 /* Enable CLOCK gating for each pipe BEFORE controller
1473 * powergating. */
1474 enable_display_pipe_clock_gating(ctx,
1475 true);
1476
1477 dc->hwss.power_down_front_end(dc, i);
1478 }
1479 }
1480
1481 /**
1482 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1483 * 1. Power down all DC HW blocks
1484 * 2. Disable VGA engine on all controllers
1485 * 3. Enable power gating for controller
1486 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1487 */
1488 void dce110_enable_accelerated_mode(struct dc *dc)
1489 {
1490 power_down_all_hw_blocks(dc);
1491
1492 disable_vga_and_power_gate_all_controllers(dc);
1493 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1494 }
1495
1496 static uint32_t compute_pstate_blackout_duration(
1497 struct bw_fixed blackout_duration,
1498 const struct dc_stream_state *stream)
1499 {
1500 uint32_t total_dest_line_time_ns;
1501 uint32_t pstate_blackout_duration_ns;
1502
1503 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1504
1505 total_dest_line_time_ns = 1000000UL *
1506 stream->timing.h_total /
1507 stream->timing.pix_clk_khz +
1508 pstate_blackout_duration_ns;
1509
1510 return total_dest_line_time_ns;
1511 }
1512
1513 void dce110_set_displaymarks(
1514 const struct dc *dc,
1515 struct dc_state *context)
1516 {
1517 uint8_t i, num_pipes;
1518 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1519
1520 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1521 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1522 uint32_t total_dest_line_time_ns;
1523
1524 if (pipe_ctx->stream == NULL)
1525 continue;
1526
1527 total_dest_line_time_ns = compute_pstate_blackout_duration(
1528 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1529 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1530 pipe_ctx->plane_res.mi,
1531 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1532 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1533 context->bw.dce.urgent_wm_ns[num_pipes],
1534 total_dest_line_time_ns);
1535 if (i == underlay_idx) {
1536 num_pipes++;
1537 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1538 pipe_ctx->plane_res.mi,
1539 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1540 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1541 context->bw.dce.urgent_wm_ns[num_pipes],
1542 total_dest_line_time_ns);
1543 }
1544 num_pipes++;
1545 }
1546 }
1547
1548 static void set_safe_displaymarks(
1549 struct resource_context *res_ctx,
1550 const struct resource_pool *pool)
1551 {
1552 int i;
1553 int underlay_idx = pool->underlay_pipe_index;
1554 struct dce_watermarks max_marks = {
1555 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1556 struct dce_watermarks nbp_marks = {
1557 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1558
1559 for (i = 0; i < MAX_PIPES; i++) {
1560 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1561 continue;
1562
1563 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1564 res_ctx->pipe_ctx[i].plane_res.mi,
1565 nbp_marks,
1566 max_marks,
1567 max_marks,
1568 MAX_WATERMARK);
1569
1570 if (i == underlay_idx)
1571 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1572 res_ctx->pipe_ctx[i].plane_res.mi,
1573 nbp_marks,
1574 max_marks,
1575 max_marks,
1576 MAX_WATERMARK);
1577
1578 }
1579 }
1580
1581 /*******************************************************************************
1582 * Public functions
1583 ******************************************************************************/
1584
1585 static void set_drr(struct pipe_ctx **pipe_ctx,
1586 int num_pipes, int vmin, int vmax)
1587 {
1588 int i = 0;
1589 struct drr_params params = {0};
1590
1591 params.vertical_total_max = vmax;
1592 params.vertical_total_min = vmin;
1593
1594 /* TODO: If multiple pipes are to be supported, you need
1595 * some GSL stuff
1596 */
1597
1598 for (i = 0; i < num_pipes; i++) {
1599 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1600 }
1601 }
1602
1603 static void get_position(struct pipe_ctx **pipe_ctx,
1604 int num_pipes,
1605 struct crtc_position *position)
1606 {
1607 int i = 0;
1608
1609 /* TODO: handle pipes > 1
1610 */
1611 for (i = 0; i < num_pipes; i++)
1612 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1613 }
1614
1615 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1616 int num_pipes, const struct dc_static_screen_events *events)
1617 {
1618 unsigned int i;
1619 unsigned int value = 0;
1620
1621 if (events->overlay_update)
1622 value |= 0x100;
1623 if (events->surface_update)
1624 value |= 0x80;
1625 if (events->cursor_update)
1626 value |= 0x2;
1627
1628 #if defined(CONFIG_DRM_AMD_DC_FBC)
1629 value |= 0x84;
1630 #endif
1631
1632 for (i = 0; i < num_pipes; i++)
1633 pipe_ctx[i]->stream_res.tg->funcs->
1634 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1635 }
1636
1637 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1638 * may not be programmed yet.
1639 * TODO: after mode set, pre_mode_set = false,
1640 * may read PLL register to get pixel clock
1641 */
1642 static uint32_t get_max_pixel_clock_for_all_paths(
1643 struct dc *dc,
1644 struct dc_state *context,
1645 bool pre_mode_set)
1646 {
1647 uint32_t max_pix_clk = 0;
1648 int i;
1649
1650 if (!pre_mode_set) {
1651 /* TODO: read ASIC register to get pixel clock */
1652 ASSERT(0);
1653 }
1654
1655 for (i = 0; i < MAX_PIPES; i++) {
1656 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1657
1658 if (pipe_ctx->stream == NULL)
1659 continue;
1660
1661 /* do not check under lay */
1662 if (pipe_ctx->top_pipe)
1663 continue;
1664
1665 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1666 max_pix_clk =
1667 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1668 }
1669
1670 if (max_pix_clk == 0)
1671 ASSERT(0);
1672
1673 return max_pix_clk;
1674 }
1675
1676 /*
1677 * Find clock state based on clock requested. if clock value is 0, simply
1678 * set clock state as requested without finding clock state by clock value
1679 */
1680
1681 static void apply_min_clocks(
1682 struct dc *dc,
1683 struct dc_state *context,
1684 enum dm_pp_clocks_state *clocks_state,
1685 bool pre_mode_set)
1686 {
1687 struct state_dependent_clocks req_clocks = {0};
1688
1689 if (!pre_mode_set) {
1690 /* set clock_state without verification */
1691 if (context->dis_clk->funcs->set_min_clocks_state) {
1692 context->dis_clk->funcs->set_min_clocks_state(
1693 context->dis_clk, *clocks_state);
1694 return;
1695 }
1696
1697 /* TODO: This is incorrect. Figure out how to fix. */
1698 context->dis_clk->funcs->apply_clock_voltage_request(
1699 context->dis_clk,
1700 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1701 context->dis_clk->cur_clocks_value.dispclk_in_khz,
1702 pre_mode_set,
1703 false);
1704
1705 context->dis_clk->funcs->apply_clock_voltage_request(
1706 context->dis_clk,
1707 DM_PP_CLOCK_TYPE_PIXELCLK,
1708 context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1709 pre_mode_set,
1710 false);
1711
1712 context->dis_clk->funcs->apply_clock_voltage_request(
1713 context->dis_clk,
1714 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1715 context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1716 pre_mode_set,
1717 false);
1718 return;
1719 }
1720
1721 /* get the required state based on state dependent clocks:
1722 * display clock and pixel clock
1723 */
1724 req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1725
1726 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1727 dc, context, true);
1728
1729 if (context->dis_clk->funcs->get_required_clocks_state) {
1730 *clocks_state = context->dis_clk->funcs->get_required_clocks_state(
1731 context->dis_clk, &req_clocks);
1732 context->dis_clk->funcs->set_min_clocks_state(
1733 context->dis_clk, *clocks_state);
1734 } else {
1735 context->dis_clk->funcs->apply_clock_voltage_request(
1736 context->dis_clk,
1737 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1738 req_clocks.display_clk_khz,
1739 pre_mode_set,
1740 false);
1741
1742 context->dis_clk->funcs->apply_clock_voltage_request(
1743 context->dis_clk,
1744 DM_PP_CLOCK_TYPE_PIXELCLK,
1745 req_clocks.pixel_clk_khz,
1746 pre_mode_set,
1747 false);
1748
1749 context->dis_clk->funcs->apply_clock_voltage_request(
1750 context->dis_clk,
1751 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1752 req_clocks.pixel_clk_khz,
1753 pre_mode_set,
1754 false);
1755 }
1756 }
1757
1758 #if defined(CONFIG_DRM_AMD_DC_FBC)
1759
1760 /*
1761 * Check if FBC can be enabled
1762 */
1763 static enum dc_status validate_fbc(struct dc *dc,
1764 struct dc_state *context)
1765 {
1766 struct pipe_ctx *pipe_ctx =
1767 &context->res_ctx.pipe_ctx[0];
1768
1769 ASSERT(dc->fbc_compressor);
1770
1771 /* FBC memory should be allocated */
1772 if (!dc->ctx->fbc_gpu_addr)
1773 return DC_ERROR_UNEXPECTED;
1774
1775 /* Only supports single display */
1776 if (context->stream_count != 1)
1777 return DC_ERROR_UNEXPECTED;
1778
1779 /* Only supports eDP */
1780 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1781 return DC_ERROR_UNEXPECTED;
1782
1783 /* PSR should not be enabled */
1784 if (pipe_ctx->stream->sink->link->psr_enabled)
1785 return DC_ERROR_UNEXPECTED;
1786
1787 /* Nothing to compress */
1788 if (!pipe_ctx->plane_state)
1789 return DC_ERROR_UNEXPECTED;
1790
1791 /* Only for non-linear tiling */
1792 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1793 return DC_ERROR_UNEXPECTED;
1794
1795 return DC_OK;
1796 }
1797
1798 /*
1799 * Enable FBC
1800 */
1801 static enum dc_status enable_fbc(struct dc *dc,
1802 struct dc_state *context)
1803 {
1804 enum dc_status status = validate_fbc(dc, context);
1805
1806 if (status == DC_OK) {
1807 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1808 struct compr_addr_and_pitch_params params = {0, 0, 0};
1809 struct compressor *compr = dc->fbc_compressor;
1810 struct pipe_ctx *pipe_ctx =
1811 &context->res_ctx.pipe_ctx[0];
1812
1813 params.source_view_width =
1814 pipe_ctx->stream->timing.h_addressable;
1815 params.source_view_height =
1816 pipe_ctx->stream->timing.v_addressable;
1817
1818 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1819
1820 compr->funcs->surface_address_and_pitch(compr, &params);
1821 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1822
1823 compr->funcs->enable_fbc(compr, &params);
1824 }
1825 return status;
1826 }
1827 #endif
1828
1829 static enum dc_status apply_ctx_to_hw_fpga(
1830 struct dc *dc,
1831 struct dc_state *context)
1832 {
1833 enum dc_status status = DC_ERROR_UNEXPECTED;
1834 int i;
1835
1836 for (i = 0; i < MAX_PIPES; i++) {
1837 struct pipe_ctx *pipe_ctx_old =
1838 &dc->current_state->res_ctx.pipe_ctx[i];
1839 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1840
1841 if (pipe_ctx->stream == NULL)
1842 continue;
1843
1844 if (pipe_ctx->stream == pipe_ctx_old->stream)
1845 continue;
1846
1847 status = apply_single_controller_ctx_to_hw(
1848 pipe_ctx,
1849 context,
1850 dc);
1851
1852 if (status != DC_OK)
1853 return status;
1854 }
1855
1856 return DC_OK;
1857 }
1858
1859 static void dce110_reset_hw_ctx_wrap(
1860 struct dc *dc,
1861 struct dc_state *context)
1862 {
1863 int i;
1864
1865 /* Reset old context */
1866 /* look up the targets that have been removed since last commit */
1867 for (i = 0; i < MAX_PIPES; i++) {
1868 struct pipe_ctx *pipe_ctx_old =
1869 &dc->current_state->res_ctx.pipe_ctx[i];
1870 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1871
1872 /* Note: We need to disable output if clock sources change,
1873 * since bios does optimization and doesn't apply if changing
1874 * PHY when not already disabled.
1875 */
1876
1877 /* Skip underlay pipe since it will be handled in commit surface*/
1878 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1879 continue;
1880
1881 if (!pipe_ctx->stream ||
1882 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1883 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1884
1885 /* Disable if new stream is null. O/w, if stream is
1886 * disabled already, no need to disable again.
1887 */
1888 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1889 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1890
1891 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1892 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1893 dm_error("DC: failed to blank crtc!\n");
1894 BREAK_TO_DEBUGGER();
1895 }
1896 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1897 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1898 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1899
1900 if (old_clk)
1901 old_clk->funcs->cs_power_down(old_clk);
1902
1903 dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
1904
1905 pipe_ctx_old->stream = NULL;
1906 }
1907 }
1908 }
1909
1910
1911 enum dc_status dce110_apply_ctx_to_hw(
1912 struct dc *dc,
1913 struct dc_state *context)
1914 {
1915 struct dc_bios *dcb = dc->ctx->dc_bios;
1916 enum dc_status status;
1917 int i;
1918 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1919
1920 /* Reset old context */
1921 /* look up the targets that have been removed since last commit */
1922 dc->hwss.reset_hw_ctx_wrap(dc, context);
1923
1924 /* Skip applying if no targets */
1925 if (context->stream_count <= 0)
1926 return DC_OK;
1927
1928 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1929 apply_ctx_to_hw_fpga(dc, context);
1930 return DC_OK;
1931 }
1932
1933 /* Apply new context */
1934 dcb->funcs->set_scratch_critical_state(dcb, true);
1935
1936 /* below is for real asic only */
1937 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1938 struct pipe_ctx *pipe_ctx_old =
1939 &dc->current_state->res_ctx.pipe_ctx[i];
1940 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1941
1942 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1943 continue;
1944
1945 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1946 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1947 dce_crtc_switch_to_clk_src(dc->hwseq,
1948 pipe_ctx->clock_source, i);
1949 continue;
1950 }
1951
1952 dc->hwss.enable_display_power_gating(
1953 dc, i, dc->ctx->dc_bios,
1954 PIPE_GATING_CONTROL_DISABLE);
1955 }
1956
1957 set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1958
1959 #if defined(CONFIG_DRM_AMD_DC_FBC)
1960 if (dc->fbc_compressor)
1961 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1962 #endif
1963 /*TODO: when pplib works*/
1964 apply_min_clocks(dc, context, &clocks_state, true);
1965
1966 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1967 if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1968 if (context->bw.dcn.calc_clk.fclk_khz
1969 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
1970 struct dm_pp_clock_for_voltage_req clock;
1971
1972 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1973 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1974 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1975 dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1976 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1977 }
1978 if (context->bw.dcn.calc_clk.dcfclk_khz
1979 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
1980 struct dm_pp_clock_for_voltage_req clock;
1981
1982 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1983 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1984 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1985 dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1986 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1987 }
1988 if (context->bw.dcn.calc_clk.dispclk_khz
1989 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
1990 dc->res_pool->display_clock->funcs->set_clock(
1991 dc->res_pool->display_clock,
1992 context->bw.dcn.calc_clk.dispclk_khz);
1993 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
1994 context->bw.dcn.calc_clk.dispclk_khz;
1995 context->bw.dcn.cur_clk.dispclk_khz =
1996 context->bw.dcn.calc_clk.dispclk_khz;
1997 }
1998 } else
1999 #endif
2000 if (context->bw.dce.dispclk_khz
2001 > dc->current_state->bw.dce.dispclk_khz) {
2002 dc->res_pool->display_clock->funcs->set_clock(
2003 dc->res_pool->display_clock,
2004 context->bw.dce.dispclk_khz * 115 / 100);
2005 }
2006 /* program audio wall clock. use HDMI as clock source if HDMI
2007 * audio active. Otherwise, use DP as clock source
2008 * first, loop to find any HDMI audio, if not, loop find DP audio
2009 */
2010 /* Setup audio rate clock source */
2011 /* Issue:
2012 * Audio lag happened on DP monitor when unplug a HDMI monitor
2013 *
2014 * Cause:
2015 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2016 * is set to either dto0 or dto1, audio should work fine.
2017 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2018 * set to dto0 will cause audio lag.
2019 *
2020 * Solution:
2021 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2022 * find first available pipe with audio, setup audio wall DTO per topology
2023 * instead of per pipe.
2024 */
2025 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2026 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2027
2028 if (pipe_ctx->stream == NULL)
2029 continue;
2030
2031 if (pipe_ctx->top_pipe)
2032 continue;
2033
2034 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2035 continue;
2036
2037 if (pipe_ctx->stream_res.audio != NULL) {
2038 struct audio_output audio_output;
2039
2040 build_audio_output(context, pipe_ctx, &audio_output);
2041
2042 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2043 pipe_ctx->stream_res.audio,
2044 pipe_ctx->stream->signal,
2045 &audio_output.crtc_info,
2046 &audio_output.pll_info);
2047 break;
2048 }
2049 }
2050
2051 /* no HDMI audio is found, try DP audio */
2052 if (i == dc->res_pool->pipe_count) {
2053 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2054 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2055
2056 if (pipe_ctx->stream == NULL)
2057 continue;
2058
2059 if (pipe_ctx->top_pipe)
2060 continue;
2061
2062 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2063 continue;
2064
2065 if (pipe_ctx->stream_res.audio != NULL) {
2066 struct audio_output audio_output;
2067
2068 build_audio_output(context, pipe_ctx, &audio_output);
2069
2070 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2071 pipe_ctx->stream_res.audio,
2072 pipe_ctx->stream->signal,
2073 &audio_output.crtc_info,
2074 &audio_output.pll_info);
2075 break;
2076 }
2077 }
2078 }
2079
2080 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2081 struct pipe_ctx *pipe_ctx_old =
2082 &dc->current_state->res_ctx.pipe_ctx[i];
2083 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2084
2085 if (pipe_ctx->stream == NULL)
2086 continue;
2087
2088 if (pipe_ctx->stream == pipe_ctx_old->stream)
2089 continue;
2090
2091 if (pipe_ctx->stream && pipe_ctx_old->stream
2092 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2093 continue;
2094
2095 if (pipe_ctx->top_pipe)
2096 continue;
2097
2098 if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
2099
2100 struct audio_output audio_output;
2101
2102 build_audio_output(context, pipe_ctx, &audio_output);
2103
2104 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2105 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
2106 pipe_ctx->stream_res.stream_enc,
2107 pipe_ctx->stream_res.audio->inst,
2108 &pipe_ctx->stream->audio_info);
2109 else
2110 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
2111 pipe_ctx->stream_res.stream_enc,
2112 pipe_ctx->stream_res.audio->inst,
2113 &pipe_ctx->stream->audio_info,
2114 &audio_output.crtc_info);
2115
2116 pipe_ctx->stream_res.audio->funcs->az_configure(
2117 pipe_ctx->stream_res.audio,
2118 pipe_ctx->stream->signal,
2119 &audio_output.crtc_info,
2120 &pipe_ctx->stream->audio_info);
2121 }
2122
2123 status = apply_single_controller_ctx_to_hw(
2124 pipe_ctx,
2125 context,
2126 dc);
2127
2128 if (dc->hwss.power_on_front_end)
2129 dc->hwss.power_on_front_end(dc, pipe_ctx, context);
2130
2131 if (DC_OK != status)
2132 return status;
2133 }
2134
2135 /* pplib is notified if disp_num changed */
2136 dc->hwss.set_bandwidth(dc, context, true);
2137
2138 /* to save power */
2139 apply_min_clocks(dc, context, &clocks_state, false);
2140
2141 dcb->funcs->set_scratch_critical_state(dcb, false);
2142
2143 #if defined(CONFIG_DRM_AMD_DC_FBC)
2144 if (dc->fbc_compressor)
2145 enable_fbc(dc, context);
2146
2147 #endif
2148
2149 return DC_OK;
2150 }
2151
2152 /*******************************************************************************
2153 * Front End programming
2154 ******************************************************************************/
2155 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2156 {
2157 struct default_adjustment default_adjust = { 0 };
2158
2159 default_adjust.force_hw_default = false;
2160 if (pipe_ctx->plane_state == NULL)
2161 default_adjust.in_color_space = COLOR_SPACE_SRGB;
2162 else
2163 default_adjust.in_color_space =
2164 pipe_ctx->plane_state->color_space;
2165 if (pipe_ctx->stream == NULL)
2166 default_adjust.out_color_space = COLOR_SPACE_SRGB;
2167 else
2168 default_adjust.out_color_space =
2169 pipe_ctx->stream->output_color_space;
2170 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2171 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2172
2173 /* display color depth */
2174 default_adjust.color_depth =
2175 pipe_ctx->stream->timing.display_color_depth;
2176
2177 /* Lb color depth */
2178 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2179
2180 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2181 pipe_ctx->plane_res.xfm, &default_adjust);
2182 }
2183
2184
2185 /*******************************************************************************
2186 * In order to turn on/off specific surface we will program
2187 * Blender + CRTC
2188 *
2189 * In case that we have two surfaces and they have a different visibility
2190 * we can't turn off the CRTC since it will turn off the entire display
2191 *
2192 * |----------------------------------------------- |
2193 * |bottom pipe|curr pipe | | |
2194 * |Surface |Surface | Blender | CRCT |
2195 * |visibility |visibility | Configuration| |
2196 * |------------------------------------------------|
2197 * | off | off | CURRENT_PIPE | blank |
2198 * | off | on | CURRENT_PIPE | unblank |
2199 * | on | off | OTHER_PIPE | unblank |
2200 * | on | on | BLENDING | unblank |
2201 * -------------------------------------------------|
2202 *
2203 ******************************************************************************/
2204 static void program_surface_visibility(const struct dc *dc,
2205 struct pipe_ctx *pipe_ctx)
2206 {
2207 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2208 bool blank_target = false;
2209
2210 if (pipe_ctx->bottom_pipe) {
2211
2212 /* For now we are supporting only two pipes */
2213 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2214
2215 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2216 if (pipe_ctx->plane_state->visible)
2217 blender_mode = BLND_MODE_BLENDING;
2218 else
2219 blender_mode = BLND_MODE_OTHER_PIPE;
2220
2221 } else if (!pipe_ctx->plane_state->visible)
2222 blank_target = true;
2223
2224 } else if (!pipe_ctx->plane_state->visible)
2225 blank_target = true;
2226
2227 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
2228 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2229
2230 }
2231
2232 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2233 {
2234 struct xfm_grph_csc_adjustment adjust;
2235 memset(&adjust, 0, sizeof(adjust));
2236 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2237
2238
2239 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2240 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2241 adjust.temperature_matrix[0] =
2242 pipe_ctx->stream->
2243 gamut_remap_matrix.matrix[0];
2244 adjust.temperature_matrix[1] =
2245 pipe_ctx->stream->
2246 gamut_remap_matrix.matrix[1];
2247 adjust.temperature_matrix[2] =
2248 pipe_ctx->stream->
2249 gamut_remap_matrix.matrix[2];
2250 adjust.temperature_matrix[3] =
2251 pipe_ctx->stream->
2252 gamut_remap_matrix.matrix[4];
2253 adjust.temperature_matrix[4] =
2254 pipe_ctx->stream->
2255 gamut_remap_matrix.matrix[5];
2256 adjust.temperature_matrix[5] =
2257 pipe_ctx->stream->
2258 gamut_remap_matrix.matrix[6];
2259 adjust.temperature_matrix[6] =
2260 pipe_ctx->stream->
2261 gamut_remap_matrix.matrix[8];
2262 adjust.temperature_matrix[7] =
2263 pipe_ctx->stream->
2264 gamut_remap_matrix.matrix[9];
2265 adjust.temperature_matrix[8] =
2266 pipe_ctx->stream->
2267 gamut_remap_matrix.matrix[10];
2268 }
2269
2270 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2271 }
2272
2273 /**
2274 * TODO REMOVE, USE UPDATE INSTEAD
2275 */
2276 static void set_plane_config(
2277 const struct dc *dc,
2278 struct pipe_ctx *pipe_ctx,
2279 struct resource_context *res_ctx)
2280 {
2281 struct mem_input *mi = pipe_ctx->plane_res.mi;
2282 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2283 struct xfm_grph_csc_adjustment adjust;
2284 struct out_csc_color_matrix tbl_entry;
2285 unsigned int i;
2286
2287 memset(&adjust, 0, sizeof(adjust));
2288 memset(&tbl_entry, 0, sizeof(tbl_entry));
2289 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2290
2291 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2292
2293 set_default_colors(pipe_ctx);
2294 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2295 == true) {
2296 tbl_entry.color_space =
2297 pipe_ctx->stream->output_color_space;
2298
2299 for (i = 0; i < 12; i++)
2300 tbl_entry.regval[i] =
2301 pipe_ctx->stream->csc_color_matrix.matrix[i];
2302
2303 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2304 (pipe_ctx->plane_res.xfm, &tbl_entry);
2305 }
2306
2307 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2308 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2309 adjust.temperature_matrix[0] =
2310 pipe_ctx->stream->
2311 gamut_remap_matrix.matrix[0];
2312 adjust.temperature_matrix[1] =
2313 pipe_ctx->stream->
2314 gamut_remap_matrix.matrix[1];
2315 adjust.temperature_matrix[2] =
2316 pipe_ctx->stream->
2317 gamut_remap_matrix.matrix[2];
2318 adjust.temperature_matrix[3] =
2319 pipe_ctx->stream->
2320 gamut_remap_matrix.matrix[4];
2321 adjust.temperature_matrix[4] =
2322 pipe_ctx->stream->
2323 gamut_remap_matrix.matrix[5];
2324 adjust.temperature_matrix[5] =
2325 pipe_ctx->stream->
2326 gamut_remap_matrix.matrix[6];
2327 adjust.temperature_matrix[6] =
2328 pipe_ctx->stream->
2329 gamut_remap_matrix.matrix[8];
2330 adjust.temperature_matrix[7] =
2331 pipe_ctx->stream->
2332 gamut_remap_matrix.matrix[9];
2333 adjust.temperature_matrix[8] =
2334 pipe_ctx->stream->
2335 gamut_remap_matrix.matrix[10];
2336 }
2337
2338 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2339
2340 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2341 program_scaler(dc, pipe_ctx);
2342
2343 program_surface_visibility(dc, pipe_ctx);
2344
2345 mi->funcs->mem_input_program_surface_config(
2346 mi,
2347 plane_state->format,
2348 &plane_state->tiling_info,
2349 &plane_state->plane_size,
2350 plane_state->rotation,
2351 NULL,
2352 false);
2353 if (mi->funcs->set_blank)
2354 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2355
2356 if (dc->config.gpu_vm_support)
2357 mi->funcs->mem_input_program_pte_vm(
2358 pipe_ctx->plane_res.mi,
2359 plane_state->format,
2360 &plane_state->tiling_info,
2361 plane_state->rotation);
2362 }
2363
2364 static void update_plane_addr(const struct dc *dc,
2365 struct pipe_ctx *pipe_ctx)
2366 {
2367 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2368
2369 if (plane_state == NULL)
2370 return;
2371
2372 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2373 pipe_ctx->plane_res.mi,
2374 &plane_state->address,
2375 plane_state->flip_immediate);
2376
2377 plane_state->status.requested_address = plane_state->address;
2378 }
2379
2380 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2381 {
2382 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2383
2384 if (plane_state == NULL)
2385 return;
2386
2387 plane_state->status.is_flip_pending =
2388 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2389 pipe_ctx->plane_res.mi);
2390
2391 if (plane_state->status.is_flip_pending && !plane_state->visible)
2392 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2393
2394 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2395 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2396 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2397 plane_state->status.is_right_eye =\
2398 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2399 }
2400 }
2401
2402 void dce110_power_down(struct dc *dc)
2403 {
2404 power_down_all_hw_blocks(dc);
2405 disable_vga_and_power_gate_all_controllers(dc);
2406 }
2407
2408 static bool wait_for_reset_trigger_to_occur(
2409 struct dc_context *dc_ctx,
2410 struct timing_generator *tg)
2411 {
2412 bool rc = false;
2413
2414 /* To avoid endless loop we wait at most
2415 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2416 const uint32_t frames_to_wait_on_triggered_reset = 10;
2417 uint32_t i;
2418
2419 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2420
2421 if (!tg->funcs->is_counter_moving(tg)) {
2422 DC_ERROR("TG counter is not moving!\n");
2423 break;
2424 }
2425
2426 if (tg->funcs->did_triggered_reset_occur(tg)) {
2427 rc = true;
2428 /* usually occurs at i=1 */
2429 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2430 i);
2431 break;
2432 }
2433
2434 /* Wait for one frame. */
2435 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2436 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2437 }
2438
2439 if (false == rc)
2440 DC_ERROR("GSL: Timeout on reset trigger!\n");
2441
2442 return rc;
2443 }
2444
2445 /* Enable timing synchronization for a group of Timing Generators. */
2446 static void dce110_enable_timing_synchronization(
2447 struct dc *dc,
2448 int group_index,
2449 int group_size,
2450 struct pipe_ctx *grouped_pipes[])
2451 {
2452 struct dc_context *dc_ctx = dc->ctx;
2453 struct dcp_gsl_params gsl_params = { 0 };
2454 int i;
2455
2456 DC_SYNC_INFO("GSL: Setting-up...\n");
2457
2458 /* Designate a single TG in the group as a master.
2459 * Since HW doesn't care which one, we always assign
2460 * the 1st one in the group. */
2461 gsl_params.gsl_group = 0;
2462 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2463
2464 for (i = 0; i < group_size; i++)
2465 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2466 grouped_pipes[i]->stream_res.tg, &gsl_params);
2467
2468 /* Reset slave controllers on master VSync */
2469 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2470
2471 for (i = 1 /* skip the master */; i < group_size; i++)
2472 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2473 grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
2474
2475
2476
2477 for (i = 1 /* skip the master */; i < group_size; i++) {
2478 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2479 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2480 /* Regardless of success of the wait above, remove the reset or
2481 * the driver will start timing out on Display requests. */
2482 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2483 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
2484 }
2485
2486
2487 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2488 * is that the sync'ed displays will not drift out of sync over time*/
2489 DC_SYNC_INFO("GSL: Restoring register states.\n");
2490 for (i = 0; i < group_size; i++)
2491 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2492
2493 DC_SYNC_INFO("GSL: Set-up complete.\n");
2494 }
2495
2496 static void init_hw(struct dc *dc)
2497 {
2498 int i;
2499 struct dc_bios *bp;
2500 struct transform *xfm;
2501 struct abm *abm;
2502
2503 bp = dc->ctx->dc_bios;
2504 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2505 xfm = dc->res_pool->transforms[i];
2506 xfm->funcs->transform_reset(xfm);
2507
2508 dc->hwss.enable_display_power_gating(
2509 dc, i, bp,
2510 PIPE_GATING_CONTROL_INIT);
2511 dc->hwss.enable_display_power_gating(
2512 dc, i, bp,
2513 PIPE_GATING_CONTROL_DISABLE);
2514 dc->hwss.enable_display_pipe_clock_gating(
2515 dc->ctx,
2516 true);
2517 }
2518
2519 dce_clock_gating_power_up(dc->hwseq, false);
2520 /***************************************/
2521
2522 for (i = 0; i < dc->link_count; i++) {
2523 /****************************************/
2524 /* Power up AND update implementation according to the
2525 * required signal (which may be different from the
2526 * default signal on connector). */
2527 struct dc_link *link = dc->links[i];
2528
2529 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2530 dc->hwss.edp_power_control(link, true);
2531
2532 link->link_enc->funcs->hw_init(link->link_enc);
2533 }
2534
2535 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2536 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2537
2538 tg->funcs->disable_vga(tg);
2539
2540 /* Blank controller using driver code instead of
2541 * command table. */
2542 tg->funcs->set_blank(tg, true);
2543 hwss_wait_for_blank_complete(tg);
2544 }
2545
2546 for (i = 0; i < dc->res_pool->audio_count; i++) {
2547 struct audio *audio = dc->res_pool->audios[i];
2548 audio->funcs->hw_init(audio);
2549 }
2550
2551 abm = dc->res_pool->abm;
2552 if (abm != NULL) {
2553 abm->funcs->init_backlight(abm);
2554 abm->funcs->abm_init(abm);
2555 }
2556 #if defined(CONFIG_DRM_AMD_DC_FBC)
2557 if (dc->fbc_compressor)
2558 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2559 #endif
2560
2561 }
2562
2563 void dce110_fill_display_configs(
2564 const struct dc_state *context,
2565 struct dm_pp_display_configuration *pp_display_cfg)
2566 {
2567 int j;
2568 int num_cfgs = 0;
2569
2570 for (j = 0; j < context->stream_count; j++) {
2571 int k;
2572
2573 const struct dc_stream_state *stream = context->streams[j];
2574 struct dm_pp_single_disp_config *cfg =
2575 &pp_display_cfg->disp_configs[num_cfgs];
2576 const struct pipe_ctx *pipe_ctx = NULL;
2577
2578 for (k = 0; k < MAX_PIPES; k++)
2579 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2580 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2581 break;
2582 }
2583
2584 ASSERT(pipe_ctx != NULL);
2585
2586 num_cfgs++;
2587 cfg->signal = pipe_ctx->stream->signal;
2588 cfg->pipe_idx = pipe_ctx->pipe_idx;
2589 cfg->src_height = stream->src.height;
2590 cfg->src_width = stream->src.width;
2591 cfg->ddi_channel_mapping =
2592 stream->sink->link->ddi_channel_mapping.raw;
2593 cfg->transmitter =
2594 stream->sink->link->link_enc->transmitter;
2595 cfg->link_settings.lane_count =
2596 stream->sink->link->cur_link_settings.lane_count;
2597 cfg->link_settings.link_rate =
2598 stream->sink->link->cur_link_settings.link_rate;
2599 cfg->link_settings.link_spread =
2600 stream->sink->link->cur_link_settings.link_spread;
2601 cfg->sym_clock = stream->phy_pix_clk;
2602 /* Round v_refresh*/
2603 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2604 cfg->v_refresh /= stream->timing.h_total;
2605 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2606 / stream->timing.v_total;
2607 }
2608
2609 pp_display_cfg->display_count = num_cfgs;
2610 }
2611
2612 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
2613 {
2614 uint8_t j;
2615 uint32_t min_vertical_blank_time = -1;
2616
2617 for (j = 0; j < context->stream_count; j++) {
2618 struct dc_stream_state *stream = context->streams[j];
2619 uint32_t vertical_blank_in_pixels = 0;
2620 uint32_t vertical_blank_time = 0;
2621
2622 vertical_blank_in_pixels = stream->timing.h_total *
2623 (stream->timing.v_total
2624 - stream->timing.v_addressable);
2625
2626 vertical_blank_time = vertical_blank_in_pixels
2627 * 1000 / stream->timing.pix_clk_khz;
2628
2629 if (min_vertical_blank_time > vertical_blank_time)
2630 min_vertical_blank_time = vertical_blank_time;
2631 }
2632
2633 return min_vertical_blank_time;
2634 }
2635
2636 static int determine_sclk_from_bounding_box(
2637 const struct dc *dc,
2638 int required_sclk)
2639 {
2640 int i;
2641
2642 /*
2643 * Some asics do not give us sclk levels, so we just report the actual
2644 * required sclk
2645 */
2646 if (dc->sclk_lvls.num_levels == 0)
2647 return required_sclk;
2648
2649 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2650 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2651 return dc->sclk_lvls.clocks_in_khz[i];
2652 }
2653 /*
2654 * even maximum level could not satisfy requirement, this
2655 * is unexpected at this stage, should have been caught at
2656 * validation time
2657 */
2658 ASSERT(0);
2659 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2660 }
2661
2662 static void pplib_apply_display_requirements(
2663 struct dc *dc,
2664 struct dc_state *context)
2665 {
2666 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2667
2668 pp_display_cfg->all_displays_in_sync =
2669 context->bw.dce.all_displays_in_sync;
2670 pp_display_cfg->nb_pstate_switch_disable =
2671 context->bw.dce.nbp_state_change_enable == false;
2672 pp_display_cfg->cpu_cc6_disable =
2673 context->bw.dce.cpuc_state_change_enable == false;
2674 pp_display_cfg->cpu_pstate_disable =
2675 context->bw.dce.cpup_state_change_enable == false;
2676 pp_display_cfg->cpu_pstate_separation_time =
2677 context->bw.dce.blackout_recovery_time_us;
2678
2679 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2680 / MEMORY_TYPE_MULTIPLIER;
2681
2682 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2683 dc,
2684 context->bw.dce.sclk_khz);
2685
2686 pp_display_cfg->min_engine_clock_deep_sleep_khz
2687 = context->bw.dce.sclk_deep_sleep_khz;
2688
2689 pp_display_cfg->avail_mclk_switch_time_us =
2690 dce110_get_min_vblank_time_us(context);
2691 /* TODO: dce11.2*/
2692 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2693
2694 pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2695
2696 dce110_fill_display_configs(context, pp_display_cfg);
2697
2698 /* TODO: is this still applicable?*/
2699 if (pp_display_cfg->display_count == 1) {
2700 const struct dc_crtc_timing *timing =
2701 &context->streams[0]->timing;
2702
2703 pp_display_cfg->crtc_index =
2704 pp_display_cfg->disp_configs[0].pipe_idx;
2705 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2706 / timing->pix_clk_khz;
2707 }
2708
2709 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2710 struct dm_pp_display_configuration)) != 0)
2711 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2712
2713 dc->prev_display_config = *pp_display_cfg;
2714 }
2715
2716 static void dce110_set_bandwidth(
2717 struct dc *dc,
2718 struct dc_state *context,
2719 bool decrease_allowed)
2720 {
2721 dce110_set_displaymarks(dc, context);
2722
2723 if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
2724 dc->res_pool->display_clock->funcs->set_clock(
2725 dc->res_pool->display_clock,
2726 context->bw.dce.dispclk_khz * 115 / 100);
2727 dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2728 }
2729
2730 pplib_apply_display_requirements(dc, context);
2731 }
2732
2733 static void dce110_program_front_end_for_pipe(
2734 struct dc *dc, struct pipe_ctx *pipe_ctx)
2735 {
2736 struct mem_input *mi = pipe_ctx->plane_res.mi;
2737 struct pipe_ctx *old_pipe = NULL;
2738 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2739 struct xfm_grph_csc_adjustment adjust;
2740 struct out_csc_color_matrix tbl_entry;
2741 struct pipe_ctx *cur_pipe_ctx =
2742 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2743 unsigned int i;
2744
2745 memset(&tbl_entry, 0, sizeof(tbl_entry));
2746
2747 if (dc->current_state)
2748 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2749
2750 memset(&adjust, 0, sizeof(adjust));
2751 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2752
2753 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2754
2755 set_default_colors(pipe_ctx);
2756 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2757 == true) {
2758 tbl_entry.color_space =
2759 pipe_ctx->stream->output_color_space;
2760
2761 for (i = 0; i < 12; i++)
2762 tbl_entry.regval[i] =
2763 pipe_ctx->stream->csc_color_matrix.matrix[i];
2764
2765 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2766 (pipe_ctx->plane_res.xfm, &tbl_entry);
2767 }
2768
2769 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2770 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2771 adjust.temperature_matrix[0] =
2772 pipe_ctx->stream->
2773 gamut_remap_matrix.matrix[0];
2774 adjust.temperature_matrix[1] =
2775 pipe_ctx->stream->
2776 gamut_remap_matrix.matrix[1];
2777 adjust.temperature_matrix[2] =
2778 pipe_ctx->stream->
2779 gamut_remap_matrix.matrix[2];
2780 adjust.temperature_matrix[3] =
2781 pipe_ctx->stream->
2782 gamut_remap_matrix.matrix[4];
2783 adjust.temperature_matrix[4] =
2784 pipe_ctx->stream->
2785 gamut_remap_matrix.matrix[5];
2786 adjust.temperature_matrix[5] =
2787 pipe_ctx->stream->
2788 gamut_remap_matrix.matrix[6];
2789 adjust.temperature_matrix[6] =
2790 pipe_ctx->stream->
2791 gamut_remap_matrix.matrix[8];
2792 adjust.temperature_matrix[7] =
2793 pipe_ctx->stream->
2794 gamut_remap_matrix.matrix[9];
2795 adjust.temperature_matrix[8] =
2796 pipe_ctx->stream->
2797 gamut_remap_matrix.matrix[10];
2798 }
2799
2800 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2801
2802 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2803
2804 program_scaler(dc, pipe_ctx);
2805
2806 #if defined(CONFIG_DRM_AMD_DC_FBC)
2807 if (dc->fbc_compressor && old_pipe->stream) {
2808 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2809 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2810 else
2811 enable_fbc(dc, dc->current_state);
2812 }
2813 #endif
2814
2815 mi->funcs->mem_input_program_surface_config(
2816 mi,
2817 plane_state->format,
2818 &plane_state->tiling_info,
2819 &plane_state->plane_size,
2820 plane_state->rotation,
2821 NULL,
2822 false);
2823 if (mi->funcs->set_blank)
2824 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2825
2826 if (dc->config.gpu_vm_support)
2827 mi->funcs->mem_input_program_pte_vm(
2828 pipe_ctx->plane_res.mi,
2829 plane_state->format,
2830 &plane_state->tiling_info,
2831 plane_state->rotation);
2832
2833 /* Moved programming gamma from dc to hwss */
2834 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
2835 dc->hwss.set_input_transfer_func(
2836 pipe_ctx, pipe_ctx->plane_state);
2837 dc->hwss.set_output_transfer_func(
2838 pipe_ctx, pipe_ctx->stream);
2839 }
2840
2841 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2842 "Pipe:%d 0x%x: addr hi:0x%x, "
2843 "addr low:0x%x, "
2844 "src: %d, %d, %d,"
2845 " %d; dst: %d, %d, %d, %d;"
2846 "clip: %d, %d, %d, %d\n",
2847 pipe_ctx->pipe_idx,
2848 pipe_ctx->plane_state,
2849 pipe_ctx->plane_state->address.grph.addr.high_part,
2850 pipe_ctx->plane_state->address.grph.addr.low_part,
2851 pipe_ctx->plane_state->src_rect.x,
2852 pipe_ctx->plane_state->src_rect.y,
2853 pipe_ctx->plane_state->src_rect.width,
2854 pipe_ctx->plane_state->src_rect.height,
2855 pipe_ctx->plane_state->dst_rect.x,
2856 pipe_ctx->plane_state->dst_rect.y,
2857 pipe_ctx->plane_state->dst_rect.width,
2858 pipe_ctx->plane_state->dst_rect.height,
2859 pipe_ctx->plane_state->clip_rect.x,
2860 pipe_ctx->plane_state->clip_rect.y,
2861 pipe_ctx->plane_state->clip_rect.width,
2862 pipe_ctx->plane_state->clip_rect.height);
2863
2864 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2865 "Pipe %d: width, height, x, y\n"
2866 "viewport:%d, %d, %d, %d\n"
2867 "recout: %d, %d, %d, %d\n",
2868 pipe_ctx->pipe_idx,
2869 pipe_ctx->plane_res.scl_data.viewport.width,
2870 pipe_ctx->plane_res.scl_data.viewport.height,
2871 pipe_ctx->plane_res.scl_data.viewport.x,
2872 pipe_ctx->plane_res.scl_data.viewport.y,
2873 pipe_ctx->plane_res.scl_data.recout.width,
2874 pipe_ctx->plane_res.scl_data.recout.height,
2875 pipe_ctx->plane_res.scl_data.recout.x,
2876 pipe_ctx->plane_res.scl_data.recout.y);
2877 }
2878
2879 static void dce110_apply_ctx_for_surface(
2880 struct dc *dc,
2881 const struct dc_stream_state *stream,
2882 int num_planes,
2883 struct dc_state *context)
2884 {
2885 int i;
2886
2887 if (num_planes == 0)
2888 return;
2889
2890 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2891 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2892 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2893
2894 if (stream == pipe_ctx->stream) {
2895 if (!pipe_ctx->top_pipe &&
2896 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2897 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2898 }
2899 }
2900
2901 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2902 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2903
2904 if (pipe_ctx->stream != stream)
2905 continue;
2906
2907 /* Need to allocate mem before program front end for Fiji */
2908 if (pipe_ctx->plane_res.mi != NULL)
2909 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2910 pipe_ctx->plane_res.mi,
2911 pipe_ctx->stream->timing.h_total,
2912 pipe_ctx->stream->timing.v_total,
2913 pipe_ctx->stream->timing.pix_clk_khz,
2914 context->stream_count);
2915
2916 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2917
2918 dc->hwss.update_plane_addr(dc, pipe_ctx);
2919
2920 program_surface_visibility(dc, pipe_ctx);
2921
2922 }
2923
2924 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2925 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2926 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2927
2928 if ((stream == pipe_ctx->stream) &&
2929 (!pipe_ctx->top_pipe) &&
2930 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2931 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2932 }
2933 }
2934
2935 static void dce110_power_down_fe(struct dc *dc, int fe_idx)
2936 {
2937 /* Do not power down fe when stream is active on dce*/
2938 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2939 return;
2940
2941 dc->hwss.enable_display_power_gating(
2942 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2943
2944 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2945 dc->res_pool->transforms[fe_idx]);
2946 }
2947
2948 static void dce110_wait_for_mpcc_disconnect(
2949 struct dc *dc,
2950 struct resource_pool *res_pool,
2951 struct pipe_ctx *pipe_ctx)
2952 {
2953 /* do nothing*/
2954 }
2955
2956 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2957 enum dc_color_space colorspace,
2958 uint16_t *matrix)
2959 {
2960 int i;
2961 struct out_csc_color_matrix tbl_entry;
2962
2963 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2964 == true) {
2965 enum dc_color_space color_space =
2966 pipe_ctx->stream->output_color_space;
2967
2968 //uint16_t matrix[12];
2969 for (i = 0; i < 12; i++)
2970 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2971
2972 tbl_entry.color_space = color_space;
2973 //tbl_entry.regval = matrix;
2974 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2975 }
2976 }
2977
2978 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2979
2980 static void optimize_shared_resources(struct dc *dc) {}
2981
2982 static const struct hw_sequencer_funcs dce110_funcs = {
2983 .program_gamut_remap = program_gamut_remap,
2984 .program_csc_matrix = program_csc_matrix,
2985 .init_hw = init_hw,
2986 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2987 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2988 .set_plane_config = set_plane_config,
2989 .update_plane_addr = update_plane_addr,
2990 .update_pending_status = dce110_update_pending_status,
2991 .set_input_transfer_func = dce110_set_input_transfer_func,
2992 .set_output_transfer_func = dce110_set_output_transfer_func,
2993 .power_down = dce110_power_down,
2994 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2995 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2996 .update_info_frame = dce110_update_info_frame,
2997 .enable_stream = dce110_enable_stream,
2998 .disable_stream = dce110_disable_stream,
2999 .unblank_stream = dce110_unblank_stream,
3000 .blank_stream = dce110_blank_stream,
3001 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3002 .enable_display_power_gating = dce110_enable_display_power_gating,
3003 .power_down_front_end = dce110_power_down_fe,
3004 .pipe_control_lock = dce_pipe_control_lock,
3005 .set_bandwidth = dce110_set_bandwidth,
3006 .set_drr = set_drr,
3007 .get_position = get_position,
3008 .set_static_screen_control = set_static_screen_control,
3009 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3010 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
3011 .setup_stereo = NULL,
3012 .set_avmute = dce110_set_avmute,
3013 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3014 .ready_shared_resources = ready_shared_resources,
3015 .optimize_shared_resources = optimize_shared_resources,
3016 .edp_backlight_control = hwss_edp_backlight_control,
3017 .edp_power_control = hwss_edp_power_control,
3018 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
3019 };
3020
3021 void dce110_hw_sequencer_construct(struct dc *dc)
3022 {
3023 dc->hwss = dce110_funcs;
3024 }
3025
ubuntu-bionic-kernel mirror