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drm/i915: Record the default hw state after reset upon load
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/debugfs.h>
30 #include <linux/sort.h>
31 #include <linux/sched/mm.h>
32 #include "intel_drv.h"
33 #include "i915_guc_submission.h"
34
35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
36 {
37 return to_i915(node->minor->dev);
38 }
39
40 static __always_inline void seq_print_param(struct seq_file *m,
41 const char *name,
42 const char *type,
43 const void *x)
44 {
45 if (!__builtin_strcmp(type, "bool"))
46 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
47 else if (!__builtin_strcmp(type, "int"))
48 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
49 else if (!__builtin_strcmp(type, "unsigned int"))
50 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
51 else if (!__builtin_strcmp(type, "char *"))
52 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
53 else
54 BUILD_BUG();
55 }
56
57 static int i915_capabilities(struct seq_file *m, void *data)
58 {
59 struct drm_i915_private *dev_priv = node_to_i915(m->private);
60 const struct intel_device_info *info = INTEL_INFO(dev_priv);
61
62 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
63 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
64 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
65
66 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
67 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
68 #undef PRINT_FLAG
69
70 kernel_param_lock(THIS_MODULE);
71 #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
72 I915_PARAMS_FOR_EACH(PRINT_PARAM);
73 #undef PRINT_PARAM
74 kernel_param_unlock(THIS_MODULE);
75
76 return 0;
77 }
78
79 static char get_active_flag(struct drm_i915_gem_object *obj)
80 {
81 return i915_gem_object_is_active(obj) ? '*' : ' ';
82 }
83
84 static char get_pin_flag(struct drm_i915_gem_object *obj)
85 {
86 return obj->pin_global ? 'p' : ' ';
87 }
88
89 static char get_tiling_flag(struct drm_i915_gem_object *obj)
90 {
91 switch (i915_gem_object_get_tiling(obj)) {
92 default:
93 case I915_TILING_NONE: return ' ';
94 case I915_TILING_X: return 'X';
95 case I915_TILING_Y: return 'Y';
96 }
97 }
98
99 static char get_global_flag(struct drm_i915_gem_object *obj)
100 {
101 return obj->userfault_count ? 'g' : ' ';
102 }
103
104 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
105 {
106 return obj->mm.mapping ? 'M' : ' ';
107 }
108
109 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
110 {
111 u64 size = 0;
112 struct i915_vma *vma;
113
114 list_for_each_entry(vma, &obj->vma_list, obj_link) {
115 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
116 size += vma->node.size;
117 }
118
119 return size;
120 }
121
122 static const char *
123 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
124 {
125 size_t x = 0;
126
127 switch (page_sizes) {
128 case 0:
129 return "";
130 case I915_GTT_PAGE_SIZE_4K:
131 return "4K";
132 case I915_GTT_PAGE_SIZE_64K:
133 return "64K";
134 case I915_GTT_PAGE_SIZE_2M:
135 return "2M";
136 default:
137 if (!buf)
138 return "M";
139
140 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
141 x += snprintf(buf + x, len - x, "2M, ");
142 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
143 x += snprintf(buf + x, len - x, "64K, ");
144 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
145 x += snprintf(buf + x, len - x, "4K, ");
146 buf[x-2] = '\0';
147
148 return buf;
149 }
150 }
151
152 static void
153 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
154 {
155 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
156 struct intel_engine_cs *engine;
157 struct i915_vma *vma;
158 unsigned int frontbuffer_bits;
159 int pin_count = 0;
160
161 lockdep_assert_held(&obj->base.dev->struct_mutex);
162
163 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
164 &obj->base,
165 get_active_flag(obj),
166 get_pin_flag(obj),
167 get_tiling_flag(obj),
168 get_global_flag(obj),
169 get_pin_mapped_flag(obj),
170 obj->base.size / 1024,
171 obj->base.read_domains,
172 obj->base.write_domain,
173 i915_cache_level_str(dev_priv, obj->cache_level),
174 obj->mm.dirty ? " dirty" : "",
175 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
176 if (obj->base.name)
177 seq_printf(m, " (name: %d)", obj->base.name);
178 list_for_each_entry(vma, &obj->vma_list, obj_link) {
179 if (i915_vma_is_pinned(vma))
180 pin_count++;
181 }
182 seq_printf(m, " (pinned x %d)", pin_count);
183 if (obj->pin_global)
184 seq_printf(m, " (global)");
185 list_for_each_entry(vma, &obj->vma_list, obj_link) {
186 if (!drm_mm_node_allocated(&vma->node))
187 continue;
188
189 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
190 i915_vma_is_ggtt(vma) ? "g" : "pp",
191 vma->node.start, vma->node.size,
192 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
193 if (i915_vma_is_ggtt(vma)) {
194 switch (vma->ggtt_view.type) {
195 case I915_GGTT_VIEW_NORMAL:
196 seq_puts(m, ", normal");
197 break;
198
199 case I915_GGTT_VIEW_PARTIAL:
200 seq_printf(m, ", partial [%08llx+%x]",
201 vma->ggtt_view.partial.offset << PAGE_SHIFT,
202 vma->ggtt_view.partial.size << PAGE_SHIFT);
203 break;
204
205 case I915_GGTT_VIEW_ROTATED:
206 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
207 vma->ggtt_view.rotated.plane[0].width,
208 vma->ggtt_view.rotated.plane[0].height,
209 vma->ggtt_view.rotated.plane[0].stride,
210 vma->ggtt_view.rotated.plane[0].offset,
211 vma->ggtt_view.rotated.plane[1].width,
212 vma->ggtt_view.rotated.plane[1].height,
213 vma->ggtt_view.rotated.plane[1].stride,
214 vma->ggtt_view.rotated.plane[1].offset);
215 break;
216
217 default:
218 MISSING_CASE(vma->ggtt_view.type);
219 break;
220 }
221 }
222 if (vma->fence)
223 seq_printf(m, " , fence: %d%s",
224 vma->fence->id,
225 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
226 seq_puts(m, ")");
227 }
228 if (obj->stolen)
229 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
230
231 engine = i915_gem_object_last_write_engine(obj);
232 if (engine)
233 seq_printf(m, " (%s)", engine->name);
234
235 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
236 if (frontbuffer_bits)
237 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
238 }
239
240 static int obj_rank_by_stolen(const void *A, const void *B)
241 {
242 const struct drm_i915_gem_object *a =
243 *(const struct drm_i915_gem_object **)A;
244 const struct drm_i915_gem_object *b =
245 *(const struct drm_i915_gem_object **)B;
246
247 if (a->stolen->start < b->stolen->start)
248 return -1;
249 if (a->stolen->start > b->stolen->start)
250 return 1;
251 return 0;
252 }
253
254 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
255 {
256 struct drm_i915_private *dev_priv = node_to_i915(m->private);
257 struct drm_device *dev = &dev_priv->drm;
258 struct drm_i915_gem_object **objects;
259 struct drm_i915_gem_object *obj;
260 u64 total_obj_size, total_gtt_size;
261 unsigned long total, count, n;
262 int ret;
263
264 total = READ_ONCE(dev_priv->mm.object_count);
265 objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
266 if (!objects)
267 return -ENOMEM;
268
269 ret = mutex_lock_interruptible(&dev->struct_mutex);
270 if (ret)
271 goto out;
272
273 total_obj_size = total_gtt_size = count = 0;
274
275 spin_lock(&dev_priv->mm.obj_lock);
276 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
277 if (count == total)
278 break;
279
280 if (obj->stolen == NULL)
281 continue;
282
283 objects[count++] = obj;
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
289 if (count == total)
290 break;
291
292 if (obj->stolen == NULL)
293 continue;
294
295 objects[count++] = obj;
296 total_obj_size += obj->base.size;
297 }
298 spin_unlock(&dev_priv->mm.obj_lock);
299
300 sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
301
302 seq_puts(m, "Stolen:\n");
303 for (n = 0; n < count; n++) {
304 seq_puts(m, " ");
305 describe_obj(m, objects[n]);
306 seq_putc(m, '\n');
307 }
308 seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310
311 mutex_unlock(&dev->struct_mutex);
312 out:
313 kvfree(objects);
314 return ret;
315 }
316
317 struct file_stats {
318 struct drm_i915_file_private *file_priv;
319 unsigned long count;
320 u64 total, unbound;
321 u64 global, shared;
322 u64 active, inactive;
323 };
324
325 static int per_file_stats(int id, void *ptr, void *data)
326 {
327 struct drm_i915_gem_object *obj = ptr;
328 struct file_stats *stats = data;
329 struct i915_vma *vma;
330
331 lockdep_assert_held(&obj->base.dev->struct_mutex);
332
333 stats->count++;
334 stats->total += obj->base.size;
335 if (!obj->bind_count)
336 stats->unbound += obj->base.size;
337 if (obj->base.name || obj->base.dma_buf)
338 stats->shared += obj->base.size;
339
340 list_for_each_entry(vma, &obj->vma_list, obj_link) {
341 if (!drm_mm_node_allocated(&vma->node))
342 continue;
343
344 if (i915_vma_is_ggtt(vma)) {
345 stats->global += vma->node.size;
346 } else {
347 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
348
349 if (ppgtt->base.file != stats->file_priv)
350 continue;
351 }
352
353 if (i915_vma_is_active(vma))
354 stats->active += vma->node.size;
355 else
356 stats->inactive += vma->node.size;
357 }
358
359 return 0;
360 }
361
362 #define print_file_stats(m, name, stats) do { \
363 if (stats.count) \
364 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
365 name, \
366 stats.count, \
367 stats.total, \
368 stats.active, \
369 stats.inactive, \
370 stats.global, \
371 stats.shared, \
372 stats.unbound); \
373 } while (0)
374
375 static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
377 {
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
380 struct intel_engine_cs *engine;
381 enum intel_engine_id id;
382 int j;
383
384 memset(&stats, 0, sizeof(stats));
385
386 for_each_engine(engine, dev_priv, id) {
387 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
388 list_for_each_entry(obj,
389 &engine->batch_pool.cache_list[j],
390 batch_pool_link)
391 per_file_stats(0, obj, &stats);
392 }
393 }
394
395 print_file_stats(m, "[k]batch pool", stats);
396 }
397
398 static int per_file_ctx_stats(int id, void *ptr, void *data)
399 {
400 struct i915_gem_context *ctx = ptr;
401 int n;
402
403 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
404 if (ctx->engine[n].state)
405 per_file_stats(0, ctx->engine[n].state->obj, data);
406 if (ctx->engine[n].ring)
407 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
408 }
409
410 return 0;
411 }
412
413 static void print_context_stats(struct seq_file *m,
414 struct drm_i915_private *dev_priv)
415 {
416 struct drm_device *dev = &dev_priv->drm;
417 struct file_stats stats;
418 struct drm_file *file;
419
420 memset(&stats, 0, sizeof(stats));
421
422 mutex_lock(&dev->struct_mutex);
423 if (dev_priv->kernel_context)
424 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
425
426 list_for_each_entry(file, &dev->filelist, lhead) {
427 struct drm_i915_file_private *fpriv = file->driver_priv;
428 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
429 }
430 mutex_unlock(&dev->struct_mutex);
431
432 print_file_stats(m, "[k]contexts", stats);
433 }
434
435 static int i915_gem_object_info(struct seq_file *m, void *data)
436 {
437 struct drm_i915_private *dev_priv = node_to_i915(m->private);
438 struct drm_device *dev = &dev_priv->drm;
439 struct i915_ggtt *ggtt = &dev_priv->ggtt;
440 u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
441 u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
442 struct drm_i915_gem_object *obj;
443 unsigned int page_sizes = 0;
444 struct drm_file *file;
445 char buf[80];
446 int ret;
447
448 ret = mutex_lock_interruptible(&dev->struct_mutex);
449 if (ret)
450 return ret;
451
452 seq_printf(m, "%u objects, %llu bytes\n",
453 dev_priv->mm.object_count,
454 dev_priv->mm.object_memory);
455
456 size = count = 0;
457 mapped_size = mapped_count = 0;
458 purgeable_size = purgeable_count = 0;
459 huge_size = huge_count = 0;
460
461 spin_lock(&dev_priv->mm.obj_lock);
462 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
463 size += obj->base.size;
464 ++count;
465
466 if (obj->mm.madv == I915_MADV_DONTNEED) {
467 purgeable_size += obj->base.size;
468 ++purgeable_count;
469 }
470
471 if (obj->mm.mapping) {
472 mapped_count++;
473 mapped_size += obj->base.size;
474 }
475
476 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
477 huge_count++;
478 huge_size += obj->base.size;
479 page_sizes |= obj->mm.page_sizes.sg;
480 }
481 }
482 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
483
484 size = count = dpy_size = dpy_count = 0;
485 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
486 size += obj->base.size;
487 ++count;
488
489 if (obj->pin_global) {
490 dpy_size += obj->base.size;
491 ++dpy_count;
492 }
493
494 if (obj->mm.madv == I915_MADV_DONTNEED) {
495 purgeable_size += obj->base.size;
496 ++purgeable_count;
497 }
498
499 if (obj->mm.mapping) {
500 mapped_count++;
501 mapped_size += obj->base.size;
502 }
503
504 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
505 huge_count++;
506 huge_size += obj->base.size;
507 page_sizes |= obj->mm.page_sizes.sg;
508 }
509 }
510 spin_unlock(&dev_priv->mm.obj_lock);
511
512 seq_printf(m, "%u bound objects, %llu bytes\n",
513 count, size);
514 seq_printf(m, "%u purgeable objects, %llu bytes\n",
515 purgeable_count, purgeable_size);
516 seq_printf(m, "%u mapped objects, %llu bytes\n",
517 mapped_count, mapped_size);
518 seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
519 huge_count,
520 stringify_page_sizes(page_sizes, buf, sizeof(buf)),
521 huge_size);
522 seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
523 dpy_count, dpy_size);
524
525 seq_printf(m, "%llu [%llu] gtt total\n",
526 ggtt->base.total, ggtt->mappable_end);
527 seq_printf(m, "Supported page sizes: %s\n",
528 stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
529 buf, sizeof(buf)));
530
531 seq_putc(m, '\n');
532 print_batch_pool_stats(m, dev_priv);
533 mutex_unlock(&dev->struct_mutex);
534
535 mutex_lock(&dev->filelist_mutex);
536 print_context_stats(m, dev_priv);
537 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
538 struct file_stats stats;
539 struct drm_i915_file_private *file_priv = file->driver_priv;
540 struct drm_i915_gem_request *request;
541 struct task_struct *task;
542
543 mutex_lock(&dev->struct_mutex);
544
545 memset(&stats, 0, sizeof(stats));
546 stats.file_priv = file->driver_priv;
547 spin_lock(&file->table_lock);
548 idr_for_each(&file->object_idr, per_file_stats, &stats);
549 spin_unlock(&file->table_lock);
550 /*
551 * Although we have a valid reference on file->pid, that does
552 * not guarantee that the task_struct who called get_pid() is
553 * still alive (e.g. get_pid(current) => fork() => exit()).
554 * Therefore, we need to protect this ->comm access using RCU.
555 */
556 request = list_first_entry_or_null(&file_priv->mm.request_list,
557 struct drm_i915_gem_request,
558 client_link);
559 rcu_read_lock();
560 task = pid_task(request && request->ctx->pid ?
561 request->ctx->pid : file->pid,
562 PIDTYPE_PID);
563 print_file_stats(m, task ? task->comm : "<unknown>", stats);
564 rcu_read_unlock();
565
566 mutex_unlock(&dev->struct_mutex);
567 }
568 mutex_unlock(&dev->filelist_mutex);
569
570 return 0;
571 }
572
573 static int i915_gem_gtt_info(struct seq_file *m, void *data)
574 {
575 struct drm_info_node *node = m->private;
576 struct drm_i915_private *dev_priv = node_to_i915(node);
577 struct drm_device *dev = &dev_priv->drm;
578 struct drm_i915_gem_object **objects;
579 struct drm_i915_gem_object *obj;
580 u64 total_obj_size, total_gtt_size;
581 unsigned long nobject, n;
582 int count, ret;
583
584 nobject = READ_ONCE(dev_priv->mm.object_count);
585 objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
586 if (!objects)
587 return -ENOMEM;
588
589 ret = mutex_lock_interruptible(&dev->struct_mutex);
590 if (ret)
591 return ret;
592
593 count = 0;
594 spin_lock(&dev_priv->mm.obj_lock);
595 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
596 objects[count++] = obj;
597 if (count == nobject)
598 break;
599 }
600 spin_unlock(&dev_priv->mm.obj_lock);
601
602 total_obj_size = total_gtt_size = 0;
603 for (n = 0; n < count; n++) {
604 obj = objects[n];
605
606 seq_puts(m, " ");
607 describe_obj(m, obj);
608 seq_putc(m, '\n');
609 total_obj_size += obj->base.size;
610 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
611 }
612
613 mutex_unlock(&dev->struct_mutex);
614
615 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
616 count, total_obj_size, total_gtt_size);
617 kvfree(objects);
618
619 return 0;
620 }
621
622 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
623 {
624 struct drm_i915_private *dev_priv = node_to_i915(m->private);
625 struct drm_device *dev = &dev_priv->drm;
626 struct drm_i915_gem_object *obj;
627 struct intel_engine_cs *engine;
628 enum intel_engine_id id;
629 int total = 0;
630 int ret, j;
631
632 ret = mutex_lock_interruptible(&dev->struct_mutex);
633 if (ret)
634 return ret;
635
636 for_each_engine(engine, dev_priv, id) {
637 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
638 int count;
639
640 count = 0;
641 list_for_each_entry(obj,
642 &engine->batch_pool.cache_list[j],
643 batch_pool_link)
644 count++;
645 seq_printf(m, "%s cache[%d]: %d objects\n",
646 engine->name, j, count);
647
648 list_for_each_entry(obj,
649 &engine->batch_pool.cache_list[j],
650 batch_pool_link) {
651 seq_puts(m, " ");
652 describe_obj(m, obj);
653 seq_putc(m, '\n');
654 }
655
656 total += count;
657 }
658 }
659
660 seq_printf(m, "total: %d\n", total);
661
662 mutex_unlock(&dev->struct_mutex);
663
664 return 0;
665 }
666
667 static void i915_ring_seqno_info(struct seq_file *m,
668 struct intel_engine_cs *engine)
669 {
670 struct intel_breadcrumbs *b = &engine->breadcrumbs;
671 struct rb_node *rb;
672
673 seq_printf(m, "Current sequence (%s): %x\n",
674 engine->name, intel_engine_get_seqno(engine));
675
676 spin_lock_irq(&b->rb_lock);
677 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
678 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
679
680 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
681 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
682 }
683 spin_unlock_irq(&b->rb_lock);
684 }
685
686 static int i915_gem_seqno_info(struct seq_file *m, void *data)
687 {
688 struct drm_i915_private *dev_priv = node_to_i915(m->private);
689 struct intel_engine_cs *engine;
690 enum intel_engine_id id;
691
692 for_each_engine(engine, dev_priv, id)
693 i915_ring_seqno_info(m, engine);
694
695 return 0;
696 }
697
698
699 static int i915_interrupt_info(struct seq_file *m, void *data)
700 {
701 struct drm_i915_private *dev_priv = node_to_i915(m->private);
702 struct intel_engine_cs *engine;
703 enum intel_engine_id id;
704 int i, pipe;
705
706 intel_runtime_pm_get(dev_priv);
707
708 if (IS_CHERRYVIEW(dev_priv)) {
709 seq_printf(m, "Master Interrupt Control:\t%08x\n",
710 I915_READ(GEN8_MASTER_IRQ));
711
712 seq_printf(m, "Display IER:\t%08x\n",
713 I915_READ(VLV_IER));
714 seq_printf(m, "Display IIR:\t%08x\n",
715 I915_READ(VLV_IIR));
716 seq_printf(m, "Display IIR_RW:\t%08x\n",
717 I915_READ(VLV_IIR_RW));
718 seq_printf(m, "Display IMR:\t%08x\n",
719 I915_READ(VLV_IMR));
720 for_each_pipe(dev_priv, pipe) {
721 enum intel_display_power_domain power_domain;
722
723 power_domain = POWER_DOMAIN_PIPE(pipe);
724 if (!intel_display_power_get_if_enabled(dev_priv,
725 power_domain)) {
726 seq_printf(m, "Pipe %c power disabled\n",
727 pipe_name(pipe));
728 continue;
729 }
730
731 seq_printf(m, "Pipe %c stat:\t%08x\n",
732 pipe_name(pipe),
733 I915_READ(PIPESTAT(pipe)));
734
735 intel_display_power_put(dev_priv, power_domain);
736 }
737
738 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
739 seq_printf(m, "Port hotplug:\t%08x\n",
740 I915_READ(PORT_HOTPLUG_EN));
741 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
742 I915_READ(VLV_DPFLIPSTAT));
743 seq_printf(m, "DPINVGTT:\t%08x\n",
744 I915_READ(DPINVGTT));
745 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
746
747 for (i = 0; i < 4; i++) {
748 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
749 i, I915_READ(GEN8_GT_IMR(i)));
750 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
751 i, I915_READ(GEN8_GT_IIR(i)));
752 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
753 i, I915_READ(GEN8_GT_IER(i)));
754 }
755
756 seq_printf(m, "PCU interrupt mask:\t%08x\n",
757 I915_READ(GEN8_PCU_IMR));
758 seq_printf(m, "PCU interrupt identity:\t%08x\n",
759 I915_READ(GEN8_PCU_IIR));
760 seq_printf(m, "PCU interrupt enable:\t%08x\n",
761 I915_READ(GEN8_PCU_IER));
762 } else if (INTEL_GEN(dev_priv) >= 8) {
763 seq_printf(m, "Master Interrupt Control:\t%08x\n",
764 I915_READ(GEN8_MASTER_IRQ));
765
766 for (i = 0; i < 4; i++) {
767 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
768 i, I915_READ(GEN8_GT_IMR(i)));
769 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
770 i, I915_READ(GEN8_GT_IIR(i)));
771 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
772 i, I915_READ(GEN8_GT_IER(i)));
773 }
774
775 for_each_pipe(dev_priv, pipe) {
776 enum intel_display_power_domain power_domain;
777
778 power_domain = POWER_DOMAIN_PIPE(pipe);
779 if (!intel_display_power_get_if_enabled(dev_priv,
780 power_domain)) {
781 seq_printf(m, "Pipe %c power disabled\n",
782 pipe_name(pipe));
783 continue;
784 }
785 seq_printf(m, "Pipe %c IMR:\t%08x\n",
786 pipe_name(pipe),
787 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
788 seq_printf(m, "Pipe %c IIR:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
791 seq_printf(m, "Pipe %c IER:\t%08x\n",
792 pipe_name(pipe),
793 I915_READ(GEN8_DE_PIPE_IER(pipe)));
794
795 intel_display_power_put(dev_priv, power_domain);
796 }
797
798 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_PORT_IMR));
800 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_PORT_IIR));
802 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_PORT_IER));
804
805 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
806 I915_READ(GEN8_DE_MISC_IMR));
807 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
808 I915_READ(GEN8_DE_MISC_IIR));
809 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
810 I915_READ(GEN8_DE_MISC_IER));
811
812 seq_printf(m, "PCU interrupt mask:\t%08x\n",
813 I915_READ(GEN8_PCU_IMR));
814 seq_printf(m, "PCU interrupt identity:\t%08x\n",
815 I915_READ(GEN8_PCU_IIR));
816 seq_printf(m, "PCU interrupt enable:\t%08x\n",
817 I915_READ(GEN8_PCU_IER));
818 } else if (IS_VALLEYVIEW(dev_priv)) {
819 seq_printf(m, "Display IER:\t%08x\n",
820 I915_READ(VLV_IER));
821 seq_printf(m, "Display IIR:\t%08x\n",
822 I915_READ(VLV_IIR));
823 seq_printf(m, "Display IIR_RW:\t%08x\n",
824 I915_READ(VLV_IIR_RW));
825 seq_printf(m, "Display IMR:\t%08x\n",
826 I915_READ(VLV_IMR));
827 for_each_pipe(dev_priv, pipe) {
828 enum intel_display_power_domain power_domain;
829
830 power_domain = POWER_DOMAIN_PIPE(pipe);
831 if (!intel_display_power_get_if_enabled(dev_priv,
832 power_domain)) {
833 seq_printf(m, "Pipe %c power disabled\n",
834 pipe_name(pipe));
835 continue;
836 }
837
838 seq_printf(m, "Pipe %c stat:\t%08x\n",
839 pipe_name(pipe),
840 I915_READ(PIPESTAT(pipe)));
841 intel_display_power_put(dev_priv, power_domain);
842 }
843
844 seq_printf(m, "Master IER:\t%08x\n",
845 I915_READ(VLV_MASTER_IER));
846
847 seq_printf(m, "Render IER:\t%08x\n",
848 I915_READ(GTIER));
849 seq_printf(m, "Render IIR:\t%08x\n",
850 I915_READ(GTIIR));
851 seq_printf(m, "Render IMR:\t%08x\n",
852 I915_READ(GTIMR));
853
854 seq_printf(m, "PM IER:\t\t%08x\n",
855 I915_READ(GEN6_PMIER));
856 seq_printf(m, "PM IIR:\t\t%08x\n",
857 I915_READ(GEN6_PMIIR));
858 seq_printf(m, "PM IMR:\t\t%08x\n",
859 I915_READ(GEN6_PMIMR));
860
861 seq_printf(m, "Port hotplug:\t%08x\n",
862 I915_READ(PORT_HOTPLUG_EN));
863 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
864 I915_READ(VLV_DPFLIPSTAT));
865 seq_printf(m, "DPINVGTT:\t%08x\n",
866 I915_READ(DPINVGTT));
867
868 } else if (!HAS_PCH_SPLIT(dev_priv)) {
869 seq_printf(m, "Interrupt enable: %08x\n",
870 I915_READ(IER));
871 seq_printf(m, "Interrupt identity: %08x\n",
872 I915_READ(IIR));
873 seq_printf(m, "Interrupt mask: %08x\n",
874 I915_READ(IMR));
875 for_each_pipe(dev_priv, pipe)
876 seq_printf(m, "Pipe %c stat: %08x\n",
877 pipe_name(pipe),
878 I915_READ(PIPESTAT(pipe)));
879 } else {
880 seq_printf(m, "North Display Interrupt enable: %08x\n",
881 I915_READ(DEIER));
882 seq_printf(m, "North Display Interrupt identity: %08x\n",
883 I915_READ(DEIIR));
884 seq_printf(m, "North Display Interrupt mask: %08x\n",
885 I915_READ(DEIMR));
886 seq_printf(m, "South Display Interrupt enable: %08x\n",
887 I915_READ(SDEIER));
888 seq_printf(m, "South Display Interrupt identity: %08x\n",
889 I915_READ(SDEIIR));
890 seq_printf(m, "South Display Interrupt mask: %08x\n",
891 I915_READ(SDEIMR));
892 seq_printf(m, "Graphics Interrupt enable: %08x\n",
893 I915_READ(GTIER));
894 seq_printf(m, "Graphics Interrupt identity: %08x\n",
895 I915_READ(GTIIR));
896 seq_printf(m, "Graphics Interrupt mask: %08x\n",
897 I915_READ(GTIMR));
898 }
899 for_each_engine(engine, dev_priv, id) {
900 if (INTEL_GEN(dev_priv) >= 6) {
901 seq_printf(m,
902 "Graphics Interrupt mask (%s): %08x\n",
903 engine->name, I915_READ_IMR(engine));
904 }
905 i915_ring_seqno_info(m, engine);
906 }
907 intel_runtime_pm_put(dev_priv);
908
909 return 0;
910 }
911
912 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
913 {
914 struct drm_i915_private *dev_priv = node_to_i915(m->private);
915 struct drm_device *dev = &dev_priv->drm;
916 int i, ret;
917
918 ret = mutex_lock_interruptible(&dev->struct_mutex);
919 if (ret)
920 return ret;
921
922 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
923 for (i = 0; i < dev_priv->num_fence_regs; i++) {
924 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
925
926 seq_printf(m, "Fence %d, pin count = %d, object = ",
927 i, dev_priv->fence_regs[i].pin_count);
928 if (!vma)
929 seq_puts(m, "unused");
930 else
931 describe_obj(m, vma->obj);
932 seq_putc(m, '\n');
933 }
934
935 mutex_unlock(&dev->struct_mutex);
936 return 0;
937 }
938
939 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
940 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
941 size_t count, loff_t *pos)
942 {
943 struct i915_gpu_state *error = file->private_data;
944 struct drm_i915_error_state_buf str;
945 ssize_t ret;
946 loff_t tmp;
947
948 if (!error)
949 return 0;
950
951 ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
952 if (ret)
953 return ret;
954
955 ret = i915_error_state_to_str(&str, error);
956 if (ret)
957 goto out;
958
959 tmp = 0;
960 ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
961 if (ret < 0)
962 goto out;
963
964 *pos = str.start + ret;
965 out:
966 i915_error_state_buf_release(&str);
967 return ret;
968 }
969
970 static int gpu_state_release(struct inode *inode, struct file *file)
971 {
972 i915_gpu_state_put(file->private_data);
973 return 0;
974 }
975
976 static int i915_gpu_info_open(struct inode *inode, struct file *file)
977 {
978 struct drm_i915_private *i915 = inode->i_private;
979 struct i915_gpu_state *gpu;
980
981 intel_runtime_pm_get(i915);
982 gpu = i915_capture_gpu_state(i915);
983 intel_runtime_pm_put(i915);
984 if (!gpu)
985 return -ENOMEM;
986
987 file->private_data = gpu;
988 return 0;
989 }
990
991 static const struct file_operations i915_gpu_info_fops = {
992 .owner = THIS_MODULE,
993 .open = i915_gpu_info_open,
994 .read = gpu_state_read,
995 .llseek = default_llseek,
996 .release = gpu_state_release,
997 };
998
999 static ssize_t
1000 i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1002 size_t cnt,
1003 loff_t *ppos)
1004 {
1005 struct i915_gpu_state *error = filp->private_data;
1006
1007 if (!error)
1008 return 0;
1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011 i915_reset_error_state(error->i915);
1012
1013 return cnt;
1014 }
1015
1016 static int i915_error_state_open(struct inode *inode, struct file *file)
1017 {
1018 file->private_data = i915_first_error_state(inode->i_private);
1019 return 0;
1020 }
1021
1022 static const struct file_operations i915_error_state_fops = {
1023 .owner = THIS_MODULE,
1024 .open = i915_error_state_open,
1025 .read = gpu_state_read,
1026 .write = i915_error_state_write,
1027 .llseek = default_llseek,
1028 .release = gpu_state_release,
1029 };
1030 #endif
1031
1032 static int
1033 i915_next_seqno_set(void *data, u64 val)
1034 {
1035 struct drm_i915_private *dev_priv = data;
1036 struct drm_device *dev = &dev_priv->drm;
1037 int ret;
1038
1039 ret = mutex_lock_interruptible(&dev->struct_mutex);
1040 if (ret)
1041 return ret;
1042
1043 ret = i915_gem_set_global_seqno(dev, val);
1044 mutex_unlock(&dev->struct_mutex);
1045
1046 return ret;
1047 }
1048
1049 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1050 NULL, i915_next_seqno_set,
1051 "0x%llx\n");
1052
1053 static int i915_frequency_info(struct seq_file *m, void *unused)
1054 {
1055 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1056 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1057 int ret = 0;
1058
1059 intel_runtime_pm_get(dev_priv);
1060
1061 if (IS_GEN5(dev_priv)) {
1062 u16 rgvswctl = I915_READ16(MEMSWCTL);
1063 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1064
1065 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1066 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1067 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1068 MEMSTAT_VID_SHIFT);
1069 seq_printf(m, "Current P-state: %d\n",
1070 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1071 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1072 u32 rpmodectl, freq_sts;
1073
1074 mutex_lock(&dev_priv->pcu_lock);
1075
1076 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1077 seq_printf(m, "Video Turbo Mode: %s\n",
1078 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1079 seq_printf(m, "HW control enabled: %s\n",
1080 yesno(rpmodectl & GEN6_RP_ENABLE));
1081 seq_printf(m, "SW control enabled: %s\n",
1082 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1083 GEN6_RP_MEDIA_SW_MODE));
1084
1085 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1086 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1087 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1088
1089 seq_printf(m, "actual GPU freq: %d MHz\n",
1090 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1091
1092 seq_printf(m, "current GPU freq: %d MHz\n",
1093 intel_gpu_freq(dev_priv, rps->cur_freq));
1094
1095 seq_printf(m, "max GPU freq: %d MHz\n",
1096 intel_gpu_freq(dev_priv, rps->max_freq));
1097
1098 seq_printf(m, "min GPU freq: %d MHz\n",
1099 intel_gpu_freq(dev_priv, rps->min_freq));
1100
1101 seq_printf(m, "idle GPU freq: %d MHz\n",
1102 intel_gpu_freq(dev_priv, rps->idle_freq));
1103
1104 seq_printf(m,
1105 "efficient (RPe) frequency: %d MHz\n",
1106 intel_gpu_freq(dev_priv, rps->efficient_freq));
1107 mutex_unlock(&dev_priv->pcu_lock);
1108 } else if (INTEL_GEN(dev_priv) >= 6) {
1109 u32 rp_state_limits;
1110 u32 gt_perf_status;
1111 u32 rp_state_cap;
1112 u32 rpmodectl, rpinclimit, rpdeclimit;
1113 u32 rpstat, cagf, reqf;
1114 u32 rpupei, rpcurup, rpprevup;
1115 u32 rpdownei, rpcurdown, rpprevdown;
1116 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1117 int max_freq;
1118
1119 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1120 if (IS_GEN9_LP(dev_priv)) {
1121 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1122 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1123 } else {
1124 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1125 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1126 }
1127
1128 /* RPSTAT1 is in the GT power well */
1129 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1130
1131 reqf = I915_READ(GEN6_RPNSWREQ);
1132 if (INTEL_GEN(dev_priv) >= 9)
1133 reqf >>= 23;
1134 else {
1135 reqf &= ~GEN6_TURBO_DISABLE;
1136 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1137 reqf >>= 24;
1138 else
1139 reqf >>= 25;
1140 }
1141 reqf = intel_gpu_freq(dev_priv, reqf);
1142
1143 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1144 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1145 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1146
1147 rpstat = I915_READ(GEN6_RPSTAT1);
1148 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1149 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1150 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1151 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1152 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1153 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1154 if (INTEL_GEN(dev_priv) >= 9)
1155 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1156 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1157 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1158 else
1159 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1160 cagf = intel_gpu_freq(dev_priv, cagf);
1161
1162 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1163
1164 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1165 pm_ier = I915_READ(GEN6_PMIER);
1166 pm_imr = I915_READ(GEN6_PMIMR);
1167 pm_isr = I915_READ(GEN6_PMISR);
1168 pm_iir = I915_READ(GEN6_PMIIR);
1169 pm_mask = I915_READ(GEN6_PMINTRMSK);
1170 } else {
1171 pm_ier = I915_READ(GEN8_GT_IER(2));
1172 pm_imr = I915_READ(GEN8_GT_IMR(2));
1173 pm_isr = I915_READ(GEN8_GT_ISR(2));
1174 pm_iir = I915_READ(GEN8_GT_IIR(2));
1175 pm_mask = I915_READ(GEN6_PMINTRMSK);
1176 }
1177 seq_printf(m, "Video Turbo Mode: %s\n",
1178 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1179 seq_printf(m, "HW control enabled: %s\n",
1180 yesno(rpmodectl & GEN6_RP_ENABLE));
1181 seq_printf(m, "SW control enabled: %s\n",
1182 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1183 GEN6_RP_MEDIA_SW_MODE));
1184 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1185 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1186 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1187 rps->pm_intrmsk_mbz);
1188 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1189 seq_printf(m, "Render p-state ratio: %d\n",
1190 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1191 seq_printf(m, "Render p-state VID: %d\n",
1192 gt_perf_status & 0xff);
1193 seq_printf(m, "Render p-state limit: %d\n",
1194 rp_state_limits & 0xff);
1195 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1196 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1197 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1198 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1199 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1200 seq_printf(m, "CAGF: %dMHz\n", cagf);
1201 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1202 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1203 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1204 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1205 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1206 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1207 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1208
1209 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1210 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1211 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1212 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1213 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1214 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1215 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1216
1217 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1218 rp_state_cap >> 16) & 0xff;
1219 max_freq *= (IS_GEN9_BC(dev_priv) ||
1220 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1221 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1222 intel_gpu_freq(dev_priv, max_freq));
1223
1224 max_freq = (rp_state_cap & 0xff00) >> 8;
1225 max_freq *= (IS_GEN9_BC(dev_priv) ||
1226 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1227 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1228 intel_gpu_freq(dev_priv, max_freq));
1229
1230 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1231 rp_state_cap >> 0) & 0xff;
1232 max_freq *= (IS_GEN9_BC(dev_priv) ||
1233 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1234 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1235 intel_gpu_freq(dev_priv, max_freq));
1236 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1237 intel_gpu_freq(dev_priv, rps->max_freq));
1238
1239 seq_printf(m, "Current freq: %d MHz\n",
1240 intel_gpu_freq(dev_priv, rps->cur_freq));
1241 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1242 seq_printf(m, "Idle freq: %d MHz\n",
1243 intel_gpu_freq(dev_priv, rps->idle_freq));
1244 seq_printf(m, "Min freq: %d MHz\n",
1245 intel_gpu_freq(dev_priv, rps->min_freq));
1246 seq_printf(m, "Boost freq: %d MHz\n",
1247 intel_gpu_freq(dev_priv, rps->boost_freq));
1248 seq_printf(m, "Max freq: %d MHz\n",
1249 intel_gpu_freq(dev_priv, rps->max_freq));
1250 seq_printf(m,
1251 "efficient (RPe) frequency: %d MHz\n",
1252 intel_gpu_freq(dev_priv, rps->efficient_freq));
1253 } else {
1254 seq_puts(m, "no P-state info available\n");
1255 }
1256
1257 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1258 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1259 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1260
1261 intel_runtime_pm_put(dev_priv);
1262 return ret;
1263 }
1264
1265 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1266 struct seq_file *m,
1267 struct intel_instdone *instdone)
1268 {
1269 int slice;
1270 int subslice;
1271
1272 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1273 instdone->instdone);
1274
1275 if (INTEL_GEN(dev_priv) <= 3)
1276 return;
1277
1278 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1279 instdone->slice_common);
1280
1281 if (INTEL_GEN(dev_priv) <= 6)
1282 return;
1283
1284 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1285 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1286 slice, subslice, instdone->sampler[slice][subslice]);
1287
1288 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1289 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1290 slice, subslice, instdone->row[slice][subslice]);
1291 }
1292
1293 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1294 {
1295 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1296 struct intel_engine_cs *engine;
1297 u64 acthd[I915_NUM_ENGINES];
1298 u32 seqno[I915_NUM_ENGINES];
1299 struct intel_instdone instdone;
1300 enum intel_engine_id id;
1301
1302 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1303 seq_puts(m, "Wedged\n");
1304 if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1305 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1306 if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1307 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1308 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1309 seq_puts(m, "Waiter holding struct mutex\n");
1310 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1311 seq_puts(m, "struct_mutex blocked for reset\n");
1312
1313 if (!i915_modparams.enable_hangcheck) {
1314 seq_puts(m, "Hangcheck disabled\n");
1315 return 0;
1316 }
1317
1318 intel_runtime_pm_get(dev_priv);
1319
1320 for_each_engine(engine, dev_priv, id) {
1321 acthd[id] = intel_engine_get_active_head(engine);
1322 seqno[id] = intel_engine_get_seqno(engine);
1323 }
1324
1325 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1326
1327 intel_runtime_pm_put(dev_priv);
1328
1329 if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1330 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1331 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1332 jiffies));
1333 else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1334 seq_puts(m, "Hangcheck active, work pending\n");
1335 else
1336 seq_puts(m, "Hangcheck inactive\n");
1337
1338 seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1339
1340 for_each_engine(engine, dev_priv, id) {
1341 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1342 struct rb_node *rb;
1343
1344 seq_printf(m, "%s:\n", engine->name);
1345 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1346 engine->hangcheck.seqno, seqno[id],
1347 intel_engine_last_submit(engine),
1348 engine->timeline->inflight_seqnos);
1349 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1350 yesno(intel_engine_has_waiter(engine)),
1351 yesno(test_bit(engine->id,
1352 &dev_priv->gpu_error.missed_irq_rings)),
1353 yesno(engine->hangcheck.stalled));
1354
1355 spin_lock_irq(&b->rb_lock);
1356 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1357 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1358
1359 seq_printf(m, "\t%s [%d] waiting for %x\n",
1360 w->tsk->comm, w->tsk->pid, w->seqno);
1361 }
1362 spin_unlock_irq(&b->rb_lock);
1363
1364 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1365 (long long)engine->hangcheck.acthd,
1366 (long long)acthd[id]);
1367 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1368 hangcheck_action_to_str(engine->hangcheck.action),
1369 engine->hangcheck.action,
1370 jiffies_to_msecs(jiffies -
1371 engine->hangcheck.action_timestamp));
1372
1373 if (engine->id == RCS) {
1374 seq_puts(m, "\tinstdone read =\n");
1375
1376 i915_instdone_info(dev_priv, m, &instdone);
1377
1378 seq_puts(m, "\tinstdone accu =\n");
1379
1380 i915_instdone_info(dev_priv, m,
1381 &engine->hangcheck.instdone);
1382 }
1383 }
1384
1385 return 0;
1386 }
1387
1388 static int i915_reset_info(struct seq_file *m, void *unused)
1389 {
1390 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1391 struct i915_gpu_error *error = &dev_priv->gpu_error;
1392 struct intel_engine_cs *engine;
1393 enum intel_engine_id id;
1394
1395 seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1396
1397 for_each_engine(engine, dev_priv, id) {
1398 seq_printf(m, "%s = %u\n", engine->name,
1399 i915_reset_engine_count(error, engine));
1400 }
1401
1402 return 0;
1403 }
1404
1405 static int ironlake_drpc_info(struct seq_file *m)
1406 {
1407 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1408 u32 rgvmodectl, rstdbyctl;
1409 u16 crstandvid;
1410
1411 rgvmodectl = I915_READ(MEMMODECTL);
1412 rstdbyctl = I915_READ(RSTDBYCTL);
1413 crstandvid = I915_READ16(CRSTANDVID);
1414
1415 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1416 seq_printf(m, "Boost freq: %d\n",
1417 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1418 MEMMODE_BOOST_FREQ_SHIFT);
1419 seq_printf(m, "HW control enabled: %s\n",
1420 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1421 seq_printf(m, "SW control enabled: %s\n",
1422 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1423 seq_printf(m, "Gated voltage change: %s\n",
1424 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1425 seq_printf(m, "Starting frequency: P%d\n",
1426 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1427 seq_printf(m, "Max P-state: P%d\n",
1428 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1429 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1430 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1431 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1432 seq_printf(m, "Render standby enabled: %s\n",
1433 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1434 seq_puts(m, "Current RS state: ");
1435 switch (rstdbyctl & RSX_STATUS_MASK) {
1436 case RSX_STATUS_ON:
1437 seq_puts(m, "on\n");
1438 break;
1439 case RSX_STATUS_RC1:
1440 seq_puts(m, "RC1\n");
1441 break;
1442 case RSX_STATUS_RC1E:
1443 seq_puts(m, "RC1E\n");
1444 break;
1445 case RSX_STATUS_RS1:
1446 seq_puts(m, "RS1\n");
1447 break;
1448 case RSX_STATUS_RS2:
1449 seq_puts(m, "RS2 (RC6)\n");
1450 break;
1451 case RSX_STATUS_RS3:
1452 seq_puts(m, "RC3 (RC6+)\n");
1453 break;
1454 default:
1455 seq_puts(m, "unknown\n");
1456 break;
1457 }
1458
1459 return 0;
1460 }
1461
1462 static int i915_forcewake_domains(struct seq_file *m, void *data)
1463 {
1464 struct drm_i915_private *i915 = node_to_i915(m->private);
1465 struct intel_uncore_forcewake_domain *fw_domain;
1466 unsigned int tmp;
1467
1468 seq_printf(m, "user.bypass_count = %u\n",
1469 i915->uncore.user_forcewake.count);
1470
1471 for_each_fw_domain(fw_domain, i915, tmp)
1472 seq_printf(m, "%s.wake_count = %u\n",
1473 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1474 READ_ONCE(fw_domain->wake_count));
1475
1476 return 0;
1477 }
1478
1479 static void print_rc6_res(struct seq_file *m,
1480 const char *title,
1481 const i915_reg_t reg)
1482 {
1483 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1484
1485 seq_printf(m, "%s %u (%llu us)\n",
1486 title, I915_READ(reg),
1487 intel_rc6_residency_us(dev_priv, reg));
1488 }
1489
1490 static int vlv_drpc_info(struct seq_file *m)
1491 {
1492 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1493 u32 rcctl1, pw_status;
1494
1495 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1496 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1497
1498 seq_printf(m, "RC6 Enabled: %s\n",
1499 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1500 GEN6_RC_CTL_EI_MODE(1))));
1501 seq_printf(m, "Render Power Well: %s\n",
1502 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1503 seq_printf(m, "Media Power Well: %s\n",
1504 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1505
1506 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1507 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1508
1509 return i915_forcewake_domains(m, NULL);
1510 }
1511
1512 static int gen6_drpc_info(struct seq_file *m)
1513 {
1514 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1515 u32 gt_core_status, rcctl1, rc6vids = 0;
1516 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1517 unsigned forcewake_count;
1518 int count = 0;
1519
1520 forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1521 if (forcewake_count) {
1522 seq_puts(m, "RC information inaccurate because somebody "
1523 "holds a forcewake reference \n");
1524 } else {
1525 /* NB: we cannot use forcewake, else we read the wrong values */
1526 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1527 udelay(10);
1528 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1529 }
1530
1531 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1532 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1533
1534 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535 if (INTEL_GEN(dev_priv) >= 9) {
1536 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1537 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1538 }
1539
1540 mutex_lock(&dev_priv->pcu_lock);
1541 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1542 mutex_unlock(&dev_priv->pcu_lock);
1543
1544 seq_printf(m, "RC1e Enabled: %s\n",
1545 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546 seq_printf(m, "RC6 Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548 if (INTEL_GEN(dev_priv) >= 9) {
1549 seq_printf(m, "Render Well Gating Enabled: %s\n",
1550 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1551 seq_printf(m, "Media Well Gating Enabled: %s\n",
1552 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1553 }
1554 seq_printf(m, "Deep RC6 Enabled: %s\n",
1555 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1556 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1557 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1558 seq_puts(m, "Current RC state: ");
1559 switch (gt_core_status & GEN6_RCn_MASK) {
1560 case GEN6_RC0:
1561 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1562 seq_puts(m, "Core Power Down\n");
1563 else
1564 seq_puts(m, "on\n");
1565 break;
1566 case GEN6_RC3:
1567 seq_puts(m, "RC3\n");
1568 break;
1569 case GEN6_RC6:
1570 seq_puts(m, "RC6\n");
1571 break;
1572 case GEN6_RC7:
1573 seq_puts(m, "RC7\n");
1574 break;
1575 default:
1576 seq_puts(m, "Unknown\n");
1577 break;
1578 }
1579
1580 seq_printf(m, "Core Power Down: %s\n",
1581 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1582 if (INTEL_GEN(dev_priv) >= 9) {
1583 seq_printf(m, "Render Power Well: %s\n",
1584 (gen9_powergate_status &
1585 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1586 seq_printf(m, "Media Power Well: %s\n",
1587 (gen9_powergate_status &
1588 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1589 }
1590
1591 /* Not exactly sure what this is */
1592 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1593 GEN6_GT_GFX_RC6_LOCKED);
1594 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1595 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1596 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1597
1598 seq_printf(m, "RC6 voltage: %dmV\n",
1599 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1600 seq_printf(m, "RC6+ voltage: %dmV\n",
1601 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1602 seq_printf(m, "RC6++ voltage: %dmV\n",
1603 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1604 return i915_forcewake_domains(m, NULL);
1605 }
1606
1607 static int i915_drpc_info(struct seq_file *m, void *unused)
1608 {
1609 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1610 int err;
1611
1612 intel_runtime_pm_get(dev_priv);
1613
1614 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1615 err = vlv_drpc_info(m);
1616 else if (INTEL_GEN(dev_priv) >= 6)
1617 err = gen6_drpc_info(m);
1618 else
1619 err = ironlake_drpc_info(m);
1620
1621 intel_runtime_pm_put(dev_priv);
1622
1623 return err;
1624 }
1625
1626 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1627 {
1628 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1629
1630 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1631 dev_priv->fb_tracking.busy_bits);
1632
1633 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1634 dev_priv->fb_tracking.flip_bits);
1635
1636 return 0;
1637 }
1638
1639 static int i915_fbc_status(struct seq_file *m, void *unused)
1640 {
1641 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1642
1643 if (!HAS_FBC(dev_priv)) {
1644 seq_puts(m, "FBC unsupported on this chipset\n");
1645 return 0;
1646 }
1647
1648 intel_runtime_pm_get(dev_priv);
1649 mutex_lock(&dev_priv->fbc.lock);
1650
1651 if (intel_fbc_is_active(dev_priv))
1652 seq_puts(m, "FBC enabled\n");
1653 else
1654 seq_printf(m, "FBC disabled: %s\n",
1655 dev_priv->fbc.no_fbc_reason);
1656
1657 if (intel_fbc_is_active(dev_priv)) {
1658 u32 mask;
1659
1660 if (INTEL_GEN(dev_priv) >= 8)
1661 mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1662 else if (INTEL_GEN(dev_priv) >= 7)
1663 mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1664 else if (INTEL_GEN(dev_priv) >= 5)
1665 mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1666 else if (IS_G4X(dev_priv))
1667 mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1668 else
1669 mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1670 FBC_STAT_COMPRESSED);
1671
1672 seq_printf(m, "Compressing: %s\n", yesno(mask));
1673 }
1674
1675 mutex_unlock(&dev_priv->fbc.lock);
1676 intel_runtime_pm_put(dev_priv);
1677
1678 return 0;
1679 }
1680
1681 static int i915_fbc_false_color_get(void *data, u64 *val)
1682 {
1683 struct drm_i915_private *dev_priv = data;
1684
1685 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1686 return -ENODEV;
1687
1688 *val = dev_priv->fbc.false_color;
1689
1690 return 0;
1691 }
1692
1693 static int i915_fbc_false_color_set(void *data, u64 val)
1694 {
1695 struct drm_i915_private *dev_priv = data;
1696 u32 reg;
1697
1698 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1699 return -ENODEV;
1700
1701 mutex_lock(&dev_priv->fbc.lock);
1702
1703 reg = I915_READ(ILK_DPFC_CONTROL);
1704 dev_priv->fbc.false_color = val;
1705
1706 I915_WRITE(ILK_DPFC_CONTROL, val ?
1707 (reg | FBC_CTL_FALSE_COLOR) :
1708 (reg & ~FBC_CTL_FALSE_COLOR));
1709
1710 mutex_unlock(&dev_priv->fbc.lock);
1711 return 0;
1712 }
1713
1714 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1715 i915_fbc_false_color_get, i915_fbc_false_color_set,
1716 "%llu\n");
1717
1718 static int i915_ips_status(struct seq_file *m, void *unused)
1719 {
1720 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1721
1722 if (!HAS_IPS(dev_priv)) {
1723 seq_puts(m, "not supported\n");
1724 return 0;
1725 }
1726
1727 intel_runtime_pm_get(dev_priv);
1728
1729 seq_printf(m, "Enabled by kernel parameter: %s\n",
1730 yesno(i915_modparams.enable_ips));
1731
1732 if (INTEL_GEN(dev_priv) >= 8) {
1733 seq_puts(m, "Currently: unknown\n");
1734 } else {
1735 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736 seq_puts(m, "Currently: enabled\n");
1737 else
1738 seq_puts(m, "Currently: disabled\n");
1739 }
1740
1741 intel_runtime_pm_put(dev_priv);
1742
1743 return 0;
1744 }
1745
1746 static int i915_sr_status(struct seq_file *m, void *unused)
1747 {
1748 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1749 bool sr_enabled = false;
1750
1751 intel_runtime_pm_get(dev_priv);
1752 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1753
1754 if (INTEL_GEN(dev_priv) >= 9)
1755 /* no global SR status; inspect per-plane WM */;
1756 else if (HAS_PCH_SPLIT(dev_priv))
1757 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1758 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1759 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1760 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761 else if (IS_I915GM(dev_priv))
1762 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763 else if (IS_PINEVIEW(dev_priv))
1764 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1765 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1766 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1767
1768 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1769 intel_runtime_pm_put(dev_priv);
1770
1771 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1772
1773 return 0;
1774 }
1775
1776 static int i915_emon_status(struct seq_file *m, void *unused)
1777 {
1778 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1779 struct drm_device *dev = &dev_priv->drm;
1780 unsigned long temp, chipset, gfx;
1781 int ret;
1782
1783 if (!IS_GEN5(dev_priv))
1784 return -ENODEV;
1785
1786 intel_runtime_pm_get(dev_priv);
1787
1788 ret = mutex_lock_interruptible(&dev->struct_mutex);
1789 if (ret)
1790 return ret;
1791
1792 temp = i915_mch_val(dev_priv);
1793 chipset = i915_chipset_val(dev_priv);
1794 gfx = i915_gfx_val(dev_priv);
1795 mutex_unlock(&dev->struct_mutex);
1796
1797 seq_printf(m, "GMCH temp: %ld\n", temp);
1798 seq_printf(m, "Chipset power: %ld\n", chipset);
1799 seq_printf(m, "GFX power: %ld\n", gfx);
1800 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1801
1802 intel_runtime_pm_put(dev_priv);
1803
1804 return 0;
1805 }
1806
1807 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1808 {
1809 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1810 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1811 int ret = 0;
1812 int gpu_freq, ia_freq;
1813 unsigned int max_gpu_freq, min_gpu_freq;
1814
1815 if (!HAS_LLC(dev_priv)) {
1816 seq_puts(m, "unsupported on this chipset\n");
1817 return 0;
1818 }
1819
1820 intel_runtime_pm_get(dev_priv);
1821
1822 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1823 if (ret)
1824 goto out;
1825
1826 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1827 /* Convert GT frequency to 50 HZ units */
1828 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1829 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1830 } else {
1831 min_gpu_freq = rps->min_freq_softlimit;
1832 max_gpu_freq = rps->max_freq_softlimit;
1833 }
1834
1835 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1836
1837 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1838 ia_freq = gpu_freq;
1839 sandybridge_pcode_read(dev_priv,
1840 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1841 &ia_freq);
1842 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1843 intel_gpu_freq(dev_priv, (gpu_freq *
1844 (IS_GEN9_BC(dev_priv) ||
1845 IS_CANNONLAKE(dev_priv) ?
1846 GEN9_FREQ_SCALER : 1))),
1847 ((ia_freq >> 0) & 0xff) * 100,
1848 ((ia_freq >> 8) & 0xff) * 100);
1849 }
1850
1851 mutex_unlock(&dev_priv->pcu_lock);
1852
1853 out:
1854 intel_runtime_pm_put(dev_priv);
1855 return ret;
1856 }
1857
1858 static int i915_opregion(struct seq_file *m, void *unused)
1859 {
1860 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1861 struct drm_device *dev = &dev_priv->drm;
1862 struct intel_opregion *opregion = &dev_priv->opregion;
1863 int ret;
1864
1865 ret = mutex_lock_interruptible(&dev->struct_mutex);
1866 if (ret)
1867 goto out;
1868
1869 if (opregion->header)
1870 seq_write(m, opregion->header, OPREGION_SIZE);
1871
1872 mutex_unlock(&dev->struct_mutex);
1873
1874 out:
1875 return 0;
1876 }
1877
1878 static int i915_vbt(struct seq_file *m, void *unused)
1879 {
1880 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1881
1882 if (opregion->vbt)
1883 seq_write(m, opregion->vbt, opregion->vbt_size);
1884
1885 return 0;
1886 }
1887
1888 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1889 {
1890 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1891 struct drm_device *dev = &dev_priv->drm;
1892 struct intel_framebuffer *fbdev_fb = NULL;
1893 struct drm_framebuffer *drm_fb;
1894 int ret;
1895
1896 ret = mutex_lock_interruptible(&dev->struct_mutex);
1897 if (ret)
1898 return ret;
1899
1900 #ifdef CONFIG_DRM_FBDEV_EMULATION
1901 if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1902 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1903
1904 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1905 fbdev_fb->base.width,
1906 fbdev_fb->base.height,
1907 fbdev_fb->base.format->depth,
1908 fbdev_fb->base.format->cpp[0] * 8,
1909 fbdev_fb->base.modifier,
1910 drm_framebuffer_read_refcount(&fbdev_fb->base));
1911 describe_obj(m, fbdev_fb->obj);
1912 seq_putc(m, '\n');
1913 }
1914 #endif
1915
1916 mutex_lock(&dev->mode_config.fb_lock);
1917 drm_for_each_fb(drm_fb, dev) {
1918 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1919 if (fb == fbdev_fb)
1920 continue;
1921
1922 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1923 fb->base.width,
1924 fb->base.height,
1925 fb->base.format->depth,
1926 fb->base.format->cpp[0] * 8,
1927 fb->base.modifier,
1928 drm_framebuffer_read_refcount(&fb->base));
1929 describe_obj(m, fb->obj);
1930 seq_putc(m, '\n');
1931 }
1932 mutex_unlock(&dev->mode_config.fb_lock);
1933 mutex_unlock(&dev->struct_mutex);
1934
1935 return 0;
1936 }
1937
1938 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1939 {
1940 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1941 ring->space, ring->head, ring->tail);
1942 }
1943
1944 static int i915_context_status(struct seq_file *m, void *unused)
1945 {
1946 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1947 struct drm_device *dev = &dev_priv->drm;
1948 struct intel_engine_cs *engine;
1949 struct i915_gem_context *ctx;
1950 enum intel_engine_id id;
1951 int ret;
1952
1953 ret = mutex_lock_interruptible(&dev->struct_mutex);
1954 if (ret)
1955 return ret;
1956
1957 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1958 seq_printf(m, "HW context %u ", ctx->hw_id);
1959 if (ctx->pid) {
1960 struct task_struct *task;
1961
1962 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1963 if (task) {
1964 seq_printf(m, "(%s [%d]) ",
1965 task->comm, task->pid);
1966 put_task_struct(task);
1967 }
1968 } else if (IS_ERR(ctx->file_priv)) {
1969 seq_puts(m, "(deleted) ");
1970 } else {
1971 seq_puts(m, "(kernel) ");
1972 }
1973
1974 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1975 seq_putc(m, '\n');
1976
1977 for_each_engine(engine, dev_priv, id) {
1978 struct intel_context *ce = &ctx->engine[engine->id];
1979
1980 seq_printf(m, "%s: ", engine->name);
1981 if (ce->state)
1982 describe_obj(m, ce->state->obj);
1983 if (ce->ring)
1984 describe_ctx_ring(m, ce->ring);
1985 seq_putc(m, '\n');
1986 }
1987
1988 seq_putc(m, '\n');
1989 }
1990
1991 mutex_unlock(&dev->struct_mutex);
1992
1993 return 0;
1994 }
1995
1996 static void i915_dump_lrc_obj(struct seq_file *m,
1997 struct i915_gem_context *ctx,
1998 struct intel_engine_cs *engine)
1999 {
2000 struct i915_vma *vma = ctx->engine[engine->id].state;
2001 struct page *page;
2002 int j;
2003
2004 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2005
2006 if (!vma) {
2007 seq_puts(m, "\tFake context\n");
2008 return;
2009 }
2010
2011 if (vma->flags & I915_VMA_GLOBAL_BIND)
2012 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2013 i915_ggtt_offset(vma));
2014
2015 if (i915_gem_object_pin_pages(vma->obj)) {
2016 seq_puts(m, "\tFailed to get pages for context object\n\n");
2017 return;
2018 }
2019
2020 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2021 if (page) {
2022 u32 *reg_state = kmap_atomic(page);
2023
2024 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2025 seq_printf(m,
2026 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2027 j * 4,
2028 reg_state[j], reg_state[j + 1],
2029 reg_state[j + 2], reg_state[j + 3]);
2030 }
2031 kunmap_atomic(reg_state);
2032 }
2033
2034 i915_gem_object_unpin_pages(vma->obj);
2035 seq_putc(m, '\n');
2036 }
2037
2038 static int i915_dump_lrc(struct seq_file *m, void *unused)
2039 {
2040 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2041 struct drm_device *dev = &dev_priv->drm;
2042 struct intel_engine_cs *engine;
2043 struct i915_gem_context *ctx;
2044 enum intel_engine_id id;
2045 int ret;
2046
2047 if (!i915_modparams.enable_execlists) {
2048 seq_printf(m, "Logical Ring Contexts are disabled\n");
2049 return 0;
2050 }
2051
2052 ret = mutex_lock_interruptible(&dev->struct_mutex);
2053 if (ret)
2054 return ret;
2055
2056 list_for_each_entry(ctx, &dev_priv->contexts.list, link)
2057 for_each_engine(engine, dev_priv, id)
2058 i915_dump_lrc_obj(m, ctx, engine);
2059
2060 mutex_unlock(&dev->struct_mutex);
2061
2062 return 0;
2063 }
2064
2065 static const char *swizzle_string(unsigned swizzle)
2066 {
2067 switch (swizzle) {
2068 case I915_BIT_6_SWIZZLE_NONE:
2069 return "none";
2070 case I915_BIT_6_SWIZZLE_9:
2071 return "bit9";
2072 case I915_BIT_6_SWIZZLE_9_10:
2073 return "bit9/bit10";
2074 case I915_BIT_6_SWIZZLE_9_11:
2075 return "bit9/bit11";
2076 case I915_BIT_6_SWIZZLE_9_10_11:
2077 return "bit9/bit10/bit11";
2078 case I915_BIT_6_SWIZZLE_9_17:
2079 return "bit9/bit17";
2080 case I915_BIT_6_SWIZZLE_9_10_17:
2081 return "bit9/bit10/bit17";
2082 case I915_BIT_6_SWIZZLE_UNKNOWN:
2083 return "unknown";
2084 }
2085
2086 return "bug";
2087 }
2088
2089 static int i915_swizzle_info(struct seq_file *m, void *data)
2090 {
2091 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2092
2093 intel_runtime_pm_get(dev_priv);
2094
2095 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2096 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2097 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2098 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2099
2100 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2101 seq_printf(m, "DDC = 0x%08x\n",
2102 I915_READ(DCC));
2103 seq_printf(m, "DDC2 = 0x%08x\n",
2104 I915_READ(DCC2));
2105 seq_printf(m, "C0DRB3 = 0x%04x\n",
2106 I915_READ16(C0DRB3));
2107 seq_printf(m, "C1DRB3 = 0x%04x\n",
2108 I915_READ16(C1DRB3));
2109 } else if (INTEL_GEN(dev_priv) >= 6) {
2110 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2111 I915_READ(MAD_DIMM_C0));
2112 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2113 I915_READ(MAD_DIMM_C1));
2114 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2115 I915_READ(MAD_DIMM_C2));
2116 seq_printf(m, "TILECTL = 0x%08x\n",
2117 I915_READ(TILECTL));
2118 if (INTEL_GEN(dev_priv) >= 8)
2119 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2120 I915_READ(GAMTARBMODE));
2121 else
2122 seq_printf(m, "ARB_MODE = 0x%08x\n",
2123 I915_READ(ARB_MODE));
2124 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2125 I915_READ(DISP_ARB_CTL));
2126 }
2127
2128 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2129 seq_puts(m, "L-shaped memory detected\n");
2130
2131 intel_runtime_pm_put(dev_priv);
2132
2133 return 0;
2134 }
2135
2136 static int per_file_ctx(int id, void *ptr, void *data)
2137 {
2138 struct i915_gem_context *ctx = ptr;
2139 struct seq_file *m = data;
2140 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2141
2142 if (!ppgtt) {
2143 seq_printf(m, " no ppgtt for context %d\n",
2144 ctx->user_handle);
2145 return 0;
2146 }
2147
2148 if (i915_gem_context_is_default(ctx))
2149 seq_puts(m, " default context:\n");
2150 else
2151 seq_printf(m, " context %d:\n", ctx->user_handle);
2152 ppgtt->debug_dump(ppgtt, m);
2153
2154 return 0;
2155 }
2156
2157 static void gen8_ppgtt_info(struct seq_file *m,
2158 struct drm_i915_private *dev_priv)
2159 {
2160 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2161 struct intel_engine_cs *engine;
2162 enum intel_engine_id id;
2163 int i;
2164
2165 if (!ppgtt)
2166 return;
2167
2168 for_each_engine(engine, dev_priv, id) {
2169 seq_printf(m, "%s\n", engine->name);
2170 for (i = 0; i < 4; i++) {
2171 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2172 pdp <<= 32;
2173 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2174 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2175 }
2176 }
2177 }
2178
2179 static void gen6_ppgtt_info(struct seq_file *m,
2180 struct drm_i915_private *dev_priv)
2181 {
2182 struct intel_engine_cs *engine;
2183 enum intel_engine_id id;
2184
2185 if (IS_GEN6(dev_priv))
2186 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2187
2188 for_each_engine(engine, dev_priv, id) {
2189 seq_printf(m, "%s\n", engine->name);
2190 if (IS_GEN7(dev_priv))
2191 seq_printf(m, "GFX_MODE: 0x%08x\n",
2192 I915_READ(RING_MODE_GEN7(engine)));
2193 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2194 I915_READ(RING_PP_DIR_BASE(engine)));
2195 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2196 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2197 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2198 I915_READ(RING_PP_DIR_DCLV(engine)));
2199 }
2200 if (dev_priv->mm.aliasing_ppgtt) {
2201 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2202
2203 seq_puts(m, "aliasing PPGTT:\n");
2204 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2205
2206 ppgtt->debug_dump(ppgtt, m);
2207 }
2208
2209 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2210 }
2211
2212 static int i915_ppgtt_info(struct seq_file *m, void *data)
2213 {
2214 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2215 struct drm_device *dev = &dev_priv->drm;
2216 struct drm_file *file;
2217 int ret;
2218
2219 mutex_lock(&dev->filelist_mutex);
2220 ret = mutex_lock_interruptible(&dev->struct_mutex);
2221 if (ret)
2222 goto out_unlock;
2223
2224 intel_runtime_pm_get(dev_priv);
2225
2226 if (INTEL_GEN(dev_priv) >= 8)
2227 gen8_ppgtt_info(m, dev_priv);
2228 else if (INTEL_GEN(dev_priv) >= 6)
2229 gen6_ppgtt_info(m, dev_priv);
2230
2231 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2232 struct drm_i915_file_private *file_priv = file->driver_priv;
2233 struct task_struct *task;
2234
2235 task = get_pid_task(file->pid, PIDTYPE_PID);
2236 if (!task) {
2237 ret = -ESRCH;
2238 goto out_rpm;
2239 }
2240 seq_printf(m, "\nproc: %s\n", task->comm);
2241 put_task_struct(task);
2242 idr_for_each(&file_priv->context_idr, per_file_ctx,
2243 (void *)(unsigned long)m);
2244 }
2245
2246 out_rpm:
2247 intel_runtime_pm_put(dev_priv);
2248 mutex_unlock(&dev->struct_mutex);
2249 out_unlock:
2250 mutex_unlock(&dev->filelist_mutex);
2251 return ret;
2252 }
2253
2254 static int count_irq_waiters(struct drm_i915_private *i915)
2255 {
2256 struct intel_engine_cs *engine;
2257 enum intel_engine_id id;
2258 int count = 0;
2259
2260 for_each_engine(engine, i915, id)
2261 count += intel_engine_has_waiter(engine);
2262
2263 return count;
2264 }
2265
2266 static const char *rps_power_to_str(unsigned int power)
2267 {
2268 static const char * const strings[] = {
2269 [LOW_POWER] = "low power",
2270 [BETWEEN] = "mixed",
2271 [HIGH_POWER] = "high power",
2272 };
2273
2274 if (power >= ARRAY_SIZE(strings) || !strings[power])
2275 return "unknown";
2276
2277 return strings[power];
2278 }
2279
2280 static int i915_rps_boost_info(struct seq_file *m, void *data)
2281 {
2282 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2283 struct drm_device *dev = &dev_priv->drm;
2284 struct intel_rps *rps = &dev_priv->gt_pm.rps;
2285 struct drm_file *file;
2286
2287 seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2288 seq_printf(m, "GPU busy? %s [%d requests]\n",
2289 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2290 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2291 seq_printf(m, "Boosts outstanding? %d\n",
2292 atomic_read(&rps->num_waiters));
2293 seq_printf(m, "Frequency requested %d\n",
2294 intel_gpu_freq(dev_priv, rps->cur_freq));
2295 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2296 intel_gpu_freq(dev_priv, rps->min_freq),
2297 intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2298 intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2299 intel_gpu_freq(dev_priv, rps->max_freq));
2300 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2301 intel_gpu_freq(dev_priv, rps->idle_freq),
2302 intel_gpu_freq(dev_priv, rps->efficient_freq),
2303 intel_gpu_freq(dev_priv, rps->boost_freq));
2304
2305 mutex_lock(&dev->filelist_mutex);
2306 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2307 struct drm_i915_file_private *file_priv = file->driver_priv;
2308 struct task_struct *task;
2309
2310 rcu_read_lock();
2311 task = pid_task(file->pid, PIDTYPE_PID);
2312 seq_printf(m, "%s [%d]: %d boosts\n",
2313 task ? task->comm : "<unknown>",
2314 task ? task->pid : -1,
2315 atomic_read(&file_priv->rps_client.boosts));
2316 rcu_read_unlock();
2317 }
2318 seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2319 atomic_read(&rps->boosts));
2320 mutex_unlock(&dev->filelist_mutex);
2321
2322 if (INTEL_GEN(dev_priv) >= 6 &&
2323 rps->enabled &&
2324 dev_priv->gt.active_requests) {
2325 u32 rpup, rpupei;
2326 u32 rpdown, rpdownei;
2327
2328 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2329 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2330 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2331 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2332 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2333 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2334
2335 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2336 rps_power_to_str(rps->power));
2337 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2338 rpup && rpupei ? 100 * rpup / rpupei : 0,
2339 rps->up_threshold);
2340 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2341 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2342 rps->down_threshold);
2343 } else {
2344 seq_puts(m, "\nRPS Autotuning inactive\n");
2345 }
2346
2347 return 0;
2348 }
2349
2350 static int i915_llc(struct seq_file *m, void *data)
2351 {
2352 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2353 const bool edram = INTEL_GEN(dev_priv) > 8;
2354
2355 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2356 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2357 intel_uncore_edram_size(dev_priv)/1024/1024);
2358
2359 return 0;
2360 }
2361
2362 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2363 {
2364 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2365 struct drm_printer p;
2366
2367 if (!HAS_HUC_UCODE(dev_priv))
2368 return 0;
2369
2370 p = drm_seq_file_printer(m);
2371 intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2372
2373 intel_runtime_pm_get(dev_priv);
2374 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2375 intel_runtime_pm_put(dev_priv);
2376
2377 return 0;
2378 }
2379
2380 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2381 {
2382 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2383 struct drm_printer p;
2384 u32 tmp, i;
2385
2386 if (!HAS_GUC_UCODE(dev_priv))
2387 return 0;
2388
2389 p = drm_seq_file_printer(m);
2390 intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2391
2392 intel_runtime_pm_get(dev_priv);
2393
2394 tmp = I915_READ(GUC_STATUS);
2395
2396 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2397 seq_printf(m, "\tBootrom status = 0x%x\n",
2398 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2399 seq_printf(m, "\tuKernel status = 0x%x\n",
2400 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2401 seq_printf(m, "\tMIA Core status = 0x%x\n",
2402 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2403 seq_puts(m, "\nScratch registers:\n");
2404 for (i = 0; i < 16; i++)
2405 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2406
2407 intel_runtime_pm_put(dev_priv);
2408
2409 return 0;
2410 }
2411
2412 static void i915_guc_log_info(struct seq_file *m,
2413 struct drm_i915_private *dev_priv)
2414 {
2415 struct intel_guc *guc = &dev_priv->guc;
2416
2417 seq_puts(m, "\nGuC logging stats:\n");
2418
2419 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2420 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2421 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2422
2423 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2424 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2425 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2426
2427 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2428 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2429 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2430
2431 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2432 guc->log.flush_interrupt_count);
2433
2434 seq_printf(m, "\tCapture miss count: %u\n",
2435 guc->log.capture_miss_count);
2436 }
2437
2438 static void i915_guc_client_info(struct seq_file *m,
2439 struct drm_i915_private *dev_priv,
2440 struct i915_guc_client *client)
2441 {
2442 struct intel_engine_cs *engine;
2443 enum intel_engine_id id;
2444 uint64_t tot = 0;
2445
2446 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2447 client->priority, client->stage_id, client->proc_desc_offset);
2448 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2449 client->doorbell_id, client->doorbell_offset);
2450
2451 for_each_engine(engine, dev_priv, id) {
2452 u64 submissions = client->submissions[id];
2453 tot += submissions;
2454 seq_printf(m, "\tSubmissions: %llu %s\n",
2455 submissions, engine->name);
2456 }
2457 seq_printf(m, "\tTotal: %llu\n", tot);
2458 }
2459
2460 static bool check_guc_submission(struct seq_file *m)
2461 {
2462 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2463 const struct intel_guc *guc = &dev_priv->guc;
2464
2465 if (!guc->execbuf_client) {
2466 seq_printf(m, "GuC submission %s\n",
2467 HAS_GUC_SCHED(dev_priv) ?
2468 "disabled" :
2469 "not supported");
2470 return false;
2471 }
2472
2473 return true;
2474 }
2475
2476 static int i915_guc_info(struct seq_file *m, void *data)
2477 {
2478 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2479 const struct intel_guc *guc = &dev_priv->guc;
2480
2481 if (!check_guc_submission(m))
2482 return 0;
2483
2484 seq_printf(m, "Doorbell map:\n");
2485 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2486 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2487
2488 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2489 i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2490
2491 i915_guc_log_info(m, dev_priv);
2492
2493 /* Add more as required ... */
2494
2495 return 0;
2496 }
2497
2498 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2499 {
2500 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2501 const struct intel_guc *guc = &dev_priv->guc;
2502 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2503 struct i915_guc_client *client = guc->execbuf_client;
2504 unsigned int tmp;
2505 int index;
2506
2507 if (!check_guc_submission(m))
2508 return 0;
2509
2510 for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2511 struct intel_engine_cs *engine;
2512
2513 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2514 continue;
2515
2516 seq_printf(m, "GuC stage descriptor %u:\n", index);
2517 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2518 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2519 seq_printf(m, "\tPriority: %d\n", desc->priority);
2520 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2521 seq_printf(m, "\tEngines used: 0x%x\n",
2522 desc->engines_used);
2523 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2524 desc->db_trigger_phy,
2525 desc->db_trigger_cpu,
2526 desc->db_trigger_uk);
2527 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2528 desc->process_desc);
2529 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2530 desc->wq_addr, desc->wq_size);
2531 seq_putc(m, '\n');
2532
2533 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2534 u32 guc_engine_id = engine->guc_id;
2535 struct guc_execlist_context *lrc =
2536 &desc->lrc[guc_engine_id];
2537
2538 seq_printf(m, "\t%s LRC:\n", engine->name);
2539 seq_printf(m, "\t\tContext desc: 0x%x\n",
2540 lrc->context_desc);
2541 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2542 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2543 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2544 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2545 seq_putc(m, '\n');
2546 }
2547 }
2548
2549 return 0;
2550 }
2551
2552 static int i915_guc_log_dump(struct seq_file *m, void *data)
2553 {
2554 struct drm_info_node *node = m->private;
2555 struct drm_i915_private *dev_priv = node_to_i915(node);
2556 bool dump_load_err = !!node->info_ent->data;
2557 struct drm_i915_gem_object *obj = NULL;
2558 u32 *log;
2559 int i = 0;
2560
2561 if (dump_load_err)
2562 obj = dev_priv->guc.load_err_log;
2563 else if (dev_priv->guc.log.vma)
2564 obj = dev_priv->guc.log.vma->obj;
2565
2566 if (!obj)
2567 return 0;
2568
2569 log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2570 if (IS_ERR(log)) {
2571 DRM_DEBUG("Failed to pin object\n");
2572 seq_puts(m, "(log data unaccessible)\n");
2573 return PTR_ERR(log);
2574 }
2575
2576 for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2577 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2578 *(log + i), *(log + i + 1),
2579 *(log + i + 2), *(log + i + 3));
2580
2581 seq_putc(m, '\n');
2582
2583 i915_gem_object_unpin_map(obj);
2584
2585 return 0;
2586 }
2587
2588 static int i915_guc_log_control_get(void *data, u64 *val)
2589 {
2590 struct drm_i915_private *dev_priv = data;
2591
2592 if (!dev_priv->guc.log.vma)
2593 return -EINVAL;
2594
2595 *val = i915_modparams.guc_log_level;
2596
2597 return 0;
2598 }
2599
2600 static int i915_guc_log_control_set(void *data, u64 val)
2601 {
2602 struct drm_i915_private *dev_priv = data;
2603 int ret;
2604
2605 if (!dev_priv->guc.log.vma)
2606 return -EINVAL;
2607
2608 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
2609 if (ret)
2610 return ret;
2611
2612 intel_runtime_pm_get(dev_priv);
2613 ret = i915_guc_log_control(dev_priv, val);
2614 intel_runtime_pm_put(dev_priv);
2615
2616 mutex_unlock(&dev_priv->drm.struct_mutex);
2617 return ret;
2618 }
2619
2620 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2621 i915_guc_log_control_get, i915_guc_log_control_set,
2622 "%lld\n");
2623
2624 static const char *psr2_live_status(u32 val)
2625 {
2626 static const char * const live_status[] = {
2627 "IDLE",
2628 "CAPTURE",
2629 "CAPTURE_FS",
2630 "SLEEP",
2631 "BUFON_FW",
2632 "ML_UP",
2633 "SU_STANDBY",
2634 "FAST_SLEEP",
2635 "DEEP_SLEEP",
2636 "BUF_ON",
2637 "TG_ON"
2638 };
2639
2640 val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2641 if (val < ARRAY_SIZE(live_status))
2642 return live_status[val];
2643
2644 return "unknown";
2645 }
2646
2647 static int i915_edp_psr_status(struct seq_file *m, void *data)
2648 {
2649 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2650 u32 psrperf = 0;
2651 u32 stat[3];
2652 enum pipe pipe;
2653 bool enabled = false;
2654
2655 if (!HAS_PSR(dev_priv)) {
2656 seq_puts(m, "PSR not supported\n");
2657 return 0;
2658 }
2659
2660 intel_runtime_pm_get(dev_priv);
2661
2662 mutex_lock(&dev_priv->psr.lock);
2663 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2664 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2665 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2666 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2667 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2668 dev_priv->psr.busy_frontbuffer_bits);
2669 seq_printf(m, "Re-enable work scheduled: %s\n",
2670 yesno(work_busy(&dev_priv->psr.work.work)));
2671
2672 if (HAS_DDI(dev_priv)) {
2673 if (dev_priv->psr.psr2_support)
2674 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2675 else
2676 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2677 } else {
2678 for_each_pipe(dev_priv, pipe) {
2679 enum transcoder cpu_transcoder =
2680 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2681 enum intel_display_power_domain power_domain;
2682
2683 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2684 if (!intel_display_power_get_if_enabled(dev_priv,
2685 power_domain))
2686 continue;
2687
2688 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2689 VLV_EDP_PSR_CURR_STATE_MASK;
2690 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2691 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2692 enabled = true;
2693
2694 intel_display_power_put(dev_priv, power_domain);
2695 }
2696 }
2697
2698 seq_printf(m, "Main link in standby mode: %s\n",
2699 yesno(dev_priv->psr.link_standby));
2700
2701 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2702
2703 if (!HAS_DDI(dev_priv))
2704 for_each_pipe(dev_priv, pipe) {
2705 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2706 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2707 seq_printf(m, " pipe %c", pipe_name(pipe));
2708 }
2709 seq_puts(m, "\n");
2710
2711 /*
2712 * VLV/CHV PSR has no kind of performance counter
2713 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2714 */
2715 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2716 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2717 EDP_PSR_PERF_CNT_MASK;
2718
2719 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2720 }
2721 if (dev_priv->psr.psr2_support) {
2722 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2723
2724 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2725 psr2, psr2_live_status(psr2));
2726 }
2727 mutex_unlock(&dev_priv->psr.lock);
2728
2729 intel_runtime_pm_put(dev_priv);
2730 return 0;
2731 }
2732
2733 static int i915_sink_crc(struct seq_file *m, void *data)
2734 {
2735 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2736 struct drm_device *dev = &dev_priv->drm;
2737 struct intel_connector *connector;
2738 struct drm_connector_list_iter conn_iter;
2739 struct intel_dp *intel_dp = NULL;
2740 int ret;
2741 u8 crc[6];
2742
2743 drm_modeset_lock_all(dev);
2744 drm_connector_list_iter_begin(dev, &conn_iter);
2745 for_each_intel_connector_iter(connector, &conn_iter) {
2746 struct drm_crtc *crtc;
2747
2748 if (!connector->base.state->best_encoder)
2749 continue;
2750
2751 crtc = connector->base.state->crtc;
2752 if (!crtc->state->active)
2753 continue;
2754
2755 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2756 continue;
2757
2758 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2759
2760 ret = intel_dp_sink_crc(intel_dp, crc);
2761 if (ret)
2762 goto out;
2763
2764 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2765 crc[0], crc[1], crc[2],
2766 crc[3], crc[4], crc[5]);
2767 goto out;
2768 }
2769 ret = -ENODEV;
2770 out:
2771 drm_connector_list_iter_end(&conn_iter);
2772 drm_modeset_unlock_all(dev);
2773 return ret;
2774 }
2775
2776 static int i915_energy_uJ(struct seq_file *m, void *data)
2777 {
2778 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2779 unsigned long long power;
2780 u32 units;
2781
2782 if (INTEL_GEN(dev_priv) < 6)
2783 return -ENODEV;
2784
2785 intel_runtime_pm_get(dev_priv);
2786
2787 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2788 intel_runtime_pm_put(dev_priv);
2789 return -ENODEV;
2790 }
2791
2792 units = (power & 0x1f00) >> 8;
2793 power = I915_READ(MCH_SECP_NRG_STTS);
2794 power = (1000000 * power) >> units; /* convert to uJ */
2795
2796 intel_runtime_pm_put(dev_priv);
2797
2798 seq_printf(m, "%llu", power);
2799
2800 return 0;
2801 }
2802
2803 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2804 {
2805 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2806 struct pci_dev *pdev = dev_priv->drm.pdev;
2807
2808 if (!HAS_RUNTIME_PM(dev_priv))
2809 seq_puts(m, "Runtime power management not supported\n");
2810
2811 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2812 seq_printf(m, "IRQs disabled: %s\n",
2813 yesno(!intel_irqs_enabled(dev_priv)));
2814 #ifdef CONFIG_PM
2815 seq_printf(m, "Usage count: %d\n",
2816 atomic_read(&dev_priv->drm.dev->power.usage_count));
2817 #else
2818 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2819 #endif
2820 seq_printf(m, "PCI device power state: %s [%d]\n",
2821 pci_power_name(pdev->current_state),
2822 pdev->current_state);
2823
2824 return 0;
2825 }
2826
2827 static int i915_power_domain_info(struct seq_file *m, void *unused)
2828 {
2829 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2830 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2831 int i;
2832
2833 mutex_lock(&power_domains->lock);
2834
2835 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2836 for (i = 0; i < power_domains->power_well_count; i++) {
2837 struct i915_power_well *power_well;
2838 enum intel_display_power_domain power_domain;
2839
2840 power_well = &power_domains->power_wells[i];
2841 seq_printf(m, "%-25s %d\n", power_well->name,
2842 power_well->count);
2843
2844 for_each_power_domain(power_domain, power_well->domains)
2845 seq_printf(m, " %-23s %d\n",
2846 intel_display_power_domain_str(power_domain),
2847 power_domains->domain_use_count[power_domain]);
2848 }
2849
2850 mutex_unlock(&power_domains->lock);
2851
2852 return 0;
2853 }
2854
2855 static int i915_dmc_info(struct seq_file *m, void *unused)
2856 {
2857 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2858 struct intel_csr *csr;
2859
2860 if (!HAS_CSR(dev_priv)) {
2861 seq_puts(m, "not supported\n");
2862 return 0;
2863 }
2864
2865 csr = &dev_priv->csr;
2866
2867 intel_runtime_pm_get(dev_priv);
2868
2869 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2870 seq_printf(m, "path: %s\n", csr->fw_path);
2871
2872 if (!csr->dmc_payload)
2873 goto out;
2874
2875 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2876 CSR_VERSION_MINOR(csr->version));
2877
2878 if (IS_KABYLAKE(dev_priv) ||
2879 (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2880 seq_printf(m, "DC3 -> DC5 count: %d\n",
2881 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2882 seq_printf(m, "DC5 -> DC6 count: %d\n",
2883 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2884 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2885 seq_printf(m, "DC3 -> DC5 count: %d\n",
2886 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2887 }
2888
2889 out:
2890 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2891 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2892 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2893
2894 intel_runtime_pm_put(dev_priv);
2895
2896 return 0;
2897 }
2898
2899 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2900 struct drm_display_mode *mode)
2901 {
2902 int i;
2903
2904 for (i = 0; i < tabs; i++)
2905 seq_putc(m, '\t');
2906
2907 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2908 mode->base.id, mode->name,
2909 mode->vrefresh, mode->clock,
2910 mode->hdisplay, mode->hsync_start,
2911 mode->hsync_end, mode->htotal,
2912 mode->vdisplay, mode->vsync_start,
2913 mode->vsync_end, mode->vtotal,
2914 mode->type, mode->flags);
2915 }
2916
2917 static void intel_encoder_info(struct seq_file *m,
2918 struct intel_crtc *intel_crtc,
2919 struct intel_encoder *intel_encoder)
2920 {
2921 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2922 struct drm_device *dev = &dev_priv->drm;
2923 struct drm_crtc *crtc = &intel_crtc->base;
2924 struct intel_connector *intel_connector;
2925 struct drm_encoder *encoder;
2926
2927 encoder = &intel_encoder->base;
2928 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2929 encoder->base.id, encoder->name);
2930 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2931 struct drm_connector *connector = &intel_connector->base;
2932 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2933 connector->base.id,
2934 connector->name,
2935 drm_get_connector_status_name(connector->status));
2936 if (connector->status == connector_status_connected) {
2937 struct drm_display_mode *mode = &crtc->mode;
2938 seq_printf(m, ", mode:\n");
2939 intel_seq_print_mode(m, 2, mode);
2940 } else {
2941 seq_putc(m, '\n');
2942 }
2943 }
2944 }
2945
2946 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2947 {
2948 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2949 struct drm_device *dev = &dev_priv->drm;
2950 struct drm_crtc *crtc = &intel_crtc->base;
2951 struct intel_encoder *intel_encoder;
2952 struct drm_plane_state *plane_state = crtc->primary->state;
2953 struct drm_framebuffer *fb = plane_state->fb;
2954
2955 if (fb)
2956 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2957 fb->base.id, plane_state->src_x >> 16,
2958 plane_state->src_y >> 16, fb->width, fb->height);
2959 else
2960 seq_puts(m, "\tprimary plane disabled\n");
2961 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2962 intel_encoder_info(m, intel_crtc, intel_encoder);
2963 }
2964
2965 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2966 {
2967 struct drm_display_mode *mode = panel->fixed_mode;
2968
2969 seq_printf(m, "\tfixed mode:\n");
2970 intel_seq_print_mode(m, 2, mode);
2971 }
2972
2973 static void intel_dp_info(struct seq_file *m,
2974 struct intel_connector *intel_connector)
2975 {
2976 struct intel_encoder *intel_encoder = intel_connector->encoder;
2977 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2978
2979 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2980 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2981 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2982 intel_panel_info(m, &intel_connector->panel);
2983
2984 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2985 &intel_dp->aux);
2986 }
2987
2988 static void intel_dp_mst_info(struct seq_file *m,
2989 struct intel_connector *intel_connector)
2990 {
2991 struct intel_encoder *intel_encoder = intel_connector->encoder;
2992 struct intel_dp_mst_encoder *intel_mst =
2993 enc_to_mst(&intel_encoder->base);
2994 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2995 struct intel_dp *intel_dp = &intel_dig_port->dp;
2996 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2997 intel_connector->port);
2998
2999 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
3000 }
3001
3002 static void intel_hdmi_info(struct seq_file *m,
3003 struct intel_connector *intel_connector)
3004 {
3005 struct intel_encoder *intel_encoder = intel_connector->encoder;
3006 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3007
3008 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3009 }
3010
3011 static void intel_lvds_info(struct seq_file *m,
3012 struct intel_connector *intel_connector)
3013 {
3014 intel_panel_info(m, &intel_connector->panel);
3015 }
3016
3017 static void intel_connector_info(struct seq_file *m,
3018 struct drm_connector *connector)
3019 {
3020 struct intel_connector *intel_connector = to_intel_connector(connector);
3021 struct intel_encoder *intel_encoder = intel_connector->encoder;
3022 struct drm_display_mode *mode;
3023
3024 seq_printf(m, "connector %d: type %s, status: %s\n",
3025 connector->base.id, connector->name,
3026 drm_get_connector_status_name(connector->status));
3027 if (connector->status == connector_status_connected) {
3028 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3029 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3030 connector->display_info.width_mm,
3031 connector->display_info.height_mm);
3032 seq_printf(m, "\tsubpixel order: %s\n",
3033 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3034 seq_printf(m, "\tCEA rev: %d\n",
3035 connector->display_info.cea_rev);
3036 }
3037
3038 if (!intel_encoder)
3039 return;
3040
3041 switch (connector->connector_type) {
3042 case DRM_MODE_CONNECTOR_DisplayPort:
3043 case DRM_MODE_CONNECTOR_eDP:
3044 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3045 intel_dp_mst_info(m, intel_connector);
3046 else
3047 intel_dp_info(m, intel_connector);
3048 break;
3049 case DRM_MODE_CONNECTOR_LVDS:
3050 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3051 intel_lvds_info(m, intel_connector);
3052 break;
3053 case DRM_MODE_CONNECTOR_HDMIA:
3054 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3055 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3056 intel_hdmi_info(m, intel_connector);
3057 break;
3058 default:
3059 break;
3060 }
3061
3062 seq_printf(m, "\tmodes:\n");
3063 list_for_each_entry(mode, &connector->modes, head)
3064 intel_seq_print_mode(m, 2, mode);
3065 }
3066
3067 static const char *plane_type(enum drm_plane_type type)
3068 {
3069 switch (type) {
3070 case DRM_PLANE_TYPE_OVERLAY:
3071 return "OVL";
3072 case DRM_PLANE_TYPE_PRIMARY:
3073 return "PRI";
3074 case DRM_PLANE_TYPE_CURSOR:
3075 return "CUR";
3076 /*
3077 * Deliberately omitting default: to generate compiler warnings
3078 * when a new drm_plane_type gets added.
3079 */
3080 }
3081
3082 return "unknown";
3083 }
3084
3085 static const char *plane_rotation(unsigned int rotation)
3086 {
3087 static char buf[48];
3088 /*
3089 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3090 * will print them all to visualize if the values are misused
3091 */
3092 snprintf(buf, sizeof(buf),
3093 "%s%s%s%s%s%s(0x%08x)",
3094 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3095 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3096 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3097 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3098 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3099 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3100 rotation);
3101
3102 return buf;
3103 }
3104
3105 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3106 {
3107 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3108 struct drm_device *dev = &dev_priv->drm;
3109 struct intel_plane *intel_plane;
3110
3111 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3112 struct drm_plane_state *state;
3113 struct drm_plane *plane = &intel_plane->base;
3114 struct drm_format_name_buf format_name;
3115
3116 if (!plane->state) {
3117 seq_puts(m, "plane->state is NULL!\n");
3118 continue;
3119 }
3120
3121 state = plane->state;
3122
3123 if (state->fb) {
3124 drm_get_format_name(state->fb->format->format,
3125 &format_name);
3126 } else {
3127 sprintf(format_name.str, "N/A");
3128 }
3129
3130 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3131 plane->base.id,
3132 plane_type(intel_plane->base.type),
3133 state->crtc_x, state->crtc_y,
3134 state->crtc_w, state->crtc_h,
3135 (state->src_x >> 16),
3136 ((state->src_x & 0xffff) * 15625) >> 10,
3137 (state->src_y >> 16),
3138 ((state->src_y & 0xffff) * 15625) >> 10,
3139 (state->src_w >> 16),
3140 ((state->src_w & 0xffff) * 15625) >> 10,
3141 (state->src_h >> 16),
3142 ((state->src_h & 0xffff) * 15625) >> 10,
3143 format_name.str,
3144 plane_rotation(state->rotation));
3145 }
3146 }
3147
3148 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3149 {
3150 struct intel_crtc_state *pipe_config;
3151 int num_scalers = intel_crtc->num_scalers;
3152 int i;
3153
3154 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3155
3156 /* Not all platformas have a scaler */
3157 if (num_scalers) {
3158 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3159 num_scalers,
3160 pipe_config->scaler_state.scaler_users,
3161 pipe_config->scaler_state.scaler_id);
3162
3163 for (i = 0; i < num_scalers; i++) {
3164 struct intel_scaler *sc =
3165 &pipe_config->scaler_state.scalers[i];
3166
3167 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3168 i, yesno(sc->in_use), sc->mode);
3169 }
3170 seq_puts(m, "\n");
3171 } else {
3172 seq_puts(m, "\tNo scalers available on this platform\n");
3173 }
3174 }
3175
3176 static int i915_display_info(struct seq_file *m, void *unused)
3177 {
3178 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3179 struct drm_device *dev = &dev_priv->drm;
3180 struct intel_crtc *crtc;
3181 struct drm_connector *connector;
3182 struct drm_connector_list_iter conn_iter;
3183
3184 intel_runtime_pm_get(dev_priv);
3185 seq_printf(m, "CRTC info\n");
3186 seq_printf(m, "---------\n");
3187 for_each_intel_crtc(dev, crtc) {
3188 struct intel_crtc_state *pipe_config;
3189
3190 drm_modeset_lock(&crtc->base.mutex, NULL);
3191 pipe_config = to_intel_crtc_state(crtc->base.state);
3192
3193 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3194 crtc->base.base.id, pipe_name(crtc->pipe),
3195 yesno(pipe_config->base.active),
3196 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3197 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3198
3199 if (pipe_config->base.active) {
3200 struct intel_plane *cursor =
3201 to_intel_plane(crtc->base.cursor);
3202
3203 intel_crtc_info(m, crtc);
3204
3205 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3206 yesno(cursor->base.state->visible),
3207 cursor->base.state->crtc_x,
3208 cursor->base.state->crtc_y,
3209 cursor->base.state->crtc_w,
3210 cursor->base.state->crtc_h,
3211 cursor->cursor.base);
3212 intel_scaler_info(m, crtc);
3213 intel_plane_info(m, crtc);
3214 }
3215
3216 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3217 yesno(!crtc->cpu_fifo_underrun_disabled),
3218 yesno(!crtc->pch_fifo_underrun_disabled));
3219 drm_modeset_unlock(&crtc->base.mutex);
3220 }
3221
3222 seq_printf(m, "\n");
3223 seq_printf(m, "Connector info\n");
3224 seq_printf(m, "--------------\n");
3225 mutex_lock(&dev->mode_config.mutex);
3226 drm_connector_list_iter_begin(dev, &conn_iter);
3227 drm_for_each_connector_iter(connector, &conn_iter)
3228 intel_connector_info(m, connector);
3229 drm_connector_list_iter_end(&conn_iter);
3230 mutex_unlock(&dev->mode_config.mutex);
3231
3232 intel_runtime_pm_put(dev_priv);
3233
3234 return 0;
3235 }
3236
3237 static int i915_engine_info(struct seq_file *m, void *unused)
3238 {
3239 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3240 struct intel_engine_cs *engine;
3241 enum intel_engine_id id;
3242 struct drm_printer p;
3243
3244 intel_runtime_pm_get(dev_priv);
3245
3246 seq_printf(m, "GT awake? %s\n",
3247 yesno(dev_priv->gt.awake));
3248 seq_printf(m, "Global active requests: %d\n",
3249 dev_priv->gt.active_requests);
3250
3251 p = drm_seq_file_printer(m);
3252 for_each_engine(engine, dev_priv, id)
3253 intel_engine_dump(engine, &p);
3254
3255 intel_runtime_pm_put(dev_priv);
3256
3257 return 0;
3258 }
3259
3260 static int i915_shrinker_info(struct seq_file *m, void *unused)
3261 {
3262 struct drm_i915_private *i915 = node_to_i915(m->private);
3263
3264 seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3265 seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3266
3267 return 0;
3268 }
3269
3270 static int i915_semaphore_status(struct seq_file *m, void *unused)
3271 {
3272 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3273 struct drm_device *dev = &dev_priv->drm;
3274 struct intel_engine_cs *engine;
3275 int num_rings = INTEL_INFO(dev_priv)->num_rings;
3276 enum intel_engine_id id;
3277 int j, ret;
3278
3279 if (!i915_modparams.semaphores) {
3280 seq_puts(m, "Semaphores are disabled\n");
3281 return 0;
3282 }
3283
3284 ret = mutex_lock_interruptible(&dev->struct_mutex);
3285 if (ret)
3286 return ret;
3287 intel_runtime_pm_get(dev_priv);
3288
3289 if (IS_BROADWELL(dev_priv)) {
3290 struct page *page;
3291 uint64_t *seqno;
3292
3293 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3294
3295 seqno = (uint64_t *)kmap_atomic(page);
3296 for_each_engine(engine, dev_priv, id) {
3297 uint64_t offset;
3298
3299 seq_printf(m, "%s\n", engine->name);
3300
3301 seq_puts(m, " Last signal:");
3302 for (j = 0; j < num_rings; j++) {
3303 offset = id * I915_NUM_ENGINES + j;
3304 seq_printf(m, "0x%08llx (0x%02llx) ",
3305 seqno[offset], offset * 8);
3306 }
3307 seq_putc(m, '\n');
3308
3309 seq_puts(m, " Last wait: ");
3310 for (j = 0; j < num_rings; j++) {
3311 offset = id + (j * I915_NUM_ENGINES);
3312 seq_printf(m, "0x%08llx (0x%02llx) ",
3313 seqno[offset], offset * 8);
3314 }
3315 seq_putc(m, '\n');
3316
3317 }
3318 kunmap_atomic(seqno);
3319 } else {
3320 seq_puts(m, " Last signal:");
3321 for_each_engine(engine, dev_priv, id)
3322 for (j = 0; j < num_rings; j++)
3323 seq_printf(m, "0x%08x\n",
3324 I915_READ(engine->semaphore.mbox.signal[j]));
3325 seq_putc(m, '\n');
3326 }
3327
3328 intel_runtime_pm_put(dev_priv);
3329 mutex_unlock(&dev->struct_mutex);
3330 return 0;
3331 }
3332
3333 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3334 {
3335 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3336 struct drm_device *dev = &dev_priv->drm;
3337 int i;
3338
3339 drm_modeset_lock_all(dev);
3340 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3341 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3342
3343 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3344 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3345 pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3346 seq_printf(m, " tracked hardware state:\n");
3347 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
3348 seq_printf(m, " dpll_md: 0x%08x\n",
3349 pll->state.hw_state.dpll_md);
3350 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
3351 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
3352 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
3353 }
3354 drm_modeset_unlock_all(dev);
3355
3356 return 0;
3357 }
3358
3359 static int i915_wa_registers(struct seq_file *m, void *unused)
3360 {
3361 int i;
3362 int ret;
3363 struct intel_engine_cs *engine;
3364 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3365 struct drm_device *dev = &dev_priv->drm;
3366 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3367 enum intel_engine_id id;
3368
3369 ret = mutex_lock_interruptible(&dev->struct_mutex);
3370 if (ret)
3371 return ret;
3372
3373 intel_runtime_pm_get(dev_priv);
3374
3375 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3376 for_each_engine(engine, dev_priv, id)
3377 seq_printf(m, "HW whitelist count for %s: %d\n",
3378 engine->name, workarounds->hw_whitelist_count[id]);
3379 for (i = 0; i < workarounds->count; ++i) {
3380 i915_reg_t addr;
3381 u32 mask, value, read;
3382 bool ok;
3383
3384 addr = workarounds->reg[i].addr;
3385 mask = workarounds->reg[i].mask;
3386 value = workarounds->reg[i].value;
3387 read = I915_READ(addr);
3388 ok = (value & mask) == (read & mask);
3389 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3390 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3391 }
3392
3393 intel_runtime_pm_put(dev_priv);
3394 mutex_unlock(&dev->struct_mutex);
3395
3396 return 0;
3397 }
3398
3399 static int i915_ipc_status_show(struct seq_file *m, void *data)
3400 {
3401 struct drm_i915_private *dev_priv = m->private;
3402
3403 seq_printf(m, "Isochronous Priority Control: %s\n",
3404 yesno(dev_priv->ipc_enabled));
3405 return 0;
3406 }
3407
3408 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3409 {
3410 struct drm_i915_private *dev_priv = inode->i_private;
3411
3412 if (!HAS_IPC(dev_priv))
3413 return -ENODEV;
3414
3415 return single_open(file, i915_ipc_status_show, dev_priv);
3416 }
3417
3418 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3419 size_t len, loff_t *offp)
3420 {
3421 struct seq_file *m = file->private_data;
3422 struct drm_i915_private *dev_priv = m->private;
3423 int ret;
3424 bool enable;
3425
3426 ret = kstrtobool_from_user(ubuf, len, &enable);
3427 if (ret < 0)
3428 return ret;
3429
3430 intel_runtime_pm_get(dev_priv);
3431 if (!dev_priv->ipc_enabled && enable)
3432 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3433 dev_priv->wm.distrust_bios_wm = true;
3434 dev_priv->ipc_enabled = enable;
3435 intel_enable_ipc(dev_priv);
3436 intel_runtime_pm_put(dev_priv);
3437
3438 return len;
3439 }
3440
3441 static const struct file_operations i915_ipc_status_fops = {
3442 .owner = THIS_MODULE,
3443 .open = i915_ipc_status_open,
3444 .read = seq_read,
3445 .llseek = seq_lseek,
3446 .release = single_release,
3447 .write = i915_ipc_status_write
3448 };
3449
3450 static int i915_ddb_info(struct seq_file *m, void *unused)
3451 {
3452 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3453 struct drm_device *dev = &dev_priv->drm;
3454 struct skl_ddb_allocation *ddb;
3455 struct skl_ddb_entry *entry;
3456 enum pipe pipe;
3457 int plane;
3458
3459 if (INTEL_GEN(dev_priv) < 9)
3460 return 0;
3461
3462 drm_modeset_lock_all(dev);
3463
3464 ddb = &dev_priv->wm.skl_hw.ddb;
3465
3466 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3467
3468 for_each_pipe(dev_priv, pipe) {
3469 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3470
3471 for_each_universal_plane(dev_priv, pipe, plane) {
3472 entry = &ddb->plane[pipe][plane];
3473 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3474 entry->start, entry->end,
3475 skl_ddb_entry_size(entry));
3476 }
3477
3478 entry = &ddb->plane[pipe][PLANE_CURSOR];
3479 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3480 entry->end, skl_ddb_entry_size(entry));
3481 }
3482
3483 drm_modeset_unlock_all(dev);
3484
3485 return 0;
3486 }
3487
3488 static void drrs_status_per_crtc(struct seq_file *m,
3489 struct drm_device *dev,
3490 struct intel_crtc *intel_crtc)
3491 {
3492 struct drm_i915_private *dev_priv = to_i915(dev);
3493 struct i915_drrs *drrs = &dev_priv->drrs;
3494 int vrefresh = 0;
3495 struct drm_connector *connector;
3496 struct drm_connector_list_iter conn_iter;
3497
3498 drm_connector_list_iter_begin(dev, &conn_iter);
3499 drm_for_each_connector_iter(connector, &conn_iter) {
3500 if (connector->state->crtc != &intel_crtc->base)
3501 continue;
3502
3503 seq_printf(m, "%s:\n", connector->name);
3504 }
3505 drm_connector_list_iter_end(&conn_iter);
3506
3507 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3508 seq_puts(m, "\tVBT: DRRS_type: Static");
3509 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3510 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3511 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3512 seq_puts(m, "\tVBT: DRRS_type: None");
3513 else
3514 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3515
3516 seq_puts(m, "\n\n");
3517
3518 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3519 struct intel_panel *panel;
3520
3521 mutex_lock(&drrs->mutex);
3522 /* DRRS Supported */
3523 seq_puts(m, "\tDRRS Supported: Yes\n");
3524
3525 /* disable_drrs() will make drrs->dp NULL */
3526 if (!drrs->dp) {
3527 seq_puts(m, "Idleness DRRS: Disabled");
3528 mutex_unlock(&drrs->mutex);
3529 return;
3530 }
3531
3532 panel = &drrs->dp->attached_connector->panel;
3533 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3534 drrs->busy_frontbuffer_bits);
3535
3536 seq_puts(m, "\n\t\t");
3537 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3538 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3539 vrefresh = panel->fixed_mode->vrefresh;
3540 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3541 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3542 vrefresh = panel->downclock_mode->vrefresh;
3543 } else {
3544 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3545 drrs->refresh_rate_type);
3546 mutex_unlock(&drrs->mutex);
3547 return;
3548 }
3549 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3550
3551 seq_puts(m, "\n\t\t");
3552 mutex_unlock(&drrs->mutex);
3553 } else {
3554 /* DRRS not supported. Print the VBT parameter*/
3555 seq_puts(m, "\tDRRS Supported : No");
3556 }
3557 seq_puts(m, "\n");
3558 }
3559
3560 static int i915_drrs_status(struct seq_file *m, void *unused)
3561 {
3562 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3563 struct drm_device *dev = &dev_priv->drm;
3564 struct intel_crtc *intel_crtc;
3565 int active_crtc_cnt = 0;
3566
3567 drm_modeset_lock_all(dev);
3568 for_each_intel_crtc(dev, intel_crtc) {
3569 if (intel_crtc->base.state->active) {
3570 active_crtc_cnt++;
3571 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3572
3573 drrs_status_per_crtc(m, dev, intel_crtc);
3574 }
3575 }
3576 drm_modeset_unlock_all(dev);
3577
3578 if (!active_crtc_cnt)
3579 seq_puts(m, "No active crtc found\n");
3580
3581 return 0;
3582 }
3583
3584 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3585 {
3586 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3587 struct drm_device *dev = &dev_priv->drm;
3588 struct intel_encoder *intel_encoder;
3589 struct intel_digital_port *intel_dig_port;
3590 struct drm_connector *connector;
3591 struct drm_connector_list_iter conn_iter;
3592
3593 drm_connector_list_iter_begin(dev, &conn_iter);
3594 drm_for_each_connector_iter(connector, &conn_iter) {
3595 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3596 continue;
3597
3598 intel_encoder = intel_attached_encoder(connector);
3599 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3600 continue;
3601
3602 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3603 if (!intel_dig_port->dp.can_mst)
3604 continue;
3605
3606 seq_printf(m, "MST Source Port %c\n",
3607 port_name(intel_dig_port->port));
3608 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3609 }
3610 drm_connector_list_iter_end(&conn_iter);
3611
3612 return 0;
3613 }
3614
3615 static ssize_t i915_displayport_test_active_write(struct file *file,
3616 const char __user *ubuf,
3617 size_t len, loff_t *offp)
3618 {
3619 char *input_buffer;
3620 int status = 0;
3621 struct drm_device *dev;
3622 struct drm_connector *connector;
3623 struct drm_connector_list_iter conn_iter;
3624 struct intel_dp *intel_dp;
3625 int val = 0;
3626
3627 dev = ((struct seq_file *)file->private_data)->private;
3628
3629 if (len == 0)
3630 return 0;
3631
3632 input_buffer = memdup_user_nul(ubuf, len);
3633 if (IS_ERR(input_buffer))
3634 return PTR_ERR(input_buffer);
3635
3636 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3637
3638 drm_connector_list_iter_begin(dev, &conn_iter);
3639 drm_for_each_connector_iter(connector, &conn_iter) {
3640 struct intel_encoder *encoder;
3641
3642 if (connector->connector_type !=
3643 DRM_MODE_CONNECTOR_DisplayPort)
3644 continue;
3645
3646 encoder = to_intel_encoder(connector->encoder);
3647 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3648 continue;
3649
3650 if (encoder && connector->status == connector_status_connected) {
3651 intel_dp = enc_to_intel_dp(&encoder->base);
3652 status = kstrtoint(input_buffer, 10, &val);
3653 if (status < 0)
3654 break;
3655 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3656 /* To prevent erroneous activation of the compliance
3657 * testing code, only accept an actual value of 1 here
3658 */
3659 if (val == 1)
3660 intel_dp->compliance.test_active = 1;
3661 else
3662 intel_dp->compliance.test_active = 0;
3663 }
3664 }
3665 drm_connector_list_iter_end(&conn_iter);
3666 kfree(input_buffer);
3667 if (status < 0)
3668 return status;
3669
3670 *offp += len;
3671 return len;
3672 }
3673
3674 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3675 {
3676 struct drm_device *dev = m->private;
3677 struct drm_connector *connector;
3678 struct drm_connector_list_iter conn_iter;
3679 struct intel_dp *intel_dp;
3680
3681 drm_connector_list_iter_begin(dev, &conn_iter);
3682 drm_for_each_connector_iter(connector, &conn_iter) {
3683 struct intel_encoder *encoder;
3684
3685 if (connector->connector_type !=
3686 DRM_MODE_CONNECTOR_DisplayPort)
3687 continue;
3688
3689 encoder = to_intel_encoder(connector->encoder);
3690 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3691 continue;
3692
3693 if (encoder && connector->status == connector_status_connected) {
3694 intel_dp = enc_to_intel_dp(&encoder->base);
3695 if (intel_dp->compliance.test_active)
3696 seq_puts(m, "1");
3697 else
3698 seq_puts(m, "0");
3699 } else
3700 seq_puts(m, "0");
3701 }
3702 drm_connector_list_iter_end(&conn_iter);
3703
3704 return 0;
3705 }
3706
3707 static int i915_displayport_test_active_open(struct inode *inode,
3708 struct file *file)
3709 {
3710 struct drm_i915_private *dev_priv = inode->i_private;
3711
3712 return single_open(file, i915_displayport_test_active_show,
3713 &dev_priv->drm);
3714 }
3715
3716 static const struct file_operations i915_displayport_test_active_fops = {
3717 .owner = THIS_MODULE,
3718 .open = i915_displayport_test_active_open,
3719 .read = seq_read,
3720 .llseek = seq_lseek,
3721 .release = single_release,
3722 .write = i915_displayport_test_active_write
3723 };
3724
3725 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3726 {
3727 struct drm_device *dev = m->private;
3728 struct drm_connector *connector;
3729 struct drm_connector_list_iter conn_iter;
3730 struct intel_dp *intel_dp;
3731
3732 drm_connector_list_iter_begin(dev, &conn_iter);
3733 drm_for_each_connector_iter(connector, &conn_iter) {
3734 struct intel_encoder *encoder;
3735
3736 if (connector->connector_type !=
3737 DRM_MODE_CONNECTOR_DisplayPort)
3738 continue;
3739
3740 encoder = to_intel_encoder(connector->encoder);
3741 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3742 continue;
3743
3744 if (encoder && connector->status == connector_status_connected) {
3745 intel_dp = enc_to_intel_dp(&encoder->base);
3746 if (intel_dp->compliance.test_type ==
3747 DP_TEST_LINK_EDID_READ)
3748 seq_printf(m, "%lx",
3749 intel_dp->compliance.test_data.edid);
3750 else if (intel_dp->compliance.test_type ==
3751 DP_TEST_LINK_VIDEO_PATTERN) {
3752 seq_printf(m, "hdisplay: %d\n",
3753 intel_dp->compliance.test_data.hdisplay);
3754 seq_printf(m, "vdisplay: %d\n",
3755 intel_dp->compliance.test_data.vdisplay);
3756 seq_printf(m, "bpc: %u\n",
3757 intel_dp->compliance.test_data.bpc);
3758 }
3759 } else
3760 seq_puts(m, "0");
3761 }
3762 drm_connector_list_iter_end(&conn_iter);
3763
3764 return 0;
3765 }
3766 static int i915_displayport_test_data_open(struct inode *inode,
3767 struct file *file)
3768 {
3769 struct drm_i915_private *dev_priv = inode->i_private;
3770
3771 return single_open(file, i915_displayport_test_data_show,
3772 &dev_priv->drm);
3773 }
3774
3775 static const struct file_operations i915_displayport_test_data_fops = {
3776 .owner = THIS_MODULE,
3777 .open = i915_displayport_test_data_open,
3778 .read = seq_read,
3779 .llseek = seq_lseek,
3780 .release = single_release
3781 };
3782
3783 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3784 {
3785 struct drm_device *dev = m->private;
3786 struct drm_connector *connector;
3787 struct drm_connector_list_iter conn_iter;
3788 struct intel_dp *intel_dp;
3789
3790 drm_connector_list_iter_begin(dev, &conn_iter);
3791 drm_for_each_connector_iter(connector, &conn_iter) {
3792 struct intel_encoder *encoder;
3793
3794 if (connector->connector_type !=
3795 DRM_MODE_CONNECTOR_DisplayPort)
3796 continue;
3797
3798 encoder = to_intel_encoder(connector->encoder);
3799 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3800 continue;
3801
3802 if (encoder && connector->status == connector_status_connected) {
3803 intel_dp = enc_to_intel_dp(&encoder->base);
3804 seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3805 } else
3806 seq_puts(m, "0");
3807 }
3808 drm_connector_list_iter_end(&conn_iter);
3809
3810 return 0;
3811 }
3812
3813 static int i915_displayport_test_type_open(struct inode *inode,
3814 struct file *file)
3815 {
3816 struct drm_i915_private *dev_priv = inode->i_private;
3817
3818 return single_open(file, i915_displayport_test_type_show,
3819 &dev_priv->drm);
3820 }
3821
3822 static const struct file_operations i915_displayport_test_type_fops = {
3823 .owner = THIS_MODULE,
3824 .open = i915_displayport_test_type_open,
3825 .read = seq_read,
3826 .llseek = seq_lseek,
3827 .release = single_release
3828 };
3829
3830 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3831 {
3832 struct drm_i915_private *dev_priv = m->private;
3833 struct drm_device *dev = &dev_priv->drm;
3834 int level;
3835 int num_levels;
3836
3837 if (IS_CHERRYVIEW(dev_priv))
3838 num_levels = 3;
3839 else if (IS_VALLEYVIEW(dev_priv))
3840 num_levels = 1;
3841 else if (IS_G4X(dev_priv))
3842 num_levels = 3;
3843 else
3844 num_levels = ilk_wm_max_level(dev_priv) + 1;
3845
3846 drm_modeset_lock_all(dev);
3847
3848 for (level = 0; level < num_levels; level++) {
3849 unsigned int latency = wm[level];
3850
3851 /*
3852 * - WM1+ latency values in 0.5us units
3853 * - latencies are in us on gen9/vlv/chv
3854 */
3855 if (INTEL_GEN(dev_priv) >= 9 ||
3856 IS_VALLEYVIEW(dev_priv) ||
3857 IS_CHERRYVIEW(dev_priv) ||
3858 IS_G4X(dev_priv))
3859 latency *= 10;
3860 else if (level > 0)
3861 latency *= 5;
3862
3863 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3864 level, wm[level], latency / 10, latency % 10);
3865 }
3866
3867 drm_modeset_unlock_all(dev);
3868 }
3869
3870 static int pri_wm_latency_show(struct seq_file *m, void *data)
3871 {
3872 struct drm_i915_private *dev_priv = m->private;
3873 const uint16_t *latencies;
3874
3875 if (INTEL_GEN(dev_priv) >= 9)
3876 latencies = dev_priv->wm.skl_latency;
3877 else
3878 latencies = dev_priv->wm.pri_latency;
3879
3880 wm_latency_show(m, latencies);
3881
3882 return 0;
3883 }
3884
3885 static int spr_wm_latency_show(struct seq_file *m, void *data)
3886 {
3887 struct drm_i915_private *dev_priv = m->private;
3888 const uint16_t *latencies;
3889
3890 if (INTEL_GEN(dev_priv) >= 9)
3891 latencies = dev_priv->wm.skl_latency;
3892 else
3893 latencies = dev_priv->wm.spr_latency;
3894
3895 wm_latency_show(m, latencies);
3896
3897 return 0;
3898 }
3899
3900 static int cur_wm_latency_show(struct seq_file *m, void *data)
3901 {
3902 struct drm_i915_private *dev_priv = m->private;
3903 const uint16_t *latencies;
3904
3905 if (INTEL_GEN(dev_priv) >= 9)
3906 latencies = dev_priv->wm.skl_latency;
3907 else
3908 latencies = dev_priv->wm.cur_latency;
3909
3910 wm_latency_show(m, latencies);
3911
3912 return 0;
3913 }
3914
3915 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3916 {
3917 struct drm_i915_private *dev_priv = inode->i_private;
3918
3919 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3920 return -ENODEV;
3921
3922 return single_open(file, pri_wm_latency_show, dev_priv);
3923 }
3924
3925 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3926 {
3927 struct drm_i915_private *dev_priv = inode->i_private;
3928
3929 if (HAS_GMCH_DISPLAY(dev_priv))
3930 return -ENODEV;
3931
3932 return single_open(file, spr_wm_latency_show, dev_priv);
3933 }
3934
3935 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3936 {
3937 struct drm_i915_private *dev_priv = inode->i_private;
3938
3939 if (HAS_GMCH_DISPLAY(dev_priv))
3940 return -ENODEV;
3941
3942 return single_open(file, cur_wm_latency_show, dev_priv);
3943 }
3944
3945 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3946 size_t len, loff_t *offp, uint16_t wm[8])
3947 {
3948 struct seq_file *m = file->private_data;
3949 struct drm_i915_private *dev_priv = m->private;
3950 struct drm_device *dev = &dev_priv->drm;
3951 uint16_t new[8] = { 0 };
3952 int num_levels;
3953 int level;
3954 int ret;
3955 char tmp[32];
3956
3957 if (IS_CHERRYVIEW(dev_priv))
3958 num_levels = 3;
3959 else if (IS_VALLEYVIEW(dev_priv))
3960 num_levels = 1;
3961 else if (IS_G4X(dev_priv))
3962 num_levels = 3;
3963 else
3964 num_levels = ilk_wm_max_level(dev_priv) + 1;
3965
3966 if (len >= sizeof(tmp))
3967 return -EINVAL;
3968
3969 if (copy_from_user(tmp, ubuf, len))
3970 return -EFAULT;
3971
3972 tmp[len] = '\0';
3973
3974 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3975 &new[0], &new[1], &new[2], &new[3],
3976 &new[4], &new[5], &new[6], &new[7]);
3977 if (ret != num_levels)
3978 return -EINVAL;
3979
3980 drm_modeset_lock_all(dev);
3981
3982 for (level = 0; level < num_levels; level++)
3983 wm[level] = new[level];
3984
3985 drm_modeset_unlock_all(dev);
3986
3987 return len;
3988 }
3989
3990
3991 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3992 size_t len, loff_t *offp)
3993 {
3994 struct seq_file *m = file->private_data;
3995 struct drm_i915_private *dev_priv = m->private;
3996 uint16_t *latencies;
3997
3998 if (INTEL_GEN(dev_priv) >= 9)
3999 latencies = dev_priv->wm.skl_latency;
4000 else
4001 latencies = dev_priv->wm.pri_latency;
4002
4003 return wm_latency_write(file, ubuf, len, offp, latencies);
4004 }
4005
4006 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4007 size_t len, loff_t *offp)
4008 {
4009 struct seq_file *m = file->private_data;
4010 struct drm_i915_private *dev_priv = m->private;
4011 uint16_t *latencies;
4012
4013 if (INTEL_GEN(dev_priv) >= 9)
4014 latencies = dev_priv->wm.skl_latency;
4015 else
4016 latencies = dev_priv->wm.spr_latency;
4017
4018 return wm_latency_write(file, ubuf, len, offp, latencies);
4019 }
4020
4021 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4022 size_t len, loff_t *offp)
4023 {
4024 struct seq_file *m = file->private_data;
4025 struct drm_i915_private *dev_priv = m->private;
4026 uint16_t *latencies;
4027
4028 if (INTEL_GEN(dev_priv) >= 9)
4029 latencies = dev_priv->wm.skl_latency;
4030 else
4031 latencies = dev_priv->wm.cur_latency;
4032
4033 return wm_latency_write(file, ubuf, len, offp, latencies);
4034 }
4035
4036 static const struct file_operations i915_pri_wm_latency_fops = {
4037 .owner = THIS_MODULE,
4038 .open = pri_wm_latency_open,
4039 .read = seq_read,
4040 .llseek = seq_lseek,
4041 .release = single_release,
4042 .write = pri_wm_latency_write
4043 };
4044
4045 static const struct file_operations i915_spr_wm_latency_fops = {
4046 .owner = THIS_MODULE,
4047 .open = spr_wm_latency_open,
4048 .read = seq_read,
4049 .llseek = seq_lseek,
4050 .release = single_release,
4051 .write = spr_wm_latency_write
4052 };
4053
4054 static const struct file_operations i915_cur_wm_latency_fops = {
4055 .owner = THIS_MODULE,
4056 .open = cur_wm_latency_open,
4057 .read = seq_read,
4058 .llseek = seq_lseek,
4059 .release = single_release,
4060 .write = cur_wm_latency_write
4061 };
4062
4063 static int
4064 i915_wedged_get(void *data, u64 *val)
4065 {
4066 struct drm_i915_private *dev_priv = data;
4067
4068 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4069
4070 return 0;
4071 }
4072
4073 static int
4074 i915_wedged_set(void *data, u64 val)
4075 {
4076 struct drm_i915_private *i915 = data;
4077 struct intel_engine_cs *engine;
4078 unsigned int tmp;
4079
4080 /*
4081 * There is no safeguard against this debugfs entry colliding
4082 * with the hangcheck calling same i915_handle_error() in
4083 * parallel, causing an explosion. For now we assume that the
4084 * test harness is responsible enough not to inject gpu hangs
4085 * while it is writing to 'i915_wedged'
4086 */
4087
4088 if (i915_reset_backoff(&i915->gpu_error))
4089 return -EAGAIN;
4090
4091 for_each_engine_masked(engine, i915, val, tmp) {
4092 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4093 engine->hangcheck.stalled = true;
4094 }
4095
4096 i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4097
4098 wait_on_bit(&i915->gpu_error.flags,
4099 I915_RESET_HANDOFF,
4100 TASK_UNINTERRUPTIBLE);
4101
4102 return 0;
4103 }
4104
4105 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4106 i915_wedged_get, i915_wedged_set,
4107 "%llu\n");
4108
4109 static int
4110 fault_irq_set(struct drm_i915_private *i915,
4111 unsigned long *irq,
4112 unsigned long val)
4113 {
4114 int err;
4115
4116 err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4117 if (err)
4118 return err;
4119
4120 err = i915_gem_wait_for_idle(i915,
4121 I915_WAIT_LOCKED |
4122 I915_WAIT_INTERRUPTIBLE);
4123 if (err)
4124 goto err_unlock;
4125
4126 *irq = val;
4127 mutex_unlock(&i915->drm.struct_mutex);
4128
4129 /* Flush idle worker to disarm irq */
4130 drain_delayed_work(&i915->gt.idle_work);
4131
4132 return 0;
4133
4134 err_unlock:
4135 mutex_unlock(&i915->drm.struct_mutex);
4136 return err;
4137 }
4138
4139 static int
4140 i915_ring_missed_irq_get(void *data, u64 *val)
4141 {
4142 struct drm_i915_private *dev_priv = data;
4143
4144 *val = dev_priv->gpu_error.missed_irq_rings;
4145 return 0;
4146 }
4147
4148 static int
4149 i915_ring_missed_irq_set(void *data, u64 val)
4150 {
4151 struct drm_i915_private *i915 = data;
4152
4153 return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4154 }
4155
4156 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4157 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4158 "0x%08llx\n");
4159
4160 static int
4161 i915_ring_test_irq_get(void *data, u64 *val)
4162 {
4163 struct drm_i915_private *dev_priv = data;
4164
4165 *val = dev_priv->gpu_error.test_irq_rings;
4166
4167 return 0;
4168 }
4169
4170 static int
4171 i915_ring_test_irq_set(void *data, u64 val)
4172 {
4173 struct drm_i915_private *i915 = data;
4174
4175 val &= INTEL_INFO(i915)->ring_mask;
4176 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4177
4178 return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4179 }
4180
4181 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4182 i915_ring_test_irq_get, i915_ring_test_irq_set,
4183 "0x%08llx\n");
4184
4185 #define DROP_UNBOUND BIT(0)
4186 #define DROP_BOUND BIT(1)
4187 #define DROP_RETIRE BIT(2)
4188 #define DROP_ACTIVE BIT(3)
4189 #define DROP_FREED BIT(4)
4190 #define DROP_SHRINK_ALL BIT(5)
4191 #define DROP_IDLE BIT(6)
4192 #define DROP_ALL (DROP_UNBOUND | \
4193 DROP_BOUND | \
4194 DROP_RETIRE | \
4195 DROP_ACTIVE | \
4196 DROP_FREED | \
4197 DROP_SHRINK_ALL |\
4198 DROP_IDLE)
4199 static int
4200 i915_drop_caches_get(void *data, u64 *val)
4201 {
4202 *val = DROP_ALL;
4203
4204 return 0;
4205 }
4206
4207 static int
4208 i915_drop_caches_set(void *data, u64 val)
4209 {
4210 struct drm_i915_private *dev_priv = data;
4211 struct drm_device *dev = &dev_priv->drm;
4212 int ret = 0;
4213
4214 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4215 val, val & DROP_ALL);
4216
4217 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4218 * on ioctls on -EAGAIN. */
4219 if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4220 ret = mutex_lock_interruptible(&dev->struct_mutex);
4221 if (ret)
4222 return ret;
4223
4224 if (val & DROP_ACTIVE)
4225 ret = i915_gem_wait_for_idle(dev_priv,
4226 I915_WAIT_INTERRUPTIBLE |
4227 I915_WAIT_LOCKED);
4228
4229 if (val & DROP_RETIRE)
4230 i915_gem_retire_requests(dev_priv);
4231
4232 mutex_unlock(&dev->struct_mutex);
4233 }
4234
4235 fs_reclaim_acquire(GFP_KERNEL);
4236 if (val & DROP_BOUND)
4237 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4238
4239 if (val & DROP_UNBOUND)
4240 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4241
4242 if (val & DROP_SHRINK_ALL)
4243 i915_gem_shrink_all(dev_priv);
4244 fs_reclaim_release(GFP_KERNEL);
4245
4246 if (val & DROP_IDLE)
4247 drain_delayed_work(&dev_priv->gt.idle_work);
4248
4249 if (val & DROP_FREED) {
4250 synchronize_rcu();
4251 i915_gem_drain_freed_objects(dev_priv);
4252 }
4253
4254 return ret;
4255 }
4256
4257 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4258 i915_drop_caches_get, i915_drop_caches_set,
4259 "0x%08llx\n");
4260
4261 static int
4262 i915_max_freq_get(void *data, u64 *val)
4263 {
4264 struct drm_i915_private *dev_priv = data;
4265
4266 if (INTEL_GEN(dev_priv) < 6)
4267 return -ENODEV;
4268
4269 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4270 return 0;
4271 }
4272
4273 static int
4274 i915_max_freq_set(void *data, u64 val)
4275 {
4276 struct drm_i915_private *dev_priv = data;
4277 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4278 u32 hw_max, hw_min;
4279 int ret;
4280
4281 if (INTEL_GEN(dev_priv) < 6)
4282 return -ENODEV;
4283
4284 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4285
4286 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4287 if (ret)
4288 return ret;
4289
4290 /*
4291 * Turbo will still be enabled, but won't go above the set value.
4292 */
4293 val = intel_freq_opcode(dev_priv, val);
4294
4295 hw_max = rps->max_freq;
4296 hw_min = rps->min_freq;
4297
4298 if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4299 mutex_unlock(&dev_priv->pcu_lock);
4300 return -EINVAL;
4301 }
4302
4303 rps->max_freq_softlimit = val;
4304
4305 if (intel_set_rps(dev_priv, val))
4306 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4307
4308 mutex_unlock(&dev_priv->pcu_lock);
4309
4310 return 0;
4311 }
4312
4313 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4314 i915_max_freq_get, i915_max_freq_set,
4315 "%llu\n");
4316
4317 static int
4318 i915_min_freq_get(void *data, u64 *val)
4319 {
4320 struct drm_i915_private *dev_priv = data;
4321
4322 if (INTEL_GEN(dev_priv) < 6)
4323 return -ENODEV;
4324
4325 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4326 return 0;
4327 }
4328
4329 static int
4330 i915_min_freq_set(void *data, u64 val)
4331 {
4332 struct drm_i915_private *dev_priv = data;
4333 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4334 u32 hw_max, hw_min;
4335 int ret;
4336
4337 if (INTEL_GEN(dev_priv) < 6)
4338 return -ENODEV;
4339
4340 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4341
4342 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4343 if (ret)
4344 return ret;
4345
4346 /*
4347 * Turbo will still be enabled, but won't go below the set value.
4348 */
4349 val = intel_freq_opcode(dev_priv, val);
4350
4351 hw_max = rps->max_freq;
4352 hw_min = rps->min_freq;
4353
4354 if (val < hw_min ||
4355 val > hw_max || val > rps->max_freq_softlimit) {
4356 mutex_unlock(&dev_priv->pcu_lock);
4357 return -EINVAL;
4358 }
4359
4360 rps->min_freq_softlimit = val;
4361
4362 if (intel_set_rps(dev_priv, val))
4363 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4364
4365 mutex_unlock(&dev_priv->pcu_lock);
4366
4367 return 0;
4368 }
4369
4370 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4371 i915_min_freq_get, i915_min_freq_set,
4372 "%llu\n");
4373
4374 static int
4375 i915_cache_sharing_get(void *data, u64 *val)
4376 {
4377 struct drm_i915_private *dev_priv = data;
4378 u32 snpcr;
4379
4380 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4381 return -ENODEV;
4382
4383 intel_runtime_pm_get(dev_priv);
4384
4385 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4386
4387 intel_runtime_pm_put(dev_priv);
4388
4389 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4390
4391 return 0;
4392 }
4393
4394 static int
4395 i915_cache_sharing_set(void *data, u64 val)
4396 {
4397 struct drm_i915_private *dev_priv = data;
4398 u32 snpcr;
4399
4400 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4401 return -ENODEV;
4402
4403 if (val > 3)
4404 return -EINVAL;
4405
4406 intel_runtime_pm_get(dev_priv);
4407 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4408
4409 /* Update the cache sharing policy here as well */
4410 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4411 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4412 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4413 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4414
4415 intel_runtime_pm_put(dev_priv);
4416 return 0;
4417 }
4418
4419 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4420 i915_cache_sharing_get, i915_cache_sharing_set,
4421 "%llu\n");
4422
4423 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4424 struct sseu_dev_info *sseu)
4425 {
4426 int ss_max = 2;
4427 int ss;
4428 u32 sig1[ss_max], sig2[ss_max];
4429
4430 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4431 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4432 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4433 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4434
4435 for (ss = 0; ss < ss_max; ss++) {
4436 unsigned int eu_cnt;
4437
4438 if (sig1[ss] & CHV_SS_PG_ENABLE)
4439 /* skip disabled subslice */
4440 continue;
4441
4442 sseu->slice_mask = BIT(0);
4443 sseu->subslice_mask |= BIT(ss);
4444 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4445 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4446 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4447 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4448 sseu->eu_total += eu_cnt;
4449 sseu->eu_per_subslice = max_t(unsigned int,
4450 sseu->eu_per_subslice, eu_cnt);
4451 }
4452 }
4453
4454 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4455 struct sseu_dev_info *sseu)
4456 {
4457 int s_max = 3, ss_max = 4;
4458 int s, ss;
4459 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4460
4461 /* BXT has a single slice and at most 3 subslices. */
4462 if (IS_GEN9_LP(dev_priv)) {
4463 s_max = 1;
4464 ss_max = 3;
4465 }
4466
4467 for (s = 0; s < s_max; s++) {
4468 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4469 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4470 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4471 }
4472
4473 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4474 GEN9_PGCTL_SSA_EU19_ACK |
4475 GEN9_PGCTL_SSA_EU210_ACK |
4476 GEN9_PGCTL_SSA_EU311_ACK;
4477 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4478 GEN9_PGCTL_SSB_EU19_ACK |
4479 GEN9_PGCTL_SSB_EU210_ACK |
4480 GEN9_PGCTL_SSB_EU311_ACK;
4481
4482 for (s = 0; s < s_max; s++) {
4483 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4484 /* skip disabled slice */
4485 continue;
4486
4487 sseu->slice_mask |= BIT(s);
4488
4489 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
4490 sseu->subslice_mask =
4491 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4492
4493 for (ss = 0; ss < ss_max; ss++) {
4494 unsigned int eu_cnt;
4495
4496 if (IS_GEN9_LP(dev_priv)) {
4497 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4498 /* skip disabled subslice */
4499 continue;
4500
4501 sseu->subslice_mask |= BIT(ss);
4502 }
4503
4504 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4505 eu_mask[ss%2]);
4506 sseu->eu_total += eu_cnt;
4507 sseu->eu_per_subslice = max_t(unsigned int,
4508 sseu->eu_per_subslice,
4509 eu_cnt);
4510 }
4511 }
4512 }
4513
4514 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4515 struct sseu_dev_info *sseu)
4516 {
4517 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4518 int s;
4519
4520 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4521
4522 if (sseu->slice_mask) {
4523 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4524 sseu->eu_per_subslice =
4525 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4526 sseu->eu_total = sseu->eu_per_subslice *
4527 sseu_subslice_total(sseu);
4528
4529 /* subtract fused off EU(s) from enabled slice(s) */
4530 for (s = 0; s < fls(sseu->slice_mask); s++) {
4531 u8 subslice_7eu =
4532 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4533
4534 sseu->eu_total -= hweight8(subslice_7eu);
4535 }
4536 }
4537 }
4538
4539 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4540 const struct sseu_dev_info *sseu)
4541 {
4542 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4543 const char *type = is_available_info ? "Available" : "Enabled";
4544
4545 seq_printf(m, " %s Slice Mask: %04x\n", type,
4546 sseu->slice_mask);
4547 seq_printf(m, " %s Slice Total: %u\n", type,
4548 hweight8(sseu->slice_mask));
4549 seq_printf(m, " %s Subslice Total: %u\n", type,
4550 sseu_subslice_total(sseu));
4551 seq_printf(m, " %s Subslice Mask: %04x\n", type,
4552 sseu->subslice_mask);
4553 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
4554 hweight8(sseu->subslice_mask));
4555 seq_printf(m, " %s EU Total: %u\n", type,
4556 sseu->eu_total);
4557 seq_printf(m, " %s EU Per Subslice: %u\n", type,
4558 sseu->eu_per_subslice);
4559
4560 if (!is_available_info)
4561 return;
4562
4563 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4564 if (HAS_POOLED_EU(dev_priv))
4565 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
4566
4567 seq_printf(m, " Has Slice Power Gating: %s\n",
4568 yesno(sseu->has_slice_pg));
4569 seq_printf(m, " Has Subslice Power Gating: %s\n",
4570 yesno(sseu->has_subslice_pg));
4571 seq_printf(m, " Has EU Power Gating: %s\n",
4572 yesno(sseu->has_eu_pg));
4573 }
4574
4575 static int i915_sseu_status(struct seq_file *m, void *unused)
4576 {
4577 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4578 struct sseu_dev_info sseu;
4579
4580 if (INTEL_GEN(dev_priv) < 8)
4581 return -ENODEV;
4582
4583 seq_puts(m, "SSEU Device Info\n");
4584 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4585
4586 seq_puts(m, "SSEU Device Status\n");
4587 memset(&sseu, 0, sizeof(sseu));
4588
4589 intel_runtime_pm_get(dev_priv);
4590
4591 if (IS_CHERRYVIEW(dev_priv)) {
4592 cherryview_sseu_device_status(dev_priv, &sseu);
4593 } else if (IS_BROADWELL(dev_priv)) {
4594 broadwell_sseu_device_status(dev_priv, &sseu);
4595 } else if (INTEL_GEN(dev_priv) >= 9) {
4596 gen9_sseu_device_status(dev_priv, &sseu);
4597 }
4598
4599 intel_runtime_pm_put(dev_priv);
4600
4601 i915_print_sseu_info(m, false, &sseu);
4602
4603 return 0;
4604 }
4605
4606 static int i915_forcewake_open(struct inode *inode, struct file *file)
4607 {
4608 struct drm_i915_private *i915 = inode->i_private;
4609
4610 if (INTEL_GEN(i915) < 6)
4611 return 0;
4612
4613 intel_runtime_pm_get(i915);
4614 intel_uncore_forcewake_user_get(i915);
4615
4616 return 0;
4617 }
4618
4619 static int i915_forcewake_release(struct inode *inode, struct file *file)
4620 {
4621 struct drm_i915_private *i915 = inode->i_private;
4622
4623 if (INTEL_GEN(i915) < 6)
4624 return 0;
4625
4626 intel_uncore_forcewake_user_put(i915);
4627 intel_runtime_pm_put(i915);
4628
4629 return 0;
4630 }
4631
4632 static const struct file_operations i915_forcewake_fops = {
4633 .owner = THIS_MODULE,
4634 .open = i915_forcewake_open,
4635 .release = i915_forcewake_release,
4636 };
4637
4638 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4639 {
4640 struct drm_i915_private *dev_priv = m->private;
4641 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4642
4643 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4644 seq_printf(m, "Detected: %s\n",
4645 yesno(delayed_work_pending(&hotplug->reenable_work)));
4646
4647 return 0;
4648 }
4649
4650 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4651 const char __user *ubuf, size_t len,
4652 loff_t *offp)
4653 {
4654 struct seq_file *m = file->private_data;
4655 struct drm_i915_private *dev_priv = m->private;
4656 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4657 unsigned int new_threshold;
4658 int i;
4659 char *newline;
4660 char tmp[16];
4661
4662 if (len >= sizeof(tmp))
4663 return -EINVAL;
4664
4665 if (copy_from_user(tmp, ubuf, len))
4666 return -EFAULT;
4667
4668 tmp[len] = '\0';
4669
4670 /* Strip newline, if any */
4671 newline = strchr(tmp, '\n');
4672 if (newline)
4673 *newline = '\0';
4674
4675 if (strcmp(tmp, "reset") == 0)
4676 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4677 else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4678 return -EINVAL;
4679
4680 if (new_threshold > 0)
4681 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4682 new_threshold);
4683 else
4684 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4685
4686 spin_lock_irq(&dev_priv->irq_lock);
4687 hotplug->hpd_storm_threshold = new_threshold;
4688 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4689 for_each_hpd_pin(i)
4690 hotplug->stats[i].count = 0;
4691 spin_unlock_irq(&dev_priv->irq_lock);
4692
4693 /* Re-enable hpd immediately if we were in an irq storm */
4694 flush_delayed_work(&dev_priv->hotplug.reenable_work);
4695
4696 return len;
4697 }
4698
4699 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4700 {
4701 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4702 }
4703
4704 static const struct file_operations i915_hpd_storm_ctl_fops = {
4705 .owner = THIS_MODULE,
4706 .open = i915_hpd_storm_ctl_open,
4707 .read = seq_read,
4708 .llseek = seq_lseek,
4709 .release = single_release,
4710 .write = i915_hpd_storm_ctl_write
4711 };
4712
4713 static const struct drm_info_list i915_debugfs_list[] = {
4714 {"i915_capabilities", i915_capabilities, 0},
4715 {"i915_gem_objects", i915_gem_object_info, 0},
4716 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4717 {"i915_gem_stolen", i915_gem_stolen_list_info },
4718 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4719 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4720 {"i915_gem_interrupt", i915_interrupt_info, 0},
4721 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4722 {"i915_guc_info", i915_guc_info, 0},
4723 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4724 {"i915_guc_log_dump", i915_guc_log_dump, 0},
4725 {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4726 {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4727 {"i915_huc_load_status", i915_huc_load_status_info, 0},
4728 {"i915_frequency_info", i915_frequency_info, 0},
4729 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4730 {"i915_reset_info", i915_reset_info, 0},
4731 {"i915_drpc_info", i915_drpc_info, 0},
4732 {"i915_emon_status", i915_emon_status, 0},
4733 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4734 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4735 {"i915_fbc_status", i915_fbc_status, 0},
4736 {"i915_ips_status", i915_ips_status, 0},
4737 {"i915_sr_status", i915_sr_status, 0},
4738 {"i915_opregion", i915_opregion, 0},
4739 {"i915_vbt", i915_vbt, 0},
4740 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4741 {"i915_context_status", i915_context_status, 0},
4742 {"i915_dump_lrc", i915_dump_lrc, 0},
4743 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4744 {"i915_swizzle_info", i915_swizzle_info, 0},
4745 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4746 {"i915_llc", i915_llc, 0},
4747 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4748 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4749 {"i915_energy_uJ", i915_energy_uJ, 0},
4750 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4751 {"i915_power_domain_info", i915_power_domain_info, 0},
4752 {"i915_dmc_info", i915_dmc_info, 0},
4753 {"i915_display_info", i915_display_info, 0},
4754 {"i915_engine_info", i915_engine_info, 0},
4755 {"i915_shrinker_info", i915_shrinker_info, 0},
4756 {"i915_semaphore_status", i915_semaphore_status, 0},
4757 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4758 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4759 {"i915_wa_registers", i915_wa_registers, 0},
4760 {"i915_ddb_info", i915_ddb_info, 0},
4761 {"i915_sseu_status", i915_sseu_status, 0},
4762 {"i915_drrs_status", i915_drrs_status, 0},
4763 {"i915_rps_boost_info", i915_rps_boost_info, 0},
4764 };
4765 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4766
4767 static const struct i915_debugfs_files {
4768 const char *name;
4769 const struct file_operations *fops;
4770 } i915_debugfs_files[] = {
4771 {"i915_wedged", &i915_wedged_fops},
4772 {"i915_max_freq", &i915_max_freq_fops},
4773 {"i915_min_freq", &i915_min_freq_fops},
4774 {"i915_cache_sharing", &i915_cache_sharing_fops},
4775 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4776 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4777 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4778 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4779 {"i915_error_state", &i915_error_state_fops},
4780 {"i915_gpu_info", &i915_gpu_info_fops},
4781 #endif
4782 {"i915_next_seqno", &i915_next_seqno_fops},
4783 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4784 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4785 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4786 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4787 {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4788 {"i915_dp_test_data", &i915_displayport_test_data_fops},
4789 {"i915_dp_test_type", &i915_displayport_test_type_fops},
4790 {"i915_dp_test_active", &i915_displayport_test_active_fops},
4791 {"i915_guc_log_control", &i915_guc_log_control_fops},
4792 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4793 {"i915_ipc_status", &i915_ipc_status_fops}
4794 };
4795
4796 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4797 {
4798 struct drm_minor *minor = dev_priv->drm.primary;
4799 struct dentry *ent;
4800 int ret, i;
4801
4802 ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4803 minor->debugfs_root, to_i915(minor->dev),
4804 &i915_forcewake_fops);
4805 if (!ent)
4806 return -ENOMEM;
4807
4808 ret = intel_pipe_crc_create(minor);
4809 if (ret)
4810 return ret;
4811
4812 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4813 ent = debugfs_create_file(i915_debugfs_files[i].name,
4814 S_IRUGO | S_IWUSR,
4815 minor->debugfs_root,
4816 to_i915(minor->dev),
4817 i915_debugfs_files[i].fops);
4818 if (!ent)
4819 return -ENOMEM;
4820 }
4821
4822 return drm_debugfs_create_files(i915_debugfs_list,
4823 I915_DEBUGFS_ENTRIES,
4824 minor->debugfs_root, minor);
4825 }
4826
4827 struct dpcd_block {
4828 /* DPCD dump start address. */
4829 unsigned int offset;
4830 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4831 unsigned int end;
4832 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4833 size_t size;
4834 /* Only valid for eDP. */
4835 bool edp;
4836 };
4837
4838 static const struct dpcd_block i915_dpcd_debug[] = {
4839 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4840 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4841 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4842 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4843 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4844 { .offset = DP_SET_POWER },
4845 { .offset = DP_EDP_DPCD_REV },
4846 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4847 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4848 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4849 };
4850
4851 static int i915_dpcd_show(struct seq_file *m, void *data)
4852 {
4853 struct drm_connector *connector = m->private;
4854 struct intel_dp *intel_dp =
4855 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4856 uint8_t buf[16];
4857 ssize_t err;
4858 int i;
4859
4860 if (connector->status != connector_status_connected)
4861 return -ENODEV;
4862
4863 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4864 const struct dpcd_block *b = &i915_dpcd_debug[i];
4865 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4866
4867 if (b->edp &&
4868 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4869 continue;
4870
4871 /* low tech for now */
4872 if (WARN_ON(size > sizeof(buf)))
4873 continue;
4874
4875 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4876 if (err <= 0) {
4877 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4878 size, b->offset, err);
4879 continue;
4880 }
4881
4882 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4883 }
4884
4885 return 0;
4886 }
4887
4888 static int i915_dpcd_open(struct inode *inode, struct file *file)
4889 {
4890 return single_open(file, i915_dpcd_show, inode->i_private);
4891 }
4892
4893 static const struct file_operations i915_dpcd_fops = {
4894 .owner = THIS_MODULE,
4895 .open = i915_dpcd_open,
4896 .read = seq_read,
4897 .llseek = seq_lseek,
4898 .release = single_release,
4899 };
4900
4901 static int i915_panel_show(struct seq_file *m, void *data)
4902 {
4903 struct drm_connector *connector = m->private;
4904 struct intel_dp *intel_dp =
4905 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4906
4907 if (connector->status != connector_status_connected)
4908 return -ENODEV;
4909
4910 seq_printf(m, "Panel power up delay: %d\n",
4911 intel_dp->panel_power_up_delay);
4912 seq_printf(m, "Panel power down delay: %d\n",
4913 intel_dp->panel_power_down_delay);
4914 seq_printf(m, "Backlight on delay: %d\n",
4915 intel_dp->backlight_on_delay);
4916 seq_printf(m, "Backlight off delay: %d\n",
4917 intel_dp->backlight_off_delay);
4918
4919 return 0;
4920 }
4921
4922 static int i915_panel_open(struct inode *inode, struct file *file)
4923 {
4924 return single_open(file, i915_panel_show, inode->i_private);
4925 }
4926
4927 static const struct file_operations i915_panel_fops = {
4928 .owner = THIS_MODULE,
4929 .open = i915_panel_open,
4930 .read = seq_read,
4931 .llseek = seq_lseek,
4932 .release = single_release,
4933 };
4934
4935 /**
4936 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4937 * @connector: pointer to a registered drm_connector
4938 *
4939 * Cleanup will be done by drm_connector_unregister() through a call to
4940 * drm_debugfs_connector_remove().
4941 *
4942 * Returns 0 on success, negative error codes on error.
4943 */
4944 int i915_debugfs_connector_add(struct drm_connector *connector)
4945 {
4946 struct dentry *root = connector->debugfs_entry;
4947
4948 /* The connector must have been registered beforehands. */
4949 if (!root)
4950 return -ENODEV;
4951
4952 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4953 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4954 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4955 connector, &i915_dpcd_fops);
4956
4957 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4958 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4959 connector, &i915_panel_fops);
4960
4961 return 0;
4962 }
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