1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver
;
57 static unsigned int i915_load_fail_count
;
59 bool __i915_inject_load_failure(const char *func
, int line
)
61 if (i915_load_fail_count
>= i915_modparams
.inject_load_failure
)
64 if (++i915_load_fail_count
== i915_modparams
.inject_load_failure
) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915_modparams
.inject_load_failure
, func
, line
);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
81 static bool shown_bug_once
;
82 struct device
*kdev
= dev_priv
->drm
.dev
;
83 bool is_error
= level
[1] <= KERN_ERR
[1];
84 bool is_debug
= level
[1] == KERN_DEBUG
[1];
88 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
96 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
97 __builtin_return_address(0), &vaf
);
99 if (is_error
&& !shown_bug_once
) {
100 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
101 shown_bug_once
= true;
107 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
109 return i915_modparams
.inject_load_failure
&&
110 i915_load_fail_count
== i915_modparams
.inject_load_failure
;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch
intel_virt_detect_pch(struct drm_i915_private
*dev_priv
)
121 enum intel_pch ret
= PCH_NOP
;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv
)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
)) {
135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
138 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
139 dev_priv
->pch_id
= INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
141 dev_priv
->pch_id
= INTEL_PCH_LPT_DEVICE_ID_TYPE
;
142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
143 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146 } else if (IS_COFFEELAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
154 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
156 struct pci_dev
*pch
= NULL
;
158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
161 if (INTEL_INFO(dev_priv
)->num_pipes
== 0) {
162 dev_priv
->pch_type
= PCH_NOP
;
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
177 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
178 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
179 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
181 dev_priv
->pch_id
= id
;
183 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
184 dev_priv
->pch_type
= PCH_IBX
;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
186 WARN_ON(!IS_GEN5(dev_priv
));
187 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
188 dev_priv
->pch_type
= PCH_CPT
;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
190 WARN_ON(!IS_GEN6(dev_priv
) &&
191 !IS_IVYBRIDGE(dev_priv
));
192 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
193 /* PantherPoint is CPT compatible */
194 dev_priv
->pch_type
= PCH_CPT
;
195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
196 WARN_ON(!IS_GEN6(dev_priv
) &&
197 !IS_IVYBRIDGE(dev_priv
));
198 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
199 dev_priv
->pch_type
= PCH_LPT
;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201 WARN_ON(!IS_HASWELL(dev_priv
) &&
202 !IS_BROADWELL(dev_priv
));
203 WARN_ON(IS_HSW_ULT(dev_priv
) ||
204 IS_BDW_ULT(dev_priv
));
205 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
206 dev_priv
->pch_type
= PCH_LPT
;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
208 WARN_ON(!IS_HASWELL(dev_priv
) &&
209 !IS_BROADWELL(dev_priv
));
210 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
211 !IS_BDW_ULT(dev_priv
));
212 } else if (id
== INTEL_PCH_WPT_DEVICE_ID_TYPE
) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv
->pch_type
= PCH_LPT
;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv
) &&
217 !IS_BROADWELL(dev_priv
));
218 WARN_ON(IS_HSW_ULT(dev_priv
) ||
219 IS_BDW_ULT(dev_priv
));
220 } else if (id
== INTEL_PCH_WPT_LP_DEVICE_ID_TYPE
) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv
->pch_type
= PCH_LPT
;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv
) &&
225 !IS_BROADWELL(dev_priv
));
226 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
227 !IS_BDW_ULT(dev_priv
));
228 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
229 dev_priv
->pch_type
= PCH_SPT
;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
231 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
232 !IS_KABYLAKE(dev_priv
));
233 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
234 dev_priv
->pch_type
= PCH_SPT
;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
236 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
237 !IS_KABYLAKE(dev_priv
));
238 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
239 dev_priv
->pch_type
= PCH_KBP
;
240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
241 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
242 !IS_KABYLAKE(dev_priv
) &&
243 !IS_COFFEELAKE(dev_priv
));
244 } else if (id
== INTEL_PCH_CNP_DEVICE_ID_TYPE
) {
245 dev_priv
->pch_type
= PCH_CNP
;
246 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
247 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
248 !IS_COFFEELAKE(dev_priv
));
249 } else if (id
== INTEL_PCH_CNP_LP_DEVICE_ID_TYPE
) {
250 dev_priv
->pch_type
= PCH_CNP
;
251 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
252 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
253 !IS_COFFEELAKE(dev_priv
));
254 } else if (id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
||
255 id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
||
256 (id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
&&
257 pch
->subsystem_vendor
==
258 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
259 pch
->subsystem_device
==
260 PCI_SUBDEVICE_ID_QEMU
)) {
262 intel_virt_detect_pch(dev_priv
);
270 DRM_DEBUG_KMS("No PCH found.\n");
275 static int i915_getparam(struct drm_device
*dev
, void *data
,
276 struct drm_file
*file_priv
)
278 struct drm_i915_private
*dev_priv
= to_i915(dev
);
279 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
280 drm_i915_getparam_t
*param
= data
;
283 switch (param
->param
) {
284 case I915_PARAM_IRQ_ACTIVE
:
285 case I915_PARAM_ALLOW_BATCHBUFFER
:
286 case I915_PARAM_LAST_DISPATCH
:
287 case I915_PARAM_HAS_EXEC_CONSTANTS
:
288 /* Reject all old ums/dri params. */
290 case I915_PARAM_CHIPSET_ID
:
291 value
= pdev
->device
;
293 case I915_PARAM_REVISION
:
294 value
= pdev
->revision
;
296 case I915_PARAM_NUM_FENCES_AVAIL
:
297 value
= dev_priv
->num_fence_regs
;
299 case I915_PARAM_HAS_OVERLAY
:
300 value
= dev_priv
->overlay
? 1 : 0;
302 case I915_PARAM_HAS_BSD
:
303 value
= !!dev_priv
->engine
[VCS
];
305 case I915_PARAM_HAS_BLT
:
306 value
= !!dev_priv
->engine
[BCS
];
308 case I915_PARAM_HAS_VEBOX
:
309 value
= !!dev_priv
->engine
[VECS
];
311 case I915_PARAM_HAS_BSD2
:
312 value
= !!dev_priv
->engine
[VCS2
];
314 case I915_PARAM_HAS_LLC
:
315 value
= HAS_LLC(dev_priv
);
317 case I915_PARAM_HAS_WT
:
318 value
= HAS_WT(dev_priv
);
320 case I915_PARAM_HAS_ALIASING_PPGTT
:
321 value
= USES_PPGTT(dev_priv
);
323 case I915_PARAM_HAS_SEMAPHORES
:
324 value
= i915_modparams
.semaphores
;
326 case I915_PARAM_HAS_SECURE_BATCHES
:
327 value
= HAS_SECURE_BATCHES(dev_priv
) && capable(CAP_SYS_ADMIN
);
329 case I915_PARAM_CMD_PARSER_VERSION
:
330 value
= i915_cmd_parser_get_version(dev_priv
);
332 case I915_PARAM_SUBSLICE_TOTAL
:
333 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
337 case I915_PARAM_EU_TOTAL
:
338 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
342 case I915_PARAM_HAS_GPU_RESET
:
343 value
= i915_modparams
.enable_hangcheck
&&
344 intel_has_gpu_reset(dev_priv
);
345 if (value
&& intel_has_reset_engine(dev_priv
))
348 case I915_PARAM_HAS_RESOURCE_STREAMER
:
349 value
= HAS_RESOURCE_STREAMER(dev_priv
);
351 case I915_PARAM_HAS_POOLED_EU
:
352 value
= HAS_POOLED_EU(dev_priv
);
354 case I915_PARAM_MIN_EU_IN_POOL
:
355 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
357 case I915_PARAM_HUC_STATUS
:
358 intel_runtime_pm_get(dev_priv
);
359 value
= I915_READ(HUC_STATUS2
) & HUC_FW_VERIFIED
;
360 intel_runtime_pm_put(dev_priv
);
362 case I915_PARAM_MMAP_GTT_VERSION
:
363 /* Though we've started our numbering from 1, and so class all
364 * earlier versions as 0, in effect their value is undefined as
365 * the ioctl will report EINVAL for the unknown param!
367 value
= i915_gem_mmap_gtt_version();
369 case I915_PARAM_HAS_SCHEDULER
:
371 if (dev_priv
->engine
[RCS
] && dev_priv
->engine
[RCS
]->schedule
) {
372 value
|= I915_SCHEDULER_CAP_ENABLED
;
373 value
|= I915_SCHEDULER_CAP_PRIORITY
;
375 if (INTEL_INFO(dev_priv
)->has_logical_ring_preemption
&&
376 i915_modparams
.enable_execlists
&&
377 !i915_modparams
.enable_guc_submission
)
378 value
|= I915_SCHEDULER_CAP_PREEMPTION
;
382 case I915_PARAM_MMAP_VERSION
:
383 /* Remember to bump this if the version changes! */
384 case I915_PARAM_HAS_GEM
:
385 case I915_PARAM_HAS_PAGEFLIPPING
:
386 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
387 case I915_PARAM_HAS_RELAXED_FENCING
:
388 case I915_PARAM_HAS_COHERENT_RINGS
:
389 case I915_PARAM_HAS_RELAXED_DELTA
:
390 case I915_PARAM_HAS_GEN7_SOL_RESET
:
391 case I915_PARAM_HAS_WAIT_TIMEOUT
:
392 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
393 case I915_PARAM_HAS_PINNED_BATCHES
:
394 case I915_PARAM_HAS_EXEC_NO_RELOC
:
395 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
396 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
397 case I915_PARAM_HAS_EXEC_SOFTPIN
:
398 case I915_PARAM_HAS_EXEC_ASYNC
:
399 case I915_PARAM_HAS_EXEC_FENCE
:
400 case I915_PARAM_HAS_EXEC_CAPTURE
:
401 case I915_PARAM_HAS_EXEC_BATCH_FIRST
:
402 case I915_PARAM_HAS_EXEC_FENCE_ARRAY
:
403 /* For the time being all of these are always true;
404 * if some supported hardware does not have one of these
405 * features this value needs to be provided from
406 * INTEL_INFO(), a feature macro, or similar.
410 case I915_PARAM_HAS_CONTEXT_ISOLATION
:
411 value
= intel_engines_has_context_isolation(dev_priv
);
413 case I915_PARAM_SLICE_MASK
:
414 value
= INTEL_INFO(dev_priv
)->sseu
.slice_mask
;
418 case I915_PARAM_SUBSLICE_MASK
:
419 value
= INTEL_INFO(dev_priv
)->sseu
.subslice_mask
;
424 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
428 if (put_user(value
, param
->value
))
434 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
436 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
437 if (!dev_priv
->bridge_dev
) {
438 DRM_ERROR("bridge device not found\n");
444 /* Allocate space for the MCH regs if needed, return nonzero on error */
446 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
448 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
449 u32 temp_lo
, temp_hi
= 0;
453 if (INTEL_GEN(dev_priv
) >= 4)
454 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
455 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
456 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
458 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
461 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
465 /* Get some space for it */
466 dev_priv
->mch_res
.name
= "i915 MCHBAR";
467 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
468 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
470 MCHBAR_SIZE
, MCHBAR_SIZE
,
472 0, pcibios_align_resource
,
473 dev_priv
->bridge_dev
);
475 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
476 dev_priv
->mch_res
.start
= 0;
480 if (INTEL_GEN(dev_priv
) >= 4)
481 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
482 upper_32_bits(dev_priv
->mch_res
.start
));
484 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
485 lower_32_bits(dev_priv
->mch_res
.start
));
489 /* Setup MCHBAR if possible, return true if we should disable it again */
491 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
493 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
497 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
500 dev_priv
->mchbar_need_disable
= false;
502 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
503 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
504 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
506 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
510 /* If it's already enabled, don't have to do anything */
514 if (intel_alloc_mchbar_resource(dev_priv
))
517 dev_priv
->mchbar_need_disable
= true;
519 /* Space is allocated or reserved, so enable it. */
520 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
521 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
522 temp
| DEVEN_MCHBAR_EN
);
524 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
525 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
530 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
532 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
534 if (dev_priv
->mchbar_need_disable
) {
535 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
538 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
540 deven_val
&= ~DEVEN_MCHBAR_EN
;
541 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
546 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
549 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
554 if (dev_priv
->mch_res
.start
)
555 release_resource(&dev_priv
->mch_res
);
558 /* true = enable decode, false = disable decoder */
559 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
561 struct drm_i915_private
*dev_priv
= cookie
;
563 intel_modeset_vga_set_state(dev_priv
, state
);
565 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
566 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
568 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
571 static int i915_resume_switcheroo(struct drm_device
*dev
);
572 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
574 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
576 struct drm_device
*dev
= pci_get_drvdata(pdev
);
577 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
579 if (state
== VGA_SWITCHEROO_ON
) {
580 pr_info("switched on\n");
581 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
582 /* i915 resume handler doesn't set to D0 */
583 pci_set_power_state(pdev
, PCI_D0
);
584 i915_resume_switcheroo(dev
);
585 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
587 pr_info("switched off\n");
588 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
589 i915_suspend_switcheroo(dev
, pmm
);
590 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
594 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
596 struct drm_device
*dev
= pci_get_drvdata(pdev
);
599 * FIXME: open_count is protected by drm_global_mutex but that would lead to
600 * locking inversion with the driver load path. And the access here is
601 * completely racy anyway. So don't bother with locking for now.
603 return dev
->open_count
== 0;
606 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
607 .set_gpu_state
= i915_switcheroo_set_state
,
609 .can_switch
= i915_switcheroo_can_switch
,
612 static void i915_gem_fini(struct drm_i915_private
*dev_priv
)
614 /* Flush any outstanding unpin_work. */
615 i915_gem_drain_workqueue(dev_priv
);
617 mutex_lock(&dev_priv
->drm
.struct_mutex
);
618 intel_uc_fini_hw(dev_priv
);
619 i915_gem_cleanup_engines(dev_priv
);
620 i915_gem_contexts_fini(dev_priv
);
621 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
623 i915_gem_cleanup_userptr(dev_priv
);
625 i915_gem_drain_freed_objects(dev_priv
);
627 WARN_ON(!list_empty(&dev_priv
->contexts
.list
));
630 static int i915_load_modeset_init(struct drm_device
*dev
)
632 struct drm_i915_private
*dev_priv
= to_i915(dev
);
633 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
636 if (i915_inject_load_failure())
639 intel_bios_init(dev_priv
);
641 /* If we have > 1 VGA cards, then we need to arbitrate access
642 * to the common VGA resources.
644 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
645 * then we do not take part in VGA arbitration and the
646 * vga_client_register() fails with -ENODEV.
648 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
649 if (ret
&& ret
!= -ENODEV
)
652 intel_register_dsm_handler();
654 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
656 goto cleanup_vga_client
;
658 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
659 intel_update_rawclk(dev_priv
);
661 intel_power_domains_init_hw(dev_priv
, false);
663 intel_csr_ucode_init(dev_priv
);
665 ret
= intel_irq_install(dev_priv
);
669 intel_setup_gmbus(dev_priv
);
671 /* Important: The output setup functions called by modeset_init need
672 * working irqs for e.g. gmbus and dp aux transfers. */
673 ret
= intel_modeset_init(dev
);
677 intel_uc_init_fw(dev_priv
);
679 ret
= i915_gem_init(dev_priv
);
683 intel_setup_overlay(dev_priv
);
685 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
688 ret
= intel_fbdev_init(dev
);
692 /* Only enable hotplug handling once the fbdev is fully set up. */
693 intel_hpd_init(dev_priv
);
695 drm_kms_helper_poll_init(dev
);
700 if (i915_gem_suspend(dev_priv
))
701 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
702 i915_gem_fini(dev_priv
);
704 intel_uc_fini_fw(dev_priv
);
706 drm_irq_uninstall(dev
);
707 intel_teardown_gmbus(dev_priv
);
709 intel_csr_ucode_fini(dev_priv
);
710 intel_power_domains_fini(dev_priv
);
711 vga_switcheroo_unregister_client(pdev
);
713 vga_client_register(pdev
, NULL
, NULL
, NULL
);
718 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
720 struct apertures_struct
*ap
;
721 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
722 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
726 ap
= alloc_apertures(1);
730 ap
->ranges
[0].base
= ggtt
->gmadr
.start
;
731 ap
->ranges
[0].size
= ggtt
->mappable_end
;
734 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
736 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
743 #if !defined(CONFIG_VGA_CONSOLE)
744 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
748 #elif !defined(CONFIG_DUMMY_CONSOLE)
749 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
754 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
758 DRM_INFO("Replacing VGA console driver\n");
761 if (con_is_bound(&vga_con
))
762 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
764 ret
= do_unregister_con_driver(&vga_con
);
766 /* Ignore "already unregistered". */
776 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
779 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
780 * CHV x1 PHY (DP/HDMI D)
781 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
783 if (IS_CHERRYVIEW(dev_priv
)) {
784 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
785 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
786 } else if (IS_VALLEYVIEW(dev_priv
)) {
787 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
791 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
794 * The i915 workqueue is primarily used for batched retirement of
795 * requests (and thus managing bo) once the task has been completed
796 * by the GPU. i915_gem_retire_requests() is called directly when we
797 * need high-priority retirement, such as waiting for an explicit
800 * It is also used for periodic low-priority events, such as
801 * idle-timers and recording error state.
803 * All tasks on the workqueue are expected to acquire the dev mutex
804 * so there is no point in running more than one instance of the
805 * workqueue at any time. Use an ordered one.
807 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
808 if (dev_priv
->wq
== NULL
)
811 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
812 if (dev_priv
->hotplug
.dp_wq
== NULL
)
818 destroy_workqueue(dev_priv
->wq
);
820 DRM_ERROR("Failed to allocate workqueues.\n");
825 static void i915_engines_cleanup(struct drm_i915_private
*i915
)
827 struct intel_engine_cs
*engine
;
828 enum intel_engine_id id
;
830 for_each_engine(engine
, i915
, id
)
834 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
836 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
837 destroy_workqueue(dev_priv
->wq
);
841 * We don't keep the workarounds for pre-production hardware, so we expect our
842 * driver to fail on these machines in one way or another. A little warning on
843 * dmesg may help both the user and the bug triagers.
845 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
849 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
850 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
851 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
854 DRM_ERROR("This is a pre-production stepping. "
855 "It may not be fully functional.\n");
856 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
861 * i915_driver_init_early - setup state not requiring device access
862 * @dev_priv: device private
864 * Initialize everything that is a "SW-only" state, that is state not
865 * requiring accessing the device or exposing the driver via kernel internal
866 * or userspace interfaces. Example steps belonging here: lock initialization,
867 * system memory allocation, setting up device specific attributes and
868 * function hooks not requiring accessing the device.
870 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
871 const struct pci_device_id
*ent
)
873 const struct intel_device_info
*match_info
=
874 (struct intel_device_info
*)ent
->driver_data
;
875 struct intel_device_info
*device_info
;
878 if (i915_inject_load_failure())
881 /* Setup the write-once "constant" device info */
882 device_info
= mkwrite_device_info(dev_priv
);
883 memcpy(device_info
, match_info
, sizeof(*device_info
));
884 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
886 BUILD_BUG_ON(INTEL_MAX_PLATFORMS
>
887 sizeof(device_info
->platform_mask
) * BITS_PER_BYTE
);
888 device_info
->platform_mask
= BIT(device_info
->platform
);
890 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
891 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
893 spin_lock_init(&dev_priv
->irq_lock
);
894 spin_lock_init(&dev_priv
->gpu_error
.lock
);
895 mutex_init(&dev_priv
->backlight_lock
);
896 spin_lock_init(&dev_priv
->uncore
.lock
);
898 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
899 mutex_init(&dev_priv
->sb_lock
);
900 mutex_init(&dev_priv
->av_mutex
);
901 mutex_init(&dev_priv
->wm
.wm_mutex
);
902 mutex_init(&dev_priv
->pps_mutex
);
904 intel_uc_init_early(dev_priv
);
905 i915_memcpy_init_early(dev_priv
);
907 ret
= i915_workqueues_init(dev_priv
);
911 /* This must be called before any calls to HAS_PCH_* */
912 intel_detect_pch(dev_priv
);
914 intel_pm_setup(dev_priv
);
915 intel_init_dpio(dev_priv
);
916 intel_power_domains_init(dev_priv
);
917 intel_irq_init(dev_priv
);
918 intel_hangcheck_init(dev_priv
);
919 intel_init_display_hooks(dev_priv
);
920 intel_init_clock_gating_hooks(dev_priv
);
921 intel_init_audio_hooks(dev_priv
);
922 ret
= i915_gem_load_init(dev_priv
);
926 intel_display_crc_init(dev_priv
);
928 intel_device_info_dump(dev_priv
);
930 intel_detect_preproduction_hw(dev_priv
);
932 i915_perf_init(dev_priv
);
937 intel_irq_fini(dev_priv
);
938 i915_workqueues_cleanup(dev_priv
);
940 i915_engines_cleanup(dev_priv
);
945 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
946 * @dev_priv: device private
948 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
950 i915_perf_fini(dev_priv
);
951 i915_gem_load_cleanup(dev_priv
);
952 intel_irq_fini(dev_priv
);
953 i915_workqueues_cleanup(dev_priv
);
954 i915_engines_cleanup(dev_priv
);
957 static int i915_mmio_setup(struct drm_i915_private
*dev_priv
)
959 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
963 mmio_bar
= IS_GEN2(dev_priv
) ? 1 : 0;
965 * Before gen4, the registers and the GTT are behind different BARs.
966 * However, from gen4 onwards, the registers and the GTT are shared
967 * in the same BAR, so we want to restrict this ioremap from
968 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
969 * the register BAR remains the same size for all the earlier
970 * generations up to Ironlake.
972 if (INTEL_GEN(dev_priv
) < 5)
973 mmio_size
= 512 * 1024;
975 mmio_size
= 2 * 1024 * 1024;
976 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
977 if (dev_priv
->regs
== NULL
) {
978 DRM_ERROR("failed to map registers\n");
983 /* Try to make sure MCHBAR is enabled before poking at it */
984 intel_setup_mchbar(dev_priv
);
989 static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv
)
991 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
993 intel_teardown_mchbar(dev_priv
);
994 pci_iounmap(pdev
, dev_priv
->regs
);
998 * i915_driver_init_mmio - setup device MMIO
999 * @dev_priv: device private
1001 * Setup minimal device state necessary for MMIO accesses later in the
1002 * initialization sequence. The setup here should avoid any other device-wide
1003 * side effects or exposing the driver via kernel internal or user space
1006 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
1010 if (i915_inject_load_failure())
1013 if (i915_get_bridge_dev(dev_priv
))
1016 ret
= i915_mmio_setup(dev_priv
);
1020 intel_uncore_init(dev_priv
);
1022 intel_uc_init_mmio(dev_priv
);
1024 ret
= intel_engines_init_mmio(dev_priv
);
1028 i915_gem_init_mmio(dev_priv
);
1033 intel_uncore_fini(dev_priv
);
1035 pci_dev_put(dev_priv
->bridge_dev
);
1041 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1042 * @dev_priv: device private
1044 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
1046 intel_uncore_fini(dev_priv
);
1047 i915_mmio_cleanup(dev_priv
);
1048 pci_dev_put(dev_priv
->bridge_dev
);
1051 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
1053 i915_modparams
.enable_execlists
=
1054 intel_sanitize_enable_execlists(dev_priv
,
1055 i915_modparams
.enable_execlists
);
1058 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1059 * user's requested state against the hardware/driver capabilities. We
1060 * do this now so that we can print out any log messages once rather
1061 * than every time we check intel_enable_ppgtt().
1063 i915_modparams
.enable_ppgtt
=
1064 intel_sanitize_enable_ppgtt(dev_priv
,
1065 i915_modparams
.enable_ppgtt
);
1066 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams
.enable_ppgtt
);
1068 i915_modparams
.semaphores
=
1069 intel_sanitize_semaphores(dev_priv
, i915_modparams
.semaphores
);
1070 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1071 yesno(i915_modparams
.semaphores
));
1073 intel_uc_sanitize_options(dev_priv
);
1075 intel_gvt_sanitize_options(dev_priv
);
1079 * i915_driver_init_hw - setup state requiring device access
1080 * @dev_priv: device private
1082 * Setup state that requires accessing the device, but doesn't require
1083 * exposing the driver via kernel internal or userspace interfaces.
1085 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1087 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1090 if (i915_inject_load_failure())
1093 intel_device_info_runtime_init(dev_priv
);
1095 intel_sanitize_options(dev_priv
);
1097 ret
= i915_ggtt_probe_hw(dev_priv
);
1101 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1102 * otherwise the vga fbdev driver falls over. */
1103 ret
= i915_kick_out_firmware_fb(dev_priv
);
1105 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1109 ret
= i915_kick_out_vgacon(dev_priv
);
1111 DRM_ERROR("failed to remove conflicting VGA console\n");
1115 ret
= i915_ggtt_init_hw(dev_priv
);
1119 ret
= i915_ggtt_enable_hw(dev_priv
);
1121 DRM_ERROR("failed to enable GGTT\n");
1125 pci_set_master(pdev
);
1128 * We don't have a max segment size, so set it to the max so sg's
1129 * debugging layer doesn't complain
1131 dma_set_max_seg_size(&pdev
->dev
, UINT_MAX
);
1133 /* overlay on gen2 is broken and can't address above 1G */
1134 if (IS_GEN2(dev_priv
)) {
1135 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1137 DRM_ERROR("failed to set DMA mask\n");
1143 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1144 * using 32bit addressing, overwriting memory if HWS is located
1147 * The documentation also mentions an issue with undefined
1148 * behaviour if any general state is accessed within a page above 4GB,
1149 * which also needs to be handled carefully.
1151 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1152 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1155 DRM_ERROR("failed to set DMA mask\n");
1161 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1162 PM_QOS_DEFAULT_VALUE
);
1164 intel_uncore_sanitize(dev_priv
);
1166 intel_opregion_setup(dev_priv
);
1168 i915_gem_load_init_fences(dev_priv
);
1170 /* On the 945G/GM, the chipset reports the MSI capability on the
1171 * integrated graphics even though the support isn't actually there
1172 * according to the published specs. It doesn't appear to function
1173 * correctly in testing on 945G.
1174 * This may be a side effect of MSI having been made available for PEG
1175 * and the registers being closely associated.
1177 * According to chipset errata, on the 965GM, MSI interrupts may
1178 * be lost or delayed, and was defeatured. MSI interrupts seem to
1179 * get lost on g4x as well, and interrupt delivery seems to stay
1180 * properly dead afterwards. So we'll just disable them for all
1181 * pre-gen5 chipsets.
1183 if (INTEL_GEN(dev_priv
) >= 5) {
1184 if (pci_enable_msi(pdev
) < 0)
1185 DRM_DEBUG_DRIVER("can't enable MSI");
1188 ret
= intel_gvt_init(dev_priv
);
1195 i915_ggtt_cleanup_hw(dev_priv
);
1201 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1202 * @dev_priv: device private
1204 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1206 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1208 if (pdev
->msi_enabled
)
1209 pci_disable_msi(pdev
);
1211 pm_qos_remove_request(&dev_priv
->pm_qos
);
1212 i915_ggtt_cleanup_hw(dev_priv
);
1216 * i915_driver_register - register the driver with the rest of the system
1217 * @dev_priv: device private
1219 * Perform any steps necessary to make the driver available via kernel
1220 * internal or userspace interfaces.
1222 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1224 struct drm_device
*dev
= &dev_priv
->drm
;
1226 i915_gem_shrinker_init(dev_priv
);
1229 * Notify a valid surface after modesetting,
1230 * when running inside a VM.
1232 if (intel_vgpu_active(dev_priv
))
1233 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1235 /* Reveal our presence to userspace */
1236 if (drm_dev_register(dev
, 0) == 0) {
1237 i915_debugfs_register(dev_priv
);
1238 i915_guc_log_register(dev_priv
);
1239 i915_setup_sysfs(dev_priv
);
1241 /* Depends on sysfs having been initialized */
1242 i915_perf_register(dev_priv
);
1244 DRM_ERROR("Failed to register driver for userspace access!\n");
1246 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1247 /* Must be done after probing outputs */
1248 intel_opregion_register(dev_priv
);
1249 acpi_video_register();
1252 if (IS_GEN5(dev_priv
))
1253 intel_gpu_ips_init(dev_priv
);
1255 intel_audio_init(dev_priv
);
1258 * Some ports require correctly set-up hpd registers for detection to
1259 * work properly (leading to ghost connected connector status), e.g. VGA
1260 * on gm45. Hence we can only set up the initial fbdev config after hpd
1261 * irqs are fully enabled. We do it last so that the async config
1262 * cannot run before the connectors are registered.
1264 intel_fbdev_initial_config_async(dev
);
1268 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1269 * @dev_priv: device private
1271 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1273 intel_fbdev_unregister(dev_priv
);
1274 intel_audio_deinit(dev_priv
);
1276 intel_gpu_ips_teardown();
1277 acpi_video_unregister();
1278 intel_opregion_unregister(dev_priv
);
1280 i915_perf_unregister(dev_priv
);
1282 i915_teardown_sysfs(dev_priv
);
1283 i915_guc_log_unregister(dev_priv
);
1284 drm_dev_unregister(&dev_priv
->drm
);
1286 i915_gem_shrinker_cleanup(dev_priv
);
1290 * i915_driver_load - setup chip and create an initial config
1292 * @ent: matching PCI ID entry
1294 * The driver load routine has to do several things:
1295 * - drive output discovery via intel_modeset_init()
1296 * - initialize the memory manager
1297 * - allocate initial config memory
1298 * - setup the DRM framebuffer with the allocated memory
1300 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1302 const struct intel_device_info
*match_info
=
1303 (struct intel_device_info
*)ent
->driver_data
;
1304 struct drm_i915_private
*dev_priv
;
1307 /* Enable nuclear pageflip on ILK+ */
1308 if (!i915_modparams
.nuclear_pageflip
&& match_info
->gen
< 5)
1309 driver
.driver_features
&= ~DRIVER_ATOMIC
;
1312 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1314 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1316 DRM_DEV_ERROR(&pdev
->dev
, "allocation failed\n");
1320 dev_priv
->drm
.pdev
= pdev
;
1321 dev_priv
->drm
.dev_private
= dev_priv
;
1323 ret
= pci_enable_device(pdev
);
1327 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1329 * Disable the system suspend direct complete optimization, which can
1330 * leave the device suspended skipping the driver's suspend handlers
1331 * if the device was already runtime suspended. This is needed due to
1332 * the difference in our runtime and system suspend sequence and
1333 * becaue the HDA driver may require us to enable the audio power
1334 * domain during system suspend.
1336 dev_pm_set_driver_flags(&pdev
->dev
, DPM_FLAG_NEVER_SKIP
);
1338 ret
= i915_driver_init_early(dev_priv
, ent
);
1340 goto out_pci_disable
;
1342 intel_runtime_pm_get(dev_priv
);
1344 ret
= i915_driver_init_mmio(dev_priv
);
1346 goto out_runtime_pm_put
;
1348 ret
= i915_driver_init_hw(dev_priv
);
1350 goto out_cleanup_mmio
;
1353 * TODO: move the vblank init and parts of modeset init steps into one
1354 * of the i915_driver_init_/i915_driver_register functions according
1355 * to the role/effect of the given init step.
1357 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1358 ret
= drm_vblank_init(&dev_priv
->drm
,
1359 INTEL_INFO(dev_priv
)->num_pipes
);
1361 goto out_cleanup_hw
;
1364 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1366 goto out_cleanup_hw
;
1368 i915_driver_register(dev_priv
);
1370 intel_runtime_pm_enable(dev_priv
);
1372 intel_init_ipc(dev_priv
);
1374 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1375 DRM_INFO("DRM_I915_DEBUG enabled\n");
1376 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1377 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1379 intel_runtime_pm_put(dev_priv
);
1384 i915_driver_cleanup_hw(dev_priv
);
1386 i915_driver_cleanup_mmio(dev_priv
);
1388 intel_runtime_pm_put(dev_priv
);
1389 i915_driver_cleanup_early(dev_priv
);
1391 pci_disable_device(pdev
);
1393 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1394 drm_dev_fini(&dev_priv
->drm
);
1400 void i915_driver_unload(struct drm_device
*dev
)
1402 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1403 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1405 i915_driver_unregister(dev_priv
);
1407 if (i915_gem_suspend(dev_priv
))
1408 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1410 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1412 drm_atomic_helper_shutdown(dev
);
1414 intel_gvt_cleanup(dev_priv
);
1416 intel_modeset_cleanup(dev
);
1419 * free the memory space allocated for the child device
1420 * config parsed from VBT
1422 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1423 kfree(dev_priv
->vbt
.child_dev
);
1424 dev_priv
->vbt
.child_dev
= NULL
;
1425 dev_priv
->vbt
.child_dev_num
= 0;
1427 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1428 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1429 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1430 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1432 vga_switcheroo_unregister_client(pdev
);
1433 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1435 intel_csr_ucode_fini(dev_priv
);
1437 /* Free error state after interrupts are fully disabled. */
1438 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1439 i915_reset_error_state(dev_priv
);
1441 i915_gem_fini(dev_priv
);
1442 intel_uc_fini_fw(dev_priv
);
1443 intel_fbc_cleanup_cfb(dev_priv
);
1445 intel_power_domains_fini(dev_priv
);
1447 i915_driver_cleanup_hw(dev_priv
);
1448 i915_driver_cleanup_mmio(dev_priv
);
1450 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1453 static void i915_driver_release(struct drm_device
*dev
)
1455 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1457 i915_driver_cleanup_early(dev_priv
);
1458 drm_dev_fini(&dev_priv
->drm
);
1463 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1465 struct drm_i915_private
*i915
= to_i915(dev
);
1468 ret
= i915_gem_open(i915
, file
);
1476 * i915_driver_lastclose - clean up after all DRM clients have exited
1479 * Take care of cleaning up after all DRM clients have exited. In the
1480 * mode setting case, we want to restore the kernel's initial mode (just
1481 * in case the last client left us in a bad state).
1483 * Additionally, in the non-mode setting case, we'll tear down the GTT
1484 * and DMA structures, since the kernel won't be using them, and clea
1487 static void i915_driver_lastclose(struct drm_device
*dev
)
1489 intel_fbdev_restore_mode(dev
);
1490 vga_switcheroo_process_delayed_switch();
1493 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1495 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1497 mutex_lock(&dev
->struct_mutex
);
1498 i915_gem_context_close(file
);
1499 i915_gem_release(dev
, file
);
1500 mutex_unlock(&dev
->struct_mutex
);
1505 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1507 struct drm_device
*dev
= &dev_priv
->drm
;
1508 struct intel_encoder
*encoder
;
1510 drm_modeset_lock_all(dev
);
1511 for_each_intel_encoder(dev
, encoder
)
1512 if (encoder
->suspend
)
1513 encoder
->suspend(encoder
);
1514 drm_modeset_unlock_all(dev
);
1517 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1519 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1521 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1523 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1524 if (acpi_target_system_state() < ACPI_STATE_S3
)
1530 static int i915_drm_suspend(struct drm_device
*dev
)
1532 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1533 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1534 pci_power_t opregion_target_state
;
1537 disable_rpm_wakeref_asserts(dev_priv
);
1539 /* We do a lot of poking in a lot of registers, make sure they work
1541 intel_display_set_init_power(dev_priv
, true);
1543 drm_kms_helper_poll_disable(dev
);
1545 pci_save_state(pdev
);
1547 error
= i915_gem_suspend(dev_priv
);
1550 "GEM idle failed, resume might fail\n");
1554 intel_display_suspend(dev
);
1556 intel_dp_mst_suspend(dev
);
1558 intel_runtime_pm_disable_interrupts(dev_priv
);
1559 intel_hpd_cancel_work(dev_priv
);
1561 intel_suspend_encoders(dev_priv
);
1563 intel_suspend_hw(dev_priv
);
1565 i915_gem_suspend_gtt_mappings(dev_priv
);
1567 i915_save_state(dev_priv
);
1569 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1570 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1572 intel_uncore_suspend(dev_priv
);
1573 intel_opregion_unregister(dev_priv
);
1575 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1577 dev_priv
->suspend_count
++;
1579 intel_csr_ucode_suspend(dev_priv
);
1582 enable_rpm_wakeref_asserts(dev_priv
);
1587 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1589 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1590 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1593 disable_rpm_wakeref_asserts(dev_priv
);
1595 intel_display_set_init_power(dev_priv
, false);
1597 i915_rc6_ctx_wa_suspend(dev_priv
);
1600 * In case of firmware assisted context save/restore don't manually
1601 * deinit the power domains. This also means the CSR/DMC firmware will
1602 * stay active, it will power down any HW resources as required and
1603 * also enable deeper system power states that would be blocked if the
1604 * firmware was inactive.
1606 if (IS_GEN9_LP(dev_priv
) || hibernation
|| !suspend_to_idle(dev_priv
) ||
1607 dev_priv
->csr
.dmc_payload
== NULL
) {
1608 intel_power_domains_suspend(dev_priv
);
1609 dev_priv
->power_domains_suspended
= true;
1613 if (IS_GEN9_LP(dev_priv
))
1614 bxt_enable_dc9(dev_priv
);
1615 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1616 hsw_enable_pc8(dev_priv
);
1617 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1618 ret
= vlv_suspend_complete(dev_priv
);
1621 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1622 if (dev_priv
->power_domains_suspended
) {
1623 intel_power_domains_init_hw(dev_priv
, true);
1624 dev_priv
->power_domains_suspended
= false;
1630 pci_disable_device(pdev
);
1632 * During hibernation on some platforms the BIOS may try to access
1633 * the device even though it's already in D3 and hang the machine. So
1634 * leave the device in D0 on those platforms and hope the BIOS will
1635 * power down the device properly. The issue was seen on multiple old
1636 * GENs with different BIOS vendors, so having an explicit blacklist
1637 * is inpractical; apply the workaround on everything pre GEN6. The
1638 * platforms where the issue was seen:
1639 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1643 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1644 pci_set_power_state(pdev
, PCI_D3hot
);
1647 enable_rpm_wakeref_asserts(dev_priv
);
1652 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1657 DRM_ERROR("dev: %p\n", dev
);
1658 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1662 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1663 state
.event
!= PM_EVENT_FREEZE
))
1666 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1669 error
= i915_drm_suspend(dev
);
1673 return i915_drm_suspend_late(dev
, false);
1676 static int i915_drm_resume(struct drm_device
*dev
)
1678 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1681 disable_rpm_wakeref_asserts(dev_priv
);
1682 intel_sanitize_gt_powersave(dev_priv
);
1684 ret
= i915_ggtt_enable_hw(dev_priv
);
1686 DRM_ERROR("failed to re-enable GGTT\n");
1688 intel_csr_ucode_resume(dev_priv
);
1690 i915_gem_resume(dev_priv
);
1692 i915_restore_state(dev_priv
);
1693 intel_pps_unlock_regs_wa(dev_priv
);
1694 intel_opregion_setup(dev_priv
);
1696 intel_init_pch_refclk(dev_priv
);
1699 * Interrupts have to be enabled before any batches are run. If not the
1700 * GPU will hang. i915_gem_init_hw() will initiate batches to
1701 * update/restore the context.
1703 * drm_mode_config_reset() needs AUX interrupts.
1705 * Modeset enabling in intel_modeset_init_hw() also needs working
1708 intel_runtime_pm_enable_interrupts(dev_priv
);
1710 drm_mode_config_reset(dev
);
1712 mutex_lock(&dev
->struct_mutex
);
1713 if (i915_gem_init_hw(dev_priv
)) {
1714 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1715 i915_gem_set_wedged(dev_priv
);
1717 mutex_unlock(&dev
->struct_mutex
);
1719 intel_guc_resume(dev_priv
);
1721 intel_modeset_init_hw(dev
);
1722 intel_init_clock_gating(dev_priv
);
1724 spin_lock_irq(&dev_priv
->irq_lock
);
1725 if (dev_priv
->display
.hpd_irq_setup
)
1726 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1727 spin_unlock_irq(&dev_priv
->irq_lock
);
1729 intel_dp_mst_resume(dev
);
1731 intel_display_resume(dev
);
1733 drm_kms_helper_poll_enable(dev
);
1736 * ... but also need to make sure that hotplug processing
1737 * doesn't cause havoc. Like in the driver load code we don't
1738 * bother with the tiny race here where we might loose hotplug
1741 intel_hpd_init(dev_priv
);
1743 intel_opregion_register(dev_priv
);
1745 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1747 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1749 intel_autoenable_gt_powersave(dev_priv
);
1751 enable_rpm_wakeref_asserts(dev_priv
);
1756 static int i915_drm_resume_early(struct drm_device
*dev
)
1758 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1759 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1763 * We have a resume ordering issue with the snd-hda driver also
1764 * requiring our device to be power up. Due to the lack of a
1765 * parent/child relationship we currently solve this with an early
1768 * FIXME: This should be solved with a special hdmi sink device or
1769 * similar so that power domains can be employed.
1773 * Note that we need to set the power state explicitly, since we
1774 * powered off the device during freeze and the PCI core won't power
1775 * it back up for us during thaw. Powering off the device during
1776 * freeze is not a hard requirement though, and during the
1777 * suspend/resume phases the PCI core makes sure we get here with the
1778 * device powered on. So in case we change our freeze logic and keep
1779 * the device powered we can also remove the following set power state
1782 ret
= pci_set_power_state(pdev
, PCI_D0
);
1784 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1789 * Note that pci_enable_device() first enables any parent bridge
1790 * device and only then sets the power state for this device. The
1791 * bridge enabling is a nop though, since bridge devices are resumed
1792 * first. The order of enabling power and enabling the device is
1793 * imposed by the PCI core as described above, so here we preserve the
1794 * same order for the freeze/thaw phases.
1796 * TODO: eventually we should remove pci_disable_device() /
1797 * pci_enable_enable_device() from suspend/resume. Due to how they
1798 * depend on the device enable refcount we can't anyway depend on them
1799 * disabling/enabling the device.
1801 if (pci_enable_device(pdev
)) {
1806 pci_set_master(pdev
);
1808 disable_rpm_wakeref_asserts(dev_priv
);
1810 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1811 ret
= vlv_resume_prepare(dev_priv
, false);
1813 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1816 intel_uncore_resume_early(dev_priv
);
1818 if (IS_GEN9_LP(dev_priv
)) {
1819 gen9_sanitize_dc_state(dev_priv
);
1820 bxt_disable_dc9(dev_priv
);
1821 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1822 hsw_disable_pc8(dev_priv
);
1825 intel_uncore_sanitize(dev_priv
);
1827 if (dev_priv
->power_domains_suspended
)
1828 intel_power_domains_init_hw(dev_priv
, true);
1830 intel_display_set_init_power(dev_priv
, true);
1832 i915_gem_sanitize(dev_priv
);
1834 i915_rc6_ctx_wa_resume(dev_priv
);
1836 enable_rpm_wakeref_asserts(dev_priv
);
1839 dev_priv
->power_domains_suspended
= false;
1844 static int i915_resume_switcheroo(struct drm_device
*dev
)
1848 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1851 ret
= i915_drm_resume_early(dev
);
1855 return i915_drm_resume(dev
);
1859 * i915_reset - reset chip after a hang
1860 * @i915: #drm_i915_private to reset
1861 * @flags: Instructions
1863 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1866 * Caller must hold the struct_mutex.
1868 * Procedure is fairly simple:
1869 * - reset the chip using the reset reg
1870 * - re-init context state
1871 * - re-init hardware status page
1872 * - re-init ring buffer
1873 * - re-init interrupt state
1876 void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
)
1878 struct i915_gpu_error
*error
= &i915
->gpu_error
;
1881 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1882 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF
, &error
->flags
));
1884 if (!test_bit(I915_RESET_HANDOFF
, &error
->flags
))
1887 /* Clear any previous failed attempts at recovery. Time to try again. */
1888 if (!i915_gem_unset_wedged(i915
))
1891 if (!(flags
& I915_RESET_QUIET
))
1892 dev_notice(i915
->drm
.dev
, "Resetting chip after gpu hang\n");
1893 error
->reset_count
++;
1895 disable_irq(i915
->drm
.irq
);
1896 ret
= i915_gem_reset_prepare(i915
);
1898 DRM_ERROR("GPU recovery failed\n");
1899 intel_gpu_reset(i915
, ALL_ENGINES
);
1903 ret
= intel_gpu_reset(i915
, ALL_ENGINES
);
1906 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1908 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1912 i915_gem_reset(i915
);
1913 intel_overlay_reset(i915
);
1915 /* Ok, now get things going again... */
1918 * Everything depends on having the GTT running, so we need to start
1921 ret
= i915_ggtt_enable_hw(i915
);
1923 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret
);
1928 * Next we need to restore the context, but we don't use those
1931 * Ring buffer needs to be re-initialized in the KMS case, or if X
1932 * was running at the time of the reset (i.e. we weren't VT
1935 ret
= i915_gem_init_hw(i915
);
1937 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1941 i915_queue_hangcheck(i915
);
1944 i915_gem_reset_finish(i915
);
1945 enable_irq(i915
->drm
.irq
);
1948 clear_bit(I915_RESET_HANDOFF
, &error
->flags
);
1949 wake_up_bit(&error
->flags
, I915_RESET_HANDOFF
);
1953 i915_gem_set_wedged(i915
);
1954 i915_gem_retire_requests(i915
);
1959 * i915_reset_engine - reset GPU engine to recover from a hang
1960 * @engine: engine to reset
1963 * Reset a specific GPU engine. Useful if a hang is detected.
1964 * Returns zero on successful reset or otherwise an error code.
1967 * - identifies the request that caused the hang and it is dropped
1968 * - reset engine (which will force the engine to idle)
1969 * - re-init/configure engine
1971 int i915_reset_engine(struct intel_engine_cs
*engine
, unsigned int flags
)
1973 struct i915_gpu_error
*error
= &engine
->i915
->gpu_error
;
1974 struct drm_i915_gem_request
*active_request
;
1977 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE
+ engine
->id
, &error
->flags
));
1979 if (!(flags
& I915_RESET_QUIET
)) {
1980 dev_notice(engine
->i915
->drm
.dev
,
1981 "Resetting %s after gpu hang\n", engine
->name
);
1983 error
->reset_engine_count
[engine
->id
]++;
1985 active_request
= i915_gem_reset_prepare_engine(engine
);
1986 if (IS_ERR(active_request
)) {
1987 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1988 ret
= PTR_ERR(active_request
);
1992 ret
= intel_gpu_reset(engine
->i915
, intel_engine_flag(engine
));
1994 /* If we fail here, we expect to fallback to a global reset */
1995 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
2001 * The request that caused the hang is stuck on elsp, we know the
2002 * active request and can drop it, adjust head to skip the offending
2003 * request to resume executing remaining requests in the queue.
2005 i915_gem_reset_engine(engine
, active_request
);
2008 * The engine and its registers (and workarounds in case of render)
2009 * have been reset to their default values. Follow the init_ring
2010 * process to program RING_MODE, HWSP and re-enable submission.
2012 ret
= engine
->init_hw(engine
);
2017 i915_gem_reset_finish_engine(engine
);
2021 static int i915_pm_suspend(struct device
*kdev
)
2023 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2024 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2027 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
2031 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2034 return i915_drm_suspend(dev
);
2037 static int i915_pm_suspend_late(struct device
*kdev
)
2039 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2042 * We have a suspend ordering issue with the snd-hda driver also
2043 * requiring our device to be power up. Due to the lack of a
2044 * parent/child relationship we currently solve this with an late
2047 * FIXME: This should be solved with a special hdmi sink device or
2048 * similar so that power domains can be employed.
2050 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2053 return i915_drm_suspend_late(dev
, false);
2056 static int i915_pm_poweroff_late(struct device
*kdev
)
2058 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2060 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2063 return i915_drm_suspend_late(dev
, true);
2066 static int i915_pm_resume_early(struct device
*kdev
)
2068 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2070 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2073 return i915_drm_resume_early(dev
);
2076 static int i915_pm_resume(struct device
*kdev
)
2078 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2080 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2083 return i915_drm_resume(dev
);
2086 /* freeze: before creating the hibernation_image */
2087 static int i915_pm_freeze(struct device
*kdev
)
2089 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2092 if (dev
->switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2093 ret
= i915_drm_suspend(dev
);
2098 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
2105 static int i915_pm_freeze_late(struct device
*kdev
)
2107 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2110 if (dev
->switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2111 ret
= i915_drm_suspend_late(dev
, true);
2116 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
2123 /* thaw: called after creating the hibernation image, but before turning off. */
2124 static int i915_pm_thaw_early(struct device
*kdev
)
2126 return i915_pm_resume_early(kdev
);
2129 static int i915_pm_thaw(struct device
*kdev
)
2131 return i915_pm_resume(kdev
);
2134 /* restore: called after loading the hibernation image. */
2135 static int i915_pm_restore_early(struct device
*kdev
)
2137 return i915_pm_resume_early(kdev
);
2140 static int i915_pm_restore(struct device
*kdev
)
2142 return i915_pm_resume(kdev
);
2146 * Save all Gunit registers that may be lost after a D3 and a subsequent
2147 * S0i[R123] transition. The list of registers needing a save/restore is
2148 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2149 * registers in the following way:
2150 * - Driver: saved/restored by the driver
2151 * - Punit : saved/restored by the Punit firmware
2152 * - No, w/o marking: no need to save/restore, since the register is R/O or
2153 * used internally by the HW in a way that doesn't depend
2154 * keeping the content across a suspend/resume.
2155 * - Debug : used for debugging
2157 * We save/restore all registers marked with 'Driver', with the following
2159 * - Registers out of use, including also registers marked with 'Debug'.
2160 * These have no effect on the driver's operation, so we don't save/restore
2161 * them to reduce the overhead.
2162 * - Registers that are fully setup by an initialization function called from
2163 * the resume path. For example many clock gating and RPS/RC6 registers.
2164 * - Registers that provide the right functionality with their reset defaults.
2166 * TODO: Except for registers that based on the above 3 criteria can be safely
2167 * ignored, we save/restore all others, practically treating the HW context as
2168 * a black-box for the driver. Further investigation is needed to reduce the
2169 * saved/restored registers even further, by following the same 3 criteria.
2171 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2173 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2176 /* GAM 0x4000-0x4770 */
2177 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2178 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2179 s
->arb_mode
= I915_READ(ARB_MODE
);
2180 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2181 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2183 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2184 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2186 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2187 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2189 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2190 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2191 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2192 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2194 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2196 /* MBC 0x9024-0x91D0, 0x8500 */
2197 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2198 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2199 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2201 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2202 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2203 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2204 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2205 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2206 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2207 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2209 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2210 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2211 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2212 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2213 s
->ecobus
= I915_READ(ECOBUS
);
2214 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2215 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2216 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2217 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2218 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2219 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2221 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2222 s
->gt_imr
= I915_READ(GTIMR
);
2223 s
->gt_ier
= I915_READ(GTIER
);
2224 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2225 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2227 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2228 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2230 /* GT SA CZ domain, 0x100000-0x138124 */
2231 s
->tilectl
= I915_READ(TILECTL
);
2232 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2233 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2234 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2235 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2237 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2238 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2239 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2240 s
->pcbr
= I915_READ(VLV_PCBR
);
2241 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2244 * Not saving any of:
2245 * DFT, 0x9800-0x9EC0
2246 * SARB, 0xB000-0xB1FC
2247 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2252 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2254 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2258 /* GAM 0x4000-0x4770 */
2259 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2260 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2261 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2262 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2263 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2265 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2266 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2268 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2269 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2271 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2272 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2273 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2274 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2276 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2278 /* MBC 0x9024-0x91D0, 0x8500 */
2279 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2280 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2281 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2283 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2284 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2285 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2286 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2287 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2288 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2289 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2291 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2292 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2293 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2294 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2295 I915_WRITE(ECOBUS
, s
->ecobus
);
2296 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2297 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2298 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2299 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2300 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2301 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2303 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2304 I915_WRITE(GTIMR
, s
->gt_imr
);
2305 I915_WRITE(GTIER
, s
->gt_ier
);
2306 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2307 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2309 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2310 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2312 /* GT SA CZ domain, 0x100000-0x138124 */
2313 I915_WRITE(TILECTL
, s
->tilectl
);
2314 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2316 * Preserve the GT allow wake and GFX force clock bit, they are not
2317 * be restored, as they are used to control the s0ix suspend/resume
2318 * sequence by the caller.
2320 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2321 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2322 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2323 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2325 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2326 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2327 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2328 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2330 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2332 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2333 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2334 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2335 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2336 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2339 static int vlv_wait_for_pw_status(struct drm_i915_private
*dev_priv
,
2342 /* The HW does not like us polling for PW_STATUS frequently, so
2343 * use the sleeping loop rather than risk the busy spin within
2344 * intel_wait_for_register().
2346 * Transitioning between RC6 states should be at most 2ms (see
2347 * valleyview_enable_rps) so use a 3ms timeout.
2349 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS
) & mask
) == val
,
2353 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2358 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2359 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2361 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2362 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2367 err
= intel_wait_for_register(dev_priv
,
2368 VLV_GTLC_SURVIVABILITY_REG
,
2369 VLV_GFX_CLK_STATUS_BIT
,
2370 VLV_GFX_CLK_STATUS_BIT
,
2373 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2374 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2379 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2385 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2386 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2388 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2389 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2390 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2392 mask
= VLV_GTLC_ALLOWWAKEACK
;
2393 val
= allow
? mask
: 0;
2395 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2397 DRM_ERROR("timeout disabling GT waking\n");
2402 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2408 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2409 val
= wait_for_on
? mask
: 0;
2412 * RC6 transitioning can be delayed up to 2 msec (see
2413 * valleyview_enable_rps), use 3 msec for safety.
2415 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2416 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2417 onoff(wait_for_on
));
2420 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2422 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2425 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2426 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2429 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2435 * Bspec defines the following GT well on flags as debug only, so
2436 * don't treat them as hard failures.
2438 vlv_wait_for_gt_wells(dev_priv
, false);
2440 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2441 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2443 vlv_check_no_gt_access(dev_priv
);
2445 err
= vlv_force_gfx_clock(dev_priv
, true);
2449 err
= vlv_allow_gt_wake(dev_priv
, false);
2453 if (!IS_CHERRYVIEW(dev_priv
))
2454 vlv_save_gunit_s0ix_state(dev_priv
);
2456 err
= vlv_force_gfx_clock(dev_priv
, false);
2463 /* For safety always re-enable waking and disable gfx clock forcing */
2464 vlv_allow_gt_wake(dev_priv
, true);
2466 vlv_force_gfx_clock(dev_priv
, false);
2471 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2478 * If any of the steps fail just try to continue, that's the best we
2479 * can do at this point. Return the first error code (which will also
2480 * leave RPM permanently disabled).
2482 ret
= vlv_force_gfx_clock(dev_priv
, true);
2484 if (!IS_CHERRYVIEW(dev_priv
))
2485 vlv_restore_gunit_s0ix_state(dev_priv
);
2487 err
= vlv_allow_gt_wake(dev_priv
, true);
2491 err
= vlv_force_gfx_clock(dev_priv
, false);
2495 vlv_check_no_gt_access(dev_priv
);
2498 intel_init_clock_gating(dev_priv
);
2503 static int intel_runtime_suspend(struct device
*kdev
)
2505 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2506 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2507 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2510 if (WARN_ON_ONCE(!(dev_priv
->gt_pm
.rc6
.enabled
&& intel_rc6_enabled())))
2513 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2516 DRM_DEBUG_KMS("Suspending device\n");
2518 disable_rpm_wakeref_asserts(dev_priv
);
2521 * We are safe here against re-faults, since the fault handler takes
2524 i915_gem_runtime_suspend(dev_priv
);
2526 intel_guc_suspend(dev_priv
);
2528 intel_runtime_pm_disable_interrupts(dev_priv
);
2531 if (IS_GEN9_LP(dev_priv
)) {
2532 bxt_display_core_uninit(dev_priv
);
2533 bxt_enable_dc9(dev_priv
);
2534 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2535 hsw_enable_pc8(dev_priv
);
2536 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2537 ret
= vlv_suspend_complete(dev_priv
);
2541 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2542 intel_runtime_pm_enable_interrupts(dev_priv
);
2544 enable_rpm_wakeref_asserts(dev_priv
);
2549 intel_uncore_suspend(dev_priv
);
2551 enable_rpm_wakeref_asserts(dev_priv
);
2552 WARN_ON_ONCE(atomic_read(&dev_priv
->runtime_pm
.wakeref_count
));
2554 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2555 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2557 dev_priv
->runtime_pm
.suspended
= true;
2560 * FIXME: We really should find a document that references the arguments
2563 if (IS_BROADWELL(dev_priv
)) {
2565 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2566 * being detected, and the call we do at intel_runtime_resume()
2567 * won't be able to restore them. Since PCI_D3hot matches the
2568 * actual specification and appears to be working, use it.
2570 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2573 * current versions of firmware which depend on this opregion
2574 * notification have repurposed the D1 definition to mean
2575 * "runtime suspended" vs. what you would normally expect (D3)
2576 * to distinguish it from notifications that might be sent via
2579 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2582 assert_forcewakes_inactive(dev_priv
);
2584 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2585 intel_hpd_poll_init(dev_priv
);
2587 DRM_DEBUG_KMS("Device suspended\n");
2591 static int intel_runtime_resume(struct device
*kdev
)
2593 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2594 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2595 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2598 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2601 DRM_DEBUG_KMS("Resuming device\n");
2603 WARN_ON_ONCE(atomic_read(&dev_priv
->runtime_pm
.wakeref_count
));
2604 disable_rpm_wakeref_asserts(dev_priv
);
2606 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2607 dev_priv
->runtime_pm
.suspended
= false;
2608 if (intel_uncore_unclaimed_mmio(dev_priv
))
2609 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2611 intel_guc_resume(dev_priv
);
2613 if (IS_GEN9_LP(dev_priv
)) {
2614 bxt_disable_dc9(dev_priv
);
2615 bxt_display_core_init(dev_priv
, true);
2616 if (dev_priv
->csr
.dmc_payload
&&
2617 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2618 gen9_enable_dc5(dev_priv
);
2619 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2620 hsw_disable_pc8(dev_priv
);
2621 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2622 ret
= vlv_resume_prepare(dev_priv
, true);
2625 intel_uncore_runtime_resume(dev_priv
);
2628 * No point of rolling back things in case of an error, as the best
2629 * we can do is to hope that things will still work (and disable RPM).
2631 i915_gem_init_swizzling(dev_priv
);
2632 i915_gem_restore_fences(dev_priv
);
2634 intel_runtime_pm_enable_interrupts(dev_priv
);
2637 * On VLV/CHV display interrupts are part of the display
2638 * power well, so hpd is reinitialized from there. For
2639 * everyone else do it here.
2641 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2642 intel_hpd_init(dev_priv
);
2644 intel_enable_ipc(dev_priv
);
2646 enable_rpm_wakeref_asserts(dev_priv
);
2649 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2651 DRM_DEBUG_KMS("Device resumed\n");
2656 const struct dev_pm_ops i915_pm_ops
= {
2658 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2661 .suspend
= i915_pm_suspend
,
2662 .suspend_late
= i915_pm_suspend_late
,
2663 .resume_early
= i915_pm_resume_early
,
2664 .resume
= i915_pm_resume
,
2668 * @freeze, @freeze_late : called (1) before creating the
2669 * hibernation image [PMSG_FREEZE] and
2670 * (2) after rebooting, before restoring
2671 * the image [PMSG_QUIESCE]
2672 * @thaw, @thaw_early : called (1) after creating the hibernation
2673 * image, before writing it [PMSG_THAW]
2674 * and (2) after failing to create or
2675 * restore the image [PMSG_RECOVER]
2676 * @poweroff, @poweroff_late: called after writing the hibernation
2677 * image, before rebooting [PMSG_HIBERNATE]
2678 * @restore, @restore_early : called after rebooting and restoring the
2679 * hibernation image [PMSG_RESTORE]
2681 .freeze
= i915_pm_freeze
,
2682 .freeze_late
= i915_pm_freeze_late
,
2683 .thaw_early
= i915_pm_thaw_early
,
2684 .thaw
= i915_pm_thaw
,
2685 .poweroff
= i915_pm_suspend
,
2686 .poweroff_late
= i915_pm_poweroff_late
,
2687 .restore_early
= i915_pm_restore_early
,
2688 .restore
= i915_pm_restore
,
2690 /* S0ix (via runtime suspend) event handlers */
2691 .runtime_suspend
= intel_runtime_suspend
,
2692 .runtime_resume
= intel_runtime_resume
,
2695 static const struct vm_operations_struct i915_gem_vm_ops
= {
2696 .fault
= i915_gem_fault
,
2697 .open
= drm_gem_vm_open
,
2698 .close
= drm_gem_vm_close
,
2701 static const struct file_operations i915_driver_fops
= {
2702 .owner
= THIS_MODULE
,
2704 .release
= drm_release
,
2705 .unlocked_ioctl
= drm_ioctl
,
2706 .mmap
= drm_gem_mmap
,
2709 .compat_ioctl
= i915_compat_ioctl
,
2710 .llseek
= noop_llseek
,
2714 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2715 struct drm_file
*file
)
2720 static const struct drm_ioctl_desc i915_ioctls
[] = {
2721 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2722 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2723 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2724 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2725 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2726 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2727 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2728 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2729 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2730 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2731 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2732 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2733 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2734 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2735 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2736 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2737 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2738 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2739 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2740 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2741 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2742 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2743 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2744 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2745 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2746 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2747 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2748 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2749 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2750 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2751 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2752 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2753 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2754 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2755 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2756 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2757 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2758 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2759 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2760 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2761 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2762 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2763 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2764 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2765 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2766 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2767 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2768 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2769 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2770 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2771 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2772 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2773 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2774 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG
, i915_perf_add_config_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
2775 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG
, i915_perf_remove_config_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
2778 static struct drm_driver driver
= {
2779 /* Don't use MTRRs here; the Xserver or userspace app should
2780 * deal with them for Intel hardware.
2783 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2784 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
| DRIVER_SYNCOBJ
,
2785 .release
= i915_driver_release
,
2786 .open
= i915_driver_open
,
2787 .lastclose
= i915_driver_lastclose
,
2788 .postclose
= i915_driver_postclose
,
2790 .gem_close_object
= i915_gem_close_object
,
2791 .gem_free_object_unlocked
= i915_gem_free_object
,
2792 .gem_vm_ops
= &i915_gem_vm_ops
,
2794 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2795 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2796 .gem_prime_export
= i915_gem_prime_export
,
2797 .gem_prime_import
= i915_gem_prime_import
,
2799 .dumb_create
= i915_gem_dumb_create
,
2800 .dumb_map_offset
= i915_gem_mmap_gtt
,
2801 .ioctls
= i915_ioctls
,
2802 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2803 .fops
= &i915_driver_fops
,
2804 .name
= DRIVER_NAME
,
2805 .desc
= DRIVER_DESC
,
2806 .date
= DRIVER_DATE
,
2807 .major
= DRIVER_MAJOR
,
2808 .minor
= DRIVER_MINOR
,
2809 .patchlevel
= DRIVER_PATCHLEVEL
,
2812 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2813 #include "selftests/mock_drm.c"