1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20171023"
84 #define DRIVER_TIMESTAMP 1508748913
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915_modparams.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func
, int line
);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t
;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val
)
125 static inline uint_fixed_16_16_t
u32_to_fixed16(uint32_t val
)
127 uint_fixed_16_16_t fp
;
129 WARN_ON(val
> U16_MAX
);
135 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp
)
137 return DIV_ROUND_UP(fp
.val
, 1 << 16);
140 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp
)
145 static inline uint_fixed_16_16_t
min_fixed16(uint_fixed_16_16_t min1
,
146 uint_fixed_16_16_t min2
)
148 uint_fixed_16_16_t min
;
150 min
.val
= min(min1
.val
, min2
.val
);
154 static inline uint_fixed_16_16_t
max_fixed16(uint_fixed_16_16_t max1
,
155 uint_fixed_16_16_t max2
)
157 uint_fixed_16_16_t max
;
159 max
.val
= max(max1
.val
, max2
.val
);
163 static inline uint_fixed_16_16_t
clamp_u64_to_fixed16(uint64_t val
)
165 uint_fixed_16_16_t fp
;
166 WARN_ON(val
> U32_MAX
);
167 fp
.val
= (uint32_t) val
;
171 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val
,
172 uint_fixed_16_16_t d
)
174 return DIV_ROUND_UP(val
.val
, d
.val
);
177 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val
,
178 uint_fixed_16_16_t mul
)
180 uint64_t intermediate_val
;
182 intermediate_val
= (uint64_t) val
* mul
.val
;
183 intermediate_val
= DIV_ROUND_UP_ULL(intermediate_val
, 1 << 16);
184 WARN_ON(intermediate_val
> U32_MAX
);
185 return (uint32_t) intermediate_val
;
188 static inline uint_fixed_16_16_t
mul_fixed16(uint_fixed_16_16_t val
,
189 uint_fixed_16_16_t mul
)
191 uint64_t intermediate_val
;
193 intermediate_val
= (uint64_t) val
.val
* mul
.val
;
194 intermediate_val
= intermediate_val
>> 16;
195 return clamp_u64_to_fixed16(intermediate_val
);
198 static inline uint_fixed_16_16_t
div_fixed16(uint32_t val
, uint32_t d
)
202 interm_val
= (uint64_t)val
<< 16;
203 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
204 return clamp_u64_to_fixed16(interm_val
);
207 static inline uint32_t div_round_up_u32_fixed16(uint32_t val
,
208 uint_fixed_16_16_t d
)
212 interm_val
= (uint64_t)val
<< 16;
213 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
.val
);
214 WARN_ON(interm_val
> U32_MAX
);
215 return (uint32_t) interm_val
;
218 static inline uint_fixed_16_16_t
mul_u32_fixed16(uint32_t val
,
219 uint_fixed_16_16_t mul
)
221 uint64_t intermediate_val
;
223 intermediate_val
= (uint64_t) val
* mul
.val
;
224 return clamp_u64_to_fixed16(intermediate_val
);
227 static inline uint_fixed_16_16_t
add_fixed16(uint_fixed_16_16_t add1
,
228 uint_fixed_16_16_t add2
)
232 interm_sum
= (uint64_t) add1
.val
+ add2
.val
;
233 return clamp_u64_to_fixed16(interm_sum
);
236 static inline uint_fixed_16_16_t
add_fixed16_u32(uint_fixed_16_16_t add1
,
240 uint_fixed_16_16_t interm_add2
= u32_to_fixed16(add2
);
242 interm_sum
= (uint64_t) add1
.val
+ interm_add2
.val
;
243 return clamp_u64_to_fixed16(interm_sum
);
246 static inline const char *yesno(bool v
)
248 return v
? "yes" : "no";
251 static inline const char *onoff(bool v
)
253 return v
? "on" : "off";
256 static inline const char *enableddisabled(bool v
)
258 return v
? "enabled" : "disabled";
267 I915_MAX_PIPES
= _PIPE_EDP
269 #define pipe_name(p) ((p) + 'A')
281 static inline const char *transcoder_name(enum transcoder transcoder
)
283 switch (transcoder
) {
292 case TRANSCODER_DSI_A
:
294 case TRANSCODER_DSI_C
:
301 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
303 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
307 * Global legacy plane identifier. Valid only for primary/sprite
308 * planes on pre-g4x, and only for primary planes on g4x+.
315 #define plane_name(p) ((p) + 'A')
317 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
320 * Per-pipe plane identifier.
321 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
322 * number of planes per CRTC. Not all platforms really have this many planes,
323 * which means some arrays of size I915_MAX_PLANES may have unused entries
324 * between the topmost sprite plane and the cursor plane.
326 * This is expected to be passed to various register macros
327 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
338 #define for_each_plane_id_on_crtc(__crtc, __p) \
339 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
340 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
351 #define port_name(p) ((p) + 'A')
353 #define I915_NUM_PHYS_VLV 2
366 enum intel_display_power_domain
{
370 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
371 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
372 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
373 POWER_DOMAIN_TRANSCODER_A
,
374 POWER_DOMAIN_TRANSCODER_B
,
375 POWER_DOMAIN_TRANSCODER_C
,
376 POWER_DOMAIN_TRANSCODER_EDP
,
377 POWER_DOMAIN_TRANSCODER_DSI_A
,
378 POWER_DOMAIN_TRANSCODER_DSI_C
,
379 POWER_DOMAIN_PORT_DDI_A_LANES
,
380 POWER_DOMAIN_PORT_DDI_B_LANES
,
381 POWER_DOMAIN_PORT_DDI_C_LANES
,
382 POWER_DOMAIN_PORT_DDI_D_LANES
,
383 POWER_DOMAIN_PORT_DDI_E_LANES
,
384 POWER_DOMAIN_PORT_DDI_A_IO
,
385 POWER_DOMAIN_PORT_DDI_B_IO
,
386 POWER_DOMAIN_PORT_DDI_C_IO
,
387 POWER_DOMAIN_PORT_DDI_D_IO
,
388 POWER_DOMAIN_PORT_DDI_E_IO
,
389 POWER_DOMAIN_PORT_DSI
,
390 POWER_DOMAIN_PORT_CRT
,
391 POWER_DOMAIN_PORT_OTHER
,
400 POWER_DOMAIN_MODESET
,
406 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
407 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
408 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
409 #define POWER_DOMAIN_TRANSCODER(tran) \
410 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
411 (tran) + POWER_DOMAIN_TRANSCODER_A)
415 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
427 #define for_each_hpd_pin(__pin) \
428 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
430 #define HPD_STORM_DEFAULT_THRESHOLD 5
432 struct i915_hotplug
{
433 struct work_struct hotplug_work
;
436 unsigned long last_jiffies
;
441 HPD_MARK_DISABLED
= 2
443 } stats
[HPD_NUM_PINS
];
445 struct delayed_work reenable_work
;
447 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
450 struct work_struct dig_port_work
;
452 struct work_struct poll_init_work
;
455 unsigned int hpd_storm_threshold
;
458 * if we get a HPD irq from DP and a HPD irq from non-DP
459 * the non-DP HPD could block the workqueue on a mode config
460 * mutex getting, that userspace may have taken. However
461 * userspace is waiting on the DP workqueue to run which is
462 * blocked behind the non-DP one.
464 struct workqueue_struct
*dp_wq
;
467 #define I915_GEM_GPU_DOMAINS \
468 (I915_GEM_DOMAIN_RENDER | \
469 I915_GEM_DOMAIN_SAMPLER | \
470 I915_GEM_DOMAIN_COMMAND | \
471 I915_GEM_DOMAIN_INSTRUCTION | \
472 I915_GEM_DOMAIN_VERTEX)
474 #define for_each_pipe(__dev_priv, __p) \
475 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
476 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
477 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
478 for_each_if ((__mask) & (1 << (__p)))
479 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
481 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
483 #define for_each_sprite(__dev_priv, __p, __s) \
485 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
488 #define for_each_port_masked(__port, __ports_mask) \
489 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
490 for_each_if ((__ports_mask) & (1 << (__port)))
492 #define for_each_crtc(dev, crtc) \
493 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
495 #define for_each_intel_plane(dev, intel_plane) \
496 list_for_each_entry(intel_plane, \
497 &(dev)->mode_config.plane_list, \
500 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
501 list_for_each_entry(intel_plane, \
502 &(dev)->mode_config.plane_list, \
504 for_each_if ((plane_mask) & \
505 (1 << drm_plane_index(&intel_plane->base)))
507 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
508 list_for_each_entry(intel_plane, \
509 &(dev)->mode_config.plane_list, \
511 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
513 #define for_each_intel_crtc(dev, intel_crtc) \
514 list_for_each_entry(intel_crtc, \
515 &(dev)->mode_config.crtc_list, \
518 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
519 list_for_each_entry(intel_crtc, \
520 &(dev)->mode_config.crtc_list, \
522 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
524 #define for_each_intel_encoder(dev, intel_encoder) \
525 list_for_each_entry(intel_encoder, \
526 &(dev)->mode_config.encoder_list, \
529 #define for_each_intel_connector_iter(intel_connector, iter) \
530 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
532 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
533 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
534 for_each_if ((intel_encoder)->base.crtc == (__crtc))
536 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
537 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
538 for_each_if ((intel_connector)->base.encoder == (__encoder))
540 #define for_each_power_domain(domain, mask) \
541 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
542 for_each_if (BIT_ULL(domain) & (mask))
544 #define for_each_power_well(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
546 (__power_well) - (__dev_priv)->power_domains.power_wells < \
547 (__dev_priv)->power_domains.power_well_count; \
550 #define for_each_power_well_rev(__dev_priv, __power_well) \
551 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
552 (__dev_priv)->power_domains.power_well_count - 1; \
553 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
556 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
557 for_each_power_well(__dev_priv, __power_well) \
558 for_each_if ((__power_well)->domains & (__domain_mask))
560 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
561 for_each_power_well_rev(__dev_priv, __power_well) \
562 for_each_if ((__power_well)->domains & (__domain_mask))
564 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
566 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
567 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
568 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
570 for_each_if (plane_state)
572 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
574 (__i) < (__state)->base.dev->mode_config.num_crtc && \
575 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
576 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
581 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
583 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
584 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
585 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
586 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
590 struct drm_i915_private
;
591 struct i915_mm_struct
;
592 struct i915_mmu_object
;
594 struct drm_i915_file_private
{
595 struct drm_i915_private
*dev_priv
;
596 struct drm_file
*file
;
600 struct list_head request_list
;
601 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
602 * chosen to prevent the CPU getting more than a frame ahead of the GPU
603 * (when using lax throttling for the frontbuffer). We also use it to
604 * offer free GPU waitboosts for severely congested workloads.
606 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
608 struct idr context_idr
;
610 struct intel_rps_client
{
614 unsigned int bsd_engine
;
616 /* Client can have a maximum of 3 contexts banned before
617 * it is denied of creating new contexts. As one context
618 * ban needs 4 consecutive hangs, and more if there is
619 * progress in between, this is a last resort stop gap measure
620 * to limit the badly behaving clients access to gpu.
622 #define I915_MAX_CLIENT_CONTEXT_BANS 3
623 atomic_t context_bans
;
626 /* Used by dp and fdi links */
627 struct intel_link_m_n
{
635 void intel_link_compute_m_n(int bpp
, int nlanes
,
636 int pixel_clock
, int link_clock
,
637 struct intel_link_m_n
*m_n
,
640 /* Interface history:
643 * 1.2: Add Power Management
644 * 1.3: Add vblank support
645 * 1.4: Fix cmdbuffer path, add heap destroy
646 * 1.5: Add vblank pipe configuration
647 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
648 * - Support vertical blank on secondary display pipe
650 #define DRIVER_MAJOR 1
651 #define DRIVER_MINOR 6
652 #define DRIVER_PATCHLEVEL 0
654 struct opregion_header
;
655 struct opregion_acpi
;
656 struct opregion_swsci
;
657 struct opregion_asle
;
659 struct intel_opregion
{
660 struct opregion_header
*header
;
661 struct opregion_acpi
*acpi
;
662 struct opregion_swsci
*swsci
;
663 u32 swsci_gbda_sub_functions
;
664 u32 swsci_sbcb_sub_functions
;
665 struct opregion_asle
*asle
;
671 struct work_struct asle_work
;
673 #define OPREGION_SIZE (8*1024)
675 struct intel_overlay
;
676 struct intel_overlay_error_state
;
678 struct sdvo_device_mapping
{
687 struct intel_connector
;
688 struct intel_encoder
;
689 struct intel_atomic_state
;
690 struct intel_crtc_state
;
691 struct intel_initial_plane_config
;
695 struct intel_cdclk_state
;
697 struct drm_i915_display_funcs
{
698 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
699 struct intel_cdclk_state
*cdclk_state
);
700 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
701 const struct intel_cdclk_state
*cdclk_state
);
702 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
703 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
704 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
705 struct intel_crtc
*intel_crtc
,
706 struct intel_crtc_state
*newstate
);
707 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
708 struct intel_crtc_state
*cstate
);
709 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
710 struct intel_crtc_state
*cstate
);
711 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
712 struct intel_crtc_state
*cstate
);
713 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
714 void (*update_wm
)(struct intel_crtc
*crtc
);
715 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
716 /* Returns the active state of the crtc, and if the crtc is active,
717 * fills out the pipe-config with the hw state. */
718 bool (*get_pipe_config
)(struct intel_crtc
*,
719 struct intel_crtc_state
*);
720 void (*get_initial_plane_config
)(struct intel_crtc
*,
721 struct intel_initial_plane_config
*);
722 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
723 struct intel_crtc_state
*crtc_state
);
724 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
725 struct drm_atomic_state
*old_state
);
726 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
727 struct drm_atomic_state
*old_state
);
728 void (*update_crtcs
)(struct drm_atomic_state
*state
);
729 void (*audio_codec_enable
)(struct drm_connector
*connector
,
730 struct intel_encoder
*encoder
,
731 const struct drm_display_mode
*adjusted_mode
);
732 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
733 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
734 const struct intel_crtc_state
*crtc_state
);
735 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
736 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
737 /* clock updates for mode set */
739 /* render clock increase/decrease */
740 /* display clock increase/decrease */
741 /* pll clock increase/decrease */
743 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
744 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
747 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
748 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
749 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
752 struct work_struct work
;
754 uint32_t *dmc_payload
;
755 uint32_t dmc_fw_size
;
758 i915_reg_t mmioaddr
[8];
759 uint32_t mmiodata
[8];
761 uint32_t allowed_dc_mask
;
764 #define DEV_INFO_FOR_EACH_FLAG(func) \
767 func(is_alpha_support); \
768 /* Keep has_* in alphabetical order */ \
769 func(has_64bit_reloc); \
770 func(has_aliasing_ppgtt); \
774 func(has_reset_engine); \
776 func(has_fpga_dbg); \
777 func(has_full_ppgtt); \
778 func(has_full_48bit_ppgtt); \
779 func(has_gmch_display); \
785 func(has_logical_ring_contexts); \
786 func(has_logical_ring_preemption); \
788 func(has_pooled_eu); \
792 func(has_resource_streamer); \
793 func(has_runtime_pm); \
795 func(unfenced_needs_alignment); \
796 func(cursor_needs_physical); \
797 func(hws_needs_physical); \
798 func(overlay_needs_physical); \
802 struct sseu_dev_info
{
808 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
811 u8 has_subslice_pg
:1;
815 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
817 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
820 /* Keep in gen based order, and chronological order within a gen */
821 enum intel_platform
{
822 INTEL_PLATFORM_UNINITIALIZED
= 0,
853 struct intel_device_info
{
858 u8 gt
; /* GT number, 0 if undefined */
860 u8 ring_mask
; /* Rings supported by the HW */
862 enum intel_platform platform
;
865 u32 display_mmio_offset
;
868 u8 num_sprites
[I915_MAX_PIPES
];
869 u8 num_scalers
[I915_MAX_PIPES
];
871 unsigned int page_sizes
; /* page sizes supported by the HW */
873 #define DEFINE_FLAG(name) u8 name:1
874 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
876 u16 ddb_size
; /* in blocks */
878 /* Register offsets for the various display pipes and transcoders */
879 int pipe_offsets
[I915_MAX_TRANSCODERS
];
880 int trans_offsets
[I915_MAX_TRANSCODERS
];
881 int palette_offsets
[I915_MAX_PIPES
];
882 int cursor_offsets
[I915_MAX_PIPES
];
884 /* Slice/subslice/EU info */
885 struct sseu_dev_info sseu
;
888 u16 degamma_lut_size
;
893 struct intel_display_error_state
;
895 struct i915_gpu_state
{
898 struct timeval boottime
;
899 struct timeval uptime
;
901 struct drm_i915_private
*i915
;
911 struct intel_device_info device_info
;
912 struct i915_params params
;
914 /* Generic register state */
918 u32 gtier
[4], ngtier
;
922 u32 error
; /* gen6+ */
923 u32 err_int
; /* gen7 */
924 u32 fault_data0
; /* gen8, gen9 */
925 u32 fault_data1
; /* gen8, gen9 */
933 u64 fence
[I915_MAX_NUM_FENCES
];
934 struct intel_overlay_error_state
*overlay
;
935 struct intel_display_error_state
*display
;
936 struct drm_i915_error_object
*semaphore
;
937 struct drm_i915_error_object
*guc_log
;
939 struct drm_i915_error_engine
{
941 /* Software tracked state */
944 unsigned long hangcheck_timestamp
;
945 bool hangcheck_stalled
;
946 enum intel_engine_hangcheck_action hangcheck_action
;
947 struct i915_address_space
*vm
;
951 /* position of active request inside the ring */
952 u32 rq_head
, rq_post
, rq_tail
;
954 /* our own tracking of ring head and tail */
977 u32 rc_psmi
; /* sleep state */
978 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
979 struct intel_instdone instdone
;
981 struct drm_i915_error_context
{
982 char comm
[TASK_COMM_LEN
];
992 struct drm_i915_error_object
{
998 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
1000 struct drm_i915_error_object
**user_bo
;
1003 struct drm_i915_error_object
*wa_ctx
;
1005 struct drm_i915_error_request
{
1014 } *requests
, execlist
[EXECLIST_MAX_PORTS
];
1015 unsigned int num_ports
;
1017 struct drm_i915_error_waiter
{
1018 char comm
[TASK_COMM_LEN
];
1030 } engine
[I915_NUM_ENGINES
];
1032 struct drm_i915_error_buffer
{
1035 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1039 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1046 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1047 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1048 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1051 enum i915_cache_level
{
1052 I915_CACHE_NONE
= 0,
1053 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1054 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1055 caches, eg sampler/render caches, and the
1056 large Last-Level-Cache. LLC is coherent with
1057 the CPU, but L3 is only visible to the GPU. */
1058 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1061 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1072 /* This is always the inner lock when overlapping with struct_mutex and
1073 * it's the outer lock when overlapping with stolen_lock. */
1076 unsigned int possible_framebuffer_bits
;
1077 unsigned int busy_bits
;
1078 unsigned int visible_pipes_mask
;
1079 struct intel_crtc
*crtc
;
1081 struct drm_mm_node compressed_fb
;
1082 struct drm_mm_node
*compressed_llb
;
1089 bool underrun_detected
;
1090 struct work_struct underrun_work
;
1093 * Due to the atomic rules we can't access some structures without the
1094 * appropriate locking, so we cache information here in order to avoid
1097 struct intel_fbc_state_cache
{
1098 struct i915_vma
*vma
;
1101 unsigned int mode_flags
;
1102 uint32_t hsw_bdw_pixel_rate
;
1106 unsigned int rotation
;
1111 * Display surface base address adjustement for
1112 * pageflips. Note that on gen4+ this only adjusts up
1113 * to a tile, offsets within a tile are handled in
1114 * the hw itself (with the TILEOFF register).
1123 const struct drm_format_info
*format
;
1124 unsigned int stride
;
1129 * This structure contains everything that's relevant to program the
1130 * hardware registers. When we want to figure out if we need to disable
1131 * and re-enable FBC for a new configuration we just check if there's
1132 * something different in the struct. The genx_fbc_activate functions
1133 * are supposed to read from it in order to program the registers.
1135 struct intel_fbc_reg_params
{
1136 struct i915_vma
*vma
;
1141 unsigned int fence_y_offset
;
1145 const struct drm_format_info
*format
;
1146 unsigned int stride
;
1150 unsigned int gen9_wa_cfb_stride
;
1153 struct intel_fbc_work
{
1155 u32 scheduled_vblank
;
1156 struct work_struct work
;
1159 const char *no_fbc_reason
;
1163 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1164 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1165 * parsing for same resolution.
1167 enum drrs_refresh_rate_type
{
1170 DRRS_MAX_RR
, /* RR count */
1173 enum drrs_support_type
{
1174 DRRS_NOT_SUPPORTED
= 0,
1175 STATIC_DRRS_SUPPORT
= 1,
1176 SEAMLESS_DRRS_SUPPORT
= 2
1182 struct delayed_work work
;
1183 struct intel_dp
*dp
;
1184 unsigned busy_frontbuffer_bits
;
1185 enum drrs_refresh_rate_type refresh_rate_type
;
1186 enum drrs_support_type type
;
1193 struct intel_dp
*enabled
;
1195 struct delayed_work work
;
1196 unsigned busy_frontbuffer_bits
;
1198 bool aux_frame_sync
;
1200 bool y_cord_support
;
1201 bool colorimetry_support
;
1204 void (*enable_source
)(struct intel_dp
*,
1205 const struct intel_crtc_state
*);
1206 void (*disable_source
)(struct intel_dp
*,
1207 const struct intel_crtc_state
*);
1208 void (*enable_sink
)(struct intel_dp
*);
1209 void (*activate
)(struct intel_dp
*);
1210 void (*setup_vsc
)(struct intel_dp
*, const struct intel_crtc_state
*);
1214 PCH_NONE
= 0, /* No PCH present */
1215 PCH_IBX
, /* Ibexpeak PCH */
1216 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
1217 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
1218 PCH_SPT
, /* Sunrisepoint PCH */
1219 PCH_KBP
, /* Kaby Lake PCH */
1220 PCH_CNP
, /* Cannon Lake PCH */
1224 enum intel_sbi_destination
{
1229 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1230 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1231 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1232 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1233 #define QUIRK_INCREASE_T12_DELAY (1<<6)
1236 struct intel_fbc_work
;
1238 struct intel_gmbus
{
1239 struct i2c_adapter adapter
;
1240 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1243 i915_reg_t gpio_reg
;
1244 struct i2c_algo_bit_data bit_algo
;
1245 struct drm_i915_private
*dev_priv
;
1248 struct i915_suspend_saved_registers
{
1250 u32 saveFBC_CONTROL
;
1251 u32 saveCACHE_MODE_0
;
1252 u32 saveMI_ARB_STATE
;
1256 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1257 u32 savePCH_PORT_HOTPLUG
;
1261 struct vlv_s0ix_state
{
1268 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1269 u32 media_max_req_count
;
1270 u32 gfx_max_req_count
;
1296 u32 rp_down_timeout
;
1302 /* Display 1 CZ domain */
1307 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1309 /* GT SA CZ domain */
1316 /* Display 2 CZ domain */
1320 u32 clock_gate_dis2
;
1323 struct intel_rps_ei
{
1331 * work, interrupts_enabled and pm_iir are protected by
1332 * dev_priv->irq_lock
1334 struct work_struct work
;
1335 bool interrupts_enabled
;
1338 /* PM interrupt bits that should never be masked */
1341 /* Frequencies are stored in potentially platform dependent multiples.
1342 * In other words, *_freq needs to be multiplied by X to be interesting.
1343 * Soft limits are those which are used for the dynamic reclocking done
1344 * by the driver (raise frequencies under heavy loads, and lower for
1345 * lighter loads). Hard limits are those imposed by the hardware.
1347 * A distinction is made for overclocking, which is never enabled by
1348 * default, and is considered to be above the hard limit if it's
1351 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1352 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1353 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1354 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1355 u8 min_freq
; /* AKA RPn. Minimum frequency */
1356 u8 boost_freq
; /* Frequency to request when wait boosting */
1357 u8 idle_freq
; /* Frequency to request when we are idle */
1358 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1359 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1360 u8 rp0_freq
; /* Non-overclocked max frequency. */
1361 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1363 u8 up_threshold
; /* Current %busy required to uplock */
1364 u8 down_threshold
; /* Current %busy required to downclock */
1367 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1370 atomic_t num_waiters
;
1373 /* manual wa residency calculations */
1374 struct intel_rps_ei ei
;
1381 struct intel_llc_pstate
{
1385 struct intel_gen6_power_mgmt
{
1386 struct intel_rps rps
;
1387 struct intel_rc6 rc6
;
1388 struct intel_llc_pstate llc_pstate
;
1389 struct delayed_work autoenable_work
;
1392 /* defined intel_pm.c */
1393 extern spinlock_t mchdev_lock
;
1395 struct intel_ilk_power_mgmt
{
1403 unsigned long last_time1
;
1404 unsigned long chipset_power
;
1407 unsigned long gfx_power
;
1414 struct drm_i915_private
;
1415 struct i915_power_well
;
1417 struct i915_power_well_ops
{
1419 * Synchronize the well's hw state to match the current sw state, for
1420 * example enable/disable it based on the current refcount. Called
1421 * during driver init and resume time, possibly after first calling
1422 * the enable/disable handlers.
1424 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1425 struct i915_power_well
*power_well
);
1427 * Enable the well and resources that depend on it (for example
1428 * interrupts located on the well). Called after the 0->1 refcount
1431 void (*enable
)(struct drm_i915_private
*dev_priv
,
1432 struct i915_power_well
*power_well
);
1434 * Disable the well and resources that depend on it. Called after
1435 * the 1->0 refcount transition.
1437 void (*disable
)(struct drm_i915_private
*dev_priv
,
1438 struct i915_power_well
*power_well
);
1439 /* Returns the hw enabled state. */
1440 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1441 struct i915_power_well
*power_well
);
1444 /* Power well structure for haswell */
1445 struct i915_power_well
{
1448 /* power well enable/disable usage count */
1450 /* cached hw enabled state */
1453 /* unique identifier for this power well */
1454 enum i915_power_well_id id
;
1456 * Arbitraty data associated with this power well. Platform and power
1464 /* Mask of pipes whose IRQ logic is backed by the pw */
1466 /* The pw is backing the VGA functionality */
1471 const struct i915_power_well_ops
*ops
;
1474 struct i915_power_domains
{
1476 * Power wells needed for initialization at driver init and suspend
1477 * time are on. They are kept on until after the first modeset.
1481 int power_well_count
;
1484 int domain_use_count
[POWER_DOMAIN_NUM
];
1485 struct i915_power_well
*power_wells
;
1488 #define MAX_L3_SLICES 2
1489 struct intel_l3_parity
{
1490 u32
*remap_info
[MAX_L3_SLICES
];
1491 struct work_struct error_work
;
1495 struct i915_gem_mm
{
1496 /** Memory allocator for GTT stolen memory */
1497 struct drm_mm stolen
;
1498 /** Protects the usage of the GTT stolen memory allocator. This is
1499 * always the inner lock when overlapping with struct_mutex. */
1500 struct mutex stolen_lock
;
1502 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
1503 spinlock_t obj_lock
;
1505 /** List of all objects in gtt_space. Used to restore gtt
1506 * mappings on resume */
1507 struct list_head bound_list
;
1509 * List of objects which are not bound to the GTT (thus
1510 * are idle and not used by the GPU). These objects may or may
1511 * not actually have any pages attached.
1513 struct list_head unbound_list
;
1515 /** List of all objects in gtt_space, currently mmaped by userspace.
1516 * All objects within this list must also be on bound_list.
1518 struct list_head userfault_list
;
1521 * List of objects which are pending destruction.
1523 struct llist_head free_list
;
1524 struct work_struct free_work
;
1525 spinlock_t free_lock
;
1528 * Small stash of WC pages
1530 struct pagevec wc_stash
;
1532 /** Usable portion of the GTT for GEM */
1533 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1536 * tmpfs instance used for shmem backed objects
1538 struct vfsmount
*gemfs
;
1540 /** PPGTT used for aliasing the PPGTT with the GTT */
1541 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1543 struct notifier_block oom_notifier
;
1544 struct notifier_block vmap_notifier
;
1545 struct shrinker shrinker
;
1547 /** LRU list of objects with fence regs on them. */
1548 struct list_head fence_list
;
1551 * Workqueue to fault in userptr pages, flushed by the execbuf
1552 * when required but otherwise left to userspace to try again
1555 struct workqueue_struct
*userptr_wq
;
1557 u64 unordered_timeline
;
1559 /* the indicator for dispatch video commands on two BSD rings */
1560 atomic_t bsd_engine_dispatch_index
;
1562 /** Bit 6 swizzling required for X tiling */
1563 uint32_t bit_6_swizzle_x
;
1564 /** Bit 6 swizzling required for Y tiling */
1565 uint32_t bit_6_swizzle_y
;
1567 /* accounting, useful for userland debugging */
1568 spinlock_t object_stat_lock
;
1573 struct drm_i915_error_state_buf
{
1574 struct drm_i915_private
*i915
;
1583 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1584 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1586 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1587 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1589 struct i915_gpu_error
{
1590 /* For hangcheck timer */
1591 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1592 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1594 struct delayed_work hangcheck_work
;
1596 /* For reset and error_state handling. */
1598 /* Protected by the above dev->gpu_error.lock. */
1599 struct i915_gpu_state
*first_error
;
1601 atomic_t pending_fb_pin
;
1603 unsigned long missed_irq_rings
;
1606 * State variable controlling the reset flow and count
1608 * This is a counter which gets incremented when reset is triggered,
1610 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1611 * meaning that any waiters holding onto the struct_mutex should
1612 * relinquish the lock immediately in order for the reset to start.
1614 * If reset is not completed succesfully, the I915_WEDGE bit is
1615 * set meaning that hardware is terminally sour and there is no
1616 * recovery. All waiters on the reset_queue will be woken when
1619 * This counter is used by the wait_seqno code to notice that reset
1620 * event happened and it needs to restart the entire ioctl (since most
1621 * likely the seqno it waited for won't ever signal anytime soon).
1623 * This is important for lock-free wait paths, where no contended lock
1624 * naturally enforces the correct ordering between the bail-out of the
1625 * waiter and the gpu reset work code.
1627 unsigned long reset_count
;
1630 * flags: Control various stages of the GPU reset
1632 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1633 * other users acquiring the struct_mutex. To do this we set the
1634 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1635 * and then check for that bit before acquiring the struct_mutex (in
1636 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1637 * secondary role in preventing two concurrent global reset attempts.
1639 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1640 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1641 * but it may be held by some long running waiter (that we cannot
1642 * interrupt without causing trouble). Once we are ready to do the GPU
1643 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1644 * they already hold the struct_mutex and want to participate they can
1645 * inspect the bit and do the reset directly, otherwise the worker
1646 * waits for the struct_mutex.
1648 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1649 * acquire the struct_mutex to reset an engine, we need an explicit
1650 * flag to prevent two concurrent reset attempts in the same engine.
1651 * As the number of engines continues to grow, allocate the flags from
1652 * the most significant bits.
1654 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1655 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1656 * i915_gem_request_alloc(), this bit is checked and the sequence
1657 * aborted (with -EIO reported to userspace) if set.
1659 unsigned long flags
;
1660 #define I915_RESET_BACKOFF 0
1661 #define I915_RESET_HANDOFF 1
1662 #define I915_RESET_MODESET 2
1663 #define I915_WEDGED (BITS_PER_LONG - 1)
1664 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1666 /** Number of times an engine has been reset */
1667 u32 reset_engine_count
[I915_NUM_ENGINES
];
1670 * Waitqueue to signal when a hang is detected. Used to for waiters
1671 * to release the struct_mutex for the reset to procede.
1673 wait_queue_head_t wait_queue
;
1676 * Waitqueue to signal when the reset has completed. Used by clients
1677 * that wait for dev_priv->mm.wedged to settle.
1679 wait_queue_head_t reset_queue
;
1681 /* For missed irq/seqno simulation. */
1682 unsigned long test_irq_rings
;
1685 enum modeset_restore
{
1686 MODESET_ON_LID_OPEN
,
1691 #define DP_AUX_A 0x40
1692 #define DP_AUX_B 0x10
1693 #define DP_AUX_C 0x20
1694 #define DP_AUX_D 0x30
1696 #define DDC_PIN_B 0x05
1697 #define DDC_PIN_C 0x04
1698 #define DDC_PIN_D 0x06
1700 struct ddi_vbt_port_info
{
1702 * This is an index in the HDMI/DVI DDI buffer translation table.
1703 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1704 * populate this field.
1706 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1707 uint8_t hdmi_level_shift
;
1709 uint8_t supports_dvi
:1;
1710 uint8_t supports_hdmi
:1;
1711 uint8_t supports_dp
:1;
1712 uint8_t supports_edp
:1;
1714 uint8_t alternate_aux_channel
;
1715 uint8_t alternate_ddc_pin
;
1717 uint8_t dp_boost_level
;
1718 uint8_t hdmi_boost_level
;
1721 enum psr_lines_to_wait
{
1722 PSR_0_LINES_TO_WAIT
= 0,
1724 PSR_4_LINES_TO_WAIT
,
1728 struct intel_vbt_data
{
1729 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1730 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1733 unsigned int int_tv_support
:1;
1734 unsigned int lvds_dither
:1;
1735 unsigned int lvds_vbt
:1;
1736 unsigned int int_crt_support
:1;
1737 unsigned int lvds_use_ssc
:1;
1738 unsigned int display_clock_mode
:1;
1739 unsigned int fdi_rx_polarity_inverted
:1;
1740 unsigned int panel_type
:4;
1742 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1744 enum drrs_support_type drrs_type
;
1755 struct edp_power_seq pps
;
1760 bool require_aux_wakeup
;
1762 enum psr_lines_to_wait lines_to_wait
;
1763 int tp1_wakeup_time
;
1764 int tp2_tp3_wakeup_time
;
1770 bool active_low_pwm
;
1771 u8 min_brightness
; /* min_brightness/255 of max */
1772 u8 controller
; /* brightness controller number */
1773 enum intel_backlight_type type
;
1779 struct mipi_config
*config
;
1780 struct mipi_pps_data
*pps
;
1786 const u8
*sequence
[MIPI_SEQ_MAX
];
1792 struct child_device_config
*child_dev
;
1794 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1795 struct sdvo_device_mapping sdvo_mappings
[2];
1798 enum intel_ddb_partitioning
{
1800 INTEL_DDB_PART_5_6
, /* IVB+ */
1803 struct intel_wm_level
{
1811 struct ilk_wm_values
{
1812 uint32_t wm_pipe
[3];
1814 uint32_t wm_lp_spr
[3];
1815 uint32_t wm_linetime
[3];
1817 enum intel_ddb_partitioning partitioning
;
1820 struct g4x_pipe_wm
{
1821 uint16_t plane
[I915_MAX_PLANES
];
1831 struct vlv_wm_ddl_values
{
1832 uint8_t plane
[I915_MAX_PLANES
];
1835 struct vlv_wm_values
{
1836 struct g4x_pipe_wm pipe
[3];
1837 struct g4x_sr_wm sr
;
1838 struct vlv_wm_ddl_values ddl
[3];
1843 struct g4x_wm_values
{
1844 struct g4x_pipe_wm pipe
[2];
1845 struct g4x_sr_wm sr
;
1846 struct g4x_sr_wm hpll
;
1852 struct skl_ddb_entry
{
1853 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1856 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1858 return entry
->end
- entry
->start
;
1861 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1862 const struct skl_ddb_entry
*e2
)
1864 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1870 struct skl_ddb_allocation
{
1871 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1872 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1875 struct skl_wm_values
{
1876 unsigned dirty_pipes
;
1877 struct skl_ddb_allocation ddb
;
1880 struct skl_wm_level
{
1882 uint16_t plane_res_b
;
1883 uint8_t plane_res_l
;
1886 /* Stores plane specific WM parameters */
1887 struct skl_wm_params
{
1888 bool x_tiled
, y_tiled
;
1892 uint32_t plane_pixel_rate
;
1893 uint32_t y_min_scanlines
;
1894 uint32_t plane_bytes_per_line
;
1895 uint_fixed_16_16_t plane_blocks_per_line
;
1896 uint_fixed_16_16_t y_tile_minimum
;
1897 uint32_t linetime_us
;
1901 * This struct helps tracking the state needed for runtime PM, which puts the
1902 * device in PCI D3 state. Notice that when this happens, nothing on the
1903 * graphics device works, even register access, so we don't get interrupts nor
1906 * Every piece of our code that needs to actually touch the hardware needs to
1907 * either call intel_runtime_pm_get or call intel_display_power_get with the
1908 * appropriate power domain.
1910 * Our driver uses the autosuspend delay feature, which means we'll only really
1911 * suspend if we stay with zero refcount for a certain amount of time. The
1912 * default value is currently very conservative (see intel_runtime_pm_enable), but
1913 * it can be changed with the standard runtime PM files from sysfs.
1915 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1916 * goes back to false exactly before we reenable the IRQs. We use this variable
1917 * to check if someone is trying to enable/disable IRQs while they're supposed
1918 * to be disabled. This shouldn't happen and we'll print some error messages in
1921 * For more, read the Documentation/power/runtime_pm.txt.
1923 struct i915_runtime_pm
{
1924 atomic_t wakeref_count
;
1929 enum intel_pipe_crc_source
{
1930 INTEL_PIPE_CRC_SOURCE_NONE
,
1931 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1932 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1933 INTEL_PIPE_CRC_SOURCE_PF
,
1934 INTEL_PIPE_CRC_SOURCE_PIPE
,
1935 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1936 INTEL_PIPE_CRC_SOURCE_TV
,
1937 INTEL_PIPE_CRC_SOURCE_DP_B
,
1938 INTEL_PIPE_CRC_SOURCE_DP_C
,
1939 INTEL_PIPE_CRC_SOURCE_DP_D
,
1940 INTEL_PIPE_CRC_SOURCE_AUTO
,
1941 INTEL_PIPE_CRC_SOURCE_MAX
,
1944 struct intel_pipe_crc_entry
{
1949 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1950 struct intel_pipe_crc
{
1952 bool opened
; /* exclusive access to the result file */
1953 struct intel_pipe_crc_entry
*entries
;
1954 enum intel_pipe_crc_source source
;
1956 wait_queue_head_t wq
;
1960 struct i915_frontbuffer_tracking
{
1964 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1971 struct i915_wa_reg
{
1974 /* bitmask representing WA bits */
1978 #define I915_MAX_WA_REGS 16
1980 struct i915_workarounds
{
1981 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1983 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1986 struct i915_virtual_gpu
{
1991 /* used in computing the new watermarks state */
1992 struct intel_wm_config
{
1993 unsigned int num_pipes_active
;
1994 bool sprites_enabled
;
1995 bool sprites_scaled
;
1998 struct i915_oa_format
{
2003 struct i915_oa_reg
{
2008 struct i915_oa_config
{
2009 char uuid
[UUID_STRING_LEN
+ 1];
2012 const struct i915_oa_reg
*mux_regs
;
2014 const struct i915_oa_reg
*b_counter_regs
;
2015 u32 b_counter_regs_len
;
2016 const struct i915_oa_reg
*flex_regs
;
2019 struct attribute_group sysfs_metric
;
2020 struct attribute
*attrs
[2];
2021 struct device_attribute sysfs_metric_id
;
2026 struct i915_perf_stream
;
2029 * struct i915_perf_stream_ops - the OPs to support a specific stream type
2031 struct i915_perf_stream_ops
{
2033 * @enable: Enables the collection of HW samples, either in response to
2034 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
2035 * without `I915_PERF_FLAG_DISABLED`.
2037 void (*enable
)(struct i915_perf_stream
*stream
);
2040 * @disable: Disables the collection of HW samples, either in response
2041 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
2044 void (*disable
)(struct i915_perf_stream
*stream
);
2047 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
2048 * once there is something ready to read() for the stream
2050 void (*poll_wait
)(struct i915_perf_stream
*stream
,
2055 * @wait_unlocked: For handling a blocking read, wait until there is
2056 * something to ready to read() for the stream. E.g. wait on the same
2057 * wait queue that would be passed to poll_wait().
2059 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
2062 * @read: Copy buffered metrics as records to userspace
2063 * **buf**: the userspace, destination buffer
2064 * **count**: the number of bytes to copy, requested by userspace
2065 * **offset**: zero at the start of the read, updated as the read
2066 * proceeds, it represents how many bytes have been copied so far and
2067 * the buffer offset for copying the next record.
2069 * Copy as many buffered i915 perf samples and records for this stream
2070 * to userspace as will fit in the given buffer.
2072 * Only write complete records; returning -%ENOSPC if there isn't room
2073 * for a complete record.
2075 * Return any error condition that results in a short read such as
2076 * -%ENOSPC or -%EFAULT, even though these may be squashed before
2077 * returning to userspace.
2079 int (*read
)(struct i915_perf_stream
*stream
,
2085 * @destroy: Cleanup any stream specific resources.
2087 * The stream will always be disabled before this is called.
2089 void (*destroy
)(struct i915_perf_stream
*stream
);
2093 * struct i915_perf_stream - state for a single open stream FD
2095 struct i915_perf_stream
{
2097 * @dev_priv: i915 drm device
2099 struct drm_i915_private
*dev_priv
;
2102 * @link: Links the stream into ``&drm_i915_private->streams``
2104 struct list_head link
;
2107 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2108 * properties given when opening a stream, representing the contents
2109 * of a single sample as read() by userspace.
2114 * @sample_size: Considering the configured contents of a sample
2115 * combined with the required header size, this is the total size
2116 * of a single sample record.
2121 * @ctx: %NULL if measuring system-wide across all contexts or a
2122 * specific context that is being monitored.
2124 struct i915_gem_context
*ctx
;
2127 * @enabled: Whether the stream is currently enabled, considering
2128 * whether the stream was opened in a disabled state and based
2129 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2134 * @ops: The callbacks providing the implementation of this specific
2135 * type of configured stream.
2137 const struct i915_perf_stream_ops
*ops
;
2140 * @oa_config: The OA configuration used by the stream.
2142 struct i915_oa_config
*oa_config
;
2146 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2148 struct i915_oa_ops
{
2150 * @is_valid_b_counter_reg: Validates register's address for
2151 * programming boolean counters for a particular platform.
2153 bool (*is_valid_b_counter_reg
)(struct drm_i915_private
*dev_priv
,
2157 * @is_valid_mux_reg: Validates register's address for programming mux
2158 * for a particular platform.
2160 bool (*is_valid_mux_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2163 * @is_valid_flex_reg: Validates register's address for programming
2164 * flex EU filtering for a particular platform.
2166 bool (*is_valid_flex_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2169 * @init_oa_buffer: Resets the head and tail pointers of the
2170 * circular buffer for periodic OA reports.
2172 * Called when first opening a stream for OA metrics, but also may be
2173 * called in response to an OA buffer overflow or other error
2176 * Note it may be necessary to clear the full OA buffer here as part of
2177 * maintaining the invariable that new reports must be written to
2178 * zeroed memory for us to be able to reliable detect if an expected
2179 * report has not yet landed in memory. (At least on Haswell the OA
2180 * buffer tail pointer is not synchronized with reports being visible
2183 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2186 * @enable_metric_set: Selects and applies any MUX configuration to set
2187 * up the Boolean and Custom (B/C) counters that are part of the
2188 * counter reports being sampled. May apply system constraints such as
2189 * disabling EU clock gating as required.
2191 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
,
2192 const struct i915_oa_config
*oa_config
);
2195 * @disable_metric_set: Remove system constraints associated with using
2198 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2201 * @oa_enable: Enable periodic sampling
2203 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2206 * @oa_disable: Disable periodic sampling
2208 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2211 * @read: Copy data from the circular OA buffer into a given userspace
2214 int (*read
)(struct i915_perf_stream
*stream
,
2220 * @oa_hw_tail_read: read the OA tail pointer register
2222 * In particular this enables us to share all the fiddly code for
2223 * handling the OA unit tail pointer race that affects multiple
2226 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
2229 struct intel_cdclk_state
{
2230 unsigned int cdclk
, vco
, ref
;
2233 struct drm_i915_private
{
2234 struct drm_device drm
;
2236 struct kmem_cache
*objects
;
2237 struct kmem_cache
*vmas
;
2238 struct kmem_cache
*luts
;
2239 struct kmem_cache
*requests
;
2240 struct kmem_cache
*dependencies
;
2241 struct kmem_cache
*priorities
;
2243 const struct intel_device_info info
;
2247 struct intel_uncore uncore
;
2249 struct i915_virtual_gpu vgpu
;
2251 struct intel_gvt
*gvt
;
2253 struct intel_huc huc
;
2254 struct intel_guc guc
;
2256 struct intel_csr csr
;
2258 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2260 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2261 * controller on different i2c buses. */
2262 struct mutex gmbus_mutex
;
2265 * Base address of the gmbus and gpio block.
2267 uint32_t gpio_mmio_base
;
2269 /* MMIO base address for MIPI regs */
2270 uint32_t mipi_mmio_base
;
2272 uint32_t psr_mmio_base
;
2274 uint32_t pps_mmio_base
;
2276 wait_queue_head_t gmbus_wait_queue
;
2278 struct pci_dev
*bridge_dev
;
2279 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2280 /* Context used internally to idle the GPU and setup initial state */
2281 struct i915_gem_context
*kernel_context
;
2282 /* Context only to be used for injecting preemption commands */
2283 struct i915_gem_context
*preempt_context
;
2284 struct i915_vma
*semaphore
;
2286 struct drm_dma_handle
*status_page_dmah
;
2287 struct resource mch_res
;
2289 /* protects the irq masks */
2290 spinlock_t irq_lock
;
2292 bool display_irqs_enabled
;
2294 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2295 struct pm_qos_request pm_qos
;
2297 /* Sideband mailbox protection */
2298 struct mutex sb_lock
;
2300 /** Cached value of IMR to avoid reads in updating the bitfield */
2303 u32 de_irq_mask
[I915_MAX_PIPES
];
2310 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2312 struct i915_hotplug hotplug
;
2313 struct intel_fbc fbc
;
2314 struct i915_drrs drrs
;
2315 struct intel_opregion opregion
;
2316 struct intel_vbt_data vbt
;
2318 bool preserve_bios_swizzle
;
2321 struct intel_overlay
*overlay
;
2323 /* backlight registers and fields in struct intel_panel */
2324 struct mutex backlight_lock
;
2327 bool no_aux_handshake
;
2329 /* protects panel power sequencer state */
2330 struct mutex pps_mutex
;
2332 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2333 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2335 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2336 unsigned int skl_preferred_vco_freq
;
2337 unsigned int max_cdclk_freq
;
2339 unsigned int max_dotclk_freq
;
2340 unsigned int rawclk_freq
;
2341 unsigned int hpll_freq
;
2342 unsigned int czclk_freq
;
2346 * The current logical cdclk state.
2347 * See intel_atomic_state.cdclk.logical
2349 * For reading holding any crtc lock is sufficient,
2350 * for writing must hold all of them.
2352 struct intel_cdclk_state logical
;
2354 * The current actual cdclk state.
2355 * See intel_atomic_state.cdclk.actual
2357 struct intel_cdclk_state actual
;
2358 /* The current hardware cdclk state */
2359 struct intel_cdclk_state hw
;
2363 * wq - Driver workqueue for GEM.
2365 * NOTE: Work items scheduled here are not allowed to grab any modeset
2366 * locks, for otherwise the flushing done in the pageflip code will
2367 * result in deadlocks.
2369 struct workqueue_struct
*wq
;
2371 /* Display functions */
2372 struct drm_i915_display_funcs display
;
2374 /* PCH chipset type */
2375 enum intel_pch pch_type
;
2376 unsigned short pch_id
;
2378 unsigned long quirks
;
2380 enum modeset_restore modeset_restore
;
2381 struct mutex modeset_restore_lock
;
2382 struct drm_atomic_state
*modeset_restore_state
;
2383 struct drm_modeset_acquire_ctx reset_ctx
;
2385 struct list_head vm_list
; /* Global list of all address spaces */
2386 struct i915_ggtt ggtt
; /* VM representing the global address space */
2388 struct i915_gem_mm mm
;
2389 DECLARE_HASHTABLE(mm_structs
, 7);
2390 struct mutex mm_lock
;
2392 struct intel_ppat ppat
;
2394 /* Kernel Modesetting */
2396 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2397 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2399 #ifdef CONFIG_DEBUG_FS
2400 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2403 /* dpll and cdclk state is protected by connection_mutex */
2404 int num_shared_dpll
;
2405 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2406 const struct intel_dpll_mgr
*dpll_mgr
;
2409 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2410 * Must be global rather than per dpll, because on some platforms
2411 * plls share registers.
2413 struct mutex dpll_lock
;
2415 unsigned int active_crtcs
;
2416 /* minimum acceptable cdclk for each pipe */
2417 int min_cdclk
[I915_MAX_PIPES
];
2419 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2421 struct i915_workarounds workarounds
;
2423 struct i915_frontbuffer_tracking fb_tracking
;
2425 struct intel_atomic_helper
{
2426 struct llist_head free_list
;
2427 struct work_struct free_work
;
2432 bool mchbar_need_disable
;
2434 struct intel_l3_parity l3_parity
;
2436 /* Cannot be determined by PCIID. You must always read a register. */
2440 * Protects RPS/RC6 register access and PCU communication.
2441 * Must be taken after struct_mutex if nested. Note that
2442 * this lock may be held for long periods of time when
2443 * talking to hw - so only take it when talking to hw!
2445 struct mutex pcu_lock
;
2447 /* gen6+ GT PM state */
2448 struct intel_gen6_power_mgmt gt_pm
;
2450 /* ilk-only ips/rps state. Everything in here is protected by the global
2451 * mchdev_lock in intel_pm.c */
2452 struct intel_ilk_power_mgmt ips
;
2454 struct i915_power_domains power_domains
;
2456 struct i915_psr psr
;
2458 struct i915_gpu_error gpu_error
;
2460 struct drm_i915_gem_object
*vlv_pctx
;
2462 /* list of fbdev register on this device */
2463 struct intel_fbdev
*fbdev
;
2464 struct work_struct fbdev_suspend_work
;
2466 struct drm_property
*broadcast_rgb_property
;
2467 struct drm_property
*force_audio_property
;
2469 /* hda/i915 audio component */
2470 struct i915_audio_component
*audio_component
;
2471 bool audio_component_registered
;
2473 * av_mutex - mutex for audio/video sync
2476 struct mutex av_mutex
;
2479 struct list_head list
;
2480 struct llist_head free_list
;
2481 struct work_struct free_work
;
2483 /* The hw wants to have a stable context identifier for the
2484 * lifetime of the context (for OA, PASID, faults, etc).
2485 * This is limited in execlists to 21 bits.
2488 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2493 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2494 u32 chv_phy_control
;
2496 * Shadows for CHV DPLL_MD regs to keep the state
2497 * checker somewhat working in the presence hardware
2498 * crappiness (can't read out DPLL_MD for pipes B & C).
2500 u32 chv_dpll_md
[I915_MAX_PIPES
];
2504 bool suspended_to_idle
;
2505 struct i915_suspend_saved_registers regfile
;
2506 struct vlv_s0ix_state vlv_s0ix_state
;
2509 I915_SAGV_UNKNOWN
= 0,
2512 I915_SAGV_NOT_CONTROLLED
2517 * Raw watermark latency values:
2518 * in 0.1us units for WM0,
2519 * in 0.5us units for WM1+.
2522 uint16_t pri_latency
[5];
2524 uint16_t spr_latency
[5];
2526 uint16_t cur_latency
[5];
2528 * Raw watermark memory latency values
2529 * for SKL for all 8 levels
2532 uint16_t skl_latency
[8];
2534 /* current hardware state */
2536 struct ilk_wm_values hw
;
2537 struct skl_wm_values skl_hw
;
2538 struct vlv_wm_values vlv
;
2539 struct g4x_wm_values g4x
;
2545 * Should be held around atomic WM register writing; also
2546 * protects * intel_crtc->wm.active and
2547 * cstate->wm.need_postvbl_update.
2549 struct mutex wm_mutex
;
2552 * Set during HW readout of watermarks/DDB. Some platforms
2553 * need to know when we're still using BIOS-provided values
2554 * (which we don't fully trust).
2556 bool distrust_bios_wm
;
2559 struct i915_runtime_pm runtime_pm
;
2564 struct kobject
*metrics_kobj
;
2565 struct ctl_table_header
*sysctl_header
;
2568 * Lock associated with adding/modifying/removing OA configs
2569 * in dev_priv->perf.metrics_idr.
2571 struct mutex metrics_lock
;
2574 * List of dynamic configurations, you need to hold
2575 * dev_priv->perf.metrics_lock to access it.
2577 struct idr metrics_idr
;
2580 * Lock associated with anything below within this structure
2581 * except exclusive_stream.
2584 struct list_head streams
;
2588 * The stream currently using the OA unit. If accessed
2589 * outside a syscall associated to its file
2590 * descriptor, you need to hold
2591 * dev_priv->drm.struct_mutex.
2593 struct i915_perf_stream
*exclusive_stream
;
2595 u32 specific_ctx_id
;
2597 struct hrtimer poll_check_timer
;
2598 wait_queue_head_t poll_wq
;
2602 * For rate limiting any notifications of spurious
2603 * invalid OA reports
2605 struct ratelimit_state spurious_report_rs
;
2608 int period_exponent
;
2609 int timestamp_frequency
;
2611 struct i915_oa_config test_config
;
2614 struct i915_vma
*vma
;
2621 * Locks reads and writes to all head/tail state
2623 * Consider: the head and tail pointer state
2624 * needs to be read consistently from a hrtimer
2625 * callback (atomic context) and read() fop
2626 * (user context) with tail pointer updates
2627 * happening in atomic context and head updates
2628 * in user context and the (unlikely)
2629 * possibility of read() errors needing to
2630 * reset all head/tail state.
2632 * Note: Contention or performance aren't
2633 * currently a significant concern here
2634 * considering the relatively low frequency of
2635 * hrtimer callbacks (5ms period) and that
2636 * reads typically only happen in response to a
2637 * hrtimer event and likely complete before the
2640 * Note: This lock is not held *while* reading
2641 * and copying data to userspace so the value
2642 * of head observed in htrimer callbacks won't
2643 * represent any partial consumption of data.
2645 spinlock_t ptr_lock
;
2648 * One 'aging' tail pointer and one 'aged'
2649 * tail pointer ready to used for reading.
2651 * Initial values of 0xffffffff are invalid
2652 * and imply that an update is required
2653 * (and should be ignored by an attempted
2661 * Index for the aged tail ready to read()
2664 unsigned int aged_tail_idx
;
2667 * A monotonic timestamp for when the current
2668 * aging tail pointer was read; used to
2669 * determine when it is old enough to trust.
2671 u64 aging_timestamp
;
2674 * Although we can always read back the head
2675 * pointer register, we prefer to avoid
2676 * trusting the HW state, just to avoid any
2677 * risk that some hardware condition could
2678 * somehow bump the head pointer unpredictably
2679 * and cause us to forward the wrong OA buffer
2680 * data to userspace.
2685 u32 gen7_latched_oastatus1
;
2686 u32 ctx_oactxctrl_offset
;
2687 u32 ctx_flexeu0_offset
;
2690 * The RPT_ID/reason field for Gen8+ includes a bit
2691 * to determine if the CTX ID in the report is valid
2692 * but the specific bit differs between Gen 8 and 9
2694 u32 gen8_valid_ctx_bit
;
2696 struct i915_oa_ops ops
;
2697 const struct i915_oa_format
*oa_formats
;
2701 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2703 void (*resume
)(struct drm_i915_private
*);
2704 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2706 struct list_head timelines
;
2707 struct i915_gem_timeline global_timeline
;
2708 u32 active_requests
;
2711 * Is the GPU currently considered idle, or busy executing
2712 * userspace requests? Whilst idle, we allow runtime power
2713 * management to power down the hardware and display clocks.
2714 * In order to reduce the effect on performance, there
2715 * is a slight delay before we do so.
2720 * We leave the user IRQ off as much as possible,
2721 * but this means that requests will finish and never
2722 * be retired once the system goes idle. Set a timer to
2723 * fire periodically while the ring is running. When it
2724 * fires, go retire requests.
2726 struct delayed_work retire_work
;
2729 * When we detect an idle GPU, we want to turn on
2730 * powersaving features. So once we see that there
2731 * are no more requests outstanding and no more
2732 * arrive within a small period of time, we fire
2733 * off the idle_work.
2735 struct delayed_work idle_work
;
2737 ktime_t last_init_time
;
2740 /* perform PHY state sanity checks? */
2741 bool chv_phy_assert
[2];
2745 /* Used to save the pipe-to-encoder mapping for audio */
2746 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2748 /* necessary resource sharing with HDMI LPE audio driver. */
2750 struct platform_device
*platdev
;
2755 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2756 * will be rejected. Instead look for a better place.
2760 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2762 return container_of(dev
, struct drm_i915_private
, drm
);
2765 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2767 return to_i915(dev_get_drvdata(kdev
));
2770 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2772 return container_of(guc
, struct drm_i915_private
, guc
);
2775 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2777 return container_of(huc
, struct drm_i915_private
, huc
);
2780 /* Simple iterator over all initialised engines */
2781 #define for_each_engine(engine__, dev_priv__, id__) \
2783 (id__) < I915_NUM_ENGINES; \
2785 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2787 /* Iterator over subset of engines selected by mask */
2788 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2789 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2790 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2792 enum hdmi_force_audio
{
2793 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2794 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2795 HDMI_AUDIO_AUTO
, /* trust EDID */
2796 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2799 #define I915_GTT_OFFSET_NONE ((u32)-1)
2802 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2803 * considered to be the frontbuffer for the given plane interface-wise. This
2804 * doesn't mean that the hw necessarily already scans it out, but that any
2805 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2807 * We have one bit per pipe and per scanout plane type.
2809 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2810 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2811 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2812 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2813 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2814 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2815 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2816 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2817 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2818 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2819 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2820 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2823 * Optimised SGL iterator for GEM objects
2825 static __always_inline
struct sgt_iter
{
2826 struct scatterlist
*sgp
;
2833 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2834 struct sgt_iter s
= { .sgp
= sgl
};
2837 s
.max
= s
.curr
= s
.sgp
->offset
;
2838 s
.max
+= s
.sgp
->length
;
2840 s
.dma
= sg_dma_address(s
.sgp
);
2842 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2848 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2851 if (unlikely(sg_is_chain(sg
)))
2852 sg
= sg_chain_ptr(sg
);
2857 * __sg_next - return the next scatterlist entry in a list
2858 * @sg: The current sg entry
2861 * If the entry is the last, return NULL; otherwise, step to the next
2862 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2863 * otherwise just return the pointer to the current element.
2865 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2867 #ifdef CONFIG_DEBUG_SG
2868 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2870 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2874 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2875 * @__dmap: DMA address (output)
2876 * @__iter: 'struct sgt_iter' (iterator state, internal)
2877 * @__sgt: sg_table to iterate over (input)
2879 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2880 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2881 ((__dmap) = (__iter).dma + (__iter).curr); \
2882 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2883 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2886 * for_each_sgt_page - iterate over the pages of the given sg_table
2887 * @__pp: page pointer (output)
2888 * @__iter: 'struct sgt_iter' (iterator state, internal)
2889 * @__sgt: sg_table to iterate over (input)
2891 #define for_each_sgt_page(__pp, __iter, __sgt) \
2892 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2893 ((__pp) = (__iter).pfn == 0 ? NULL : \
2894 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2895 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2896 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2898 static inline unsigned int i915_sg_page_sizes(struct scatterlist
*sg
)
2900 unsigned int page_sizes
;
2904 GEM_BUG_ON(sg
->offset
);
2905 GEM_BUG_ON(!IS_ALIGNED(sg
->length
, PAGE_SIZE
));
2906 page_sizes
|= sg
->length
;
2913 static inline unsigned int i915_sg_segment_size(void)
2915 unsigned int size
= swiotlb_max_segment();
2918 return SCATTERLIST_MAX_SEGMENT
;
2920 size
= rounddown(size
, PAGE_SIZE
);
2921 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2922 if (size
< PAGE_SIZE
)
2928 static inline const struct intel_device_info
*
2929 intel_info(const struct drm_i915_private
*dev_priv
)
2931 return &dev_priv
->info
;
2934 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2936 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2937 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2939 #define REVID_FOREVER 0xff
2940 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2942 #define GEN_FOREVER (0)
2944 #define INTEL_GEN_MASK(s, e) ( \
2945 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2946 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2947 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2948 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2952 * Returns true if Gen is in inclusive range [Start, End].
2954 * Use GEN_FOREVER for unbound start and or end.
2956 #define IS_GEN(dev_priv, s, e) \
2957 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2960 * Return true if revision is in range [since,until] inclusive.
2962 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2964 #define IS_REVID(p, since, until) \
2965 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2967 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2969 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2970 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2971 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2972 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2973 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2974 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2975 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2976 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2977 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2978 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2979 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2980 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2981 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2982 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2983 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2984 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2985 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2986 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2987 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2988 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2989 (dev_priv)->info.gt == 1)
2990 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2991 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2992 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2993 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2994 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2995 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2996 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2997 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2998 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2999 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
3000 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
3001 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
3002 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
3003 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
3004 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
3005 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
3006 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
3007 /* ULX machines are also considered ULT. */
3008 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
3009 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
3010 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
3011 (dev_priv)->info.gt == 3)
3012 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
3013 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
3014 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
3015 (dev_priv)->info.gt == 3)
3016 /* ULX machines are also considered ULT. */
3017 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
3018 INTEL_DEVID(dev_priv) == 0x0A1E)
3019 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
3020 INTEL_DEVID(dev_priv) == 0x1913 || \
3021 INTEL_DEVID(dev_priv) == 0x1916 || \
3022 INTEL_DEVID(dev_priv) == 0x1921 || \
3023 INTEL_DEVID(dev_priv) == 0x1926)
3024 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
3025 INTEL_DEVID(dev_priv) == 0x1915 || \
3026 INTEL_DEVID(dev_priv) == 0x191E)
3027 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
3028 INTEL_DEVID(dev_priv) == 0x5913 || \
3029 INTEL_DEVID(dev_priv) == 0x5916 || \
3030 INTEL_DEVID(dev_priv) == 0x5921 || \
3031 INTEL_DEVID(dev_priv) == 0x5926)
3032 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
3033 INTEL_DEVID(dev_priv) == 0x5915 || \
3034 INTEL_DEVID(dev_priv) == 0x591E)
3035 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
3036 (dev_priv)->info.gt == 2)
3037 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
3038 (dev_priv)->info.gt == 3)
3039 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
3040 (dev_priv)->info.gt == 4)
3041 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
3042 (dev_priv)->info.gt == 2)
3043 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
3044 (dev_priv)->info.gt == 3)
3045 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
3046 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
3047 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
3048 (dev_priv)->info.gt == 2)
3050 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
3052 #define SKL_REVID_A0 0x0
3053 #define SKL_REVID_B0 0x1
3054 #define SKL_REVID_C0 0x2
3055 #define SKL_REVID_D0 0x3
3056 #define SKL_REVID_E0 0x4
3057 #define SKL_REVID_F0 0x5
3058 #define SKL_REVID_G0 0x6
3059 #define SKL_REVID_H0 0x7
3061 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
3063 #define BXT_REVID_A0 0x0
3064 #define BXT_REVID_A1 0x1
3065 #define BXT_REVID_B0 0x3
3066 #define BXT_REVID_B_LAST 0x8
3067 #define BXT_REVID_C0 0x9
3069 #define IS_BXT_REVID(dev_priv, since, until) \
3070 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
3072 #define KBL_REVID_A0 0x0
3073 #define KBL_REVID_B0 0x1
3074 #define KBL_REVID_C0 0x2
3075 #define KBL_REVID_D0 0x3
3076 #define KBL_REVID_E0 0x4
3078 #define IS_KBL_REVID(dev_priv, since, until) \
3079 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
3081 #define GLK_REVID_A0 0x0
3082 #define GLK_REVID_A1 0x1
3084 #define IS_GLK_REVID(dev_priv, since, until) \
3085 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
3087 #define CNL_REVID_A0 0x0
3088 #define CNL_REVID_B0 0x1
3089 #define CNL_REVID_C0 0x2
3091 #define IS_CNL_REVID(p, since, until) \
3092 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
3095 * The genX designation typically refers to the render engine, so render
3096 * capability related checks should use IS_GEN, while display and other checks
3097 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
3100 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
3101 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
3102 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
3103 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
3104 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
3105 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
3106 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
3107 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
3108 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
3110 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
3111 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
3112 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
3114 #define ENGINE_MASK(id) BIT(id)
3115 #define RENDER_RING ENGINE_MASK(RCS)
3116 #define BSD_RING ENGINE_MASK(VCS)
3117 #define BLT_RING ENGINE_MASK(BCS)
3118 #define VEBOX_RING ENGINE_MASK(VECS)
3119 #define BSD2_RING ENGINE_MASK(VCS2)
3120 #define ALL_ENGINES (~0)
3122 #define HAS_ENGINE(dev_priv, id) \
3123 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
3125 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
3126 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
3127 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
3128 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
3130 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
3131 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
3132 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
3133 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
3134 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
3136 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
3138 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
3139 ((dev_priv)->info.has_logical_ring_contexts)
3140 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
3141 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
3142 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
3143 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
3144 GEM_BUG_ON((sizes) == 0); \
3145 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
3148 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
3149 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
3150 ((dev_priv)->info.overlay_needs_physical)
3152 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
3153 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
3155 /* WaRsDisableCoarsePowerGating:skl,bxt */
3156 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
3157 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
3160 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
3161 * even when in MSI mode. This results in spurious interrupt warnings if the
3162 * legacy irq no. is shared with another device. The kernel then disables that
3163 * interrupt source and so prevents the other device from working properly.
3165 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
3168 #define HAS_AUX_IRQ(dev_priv) true
3169 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
3171 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
3172 * rows, which changed the alignment requirements and fence programming.
3174 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
3175 !(IS_I915G(dev_priv) || \
3176 IS_I915GM(dev_priv)))
3177 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
3178 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
3180 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
3181 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
3182 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
3184 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
3186 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
3188 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
3189 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
3190 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
3191 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
3192 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
3194 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
3196 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
3197 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
3199 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
3202 * For now, anything with a GuC requires uCode loading, and then supports
3203 * command submission once loaded. But these are logically independent
3204 * properties, so we have separate macros to test them.
3206 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
3207 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
3208 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3209 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
3210 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3212 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3214 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
3216 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3217 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3218 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3219 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3220 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3221 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3222 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3223 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3224 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3225 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3226 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3227 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3228 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3229 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3230 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3231 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3233 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3234 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3235 #define HAS_PCH_CNP_LP(dev_priv) \
3236 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3237 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3238 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3239 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3240 #define HAS_PCH_LPT_LP(dev_priv) \
3241 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3242 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3243 #define HAS_PCH_LPT_H(dev_priv) \
3244 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3245 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3246 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3247 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3248 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3249 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3251 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3253 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3255 /* DPF == dynamic parity feature */
3256 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3257 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3258 2 : HAS_L3_DPF(dev_priv))
3260 #define GT_FREQUENCY_MULTIPLIER 50
3261 #define GEN9_FREQ_SCALER 3
3263 #include "i915_trace.h"
3265 static inline bool intel_vtd_active(void)
3267 #ifdef CONFIG_INTEL_IOMMU
3268 if (intel_iommu_gfx_mapped
)
3274 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3276 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
3280 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3282 return IS_BROXTON(dev_priv
) && intel_vtd_active();
3285 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
3288 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
3292 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
3293 const char *fmt
, ...);
3295 #define i915_report_error(dev_priv, fmt, ...) \
3296 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3298 #ifdef CONFIG_COMPAT
3299 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3302 #define i915_compat_ioctl NULL
3304 extern const struct dev_pm_ops i915_pm_ops
;
3306 extern int i915_driver_load(struct pci_dev
*pdev
,
3307 const struct pci_device_id
*ent
);
3308 extern void i915_driver_unload(struct drm_device
*dev
);
3309 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3310 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3312 #define I915_RESET_QUIET BIT(0)
3313 extern void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
);
3314 extern int i915_reset_engine(struct intel_engine_cs
*engine
,
3315 unsigned int flags
);
3317 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
3318 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3319 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3320 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3321 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3322 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3323 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3324 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3325 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3327 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
3328 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3330 /* intel_hotplug.c */
3331 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3332 u32 pin_mask
, u32 long_mask
);
3333 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3334 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3335 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3336 enum port
intel_hpd_pin_to_port(enum hpd_pin pin
);
3337 enum hpd_pin
intel_hpd_pin(enum port port
);
3338 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3339 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3342 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3344 unsigned long delay
;
3346 if (unlikely(!i915_modparams
.enable_hangcheck
))
3349 /* Don't continually defer the hangcheck so that it is always run at
3350 * least once after work has been scheduled on any ring. Otherwise,
3351 * we will ignore a hung ring if a second ring is kept busy.
3354 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3355 queue_delayed_work(system_long_wq
,
3356 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3360 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3362 const char *fmt
, ...);
3364 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3365 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
3366 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3367 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3369 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3371 return dev_priv
->gvt
;
3374 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3376 return dev_priv
->vgpu
.active
;
3379 u32
i915_pipestat_enable_mask(struct drm_i915_private
*dev_priv
,
3382 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3386 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3389 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3390 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3391 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3394 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3395 uint32_t interrupt_mask
,
3396 uint32_t enabled_irq_mask
);
3398 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3400 ilk_update_display_irq(dev_priv
, bits
, bits
);
3403 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3405 ilk_update_display_irq(dev_priv
, bits
, 0);
3407 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3409 uint32_t interrupt_mask
,
3410 uint32_t enabled_irq_mask
);
3411 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3412 enum pipe pipe
, uint32_t bits
)
3414 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3416 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3417 enum pipe pipe
, uint32_t bits
)
3419 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3421 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3422 uint32_t interrupt_mask
,
3423 uint32_t enabled_irq_mask
);
3425 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3427 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3430 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3432 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3436 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3437 struct drm_file
*file_priv
);
3438 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3439 struct drm_file
*file_priv
);
3440 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3441 struct drm_file
*file_priv
);
3442 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3443 struct drm_file
*file_priv
);
3444 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3445 struct drm_file
*file_priv
);
3446 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3447 struct drm_file
*file_priv
);
3448 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3449 struct drm_file
*file_priv
);
3450 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3451 struct drm_file
*file_priv
);
3452 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3453 struct drm_file
*file_priv
);
3454 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3455 struct drm_file
*file_priv
);
3456 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3457 struct drm_file
*file
);
3458 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3459 struct drm_file
*file
);
3460 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3461 struct drm_file
*file_priv
);
3462 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3463 struct drm_file
*file_priv
);
3464 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3465 struct drm_file
*file_priv
);
3466 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3467 struct drm_file
*file_priv
);
3468 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3469 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
3470 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3471 struct drm_file
*file
);
3472 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3473 struct drm_file
*file_priv
);
3474 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3475 struct drm_file
*file_priv
);
3476 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3477 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3478 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3479 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3480 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3481 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3483 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3484 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3485 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3486 const struct drm_i915_gem_object_ops
*ops
);
3487 struct drm_i915_gem_object
*
3488 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3489 struct drm_i915_gem_object
*
3490 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3491 const void *data
, size_t size
);
3492 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3493 void i915_gem_free_object(struct drm_gem_object
*obj
);
3495 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3497 /* A single pass should suffice to release all the freed objects (along
3498 * most call paths) , but be a little more paranoid in that freeing
3499 * the objects does take a little amount of time, during which the rcu
3500 * callbacks could have added new objects into the freed list, and
3501 * armed the work again.
3505 } while (flush_work(&i915
->mm
.free_work
));
3508 static inline void i915_gem_drain_workqueue(struct drm_i915_private
*i915
)
3511 * Similar to objects above (see i915_gem_drain_freed-objects), in
3512 * general we have workers that are armed by RCU and then rearm
3513 * themselves in their callbacks. To be paranoid, we need to
3514 * drain the workqueue a second time after waiting for the RCU
3515 * grace period so that we catch work queued via RCU from the first
3516 * pass. As neither drain_workqueue() nor flush_workqueue() report
3517 * a result, we make an assumption that we only don't require more
3518 * than 2 passes to catch all recursive RCU delayed work.
3524 drain_workqueue(i915
->wq
);
3528 struct i915_vma
* __must_check
3529 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3530 const struct i915_ggtt_view
*view
,
3535 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3536 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3538 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3540 static inline int __sg_page_count(const struct scatterlist
*sg
)
3542 return sg
->length
>> PAGE_SHIFT
;
3545 struct scatterlist
*
3546 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3547 unsigned int n
, unsigned int *offset
);
3550 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3554 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3558 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3561 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3562 struct sg_table
*pages
,
3563 unsigned int sg_page_sizes
);
3564 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3566 static inline int __must_check
3567 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3569 might_lock(&obj
->mm
.lock
);
3571 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3574 return __i915_gem_object_get_pages(obj
);
3578 i915_gem_object_has_pages(struct drm_i915_gem_object
*obj
)
3580 return !IS_ERR_OR_NULL(READ_ONCE(obj
->mm
.pages
));
3584 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3586 GEM_BUG_ON(!i915_gem_object_has_pages(obj
));
3588 atomic_inc(&obj
->mm
.pages_pin_count
);
3592 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3594 return atomic_read(&obj
->mm
.pages_pin_count
);
3598 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3600 GEM_BUG_ON(!i915_gem_object_has_pages(obj
));
3601 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3603 atomic_dec(&obj
->mm
.pages_pin_count
);
3607 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3609 __i915_gem_object_unpin_pages(obj
);
3612 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3617 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3618 enum i915_mm_subclass subclass
);
3619 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3621 enum i915_map_type
{
3624 #define I915_MAP_OVERRIDE BIT(31)
3625 I915_MAP_FORCE_WB
= I915_MAP_WB
| I915_MAP_OVERRIDE
,
3626 I915_MAP_FORCE_WC
= I915_MAP_WC
| I915_MAP_OVERRIDE
,
3630 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3631 * @obj: the object to map into kernel address space
3632 * @type: the type of mapping, used to select pgprot_t
3634 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3635 * pages and then returns a contiguous mapping of the backing storage into
3636 * the kernel address space. Based on the @type of mapping, the PTE will be
3637 * set to either WriteBack or WriteCombine (via pgprot_t).
3639 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3640 * mapping is no longer required.
3642 * Returns the pointer through which to access the mapped object, or an
3643 * ERR_PTR() on error.
3645 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3646 enum i915_map_type type
);
3649 * i915_gem_object_unpin_map - releases an earlier mapping
3650 * @obj: the object to unmap
3652 * After pinning the object and mapping its pages, once you are finished
3653 * with your access, call i915_gem_object_unpin_map() to release the pin
3654 * upon the mapping. Once the pin count reaches zero, that mapping may be
3657 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3659 i915_gem_object_unpin_pages(obj
);
3662 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3663 unsigned int *needs_clflush
);
3664 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3665 unsigned int *needs_clflush
);
3666 #define CLFLUSH_BEFORE BIT(0)
3667 #define CLFLUSH_AFTER BIT(1)
3668 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3671 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3673 i915_gem_object_unpin_pages(obj
);
3676 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3677 void i915_vma_move_to_active(struct i915_vma
*vma
,
3678 struct drm_i915_gem_request
*req
,
3679 unsigned int flags
);
3680 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3681 struct drm_device
*dev
,
3682 struct drm_mode_create_dumb
*args
);
3683 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3684 uint32_t handle
, uint64_t *offset
);
3685 int i915_gem_mmap_gtt_version(void);
3687 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3688 struct drm_i915_gem_object
*new,
3689 unsigned frontbuffer_bits
);
3691 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3693 struct drm_i915_gem_request
*
3694 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3696 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3698 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3700 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3703 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3705 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3708 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3710 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3713 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3715 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3718 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3720 return READ_ONCE(error
->reset_count
);
3723 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3724 struct intel_engine_cs
*engine
)
3726 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3729 struct drm_i915_gem_request
*
3730 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3731 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3732 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3733 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3734 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3735 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3736 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3737 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3738 struct drm_i915_gem_request
*request
);
3740 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3741 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3742 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3743 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3744 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3745 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3746 unsigned int flags
);
3747 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3748 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3749 int i915_gem_fault(struct vm_fault
*vmf
);
3750 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3753 struct intel_rps_client
*rps
);
3754 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3757 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3760 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3762 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3764 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3765 struct i915_vma
* __must_check
3766 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3768 const struct i915_ggtt_view
*view
);
3769 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3770 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3772 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3773 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3775 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3776 enum i915_cache_level cache_level
);
3778 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3779 struct dma_buf
*dma_buf
);
3781 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3782 struct drm_gem_object
*gem_obj
, int flags
);
3784 static inline struct i915_hw_ppgtt
*
3785 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3787 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3790 /* i915_gem_fence_reg.c */
3791 struct drm_i915_fence_reg
*
3792 i915_reserve_fence(struct drm_i915_private
*dev_priv
);
3793 void i915_unreserve_fence(struct drm_i915_fence_reg
*fence
);
3795 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3796 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3798 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3799 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3800 struct sg_table
*pages
);
3801 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3802 struct sg_table
*pages
);
3804 static inline struct i915_gem_context
*
3805 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3807 return idr_find(&file_priv
->context_idr
, id
);
3810 static inline struct i915_gem_context
*
3811 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3813 struct i915_gem_context
*ctx
;
3816 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3817 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3824 static inline struct intel_timeline
*
3825 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3826 struct intel_engine_cs
*engine
)
3828 struct i915_address_space
*vm
;
3830 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3831 return &vm
->timeline
.engine
[engine
->id
];
3834 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3835 struct drm_file
*file
);
3836 int i915_perf_add_config_ioctl(struct drm_device
*dev
, void *data
,
3837 struct drm_file
*file
);
3838 int i915_perf_remove_config_ioctl(struct drm_device
*dev
, void *data
,
3839 struct drm_file
*file
);
3840 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3841 struct i915_gem_context
*ctx
,
3842 uint32_t *reg_state
);
3844 /* i915_gem_evict.c */
3845 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3846 u64 min_size
, u64 alignment
,
3847 unsigned cache_level
,
3850 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3851 struct drm_mm_node
*node
,
3852 unsigned int flags
);
3853 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3855 /* belongs in i915_gem_gtt.h */
3856 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3859 if (INTEL_GEN(dev_priv
) < 6)
3860 intel_gtt_chipset_flush();
3863 /* i915_gem_stolen.c */
3864 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3865 struct drm_mm_node
*node
, u64 size
,
3866 unsigned alignment
);
3867 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3868 struct drm_mm_node
*node
, u64 size
,
3869 unsigned alignment
, u64 start
,
3871 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3872 struct drm_mm_node
*node
);
3873 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3874 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3875 struct drm_i915_gem_object
*
3876 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3877 struct drm_i915_gem_object
*
3878 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3883 /* i915_gem_internal.c */
3884 struct drm_i915_gem_object
*
3885 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3888 /* i915_gem_shrinker.c */
3889 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3890 unsigned long target
,
3891 unsigned long *nr_scanned
,
3893 #define I915_SHRINK_PURGEABLE 0x1
3894 #define I915_SHRINK_UNBOUND 0x2
3895 #define I915_SHRINK_BOUND 0x4
3896 #define I915_SHRINK_ACTIVE 0x8
3897 #define I915_SHRINK_VMAPS 0x10
3898 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3899 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3900 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3903 /* i915_gem_tiling.c */
3904 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3906 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3908 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3909 i915_gem_object_is_tiled(obj
);
3912 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3913 unsigned int tiling
, unsigned int stride
);
3914 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3915 unsigned int tiling
, unsigned int stride
);
3917 /* i915_debugfs.c */
3918 #ifdef CONFIG_DEBUG_FS
3919 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3920 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3921 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3923 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3924 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3926 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3929 /* i915_gpu_error.c */
3930 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3933 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3934 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3935 const struct i915_gpu_state
*gpu
);
3936 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3937 struct drm_i915_private
*i915
,
3938 size_t count
, loff_t pos
);
3939 static inline void i915_error_state_buf_release(
3940 struct drm_i915_error_state_buf
*eb
)
3945 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3946 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3948 const char *error_msg
);
3950 static inline struct i915_gpu_state
*
3951 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3953 kref_get(&gpu
->ref
);
3957 void __i915_gpu_state_free(struct kref
*kref
);
3958 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3961 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3964 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3965 void i915_reset_error_state(struct drm_i915_private
*i915
);
3969 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3971 const char *error_msg
)
3975 static inline struct i915_gpu_state
*
3976 i915_first_error_state(struct drm_i915_private
*i915
)
3981 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3987 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3989 /* i915_cmd_parser.c */
3990 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3991 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3992 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3993 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3994 struct drm_i915_gem_object
*batch_obj
,
3995 struct drm_i915_gem_object
*shadow_batch_obj
,
3996 u32 batch_start_offset
,
4001 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
4002 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
4003 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
4004 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
4006 /* i915_suspend.c */
4007 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
4008 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
4011 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
4012 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
4014 /* intel_lpe_audio.c */
4015 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
4016 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
4017 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
4018 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
4019 enum pipe pipe
, enum port port
,
4020 const void *eld
, int ls_clock
, bool dp_output
);
4023 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
4024 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
4025 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
4028 extern struct i2c_adapter
*
4029 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
4030 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
4031 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
4032 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
4034 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
4036 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
4039 void intel_bios_init(struct drm_i915_private
*dev_priv
);
4040 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
4041 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
4042 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
4043 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
4044 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
4045 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
4046 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
4047 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
4049 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
4053 /* intel_opregion.c */
4055 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
4056 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
4057 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
4058 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
4059 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
4061 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
4063 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
4065 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
4066 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
4067 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
4068 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
4072 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
4077 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
4081 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
4089 extern void intel_register_dsm_handler(void);
4090 extern void intel_unregister_dsm_handler(void);
4092 static inline void intel_register_dsm_handler(void) { return; }
4093 static inline void intel_unregister_dsm_handler(void) { return; }
4094 #endif /* CONFIG_ACPI */
4096 /* intel_device_info.c */
4097 static inline struct intel_device_info
*
4098 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
4100 return (struct intel_device_info
*)&dev_priv
->info
;
4103 const char *intel_platform_name(enum intel_platform platform
);
4104 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
4105 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
4108 extern void intel_modeset_init_hw(struct drm_device
*dev
);
4109 extern int intel_modeset_init(struct drm_device
*dev
);
4110 extern void intel_modeset_gem_init(struct drm_device
*dev
);
4111 extern void intel_modeset_cleanup(struct drm_device
*dev
);
4112 extern int intel_connector_register(struct drm_connector
*);
4113 extern void intel_connector_unregister(struct drm_connector
*);
4114 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
4116 extern void intel_display_resume(struct drm_device
*dev
);
4117 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
4118 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
4119 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
4120 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
4121 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
4122 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
4125 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
4126 struct drm_file
*file
);
4129 extern struct intel_overlay_error_state
*
4130 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
4131 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
4132 struct intel_overlay_error_state
*error
);
4134 extern struct intel_display_error_state
*
4135 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
4136 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
4137 struct intel_display_error_state
*error
);
4139 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
4140 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
4141 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
4142 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
4144 /* intel_sideband.c */
4145 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
4146 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
4147 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
4148 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
4149 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
4150 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4151 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4152 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4153 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4154 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4155 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4156 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
4157 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
4158 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
4159 enum intel_sbi_destination destination
);
4160 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
4161 enum intel_sbi_destination destination
);
4162 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4163 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4165 /* intel_dpio_phy.c */
4166 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
4167 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
4168 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
4169 enum port port
, u32 margin
, u32 scale
,
4170 u32 enable
, u32 deemphasis
);
4171 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4172 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4173 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
4175 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
4177 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
4178 uint8_t lane_count
);
4179 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
4180 uint8_t lane_lat_optim_mask
);
4181 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
4183 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
4184 u32 deemph_reg_value
, u32 margin_reg_value
,
4185 bool uniq_trans_scale
);
4186 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
4188 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4189 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4190 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
4191 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
4193 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
4194 u32 demph_reg_value
, u32 preemph_reg_value
,
4195 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
4196 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4197 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4198 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
4200 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
4201 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
4202 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
4203 const i915_reg_t reg
);
4205 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
4206 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
4208 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
4209 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
4210 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
4211 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
4213 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
4214 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
4215 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
4216 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
4218 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
4219 * will be implemented using 2 32-bit writes in an arbitrary order with
4220 * an arbitrary delay between them. This can cause the hardware to
4221 * act upon the intermediate value, possibly leading to corruption and
4222 * machine death. For this reason we do not support I915_WRITE64, or
4223 * dev_priv->uncore.funcs.mmio_writeq.
4225 * When reading a 64-bit value as two 32-bit values, the delay may cause
4226 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
4227 * occasionally a 64-bit register does not actualy support a full readq
4228 * and must be read using two 32-bit reads.
4230 * You have been warned.
4232 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
4234 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
4235 u32 upper, lower, old_upper, loop = 0; \
4236 upper = I915_READ(upper_reg); \
4238 old_upper = upper; \
4239 lower = I915_READ(lower_reg); \
4240 upper = I915_READ(upper_reg); \
4241 } while (upper != old_upper && loop++ < 2); \
4242 (u64)upper << 32 | lower; })
4244 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
4245 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
4247 #define __raw_read(x, s) \
4248 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4251 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4254 #define __raw_write(x, s) \
4255 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4256 i915_reg_t reg, uint##x##_t val) \
4258 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4273 /* These are untraced mmio-accessors that are only valid to be used inside
4274 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4277 * Think twice, and think again, before using these.
4279 * As an example, these accessors can possibly be used between:
4281 * spin_lock_irq(&dev_priv->uncore.lock);
4282 * intel_uncore_forcewake_get__locked();
4286 * intel_uncore_forcewake_put__locked();
4287 * spin_unlock_irq(&dev_priv->uncore.lock);
4290 * Note: some registers may not need forcewake held, so
4291 * intel_uncore_forcewake_{get,put} can be omitted, see
4292 * intel_uncore_forcewake_for_reg().
4294 * Certain architectures will die if the same cacheline is concurrently accessed
4295 * by different clients (e.g. on Ivybridge). Access to registers should
4296 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4297 * a more localised lock guarding all access to that bank of registers.
4299 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4300 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4301 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4302 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4304 /* "Broadcast RGB" property */
4305 #define INTEL_BROADCAST_RGB_AUTO 0
4306 #define INTEL_BROADCAST_RGB_FULL 1
4307 #define INTEL_BROADCAST_RGB_LIMITED 2
4309 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4311 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4312 return VLV_VGACNTRL
;
4313 else if (INTEL_GEN(dev_priv
) >= 5)
4314 return CPU_VGACNTRL
;
4319 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4321 unsigned long j
= msecs_to_jiffies(m
);
4323 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4326 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4328 /* nsecs_to_jiffies64() does not guard against overflow */
4329 if (NSEC_PER_SEC
% HZ
&&
4330 div_u64(n
, NSEC_PER_SEC
) >= MAX_JIFFY_OFFSET
/ HZ
)
4331 return MAX_JIFFY_OFFSET
;
4333 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4336 static inline unsigned long
4337 timespec_to_jiffies_timeout(const struct timespec
*value
)
4339 unsigned long j
= timespec_to_jiffies(value
);
4341 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4345 * If you need to wait X milliseconds between events A and B, but event B
4346 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4347 * when event A happened, then just before event B you call this function and
4348 * pass the timestamp as the first argument, and X as the second argument.
4351 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4353 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4356 * Don't re-read the value of "jiffies" every time since it may change
4357 * behind our back and break the math.
4359 tmp_jiffies
= jiffies
;
4360 target_jiffies
= timestamp_jiffies
+
4361 msecs_to_jiffies_timeout(to_wait_ms
);
4363 if (time_after(target_jiffies
, tmp_jiffies
)) {
4364 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4365 while (remaining_jiffies
)
4367 schedule_timeout_uninterruptible(remaining_jiffies
);
4372 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4374 struct intel_engine_cs
*engine
= req
->engine
;
4377 /* Note that the engine may have wrapped around the seqno, and
4378 * so our request->global_seqno will be ahead of the hardware,
4379 * even though it completed the request before wrapping. We catch
4380 * this by kicking all the waiters before resetting the seqno
4381 * in hardware, and also signal the fence.
4383 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4386 /* The request was dequeued before we were awoken. We check after
4387 * inspecting the hw to confirm that this was the same request
4388 * that generated the HWS update. The memory barriers within
4389 * the request execution are sufficient to ensure that a check
4390 * after reading the value from hw matches this request.
4392 seqno
= i915_gem_request_global_seqno(req
);
4396 /* Before we do the heavier coherent read of the seqno,
4397 * check the value (hopefully) in the CPU cacheline.
4399 if (__i915_gem_request_completed(req
, seqno
))
4402 /* Ensure our read of the seqno is coherent so that we
4403 * do not "miss an interrupt" (i.e. if this is the last
4404 * request and the seqno write from the GPU is not visible
4405 * by the time the interrupt fires, we will see that the
4406 * request is incomplete and go back to sleep awaiting
4407 * another interrupt that will never come.)
4409 * Strictly, we only need to do this once after an interrupt,
4410 * but it is easier and safer to do it every time the waiter
4413 if (engine
->irq_seqno_barrier
&&
4414 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4415 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4417 /* The ordering of irq_posted versus applying the barrier
4418 * is crucial. The clearing of the current irq_posted must
4419 * be visible before we perform the barrier operation,
4420 * such that if a subsequent interrupt arrives, irq_posted
4421 * is reasserted and our task rewoken (which causes us to
4422 * do another __i915_request_irq_complete() immediately
4423 * and reapply the barrier). Conversely, if the clear
4424 * occurs after the barrier, then an interrupt that arrived
4425 * whilst we waited on the barrier would not trigger a
4426 * barrier on the next pass, and the read may not see the
4429 engine
->irq_seqno_barrier(engine
);
4431 /* If we consume the irq, but we are no longer the bottom-half,
4432 * the real bottom-half may not have serialised their own
4433 * seqno check with the irq-barrier (i.e. may have inspected
4434 * the seqno before we believe it coherent since they see
4435 * irq_posted == false but we are still running).
4437 spin_lock_irq(&b
->irq_lock
);
4438 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4439 /* Note that if the bottom-half is changed as we
4440 * are sending the wake-up, the new bottom-half will
4441 * be woken by whomever made the change. We only have
4442 * to worry about when we steal the irq-posted for
4445 wake_up_process(b
->irq_wait
->tsk
);
4446 spin_unlock_irq(&b
->irq_lock
);
4448 if (__i915_gem_request_completed(req
, seqno
))
4455 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4456 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4458 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4459 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4460 * perform the operation. To check beforehand, pass in the parameters to
4461 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4462 * you only need to pass in the minor offsets, page-aligned pointers are
4465 * For just checking for SSE4.1, in the foreknowledge that the future use
4466 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4468 #define i915_can_memcpy_from_wc(dst, src, len) \
4469 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4471 #define i915_has_memcpy_from_wc() \
4472 i915_memcpy_from_wc(NULL, NULL, 0)
4475 int remap_io_mapping(struct vm_area_struct
*vma
,
4476 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4477 struct io_mapping
*iomap
);
4479 static inline int intel_hws_csb_write_index(struct drm_i915_private
*i915
)
4481 if (INTEL_GEN(i915
) >= 10)
4482 return CNL_HWS_CSB_WRITE_INDEX
;
4484 return I915_HWS_CSB_WRITE_INDEX
;