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drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_cdclk.c
1 /*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "intel_drv.h"
25
26 /**
27 * DOC: CDCLK / RAWCLK
28 *
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
33 *
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
38 *
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
43 *
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
47 *
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
52 */
53
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
56 {
57 cdclk_state->cdclk = 133333;
58 }
59
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
62 {
63 cdclk_state->cdclk = 200000;
64 }
65
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
68 {
69 cdclk_state->cdclk = 266667;
70 }
71
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
74 {
75 cdclk_state->cdclk = 333333;
76 }
77
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
80 {
81 cdclk_state->cdclk = 400000;
82 }
83
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
86 {
87 cdclk_state->cdclk = 450000;
88 }
89
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
92 {
93 struct pci_dev *pdev = dev_priv->drm.pdev;
94 u16 hpllcc = 0;
95
96 /*
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
100 */
101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
103 return;
104 }
105
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
108
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
111 */
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
116 cdclk_state->cdclk = 200000;
117 break;
118 case GC_CLOCK_166_250:
119 cdclk_state->cdclk = 250000;
120 break;
121 case GC_CLOCK_100_133:
122 cdclk_state->cdclk = 133333;
123 break;
124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
127 cdclk_state->cdclk = 266667;
128 break;
129 }
130 }
131
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
134 {
135 struct pci_dev *pdev = dev_priv->drm.pdev;
136 u16 gcfgc = 0;
137
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
139
140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
142 return;
143 }
144
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
147 cdclk_state->cdclk = 333333;
148 break;
149 default:
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
151 cdclk_state->cdclk = 190000;
152 break;
153 }
154 }
155
156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
158 {
159 struct pci_dev *pdev = dev_priv->drm.pdev;
160 u16 gcfgc = 0;
161
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
163
164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
166 return;
167 }
168
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
171 cdclk_state->cdclk = 320000;
172 break;
173 default:
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
175 cdclk_state->cdclk = 200000;
176 break;
177 }
178 }
179
180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
181 {
182 static const unsigned int blb_vco[8] = {
183 [0] = 3200000,
184 [1] = 4000000,
185 [2] = 5333333,
186 [3] = 4800000,
187 [4] = 6400000,
188 };
189 static const unsigned int pnv_vco[8] = {
190 [0] = 3200000,
191 [1] = 4000000,
192 [2] = 5333333,
193 [3] = 4800000,
194 [4] = 2666667,
195 };
196 static const unsigned int cl_vco[8] = {
197 [0] = 3200000,
198 [1] = 4000000,
199 [2] = 5333333,
200 [3] = 6400000,
201 [4] = 3333333,
202 [5] = 3566667,
203 [6] = 4266667,
204 };
205 static const unsigned int elk_vco[8] = {
206 [0] = 3200000,
207 [1] = 4000000,
208 [2] = 5333333,
209 [3] = 4800000,
210 };
211 static const unsigned int ctg_vco[8] = {
212 [0] = 3200000,
213 [1] = 4000000,
214 [2] = 5333333,
215 [3] = 6400000,
216 [4] = 2666667,
217 [5] = 4266667,
218 };
219 const unsigned int *vco_table;
220 unsigned int vco;
221 uint8_t tmp = 0;
222
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
225 vco_table = ctg_vco;
226 else if (IS_G45(dev_priv))
227 vco_table = elk_vco;
228 else if (IS_I965GM(dev_priv))
229 vco_table = cl_vco;
230 else if (IS_PINEVIEW(dev_priv))
231 vco_table = pnv_vco;
232 else if (IS_G33(dev_priv))
233 vco_table = blb_vco;
234 else
235 return 0;
236
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
238
239 vco = vco_table[tmp & 0x7];
240 if (vco == 0)
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
242 else
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
244
245 return vco;
246 }
247
248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
249 struct intel_cdclk_state *cdclk_state)
250 {
251 struct pci_dev *pdev = dev_priv->drm.pdev;
252 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
253 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
254 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
255 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
256 const uint8_t *div_table;
257 unsigned int cdclk_sel;
258 uint16_t tmp = 0;
259
260 cdclk_state->vco = intel_hpll_vco(dev_priv);
261
262 pci_read_config_word(pdev, GCFGC, &tmp);
263
264 cdclk_sel = (tmp >> 4) & 0x7;
265
266 if (cdclk_sel >= ARRAY_SIZE(div_3200))
267 goto fail;
268
269 switch (cdclk_state->vco) {
270 case 3200000:
271 div_table = div_3200;
272 break;
273 case 4000000:
274 div_table = div_4000;
275 break;
276 case 4800000:
277 div_table = div_4800;
278 break;
279 case 5333333:
280 div_table = div_5333;
281 break;
282 default:
283 goto fail;
284 }
285
286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
287 div_table[cdclk_sel]);
288 return;
289
290 fail:
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
292 cdclk_state->vco, tmp);
293 cdclk_state->cdclk = 190476;
294 }
295
296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
297 struct intel_cdclk_state *cdclk_state)
298 {
299 struct pci_dev *pdev = dev_priv->drm.pdev;
300 u16 gcfgc = 0;
301
302 pci_read_config_word(pdev, GCFGC, &gcfgc);
303
304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
306 cdclk_state->cdclk = 266667;
307 break;
308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
309 cdclk_state->cdclk = 333333;
310 break;
311 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
312 cdclk_state->cdclk = 444444;
313 break;
314 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
315 cdclk_state->cdclk = 200000;
316 break;
317 default:
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
319 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
320 cdclk_state->cdclk = 133333;
321 break;
322 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
323 cdclk_state->cdclk = 166667;
324 break;
325 }
326 }
327
328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
329 struct intel_cdclk_state *cdclk_state)
330 {
331 struct pci_dev *pdev = dev_priv->drm.pdev;
332 static const uint8_t div_3200[] = { 16, 10, 8 };
333 static const uint8_t div_4000[] = { 20, 12, 10 };
334 static const uint8_t div_5333[] = { 24, 16, 14 };
335 const uint8_t *div_table;
336 unsigned int cdclk_sel;
337 uint16_t tmp = 0;
338
339 cdclk_state->vco = intel_hpll_vco(dev_priv);
340
341 pci_read_config_word(pdev, GCFGC, &tmp);
342
343 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
344
345 if (cdclk_sel >= ARRAY_SIZE(div_3200))
346 goto fail;
347
348 switch (cdclk_state->vco) {
349 case 3200000:
350 div_table = div_3200;
351 break;
352 case 4000000:
353 div_table = div_4000;
354 break;
355 case 5333333:
356 div_table = div_5333;
357 break;
358 default:
359 goto fail;
360 }
361
362 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
363 div_table[cdclk_sel]);
364 return;
365
366 fail:
367 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
368 cdclk_state->vco, tmp);
369 cdclk_state->cdclk = 200000;
370 }
371
372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
373 struct intel_cdclk_state *cdclk_state)
374 {
375 struct pci_dev *pdev = dev_priv->drm.pdev;
376 unsigned int cdclk_sel;
377 uint16_t tmp = 0;
378
379 cdclk_state->vco = intel_hpll_vco(dev_priv);
380
381 pci_read_config_word(pdev, GCFGC, &tmp);
382
383 cdclk_sel = (tmp >> 12) & 0x1;
384
385 switch (cdclk_state->vco) {
386 case 2666667:
387 case 4000000:
388 case 5333333:
389 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
390 break;
391 case 3200000:
392 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
393 break;
394 default:
395 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
396 cdclk_state->vco, tmp);
397 cdclk_state->cdclk = 222222;
398 break;
399 }
400 }
401
402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
403 struct intel_cdclk_state *cdclk_state)
404 {
405 uint32_t lcpll = I915_READ(LCPLL_CTL);
406 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
407
408 if (lcpll & LCPLL_CD_SOURCE_FCLK)
409 cdclk_state->cdclk = 800000;
410 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
411 cdclk_state->cdclk = 450000;
412 else if (freq == LCPLL_CLK_FREQ_450)
413 cdclk_state->cdclk = 450000;
414 else if (IS_HSW_ULT(dev_priv))
415 cdclk_state->cdclk = 337500;
416 else
417 cdclk_state->cdclk = 540000;
418 }
419
420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
421 {
422 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
423 333333 : 320000;
424
425 /*
426 * We seem to get an unstable or solid color picture at 200MHz.
427 * Not sure what's wrong. For now use 200MHz only when all pipes
428 * are off.
429 */
430 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
431 return 400000;
432 else if (min_cdclk > 266667)
433 return freq_320;
434 else if (min_cdclk > 0)
435 return 266667;
436 else
437 return 200000;
438 }
439
440 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
441 struct intel_cdclk_state *cdclk_state)
442 {
443 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
444 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
445 CCK_DISPLAY_CLOCK_CONTROL,
446 cdclk_state->vco);
447 }
448
449 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
450 {
451 unsigned int credits, default_credits;
452
453 if (IS_CHERRYVIEW(dev_priv))
454 default_credits = PFI_CREDIT(12);
455 else
456 default_credits = PFI_CREDIT(8);
457
458 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
459 /* CHV suggested value is 31 or 63 */
460 if (IS_CHERRYVIEW(dev_priv))
461 credits = PFI_CREDIT_63;
462 else
463 credits = PFI_CREDIT(15);
464 } else {
465 credits = default_credits;
466 }
467
468 /*
469 * WA - write default credits before re-programming
470 * FIXME: should we also set the resend bit here?
471 */
472 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
473 default_credits);
474
475 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
476 credits | PFI_CREDIT_RESEND);
477
478 /*
479 * FIXME is this guaranteed to clear
480 * immediately or should we poll for it?
481 */
482 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
483 }
484
485 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
486 const struct intel_cdclk_state *cdclk_state)
487 {
488 int cdclk = cdclk_state->cdclk;
489 u32 val, cmd;
490
491 /* There are cases where we can end up here with power domains
492 * off and a CDCLK frequency other than the minimum, like when
493 * issuing a modeset without actually changing any display after
494 * a system suspend. So grab the PIPE-A domain, which covers
495 * the HW blocks needed for the following programming.
496 */
497 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
498
499 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
500 cmd = 2;
501 else if (cdclk == 266667)
502 cmd = 1;
503 else
504 cmd = 0;
505
506 mutex_lock(&dev_priv->pcu_lock);
507 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
508 val &= ~DSPFREQGUAR_MASK;
509 val |= (cmd << DSPFREQGUAR_SHIFT);
510 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
511 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
512 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
513 50)) {
514 DRM_ERROR("timed out waiting for CDclk change\n");
515 }
516 mutex_unlock(&dev_priv->pcu_lock);
517
518 mutex_lock(&dev_priv->sb_lock);
519
520 if (cdclk == 400000) {
521 u32 divider;
522
523 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
524 cdclk) - 1;
525
526 /* adjust cdclk divider */
527 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
528 val &= ~CCK_FREQUENCY_VALUES;
529 val |= divider;
530 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
531
532 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
533 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
534 50))
535 DRM_ERROR("timed out waiting for CDclk change\n");
536 }
537
538 /* adjust self-refresh exit latency value */
539 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
540 val &= ~0x7f;
541
542 /*
543 * For high bandwidth configs, we set a higher latency in the bunit
544 * so that the core display fetch happens in time to avoid underruns.
545 */
546 if (cdclk == 400000)
547 val |= 4500 / 250; /* 4.5 usec */
548 else
549 val |= 3000 / 250; /* 3.0 usec */
550 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
551
552 mutex_unlock(&dev_priv->sb_lock);
553
554 intel_update_cdclk(dev_priv);
555
556 vlv_program_pfi_credits(dev_priv);
557
558 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
559 }
560
561 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
562 const struct intel_cdclk_state *cdclk_state)
563 {
564 int cdclk = cdclk_state->cdclk;
565 u32 val, cmd;
566
567 switch (cdclk) {
568 case 333333:
569 case 320000:
570 case 266667:
571 case 200000:
572 break;
573 default:
574 MISSING_CASE(cdclk);
575 return;
576 }
577
578 /* There are cases where we can end up here with power domains
579 * off and a CDCLK frequency other than the minimum, like when
580 * issuing a modeset without actually changing any display after
581 * a system suspend. So grab the PIPE-A domain, which covers
582 * the HW blocks needed for the following programming.
583 */
584 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
585
586 /*
587 * Specs are full of misinformation, but testing on actual
588 * hardware has shown that we just need to write the desired
589 * CCK divider into the Punit register.
590 */
591 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
592
593 mutex_lock(&dev_priv->pcu_lock);
594 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
595 val &= ~DSPFREQGUAR_MASK_CHV;
596 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
597 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
598 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
599 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
600 50)) {
601 DRM_ERROR("timed out waiting for CDclk change\n");
602 }
603 mutex_unlock(&dev_priv->pcu_lock);
604
605 intel_update_cdclk(dev_priv);
606
607 vlv_program_pfi_credits(dev_priv);
608
609 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
610 }
611
612 static int bdw_calc_cdclk(int min_cdclk)
613 {
614 if (min_cdclk > 540000)
615 return 675000;
616 else if (min_cdclk > 450000)
617 return 540000;
618 else if (min_cdclk > 337500)
619 return 450000;
620 else
621 return 337500;
622 }
623
624 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
625 struct intel_cdclk_state *cdclk_state)
626 {
627 uint32_t lcpll = I915_READ(LCPLL_CTL);
628 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
629
630 if (lcpll & LCPLL_CD_SOURCE_FCLK)
631 cdclk_state->cdclk = 800000;
632 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
633 cdclk_state->cdclk = 450000;
634 else if (freq == LCPLL_CLK_FREQ_450)
635 cdclk_state->cdclk = 450000;
636 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
637 cdclk_state->cdclk = 540000;
638 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
639 cdclk_state->cdclk = 337500;
640 else
641 cdclk_state->cdclk = 675000;
642 }
643
644 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
645 const struct intel_cdclk_state *cdclk_state)
646 {
647 int cdclk = cdclk_state->cdclk;
648 uint32_t val, data;
649 int ret;
650
651 if (WARN((I915_READ(LCPLL_CTL) &
652 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
653 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
654 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
655 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
656 "trying to change cdclk frequency with cdclk not enabled\n"))
657 return;
658
659 mutex_lock(&dev_priv->pcu_lock);
660 ret = sandybridge_pcode_write(dev_priv,
661 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
662 mutex_unlock(&dev_priv->pcu_lock);
663 if (ret) {
664 DRM_ERROR("failed to inform pcode about cdclk change\n");
665 return;
666 }
667
668 val = I915_READ(LCPLL_CTL);
669 val |= LCPLL_CD_SOURCE_FCLK;
670 I915_WRITE(LCPLL_CTL, val);
671
672 /*
673 * According to the spec, it should be enough to poll for this 1 us.
674 * However, extensive testing shows that this can take longer.
675 */
676 if (wait_for_us(I915_READ(LCPLL_CTL) &
677 LCPLL_CD_SOURCE_FCLK_DONE, 100))
678 DRM_ERROR("Switching to FCLK failed\n");
679
680 val = I915_READ(LCPLL_CTL);
681 val &= ~LCPLL_CLK_FREQ_MASK;
682
683 switch (cdclk) {
684 case 450000:
685 val |= LCPLL_CLK_FREQ_450;
686 data = 0;
687 break;
688 case 540000:
689 val |= LCPLL_CLK_FREQ_54O_BDW;
690 data = 1;
691 break;
692 case 337500:
693 val |= LCPLL_CLK_FREQ_337_5_BDW;
694 data = 2;
695 break;
696 case 675000:
697 val |= LCPLL_CLK_FREQ_675_BDW;
698 data = 3;
699 break;
700 default:
701 WARN(1, "invalid cdclk frequency\n");
702 return;
703 }
704
705 I915_WRITE(LCPLL_CTL, val);
706
707 val = I915_READ(LCPLL_CTL);
708 val &= ~LCPLL_CD_SOURCE_FCLK;
709 I915_WRITE(LCPLL_CTL, val);
710
711 if (wait_for_us((I915_READ(LCPLL_CTL) &
712 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
713 DRM_ERROR("Switching back to LCPLL failed\n");
714
715 mutex_lock(&dev_priv->pcu_lock);
716 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
717 mutex_unlock(&dev_priv->pcu_lock);
718
719 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
720
721 intel_update_cdclk(dev_priv);
722
723 WARN(cdclk != dev_priv->cdclk.hw.cdclk,
724 "cdclk requested %d kHz but got %d kHz\n",
725 cdclk, dev_priv->cdclk.hw.cdclk);
726 }
727
728 static int skl_calc_cdclk(int min_cdclk, int vco)
729 {
730 if (vco == 8640000) {
731 if (min_cdclk > 540000)
732 return 617143;
733 else if (min_cdclk > 432000)
734 return 540000;
735 else if (min_cdclk > 308571)
736 return 432000;
737 else
738 return 308571;
739 } else {
740 if (min_cdclk > 540000)
741 return 675000;
742 else if (min_cdclk > 450000)
743 return 540000;
744 else if (min_cdclk > 337500)
745 return 450000;
746 else
747 return 337500;
748 }
749 }
750
751 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
752 struct intel_cdclk_state *cdclk_state)
753 {
754 u32 val;
755
756 cdclk_state->ref = 24000;
757 cdclk_state->vco = 0;
758
759 val = I915_READ(LCPLL1_CTL);
760 if ((val & LCPLL_PLL_ENABLE) == 0)
761 return;
762
763 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
764 return;
765
766 val = I915_READ(DPLL_CTRL1);
767
768 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
769 DPLL_CTRL1_SSC(SKL_DPLL0) |
770 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
771 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
772 return;
773
774 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
776 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
777 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
778 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
779 cdclk_state->vco = 8100000;
780 break;
781 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
782 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
783 cdclk_state->vco = 8640000;
784 break;
785 default:
786 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
787 break;
788 }
789 }
790
791 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
792 struct intel_cdclk_state *cdclk_state)
793 {
794 u32 cdctl;
795
796 skl_dpll0_update(dev_priv, cdclk_state);
797
798 cdclk_state->cdclk = cdclk_state->ref;
799
800 if (cdclk_state->vco == 0)
801 return;
802
803 cdctl = I915_READ(CDCLK_CTL);
804
805 if (cdclk_state->vco == 8640000) {
806 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
807 case CDCLK_FREQ_450_432:
808 cdclk_state->cdclk = 432000;
809 break;
810 case CDCLK_FREQ_337_308:
811 cdclk_state->cdclk = 308571;
812 break;
813 case CDCLK_FREQ_540:
814 cdclk_state->cdclk = 540000;
815 break;
816 case CDCLK_FREQ_675_617:
817 cdclk_state->cdclk = 617143;
818 break;
819 default:
820 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
821 break;
822 }
823 } else {
824 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
825 case CDCLK_FREQ_450_432:
826 cdclk_state->cdclk = 450000;
827 break;
828 case CDCLK_FREQ_337_308:
829 cdclk_state->cdclk = 337500;
830 break;
831 case CDCLK_FREQ_540:
832 cdclk_state->cdclk = 540000;
833 break;
834 case CDCLK_FREQ_675_617:
835 cdclk_state->cdclk = 675000;
836 break;
837 default:
838 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
839 break;
840 }
841 }
842 }
843
844 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
845 static int skl_cdclk_decimal(int cdclk)
846 {
847 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
848 }
849
850 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
851 int vco)
852 {
853 bool changed = dev_priv->skl_preferred_vco_freq != vco;
854
855 dev_priv->skl_preferred_vco_freq = vco;
856
857 if (changed)
858 intel_update_max_cdclk(dev_priv);
859 }
860
861 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
862 {
863 u32 val;
864
865 WARN_ON(vco != 8100000 && vco != 8640000);
866
867 /*
868 * We always enable DPLL0 with the lowest link rate possible, but still
869 * taking into account the VCO required to operate the eDP panel at the
870 * desired frequency. The usual DP link rates operate with a VCO of
871 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
872 * The modeset code is responsible for the selection of the exact link
873 * rate later on, with the constraint of choosing a frequency that
874 * works with vco.
875 */
876 val = I915_READ(DPLL_CTRL1);
877
878 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
879 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
880 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
881 if (vco == 8640000)
882 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
883 SKL_DPLL0);
884 else
885 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
886 SKL_DPLL0);
887
888 I915_WRITE(DPLL_CTRL1, val);
889 POSTING_READ(DPLL_CTRL1);
890
891 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
892
893 if (intel_wait_for_register(dev_priv,
894 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
895 5))
896 DRM_ERROR("DPLL0 not locked\n");
897
898 dev_priv->cdclk.hw.vco = vco;
899
900 /* We'll want to keep using the current vco from now on. */
901 skl_set_preferred_cdclk_vco(dev_priv, vco);
902 }
903
904 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
905 {
906 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
907 if (intel_wait_for_register(dev_priv,
908 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
909 1))
910 DRM_ERROR("Couldn't disable DPLL0\n");
911
912 dev_priv->cdclk.hw.vco = 0;
913 }
914
915 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
916 const struct intel_cdclk_state *cdclk_state)
917 {
918 int cdclk = cdclk_state->cdclk;
919 int vco = cdclk_state->vco;
920 u32 freq_select, pcu_ack, cdclk_ctl;
921 int ret;
922
923 WARN_ON((cdclk == 24000) != (vco == 0));
924
925 mutex_lock(&dev_priv->pcu_lock);
926 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
927 SKL_CDCLK_PREPARE_FOR_CHANGE,
928 SKL_CDCLK_READY_FOR_CHANGE,
929 SKL_CDCLK_READY_FOR_CHANGE, 3);
930 mutex_unlock(&dev_priv->pcu_lock);
931 if (ret) {
932 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
933 ret);
934 return;
935 }
936
937 /* Choose frequency for this cdclk */
938 switch (cdclk) {
939 case 450000:
940 case 432000:
941 freq_select = CDCLK_FREQ_450_432;
942 pcu_ack = 1;
943 break;
944 case 540000:
945 freq_select = CDCLK_FREQ_540;
946 pcu_ack = 2;
947 break;
948 case 308571:
949 case 337500:
950 default:
951 freq_select = CDCLK_FREQ_337_308;
952 pcu_ack = 0;
953 break;
954 case 617143:
955 case 675000:
956 freq_select = CDCLK_FREQ_675_617;
957 pcu_ack = 3;
958 break;
959 }
960
961 if (dev_priv->cdclk.hw.vco != 0 &&
962 dev_priv->cdclk.hw.vco != vco)
963 skl_dpll0_disable(dev_priv);
964
965 cdclk_ctl = I915_READ(CDCLK_CTL);
966
967 if (dev_priv->cdclk.hw.vco != vco) {
968 /* Wa Display #1183: skl,kbl,cfl */
969 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
970 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
971 I915_WRITE(CDCLK_CTL, cdclk_ctl);
972 }
973
974 /* Wa Display #1183: skl,kbl,cfl */
975 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
976 I915_WRITE(CDCLK_CTL, cdclk_ctl);
977 POSTING_READ(CDCLK_CTL);
978
979 if (dev_priv->cdclk.hw.vco != vco)
980 skl_dpll0_enable(dev_priv, vco);
981
982 /* Wa Display #1183: skl,kbl,cfl */
983 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
984 I915_WRITE(CDCLK_CTL, cdclk_ctl);
985
986 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
987 I915_WRITE(CDCLK_CTL, cdclk_ctl);
988
989 /* Wa Display #1183: skl,kbl,cfl */
990 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
991 I915_WRITE(CDCLK_CTL, cdclk_ctl);
992 POSTING_READ(CDCLK_CTL);
993
994 /* inform PCU of the change */
995 mutex_lock(&dev_priv->pcu_lock);
996 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
997 mutex_unlock(&dev_priv->pcu_lock);
998
999 intel_update_cdclk(dev_priv);
1000 }
1001
1002 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1003 {
1004 uint32_t cdctl, expected;
1005
1006 /*
1007 * check if the pre-os initialized the display
1008 * There is SWF18 scratchpad register defined which is set by the
1009 * pre-os which can be used by the OS drivers to check the status
1010 */
1011 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1012 goto sanitize;
1013
1014 intel_update_cdclk(dev_priv);
1015 /* Is PLL enabled and locked ? */
1016 if (dev_priv->cdclk.hw.vco == 0 ||
1017 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1018 goto sanitize;
1019
1020 /* DPLL okay; verify the cdclock
1021 *
1022 * Noticed in some instances that the freq selection is correct but
1023 * decimal part is programmed wrong from BIOS where pre-os does not
1024 * enable display. Verify the same as well.
1025 */
1026 cdctl = I915_READ(CDCLK_CTL);
1027 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1028 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1029 if (cdctl == expected)
1030 /* All well; nothing to sanitize */
1031 return;
1032
1033 sanitize:
1034 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1035
1036 /* force cdclk programming */
1037 dev_priv->cdclk.hw.cdclk = 0;
1038 /* force full PLL disable + enable */
1039 dev_priv->cdclk.hw.vco = -1;
1040 }
1041
1042 /**
1043 * skl_init_cdclk - Initialize CDCLK on SKL
1044 * @dev_priv: i915 device
1045 *
1046 * Initialize CDCLK for SKL and derivatives. This is generally
1047 * done only during the display core initialization sequence,
1048 * after which the DMC will take care of turning CDCLK off/on
1049 * as needed.
1050 */
1051 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1052 {
1053 struct intel_cdclk_state cdclk_state;
1054
1055 skl_sanitize_cdclk(dev_priv);
1056
1057 if (dev_priv->cdclk.hw.cdclk != 0 &&
1058 dev_priv->cdclk.hw.vco != 0) {
1059 /*
1060 * Use the current vco as our initial
1061 * guess as to what the preferred vco is.
1062 */
1063 if (dev_priv->skl_preferred_vco_freq == 0)
1064 skl_set_preferred_cdclk_vco(dev_priv,
1065 dev_priv->cdclk.hw.vco);
1066 return;
1067 }
1068
1069 cdclk_state = dev_priv->cdclk.hw;
1070
1071 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1072 if (cdclk_state.vco == 0)
1073 cdclk_state.vco = 8100000;
1074 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1075
1076 skl_set_cdclk(dev_priv, &cdclk_state);
1077 }
1078
1079 /**
1080 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1081 * @dev_priv: i915 device
1082 *
1083 * Uninitialize CDCLK for SKL and derivatives. This is done only
1084 * during the display core uninitialization sequence.
1085 */
1086 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1087 {
1088 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1089
1090 cdclk_state.cdclk = cdclk_state.ref;
1091 cdclk_state.vco = 0;
1092
1093 skl_set_cdclk(dev_priv, &cdclk_state);
1094 }
1095
1096 static int bxt_calc_cdclk(int min_cdclk)
1097 {
1098 if (min_cdclk > 576000)
1099 return 624000;
1100 else if (min_cdclk > 384000)
1101 return 576000;
1102 else if (min_cdclk > 288000)
1103 return 384000;
1104 else if (min_cdclk > 144000)
1105 return 288000;
1106 else
1107 return 144000;
1108 }
1109
1110 static int glk_calc_cdclk(int min_cdclk)
1111 {
1112 if (min_cdclk > 158400)
1113 return 316800;
1114 else if (min_cdclk > 79200)
1115 return 158400;
1116 else
1117 return 79200;
1118 }
1119
1120 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1121 {
1122 int ratio;
1123
1124 if (cdclk == dev_priv->cdclk.hw.ref)
1125 return 0;
1126
1127 switch (cdclk) {
1128 default:
1129 MISSING_CASE(cdclk);
1130 case 144000:
1131 case 288000:
1132 case 384000:
1133 case 576000:
1134 ratio = 60;
1135 break;
1136 case 624000:
1137 ratio = 65;
1138 break;
1139 }
1140
1141 return dev_priv->cdclk.hw.ref * ratio;
1142 }
1143
1144 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1145 {
1146 int ratio;
1147
1148 if (cdclk == dev_priv->cdclk.hw.ref)
1149 return 0;
1150
1151 switch (cdclk) {
1152 default:
1153 MISSING_CASE(cdclk);
1154 case 79200:
1155 case 158400:
1156 case 316800:
1157 ratio = 33;
1158 break;
1159 }
1160
1161 return dev_priv->cdclk.hw.ref * ratio;
1162 }
1163
1164 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1165 struct intel_cdclk_state *cdclk_state)
1166 {
1167 u32 val;
1168
1169 cdclk_state->ref = 19200;
1170 cdclk_state->vco = 0;
1171
1172 val = I915_READ(BXT_DE_PLL_ENABLE);
1173 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1174 return;
1175
1176 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1177 return;
1178
1179 val = I915_READ(BXT_DE_PLL_CTL);
1180 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1181 }
1182
1183 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1184 struct intel_cdclk_state *cdclk_state)
1185 {
1186 u32 divider;
1187 int div;
1188
1189 bxt_de_pll_update(dev_priv, cdclk_state);
1190
1191 cdclk_state->cdclk = cdclk_state->ref;
1192
1193 if (cdclk_state->vco == 0)
1194 return;
1195
1196 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1197
1198 switch (divider) {
1199 case BXT_CDCLK_CD2X_DIV_SEL_1:
1200 div = 2;
1201 break;
1202 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1203 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1204 div = 3;
1205 break;
1206 case BXT_CDCLK_CD2X_DIV_SEL_2:
1207 div = 4;
1208 break;
1209 case BXT_CDCLK_CD2X_DIV_SEL_4:
1210 div = 8;
1211 break;
1212 default:
1213 MISSING_CASE(divider);
1214 return;
1215 }
1216
1217 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1218 }
1219
1220 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1221 {
1222 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1223
1224 /* Timeout 200us */
1225 if (intel_wait_for_register(dev_priv,
1226 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1227 1))
1228 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1229
1230 dev_priv->cdclk.hw.vco = 0;
1231 }
1232
1233 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1234 {
1235 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1236 u32 val;
1237
1238 val = I915_READ(BXT_DE_PLL_CTL);
1239 val &= ~BXT_DE_PLL_RATIO_MASK;
1240 val |= BXT_DE_PLL_RATIO(ratio);
1241 I915_WRITE(BXT_DE_PLL_CTL, val);
1242
1243 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1244
1245 /* Timeout 200us */
1246 if (intel_wait_for_register(dev_priv,
1247 BXT_DE_PLL_ENABLE,
1248 BXT_DE_PLL_LOCK,
1249 BXT_DE_PLL_LOCK,
1250 1))
1251 DRM_ERROR("timeout waiting for DE PLL lock\n");
1252
1253 dev_priv->cdclk.hw.vco = vco;
1254 }
1255
1256 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1257 const struct intel_cdclk_state *cdclk_state)
1258 {
1259 int cdclk = cdclk_state->cdclk;
1260 int vco = cdclk_state->vco;
1261 u32 val, divider;
1262 int ret;
1263
1264 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1265 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1266 case 8:
1267 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1268 break;
1269 case 4:
1270 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1271 break;
1272 case 3:
1273 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1274 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1275 break;
1276 case 2:
1277 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1278 break;
1279 default:
1280 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1281 WARN_ON(vco != 0);
1282
1283 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1284 break;
1285 }
1286
1287 mutex_lock(&dev_priv->pcu_lock);
1288 /*
1289 * Inform power controller of upcoming frequency change. BSpec
1290 * requires us to wait up to 150usec, but that leads to timeouts;
1291 * the 2ms used here is based on experiment.
1292 */
1293 ret = sandybridge_pcode_write_timeout(dev_priv,
1294 HSW_PCODE_DE_WRITE_FREQ_REQ,
1295 0x80000000, 2000);
1296 mutex_unlock(&dev_priv->pcu_lock);
1297
1298 if (ret) {
1299 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1300 ret, cdclk);
1301 return;
1302 }
1303
1304 if (dev_priv->cdclk.hw.vco != 0 &&
1305 dev_priv->cdclk.hw.vco != vco)
1306 bxt_de_pll_disable(dev_priv);
1307
1308 if (dev_priv->cdclk.hw.vco != vco)
1309 bxt_de_pll_enable(dev_priv, vco);
1310
1311 val = divider | skl_cdclk_decimal(cdclk);
1312 /*
1313 * FIXME if only the cd2x divider needs changing, it could be done
1314 * without shutting off the pipe (if only one pipe is active).
1315 */
1316 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1317 /*
1318 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1319 * enable otherwise.
1320 */
1321 if (cdclk >= 500000)
1322 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1323 I915_WRITE(CDCLK_CTL, val);
1324
1325 mutex_lock(&dev_priv->pcu_lock);
1326 /*
1327 * The timeout isn't specified, the 2ms used here is based on
1328 * experiment.
1329 * FIXME: Waiting for the request completion could be delayed until
1330 * the next PCODE request based on BSpec.
1331 */
1332 ret = sandybridge_pcode_write_timeout(dev_priv,
1333 HSW_PCODE_DE_WRITE_FREQ_REQ,
1334 DIV_ROUND_UP(cdclk, 25000), 2000);
1335 mutex_unlock(&dev_priv->pcu_lock);
1336
1337 if (ret) {
1338 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1339 ret, cdclk);
1340 return;
1341 }
1342
1343 intel_update_cdclk(dev_priv);
1344 }
1345
1346 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1347 {
1348 u32 cdctl, expected;
1349
1350 intel_update_cdclk(dev_priv);
1351
1352 if (dev_priv->cdclk.hw.vco == 0 ||
1353 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1354 goto sanitize;
1355
1356 /* DPLL okay; verify the cdclock
1357 *
1358 * Some BIOS versions leave an incorrect decimal frequency value and
1359 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1360 * so sanitize this register.
1361 */
1362 cdctl = I915_READ(CDCLK_CTL);
1363 /*
1364 * Let's ignore the pipe field, since BIOS could have configured the
1365 * dividers both synching to an active pipe, or asynchronously
1366 * (PIPE_NONE).
1367 */
1368 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1369
1370 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1371 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1372 /*
1373 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1374 * enable otherwise.
1375 */
1376 if (dev_priv->cdclk.hw.cdclk >= 500000)
1377 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1378
1379 if (cdctl == expected)
1380 /* All well; nothing to sanitize */
1381 return;
1382
1383 sanitize:
1384 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1385
1386 /* force cdclk programming */
1387 dev_priv->cdclk.hw.cdclk = 0;
1388
1389 /* force full PLL disable + enable */
1390 dev_priv->cdclk.hw.vco = -1;
1391 }
1392
1393 /**
1394 * bxt_init_cdclk - Initialize CDCLK on BXT
1395 * @dev_priv: i915 device
1396 *
1397 * Initialize CDCLK for BXT and derivatives. This is generally
1398 * done only during the display core initialization sequence,
1399 * after which the DMC will take care of turning CDCLK off/on
1400 * as needed.
1401 */
1402 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1403 {
1404 struct intel_cdclk_state cdclk_state;
1405
1406 bxt_sanitize_cdclk(dev_priv);
1407
1408 if (dev_priv->cdclk.hw.cdclk != 0 &&
1409 dev_priv->cdclk.hw.vco != 0)
1410 return;
1411
1412 cdclk_state = dev_priv->cdclk.hw;
1413
1414 /*
1415 * FIXME:
1416 * - The initial CDCLK needs to be read from VBT.
1417 * Need to make this change after VBT has changes for BXT.
1418 */
1419 if (IS_GEMINILAKE(dev_priv)) {
1420 cdclk_state.cdclk = glk_calc_cdclk(0);
1421 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1422 } else {
1423 cdclk_state.cdclk = bxt_calc_cdclk(0);
1424 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1425 }
1426
1427 bxt_set_cdclk(dev_priv, &cdclk_state);
1428 }
1429
1430 /**
1431 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1432 * @dev_priv: i915 device
1433 *
1434 * Uninitialize CDCLK for BXT and derivatives. This is done only
1435 * during the display core uninitialization sequence.
1436 */
1437 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1438 {
1439 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1440
1441 cdclk_state.cdclk = cdclk_state.ref;
1442 cdclk_state.vco = 0;
1443
1444 bxt_set_cdclk(dev_priv, &cdclk_state);
1445 }
1446
1447 static int cnl_calc_cdclk(int min_cdclk)
1448 {
1449 if (min_cdclk > 336000)
1450 return 528000;
1451 else if (min_cdclk > 168000)
1452 return 336000;
1453 else
1454 return 168000;
1455 }
1456
1457 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1458 struct intel_cdclk_state *cdclk_state)
1459 {
1460 u32 val;
1461
1462 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1463 cdclk_state->ref = 24000;
1464 else
1465 cdclk_state->ref = 19200;
1466
1467 cdclk_state->vco = 0;
1468
1469 val = I915_READ(BXT_DE_PLL_ENABLE);
1470 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1471 return;
1472
1473 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1474 return;
1475
1476 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1477 }
1478
1479 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1480 struct intel_cdclk_state *cdclk_state)
1481 {
1482 u32 divider;
1483 int div;
1484
1485 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1486
1487 cdclk_state->cdclk = cdclk_state->ref;
1488
1489 if (cdclk_state->vco == 0)
1490 return;
1491
1492 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1493
1494 switch (divider) {
1495 case BXT_CDCLK_CD2X_DIV_SEL_1:
1496 div = 2;
1497 break;
1498 case BXT_CDCLK_CD2X_DIV_SEL_2:
1499 div = 4;
1500 break;
1501 default:
1502 MISSING_CASE(divider);
1503 return;
1504 }
1505
1506 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1507 }
1508
1509 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1510 {
1511 u32 val;
1512
1513 val = I915_READ(BXT_DE_PLL_ENABLE);
1514 val &= ~BXT_DE_PLL_PLL_ENABLE;
1515 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1516
1517 /* Timeout 200us */
1518 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1519 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1520
1521 dev_priv->cdclk.hw.vco = 0;
1522 }
1523
1524 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1525 {
1526 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1527 u32 val;
1528
1529 val = CNL_CDCLK_PLL_RATIO(ratio);
1530 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1531
1532 val |= BXT_DE_PLL_PLL_ENABLE;
1533 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1534
1535 /* Timeout 200us */
1536 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1537 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1538
1539 dev_priv->cdclk.hw.vco = vco;
1540 }
1541
1542 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1543 const struct intel_cdclk_state *cdclk_state)
1544 {
1545 int cdclk = cdclk_state->cdclk;
1546 int vco = cdclk_state->vco;
1547 u32 val, divider, pcu_ack;
1548 int ret;
1549
1550 mutex_lock(&dev_priv->pcu_lock);
1551 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1552 SKL_CDCLK_PREPARE_FOR_CHANGE,
1553 SKL_CDCLK_READY_FOR_CHANGE,
1554 SKL_CDCLK_READY_FOR_CHANGE, 3);
1555 mutex_unlock(&dev_priv->pcu_lock);
1556 if (ret) {
1557 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1558 ret);
1559 return;
1560 }
1561
1562 /* cdclk = vco / 2 / div{1,2} */
1563 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1564 case 4:
1565 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1566 break;
1567 case 2:
1568 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1569 break;
1570 default:
1571 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1572 WARN_ON(vco != 0);
1573
1574 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1575 break;
1576 }
1577
1578 switch (cdclk) {
1579 case 528000:
1580 pcu_ack = 2;
1581 break;
1582 case 336000:
1583 pcu_ack = 1;
1584 break;
1585 case 168000:
1586 default:
1587 pcu_ack = 0;
1588 break;
1589 }
1590
1591 if (dev_priv->cdclk.hw.vco != 0 &&
1592 dev_priv->cdclk.hw.vco != vco)
1593 cnl_cdclk_pll_disable(dev_priv);
1594
1595 if (dev_priv->cdclk.hw.vco != vco)
1596 cnl_cdclk_pll_enable(dev_priv, vco);
1597
1598 val = divider | skl_cdclk_decimal(cdclk);
1599 /*
1600 * FIXME if only the cd2x divider needs changing, it could be done
1601 * without shutting off the pipe (if only one pipe is active).
1602 */
1603 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1604 I915_WRITE(CDCLK_CTL, val);
1605
1606 /* inform PCU of the change */
1607 mutex_lock(&dev_priv->pcu_lock);
1608 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1609 mutex_unlock(&dev_priv->pcu_lock);
1610
1611 intel_update_cdclk(dev_priv);
1612 }
1613
1614 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1615 {
1616 int ratio;
1617
1618 if (cdclk == dev_priv->cdclk.hw.ref)
1619 return 0;
1620
1621 switch (cdclk) {
1622 default:
1623 MISSING_CASE(cdclk);
1624 case 168000:
1625 case 336000:
1626 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1627 break;
1628 case 528000:
1629 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1630 break;
1631 }
1632
1633 return dev_priv->cdclk.hw.ref * ratio;
1634 }
1635
1636 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1637 {
1638 u32 cdctl, expected;
1639
1640 intel_update_cdclk(dev_priv);
1641
1642 if (dev_priv->cdclk.hw.vco == 0 ||
1643 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1644 goto sanitize;
1645
1646 /* DPLL okay; verify the cdclock
1647 *
1648 * Some BIOS versions leave an incorrect decimal frequency value and
1649 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1650 * so sanitize this register.
1651 */
1652 cdctl = I915_READ(CDCLK_CTL);
1653 /*
1654 * Let's ignore the pipe field, since BIOS could have configured the
1655 * dividers both synching to an active pipe, or asynchronously
1656 * (PIPE_NONE).
1657 */
1658 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1659
1660 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1661 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1662
1663 if (cdctl == expected)
1664 /* All well; nothing to sanitize */
1665 return;
1666
1667 sanitize:
1668 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1669
1670 /* force cdclk programming */
1671 dev_priv->cdclk.hw.cdclk = 0;
1672
1673 /* force full PLL disable + enable */
1674 dev_priv->cdclk.hw.vco = -1;
1675 }
1676
1677 /**
1678 * cnl_init_cdclk - Initialize CDCLK on CNL
1679 * @dev_priv: i915 device
1680 *
1681 * Initialize CDCLK for CNL. This is generally
1682 * done only during the display core initialization sequence,
1683 * after which the DMC will take care of turning CDCLK off/on
1684 * as needed.
1685 */
1686 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1687 {
1688 struct intel_cdclk_state cdclk_state;
1689
1690 cnl_sanitize_cdclk(dev_priv);
1691
1692 if (dev_priv->cdclk.hw.cdclk != 0 &&
1693 dev_priv->cdclk.hw.vco != 0)
1694 return;
1695
1696 cdclk_state = dev_priv->cdclk.hw;
1697
1698 cdclk_state.cdclk = cnl_calc_cdclk(0);
1699 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1700
1701 cnl_set_cdclk(dev_priv, &cdclk_state);
1702 }
1703
1704 /**
1705 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1706 * @dev_priv: i915 device
1707 *
1708 * Uninitialize CDCLK for CNL. This is done only
1709 * during the display core uninitialization sequence.
1710 */
1711 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1712 {
1713 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1714
1715 cdclk_state.cdclk = cdclk_state.ref;
1716 cdclk_state.vco = 0;
1717
1718 cnl_set_cdclk(dev_priv, &cdclk_state);
1719 }
1720
1721 /**
1722 * intel_cdclk_state_compare - Determine if two CDCLK states differ
1723 * @a: first CDCLK state
1724 * @b: second CDCLK state
1725 *
1726 * Returns:
1727 * True if the CDCLK states are identical, false if they differ.
1728 */
1729 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1730 const struct intel_cdclk_state *b)
1731 {
1732 return memcmp(a, b, sizeof(*a)) == 0;
1733 }
1734
1735 /**
1736 * intel_set_cdclk - Push the CDCLK state to the hardware
1737 * @dev_priv: i915 device
1738 * @cdclk_state: new CDCLK state
1739 *
1740 * Program the hardware based on the passed in CDCLK state,
1741 * if necessary.
1742 */
1743 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1744 const struct intel_cdclk_state *cdclk_state)
1745 {
1746 if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1747 return;
1748
1749 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1750 return;
1751
1752 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1753 cdclk_state->cdclk, cdclk_state->vco,
1754 cdclk_state->ref);
1755
1756 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1757 }
1758
1759 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1760 int pixel_rate)
1761 {
1762 if (INTEL_GEN(dev_priv) >= 10)
1763 /*
1764 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1765 * once DDI clock voltage requirements are
1766 * handled correctly.
1767 */
1768 return pixel_rate;
1769 else if (IS_GEMINILAKE(dev_priv))
1770 /*
1771 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1772 * as a temporary workaround. Use a higher cdclk instead. (Note that
1773 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1774 * cdclk.)
1775 */
1776 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1777 else if (IS_GEN9(dev_priv) ||
1778 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1779 return pixel_rate;
1780 else if (IS_CHERRYVIEW(dev_priv))
1781 return DIV_ROUND_UP(pixel_rate * 100, 95);
1782 else
1783 return DIV_ROUND_UP(pixel_rate * 100, 90);
1784 }
1785
1786 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1787 {
1788 struct drm_i915_private *dev_priv =
1789 to_i915(crtc_state->base.crtc->dev);
1790 int min_cdclk;
1791
1792 if (!crtc_state->base.enable)
1793 return 0;
1794
1795 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1796
1797 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1798 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1799 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1800
1801 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1802 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1803 * there may be audio corruption or screen corruption." This cdclk
1804 * restriction for GLK is 316.8 MHz.
1805 */
1806 if (intel_crtc_has_dp_encoder(crtc_state) &&
1807 crtc_state->has_audio &&
1808 crtc_state->port_clock >= 540000 &&
1809 crtc_state->lane_count == 4) {
1810 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1811 /* Display WA #1145: glk,cnl */
1812 min_cdclk = max(316800, min_cdclk);
1813 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1814 /* Display WA #1144: skl,bxt */
1815 min_cdclk = max(432000, min_cdclk);
1816 }
1817 }
1818
1819 /*
1820 * According to BSpec, "The CD clock frequency must be at least twice
1821 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1822 */
1823 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1824 min_cdclk = max(2 * 96000, min_cdclk);
1825
1826 if (min_cdclk > dev_priv->max_cdclk_freq) {
1827 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1828 min_cdclk, dev_priv->max_cdclk_freq);
1829 return -EINVAL;
1830 }
1831
1832 return min_cdclk;
1833 }
1834
1835 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1836 {
1837 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1838 struct drm_i915_private *dev_priv = to_i915(state->dev);
1839 struct intel_crtc *crtc;
1840 struct intel_crtc_state *crtc_state;
1841 int min_cdclk, i;
1842 enum pipe pipe;
1843
1844 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1845 sizeof(intel_state->min_cdclk));
1846
1847 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1848 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1849 if (min_cdclk < 0)
1850 return min_cdclk;
1851
1852 intel_state->min_cdclk[i] = min_cdclk;
1853 }
1854
1855 min_cdclk = intel_state->cdclk.force_min_cdclk;
1856 for_each_pipe(dev_priv, pipe)
1857 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1858
1859 return min_cdclk;
1860 }
1861
1862 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1863 {
1864 struct drm_i915_private *dev_priv = to_i915(state->dev);
1865 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1866 int min_cdclk, cdclk;
1867
1868 min_cdclk = intel_compute_min_cdclk(state);
1869 if (min_cdclk < 0)
1870 return min_cdclk;
1871
1872 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
1873
1874 intel_state->cdclk.logical.cdclk = cdclk;
1875
1876 if (!intel_state->active_crtcs) {
1877 cdclk = vlv_calc_cdclk(dev_priv,
1878 intel_state->cdclk.force_min_cdclk);
1879
1880 intel_state->cdclk.actual.cdclk = cdclk;
1881 } else {
1882 intel_state->cdclk.actual =
1883 intel_state->cdclk.logical;
1884 }
1885
1886 return 0;
1887 }
1888
1889 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1890 {
1891 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1892 int min_cdclk, cdclk;
1893
1894 min_cdclk = intel_compute_min_cdclk(state);
1895 if (min_cdclk < 0)
1896 return min_cdclk;
1897
1898 /*
1899 * FIXME should also account for plane ratio
1900 * once 64bpp pixel formats are supported.
1901 */
1902 cdclk = bdw_calc_cdclk(min_cdclk);
1903
1904 intel_state->cdclk.logical.cdclk = cdclk;
1905
1906 if (!intel_state->active_crtcs) {
1907 cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
1908
1909 intel_state->cdclk.actual.cdclk = cdclk;
1910 } else {
1911 intel_state->cdclk.actual =
1912 intel_state->cdclk.logical;
1913 }
1914
1915 return 0;
1916 }
1917
1918 static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
1919 {
1920 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
1921 struct intel_crtc *crtc;
1922 struct intel_crtc_state *crtc_state;
1923 int vco, i;
1924
1925 vco = intel_state->cdclk.logical.vco;
1926 if (!vco)
1927 vco = dev_priv->skl_preferred_vco_freq;
1928
1929 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1930 if (!crtc_state->base.enable)
1931 continue;
1932
1933 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1934 continue;
1935
1936 /*
1937 * DPLL0 VCO may need to be adjusted to get the correct
1938 * clock for eDP. This will affect cdclk as well.
1939 */
1940 switch (crtc_state->port_clock / 2) {
1941 case 108000:
1942 case 216000:
1943 vco = 8640000;
1944 break;
1945 default:
1946 vco = 8100000;
1947 break;
1948 }
1949 }
1950
1951 return vco;
1952 }
1953
1954 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1955 {
1956 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1957 int min_cdclk, cdclk, vco;
1958
1959 min_cdclk = intel_compute_min_cdclk(state);
1960 if (min_cdclk < 0)
1961 return min_cdclk;
1962
1963 vco = skl_dpll0_vco(intel_state);
1964
1965 /*
1966 * FIXME should also account for plane ratio
1967 * once 64bpp pixel formats are supported.
1968 */
1969 cdclk = skl_calc_cdclk(min_cdclk, vco);
1970
1971 intel_state->cdclk.logical.vco = vco;
1972 intel_state->cdclk.logical.cdclk = cdclk;
1973
1974 if (!intel_state->active_crtcs) {
1975 cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
1976
1977 intel_state->cdclk.actual.vco = vco;
1978 intel_state->cdclk.actual.cdclk = cdclk;
1979 } else {
1980 intel_state->cdclk.actual =
1981 intel_state->cdclk.logical;
1982 }
1983
1984 return 0;
1985 }
1986
1987 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1988 {
1989 struct drm_i915_private *dev_priv = to_i915(state->dev);
1990 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1991 int min_cdclk, cdclk, vco;
1992
1993 min_cdclk = intel_compute_min_cdclk(state);
1994 if (min_cdclk < 0)
1995 return min_cdclk;
1996
1997 if (IS_GEMINILAKE(dev_priv)) {
1998 cdclk = glk_calc_cdclk(min_cdclk);
1999 vco = glk_de_pll_vco(dev_priv, cdclk);
2000 } else {
2001 cdclk = bxt_calc_cdclk(min_cdclk);
2002 vco = bxt_de_pll_vco(dev_priv, cdclk);
2003 }
2004
2005 intel_state->cdclk.logical.vco = vco;
2006 intel_state->cdclk.logical.cdclk = cdclk;
2007
2008 if (!intel_state->active_crtcs) {
2009 if (IS_GEMINILAKE(dev_priv)) {
2010 cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2011 vco = glk_de_pll_vco(dev_priv, cdclk);
2012 } else {
2013 cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2014 vco = bxt_de_pll_vco(dev_priv, cdclk);
2015 }
2016
2017 intel_state->cdclk.actual.vco = vco;
2018 intel_state->cdclk.actual.cdclk = cdclk;
2019 } else {
2020 intel_state->cdclk.actual =
2021 intel_state->cdclk.logical;
2022 }
2023
2024 return 0;
2025 }
2026
2027 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2028 {
2029 struct drm_i915_private *dev_priv = to_i915(state->dev);
2030 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2031 int min_cdclk, cdclk, vco;
2032
2033 min_cdclk = intel_compute_min_cdclk(state);
2034 if (min_cdclk < 0)
2035 return min_cdclk;
2036
2037 cdclk = cnl_calc_cdclk(min_cdclk);
2038 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2039
2040 intel_state->cdclk.logical.vco = vco;
2041 intel_state->cdclk.logical.cdclk = cdclk;
2042
2043 if (!intel_state->active_crtcs) {
2044 cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2045 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2046
2047 intel_state->cdclk.actual.vco = vco;
2048 intel_state->cdclk.actual.cdclk = cdclk;
2049 } else {
2050 intel_state->cdclk.actual =
2051 intel_state->cdclk.logical;
2052 }
2053
2054 return 0;
2055 }
2056
2057 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2058 {
2059 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2060
2061 if (INTEL_GEN(dev_priv) >= 10)
2062 /*
2063 * FIXME: Allow '2 * max_cdclk_freq'
2064 * once DDI clock voltage requirements are
2065 * handled correctly.
2066 */
2067 return max_cdclk_freq;
2068 else if (IS_GEMINILAKE(dev_priv))
2069 /*
2070 * FIXME: Limiting to 99% as a temporary workaround. See
2071 * intel_min_cdclk() for details.
2072 */
2073 return 2 * max_cdclk_freq * 99 / 100;
2074 else if (IS_GEN9(dev_priv) ||
2075 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2076 return max_cdclk_freq;
2077 else if (IS_CHERRYVIEW(dev_priv))
2078 return max_cdclk_freq*95/100;
2079 else if (INTEL_INFO(dev_priv)->gen < 4)
2080 return 2*max_cdclk_freq*90/100;
2081 else
2082 return max_cdclk_freq*90/100;
2083 }
2084
2085 /**
2086 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2087 * @dev_priv: i915 device
2088 *
2089 * Determine the maximum CDCLK frequency the platform supports, and also
2090 * derive the maximum dot clock frequency the maximum CDCLK frequency
2091 * allows.
2092 */
2093 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2094 {
2095 if (IS_CANNONLAKE(dev_priv)) {
2096 dev_priv->max_cdclk_freq = 528000;
2097 } else if (IS_GEN9_BC(dev_priv)) {
2098 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2099 int max_cdclk, vco;
2100
2101 vco = dev_priv->skl_preferred_vco_freq;
2102 WARN_ON(vco != 8100000 && vco != 8640000);
2103
2104 /*
2105 * Use the lower (vco 8640) cdclk values as a
2106 * first guess. skl_calc_cdclk() will correct it
2107 * if the preferred vco is 8100 instead.
2108 */
2109 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2110 max_cdclk = 617143;
2111 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2112 max_cdclk = 540000;
2113 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2114 max_cdclk = 432000;
2115 else
2116 max_cdclk = 308571;
2117
2118 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2119 } else if (IS_GEMINILAKE(dev_priv)) {
2120 dev_priv->max_cdclk_freq = 316800;
2121 } else if (IS_BROXTON(dev_priv)) {
2122 dev_priv->max_cdclk_freq = 624000;
2123 } else if (IS_BROADWELL(dev_priv)) {
2124 /*
2125 * FIXME with extra cooling we can allow
2126 * 540 MHz for ULX and 675 Mhz for ULT.
2127 * How can we know if extra cooling is
2128 * available? PCI ID, VTB, something else?
2129 */
2130 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2131 dev_priv->max_cdclk_freq = 450000;
2132 else if (IS_BDW_ULX(dev_priv))
2133 dev_priv->max_cdclk_freq = 450000;
2134 else if (IS_BDW_ULT(dev_priv))
2135 dev_priv->max_cdclk_freq = 540000;
2136 else
2137 dev_priv->max_cdclk_freq = 675000;
2138 } else if (IS_CHERRYVIEW(dev_priv)) {
2139 dev_priv->max_cdclk_freq = 320000;
2140 } else if (IS_VALLEYVIEW(dev_priv)) {
2141 dev_priv->max_cdclk_freq = 400000;
2142 } else {
2143 /* otherwise assume cdclk is fixed */
2144 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2145 }
2146
2147 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2148
2149 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2150 dev_priv->max_cdclk_freq);
2151
2152 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2153 dev_priv->max_dotclk_freq);
2154 }
2155
2156 /**
2157 * intel_update_cdclk - Determine the current CDCLK frequency
2158 * @dev_priv: i915 device
2159 *
2160 * Determine the current CDCLK frequency.
2161 */
2162 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2163 {
2164 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2165
2166 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2167 dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2168 dev_priv->cdclk.hw.ref);
2169
2170 /*
2171 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2172 * Programmng [sic] note: bit[9:2] should be programmed to the number
2173 * of cdclk that generates 4MHz reference clock freq which is used to
2174 * generate GMBus clock. This will vary with the cdclk freq.
2175 */
2176 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2177 I915_WRITE(GMBUSFREQ_VLV,
2178 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2179 }
2180
2181 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2182 {
2183 u32 rawclk;
2184 int divider, fraction;
2185
2186 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2187 /* 24 MHz */
2188 divider = 24000;
2189 fraction = 0;
2190 } else {
2191 /* 19.2 MHz */
2192 divider = 19000;
2193 fraction = 200;
2194 }
2195
2196 rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2197 if (fraction)
2198 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2199 fraction) - 1);
2200
2201 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2202 return divider + fraction;
2203 }
2204
2205 static int pch_rawclk(struct drm_i915_private *dev_priv)
2206 {
2207 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2208 }
2209
2210 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2211 {
2212 /* RAWCLK_FREQ_VLV register updated from power well code */
2213 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2214 CCK_DISPLAY_REF_CLOCK_CONTROL);
2215 }
2216
2217 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2218 {
2219 uint32_t clkcfg;
2220
2221 /* hrawclock is 1/4 the FSB frequency */
2222 clkcfg = I915_READ(CLKCFG);
2223 switch (clkcfg & CLKCFG_FSB_MASK) {
2224 case CLKCFG_FSB_400:
2225 return 100000;
2226 case CLKCFG_FSB_533:
2227 return 133333;
2228 case CLKCFG_FSB_667:
2229 return 166667;
2230 case CLKCFG_FSB_800:
2231 return 200000;
2232 case CLKCFG_FSB_1067:
2233 case CLKCFG_FSB_1067_ALT:
2234 return 266667;
2235 case CLKCFG_FSB_1333:
2236 case CLKCFG_FSB_1333_ALT:
2237 return 333333;
2238 default:
2239 return 133333;
2240 }
2241 }
2242
2243 /**
2244 * intel_update_rawclk - Determine the current RAWCLK frequency
2245 * @dev_priv: i915 device
2246 *
2247 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2248 * frequency clock so this needs to done only once.
2249 */
2250 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2251 {
2252
2253 if (HAS_PCH_CNP(dev_priv))
2254 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2255 else if (HAS_PCH_SPLIT(dev_priv))
2256 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2257 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2258 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2259 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2260 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2261 else
2262 /* no rawclk on other platforms, or no need to know it */
2263 return;
2264
2265 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2266 }
2267
2268 /**
2269 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2270 * @dev_priv: i915 device
2271 */
2272 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2273 {
2274 if (IS_CHERRYVIEW(dev_priv)) {
2275 dev_priv->display.set_cdclk = chv_set_cdclk;
2276 dev_priv->display.modeset_calc_cdclk =
2277 vlv_modeset_calc_cdclk;
2278 } else if (IS_VALLEYVIEW(dev_priv)) {
2279 dev_priv->display.set_cdclk = vlv_set_cdclk;
2280 dev_priv->display.modeset_calc_cdclk =
2281 vlv_modeset_calc_cdclk;
2282 } else if (IS_BROADWELL(dev_priv)) {
2283 dev_priv->display.set_cdclk = bdw_set_cdclk;
2284 dev_priv->display.modeset_calc_cdclk =
2285 bdw_modeset_calc_cdclk;
2286 } else if (IS_GEN9_LP(dev_priv)) {
2287 dev_priv->display.set_cdclk = bxt_set_cdclk;
2288 dev_priv->display.modeset_calc_cdclk =
2289 bxt_modeset_calc_cdclk;
2290 } else if (IS_GEN9_BC(dev_priv)) {
2291 dev_priv->display.set_cdclk = skl_set_cdclk;
2292 dev_priv->display.modeset_calc_cdclk =
2293 skl_modeset_calc_cdclk;
2294 } else if (IS_CANNONLAKE(dev_priv)) {
2295 dev_priv->display.set_cdclk = cnl_set_cdclk;
2296 dev_priv->display.modeset_calc_cdclk =
2297 cnl_modeset_calc_cdclk;
2298 }
2299
2300 if (IS_CANNONLAKE(dev_priv))
2301 dev_priv->display.get_cdclk = cnl_get_cdclk;
2302 else if (IS_GEN9_BC(dev_priv))
2303 dev_priv->display.get_cdclk = skl_get_cdclk;
2304 else if (IS_GEN9_LP(dev_priv))
2305 dev_priv->display.get_cdclk = bxt_get_cdclk;
2306 else if (IS_BROADWELL(dev_priv))
2307 dev_priv->display.get_cdclk = bdw_get_cdclk;
2308 else if (IS_HASWELL(dev_priv))
2309 dev_priv->display.get_cdclk = hsw_get_cdclk;
2310 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2311 dev_priv->display.get_cdclk = vlv_get_cdclk;
2312 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2313 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2314 else if (IS_GEN5(dev_priv))
2315 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2316 else if (IS_GM45(dev_priv))
2317 dev_priv->display.get_cdclk = gm45_get_cdclk;
2318 else if (IS_G45(dev_priv))
2319 dev_priv->display.get_cdclk = g33_get_cdclk;
2320 else if (IS_I965GM(dev_priv))
2321 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2322 else if (IS_I965G(dev_priv))
2323 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2324 else if (IS_PINEVIEW(dev_priv))
2325 dev_priv->display.get_cdclk = pnv_get_cdclk;
2326 else if (IS_G33(dev_priv))
2327 dev_priv->display.get_cdclk = g33_get_cdclk;
2328 else if (IS_I945GM(dev_priv))
2329 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2330 else if (IS_I945G(dev_priv))
2331 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2332 else if (IS_I915GM(dev_priv))
2333 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2334 else if (IS_I915G(dev_priv))
2335 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2336 else if (IS_I865G(dev_priv))
2337 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2338 else if (IS_I85X(dev_priv))
2339 dev_priv->display.get_cdclk = i85x_get_cdclk;
2340 else if (IS_I845G(dev_priv))
2341 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2342 else { /* 830 */
2343 WARN(!IS_I830(dev_priv),
2344 "Unknown platform. Assuming 133 MHz CDCLK\n");
2345 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2346 }
2347 }
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