drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  53                                          enum i915_power_well_id power_well_id);
  54
  55 static struct i915_power_well *
  56 lookup_power_well(struct drm_i915_private *dev_priv,
  57                   enum i915_power_well_id power_well_id);
  58
  59 const char *
  60 intel_display_power_domain_str(enum intel_display_power_domain domain)
  61 {
  62         switch (domain) {
  63         case POWER_DOMAIN_PIPE_A:
  64                 return "PIPE_A";
  65         case POWER_DOMAIN_PIPE_B:
  66                 return "PIPE_B";
  67         case POWER_DOMAIN_PIPE_C:
  68                 return "PIPE_C";
  69         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  70                 return "PIPE_A_PANEL_FITTER";
  71         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  72                 return "PIPE_B_PANEL_FITTER";
  73         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  74                 return "PIPE_C_PANEL_FITTER";
  75         case POWER_DOMAIN_TRANSCODER_A:
  76                 return "TRANSCODER_A";
  77         case POWER_DOMAIN_TRANSCODER_B:
  78                 return "TRANSCODER_B";
  79         case POWER_DOMAIN_TRANSCODER_C:
  80                 return "TRANSCODER_C";
  81         case POWER_DOMAIN_TRANSCODER_EDP:
  82                 return "TRANSCODER_EDP";
  83         case POWER_DOMAIN_TRANSCODER_DSI_A:
  84                 return "TRANSCODER_DSI_A";
  85         case POWER_DOMAIN_TRANSCODER_DSI_C:
  86                 return "TRANSCODER_DSI_C";
  87         case POWER_DOMAIN_PORT_DDI_A_LANES:
  88                 return "PORT_DDI_A_LANES";
  89         case POWER_DOMAIN_PORT_DDI_B_LANES:
  90                 return "PORT_DDI_B_LANES";
  91         case POWER_DOMAIN_PORT_DDI_C_LANES:
  92                 return "PORT_DDI_C_LANES";
  93         case POWER_DOMAIN_PORT_DDI_D_LANES:
  94                 return "PORT_DDI_D_LANES";
  95         case POWER_DOMAIN_PORT_DDI_E_LANES:
  96                 return "PORT_DDI_E_LANES";
  97         case POWER_DOMAIN_PORT_DDI_A_IO:
  98                 return "PORT_DDI_A_IO";
  99         case POWER_DOMAIN_PORT_DDI_B_IO:
 100                 return "PORT_DDI_B_IO";
 101         case POWER_DOMAIN_PORT_DDI_C_IO:
 102                 return "PORT_DDI_C_IO";
 103         case POWER_DOMAIN_PORT_DDI_D_IO:
 104                 return "PORT_DDI_D_IO";
 105         case POWER_DOMAIN_PORT_DDI_E_IO:
 106                 return "PORT_DDI_E_IO";
 107         case POWER_DOMAIN_PORT_DSI:
 108                 return "PORT_DSI";
 109         case POWER_DOMAIN_PORT_CRT:
 110                 return "PORT_CRT";
 111         case POWER_DOMAIN_PORT_OTHER:
 112                 return "PORT_OTHER";
 113         case POWER_DOMAIN_VGA:
 114                 return "VGA";
 115         case POWER_DOMAIN_AUDIO:
 116                 return "AUDIO";
 117         case POWER_DOMAIN_PLLS:
 118                 return "PLLS";
 119         case POWER_DOMAIN_AUX_A:
 120                 return "AUX_A";
 121         case POWER_DOMAIN_AUX_B:
 122                 return "AUX_B";
 123         case POWER_DOMAIN_AUX_C:
 124                 return "AUX_C";
 125         case POWER_DOMAIN_AUX_D:
 126                 return "AUX_D";
 127         case POWER_DOMAIN_GMBUS:
 128                 return "GMBUS";
 129         case POWER_DOMAIN_INIT:
 130                 return "INIT";
 131         case POWER_DOMAIN_MODESET:
 132                 return "MODESET";
 133         default:
 134                 MISSING_CASE(domain);
 135                 return "?";
 136         }
 137 }
 138
 139 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 140                                     struct i915_power_well *power_well)
 141 {
 142         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 143         power_well->ops->enable(dev_priv, power_well);
 144         power_well->hw_enabled = true;
 145 }
 146
 147 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 148                                      struct i915_power_well *power_well)
 149 {
 150         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 151         power_well->hw_enabled = false;
 152         power_well->ops->disable(dev_priv, power_well);
 153 }
 154
 155 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 156                                  struct i915_power_well *power_well)
 157 {
 158         if (!power_well->count++)
 159                 intel_power_well_enable(dev_priv, power_well);
 160 }
 161
 162 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 163                                  struct i915_power_well *power_well)
 164 {
 165         WARN(!power_well->count, "Use count on power well %s is already zero",
 166              power_well->name);
 167
 168         if (!--power_well->count)
 169                 intel_power_well_disable(dev_priv, power_well);
 170 }
 171
 172 /*
 173  * We should only use the power well if we explicitly asked the hardware to
 174  * enable it, so check if it's enabled and also check if we've requested it to
 175  * be enabled.
 176  */
 177 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 178                                    struct i915_power_well *power_well)
 179 {
 180         enum i915_power_well_id id = power_well->id;
 181         u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
 182
 183         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_well *power_well;
 202         bool is_enabled;
 203
 204         if (dev_priv->pm.suspended)
 205                 return false;
 206
 207         is_enabled = true;
 208
 209         for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
 210                 if (power_well->always_on)
 211                         continue;
 212
 213                 if (!power_well->hw_enabled) {
 214                         is_enabled = false;
 215                         break;
 216                 }
 217         }
 218
 219         return is_enabled;
 220 }
 221
 222 /**
 223  * intel_display_power_is_enabled - check for a power domain
 224  * @dev_priv: i915 device instance
 225  * @domain: power domain to check
 226  *
 227  * This function can be used to check the hw power domain state. It is mostly
 228  * used in hardware state readout functions. Everywhere else code should rely
 229  * upon explicit power domain reference counting to ensure that the hardware
 230  * block is powered up before accessing it.
 231  *
 232  * Callers must hold the relevant modesetting locks to ensure that concurrent
 233  * threads can't disable the power well while the caller tries to read a few
 234  * registers.
 235  *
 236  * Returns:
 237  * True when the power domain is enabled, false otherwise.
 238  */
 239 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 240                                     enum intel_display_power_domain domain)
 241 {
 242         struct i915_power_domains *power_domains;
 243         bool ret;
 244
 245         power_domains = &dev_priv->power_domains;
 246
 247         mutex_lock(&power_domains->lock);
 248         ret = __intel_display_power_is_enabled(dev_priv, domain);
 249         mutex_unlock(&power_domains->lock);
 250
 251         return ret;
 252 }
 253
 254 /**
 255  * intel_display_set_init_power - set the initial power domain state
 256  * @dev_priv: i915 device instance
 257  * @enable: whether to enable or disable the initial power domain state
 258  *
 259  * For simplicity our driver load/unload and system suspend/resume code assumes
 260  * that all power domains are always enabled. This functions controls the state
 261  * of this little hack. While the initial power domain state is enabled runtime
 262  * pm is effectively disabled.
 263  */
 264 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 265                                   bool enable)
 266 {
 267         if (dev_priv->power_domains.init_power_on == enable)
 268                 return;
 269
 270         if (enable)
 271                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 272         else
 273                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 274
 275         dev_priv->power_domains.init_power_on = enable;
 276 }
 277
 278 /*
 279  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 280  * when not needed anymore. We have 4 registers that can request the power well
 281  * to be enabled, and it will only be disabled if none of the registers is
 282  * requesting it to be enabled.
 283  */
 284 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
 285                                        u8 irq_pipe_mask, bool has_vga)
 286 {
 287         struct pci_dev *pdev = dev_priv->drm.pdev;
 288
 289         /*
 290          * After we re-enable the power well, if we touch VGA register 0x3d5
 291          * we'll get unclaimed register interrupts. This stops after we write
 292          * anything to the VGA MSR register. The vgacon module uses this
 293          * register all the time, so if we unbind our driver and, as a
 294          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 295          * console_unlock(). So make here we touch the VGA MSR register, making
 296          * sure vgacon can keep working normally without triggering interrupts
 297          * and error messages.
 298          */
 299         if (has_vga) {
 300                 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
 301                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 302                 vga_put(pdev, VGA_RSRC_LEGACY_IO);
 303         }
 304
 305         if (irq_pipe_mask)
 306                 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
 307 }
 308
 309 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
 310                                        u8 irq_pipe_mask)
 311 {
 312         if (irq_pipe_mask)
 313                 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
 314 }
 315
 316 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 317                                        struct i915_power_well *power_well)
 318 {
 319         struct pci_dev *pdev = dev_priv->drm.pdev;
 320
 321         /*
 322          * After we re-enable the power well, if we touch VGA register 0x3d5
 323          * we'll get unclaimed register interrupts. This stops after we write
 324          * anything to the VGA MSR register. The vgacon module uses this
 325          * register all the time, so if we unbind our driver and, as a
 326          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 327          * console_unlock(). So make here we touch the VGA MSR register, making
 328          * sure vgacon can keep working normally without triggering interrupts
 329          * and error messages.
 330          */
 331         if (power_well->id == SKL_DISP_PW_2) {
 332                 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
 333                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 334                 vga_put(pdev, VGA_RSRC_LEGACY_IO);
 335
 336                 gen8_irq_power_well_post_enable(dev_priv,
 337                                                 1 << PIPE_C | 1 << PIPE_B);
 338         }
 339 }
 340
 341 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 342                                        struct i915_power_well *power_well)
 343 {
 344         if (power_well->id == SKL_DISP_PW_2)
 345                 gen8_irq_power_well_pre_disable(dev_priv,
 346                                                 1 << PIPE_C | 1 << PIPE_B);
 347 }
 348
 349 static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
 350                                             struct i915_power_well *power_well)
 351 {
 352         enum i915_power_well_id id = power_well->id;
 353
 354         /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
 355         WARN_ON(intel_wait_for_register(dev_priv,
 356                                         HSW_PWR_WELL_DRIVER,
 357                                         HSW_PWR_WELL_CTL_STATE(id),
 358                                         HSW_PWR_WELL_CTL_STATE(id),
 359                                         1));
 360 }
 361
 362 static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv,
 363                                       enum i915_power_well_id id)
 364 {
 365         u32 req_mask = HSW_PWR_WELL_CTL_REQ(id);
 366         u32 ret;
 367
 368         ret = I915_READ(HSW_PWR_WELL_BIOS) & req_mask ? 1 : 0;
 369         ret |= I915_READ(HSW_PWR_WELL_DRIVER) & req_mask ? 2 : 0;
 370         ret |= I915_READ(HSW_PWR_WELL_KVMR) & req_mask ? 4 : 0;
 371         ret |= I915_READ(HSW_PWR_WELL_DEBUG) & req_mask ? 8 : 0;
 372
 373         return ret;
 374 }
 375
 376 static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
 377                                              struct i915_power_well *power_well)
 378 {
 379         enum i915_power_well_id id = power_well->id;
 380         bool disabled;
 381         u32 reqs;
 382
 383         /*
 384          * Bspec doesn't require waiting for PWs to get disabled, but still do
 385          * this for paranoia. The known cases where a PW will be forced on:
 386          * - a KVMR request on any power well via the KVMR request register
 387          * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
 388          *   DEBUG request registers
 389          * Skip the wait in case any of the request bits are set and print a
 390          * diagnostic message.
 391          */
 392         wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) &
 393                                HSW_PWR_WELL_CTL_STATE(id))) ||
 394                  (reqs = gen9_power_well_requesters(dev_priv, id)), 1);
 395         if (disabled)
 396                 return;
 397
 398         DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
 399                       power_well->name,
 400                       !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
 401 }
 402
 403 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 404                                   struct i915_power_well *power_well)
 405 {
 406         enum i915_power_well_id id = power_well->id;
 407         u32 val;
 408
 409         val = I915_READ(HSW_PWR_WELL_DRIVER);
 410         I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id));
 411
 412         if (intel_wait_for_register(dev_priv,
 413                                     HSW_PWR_WELL_DRIVER,
 414                                     HSW_PWR_WELL_CTL_STATE(id),
 415                                     HSW_PWR_WELL_CTL_STATE(id),
 416                                     20))
 417                 DRM_ERROR("Timeout enabling power well\n");
 418
 419         hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
 420                                    power_well->hsw.has_vga);
 421 }
 422
 423 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 424                                    struct i915_power_well *power_well)
 425 {
 426         enum i915_power_well_id id = power_well->id;
 427         u32 val;
 428
 429         hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
 430
 431         val = I915_READ(HSW_PWR_WELL_DRIVER);
 432         I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
 433         POSTING_READ(HSW_PWR_WELL_DRIVER);
 434 }
 435
 436 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 437         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
 438         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
 439         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
 440         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
 441         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
 442         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
 443         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
 444         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
 445         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
 446         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
 447         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
 448         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
 449         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 450         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
 451         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
 452         BIT_ULL(POWER_DOMAIN_VGA) |                             \
 453         BIT_ULL(POWER_DOMAIN_INIT))
 454 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (          \
 455         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
 456         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
 457         BIT_ULL(POWER_DOMAIN_INIT))
 458 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS (            \
 459         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
 460         BIT_ULL(POWER_DOMAIN_INIT))
 461 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS (            \
 462         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
 463         BIT_ULL(POWER_DOMAIN_INIT))
 464 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS (            \
 465         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
 466         BIT_ULL(POWER_DOMAIN_INIT))
 467 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 468         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 469         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
 470         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 471         BIT_ULL(POWER_DOMAIN_INIT))
 472
 473 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 474         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
 475         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
 476         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
 477         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
 478         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
 479         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
 480         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
 481         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
 482         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
 483         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
 484         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 485         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
 486         BIT_ULL(POWER_DOMAIN_VGA) |                             \
 487         BIT_ULL(POWER_DOMAIN_GMBUS) |                   \
 488         BIT_ULL(POWER_DOMAIN_INIT))
 489 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 490         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 491         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
 492         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 493         BIT_ULL(POWER_DOMAIN_INIT))
 494 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 495         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
 496         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 497         BIT_ULL(POWER_DOMAIN_INIT))
 498 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 499         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
 500         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
 501         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
 502         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 503         BIT_ULL(POWER_DOMAIN_INIT))
 504
 505 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 506         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
 507         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
 508         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
 509         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
 510         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
 511         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
 512         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
 513         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
 514         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
 515         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
 516         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 517         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
 518         BIT_ULL(POWER_DOMAIN_VGA) |                             \
 519         BIT_ULL(POWER_DOMAIN_INIT))
 520 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS (            \
 521         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
 522 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS (            \
 523         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
 524 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS (            \
 525         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
 526 #define GLK_DPIO_CMN_A_POWER_DOMAINS (                  \
 527         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) |                \
 528         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 529         BIT_ULL(POWER_DOMAIN_INIT))
 530 #define GLK_DPIO_CMN_B_POWER_DOMAINS (                  \
 531         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
 532         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
 533         BIT_ULL(POWER_DOMAIN_INIT))
 534 #define GLK_DPIO_CMN_C_POWER_DOMAINS (                  \
 535         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
 536         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 537         BIT_ULL(POWER_DOMAIN_INIT))
 538 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS (               \
 539         BIT_ULL(POWER_DOMAIN_AUX_A) |           \
 540         BIT_ULL(POWER_DOMAIN_INIT))
 541 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS (               \
 542         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
 543         BIT_ULL(POWER_DOMAIN_INIT))
 544 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS (               \
 545         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
 546         BIT_ULL(POWER_DOMAIN_INIT))
 547 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 548         GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 549         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
 550         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 551         BIT_ULL(POWER_DOMAIN_INIT))
 552
 553 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 554         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
 555         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
 556         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
 557         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
 558         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
 559         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
 560         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
 561         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
 562         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
 563         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
 564         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |                \
 565         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
 566         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 567         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
 568         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
 569         BIT_ULL(POWER_DOMAIN_VGA) |                             \
 570         BIT_ULL(POWER_DOMAIN_INIT))
 571 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (            \
 572         BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |           \
 573         BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
 574         BIT_ULL(POWER_DOMAIN_INIT))
 575 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (            \
 576         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
 577         BIT_ULL(POWER_DOMAIN_INIT))
 578 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (            \
 579         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
 580         BIT_ULL(POWER_DOMAIN_INIT))
 581 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (            \
 582         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
 583         BIT_ULL(POWER_DOMAIN_INIT))
 584 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS (               \
 585         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 586         BIT_ULL(POWER_DOMAIN_INIT))
 587 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS (               \
 588         BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
 589         BIT_ULL(POWER_DOMAIN_INIT))
 590 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS (               \
 591         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
 592         BIT_ULL(POWER_DOMAIN_INIT))
 593 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS (               \
 594         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
 595         BIT_ULL(POWER_DOMAIN_INIT))
 596 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 597         CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 598         BIT_ULL(POWER_DOMAIN_MODESET) |                 \
 599         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
 600         BIT_ULL(POWER_DOMAIN_INIT))
 601
 602 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 603 {
 604         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 605                   "DC9 already programmed to be enabled.\n");
 606         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 607                   "DC5 still not disabled to enable DC9.\n");
 608         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) &
 609                   HSW_PWR_WELL_CTL_REQ(SKL_DISP_PW_2),
 610                   "Power well 2 on.\n");
 611         WARN_ONCE(intel_irqs_enabled(dev_priv),
 612                   "Interrupts not disabled yet.\n");
 613
 614          /*
 615           * TODO: check for the following to verify the conditions to enter DC9
 616           * state are satisfied:
 617           * 1] Check relevant display engine registers to verify if mode set
 618           * disable sequence was followed.
 619           * 2] Check if display uninitialize sequence is initialized.
 620           */
 621 }
 622
 623 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 624 {
 625         WARN_ONCE(intel_irqs_enabled(dev_priv),
 626                   "Interrupts not disabled yet.\n");
 627         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 628                   "DC5 still not disabled.\n");
 629
 630          /*
 631           * TODO: check for the following to verify DC9 state was indeed
 632           * entered before programming to disable it:
 633           * 1] Check relevant display engine registers to verify if mode
 634           *  set disable sequence was followed.
 635           * 2] Check if display uninitialize sequence is initialized.
 636           */
 637 }
 638
 639 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 640                                 u32 state)
 641 {
 642         int rewrites = 0;
 643         int rereads = 0;
 644         u32 v;
 645
 646         I915_WRITE(DC_STATE_EN, state);
 647
 648         /* It has been observed that disabling the dc6 state sometimes
 649          * doesn't stick and dmc keeps returning old value. Make sure
 650          * the write really sticks enough times and also force rewrite until
 651          * we are confident that state is exactly what we want.
 652          */
 653         do  {
 654                 v = I915_READ(DC_STATE_EN);
 655
 656                 if (v != state) {
 657                         I915_WRITE(DC_STATE_EN, state);
 658                         rewrites++;
 659                         rereads = 0;
 660                 } else if (rereads++ > 5) {
 661                         break;
 662                 }
 663
 664         } while (rewrites < 100);
 665
 666         if (v != state)
 667                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 668                           state, v);
 669
 670         /* Most of the times we need one retry, avoid spam */
 671         if (rewrites > 1)
 672                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 673                               state, rewrites);
 674 }
 675
 676 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 677 {
 678         u32 mask;
 679
 680         mask = DC_STATE_EN_UPTO_DC5;
 681         if (IS_GEN9_LP(dev_priv))
 682                 mask |= DC_STATE_EN_DC9;
 683         else
 684                 mask |= DC_STATE_EN_UPTO_DC6;
 685
 686         return mask;
 687 }
 688
 689 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 690 {
 691         u32 val;
 692
 693         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 694
 695         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 696                       dev_priv->csr.dc_state, val);
 697         dev_priv->csr.dc_state = val;
 698 }
 699
 700 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 701 {
 702         uint32_t val;
 703         uint32_t mask;
 704
 705         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 706                 state &= dev_priv->csr.allowed_dc_mask;
 707
 708         val = I915_READ(DC_STATE_EN);
 709         mask = gen9_dc_mask(dev_priv);
 710         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 711                       val & mask, state);
 712
 713         /* Check if DMC is ignoring our DC state requests */
 714         if ((val & mask) != dev_priv->csr.dc_state)
 715                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 716                           dev_priv->csr.dc_state, val & mask);
 717
 718         val &= ~mask;
 719         val |= state;
 720
 721         gen9_write_dc_state(dev_priv, val);
 722
 723         dev_priv->csr.dc_state = val & mask;
 724 }
 725
 726 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 727 {
 728         assert_can_enable_dc9(dev_priv);
 729
 730         DRM_DEBUG_KMS("Enabling DC9\n");
 731
 732         intel_power_sequencer_reset(dev_priv);
 733         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 734 }
 735
 736 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 737 {
 738         assert_can_disable_dc9(dev_priv);
 739
 740         DRM_DEBUG_KMS("Disabling DC9\n");
 741
 742         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 743
 744         intel_pps_unlock_regs_wa(dev_priv);
 745 }
 746
 747 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 748 {
 749         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 750                   "CSR program storage start is NULL\n");
 751         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 752         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 753 }
 754
 755 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 756 {
 757         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 758                                         SKL_DISP_PW_2);
 759
 760         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 761
 762         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 763                   "DC5 already programmed to be enabled.\n");
 764         assert_rpm_wakelock_held(dev_priv);
 765
 766         assert_csr_loaded(dev_priv);
 767 }
 768
 769 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 770 {
 771         assert_can_enable_dc5(dev_priv);
 772
 773         DRM_DEBUG_KMS("Enabling DC5\n");
 774
 775         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 776 }
 777
 778 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 779 {
 780         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 781                   "Backlight is not disabled.\n");
 782         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 783                   "DC6 already programmed to be enabled.\n");
 784
 785         assert_csr_loaded(dev_priv);
 786 }
 787
 788 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 789 {
 790         assert_can_enable_dc6(dev_priv);
 791
 792         DRM_DEBUG_KMS("Enabling DC6\n");
 793
 794         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 795
 796 }
 797
 798 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 799 {
 800         DRM_DEBUG_KMS("Disabling DC6\n");
 801
 802         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 803 }
 804
 805 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 806                                struct i915_power_well *power_well, bool enable)
 807 {
 808         uint32_t tmp, fuse_status;
 809         uint32_t req_mask, state_mask;
 810         bool check_fuse_status = false;
 811
 812         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 813         fuse_status = I915_READ(SKL_FUSE_STATUS);
 814
 815         switch (power_well->id) {
 816         case SKL_DISP_PW_1:
 817                 if (intel_wait_for_register(dev_priv,
 818                                             SKL_FUSE_STATUS,
 819                                             SKL_FUSE_PG0_DIST_STATUS,
 820                                             SKL_FUSE_PG0_DIST_STATUS,
 821                                             1)) {
 822                         DRM_ERROR("PG0 not enabled\n");
 823                         return;
 824                 }
 825                 break;
 826         case SKL_DISP_PW_2:
 827                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 828                         DRM_ERROR("PG1 in disabled state\n");
 829                         return;
 830                 }
 831                 break;
 832         case SKL_DISP_PW_MISC_IO:
 833         case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
 834         case SKL_DISP_PW_DDI_B:
 835         case SKL_DISP_PW_DDI_C:
 836         case SKL_DISP_PW_DDI_D:
 837         case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
 838         case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
 839         case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
 840         case CNL_DISP_PW_AUX_D:
 841                 break;
 842         default:
 843                 WARN(1, "Unknown power well %u\n", power_well->id);
 844                 return;
 845         }
 846
 847         req_mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
 848         state_mask = HSW_PWR_WELL_CTL_STATE(power_well->id);
 849
 850         if (!enable)
 851                 skl_power_well_pre_disable(dev_priv, power_well);
 852
 853         if (enable) {
 854                 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 855
 856                 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 857                 check_fuse_status = true;
 858
 859                 gen9_wait_for_power_well_enable(dev_priv, power_well);
 860         } else {
 861                 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 862                 POSTING_READ(HSW_PWR_WELL_DRIVER);
 863                 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 864
 865                 gen9_wait_for_power_well_disable(dev_priv, power_well);
 866         }
 867
 868         if (check_fuse_status) {
 869                 if (power_well->id == SKL_DISP_PW_1) {
 870                         if (intel_wait_for_register(dev_priv,
 871                                                     SKL_FUSE_STATUS,
 872                                                     SKL_FUSE_PG1_DIST_STATUS,
 873                                                     SKL_FUSE_PG1_DIST_STATUS,
 874                                                     1))
 875                                 DRM_ERROR("PG1 distributing status timeout\n");
 876                 } else if (power_well->id == SKL_DISP_PW_2) {
 877                         if (intel_wait_for_register(dev_priv,
 878                                                     SKL_FUSE_STATUS,
 879                                                     SKL_FUSE_PG2_DIST_STATUS,
 880                                                     SKL_FUSE_PG2_DIST_STATUS,
 881                                                     1))
 882                                 DRM_ERROR("PG2 distributing status timeout\n");
 883                 }
 884         }
 885
 886         if (enable)
 887                 skl_power_well_post_enable(dev_priv, power_well);
 888 }
 889
 890 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 891                                    struct i915_power_well *power_well)
 892 {
 893         enum i915_power_well_id id = power_well->id;
 894         u32 mask = HSW_PWR_WELL_CTL_REQ(id);
 895         u32 bios_req = I915_READ(HSW_PWR_WELL_BIOS);
 896
 897         /* Take over the request bit if set by BIOS. */
 898         if (bios_req & mask) {
 899                 u32 drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
 900
 901                 if (!(drv_req & mask))
 902                         I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
 903                 I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
 904         }
 905 }
 906
 907 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 908                                         struct i915_power_well *power_well)
 909 {
 910         uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id) |
 911                         HSW_PWR_WELL_CTL_STATE(power_well->id);
 912
 913         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 914 }
 915
 916 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 917                                 struct i915_power_well *power_well)
 918 {
 919         uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id);
 920         uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
 921
 922         /* Take over the request bit if set by BIOS. */
 923         if (bios_req & mask) {
 924                 uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
 925
 926                 if (!(drv_req & mask))
 927                         I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
 928                 I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
 929         }
 930 }
 931
 932 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 933                                 struct i915_power_well *power_well)
 934 {
 935         skl_set_power_well(dev_priv, power_well, true);
 936 }
 937
 938 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 939                                 struct i915_power_well *power_well)
 940 {
 941         skl_set_power_well(dev_priv, power_well, false);
 942 }
 943
 944 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 945                                            struct i915_power_well *power_well)
 946 {
 947         bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
 948 }
 949
 950 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 951                                             struct i915_power_well *power_well)
 952 {
 953         bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
 954 }
 955
 956 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 957                                             struct i915_power_well *power_well)
 958 {
 959         return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy);
 960 }
 961
 962 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 963 {
 964         struct i915_power_well *power_well;
 965
 966         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 967         if (power_well->count > 0)
 968                 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
 969
 970         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 971         if (power_well->count > 0)
 972                 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
 973
 974         if (IS_GEMINILAKE(dev_priv)) {
 975                 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
 976                 if (power_well->count > 0)
 977                         bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
 978         }
 979 }
 980
 981 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 982                                            struct i915_power_well *power_well)
 983 {
 984         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 985 }
 986
 987 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 988 {
 989         u32 tmp = I915_READ(DBUF_CTL);
 990
 991         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 992              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 993              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 994 }
 995
 996 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 997                                           struct i915_power_well *power_well)
 998 {
 999         struct intel_cdclk_state cdclk_state = {};
1000
1001         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1002
1003         dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
1004         WARN_ON(!intel_cdclk_state_compare(&dev_priv->cdclk.hw, &cdclk_state));
1005
1006         gen9_assert_dbuf_enabled(dev_priv);
1007
1008         if (IS_GEN9_LP(dev_priv))
1009                 bxt_verify_ddi_phy_power_wells(dev_priv);
1010 }
1011
1012 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
1013                                            struct i915_power_well *power_well)
1014 {
1015         if (!dev_priv->csr.dmc_payload)
1016                 return;
1017
1018         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
1019                 skl_enable_dc6(dev_priv);
1020         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
1021                 gen9_enable_dc5(dev_priv);
1022 }
1023
1024 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
1025                                          struct i915_power_well *power_well)
1026 {
1027 }
1028
1029 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
1030                                            struct i915_power_well *power_well)
1031 {
1032 }
1033
1034 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
1035                                              struct i915_power_well *power_well)
1036 {
1037         return true;
1038 }
1039
1040 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
1041                                          struct i915_power_well *power_well)
1042 {
1043         if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
1044                 i830_enable_pipe(dev_priv, PIPE_A);
1045         if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
1046                 i830_enable_pipe(dev_priv, PIPE_B);
1047 }
1048
1049 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
1050                                           struct i915_power_well *power_well)
1051 {
1052         i830_disable_pipe(dev_priv, PIPE_B);
1053         i830_disable_pipe(dev_priv, PIPE_A);
1054 }
1055
1056 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
1057                                           struct i915_power_well *power_well)
1058 {
1059         return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
1060                 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1061 }
1062
1063 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
1064                                           struct i915_power_well *power_well)
1065 {
1066         if (power_well->count > 0)
1067                 i830_pipes_power_well_enable(dev_priv, power_well);
1068         else
1069                 i830_pipes_power_well_disable(dev_priv, power_well);
1070 }
1071
1072 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
1073                                struct i915_power_well *power_well, bool enable)
1074 {
1075         enum i915_power_well_id power_well_id = power_well->id;
1076         u32 mask;
1077         u32 state;
1078         u32 ctrl;
1079
1080         mask = PUNIT_PWRGT_MASK(power_well_id);
1081         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
1082                          PUNIT_PWRGT_PWR_GATE(power_well_id);
1083
1084         mutex_lock(&dev_priv->rps.hw_lock);
1085
1086 #define COND \
1087         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1088
1089         if (COND)
1090                 goto out;
1091
1092         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
1093         ctrl &= ~mask;
1094         ctrl |= state;
1095         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
1096
1097         if (wait_for(COND, 100))
1098                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1099                           state,
1100                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1101
1102 #undef COND
1103
1104 out:
1105         mutex_unlock(&dev_priv->rps.hw_lock);
1106 }
1107
1108 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1109                                   struct i915_power_well *power_well)
1110 {
1111         vlv_set_power_well(dev_priv, power_well, true);
1112 }
1113
1114 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1115                                    struct i915_power_well *power_well)
1116 {
1117         vlv_set_power_well(dev_priv, power_well, false);
1118 }
1119
1120 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1121                                    struct i915_power_well *power_well)
1122 {
1123         enum i915_power_well_id power_well_id = power_well->id;
1124         bool enabled = false;
1125         u32 mask;
1126         u32 state;
1127         u32 ctrl;
1128
1129         mask = PUNIT_PWRGT_MASK(power_well_id);
1130         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1131
1132         mutex_lock(&dev_priv->rps.hw_lock);
1133
1134         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1135         /*
1136          * We only ever set the power-on and power-gate states, anything
1137          * else is unexpected.
1138          */
1139         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1140                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1141         if (state == ctrl)
1142                 enabled = true;
1143
1144         /*
1145          * A transient state at this point would mean some unexpected party
1146          * is poking at the power controls too.
1147          */
1148         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1149         WARN_ON(ctrl != state);
1150
1151         mutex_unlock(&dev_priv->rps.hw_lock);
1152
1153         return enabled;
1154 }
1155
1156 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1157 {
1158         u32 val;
1159
1160         /*
1161          * On driver load, a pipe may be active and driving a DSI display.
1162          * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1163          * (and never recovering) in this case. intel_dsi_post_disable() will
1164          * clear it when we turn off the display.
1165          */
1166         val = I915_READ(DSPCLK_GATE_D);
1167         val &= DPOUNIT_CLOCK_GATE_DISABLE;
1168         val |= VRHUNIT_CLOCK_GATE_DISABLE;
1169         I915_WRITE(DSPCLK_GATE_D, val);
1170
1171         /*
1172          * Disable trickle feed and enable pnd deadline calculation
1173          */
1174         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1175         I915_WRITE(CBR1_VLV, 0);
1176
1177         WARN_ON(dev_priv->rawclk_freq == 0);
1178
1179         I915_WRITE(RAWCLK_FREQ_VLV,
1180                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1181 }
1182
1183 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1184 {
1185         struct intel_encoder *encoder;
1186         enum pipe pipe;
1187
1188         /*
1189          * Enable the CRI clock source so we can get at the
1190          * display and the reference clock for VGA
1191          * hotplug / manual detection. Supposedly DSI also
1192          * needs the ref clock up and running.
1193          *
1194          * CHV DPLL B/C have some issues if VGA mode is enabled.
1195          */
1196         for_each_pipe(dev_priv, pipe) {
1197                 u32 val = I915_READ(DPLL(pipe));
1198
1199                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1200                 if (pipe != PIPE_A)
1201                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1202
1203                 I915_WRITE(DPLL(pipe), val);
1204         }
1205
1206         vlv_init_display_clock_gating(dev_priv);
1207
1208         spin_lock_irq(&dev_priv->irq_lock);
1209         valleyview_enable_display_irqs(dev_priv);
1210         spin_unlock_irq(&dev_priv->irq_lock);
1211
1212         /*
1213          * During driver initialization/resume we can avoid restoring the
1214          * part of the HW/SW state that will be inited anyway explicitly.
1215          */
1216         if (dev_priv->power_domains.initializing)
1217                 return;
1218
1219         intel_hpd_init(dev_priv);
1220
1221         /* Re-enable the ADPA, if we have one */
1222         for_each_intel_encoder(&dev_priv->drm, encoder) {
1223                 if (encoder->type == INTEL_OUTPUT_ANALOG)
1224                         intel_crt_reset(&encoder->base);
1225         }
1226
1227         i915_redisable_vga_power_on(dev_priv);
1228
1229         intel_pps_unlock_regs_wa(dev_priv);
1230 }
1231
1232 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1233 {
1234         spin_lock_irq(&dev_priv->irq_lock);
1235         valleyview_disable_display_irqs(dev_priv);
1236         spin_unlock_irq(&dev_priv->irq_lock);
1237
1238         /* make sure we're done processing display irqs */
1239         synchronize_irq(dev_priv->drm.irq);
1240
1241         intel_power_sequencer_reset(dev_priv);
1242
1243         /* Prevent us from re-enabling polling on accident in late suspend */
1244         if (!dev_priv->drm.dev->power.is_suspended)
1245                 intel_hpd_poll_init(dev_priv);
1246 }
1247
1248 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1249                                           struct i915_power_well *power_well)
1250 {
1251         WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
1252
1253         vlv_set_power_well(dev_priv, power_well, true);
1254
1255         vlv_display_power_well_init(dev_priv);
1256 }
1257
1258 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1259                                            struct i915_power_well *power_well)
1260 {
1261         WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
1262
1263         vlv_display_power_well_deinit(dev_priv);
1264
1265         vlv_set_power_well(dev_priv, power_well, false);
1266 }
1267
1268 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1269                                            struct i915_power_well *power_well)
1270 {
1271         WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
1272
1273         /* since ref/cri clock was enabled */
1274         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1275
1276         vlv_set_power_well(dev_priv, power_well, true);
1277
1278         /*
1279          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1280          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1281          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1282          *   b. The other bits such as sfr settings / modesel may all
1283          *      be set to 0.
1284          *
1285          * This should only be done on init and resume from S3 with
1286          * both PLLs disabled, or we risk losing DPIO and PLL
1287          * synchronization.
1288          */
1289         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1290 }
1291
1292 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1293                                             struct i915_power_well *power_well)
1294 {
1295         enum pipe pipe;
1296
1297         WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
1298
1299         for_each_pipe(dev_priv, pipe)
1300                 assert_pll_disabled(dev_priv, pipe);
1301
1302         /* Assert common reset */
1303         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1304
1305         vlv_set_power_well(dev_priv, power_well, false);
1306 }
1307
1308 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
1309
1310 static struct i915_power_well *
1311 lookup_power_well(struct drm_i915_private *dev_priv,
1312                   enum i915_power_well_id power_well_id)
1313 {
1314         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1315         int i;
1316
1317         for (i = 0; i < power_domains->power_well_count; i++) {
1318                 struct i915_power_well *power_well;
1319
1320                 power_well = &power_domains->power_wells[i];
1321                 if (power_well->id == power_well_id)
1322                         return power_well;
1323         }
1324
1325         return NULL;
1326 }
1327
1328 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1329
1330 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1331 {
1332         struct i915_power_well *cmn_bc =
1333                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1334         struct i915_power_well *cmn_d =
1335                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1336         u32 phy_control = dev_priv->chv_phy_control;
1337         u32 phy_status = 0;
1338         u32 phy_status_mask = 0xffffffff;
1339
1340         /*
1341          * The BIOS can leave the PHY is some weird state
1342          * where it doesn't fully power down some parts.
1343          * Disable the asserts until the PHY has been fully
1344          * reset (ie. the power well has been disabled at
1345          * least once).
1346          */
1347         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1348                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1349                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1350                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1351                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1352                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1353                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1354
1355         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1356                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1357                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1358                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1359
1360         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1361                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1362
1363                 /* this assumes override is only used to enable lanes */
1364                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1365                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1366
1367                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1368                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1369
1370                 /* CL1 is on whenever anything is on in either channel */
1371                 if (BITS_SET(phy_control,
1372                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1373                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1374                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1375
1376                 /*
1377                  * The DPLLB check accounts for the pipe B + port A usage
1378                  * with CL2 powered up but all the lanes in the second channel
1379                  * powered down.
1380                  */
1381                 if (BITS_SET(phy_control,
1382                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1383                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1384                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1385
1386                 if (BITS_SET(phy_control,
1387                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1388                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1389                 if (BITS_SET(phy_control,
1390                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1391                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1392
1393                 if (BITS_SET(phy_control,
1394                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1395                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1396                 if (BITS_SET(phy_control,
1397                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1398                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1399         }
1400
1401         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1402                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1403
1404                 /* this assumes override is only used to enable lanes */
1405                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1406                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1407
1408                 if (BITS_SET(phy_control,
1409                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1410                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1411
1412                 if (BITS_SET(phy_control,
1413                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1414                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1415                 if (BITS_SET(phy_control,
1416                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1417                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1418         }
1419
1420         phy_status &= phy_status_mask;
1421
1422         /*
1423          * The PHY may be busy with some initial calibration and whatnot,
1424          * so the power state can take a while to actually change.
1425          */
1426         if (intel_wait_for_register(dev_priv,
1427                                     DISPLAY_PHY_STATUS,
1428                                     phy_status_mask,
1429                                     phy_status,
1430                                     10))
1431                 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1432                           I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1433                            phy_status, dev_priv->chv_phy_control);
1434 }
1435
1436 #undef BITS_SET
1437
1438 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1439                                            struct i915_power_well *power_well)
1440 {
1441         enum dpio_phy phy;
1442         enum pipe pipe;
1443         uint32_t tmp;
1444
1445         WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1446                      power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
1447
1448         if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1449                 pipe = PIPE_A;
1450                 phy = DPIO_PHY0;
1451         } else {
1452                 pipe = PIPE_C;
1453                 phy = DPIO_PHY1;
1454         }
1455
1456         /* since ref/cri clock was enabled */
1457         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1458         vlv_set_power_well(dev_priv, power_well, true);
1459
1460         /* Poll for phypwrgood signal */
1461         if (intel_wait_for_register(dev_priv,
1462                                     DISPLAY_PHY_STATUS,
1463                                     PHY_POWERGOOD(phy),
1464                                     PHY_POWERGOOD(phy),
1465                                     1))
1466                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1467
1468         mutex_lock(&dev_priv->sb_lock);
1469
1470         /* Enable dynamic power down */
1471         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1472         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1473                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1474         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1475
1476         if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1477                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1478                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1479                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1480         } else {
1481                 /*
1482                  * Force the non-existing CL2 off. BXT does this
1483                  * too, so maybe it saves some power even though
1484                  * CL2 doesn't exist?
1485                  */
1486                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1487                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1488                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1489         }
1490
1491         mutex_unlock(&dev_priv->sb_lock);
1492
1493         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1494         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1495
1496         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1497                       phy, dev_priv->chv_phy_control);
1498
1499         assert_chv_phy_status(dev_priv);
1500 }
1501
1502 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1503                                             struct i915_power_well *power_well)
1504 {
1505         enum dpio_phy phy;
1506
1507         WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1508                      power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
1509
1510         if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1511                 phy = DPIO_PHY0;
1512                 assert_pll_disabled(dev_priv, PIPE_A);
1513                 assert_pll_disabled(dev_priv, PIPE_B);
1514         } else {
1515                 phy = DPIO_PHY1;
1516                 assert_pll_disabled(dev_priv, PIPE_C);
1517         }
1518
1519         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1520         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1521
1522         vlv_set_power_well(dev_priv, power_well, false);
1523
1524         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1525                       phy, dev_priv->chv_phy_control);
1526
1527         /* PHY is fully reset now, so we can enable the PHY state asserts */
1528         dev_priv->chv_phy_assert[phy] = true;
1529
1530         assert_chv_phy_status(dev_priv);
1531 }
1532
1533 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1534                                      enum dpio_channel ch, bool override, unsigned int mask)
1535 {
1536         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1537         u32 reg, val, expected, actual;
1538
1539         /*
1540          * The BIOS can leave the PHY is some weird state
1541          * where it doesn't fully power down some parts.
1542          * Disable the asserts until the PHY has been fully
1543          * reset (ie. the power well has been disabled at
1544          * least once).
1545          */
1546         if (!dev_priv->chv_phy_assert[phy])
1547                 return;
1548
1549         if (ch == DPIO_CH0)
1550                 reg = _CHV_CMN_DW0_CH0;
1551         else
1552                 reg = _CHV_CMN_DW6_CH1;
1553
1554         mutex_lock(&dev_priv->sb_lock);
1555         val = vlv_dpio_read(dev_priv, pipe, reg);
1556         mutex_unlock(&dev_priv->sb_lock);
1557
1558         /*
1559          * This assumes !override is only used when the port is disabled.
1560          * All lanes should power down even without the override when
1561          * the port is disabled.
1562          */
1563         if (!override || mask == 0xf) {
1564                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1565                 /*
1566                  * If CH1 common lane is not active anymore
1567                  * (eg. for pipe B DPLL) the entire channel will
1568                  * shut down, which causes the common lane registers
1569                  * to read as 0. That means we can't actually check
1570                  * the lane power down status bits, but as the entire
1571                  * register reads as 0 it's a good indication that the
1572                  * channel is indeed entirely powered down.
1573                  */
1574                 if (ch == DPIO_CH1 && val == 0)
1575                         expected = 0;
1576         } else if (mask != 0x0) {
1577                 expected = DPIO_ANYDL_POWERDOWN;
1578         } else {
1579                 expected = 0;
1580         }
1581
1582         if (ch == DPIO_CH0)
1583                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1584         else
1585                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1586         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1587
1588         WARN(actual != expected,
1589              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1590              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1591              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1592              reg, val);
1593 }
1594
1595 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1596                           enum dpio_channel ch, bool override)
1597 {
1598         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1599         bool was_override;
1600
1601         mutex_lock(&power_domains->lock);
1602
1603         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1604
1605         if (override == was_override)
1606                 goto out;
1607
1608         if (override)
1609                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1610         else
1611                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1612
1613         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1614
1615         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1616                       phy, ch, dev_priv->chv_phy_control);
1617
1618         assert_chv_phy_status(dev_priv);
1619
1620 out:
1621         mutex_unlock(&power_domains->lock);
1622
1623         return was_override;
1624 }
1625
1626 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1627                              bool override, unsigned int mask)
1628 {
1629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1630         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1631         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1632         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1633
1634         mutex_lock(&power_domains->lock);
1635
1636         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1637         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1638
1639         if (override)
1640                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1641         else
1642                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1643
1644         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1645
1646         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1647                       phy, ch, mask, dev_priv->chv_phy_control);
1648
1649         assert_chv_phy_status(dev_priv);
1650
1651         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1652
1653         mutex_unlock(&power_domains->lock);
1654 }
1655
1656 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1657                                         struct i915_power_well *power_well)
1658 {
1659         enum pipe pipe = PIPE_A;
1660         bool enabled;
1661         u32 state, ctrl;
1662
1663         mutex_lock(&dev_priv->rps.hw_lock);
1664
1665         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1666         /*
1667          * We only ever set the power-on and power-gate states, anything
1668          * else is unexpected.
1669          */
1670         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1671         enabled = state == DP_SSS_PWR_ON(pipe);
1672
1673         /*
1674          * A transient state at this point would mean some unexpected party
1675          * is poking at the power controls too.
1676          */
1677         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1678         WARN_ON(ctrl << 16 != state);
1679
1680         mutex_unlock(&dev_priv->rps.hw_lock);
1681
1682         return enabled;
1683 }
1684
1685 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1686                                     struct i915_power_well *power_well,
1687                                     bool enable)
1688 {
1689         enum pipe pipe = PIPE_A;
1690         u32 state;
1691         u32 ctrl;
1692
1693         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1694
1695         mutex_lock(&dev_priv->rps.hw_lock);
1696
1697 #define COND \
1698         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1699
1700         if (COND)
1701                 goto out;
1702
1703         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1704         ctrl &= ~DP_SSC_MASK(pipe);
1705         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1706         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1707
1708         if (wait_for(COND, 100))
1709                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1710                           state,
1711                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1712
1713 #undef COND
1714
1715 out:
1716         mutex_unlock(&dev_priv->rps.hw_lock);
1717 }
1718
1719 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1720                                        struct i915_power_well *power_well)
1721 {
1722         WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
1723
1724         chv_set_pipe_power_well(dev_priv, power_well, true);
1725
1726         vlv_display_power_well_init(dev_priv);
1727 }
1728
1729 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1730                                         struct i915_power_well *power_well)
1731 {
1732         WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
1733
1734         vlv_display_power_well_deinit(dev_priv);
1735
1736         chv_set_pipe_power_well(dev_priv, power_well, false);
1737 }
1738
1739 static void
1740 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1741                                  enum intel_display_power_domain domain)
1742 {
1743         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1744         struct i915_power_well *power_well;
1745
1746         for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
1747                 intel_power_well_get(dev_priv, power_well);
1748
1749         power_domains->domain_use_count[domain]++;
1750 }
1751
1752 /**
1753  * intel_display_power_get - grab a power domain reference
1754  * @dev_priv: i915 device instance
1755  * @domain: power domain to reference
1756  *
1757  * This function grabs a power domain reference for @domain and ensures that the
1758  * power domain and all its parents are powered up. Therefore users should only
1759  * grab a reference to the innermost power domain they need.
1760  *
1761  * Any power domain reference obtained by this function must have a symmetric
1762  * call to intel_display_power_put() to release the reference again.
1763  */
1764 void intel_display_power_get(struct drm_i915_private *dev_priv,
1765                              enum intel_display_power_domain domain)
1766 {
1767         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1768
1769         intel_runtime_pm_get(dev_priv);
1770
1771         mutex_lock(&power_domains->lock);
1772
1773         __intel_display_power_get_domain(dev_priv, domain);
1774
1775         mutex_unlock(&power_domains->lock);
1776 }
1777
1778 /**
1779  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1780  * @dev_priv: i915 device instance
1781  * @domain: power domain to reference
1782  *
1783  * This function grabs a power domain reference for @domain and ensures that the
1784  * power domain and all its parents are powered up. Therefore users should only
1785  * grab a reference to the innermost power domain they need.
1786  *
1787  * Any power domain reference obtained by this function must have a symmetric
1788  * call to intel_display_power_put() to release the reference again.
1789  */
1790 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1791                                         enum intel_display_power_domain domain)
1792 {
1793         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1794         bool is_enabled;
1795
1796         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1797                 return false;
1798
1799         mutex_lock(&power_domains->lock);
1800
1801         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1802                 __intel_display_power_get_domain(dev_priv, domain);
1803                 is_enabled = true;
1804         } else {
1805                 is_enabled = false;
1806         }
1807
1808         mutex_unlock(&power_domains->lock);
1809
1810         if (!is_enabled)
1811                 intel_runtime_pm_put(dev_priv);
1812
1813         return is_enabled;
1814 }
1815
1816 /**
1817  * intel_display_power_put - release a power domain reference
1818  * @dev_priv: i915 device instance
1819  * @domain: power domain to reference
1820  *
1821  * This function drops the power domain reference obtained by
1822  * intel_display_power_get() and might power down the corresponding hardware
1823  * block right away if this is the last reference.
1824  */
1825 void intel_display_power_put(struct drm_i915_private *dev_priv,
1826                              enum intel_display_power_domain domain)
1827 {
1828         struct i915_power_domains *power_domains;
1829         struct i915_power_well *power_well;
1830
1831         power_domains = &dev_priv->power_domains;
1832
1833         mutex_lock(&power_domains->lock);
1834
1835         WARN(!power_domains->domain_use_count[domain],
1836              "Use count on domain %s is already zero\n",
1837              intel_display_power_domain_str(domain));
1838         power_domains->domain_use_count[domain]--;
1839
1840         for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
1841                 intel_power_well_put(dev_priv, power_well);
1842
1843         mutex_unlock(&power_domains->lock);
1844
1845         intel_runtime_pm_put(dev_priv);
1846 }
1847
1848 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1849         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1850         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1851         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |             \
1852         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1853         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1854         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1855         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1856         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1857         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1858         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1859         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1860         BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
1861         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1862         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1863         BIT_ULL(POWER_DOMAIN_INIT))
1864
1865 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1866         BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
1867         BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
1868         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |             \
1869         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |             \
1870         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
1871         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
1872         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
1873         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |                \
1874         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |                \
1875         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |                \
1876         BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */    \
1877         BIT_ULL(POWER_DOMAIN_VGA) |                             \
1878         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
1879         BIT_ULL(POWER_DOMAIN_INIT))
1880
1881 #define VLV_DISPLAY_POWER_DOMAINS (             \
1882         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1883         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1884         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1885         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1886         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1887         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1888         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1889         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1890         BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
1891         BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
1892         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1893         BIT_ULL(POWER_DOMAIN_AUDIO) |           \
1894         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1895         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1896         BIT_ULL(POWER_DOMAIN_GMBUS) |           \
1897         BIT_ULL(POWER_DOMAIN_INIT))
1898
1899 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1900         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1901         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1902         BIT_ULL(POWER_DOMAIN_PORT_CRT) |                \
1903         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1904         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1905         BIT_ULL(POWER_DOMAIN_INIT))
1906
1907 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1908         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1909         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1910         BIT_ULL(POWER_DOMAIN_INIT))
1911
1912 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1913         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1914         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1915         BIT_ULL(POWER_DOMAIN_INIT))
1916
1917 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1918         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1919         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1920         BIT_ULL(POWER_DOMAIN_INIT))
1921
1922 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1923         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1924         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1925         BIT_ULL(POWER_DOMAIN_INIT))
1926
1927 #define CHV_DISPLAY_POWER_DOMAINS (             \
1928         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1929         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1930         BIT_ULL(POWER_DOMAIN_PIPE_C) |          \
1931         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1932         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1933         BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |     \
1934         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1935         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1936         BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |    \
1937         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1938         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1939         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1940         BIT_ULL(POWER_DOMAIN_PORT_DSI) |                \
1941         BIT_ULL(POWER_DOMAIN_VGA) |                     \
1942         BIT_ULL(POWER_DOMAIN_AUDIO) |           \
1943         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1944         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1945         BIT_ULL(POWER_DOMAIN_AUX_D) |           \
1946         BIT_ULL(POWER_DOMAIN_GMBUS) |           \
1947         BIT_ULL(POWER_DOMAIN_INIT))
1948
1949 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1950         BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
1951         BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
1952         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
1953         BIT_ULL(POWER_DOMAIN_AUX_C) |           \
1954         BIT_ULL(POWER_DOMAIN_INIT))
1955
1956 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1957         BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
1958         BIT_ULL(POWER_DOMAIN_AUX_D) |           \
1959         BIT_ULL(POWER_DOMAIN_INIT))
1960
1961 #define I830_PIPES_POWER_DOMAINS (              \
1962         BIT_ULL(POWER_DOMAIN_PIPE_A) |          \
1963         BIT_ULL(POWER_DOMAIN_PIPE_B) |          \
1964         BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |     \
1965         BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
1966         BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |    \
1967         BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |    \
1968         BIT_ULL(POWER_DOMAIN_INIT))
1969
1970 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1971         .sync_hw = i9xx_power_well_sync_hw_noop,
1972         .enable = i9xx_always_on_power_well_noop,
1973         .disable = i9xx_always_on_power_well_noop,
1974         .is_enabled = i9xx_always_on_power_well_enabled,
1975 };
1976
1977 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1978         .sync_hw = i9xx_power_well_sync_hw_noop,
1979         .enable = chv_pipe_power_well_enable,
1980         .disable = chv_pipe_power_well_disable,
1981         .is_enabled = chv_pipe_power_well_enabled,
1982 };
1983
1984 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1985         .sync_hw = i9xx_power_well_sync_hw_noop,
1986         .enable = chv_dpio_cmn_power_well_enable,
1987         .disable = chv_dpio_cmn_power_well_disable,
1988         .is_enabled = vlv_power_well_enabled,
1989 };
1990
1991 static struct i915_power_well i9xx_always_on_power_well[] = {
1992         {
1993                 .name = "always-on",
1994                 .always_on = 1,
1995                 .domains = POWER_DOMAIN_MASK,
1996                 .ops = &i9xx_always_on_power_well_ops,
1997                 .id = I915_DISP_PW_ALWAYS_ON,
1998         },
1999 };
2000
2001 static const struct i915_power_well_ops i830_pipes_power_well_ops = {
2002         .sync_hw = i830_pipes_power_well_sync_hw,
2003         .enable = i830_pipes_power_well_enable,
2004         .disable = i830_pipes_power_well_disable,
2005         .is_enabled = i830_pipes_power_well_enabled,
2006 };
2007
2008 static struct i915_power_well i830_power_wells[] = {
2009         {
2010                 .name = "always-on",
2011                 .always_on = 1,
2012                 .domains = POWER_DOMAIN_MASK,
2013                 .ops = &i9xx_always_on_power_well_ops,
2014                 .id = I915_DISP_PW_ALWAYS_ON,
2015         },
2016         {
2017                 .name = "pipes",
2018                 .domains = I830_PIPES_POWER_DOMAINS,
2019                 .ops = &i830_pipes_power_well_ops,
2020                 .id = I830_DISP_PW_PIPES,
2021         },
2022 };
2023
2024 static const struct i915_power_well_ops hsw_power_well_ops = {
2025         .sync_hw = hsw_power_well_sync_hw,
2026         .enable = hsw_power_well_enable,
2027         .disable = hsw_power_well_disable,
2028         .is_enabled = hsw_power_well_enabled,
2029 };
2030
2031 static const struct i915_power_well_ops skl_power_well_ops = {
2032         .sync_hw = skl_power_well_sync_hw,
2033         .enable = skl_power_well_enable,
2034         .disable = skl_power_well_disable,
2035         .is_enabled = skl_power_well_enabled,
2036 };
2037
2038 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
2039         .sync_hw = i9xx_power_well_sync_hw_noop,
2040         .enable = gen9_dc_off_power_well_enable,
2041         .disable = gen9_dc_off_power_well_disable,
2042         .is_enabled = gen9_dc_off_power_well_enabled,
2043 };
2044
2045 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
2046         .sync_hw = i9xx_power_well_sync_hw_noop,
2047         .enable = bxt_dpio_cmn_power_well_enable,
2048         .disable = bxt_dpio_cmn_power_well_disable,
2049         .is_enabled = bxt_dpio_cmn_power_well_enabled,
2050 };
2051
2052 static struct i915_power_well hsw_power_wells[] = {
2053         {
2054                 .name = "always-on",
2055                 .always_on = 1,
2056                 .domains = POWER_DOMAIN_MASK,
2057                 .ops = &i9xx_always_on_power_well_ops,
2058                 .id = I915_DISP_PW_ALWAYS_ON,
2059         },
2060         {
2061                 .name = "display",
2062                 .domains = HSW_DISPLAY_POWER_DOMAINS,
2063                 .ops = &hsw_power_well_ops,
2064                 .id = HSW_DISP_PW_GLOBAL,
2065                 .hsw.has_vga = true,
2066         },
2067 };
2068
2069 static struct i915_power_well bdw_power_wells[] = {
2070         {
2071                 .name = "always-on",
2072                 .always_on = 1,
2073                 .domains = POWER_DOMAIN_MASK,
2074                 .ops = &i9xx_always_on_power_well_ops,
2075                 .id = I915_DISP_PW_ALWAYS_ON,
2076         },
2077         {
2078                 .name = "display",
2079                 .domains = BDW_DISPLAY_POWER_DOMAINS,
2080                 .ops = &hsw_power_well_ops,
2081                 .id = HSW_DISP_PW_GLOBAL,
2082                 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2083                 .hsw.has_vga = true,
2084         },
2085 };
2086
2087 static const struct i915_power_well_ops vlv_display_power_well_ops = {
2088         .sync_hw = i9xx_power_well_sync_hw_noop,
2089         .enable = vlv_display_power_well_enable,
2090         .disable = vlv_display_power_well_disable,
2091         .is_enabled = vlv_power_well_enabled,
2092 };
2093
2094 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
2095         .sync_hw = i9xx_power_well_sync_hw_noop,
2096         .enable = vlv_dpio_cmn_power_well_enable,
2097         .disable = vlv_dpio_cmn_power_well_disable,
2098         .is_enabled = vlv_power_well_enabled,
2099 };
2100
2101 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
2102         .sync_hw = i9xx_power_well_sync_hw_noop,
2103         .enable = vlv_power_well_enable,
2104         .disable = vlv_power_well_disable,
2105         .is_enabled = vlv_power_well_enabled,
2106 };
2107
2108 static struct i915_power_well vlv_power_wells[] = {
2109         {
2110                 .name = "always-on",
2111                 .always_on = 1,
2112                 .domains = POWER_DOMAIN_MASK,
2113                 .ops = &i9xx_always_on_power_well_ops,
2114                 .id = I915_DISP_PW_ALWAYS_ON,
2115         },
2116         {
2117                 .name = "display",
2118                 .domains = VLV_DISPLAY_POWER_DOMAINS,
2119                 .id = PUNIT_POWER_WELL_DISP2D,
2120                 .ops = &vlv_display_power_well_ops,
2121         },
2122         {
2123                 .name = "dpio-tx-b-01",
2124                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2125                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2126                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2127                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2128                 .ops = &vlv_dpio_power_well_ops,
2129                 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
2130         },
2131         {
2132                 .name = "dpio-tx-b-23",
2133                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2134                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2135                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2136                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2137                 .ops = &vlv_dpio_power_well_ops,
2138                 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
2139         },
2140         {
2141                 .name = "dpio-tx-c-01",
2142                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2143                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2144                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2145                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2146                 .ops = &vlv_dpio_power_well_ops,
2147                 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
2148         },
2149         {
2150                 .name = "dpio-tx-c-23",
2151                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2152                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2153                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2154                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2155                 .ops = &vlv_dpio_power_well_ops,
2156                 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
2157         },
2158         {
2159                 .name = "dpio-common",
2160                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2161                 .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
2162                 .ops = &vlv_dpio_cmn_power_well_ops,
2163         },
2164 };
2165
2166 static struct i915_power_well chv_power_wells[] = {
2167         {
2168                 .name = "always-on",
2169                 .always_on = 1,
2170                 .domains = POWER_DOMAIN_MASK,
2171                 .ops = &i9xx_always_on_power_well_ops,
2172                 .id = I915_DISP_PW_ALWAYS_ON,
2173         },
2174         {
2175                 .name = "display",
2176                 /*
2177                  * Pipe A power well is the new disp2d well. Pipe B and C
2178                  * power wells don't actually exist. Pipe A power well is
2179                  * required for any pipe to work.
2180                  */
2181                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2182                 .id = CHV_DISP_PW_PIPE_A,
2183                 .ops = &chv_pipe_power_well_ops,
2184         },
2185         {
2186                 .name = "dpio-common-bc",
2187                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2188                 .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
2189                 .ops = &chv_dpio_cmn_power_well_ops,
2190         },
2191         {
2192                 .name = "dpio-common-d",
2193                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2194                 .id = PUNIT_POWER_WELL_DPIO_CMN_D,
2195                 .ops = &chv_dpio_cmn_power_well_ops,
2196         },
2197 };
2198
2199 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2200                                          enum i915_power_well_id power_well_id)
2201 {
2202         struct i915_power_well *power_well;
2203         bool ret;
2204
2205         power_well = lookup_power_well(dev_priv, power_well_id);
2206         ret = power_well->ops->is_enabled(dev_priv, power_well);
2207
2208         return ret;
2209 }
2210
2211 static struct i915_power_well skl_power_wells[] = {
2212         {
2213                 .name = "always-on",
2214                 .always_on = 1,
2215                 .domains = POWER_DOMAIN_MASK,
2216                 .ops = &i9xx_always_on_power_well_ops,
2217                 .id = I915_DISP_PW_ALWAYS_ON,
2218         },
2219         {
2220                 .name = "power well 1",
2221                 /* Handled by the DMC firmware */
2222                 .domains = 0,
2223                 .ops = &skl_power_well_ops,
2224                 .id = SKL_DISP_PW_1,
2225         },
2226         {
2227                 .name = "MISC IO power well",
2228                 /* Handled by the DMC firmware */
2229                 .domains = 0,
2230                 .ops = &skl_power_well_ops,
2231                 .id = SKL_DISP_PW_MISC_IO,
2232         },
2233         {
2234                 .name = "DC off",
2235                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2236                 .ops = &gen9_dc_off_power_well_ops,
2237                 .id = SKL_DISP_PW_DC_OFF,
2238         },
2239         {
2240                 .name = "power well 2",
2241                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2242                 .ops = &skl_power_well_ops,
2243                 .id = SKL_DISP_PW_2,
2244         },
2245         {
2246                 .name = "DDI A/E IO power well",
2247                 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
2248                 .ops = &skl_power_well_ops,
2249                 .id = SKL_DISP_PW_DDI_A_E,
2250         },
2251         {
2252                 .name = "DDI B IO power well",
2253                 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2254                 .ops = &skl_power_well_ops,
2255                 .id = SKL_DISP_PW_DDI_B,
2256         },
2257         {
2258                 .name = "DDI C IO power well",
2259                 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2260                 .ops = &skl_power_well_ops,
2261                 .id = SKL_DISP_PW_DDI_C,
2262         },
2263         {
2264                 .name = "DDI D IO power well",
2265                 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
2266                 .ops = &skl_power_well_ops,
2267                 .id = SKL_DISP_PW_DDI_D,
2268         },
2269 };
2270
2271 static struct i915_power_well bxt_power_wells[] = {
2272         {
2273                 .name = "always-on",
2274                 .always_on = 1,
2275                 .domains = POWER_DOMAIN_MASK,
2276                 .ops = &i9xx_always_on_power_well_ops,
2277                 .id = I915_DISP_PW_ALWAYS_ON,
2278         },
2279         {
2280                 .name = "power well 1",
2281                 .domains = 0,
2282                 .ops = &skl_power_well_ops,
2283                 .id = SKL_DISP_PW_1,
2284         },
2285         {
2286                 .name = "DC off",
2287                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2288                 .ops = &gen9_dc_off_power_well_ops,
2289                 .id = SKL_DISP_PW_DC_OFF,
2290         },
2291         {
2292                 .name = "power well 2",
2293                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2294                 .ops = &skl_power_well_ops,
2295                 .id = SKL_DISP_PW_2,
2296         },
2297         {
2298                 .name = "dpio-common-a",
2299                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2300                 .ops = &bxt_dpio_cmn_power_well_ops,
2301                 .id = BXT_DPIO_CMN_A,
2302                 .bxt.phy = DPIO_PHY1,
2303         },
2304         {
2305                 .name = "dpio-common-bc",
2306                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2307                 .ops = &bxt_dpio_cmn_power_well_ops,
2308                 .id = BXT_DPIO_CMN_BC,
2309                 .bxt.phy = DPIO_PHY0,
2310         },
2311 };
2312
2313 static struct i915_power_well glk_power_wells[] = {
2314         {
2315                 .name = "always-on",
2316                 .always_on = 1,
2317                 .domains = POWER_DOMAIN_MASK,
2318                 .ops = &i9xx_always_on_power_well_ops,
2319                 .id = I915_DISP_PW_ALWAYS_ON,
2320         },
2321         {
2322                 .name = "power well 1",
2323                 /* Handled by the DMC firmware */
2324                 .domains = 0,
2325                 .ops = &skl_power_well_ops,
2326                 .id = SKL_DISP_PW_1,
2327         },
2328         {
2329                 .name = "DC off",
2330                 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
2331                 .ops = &gen9_dc_off_power_well_ops,
2332                 .id = SKL_DISP_PW_DC_OFF,
2333         },
2334         {
2335                 .name = "power well 2",
2336                 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2337                 .ops = &skl_power_well_ops,
2338                 .id = SKL_DISP_PW_2,
2339         },
2340         {
2341                 .name = "dpio-common-a",
2342                 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
2343                 .ops = &bxt_dpio_cmn_power_well_ops,
2344                 .id = BXT_DPIO_CMN_A,
2345                 .bxt.phy = DPIO_PHY1,
2346         },
2347         {
2348                 .name = "dpio-common-b",
2349                 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
2350                 .ops = &bxt_dpio_cmn_power_well_ops,
2351                 .id = BXT_DPIO_CMN_BC,
2352                 .bxt.phy = DPIO_PHY0,
2353         },
2354         {
2355                 .name = "dpio-common-c",
2356                 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
2357                 .ops = &bxt_dpio_cmn_power_well_ops,
2358                 .id = GLK_DPIO_CMN_C,
2359                 .bxt.phy = DPIO_PHY2,
2360         },
2361         {
2362                 .name = "AUX A",
2363                 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
2364                 .ops = &skl_power_well_ops,
2365                 .id = GLK_DISP_PW_AUX_A,
2366         },
2367         {
2368                 .name = "AUX B",
2369                 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
2370                 .ops = &skl_power_well_ops,
2371                 .id = GLK_DISP_PW_AUX_B,
2372         },
2373         {
2374                 .name = "AUX C",
2375                 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
2376                 .ops = &skl_power_well_ops,
2377                 .id = GLK_DISP_PW_AUX_C,
2378         },
2379         {
2380                 .name = "DDI A IO power well",
2381                 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
2382                 .ops = &skl_power_well_ops,
2383                 .id = GLK_DISP_PW_DDI_A,
2384         },
2385         {
2386                 .name = "DDI B IO power well",
2387                 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
2388                 .ops = &skl_power_well_ops,
2389                 .id = SKL_DISP_PW_DDI_B,
2390         },
2391         {
2392                 .name = "DDI C IO power well",
2393                 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
2394                 .ops = &skl_power_well_ops,
2395                 .id = SKL_DISP_PW_DDI_C,
2396         },
2397 };
2398
2399 static struct i915_power_well cnl_power_wells[] = {
2400         {
2401                 .name = "always-on",
2402                 .always_on = 1,
2403                 .domains = POWER_DOMAIN_MASK,
2404                 .ops = &i9xx_always_on_power_well_ops,
2405                 .id = I915_DISP_PW_ALWAYS_ON,
2406         },
2407         {
2408                 .name = "power well 1",
2409                 /* Handled by the DMC firmware */
2410                 .domains = 0,
2411                 .ops = &skl_power_well_ops,
2412                 .id = SKL_DISP_PW_1,
2413         },
2414         {
2415                 .name = "AUX A",
2416                 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
2417                 .ops = &skl_power_well_ops,
2418                 .id = CNL_DISP_PW_AUX_A,
2419         },
2420         {
2421                 .name = "AUX B",
2422                 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
2423                 .ops = &skl_power_well_ops,
2424                 .id = CNL_DISP_PW_AUX_B,
2425         },
2426         {
2427                 .name = "AUX C",
2428                 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
2429                 .ops = &skl_power_well_ops,
2430                 .id = CNL_DISP_PW_AUX_C,
2431         },
2432         {
2433                 .name = "AUX D",
2434                 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
2435                 .ops = &skl_power_well_ops,
2436                 .id = CNL_DISP_PW_AUX_D,
2437         },
2438         {
2439                 .name = "DC off",
2440                 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
2441                 .ops = &gen9_dc_off_power_well_ops,
2442                 .id = SKL_DISP_PW_DC_OFF,
2443         },
2444         {
2445                 .name = "power well 2",
2446                 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2447                 .ops = &skl_power_well_ops,
2448                 .id = SKL_DISP_PW_2,
2449         },
2450         {
2451                 .name = "DDI A IO power well",
2452                 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
2453                 .ops = &skl_power_well_ops,
2454                 .id = CNL_DISP_PW_DDI_A,
2455         },
2456         {
2457                 .name = "DDI B IO power well",
2458                 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
2459                 .ops = &skl_power_well_ops,
2460                 .id = SKL_DISP_PW_DDI_B,
2461         },
2462         {
2463                 .name = "DDI C IO power well",
2464                 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
2465                 .ops = &skl_power_well_ops,
2466                 .id = SKL_DISP_PW_DDI_C,
2467         },
2468         {
2469                 .name = "DDI D IO power well",
2470                 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
2471                 .ops = &skl_power_well_ops,
2472                 .id = SKL_DISP_PW_DDI_D,
2473         },
2474 };
2475
2476 static int
2477 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2478                                    int disable_power_well)
2479 {
2480         if (disable_power_well >= 0)
2481                 return !!disable_power_well;
2482
2483         return 1;
2484 }
2485
2486 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2487                                     int enable_dc)
2488 {
2489         uint32_t mask;
2490         int requested_dc;
2491         int max_dc;
2492
2493         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
2494                 max_dc = 2;
2495                 mask = 0;
2496         } else if (IS_GEN9_LP(dev_priv)) {
2497                 max_dc = 1;
2498                 /*
2499                  * DC9 has a separate HW flow from the rest of the DC states,
2500                  * not depending on the DMC firmware. It's needed by system
2501                  * suspend/resume, so allow it unconditionally.
2502                  */
2503                 mask = DC_STATE_EN_DC9;
2504         } else {
2505                 max_dc = 0;
2506                 mask = 0;
2507         }
2508
2509         if (!i915.disable_power_well)
2510                 max_dc = 0;
2511
2512         if (enable_dc >= 0 && enable_dc <= max_dc) {
2513                 requested_dc = enable_dc;
2514         } else if (enable_dc == -1) {
2515                 requested_dc = max_dc;
2516         } else if (enable_dc > max_dc && enable_dc <= 2) {
2517                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2518                               enable_dc, max_dc);
2519                 requested_dc = max_dc;
2520         } else {
2521                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2522                 requested_dc = max_dc;
2523         }
2524
2525         if (requested_dc > 1)
2526                 mask |= DC_STATE_EN_UPTO_DC6;
2527         if (requested_dc > 0)
2528                 mask |= DC_STATE_EN_UPTO_DC5;
2529
2530         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2531
2532         return mask;
2533 }
2534
2535 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv)
2536 {
2537         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2538         u64 power_well_ids;
2539         int i;
2540
2541         power_well_ids = 0;
2542         for (i = 0; i < power_domains->power_well_count; i++) {
2543                 enum i915_power_well_id id = power_domains->power_wells[i].id;
2544
2545                 WARN_ON(id >= sizeof(power_well_ids) * 8);
2546                 WARN_ON(power_well_ids & BIT_ULL(id));
2547                 power_well_ids |= BIT_ULL(id);
2548         }
2549 }
2550
2551 #define set_power_wells(power_domains, __power_wells) ({                \
2552         (power_domains)->power_wells = (__power_wells);                 \
2553         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2554 })
2555
2556 /**
2557  * intel_power_domains_init - initializes the power domain structures
2558  * @dev_priv: i915 device instance
2559  *
2560  * Initializes the power domain structures for @dev_priv depending upon the
2561  * supported platform.
2562  */
2563 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2564 {
2565         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2566
2567         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2568                                                      i915.disable_power_well);
2569         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2570                                                             i915.enable_dc);
2571
2572         BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
2573
2574         mutex_init(&power_domains->lock);
2575
2576         /*
2577          * The enabling order will be from lower to higher indexed wells,
2578          * the disabling order is reversed.
2579          */
2580         if (IS_HASWELL(dev_priv)) {
2581                 set_power_wells(power_domains, hsw_power_wells);
2582         } else if (IS_BROADWELL(dev_priv)) {
2583                 set_power_wells(power_domains, bdw_power_wells);
2584         } else if (IS_GEN9_BC(dev_priv)) {
2585                 set_power_wells(power_domains, skl_power_wells);
2586         } else if (IS_CANNONLAKE(dev_priv)) {
2587                 set_power_wells(power_domains, cnl_power_wells);
2588         } else if (IS_BROXTON(dev_priv)) {
2589                 set_power_wells(power_domains, bxt_power_wells);
2590         } else if (IS_GEMINILAKE(dev_priv)) {
2591                 set_power_wells(power_domains, glk_power_wells);
2592         } else if (IS_CHERRYVIEW(dev_priv)) {
2593                 set_power_wells(power_domains, chv_power_wells);
2594         } else if (IS_VALLEYVIEW(dev_priv)) {
2595                 set_power_wells(power_domains, vlv_power_wells);
2596         } else if (IS_I830(dev_priv)) {
2597                 set_power_wells(power_domains, i830_power_wells);
2598         } else {
2599                 set_power_wells(power_domains, i9xx_always_on_power_well);
2600         }
2601
2602         assert_power_well_ids_unique(dev_priv);
2603
2604         return 0;
2605 }
2606
2607 /**
2608  * intel_power_domains_fini - finalizes the power domain structures
2609  * @dev_priv: i915 device instance
2610  *
2611  * Finalizes the power domain structures for @dev_priv depending upon the
2612  * supported platform. This function also disables runtime pm and ensures that
2613  * the device stays powered up so that the driver can be reloaded.
2614  */
2615 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2616 {
2617         struct device *kdev = &dev_priv->drm.pdev->dev;
2618
2619         /*
2620          * The i915.ko module is still not prepared to be loaded when
2621          * the power well is not enabled, so just enable it in case
2622          * we're going to unload/reload.
2623          * The following also reacquires the RPM reference the core passed
2624          * to the driver during loading, which is dropped in
2625          * intel_runtime_pm_enable(). We have to hand back the control of the
2626          * device to the core with this reference held.
2627          */
2628         intel_display_set_init_power(dev_priv, true);
2629
2630         /* Remove the refcount we took to keep power well support disabled. */
2631         if (!i915.disable_power_well)
2632                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2633
2634         /*
2635          * Remove the refcount we took in intel_runtime_pm_enable() in case
2636          * the platform doesn't support runtime PM.
2637          */
2638         if (!HAS_RUNTIME_PM(dev_priv))
2639                 pm_runtime_put(kdev);
2640 }
2641
2642 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2643 {
2644         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2645         struct i915_power_well *power_well;
2646
2647         mutex_lock(&power_domains->lock);
2648         for_each_power_well(dev_priv, power_well) {
2649                 power_well->ops->sync_hw(dev_priv, power_well);
2650                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2651                                                                      power_well);
2652         }
2653         mutex_unlock(&power_domains->lock);
2654 }
2655
2656 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2657 {
2658         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2659         POSTING_READ(DBUF_CTL);
2660
2661         udelay(10);
2662
2663         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2664                 DRM_ERROR("DBuf power enable timeout\n");
2665 }
2666
2667 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2668 {
2669         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2670         POSTING_READ(DBUF_CTL);
2671
2672         udelay(10);
2673
2674         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2675                 DRM_ERROR("DBuf power disable timeout!\n");
2676 }
2677
2678 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2679                                    bool resume)
2680 {
2681         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2682         struct i915_power_well *well;
2683         uint32_t val;
2684
2685         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2686
2687         /* enable PCH reset handshake */
2688         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2689         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2690
2691         /* enable PG1 and Misc I/O */
2692         mutex_lock(&power_domains->lock);
2693
2694         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2695         intel_power_well_enable(dev_priv, well);
2696
2697         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2698         intel_power_well_enable(dev_priv, well);
2699
2700         mutex_unlock(&power_domains->lock);
2701
2702         skl_init_cdclk(dev_priv);
2703
2704         gen9_dbuf_enable(dev_priv);
2705
2706         if (resume && dev_priv->csr.dmc_payload)
2707                 intel_csr_load_program(dev_priv);
2708 }
2709
2710 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2711 {
2712         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2713         struct i915_power_well *well;
2714
2715         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2716
2717         gen9_dbuf_disable(dev_priv);
2718
2719         skl_uninit_cdclk(dev_priv);
2720
2721         /* The spec doesn't call for removing the reset handshake flag */
2722         /* disable PG1 and Misc I/O */
2723
2724         mutex_lock(&power_domains->lock);
2725
2726         /*
2727          * BSpec says to keep the MISC IO power well enabled here, only
2728          * remove our request for power well 1.
2729          * Note that even though the driver's request is removed power well 1
2730          * may stay enabled after this due to DMC's own request on it.
2731          */
2732         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2733         intel_power_well_disable(dev_priv, well);
2734
2735         mutex_unlock(&power_domains->lock);
2736
2737         usleep_range(10, 30);           /* 10 us delay per Bspec */
2738 }
2739
2740 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2741                            bool resume)
2742 {
2743         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2744         struct i915_power_well *well;
2745         uint32_t val;
2746
2747         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2748
2749         /*
2750          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2751          * or else the reset will hang because there is no PCH to respond.
2752          * Move the handshake programming to initialization sequence.
2753          * Previously was left up to BIOS.
2754          */
2755         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2756         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2757         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2758
2759         /* Enable PG1 */
2760         mutex_lock(&power_domains->lock);
2761
2762         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2763         intel_power_well_enable(dev_priv, well);
2764
2765         mutex_unlock(&power_domains->lock);
2766
2767         bxt_init_cdclk(dev_priv);
2768
2769         gen9_dbuf_enable(dev_priv);
2770
2771         if (resume && dev_priv->csr.dmc_payload)
2772                 intel_csr_load_program(dev_priv);
2773 }
2774
2775 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2776 {
2777         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2778         struct i915_power_well *well;
2779
2780         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2781
2782         gen9_dbuf_disable(dev_priv);
2783
2784         bxt_uninit_cdclk(dev_priv);
2785
2786         /* The spec doesn't call for removing the reset handshake flag */
2787
2788         /*
2789          * Disable PW1 (PG1).
2790          * Note that even though the driver's request is removed power well 1
2791          * may stay enabled after this due to DMC's own request on it.
2792          */
2793         mutex_lock(&power_domains->lock);
2794
2795         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2796         intel_power_well_disable(dev_priv, well);
2797
2798         mutex_unlock(&power_domains->lock);
2799
2800         usleep_range(10, 30);           /* 10 us delay per Bspec */
2801 }
2802
2803 #define CNL_PROCMON_IDX(val) \
2804         (((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
2805 #define NUM_CNL_PROCMON \
2806         (CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
2807
2808 static const struct cnl_procmon {
2809         u32 dw1, dw9, dw10;
2810 } cnl_procmon_values[NUM_CNL_PROCMON] = {
2811         [CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
2812                 { .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
2813         [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
2814                 { .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
2815         [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
2816                 { .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
2817         [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
2818                 { .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
2819         [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
2820                 { .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
2821 };
2822
2823 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
2824 {
2825         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2826         const struct cnl_procmon *procmon;
2827         struct i915_power_well *well;
2828         u32 val;
2829
2830         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2831
2832         /* 1. Enable PCH Reset Handshake */
2833         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2834         val |= RESET_PCH_HANDSHAKE_ENABLE;
2835         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2836
2837         /* 2. Enable Comp */
2838         val = I915_READ(CHICKEN_MISC_2);
2839         val &= ~COMP_PWR_DOWN;
2840         I915_WRITE(CHICKEN_MISC_2, val);
2841
2842         val = I915_READ(CNL_PORT_COMP_DW3);
2843         procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
2844
2845         WARN_ON(procmon->dw10 == 0);
2846
2847         val = I915_READ(CNL_PORT_COMP_DW1);
2848         val &= ~((0xff << 16) | 0xff);
2849         val |= procmon->dw1;
2850         I915_WRITE(CNL_PORT_COMP_DW1, val);
2851
2852         I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
2853         I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
2854
2855         val = I915_READ(CNL_PORT_COMP_DW0);
2856         val |= COMP_INIT;
2857         I915_WRITE(CNL_PORT_COMP_DW0, val);
2858
2859         /* 3. */
2860         val = I915_READ(CNL_PORT_CL1CM_DW5);
2861         val |= CL_POWER_DOWN_ENABLE;
2862         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2863
2864         /*
2865          * 4. Enable Power Well 1 (PG1).
2866          *    The AUX IO power wells will be enabled on demand.
2867          */
2868         mutex_lock(&power_domains->lock);
2869         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2870         intel_power_well_enable(dev_priv, well);
2871         mutex_unlock(&power_domains->lock);
2872
2873         /* 5. Enable CD clock */
2874         cnl_init_cdclk(dev_priv);
2875
2876         /* 6. Enable DBUF */
2877         gen9_dbuf_enable(dev_priv);
2878 }
2879
2880 #undef CNL_PROCMON_IDX
2881 #undef NUM_CNL_PROCMON
2882
2883 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
2884 {
2885         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2886         struct i915_power_well *well;
2887         u32 val;
2888
2889         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2890
2891         /* 1. Disable all display engine functions -> aready done */
2892
2893         /* 2. Disable DBUF */
2894         gen9_dbuf_disable(dev_priv);
2895
2896         /* 3. Disable CD clock */
2897         cnl_uninit_cdclk(dev_priv);
2898
2899         /*
2900          * 4. Disable Power Well 1 (PG1).
2901          *    The AUX IO power wells are toggled on demand, so they are already
2902          *    disabled at this point.
2903          */
2904         mutex_lock(&power_domains->lock);
2905         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2906         intel_power_well_disable(dev_priv, well);
2907         mutex_unlock(&power_domains->lock);
2908
2909         usleep_range(10, 30);           /* 10 us delay per Bspec */
2910
2911         /* 5. Disable Comp */
2912         val = I915_READ(CHICKEN_MISC_2);
2913         val |= COMP_PWR_DOWN;
2914         I915_WRITE(CHICKEN_MISC_2, val);
2915 }
2916
2917 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2918 {
2919         struct i915_power_well *cmn_bc =
2920                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2921         struct i915_power_well *cmn_d =
2922                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2923
2924         /*
2925          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2926          * workaround never ever read DISPLAY_PHY_CONTROL, and
2927          * instead maintain a shadow copy ourselves. Use the actual
2928          * power well state and lane status to reconstruct the
2929          * expected initial value.
2930          */
2931         dev_priv->chv_phy_control =
2932                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2933                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2934                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2935                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2936                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2937
2938         /*
2939          * If all lanes are disabled we leave the override disabled
2940          * with all power down bits cleared to match the state we
2941          * would use after disabling the port. Otherwise enable the
2942          * override and set the lane powerdown bits accding to the
2943          * current lane status.
2944          */
2945         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2946                 uint32_t status = I915_READ(DPLL(PIPE_A));
2947                 unsigned int mask;
2948
2949                 mask = status & DPLL_PORTB_READY_MASK;
2950                 if (mask == 0xf)
2951                         mask = 0x0;
2952                 else
2953                         dev_priv->chv_phy_control |=
2954                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2955
2956                 dev_priv->chv_phy_control |=
2957                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2958
2959                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2960                 if (mask == 0xf)
2961                         mask = 0x0;
2962                 else
2963                         dev_priv->chv_phy_control |=
2964                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2965
2966                 dev_priv->chv_phy_control |=
2967                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2968
2969                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2970
2971                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2972         } else {
2973                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2974         }
2975
2976         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2977                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2978                 unsigned int mask;
2979
2980                 mask = status & DPLL_PORTD_READY_MASK;
2981
2982                 if (mask == 0xf)
2983                         mask = 0x0;
2984                 else
2985                         dev_priv->chv_phy_control |=
2986                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2987
2988                 dev_priv->chv_phy_control |=
2989                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2990
2991                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2992
2993                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2994         } else {
2995                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2996         }
2997
2998         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2999
3000         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
3001                       dev_priv->chv_phy_control);
3002 }
3003
3004 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
3005 {
3006         struct i915_power_well *cmn =
3007                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
3008         struct i915_power_well *disp2d =
3009                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
3010
3011         /* If the display might be already active skip this */
3012         if (cmn->ops->is_enabled(dev_priv, cmn) &&
3013             disp2d->ops->is_enabled(dev_priv, disp2d) &&
3014             I915_READ(DPIO_CTL) & DPIO_CMNRST)
3015                 return;
3016
3017         DRM_DEBUG_KMS("toggling display PHY side reset\n");
3018
3019         /* cmnlane needs DPLL registers */
3020         disp2d->ops->enable(dev_priv, disp2d);
3021
3022         /*
3023          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
3024          * Need to assert and de-assert PHY SB reset by gating the
3025          * common lane power, then un-gating it.
3026          * Simply ungating isn't enough to reset the PHY enough to get
3027          * ports and lanes running.
3028          */
3029         cmn->ops->disable(dev_priv, cmn);
3030 }
3031
3032 /**
3033  * intel_power_domains_init_hw - initialize hardware power domain state
3034  * @dev_priv: i915 device instance
3035  * @resume: Called from resume code paths or not
3036  *
3037  * This function initializes the hardware power domain state and enables all
3038  * power wells belonging to the INIT power domain. Power wells in other
3039  * domains (and not in the INIT domain) are referenced or disabled during the
3040  * modeset state HW readout. After that the reference count of each power well
3041  * must match its HW enabled state, see intel_power_domains_verify_state().
3042  */
3043 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
3044 {
3045         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3046
3047         power_domains->initializing = true;
3048
3049         if (IS_CANNONLAKE(dev_priv)) {
3050                 cnl_display_core_init(dev_priv, resume);
3051         } else if (IS_GEN9_BC(dev_priv)) {
3052                 skl_display_core_init(dev_priv, resume);
3053         } else if (IS_GEN9_LP(dev_priv)) {
3054                 bxt_display_core_init(dev_priv, resume);
3055         } else if (IS_CHERRYVIEW(dev_priv)) {
3056                 mutex_lock(&power_domains->lock);
3057                 chv_phy_control_init(dev_priv);
3058                 mutex_unlock(&power_domains->lock);
3059         } else if (IS_VALLEYVIEW(dev_priv)) {
3060                 mutex_lock(&power_domains->lock);
3061                 vlv_cmnlane_wa(dev_priv);
3062                 mutex_unlock(&power_domains->lock);
3063         }
3064
3065         /* For now, we need the power well to be always enabled. */
3066         intel_display_set_init_power(dev_priv, true);
3067         /* Disable power support if the user asked so. */
3068         if (!i915.disable_power_well)
3069                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
3070         intel_power_domains_sync_hw(dev_priv);
3071         power_domains->initializing = false;
3072 }
3073
3074 /**
3075  * intel_power_domains_suspend - suspend power domain state
3076  * @dev_priv: i915 device instance
3077  *
3078  * This function prepares the hardware power domain state before entering
3079  * system suspend. It must be paired with intel_power_domains_init_hw().
3080  */
3081 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
3082 {
3083         /*
3084          * Even if power well support was disabled we still want to disable
3085          * power wells while we are system suspended.
3086          */
3087         if (!i915.disable_power_well)
3088                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
3089
3090         if (IS_CANNONLAKE(dev_priv))
3091                 cnl_display_core_uninit(dev_priv);
3092         else if (IS_GEN9_BC(dev_priv))
3093                 skl_display_core_uninit(dev_priv);
3094         else if (IS_GEN9_LP(dev_priv))
3095                 bxt_display_core_uninit(dev_priv);
3096 }
3097
3098 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
3099 {
3100         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3101         struct i915_power_well *power_well;
3102
3103         for_each_power_well(dev_priv, power_well) {
3104                 enum intel_display_power_domain domain;
3105
3106                 DRM_DEBUG_DRIVER("%-25s %d\n",
3107                                  power_well->name, power_well->count);
3108
3109                 for_each_power_domain(domain, power_well->domains)
3110                         DRM_DEBUG_DRIVER("  %-23s %d\n",
3111                                          intel_display_power_domain_str(domain),
3112                                          power_domains->domain_use_count[domain]);
3113         }
3114 }
3115
3116 /**
3117  * intel_power_domains_verify_state - verify the HW/SW state for all power wells
3118  * @dev_priv: i915 device instance
3119  *
3120  * Verify if the reference count of each power well matches its HW enabled
3121  * state and the total refcount of the domains it belongs to. This must be
3122  * called after modeset HW state sanitization, which is responsible for
3123  * acquiring reference counts for any power wells in use and disabling the
3124  * ones left on by BIOS but not required by any active output.
3125  */
3126 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
3127 {
3128         struct i915_power_domains *power_domains = &dev_priv->power_domains;
3129         struct i915_power_well *power_well;
3130         bool dump_domain_info;
3131
3132         mutex_lock(&power_domains->lock);
3133
3134         dump_domain_info = false;
3135         for_each_power_well(dev_priv, power_well) {
3136                 enum intel_display_power_domain domain;
3137                 int domains_count;
3138                 bool enabled;
3139
3140                 /*
3141                  * Power wells not belonging to any domain (like the MISC_IO
3142                  * and PW1 power wells) are under FW control, so ignore them,
3143                  * since their state can change asynchronously.
3144                  */
3145                 if (!power_well->domains)
3146                         continue;
3147
3148                 enabled = power_well->ops->is_enabled(dev_priv, power_well);
3149                 if ((power_well->count || power_well->always_on) != enabled)
3150                         DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
3151                                   power_well->name, power_well->count, enabled);
3152
3153                 domains_count = 0;
3154                 for_each_power_domain(domain, power_well->domains)
3155                         domains_count += power_domains->domain_use_count[domain];
3156
3157                 if (power_well->count != domains_count) {
3158                         DRM_ERROR("power well %s refcount/domain refcount mismatch "
3159                                   "(refcount %d/domains refcount %d)\n",
3160                                   power_well->name, power_well->count,
3161                                   domains_count);
3162                         dump_domain_info = true;
3163                 }
3164         }
3165
3166         if (dump_domain_info) {
3167                 static bool dumped;
3168
3169                 if (!dumped) {
3170                         intel_power_domains_dump_info(dev_priv);
3171                         dumped = true;
3172                 }
3173         }
3174
3175         mutex_unlock(&power_domains->lock);
3176 }
3177
3178 /**
3179  * intel_runtime_pm_get - grab a runtime pm reference
3180  * @dev_priv: i915 device instance
3181  *
3182  * This function grabs a device-level runtime pm reference (mostly used for GEM
3183  * code to ensure the GTT or GT is on) and ensures that it is powered up.
3184  *
3185  * Any runtime pm reference obtained by this function must have a symmetric
3186  * call to intel_runtime_pm_put() to release the reference again.
3187  */
3188 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
3189 {
3190         struct pci_dev *pdev = dev_priv->drm.pdev;
3191         struct device *kdev = &pdev->dev;
3192         int ret;
3193
3194         ret = pm_runtime_get_sync(kdev);
3195         WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
3196
3197         atomic_inc(&dev_priv->pm.wakeref_count);
3198         assert_rpm_wakelock_held(dev_priv);
3199 }
3200
3201 /**
3202  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
3203  * @dev_priv: i915 device instance
3204  *
3205  * This function grabs a device-level runtime pm reference if the device is
3206  * already in use and ensures that it is powered up.
3207  *
3208  * Any runtime pm reference obtained by this function must have a symmetric
3209  * call to intel_runtime_pm_put() to release the reference again.
3210  */
3211 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
3212 {
3213         struct pci_dev *pdev = dev_priv->drm.pdev;
3214         struct device *kdev = &pdev->dev;
3215
3216         if (IS_ENABLED(CONFIG_PM)) {
3217                 int ret = pm_runtime_get_if_in_use(kdev);
3218
3219                 /*
3220                  * In cases runtime PM is disabled by the RPM core and we get
3221                  * an -EINVAL return value we are not supposed to call this
3222                  * function, since the power state is undefined. This applies
3223                  * atm to the late/early system suspend/resume handlers.
3224                  */
3225                 WARN_ONCE(ret < 0,
3226                           "pm_runtime_get_if_in_use() failed: %d\n", ret);
3227                 if (ret <= 0)
3228                         return false;
3229         }
3230
3231         atomic_inc(&dev_priv->pm.wakeref_count);
3232         assert_rpm_wakelock_held(dev_priv);
3233
3234         return true;
3235 }
3236
3237 /**
3238  * intel_runtime_pm_get_noresume - grab a runtime pm reference
3239  * @dev_priv: i915 device instance
3240  *
3241  * This function grabs a device-level runtime pm reference (mostly used for GEM
3242  * code to ensure the GTT or GT is on).
3243  *
3244  * It will _not_ power up the device but instead only check that it's powered
3245  * on.  Therefore it is only valid to call this functions from contexts where
3246  * the device is known to be powered up and where trying to power it up would
3247  * result in hilarity and deadlocks. That pretty much means only the system
3248  * suspend/resume code where this is used to grab runtime pm references for
3249  * delayed setup down in work items.
3250  *
3251  * Any runtime pm reference obtained by this function must have a symmetric
3252  * call to intel_runtime_pm_put() to release the reference again.
3253  */
3254 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
3255 {
3256         struct pci_dev *pdev = dev_priv->drm.pdev;
3257         struct device *kdev = &pdev->dev;
3258
3259         assert_rpm_wakelock_held(dev_priv);
3260         pm_runtime_get_noresume(kdev);
3261
3262         atomic_inc(&dev_priv->pm.wakeref_count);
3263 }
3264
3265 /**
3266  * intel_runtime_pm_put - release a runtime pm reference
3267  * @dev_priv: i915 device instance
3268  *
3269  * This function drops the device-level runtime pm reference obtained by
3270  * intel_runtime_pm_get() and might power down the corresponding
3271  * hardware block right away if this is the last reference.
3272  */
3273 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
3274 {
3275         struct pci_dev *pdev = dev_priv->drm.pdev;
3276         struct device *kdev = &pdev->dev;
3277
3278         assert_rpm_wakelock_held(dev_priv);
3279         atomic_dec(&dev_priv->pm.wakeref_count);
3280
3281         pm_runtime_mark_last_busy(kdev);
3282         pm_runtime_put_autosuspend(kdev);
3283 }
3284
3285 /**
3286  * intel_runtime_pm_enable - enable runtime pm
3287  * @dev_priv: i915 device instance
3288  *
3289  * This function enables runtime pm at the end of the driver load sequence.
3290  *
3291  * Note that this function does currently not enable runtime pm for the
3292  * subordinate display power domains. That is only done on the first modeset
3293  * using intel_display_set_init_power().
3294  */
3295 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
3296 {
3297         struct pci_dev *pdev = dev_priv->drm.pdev;
3298         struct device *kdev = &pdev->dev;
3299
3300         pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
3301         pm_runtime_mark_last_busy(kdev);
3302
3303         /*
3304          * Take a permanent reference to disable the RPM functionality and drop
3305          * it only when unloading the driver. Use the low level get/put helpers,
3306          * so the driver's own RPM reference tracking asserts also work on
3307          * platforms without RPM support.
3308          */
3309         if (!HAS_RUNTIME_PM(dev_priv)) {
3310                 int ret;
3311
3312                 pm_runtime_dont_use_autosuspend(kdev);
3313                 ret = pm_runtime_get_sync(kdev);
3314                 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
3315         } else {
3316                 pm_runtime_use_autosuspend(kdev);
3317         }
3318
3319         /*
3320          * The core calls the driver load handler with an RPM reference held.
3321          * We drop that here and will reacquire it during unloading in
3322          * intel_power_domains_fini().
3323          */
3324         pm_runtime_put_autosuspend(kdev);
3325 }