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Merge tag 'v4.15-rc1' into drm-misc-fixes
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / vc4 / vc4_hdmi.c
1 /*
2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /**
21 * DOC: VC4 Falcon HDMI module
22 *
23 * The HDMI core has a state machine and a PHY. On BCM2835, most of
24 * the unit operates off of the HSM clock from CPRMAN. It also
25 * internally uses the PLLH_PIX clock for the PHY.
26 *
27 * HDMI infoframes are kept within a small packet ram, where each
28 * packet can be individually enabled for including in a frame.
29 *
30 * HDMI audio is implemented entirely within the HDMI IP block. A
31 * register in the HDMI encoder takes SPDIF frames from the DMA engine
32 * and transfers them over an internal MAI (multi-channel audio
33 * interconnect) bus to the encoder side for insertion into the video
34 * blank regions.
35 *
36 * The driver's HDMI encoder does not yet support power management.
37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
38 * continuously running, and only the HDMI logic and packet ram are
39 * powered off/on at disable/enable time.
40 *
41 * The driver does not yet support CEC control, though the HDMI
42 * encoder block has CEC support.
43 */
44
45 #include <drm/drm_atomic_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_edid.h>
48 #include <linux/clk.h>
49 #include <linux/component.h>
50 #include <linux/i2c.h>
51 #include <linux/of_address.h>
52 #include <linux/of_gpio.h>
53 #include <linux/of_platform.h>
54 #include <linux/pm_runtime.h>
55 #include <linux/rational.h>
56 #include <sound/dmaengine_pcm.h>
57 #include <sound/pcm_drm_eld.h>
58 #include <sound/pcm_params.h>
59 #include <sound/soc.h>
60 #include "media/cec.h"
61 #include "vc4_drv.h"
62 #include "vc4_regs.h"
63
64 #define HSM_CLOCK_FREQ 163682864
65 #define CEC_CLOCK_FREQ 40000
66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
67
68 /* HDMI audio information */
69 struct vc4_hdmi_audio {
70 struct snd_soc_card card;
71 struct snd_soc_dai_link link;
72 int samplerate;
73 int channels;
74 struct snd_dmaengine_dai_dma_data dma_data;
75 struct snd_pcm_substream *substream;
76 };
77
78 /* General HDMI hardware state. */
79 struct vc4_hdmi {
80 struct platform_device *pdev;
81
82 struct drm_encoder *encoder;
83 struct drm_connector *connector;
84
85 struct vc4_hdmi_audio audio;
86
87 struct i2c_adapter *ddc;
88 void __iomem *hdmicore_regs;
89 void __iomem *hd_regs;
90 int hpd_gpio;
91 bool hpd_active_low;
92
93 struct cec_adapter *cec_adap;
94 struct cec_msg cec_rx_msg;
95 bool cec_tx_ok;
96 bool cec_irq_was_rx;
97
98 struct clk *pixel_clock;
99 struct clk *hsm_clock;
100 };
101
102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
106
107 /* VC4 HDMI encoder KMS struct */
108 struct vc4_hdmi_encoder {
109 struct vc4_encoder base;
110 bool hdmi_monitor;
111 bool limited_rgb_range;
112 bool rgb_range_selectable;
113 };
114
115 static inline struct vc4_hdmi_encoder *
116 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
117 {
118 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
119 }
120
121 /* VC4 HDMI connector KMS struct */
122 struct vc4_hdmi_connector {
123 struct drm_connector base;
124
125 /* Since the connector is attached to just the one encoder,
126 * this is the reference to it so we can do the best_encoder()
127 * hook.
128 */
129 struct drm_encoder *encoder;
130 };
131
132 static inline struct vc4_hdmi_connector *
133 to_vc4_hdmi_connector(struct drm_connector *connector)
134 {
135 return container_of(connector, struct vc4_hdmi_connector, base);
136 }
137
138 #define HDMI_REG(reg) { reg, #reg }
139 static const struct {
140 u32 reg;
141 const char *name;
142 } hdmi_regs[] = {
143 HDMI_REG(VC4_HDMI_CORE_REV),
144 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
145 HDMI_REG(VC4_HDMI_HOTPLUG_INT),
146 HDMI_REG(VC4_HDMI_HOTPLUG),
147 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
148 HDMI_REG(VC4_HDMI_MAI_CONFIG),
149 HDMI_REG(VC4_HDMI_MAI_FORMAT),
150 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
151 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
152 HDMI_REG(VC4_HDMI_HORZA),
153 HDMI_REG(VC4_HDMI_HORZB),
154 HDMI_REG(VC4_HDMI_FIFO_CTL),
155 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
156 HDMI_REG(VC4_HDMI_VERTA0),
157 HDMI_REG(VC4_HDMI_VERTA1),
158 HDMI_REG(VC4_HDMI_VERTB0),
159 HDMI_REG(VC4_HDMI_VERTB1),
160 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
161 HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
162
163 HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
164 HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
165 HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
166 HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
167 HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
168 HDMI_REG(VC4_HDMI_CPU_STATUS),
169 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
170
171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
174 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
178 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
179 };
180
181 static const struct {
182 u32 reg;
183 const char *name;
184 } hd_regs[] = {
185 HDMI_REG(VC4_HD_M_CTL),
186 HDMI_REG(VC4_HD_MAI_CTL),
187 HDMI_REG(VC4_HD_MAI_THR),
188 HDMI_REG(VC4_HD_MAI_FMT),
189 HDMI_REG(VC4_HD_MAI_SMP),
190 HDMI_REG(VC4_HD_VID_CTL),
191 HDMI_REG(VC4_HD_CSC_CTL),
192 HDMI_REG(VC4_HD_FRAME_COUNT),
193 };
194
195 #ifdef CONFIG_DEBUG_FS
196 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
197 {
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *dev = node->minor->dev;
200 struct vc4_dev *vc4 = to_vc4_dev(dev);
201 int i;
202
203 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
204 seq_printf(m, "%s (0x%04x): 0x%08x\n",
205 hdmi_regs[i].name, hdmi_regs[i].reg,
206 HDMI_READ(hdmi_regs[i].reg));
207 }
208
209 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
210 seq_printf(m, "%s (0x%04x): 0x%08x\n",
211 hd_regs[i].name, hd_regs[i].reg,
212 HD_READ(hd_regs[i].reg));
213 }
214
215 return 0;
216 }
217 #endif /* CONFIG_DEBUG_FS */
218
219 static void vc4_hdmi_dump_regs(struct drm_device *dev)
220 {
221 struct vc4_dev *vc4 = to_vc4_dev(dev);
222 int i;
223
224 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
225 DRM_INFO("0x%04x (%s): 0x%08x\n",
226 hdmi_regs[i].reg, hdmi_regs[i].name,
227 HDMI_READ(hdmi_regs[i].reg));
228 }
229 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
230 DRM_INFO("0x%04x (%s): 0x%08x\n",
231 hd_regs[i].reg, hd_regs[i].name,
232 HD_READ(hd_regs[i].reg));
233 }
234 }
235
236 static enum drm_connector_status
237 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
238 {
239 struct drm_device *dev = connector->dev;
240 struct vc4_dev *vc4 = to_vc4_dev(dev);
241
242 if (vc4->hdmi->hpd_gpio) {
243 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
244 vc4->hdmi->hpd_active_low)
245 return connector_status_connected;
246 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
247 return connector_status_disconnected;
248 }
249
250 if (drm_probe_ddc(vc4->hdmi->ddc))
251 return connector_status_connected;
252
253 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
254 return connector_status_connected;
255 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
256 return connector_status_disconnected;
257 }
258
259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
260 {
261 drm_connector_unregister(connector);
262 drm_connector_cleanup(connector);
263 }
264
265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
266 {
267 struct vc4_hdmi_connector *vc4_connector =
268 to_vc4_hdmi_connector(connector);
269 struct drm_encoder *encoder = vc4_connector->encoder;
270 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
271 struct drm_device *dev = connector->dev;
272 struct vc4_dev *vc4 = to_vc4_dev(dev);
273 int ret = 0;
274 struct edid *edid;
275
276 edid = drm_get_edid(connector, vc4->hdmi->ddc);
277 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
278 if (!edid)
279 return -ENODEV;
280
281 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
282
283 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
284 vc4_encoder->rgb_range_selectable =
285 drm_rgb_quant_range_selectable(edid);
286 }
287
288 drm_mode_connector_update_edid_property(connector, edid);
289 ret = drm_add_edid_modes(connector, edid);
290 drm_edid_to_eld(connector, edid);
291 kfree(edid);
292
293 return ret;
294 }
295
296 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
297 .detect = vc4_hdmi_connector_detect,
298 .fill_modes = drm_helper_probe_single_connector_modes,
299 .destroy = vc4_hdmi_connector_destroy,
300 .reset = drm_atomic_helper_connector_reset,
301 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
302 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
303 };
304
305 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
306 .get_modes = vc4_hdmi_connector_get_modes,
307 };
308
309 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
310 struct drm_encoder *encoder)
311 {
312 struct drm_connector *connector;
313 struct vc4_hdmi_connector *hdmi_connector;
314
315 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
316 GFP_KERNEL);
317 if (!hdmi_connector)
318 return ERR_PTR(-ENOMEM);
319 connector = &hdmi_connector->base;
320
321 hdmi_connector->encoder = encoder;
322
323 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
324 DRM_MODE_CONNECTOR_HDMIA);
325 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
326
327 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
328 DRM_CONNECTOR_POLL_DISCONNECT);
329
330 connector->interlace_allowed = 1;
331 connector->doublescan_allowed = 0;
332
333 drm_mode_connector_attach_encoder(connector, encoder);
334
335 return connector;
336 }
337
338 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
339 {
340 drm_encoder_cleanup(encoder);
341 }
342
343 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
344 .destroy = vc4_hdmi_encoder_destroy,
345 };
346
347 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
348 enum hdmi_infoframe_type type)
349 {
350 struct drm_device *dev = encoder->dev;
351 struct vc4_dev *vc4 = to_vc4_dev(dev);
352 u32 packet_id = type - 0x80;
353
354 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
355 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
356
357 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
358 BIT(packet_id)), 100);
359 }
360
361 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
362 union hdmi_infoframe *frame)
363 {
364 struct drm_device *dev = encoder->dev;
365 struct vc4_dev *vc4 = to_vc4_dev(dev);
366 u32 packet_id = frame->any.type - 0x80;
367 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
368 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
369 ssize_t len, i;
370 int ret;
371
372 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
373 VC4_HDMI_RAM_PACKET_ENABLE),
374 "Packet RAM has to be on to store the packet.");
375
376 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
377 if (len < 0)
378 return;
379
380 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
381 if (ret) {
382 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
383 return;
384 }
385
386 for (i = 0; i < len; i += 7) {
387 HDMI_WRITE(packet_reg,
388 buffer[i + 0] << 0 |
389 buffer[i + 1] << 8 |
390 buffer[i + 2] << 16);
391 packet_reg += 4;
392
393 HDMI_WRITE(packet_reg,
394 buffer[i + 3] << 0 |
395 buffer[i + 4] << 8 |
396 buffer[i + 5] << 16 |
397 buffer[i + 6] << 24);
398 packet_reg += 4;
399 }
400
401 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
402 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
403 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
404 BIT(packet_id)), 100);
405 if (ret)
406 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
407 }
408
409 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
410 {
411 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
412 struct drm_crtc *crtc = encoder->crtc;
413 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
414 union hdmi_infoframe frame;
415 int ret;
416
417 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
418 if (ret < 0) {
419 DRM_ERROR("couldn't fill AVI infoframe\n");
420 return;
421 }
422
423 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
424 vc4_encoder->limited_rgb_range ?
425 HDMI_QUANTIZATION_RANGE_LIMITED :
426 HDMI_QUANTIZATION_RANGE_FULL,
427 vc4_encoder->rgb_range_selectable,
428 false);
429
430 vc4_hdmi_write_infoframe(encoder, &frame);
431 }
432
433 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
434 {
435 union hdmi_infoframe frame;
436 int ret;
437
438 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
439 if (ret < 0) {
440 DRM_ERROR("couldn't fill SPD infoframe\n");
441 return;
442 }
443
444 frame.spd.sdi = HDMI_SPD_SDI_PC;
445
446 vc4_hdmi_write_infoframe(encoder, &frame);
447 }
448
449 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
450 {
451 struct drm_device *drm = encoder->dev;
452 struct vc4_dev *vc4 = drm->dev_private;
453 struct vc4_hdmi *hdmi = vc4->hdmi;
454 union hdmi_infoframe frame;
455 int ret;
456
457 ret = hdmi_audio_infoframe_init(&frame.audio);
458
459 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
460 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
461 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
462 frame.audio.channels = hdmi->audio.channels;
463
464 vc4_hdmi_write_infoframe(encoder, &frame);
465 }
466
467 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
468 {
469 vc4_hdmi_set_avi_infoframe(encoder);
470 vc4_hdmi_set_spd_infoframe(encoder);
471 }
472
473 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
474 {
475 struct drm_device *dev = encoder->dev;
476 struct vc4_dev *vc4 = to_vc4_dev(dev);
477 struct vc4_hdmi *hdmi = vc4->hdmi;
478 int ret;
479
480 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
481
482 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
483 HD_WRITE(VC4_HD_VID_CTL,
484 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
485
486 clk_disable_unprepare(hdmi->pixel_clock);
487
488 ret = pm_runtime_put(&hdmi->pdev->dev);
489 if (ret < 0)
490 DRM_ERROR("Failed to release power domain: %d\n", ret);
491 }
492
493 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
494 {
495 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
496 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
497 struct drm_device *dev = encoder->dev;
498 struct vc4_dev *vc4 = to_vc4_dev(dev);
499 struct vc4_hdmi *hdmi = vc4->hdmi;
500 bool debug_dump_regs = false;
501 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
502 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
503 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
504 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
505 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
506 VC4_HDMI_VERTA_VSP) |
507 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
508 VC4_HDMI_VERTA_VFP) |
509 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
510 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
511 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
512 VC4_HDMI_VERTB_VBP));
513 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
514 VC4_SET_FIELD(mode->crtc_vtotal -
515 mode->crtc_vsync_end -
516 interlaced,
517 VC4_HDMI_VERTB_VBP));
518 u32 csc_ctl;
519 int ret;
520
521 ret = pm_runtime_get_sync(&hdmi->pdev->dev);
522 if (ret < 0) {
523 DRM_ERROR("Failed to retain power domain: %d\n", ret);
524 return;
525 }
526
527 ret = clk_set_rate(hdmi->pixel_clock,
528 mode->clock * 1000 *
529 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
530 if (ret) {
531 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
532 return;
533 }
534
535 ret = clk_prepare_enable(hdmi->pixel_clock);
536 if (ret) {
537 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
538 return;
539 }
540
541 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
542 VC4_HDMI_SW_RESET_HDMI |
543 VC4_HDMI_SW_RESET_FORMAT_DETECT);
544
545 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
546
547 /* PHY should be in reset, like
548 * vc4_hdmi_encoder_disable() does.
549 */
550 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
551
552 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
553
554 if (debug_dump_regs) {
555 DRM_INFO("HDMI regs before:\n");
556 vc4_hdmi_dump_regs(dev);
557 }
558
559 HD_WRITE(VC4_HD_VID_CTL, 0);
560
561 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
562 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
563 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
564 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
565
566 HDMI_WRITE(VC4_HDMI_HORZA,
567 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
568 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
569 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
570 VC4_HDMI_HORZA_HAP));
571
572 HDMI_WRITE(VC4_HDMI_HORZB,
573 VC4_SET_FIELD((mode->htotal -
574 mode->hsync_end) * pixel_rep,
575 VC4_HDMI_HORZB_HBP) |
576 VC4_SET_FIELD((mode->hsync_end -
577 mode->hsync_start) * pixel_rep,
578 VC4_HDMI_HORZB_HSP) |
579 VC4_SET_FIELD((mode->hsync_start -
580 mode->hdisplay) * pixel_rep,
581 VC4_HDMI_HORZB_HFP));
582
583 HDMI_WRITE(VC4_HDMI_VERTA0, verta);
584 HDMI_WRITE(VC4_HDMI_VERTA1, verta);
585
586 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
587 HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
588
589 HD_WRITE(VC4_HD_VID_CTL,
590 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
591 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
592
593 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
594 VC4_HD_CSC_CTL_ORDER);
595
596 if (vc4_encoder->hdmi_monitor &&
597 drm_default_rgb_quant_range(mode) ==
598 HDMI_QUANTIZATION_RANGE_LIMITED) {
599 /* CEA VICs other than #1 requre limited range RGB
600 * output unless overridden by an AVI infoframe.
601 * Apply a colorspace conversion to squash 0-255 down
602 * to 16-235. The matrix here is:
603 *
604 * [ 0 0 0.8594 16]
605 * [ 0 0.8594 0 16]
606 * [ 0.8594 0 0 16]
607 * [ 0 0 0 1]
608 */
609 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
610 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
611 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
612 VC4_HD_CSC_CTL_MODE);
613
614 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
615 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
616 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
617 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
618 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
619 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
620 vc4_encoder->limited_rgb_range = true;
621 } else {
622 vc4_encoder->limited_rgb_range = false;
623 }
624
625 /* The RGB order applies even when CSC is disabled. */
626 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
627
628 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
629
630 if (debug_dump_regs) {
631 DRM_INFO("HDMI regs after:\n");
632 vc4_hdmi_dump_regs(dev);
633 }
634
635 HD_WRITE(VC4_HD_VID_CTL,
636 HD_READ(VC4_HD_VID_CTL) |
637 VC4_HD_VID_CTL_ENABLE |
638 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
639 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
640
641 if (vc4_encoder->hdmi_monitor) {
642 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
643 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
644 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
645
646 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
647 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
648 WARN_ONCE(ret, "Timeout waiting for "
649 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
650 } else {
651 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
652 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
653 ~(VC4_HDMI_RAM_PACKET_ENABLE));
654 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
655 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
656 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
657
658 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
659 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
660 WARN_ONCE(ret, "Timeout waiting for "
661 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
662 }
663
664 if (vc4_encoder->hdmi_monitor) {
665 u32 drift;
666
667 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
668 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
669 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
670 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
671 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
672
673 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
674 VC4_HDMI_RAM_PACKET_ENABLE);
675
676 vc4_hdmi_set_infoframes(encoder);
677
678 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
679 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
680
681 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
682 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
683 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
684 drift | VC4_HDMI_FIFO_CTL_RECENTER);
685 udelay(1000);
686 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
687 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
688 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
689 drift | VC4_HDMI_FIFO_CTL_RECENTER);
690
691 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
692 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
693 WARN_ONCE(ret, "Timeout waiting for "
694 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
695 }
696 }
697
698 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
699 .disable = vc4_hdmi_encoder_disable,
700 .enable = vc4_hdmi_encoder_enable,
701 };
702
703 /* HDMI audio codec callbacks */
704 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
705 {
706 struct drm_device *drm = hdmi->encoder->dev;
707 struct vc4_dev *vc4 = to_vc4_dev(drm);
708 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
709 unsigned long n, m;
710
711 rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
712 VC4_HD_MAI_SMP_N_MASK >>
713 VC4_HD_MAI_SMP_N_SHIFT,
714 (VC4_HD_MAI_SMP_M_MASK >>
715 VC4_HD_MAI_SMP_M_SHIFT) + 1,
716 &n, &m);
717
718 HD_WRITE(VC4_HD_MAI_SMP,
719 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
720 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
721 }
722
723 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
724 {
725 struct drm_encoder *encoder = hdmi->encoder;
726 struct drm_crtc *crtc = encoder->crtc;
727 struct drm_device *drm = encoder->dev;
728 struct vc4_dev *vc4 = to_vc4_dev(drm);
729 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
730 u32 samplerate = hdmi->audio.samplerate;
731 u32 n, cts;
732 u64 tmp;
733
734 n = 128 * samplerate / 1000;
735 tmp = (u64)(mode->clock * 1000) * n;
736 do_div(tmp, 128 * samplerate);
737 cts = tmp;
738
739 HDMI_WRITE(VC4_HDMI_CRP_CFG,
740 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
741 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
742
743 /*
744 * We could get slightly more accurate clocks in some cases by
745 * providing a CTS_1 value. The two CTS values are alternated
746 * between based on the period fields
747 */
748 HDMI_WRITE(VC4_HDMI_CTS_0, cts);
749 HDMI_WRITE(VC4_HDMI_CTS_1, cts);
750 }
751
752 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
753 {
754 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
755
756 return snd_soc_card_get_drvdata(card);
757 }
758
759 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
760 struct snd_soc_dai *dai)
761 {
762 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
763 struct drm_encoder *encoder = hdmi->encoder;
764 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
765 int ret;
766
767 if (hdmi->audio.substream && hdmi->audio.substream != substream)
768 return -EINVAL;
769
770 hdmi->audio.substream = substream;
771
772 /*
773 * If the HDMI encoder hasn't probed, or the encoder is
774 * currently in DVI mode, treat the codec dai as missing.
775 */
776 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
777 VC4_HDMI_RAM_PACKET_ENABLE))
778 return -ENODEV;
779
780 ret = snd_pcm_hw_constraint_eld(substream->runtime,
781 hdmi->connector->eld);
782 if (ret)
783 return ret;
784
785 return 0;
786 }
787
788 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
789 {
790 return 0;
791 }
792
793 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
794 {
795 struct drm_encoder *encoder = hdmi->encoder;
796 struct drm_device *drm = encoder->dev;
797 struct device *dev = &hdmi->pdev->dev;
798 struct vc4_dev *vc4 = to_vc4_dev(drm);
799 int ret;
800
801 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
802 if (ret)
803 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
804
805 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
806 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
807 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
808 }
809
810 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
811 struct snd_soc_dai *dai)
812 {
813 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
814
815 if (substream != hdmi->audio.substream)
816 return;
817
818 vc4_hdmi_audio_reset(hdmi);
819
820 hdmi->audio.substream = NULL;
821 }
822
823 /* HDMI audio codec callbacks */
824 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
825 struct snd_pcm_hw_params *params,
826 struct snd_soc_dai *dai)
827 {
828 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
829 struct drm_encoder *encoder = hdmi->encoder;
830 struct drm_device *drm = encoder->dev;
831 struct device *dev = &hdmi->pdev->dev;
832 struct vc4_dev *vc4 = to_vc4_dev(drm);
833 u32 audio_packet_config, channel_mask;
834 u32 channel_map, i;
835
836 if (substream != hdmi->audio.substream)
837 return -EINVAL;
838
839 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
840 params_rate(params), params_width(params),
841 params_channels(params));
842
843 hdmi->audio.channels = params_channels(params);
844 hdmi->audio.samplerate = params_rate(params);
845
846 HD_WRITE(VC4_HD_MAI_CTL,
847 VC4_HD_MAI_CTL_RESET |
848 VC4_HD_MAI_CTL_FLUSH |
849 VC4_HD_MAI_CTL_DLATE |
850 VC4_HD_MAI_CTL_ERRORE |
851 VC4_HD_MAI_CTL_ERRORF);
852
853 vc4_hdmi_audio_set_mai_clock(hdmi);
854
855 audio_packet_config =
856 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
857 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
858 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
859
860 channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
861 audio_packet_config |= VC4_SET_FIELD(channel_mask,
862 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
863
864 /* Set the MAI threshold. This logic mimics the firmware's. */
865 if (hdmi->audio.samplerate > 96000) {
866 HD_WRITE(VC4_HD_MAI_THR,
867 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
868 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
869 } else if (hdmi->audio.samplerate > 48000) {
870 HD_WRITE(VC4_HD_MAI_THR,
871 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
872 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
873 } else {
874 HD_WRITE(VC4_HD_MAI_THR,
875 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
876 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
877 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
878 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
879 }
880
881 HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
882 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
883 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
884
885 channel_map = 0;
886 for (i = 0; i < 8; i++) {
887 if (channel_mask & BIT(i))
888 channel_map |= i << (3 * i);
889 }
890
891 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
892 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
893 vc4_hdmi_set_n_cts(hdmi);
894
895 return 0;
896 }
897
898 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
899 struct snd_soc_dai *dai)
900 {
901 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
902 struct drm_encoder *encoder = hdmi->encoder;
903 struct drm_device *drm = encoder->dev;
904 struct vc4_dev *vc4 = to_vc4_dev(drm);
905
906 switch (cmd) {
907 case SNDRV_PCM_TRIGGER_START:
908 vc4_hdmi_set_audio_infoframe(encoder);
909 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
910 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
911 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
912 HD_WRITE(VC4_HD_MAI_CTL,
913 VC4_SET_FIELD(hdmi->audio.channels,
914 VC4_HD_MAI_CTL_CHNUM) |
915 VC4_HD_MAI_CTL_ENABLE);
916 break;
917 case SNDRV_PCM_TRIGGER_STOP:
918 HD_WRITE(VC4_HD_MAI_CTL,
919 VC4_HD_MAI_CTL_DLATE |
920 VC4_HD_MAI_CTL_ERRORE |
921 VC4_HD_MAI_CTL_ERRORF);
922 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
923 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
924 VC4_HDMI_TX_PHY_RNG_PWRDN);
925 break;
926 default:
927 break;
928 }
929
930 return 0;
931 }
932
933 static inline struct vc4_hdmi *
934 snd_component_to_hdmi(struct snd_soc_component *component)
935 {
936 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
937
938 return snd_soc_card_get_drvdata(card);
939 }
940
941 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
942 struct snd_ctl_elem_info *uinfo)
943 {
944 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
945 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
946
947 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
948 uinfo->count = sizeof(hdmi->connector->eld);
949
950 return 0;
951 }
952
953 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
954 struct snd_ctl_elem_value *ucontrol)
955 {
956 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
957 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
958
959 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
960 sizeof(hdmi->connector->eld));
961
962 return 0;
963 }
964
965 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
966 {
967 .access = SNDRV_CTL_ELEM_ACCESS_READ |
968 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
969 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
970 .name = "ELD",
971 .info = vc4_hdmi_audio_eld_ctl_info,
972 .get = vc4_hdmi_audio_eld_ctl_get,
973 },
974 };
975
976 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
977 SND_SOC_DAPM_OUTPUT("TX"),
978 };
979
980 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
981 { "TX", NULL, "Playback" },
982 };
983
984 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = {
985 .component_driver = {
986 .controls = vc4_hdmi_audio_controls,
987 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
988 .dapm_widgets = vc4_hdmi_audio_widgets,
989 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
990 .dapm_routes = vc4_hdmi_audio_routes,
991 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
992 },
993 };
994
995 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
996 .startup = vc4_hdmi_audio_startup,
997 .shutdown = vc4_hdmi_audio_shutdown,
998 .hw_params = vc4_hdmi_audio_hw_params,
999 .set_fmt = vc4_hdmi_audio_set_fmt,
1000 .trigger = vc4_hdmi_audio_trigger,
1001 };
1002
1003 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1004 .name = "vc4-hdmi-hifi",
1005 .playback = {
1006 .stream_name = "Playback",
1007 .channels_min = 2,
1008 .channels_max = 8,
1009 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1010 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1011 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1012 SNDRV_PCM_RATE_192000,
1013 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1014 },
1015 };
1016
1017 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1018 .name = "vc4-hdmi-cpu-dai-component",
1019 };
1020
1021 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1022 {
1023 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1024
1025 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1026
1027 return 0;
1028 }
1029
1030 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1031 .name = "vc4-hdmi-cpu-dai",
1032 .probe = vc4_hdmi_audio_cpu_dai_probe,
1033 .playback = {
1034 .stream_name = "Playback",
1035 .channels_min = 1,
1036 .channels_max = 8,
1037 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1038 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1039 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1040 SNDRV_PCM_RATE_192000,
1041 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1042 },
1043 .ops = &vc4_hdmi_audio_dai_ops,
1044 };
1045
1046 static const struct snd_dmaengine_pcm_config pcm_conf = {
1047 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1048 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1049 };
1050
1051 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1052 {
1053 struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1054 struct snd_soc_card *card = &hdmi->audio.card;
1055 struct device *dev = &hdmi->pdev->dev;
1056 const __be32 *addr;
1057 int ret;
1058
1059 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1060 dev_warn(dev,
1061 "'dmas' DT property is missing, no HDMI audio\n");
1062 return 0;
1063 }
1064
1065 /*
1066 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1067 * the bus address specified in the DT, because the physical address
1068 * (the one returned by platform_get_resource()) is not appropriate
1069 * for DMA transfers.
1070 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1071 */
1072 addr = of_get_address(dev->of_node, 1, NULL, NULL);
1073 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1074 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1075 hdmi->audio.dma_data.maxburst = 2;
1076
1077 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1078 if (ret) {
1079 dev_err(dev, "Could not register PCM component: %d\n", ret);
1080 return ret;
1081 }
1082
1083 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1084 &vc4_hdmi_audio_cpu_dai_drv, 1);
1085 if (ret) {
1086 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1087 return ret;
1088 }
1089
1090 /* register codec and codec dai */
1091 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv,
1092 &vc4_hdmi_audio_codec_dai_drv, 1);
1093 if (ret) {
1094 dev_err(dev, "Could not register codec: %d\n", ret);
1095 return ret;
1096 }
1097
1098 dai_link->name = "MAI";
1099 dai_link->stream_name = "MAI PCM";
1100 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1101 dai_link->cpu_dai_name = dev_name(dev);
1102 dai_link->codec_name = dev_name(dev);
1103 dai_link->platform_name = dev_name(dev);
1104
1105 card->dai_link = dai_link;
1106 card->num_links = 1;
1107 card->name = "vc4-hdmi";
1108 card->dev = dev;
1109
1110 /*
1111 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1112 * stores a pointer to the snd card object in dev->driver_data. This
1113 * means we cannot use it for something else. The hdmi back-pointer is
1114 * now stored in card->drvdata and should be retrieved with
1115 * snd_soc_card_get_drvdata() if needed.
1116 */
1117 snd_soc_card_set_drvdata(card, hdmi);
1118 ret = devm_snd_soc_register_card(dev, card);
1119 if (ret) {
1120 dev_err(dev, "Could not register sound card: %d\n", ret);
1121 goto unregister_codec;
1122 }
1123
1124 return 0;
1125
1126 unregister_codec:
1127 snd_soc_unregister_codec(dev);
1128
1129 return ret;
1130 }
1131
1132 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
1133 {
1134 struct device *dev = &hdmi->pdev->dev;
1135
1136 /*
1137 * If drvdata is not set this means the audio card was not
1138 * registered, just skip codec unregistration in this case.
1139 */
1140 if (dev_get_drvdata(dev))
1141 snd_soc_unregister_codec(dev);
1142 }
1143
1144 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1145 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1146 {
1147 struct vc4_dev *vc4 = priv;
1148 struct vc4_hdmi *hdmi = vc4->hdmi;
1149
1150 if (hdmi->cec_irq_was_rx) {
1151 if (hdmi->cec_rx_msg.len)
1152 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1153 } else if (hdmi->cec_tx_ok) {
1154 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1155 0, 0, 0, 0);
1156 } else {
1157 /*
1158 * This CEC implementation makes 1 retry, so if we
1159 * get a NACK, then that means it made 2 attempts.
1160 */
1161 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1162 0, 2, 0, 0);
1163 }
1164 return IRQ_HANDLED;
1165 }
1166
1167 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1168 {
1169 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1170 unsigned int i;
1171
1172 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1173 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1174 for (i = 0; i < msg->len; i += 4) {
1175 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1176
1177 msg->msg[i] = val & 0xff;
1178 msg->msg[i + 1] = (val >> 8) & 0xff;
1179 msg->msg[i + 2] = (val >> 16) & 0xff;
1180 msg->msg[i + 3] = (val >> 24) & 0xff;
1181 }
1182 }
1183
1184 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1185 {
1186 struct vc4_dev *vc4 = priv;
1187 struct vc4_hdmi *hdmi = vc4->hdmi;
1188 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1189 u32 cntrl1, cntrl5;
1190
1191 if (!(stat & VC4_HDMI_CPU_CEC))
1192 return IRQ_NONE;
1193 hdmi->cec_rx_msg.len = 0;
1194 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1195 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1196 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1197 if (hdmi->cec_irq_was_rx) {
1198 vc4_cec_read_msg(vc4, cntrl1);
1199 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1200 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1201 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1202 } else {
1203 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1204 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1205 }
1206 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1207 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1208
1209 return IRQ_WAKE_THREAD;
1210 }
1211
1212 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1213 {
1214 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1215 /* clock period in microseconds */
1216 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1217 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1218
1219 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1220 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1221 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1222 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1223 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1224
1225 if (enable) {
1226 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1227 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1228 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1229 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1230 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1231 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1232 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1233 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1234 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1235 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1236 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1237 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1238 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1239 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1240 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1241 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1242 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1243 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1244 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1245
1246 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1247 } else {
1248 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1249 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1250 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1251 }
1252 return 0;
1253 }
1254
1255 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1256 {
1257 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1258
1259 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1260 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1261 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1262 return 0;
1263 }
1264
1265 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1266 u32 signal_free_time, struct cec_msg *msg)
1267 {
1268 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1269 u32 val;
1270 unsigned int i;
1271
1272 for (i = 0; i < msg->len; i += 4)
1273 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1274 (msg->msg[i]) |
1275 (msg->msg[i + 1] << 8) |
1276 (msg->msg[i + 2] << 16) |
1277 (msg->msg[i + 3] << 24));
1278
1279 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1280 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1281 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1282 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1283 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1284 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1285
1286 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1287 return 0;
1288 }
1289
1290 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1291 .adap_enable = vc4_hdmi_cec_adap_enable,
1292 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1293 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1294 };
1295 #endif
1296
1297 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1298 {
1299 struct platform_device *pdev = to_platform_device(dev);
1300 struct drm_device *drm = dev_get_drvdata(master);
1301 struct vc4_dev *vc4 = drm->dev_private;
1302 struct vc4_hdmi *hdmi;
1303 struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1304 struct device_node *ddc_node;
1305 u32 value;
1306 int ret;
1307
1308 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1309 if (!hdmi)
1310 return -ENOMEM;
1311
1312 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1313 GFP_KERNEL);
1314 if (!vc4_hdmi_encoder)
1315 return -ENOMEM;
1316 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1317 hdmi->encoder = &vc4_hdmi_encoder->base.base;
1318
1319 hdmi->pdev = pdev;
1320 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1321 if (IS_ERR(hdmi->hdmicore_regs))
1322 return PTR_ERR(hdmi->hdmicore_regs);
1323
1324 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1325 if (IS_ERR(hdmi->hd_regs))
1326 return PTR_ERR(hdmi->hd_regs);
1327
1328 hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1329 if (IS_ERR(hdmi->pixel_clock)) {
1330 DRM_ERROR("Failed to get pixel clock\n");
1331 return PTR_ERR(hdmi->pixel_clock);
1332 }
1333 hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1334 if (IS_ERR(hdmi->hsm_clock)) {
1335 DRM_ERROR("Failed to get HDMI state machine clock\n");
1336 return PTR_ERR(hdmi->hsm_clock);
1337 }
1338
1339 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1340 if (!ddc_node) {
1341 DRM_ERROR("Failed to find ddc node in device tree\n");
1342 return -ENODEV;
1343 }
1344
1345 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1346 of_node_put(ddc_node);
1347 if (!hdmi->ddc) {
1348 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1349 return -EPROBE_DEFER;
1350 }
1351
1352 /* This is the rate that is set by the firmware. The number
1353 * needs to be a bit higher than the pixel clock rate
1354 * (generally 148.5Mhz).
1355 */
1356 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1357 if (ret) {
1358 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1359 goto err_put_i2c;
1360 }
1361
1362 ret = clk_prepare_enable(hdmi->hsm_clock);
1363 if (ret) {
1364 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1365 ret);
1366 goto err_put_i2c;
1367 }
1368
1369 /* Only use the GPIO HPD pin if present in the DT, otherwise
1370 * we'll use the HDMI core's register.
1371 */
1372 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1373 enum of_gpio_flags hpd_gpio_flags;
1374
1375 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1376 "hpd-gpios", 0,
1377 &hpd_gpio_flags);
1378 if (hdmi->hpd_gpio < 0) {
1379 ret = hdmi->hpd_gpio;
1380 goto err_unprepare_hsm;
1381 }
1382
1383 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1384 }
1385
1386 vc4->hdmi = hdmi;
1387
1388 /* HDMI core must be enabled. */
1389 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1390 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1391 udelay(1);
1392 HD_WRITE(VC4_HD_M_CTL, 0);
1393
1394 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1395 }
1396 pm_runtime_enable(dev);
1397
1398 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1399 DRM_MODE_ENCODER_TMDS, NULL);
1400 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1401
1402 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1403 if (IS_ERR(hdmi->connector)) {
1404 ret = PTR_ERR(hdmi->connector);
1405 goto err_destroy_encoder;
1406 }
1407 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1408 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1409 vc4, "vc4",
1410 CEC_CAP_TRANSMIT |
1411 CEC_CAP_LOG_ADDRS |
1412 CEC_CAP_PASSTHROUGH |
1413 CEC_CAP_RC, 1);
1414 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1415 if (ret < 0)
1416 goto err_destroy_conn;
1417 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1418 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1419 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1420 /*
1421 * Set the logical address to Unregistered and set the clock
1422 * divider: the hsm_clock rate and this divider setting will
1423 * give a 40 kHz CEC clock.
1424 */
1425 value |= VC4_HDMI_CEC_ADDR_MASK |
1426 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1427 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1428 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1429 vc4_cec_irq_handler,
1430 vc4_cec_irq_handler_thread, 0,
1431 "vc4 hdmi cec", vc4);
1432 if (ret)
1433 goto err_delete_cec_adap;
1434 ret = cec_register_adapter(hdmi->cec_adap, dev);
1435 if (ret < 0)
1436 goto err_delete_cec_adap;
1437 #endif
1438
1439 ret = vc4_hdmi_audio_init(hdmi);
1440 if (ret)
1441 goto err_destroy_encoder;
1442
1443 return 0;
1444
1445 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1446 err_delete_cec_adap:
1447 cec_delete_adapter(hdmi->cec_adap);
1448 err_destroy_conn:
1449 vc4_hdmi_connector_destroy(hdmi->connector);
1450 #endif
1451 err_destroy_encoder:
1452 vc4_hdmi_encoder_destroy(hdmi->encoder);
1453 err_unprepare_hsm:
1454 clk_disable_unprepare(hdmi->hsm_clock);
1455 pm_runtime_disable(dev);
1456 err_put_i2c:
1457 put_device(&hdmi->ddc->dev);
1458
1459 return ret;
1460 }
1461
1462 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1463 void *data)
1464 {
1465 struct drm_device *drm = dev_get_drvdata(master);
1466 struct vc4_dev *vc4 = drm->dev_private;
1467 struct vc4_hdmi *hdmi = vc4->hdmi;
1468
1469 vc4_hdmi_audio_cleanup(hdmi);
1470 cec_unregister_adapter(hdmi->cec_adap);
1471 vc4_hdmi_connector_destroy(hdmi->connector);
1472 vc4_hdmi_encoder_destroy(hdmi->encoder);
1473
1474 clk_disable_unprepare(hdmi->hsm_clock);
1475 pm_runtime_disable(dev);
1476
1477 put_device(&hdmi->ddc->dev);
1478
1479 vc4->hdmi = NULL;
1480 }
1481
1482 static const struct component_ops vc4_hdmi_ops = {
1483 .bind = vc4_hdmi_bind,
1484 .unbind = vc4_hdmi_unbind,
1485 };
1486
1487 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1488 {
1489 return component_add(&pdev->dev, &vc4_hdmi_ops);
1490 }
1491
1492 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1493 {
1494 component_del(&pdev->dev, &vc4_hdmi_ops);
1495 return 0;
1496 }
1497
1498 static const struct of_device_id vc4_hdmi_dt_match[] = {
1499 { .compatible = "brcm,bcm2835-hdmi" },
1500 {}
1501 };
1502
1503 struct platform_driver vc4_hdmi_driver = {
1504 .probe = vc4_hdmi_dev_probe,
1505 .remove = vc4_hdmi_dev_remove,
1506 .driver = {
1507 .name = "vc4_hdmi",
1508 .of_match_table = vc4_hdmi_dt_match,
1509 },
1510 };
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