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[media] rc: Postpone ISR registration
[mirror_ubuntu-bionic-kernel.git] / drivers / media / rc / winbond-cir.c
1 /*
2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
3 * SuperI/O chips.
4 *
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
8 *
9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
11 *
12 * Dedicated to my daughter Matilda, without whose loving attention this
13 * driver would have been finished in half the time and with a fraction
14 * of the bugs.
15 *
16 * Written using:
17 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
18 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
19 * o DSDT dumps
20 *
21 * Supported features:
22 * o IR Receive
23 * o IR Transmit
24 * o Wake-On-CIR functionality
25 *
26 * To do:
27 * o Learning
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License as published by
31 * the Free Software Foundation; either version 2 of the License, or
32 * (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
42 */
43
44 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
46 #include <linux/module.h>
47 #include <linux/pnp.h>
48 #include <linux/interrupt.h>
49 #include <linux/timer.h>
50 #include <linux/leds.h>
51 #include <linux/spinlock.h>
52 #include <linux/pci_ids.h>
53 #include <linux/io.h>
54 #include <linux/bitrev.h>
55 #include <linux/slab.h>
56 #include <linux/wait.h>
57 #include <linux/sched.h>
58 #include <media/rc-core.h>
59
60 #define DRVNAME "winbond-cir"
61
62 /* CEIR Wake-Up Registers, relative to data->wbase */
63 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
64 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
65 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
66 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
67 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
68 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
69 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
70 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
71 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
72 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
73
74 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
75 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
76 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
77 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
78 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
79 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
80
81 /* SP3 Banked Registers, relative to data->sbase */
82 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
83 /* Bank 0 */
84 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
85 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
86 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
87 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
88 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
89 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
90 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
91 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
92 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
93 /* Bank 2 */
94 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
95 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
96 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
97 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
98 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
99 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
100 /* Bank 3 */
101 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
102 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
103 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
104 /* Bank 4 */
105 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
106 /* Bank 5 */
107 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
108 /* Bank 6 */
109 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
110 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
111 /* Bank 7 */
112 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
113 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
114 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
115 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
116 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
117
118 /*
119 * Magic values follow
120 */
121
122 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
123 #define WBCIR_IRQ_NONE 0x00
124 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
125 #define WBCIR_IRQ_RX 0x01
126 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
127 #define WBCIR_IRQ_TX_LOW 0x02
128 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
129 #define WBCIR_IRQ_ERR 0x04
130 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
131 #define WBCIR_IRQ_TX_EMPTY 0x20
132 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
133 #define WBCIR_LED_ENABLE 0x80
134 /* RX data available bit for WBCIR_REG_SP3_LSR */
135 #define WBCIR_RX_AVAIL 0x01
136 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
137 #define WBCIR_RX_OVERRUN 0x02
138 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
139 #define WBCIR_TX_EOT 0x04
140 /* RX disable bit for WBCIR_REG_SP3_ASCR */
141 #define WBCIR_RX_DISABLE 0x20
142 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
143 #define WBCIR_TX_UNDERRUN 0x40
144 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
145 #define WBCIR_EXT_ENABLE 0x01
146 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
147 #define WBCIR_REGSEL_COMPARE 0x10
148 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
149 #define WBCIR_REGSEL_MASK 0x20
150 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
151 #define WBCIR_REG_ADDR0 0x00
152
153 /* Valid banks for the SP3 UART */
154 enum wbcir_bank {
155 WBCIR_BANK_0 = 0x00,
156 WBCIR_BANK_1 = 0x80,
157 WBCIR_BANK_2 = 0xE0,
158 WBCIR_BANK_3 = 0xE4,
159 WBCIR_BANK_4 = 0xE8,
160 WBCIR_BANK_5 = 0xEC,
161 WBCIR_BANK_6 = 0xF0,
162 WBCIR_BANK_7 = 0xF4,
163 };
164
165 /* Supported power-on IR Protocols */
166 enum wbcir_protocol {
167 IR_PROTOCOL_RC5 = 0x0,
168 IR_PROTOCOL_NEC = 0x1,
169 IR_PROTOCOL_RC6 = 0x2,
170 };
171
172 /* Possible states for IR reception */
173 enum wbcir_rxstate {
174 WBCIR_RXSTATE_INACTIVE = 0,
175 WBCIR_RXSTATE_ACTIVE,
176 WBCIR_RXSTATE_ERROR
177 };
178
179 /* Possible states for IR transmission */
180 enum wbcir_txstate {
181 WBCIR_TXSTATE_INACTIVE = 0,
182 WBCIR_TXSTATE_ACTIVE,
183 WBCIR_TXSTATE_DONE,
184 WBCIR_TXSTATE_ERROR
185 };
186
187 /* Misc */
188 #define WBCIR_NAME "Winbond CIR"
189 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
190 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
191 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
192 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
193 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
194 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
195
196 /* Per-device data */
197 struct wbcir_data {
198 spinlock_t spinlock;
199 struct rc_dev *dev;
200 struct led_classdev led;
201
202 unsigned long wbase; /* Wake-Up Baseaddr */
203 unsigned long ebase; /* Enhanced Func. Baseaddr */
204 unsigned long sbase; /* Serial Port Baseaddr */
205 unsigned int irq; /* Serial Port IRQ */
206 u8 irqmask;
207
208 /* RX state */
209 enum wbcir_rxstate rxstate;
210 struct led_trigger *rxtrigger;
211 struct ir_raw_event rxev;
212
213 /* TX state */
214 enum wbcir_txstate txstate;
215 struct led_trigger *txtrigger;
216 u32 txlen;
217 u32 txoff;
218 u32 *txbuf;
219 wait_queue_head_t txwaitq;
220 u8 txmask;
221 u32 txcarrier;
222 };
223
224 static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
225 module_param(protocol, uint, 0444);
226 MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command "
227 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
228
229 static bool invert; /* default = 0 */
230 module_param(invert, bool, 0444);
231 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
232
233 static bool txandrx; /* default = 0 */
234 module_param(txandrx, bool, 0444);
235 MODULE_PARM_DESC(invert, "Allow simultaneous TX and RX");
236
237 static unsigned int wake_sc = 0x800F040C;
238 module_param(wake_sc, uint, 0644);
239 MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
240
241 static unsigned int wake_rc6mode = 6;
242 module_param(wake_rc6mode, uint, 0644);
243 MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command "
244 "(0 = 0, 6 = 6A, default)");
245
246
247
248 /*****************************************************************************
249 *
250 * UTILITY FUNCTIONS
251 *
252 *****************************************************************************/
253
254 /* Caller needs to hold wbcir_lock */
255 static void
256 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
257 {
258 u8 val;
259
260 val = inb(addr);
261 val = ((val & ~mask) | (bits & mask));
262 outb(val, addr);
263 }
264
265 /* Selects the register bank for the serial port */
266 static inline void
267 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
268 {
269 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
270 }
271
272 static inline void
273 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
274 {
275 if (data->irqmask == irqmask)
276 return;
277
278 wbcir_select_bank(data, WBCIR_BANK_0);
279 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
280 data->irqmask = irqmask;
281 }
282
283 static enum led_brightness
284 wbcir_led_brightness_get(struct led_classdev *led_cdev)
285 {
286 struct wbcir_data *data = container_of(led_cdev,
287 struct wbcir_data,
288 led);
289
290 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
291 return LED_FULL;
292 else
293 return LED_OFF;
294 }
295
296 static void
297 wbcir_led_brightness_set(struct led_classdev *led_cdev,
298 enum led_brightness brightness)
299 {
300 struct wbcir_data *data = container_of(led_cdev,
301 struct wbcir_data,
302 led);
303
304 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
305 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
306 WBCIR_LED_ENABLE);
307 }
308
309 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
310 static u8
311 wbcir_to_rc6cells(u8 val)
312 {
313 u8 coded = 0x00;
314 int i;
315
316 val &= 0x0F;
317 for (i = 0; i < 4; i++) {
318 if (val & 0x01)
319 coded |= 0x02 << (i * 2);
320 else
321 coded |= 0x01 << (i * 2);
322 val >>= 1;
323 }
324
325 return coded;
326 }
327
328 /*****************************************************************************
329 *
330 * INTERRUPT FUNCTIONS
331 *
332 *****************************************************************************/
333
334 static void
335 wbcir_idle_rx(struct rc_dev *dev, bool idle)
336 {
337 struct wbcir_data *data = dev->priv;
338
339 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) {
340 data->rxstate = WBCIR_RXSTATE_ACTIVE;
341 led_trigger_event(data->rxtrigger, LED_FULL);
342 }
343
344 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE)
345 /* Tell hardware to go idle by setting RXINACTIVE */
346 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
347 }
348
349 static void
350 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
351 {
352 u8 irdata;
353 DEFINE_IR_RAW_EVENT(rawir);
354
355 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
356 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
357 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
358 if (data->rxstate == WBCIR_RXSTATE_ERROR)
359 continue;
360 rawir.pulse = irdata & 0x80 ? false : true;
361 rawir.duration = US_TO_NS((irdata & 0x7F) * 10);
362 ir_raw_event_store_with_filter(data->dev, &rawir);
363 }
364
365 /* Check if we should go idle */
366 if (data->dev->idle) {
367 led_trigger_event(data->rxtrigger, LED_OFF);
368 data->rxstate = WBCIR_RXSTATE_INACTIVE;
369 }
370
371 ir_raw_event_handle(data->dev);
372 }
373
374 static void
375 wbcir_irq_tx(struct wbcir_data *data)
376 {
377 unsigned int space;
378 unsigned int used;
379 u8 bytes[16];
380 u8 byte;
381
382 if (!data->txbuf)
383 return;
384
385 switch (data->txstate) {
386 case WBCIR_TXSTATE_INACTIVE:
387 /* TX FIFO empty */
388 space = 16;
389 led_trigger_event(data->txtrigger, LED_FULL);
390 break;
391 case WBCIR_TXSTATE_ACTIVE:
392 /* TX FIFO low (3 bytes or less) */
393 space = 13;
394 break;
395 case WBCIR_TXSTATE_ERROR:
396 space = 0;
397 break;
398 default:
399 return;
400 }
401
402 /*
403 * TX data is run-length coded in bytes: YXXXXXXX
404 * Y = space (1) or pulse (0)
405 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
406 */
407 for (used = 0; used < space && data->txoff != data->txlen; used++) {
408 if (data->txbuf[data->txoff] == 0) {
409 data->txoff++;
410 continue;
411 }
412 byte = min((u32)0x80, data->txbuf[data->txoff]);
413 data->txbuf[data->txoff] -= byte;
414 byte--;
415 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
416 bytes[used] = byte;
417 }
418
419 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
420 data->txoff++;
421
422 if (used == 0) {
423 /* Finished */
424 if (data->txstate == WBCIR_TXSTATE_ERROR)
425 /* Clear TX underrun bit */
426 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
427 else
428 data->txstate = WBCIR_TXSTATE_DONE;
429 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
430 led_trigger_event(data->txtrigger, LED_OFF);
431 wake_up(&data->txwaitq);
432 } else if (data->txoff == data->txlen) {
433 /* At the end of transmission, tell the hw before last byte */
434 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
435 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
436 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
437 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
438 WBCIR_IRQ_TX_EMPTY);
439 } else {
440 /* More data to follow... */
441 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
442 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
443 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
444 WBCIR_IRQ_TX_LOW);
445 data->txstate = WBCIR_TXSTATE_ACTIVE;
446 }
447 }
448 }
449
450 static irqreturn_t
451 wbcir_irq_handler(int irqno, void *cookie)
452 {
453 struct pnp_dev *device = cookie;
454 struct wbcir_data *data = pnp_get_drvdata(device);
455 unsigned long flags;
456 u8 status;
457
458 spin_lock_irqsave(&data->spinlock, flags);
459 wbcir_select_bank(data, WBCIR_BANK_0);
460 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
461 status &= data->irqmask;
462
463 if (!status) {
464 spin_unlock_irqrestore(&data->spinlock, flags);
465 return IRQ_NONE;
466 }
467
468 if (status & WBCIR_IRQ_ERR) {
469 /* RX overflow? (read clears bit) */
470 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
471 data->rxstate = WBCIR_RXSTATE_ERROR;
472 ir_raw_event_reset(data->dev);
473 }
474
475 /* TX underflow? */
476 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
477 data->txstate = WBCIR_TXSTATE_ERROR;
478 }
479
480 if (status & WBCIR_IRQ_RX)
481 wbcir_irq_rx(data, device);
482
483 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
484 wbcir_irq_tx(data);
485
486 spin_unlock_irqrestore(&data->spinlock, flags);
487 return IRQ_HANDLED;
488 }
489
490 /*****************************************************************************
491 *
492 * RC-CORE INTERFACE FUNCTIONS
493 *
494 *****************************************************************************/
495
496 static int
497 wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
498 {
499 struct wbcir_data *data = dev->priv;
500 unsigned long flags;
501 u8 val;
502 u32 freq;
503
504 freq = DIV_ROUND_CLOSEST(carrier, 1000);
505 if (freq < 30 || freq > 60)
506 return -EINVAL;
507
508 switch (freq) {
509 case 58:
510 case 59:
511 case 60:
512 val = freq - 58;
513 freq *= 1000;
514 break;
515 case 57:
516 val = freq - 27;
517 freq = 56900;
518 break;
519 default:
520 val = freq - 27;
521 freq *= 1000;
522 break;
523 }
524
525 spin_lock_irqsave(&data->spinlock, flags);
526 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
527 spin_unlock_irqrestore(&data->spinlock, flags);
528 return -EBUSY;
529 }
530
531 if (data->txcarrier != freq) {
532 wbcir_select_bank(data, WBCIR_BANK_7);
533 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
534 data->txcarrier = freq;
535 }
536
537 spin_unlock_irqrestore(&data->spinlock, flags);
538 return 0;
539 }
540
541 static int
542 wbcir_txmask(struct rc_dev *dev, u32 mask)
543 {
544 struct wbcir_data *data = dev->priv;
545 unsigned long flags;
546 u8 val;
547
548 /* Four outputs, only one output can be enabled at a time */
549 switch (mask) {
550 case 0x1:
551 val = 0x0;
552 break;
553 case 0x2:
554 val = 0x1;
555 break;
556 case 0x4:
557 val = 0x2;
558 break;
559 case 0x8:
560 val = 0x3;
561 break;
562 default:
563 return -EINVAL;
564 }
565
566 spin_lock_irqsave(&data->spinlock, flags);
567 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
568 spin_unlock_irqrestore(&data->spinlock, flags);
569 return -EBUSY;
570 }
571
572 if (data->txmask != mask) {
573 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
574 data->txmask = mask;
575 }
576
577 spin_unlock_irqrestore(&data->spinlock, flags);
578 return 0;
579 }
580
581 static int
582 wbcir_tx(struct rc_dev *dev, unsigned *buf, unsigned count)
583 {
584 struct wbcir_data *data = dev->priv;
585 unsigned i;
586 unsigned long flags;
587
588 /* Not sure if this is possible, but better safe than sorry */
589 spin_lock_irqsave(&data->spinlock, flags);
590 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
591 spin_unlock_irqrestore(&data->spinlock, flags);
592 return -EBUSY;
593 }
594
595 /* Convert values to multiples of 10us */
596 for (i = 0; i < count; i++)
597 buf[i] = DIV_ROUND_CLOSEST(buf[i], 10);
598
599 /* Fill the TX fifo once, the irq handler will do the rest */
600 data->txbuf = buf;
601 data->txlen = count;
602 data->txoff = 0;
603 wbcir_irq_tx(data);
604
605 /* Wait for the TX to complete */
606 while (data->txstate == WBCIR_TXSTATE_ACTIVE) {
607 spin_unlock_irqrestore(&data->spinlock, flags);
608 wait_event(data->txwaitq, data->txstate != WBCIR_TXSTATE_ACTIVE);
609 spin_lock_irqsave(&data->spinlock, flags);
610 }
611
612 /* We're done */
613 if (data->txstate == WBCIR_TXSTATE_ERROR)
614 count = -EAGAIN;
615 data->txstate = WBCIR_TXSTATE_INACTIVE;
616 data->txbuf = NULL;
617 spin_unlock_irqrestore(&data->spinlock, flags);
618
619 return count;
620 }
621
622 /*****************************************************************************
623 *
624 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
625 *
626 *****************************************************************************/
627
628 static void
629 wbcir_shutdown(struct pnp_dev *device)
630 {
631 struct device *dev = &device->dev;
632 struct wbcir_data *data = pnp_get_drvdata(device);
633 bool do_wake = true;
634 u8 match[11];
635 u8 mask[11];
636 u8 rc6_csl = 0;
637 int i;
638
639 memset(match, 0, sizeof(match));
640 memset(mask, 0, sizeof(mask));
641
642 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
643 do_wake = false;
644 goto finish;
645 }
646
647 switch (protocol) {
648 case IR_PROTOCOL_RC5:
649 if (wake_sc > 0xFFF) {
650 do_wake = false;
651 dev_err(dev, "RC5 - Invalid wake scancode\n");
652 break;
653 }
654
655 /* Mask = 13 bits, ex toggle */
656 mask[0] = 0xFF;
657 mask[1] = 0x17;
658
659 match[0] = (wake_sc & 0x003F); /* 6 command bits */
660 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
661 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
662 if (!(wake_sc & 0x0040)) /* 2nd start bit */
663 match[1] |= 0x10;
664
665 break;
666
667 case IR_PROTOCOL_NEC:
668 if (wake_sc > 0xFFFFFF) {
669 do_wake = false;
670 dev_err(dev, "NEC - Invalid wake scancode\n");
671 break;
672 }
673
674 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
675
676 match[1] = bitrev8((wake_sc & 0xFF));
677 match[0] = ~match[1];
678
679 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
680 if (wake_sc > 0xFFFF)
681 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
682 else
683 match[2] = ~match[3];
684
685 break;
686
687 case IR_PROTOCOL_RC6:
688
689 if (wake_rc6mode == 0) {
690 if (wake_sc > 0xFFFF) {
691 do_wake = false;
692 dev_err(dev, "RC6 - Invalid wake scancode\n");
693 break;
694 }
695
696 /* Command */
697 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
698 mask[0] = 0xFF;
699 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
700 mask[1] = 0xFF;
701
702 /* Address */
703 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
704 mask[2] = 0xFF;
705 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
706 mask[3] = 0xFF;
707
708 /* Header */
709 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
710 mask[4] = 0xF0;
711 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
712 mask[5] = 0x0F;
713
714 rc6_csl = 44;
715
716 } else if (wake_rc6mode == 6) {
717 i = 0;
718
719 /* Command */
720 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
721 mask[i++] = 0xFF;
722 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
723 mask[i++] = 0xFF;
724
725 /* Address + Toggle */
726 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
727 mask[i++] = 0xFF;
728 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
729 mask[i++] = 0x3F;
730
731 /* Customer bits 7 - 0 */
732 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
733 mask[i++] = 0xFF;
734 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
735 mask[i++] = 0xFF;
736
737 if (wake_sc & 0x80000000) {
738 /* Customer range bit and bits 15 - 8 */
739 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
740 mask[i++] = 0xFF;
741 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
742 mask[i++] = 0xFF;
743 rc6_csl = 76;
744 } else if (wake_sc <= 0x007FFFFF) {
745 rc6_csl = 60;
746 } else {
747 do_wake = false;
748 dev_err(dev, "RC6 - Invalid wake scancode\n");
749 break;
750 }
751
752 /* Header */
753 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
754 mask[i++] = 0xFF;
755 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
756 mask[i++] = 0x0F;
757
758 } else {
759 do_wake = false;
760 dev_err(dev, "RC6 - Invalid wake mode\n");
761 }
762
763 break;
764
765 default:
766 do_wake = false;
767 break;
768 }
769
770 finish:
771 if (do_wake) {
772 /* Set compare and compare mask */
773 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
774 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
775 0x3F);
776 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
777 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
778 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
779 0x3F);
780 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
781
782 /* RC6 Compare String Len */
783 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
784
785 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
786 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
787
788 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
789 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
790
791 /* Set CEIR_EN */
792 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
793
794 } else {
795 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
796 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
797
798 /* Clear CEIR_EN */
799 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
800 }
801
802 /*
803 * ACPI will set the HW disable bit for SP3 which means that the
804 * output signals are left in an undefined state which may cause
805 * spurious interrupts which we need to ignore until the hardware
806 * is reinitialized.
807 */
808 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
809 disable_irq(data->irq);
810
811 /* Disable LED */
812 led_trigger_event(data->rxtrigger, LED_OFF);
813 led_trigger_event(data->txtrigger, LED_OFF);
814 }
815
816 static int
817 wbcir_suspend(struct pnp_dev *device, pm_message_t state)
818 {
819 wbcir_shutdown(device);
820 return 0;
821 }
822
823 static void
824 wbcir_init_hw(struct wbcir_data *data)
825 {
826 u8 tmp;
827
828 /* Disable interrupts */
829 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
830
831 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
832 tmp = protocol << 4;
833 if (invert)
834 tmp |= 0x08;
835 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
836
837 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
838 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
839
840 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
841 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
842
843 /* Set RC5 cell time to correspond to 36 kHz */
844 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
845
846 /* Set IRTX_INV */
847 if (invert)
848 outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL);
849 else
850 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
851
852 /*
853 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
854 * set SP3_IRRX_SW to binary 01, helpfully not documented
855 */
856 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
857 data->txmask = 0x1;
858
859 /* Enable extended mode */
860 wbcir_select_bank(data, WBCIR_BANK_2);
861 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
862
863 /*
864 * Configure baud generator, IR data will be sampled at
865 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
866 *
867 * The ECIR registers include a flag to change the
868 * 24Mhz clock freq to 48Mhz.
869 *
870 * It's not documented in the specs, but fifo levels
871 * other than 16 seems to be unsupported.
872 */
873
874 /* prescaler 1.0, tx/rx fifo lvl 16 */
875 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
876
877 /* Set baud divisor to sample every 10 us */
878 outb(0x0F, data->sbase + WBCIR_REG_SP3_BGDL);
879 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
880
881 /* Set CEIR mode */
882 wbcir_select_bank(data, WBCIR_BANK_0);
883 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
884 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
885 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
886
887 /* Disable RX demod, enable run-length enc/dec, set freq span */
888 wbcir_select_bank(data, WBCIR_BANK_7);
889 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
890
891 /* Disable timer */
892 wbcir_select_bank(data, WBCIR_BANK_4);
893 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
894
895 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
896 wbcir_select_bank(data, WBCIR_BANK_5);
897 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
898
899 /* Disable CRC */
900 wbcir_select_bank(data, WBCIR_BANK_6);
901 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
902
903 /* Set RX demodulation freq, not really used */
904 wbcir_select_bank(data, WBCIR_BANK_7);
905 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
906
907 /* Set TX modulation, 36kHz, 7us pulse width */
908 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
909 data->txcarrier = 36000;
910
911 /* Set invert and pin direction */
912 if (invert)
913 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
914 else
915 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
916
917 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
918 wbcir_select_bank(data, WBCIR_BANK_0);
919 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
920
921 /* Clear AUX status bits */
922 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
923
924 /* Clear RX state */
925 data->rxstate = WBCIR_RXSTATE_INACTIVE;
926 data->rxev.duration = 0;
927 ir_raw_event_reset(data->dev);
928 ir_raw_event_handle(data->dev);
929
930 /*
931 * Check TX state, if we did a suspend/resume cycle while TX was
932 * active, we will have a process waiting in txwaitq.
933 */
934 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
935 data->txstate = WBCIR_TXSTATE_ERROR;
936 wake_up(&data->txwaitq);
937 }
938
939 /* Enable interrupts */
940 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
941 }
942
943 static int
944 wbcir_resume(struct pnp_dev *device)
945 {
946 struct wbcir_data *data = pnp_get_drvdata(device);
947
948 wbcir_init_hw(data);
949 enable_irq(data->irq);
950
951 return 0;
952 }
953
954 static int __devinit
955 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
956 {
957 struct device *dev = &device->dev;
958 struct wbcir_data *data;
959 int err;
960
961 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
962 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
963 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
964 dev_err(dev, "Invalid resources\n");
965 return -ENODEV;
966 }
967
968 data = kzalloc(sizeof(*data), GFP_KERNEL);
969 if (!data) {
970 err = -ENOMEM;
971 goto exit;
972 }
973
974 pnp_set_drvdata(device, data);
975
976 spin_lock_init(&data->spinlock);
977 init_waitqueue_head(&data->txwaitq);
978 data->ebase = pnp_port_start(device, 0);
979 data->wbase = pnp_port_start(device, 1);
980 data->sbase = pnp_port_start(device, 2);
981 data->irq = pnp_irq(device, 0);
982
983 if (data->wbase == 0 || data->ebase == 0 ||
984 data->sbase == 0 || data->irq == 0) {
985 err = -ENODEV;
986 dev_err(dev, "Invalid resources\n");
987 goto exit_free_data;
988 }
989
990 dev_dbg(&device->dev, "Found device "
991 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
992 data->wbase, data->ebase, data->sbase, data->irq);
993
994 led_trigger_register_simple("cir-tx", &data->txtrigger);
995 if (!data->txtrigger) {
996 err = -ENOMEM;
997 goto exit_free_data;
998 }
999
1000 led_trigger_register_simple("cir-rx", &data->rxtrigger);
1001 if (!data->rxtrigger) {
1002 err = -ENOMEM;
1003 goto exit_unregister_txtrigger;
1004 }
1005
1006 data->led.name = "cir::activity";
1007 data->led.default_trigger = "cir-rx";
1008 data->led.brightness_set = wbcir_led_brightness_set;
1009 data->led.brightness_get = wbcir_led_brightness_get;
1010 err = led_classdev_register(&device->dev, &data->led);
1011 if (err)
1012 goto exit_unregister_rxtrigger;
1013
1014 data->dev = rc_allocate_device();
1015 if (!data->dev) {
1016 err = -ENOMEM;
1017 goto exit_unregister_led;
1018 }
1019
1020 data->dev->driver_type = RC_DRIVER_IR_RAW;
1021 data->dev->driver_name = WBCIR_NAME;
1022 data->dev->input_name = WBCIR_NAME;
1023 data->dev->input_phys = "wbcir/cir0";
1024 data->dev->input_id.bustype = BUS_HOST;
1025 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1026 data->dev->input_id.product = WBCIR_ID_FAMILY;
1027 data->dev->input_id.version = WBCIR_ID_CHIP;
1028 data->dev->map_name = RC_MAP_RC6_MCE;
1029 data->dev->s_idle = wbcir_idle_rx;
1030 data->dev->s_tx_mask = wbcir_txmask;
1031 data->dev->s_tx_carrier = wbcir_txcarrier;
1032 data->dev->tx_ir = wbcir_tx;
1033 data->dev->priv = data;
1034 data->dev->dev.parent = &device->dev;
1035
1036 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1037 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1038 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1039 err = -EBUSY;
1040 goto exit_free_rc;
1041 }
1042
1043 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1044 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1045 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1046 err = -EBUSY;
1047 goto exit_release_wbase;
1048 }
1049
1050 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1051 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1052 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1053 err = -EBUSY;
1054 goto exit_release_ebase;
1055 }
1056
1057 err = request_irq(data->irq, wbcir_irq_handler,
1058 IRQF_DISABLED, DRVNAME, device);
1059 if (err) {
1060 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1061 err = -EBUSY;
1062 goto exit_release_sbase;
1063 }
1064
1065 err = rc_register_device(data->dev);
1066 if (err)
1067 goto exit_free_irq;
1068
1069 device_init_wakeup(&device->dev, 1);
1070
1071 wbcir_init_hw(data);
1072
1073 return 0;
1074
1075 exit_free_irq:
1076 free_irq(data->irq, device);
1077 exit_release_sbase:
1078 release_region(data->sbase, SP_IOMEM_LEN);
1079 exit_release_ebase:
1080 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1081 exit_release_wbase:
1082 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1083 exit_free_rc:
1084 rc_free_device(data->dev);
1085 exit_unregister_led:
1086 led_classdev_unregister(&data->led);
1087 exit_unregister_rxtrigger:
1088 led_trigger_unregister_simple(data->rxtrigger);
1089 exit_unregister_txtrigger:
1090 led_trigger_unregister_simple(data->txtrigger);
1091 exit_free_data:
1092 kfree(data);
1093 pnp_set_drvdata(device, NULL);
1094 exit:
1095 return err;
1096 }
1097
1098 static void __devexit
1099 wbcir_remove(struct pnp_dev *device)
1100 {
1101 struct wbcir_data *data = pnp_get_drvdata(device);
1102
1103 /* Disable interrupts */
1104 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1105 free_irq(data->irq, device);
1106
1107 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1108 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1109
1110 /* Clear CEIR_EN */
1111 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1112
1113 /* Clear BUFF_EN, END_EN, MATCH_EN */
1114 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1115
1116 rc_unregister_device(data->dev);
1117
1118 led_trigger_unregister_simple(data->rxtrigger);
1119 led_trigger_unregister_simple(data->txtrigger);
1120 led_classdev_unregister(&data->led);
1121
1122 /* This is ok since &data->led isn't actually used */
1123 wbcir_led_brightness_set(&data->led, LED_OFF);
1124
1125 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1126 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1127 release_region(data->sbase, SP_IOMEM_LEN);
1128
1129 kfree(data);
1130
1131 pnp_set_drvdata(device, NULL);
1132 }
1133
1134 static const struct pnp_device_id wbcir_ids[] = {
1135 { "WEC1022", 0 },
1136 { "", 0 }
1137 };
1138 MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1139
1140 static struct pnp_driver wbcir_driver = {
1141 .name = WBCIR_NAME,
1142 .id_table = wbcir_ids,
1143 .probe = wbcir_probe,
1144 .remove = __devexit_p(wbcir_remove),
1145 .suspend = wbcir_suspend,
1146 .resume = wbcir_resume,
1147 .shutdown = wbcir_shutdown
1148 };
1149
1150 static int __init
1151 wbcir_init(void)
1152 {
1153 int ret;
1154
1155 switch (protocol) {
1156 case IR_PROTOCOL_RC5:
1157 case IR_PROTOCOL_NEC:
1158 case IR_PROTOCOL_RC6:
1159 break;
1160 default:
1161 pr_err("Invalid power-on protocol\n");
1162 }
1163
1164 ret = pnp_register_driver(&wbcir_driver);
1165 if (ret)
1166 pr_err("Unable to register driver\n");
1167
1168 return ret;
1169 }
1170
1171 static void __exit
1172 wbcir_exit(void)
1173 {
1174 pnp_unregister_driver(&wbcir_driver);
1175 }
1176
1177 module_init(wbcir_init);
1178 module_exit(wbcir_exit);
1179
1180 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1181 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1182 MODULE_LICENSE("GPL");
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