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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / ti / netcp_ethss.c
1 /*
2 * Keystone GBE and XGBE subsystem code
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated
5 * Authors: Sandeep Nair <sandeep_n@ti.com>
6 * Sandeep Paulraj <s-paulraj@ti.com>
7 * Cyril Chemparathy <cyril@ti.com>
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * Wingman Kwok <w-kwok2@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
16 * kind, whether express or implied; without even the implied warranty
17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/io.h>
22 #include <linux/module.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_address.h>
25 #include <linux/if_vlan.h>
26 #include <linux/ptp_classify.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/ethtool.h>
29
30 #include "cpsw_ale.h"
31 #include "netcp.h"
32 #include "cpts.h"
33
34 #define NETCP_DRIVER_NAME "TI KeyStone Ethernet Driver"
35 #define NETCP_DRIVER_VERSION "v1.0"
36
37 #define GBE_IDENT(reg) ((reg >> 16) & 0xffff)
38 #define GBE_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
39 #define GBE_MINOR_VERSION(reg) (reg & 0xff)
40 #define GBE_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
41
42 /* 1G Ethernet SS defines */
43 #define GBE_MODULE_NAME "netcp-gbe"
44 #define GBE_SS_VERSION_14 0x4ed21104
45
46 #define GBE_SS_REG_INDEX 0
47 #define GBE_SGMII34_REG_INDEX 1
48 #define GBE_SM_REG_INDEX 2
49 /* offset relative to base of GBE_SS_REG_INDEX */
50 #define GBE13_SGMII_MODULE_OFFSET 0x100
51 /* offset relative to base of GBE_SM_REG_INDEX */
52 #define GBE13_HOST_PORT_OFFSET 0x34
53 #define GBE13_SLAVE_PORT_OFFSET 0x60
54 #define GBE13_EMAC_OFFSET 0x100
55 #define GBE13_SLAVE_PORT2_OFFSET 0x200
56 #define GBE13_HW_STATS_OFFSET 0x300
57 #define GBE13_CPTS_OFFSET 0x500
58 #define GBE13_ALE_OFFSET 0x600
59 #define GBE13_HOST_PORT_NUM 0
60 #define GBE13_NUM_ALE_ENTRIES 1024
61
62 /* 1G Ethernet NU SS defines */
63 #define GBENU_MODULE_NAME "netcp-gbenu"
64 #define GBE_SS_ID_NU 0x4ee6
65 #define GBE_SS_ID_2U 0x4ee8
66
67 #define IS_SS_ID_MU(d) \
68 ((GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) || \
69 (GBE_IDENT((d)->ss_version) == GBE_SS_ID_2U))
70
71 #define IS_SS_ID_NU(d) \
72 (GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU)
73
74 #define GBENU_SS_REG_INDEX 0
75 #define GBENU_SM_REG_INDEX 1
76 #define GBENU_SGMII_MODULE_OFFSET 0x100
77 #define GBENU_HOST_PORT_OFFSET 0x1000
78 #define GBENU_SLAVE_PORT_OFFSET 0x2000
79 #define GBENU_EMAC_OFFSET 0x2330
80 #define GBENU_HW_STATS_OFFSET 0x1a000
81 #define GBENU_CPTS_OFFSET 0x1d000
82 #define GBENU_ALE_OFFSET 0x1e000
83 #define GBENU_HOST_PORT_NUM 0
84 #define GBENU_SGMII_MODULE_SIZE 0x100
85
86 /* 10G Ethernet SS defines */
87 #define XGBE_MODULE_NAME "netcp-xgbe"
88 #define XGBE_SS_VERSION_10 0x4ee42100
89
90 #define XGBE_SS_REG_INDEX 0
91 #define XGBE_SM_REG_INDEX 1
92 #define XGBE_SERDES_REG_INDEX 2
93
94 /* offset relative to base of XGBE_SS_REG_INDEX */
95 #define XGBE10_SGMII_MODULE_OFFSET 0x100
96 #define IS_SS_ID_XGBE(d) ((d)->ss_version == XGBE_SS_VERSION_10)
97 /* offset relative to base of XGBE_SM_REG_INDEX */
98 #define XGBE10_HOST_PORT_OFFSET 0x34
99 #define XGBE10_SLAVE_PORT_OFFSET 0x64
100 #define XGBE10_EMAC_OFFSET 0x400
101 #define XGBE10_CPTS_OFFSET 0x600
102 #define XGBE10_ALE_OFFSET 0x700
103 #define XGBE10_HW_STATS_OFFSET 0x800
104 #define XGBE10_HOST_PORT_NUM 0
105 #define XGBE10_NUM_ALE_ENTRIES 2048
106
107 #define GBE_TIMER_INTERVAL (HZ / 2)
108
109 /* Soft reset register values */
110 #define SOFT_RESET_MASK BIT(0)
111 #define SOFT_RESET BIT(0)
112 #define DEVICE_EMACSL_RESET_POLL_COUNT 100
113 #define GMACSL_RET_WARN_RESET_INCOMPLETE -2
114
115 #define MACSL_RX_ENABLE_CSF BIT(23)
116 #define MACSL_ENABLE_EXT_CTL BIT(18)
117 #define MACSL_XGMII_ENABLE BIT(13)
118 #define MACSL_XGIG_MODE BIT(8)
119 #define MACSL_GIG_MODE BIT(7)
120 #define MACSL_GMII_ENABLE BIT(5)
121 #define MACSL_FULLDUPLEX BIT(0)
122
123 #define GBE_CTL_P0_ENABLE BIT(2)
124 #define ETH_SW_CTL_P0_TX_CRC_REMOVE BIT(13)
125 #define GBE13_REG_VAL_STAT_ENABLE_ALL 0xff
126 #define XGBE_REG_VAL_STAT_ENABLE_ALL 0xf
127 #define GBE_STATS_CD_SEL BIT(28)
128
129 #define GBE_PORT_MASK(x) (BIT(x) - 1)
130 #define GBE_MASK_NO_PORTS 0
131
132 #define GBE_DEF_1G_MAC_CONTROL \
133 (MACSL_GIG_MODE | MACSL_GMII_ENABLE | \
134 MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF)
135
136 #define GBE_DEF_10G_MAC_CONTROL \
137 (MACSL_XGIG_MODE | MACSL_XGMII_ENABLE | \
138 MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF)
139
140 #define GBE_STATSA_MODULE 0
141 #define GBE_STATSB_MODULE 1
142 #define GBE_STATSC_MODULE 2
143 #define GBE_STATSD_MODULE 3
144
145 #define GBENU_STATS0_MODULE 0
146 #define GBENU_STATS1_MODULE 1
147 #define GBENU_STATS2_MODULE 2
148 #define GBENU_STATS3_MODULE 3
149 #define GBENU_STATS4_MODULE 4
150 #define GBENU_STATS5_MODULE 5
151 #define GBENU_STATS6_MODULE 6
152 #define GBENU_STATS7_MODULE 7
153 #define GBENU_STATS8_MODULE 8
154
155 #define XGBE_STATS0_MODULE 0
156 #define XGBE_STATS1_MODULE 1
157 #define XGBE_STATS2_MODULE 2
158
159 /* s: 0-based slave_port */
160 #define SGMII_BASE(d, s) \
161 (((s) < 2) ? (d)->sgmii_port_regs : (d)->sgmii_port34_regs)
162
163 #define GBE_TX_QUEUE 648
164 #define GBE_TXHOOK_ORDER 0
165 #define GBE_RXHOOK_ORDER 0
166 #define GBE_DEFAULT_ALE_AGEOUT 30
167 #define SLAVE_LINK_IS_XGMII(s) ((s)->link_interface >= XGMII_LINK_MAC_PHY)
168 #define NETCP_LINK_STATE_INVALID -1
169
170 #define GBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
171 offsetof(struct gbe##_##rb, rn)
172 #define GBENU_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
173 offsetof(struct gbenu##_##rb, rn)
174 #define XGBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
175 offsetof(struct xgbe##_##rb, rn)
176 #define GBE_REG_ADDR(p, rb, rn) (p->rb + p->rb##_ofs.rn)
177
178 #define HOST_TX_PRI_MAP_DEFAULT 0x00000000
179
180 #if IS_ENABLED(CONFIG_TI_CPTS)
181 /* Px_TS_CTL register fields */
182 #define TS_RX_ANX_F_EN BIT(0)
183 #define TS_RX_VLAN_LT1_EN BIT(1)
184 #define TS_RX_VLAN_LT2_EN BIT(2)
185 #define TS_RX_ANX_D_EN BIT(3)
186 #define TS_TX_ANX_F_EN BIT(4)
187 #define TS_TX_VLAN_LT1_EN BIT(5)
188 #define TS_TX_VLAN_LT2_EN BIT(6)
189 #define TS_TX_ANX_D_EN BIT(7)
190 #define TS_LT2_EN BIT(8)
191 #define TS_RX_ANX_E_EN BIT(9)
192 #define TS_TX_ANX_E_EN BIT(10)
193 #define TS_MSG_TYPE_EN_SHIFT 16
194 #define TS_MSG_TYPE_EN_MASK 0xffff
195
196 /* Px_TS_SEQ_LTYPE register fields */
197 #define TS_SEQ_ID_OFS_SHIFT 16
198 #define TS_SEQ_ID_OFS_MASK 0x3f
199
200 /* Px_TS_CTL_LTYPE2 register fields */
201 #define TS_107 BIT(16)
202 #define TS_129 BIT(17)
203 #define TS_130 BIT(18)
204 #define TS_131 BIT(19)
205 #define TS_132 BIT(20)
206 #define TS_319 BIT(21)
207 #define TS_320 BIT(22)
208 #define TS_TTL_NONZERO BIT(23)
209 #define TS_UNI_EN BIT(24)
210 #define TS_UNI_EN_SHIFT 24
211
212 #define TS_TX_ANX_ALL_EN \
213 (TS_TX_ANX_D_EN | TS_TX_ANX_E_EN | TS_TX_ANX_F_EN)
214
215 #define TS_RX_ANX_ALL_EN \
216 (TS_RX_ANX_D_EN | TS_RX_ANX_E_EN | TS_RX_ANX_F_EN)
217
218 #define TS_CTL_DST_PORT TS_319
219 #define TS_CTL_DST_PORT_SHIFT 21
220
221 #define TS_CTL_MADDR_ALL \
222 (TS_107 | TS_129 | TS_130 | TS_131 | TS_132)
223
224 #define TS_CTL_MADDR_SHIFT 16
225
226 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
227 #define EVENT_MSG_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
228 #endif /* CONFIG_TI_CPTS */
229
230 struct xgbe_ss_regs {
231 u32 id_ver;
232 u32 synce_count;
233 u32 synce_mux;
234 u32 control;
235 };
236
237 struct xgbe_switch_regs {
238 u32 id_ver;
239 u32 control;
240 u32 emcontrol;
241 u32 stat_port_en;
242 u32 ptype;
243 u32 soft_idle;
244 u32 thru_rate;
245 u32 gap_thresh;
246 u32 tx_start_wds;
247 u32 flow_control;
248 u32 cppi_thresh;
249 };
250
251 struct xgbe_port_regs {
252 u32 blk_cnt;
253 u32 port_vlan;
254 u32 tx_pri_map;
255 u32 sa_lo;
256 u32 sa_hi;
257 u32 ts_ctl;
258 u32 ts_seq_ltype;
259 u32 ts_vlan;
260 u32 ts_ctl_ltype2;
261 u32 ts_ctl2;
262 u32 control;
263 };
264
265 struct xgbe_host_port_regs {
266 u32 blk_cnt;
267 u32 port_vlan;
268 u32 tx_pri_map;
269 u32 src_id;
270 u32 rx_pri_map;
271 u32 rx_maxlen;
272 };
273
274 struct xgbe_emac_regs {
275 u32 id_ver;
276 u32 mac_control;
277 u32 mac_status;
278 u32 soft_reset;
279 u32 rx_maxlen;
280 u32 __reserved_0;
281 u32 rx_pause;
282 u32 tx_pause;
283 u32 em_control;
284 u32 __reserved_1;
285 u32 tx_gap;
286 u32 rsvd[4];
287 };
288
289 struct xgbe_host_hw_stats {
290 u32 rx_good_frames;
291 u32 rx_broadcast_frames;
292 u32 rx_multicast_frames;
293 u32 __rsvd_0[3];
294 u32 rx_oversized_frames;
295 u32 __rsvd_1;
296 u32 rx_undersized_frames;
297 u32 __rsvd_2;
298 u32 overrun_type4;
299 u32 overrun_type5;
300 u32 rx_bytes;
301 u32 tx_good_frames;
302 u32 tx_broadcast_frames;
303 u32 tx_multicast_frames;
304 u32 __rsvd_3[9];
305 u32 tx_bytes;
306 u32 tx_64byte_frames;
307 u32 tx_65_to_127byte_frames;
308 u32 tx_128_to_255byte_frames;
309 u32 tx_256_to_511byte_frames;
310 u32 tx_512_to_1023byte_frames;
311 u32 tx_1024byte_frames;
312 u32 net_bytes;
313 u32 rx_sof_overruns;
314 u32 rx_mof_overruns;
315 u32 rx_dma_overruns;
316 };
317
318 struct xgbe_hw_stats {
319 u32 rx_good_frames;
320 u32 rx_broadcast_frames;
321 u32 rx_multicast_frames;
322 u32 rx_pause_frames;
323 u32 rx_crc_errors;
324 u32 rx_align_code_errors;
325 u32 rx_oversized_frames;
326 u32 rx_jabber_frames;
327 u32 rx_undersized_frames;
328 u32 rx_fragments;
329 u32 overrun_type4;
330 u32 overrun_type5;
331 u32 rx_bytes;
332 u32 tx_good_frames;
333 u32 tx_broadcast_frames;
334 u32 tx_multicast_frames;
335 u32 tx_pause_frames;
336 u32 tx_deferred_frames;
337 u32 tx_collision_frames;
338 u32 tx_single_coll_frames;
339 u32 tx_mult_coll_frames;
340 u32 tx_excessive_collisions;
341 u32 tx_late_collisions;
342 u32 tx_underrun;
343 u32 tx_carrier_sense_errors;
344 u32 tx_bytes;
345 u32 tx_64byte_frames;
346 u32 tx_65_to_127byte_frames;
347 u32 tx_128_to_255byte_frames;
348 u32 tx_256_to_511byte_frames;
349 u32 tx_512_to_1023byte_frames;
350 u32 tx_1024byte_frames;
351 u32 net_bytes;
352 u32 rx_sof_overruns;
353 u32 rx_mof_overruns;
354 u32 rx_dma_overruns;
355 };
356
357 struct gbenu_ss_regs {
358 u32 id_ver;
359 u32 synce_count; /* NU */
360 u32 synce_mux; /* NU */
361 u32 control; /* 2U */
362 u32 __rsvd_0[2]; /* 2U */
363 u32 rgmii_status; /* 2U */
364 u32 ss_status; /* 2U */
365 };
366
367 struct gbenu_switch_regs {
368 u32 id_ver;
369 u32 control;
370 u32 __rsvd_0[2];
371 u32 emcontrol;
372 u32 stat_port_en;
373 u32 ptype; /* NU */
374 u32 soft_idle;
375 u32 thru_rate; /* NU */
376 u32 gap_thresh; /* NU */
377 u32 tx_start_wds; /* NU */
378 u32 eee_prescale; /* 2U */
379 u32 tx_g_oflow_thresh_set; /* NU */
380 u32 tx_g_oflow_thresh_clr; /* NU */
381 u32 tx_g_buf_thresh_set_l; /* NU */
382 u32 tx_g_buf_thresh_set_h; /* NU */
383 u32 tx_g_buf_thresh_clr_l; /* NU */
384 u32 tx_g_buf_thresh_clr_h; /* NU */
385 };
386
387 struct gbenu_port_regs {
388 u32 __rsvd_0;
389 u32 control;
390 u32 max_blks; /* 2U */
391 u32 mem_align1;
392 u32 blk_cnt;
393 u32 port_vlan;
394 u32 tx_pri_map; /* NU */
395 u32 pri_ctl; /* 2U */
396 u32 rx_pri_map;
397 u32 rx_maxlen;
398 u32 tx_blks_pri; /* NU */
399 u32 __rsvd_1;
400 u32 idle2lpi; /* 2U */
401 u32 lpi2idle; /* 2U */
402 u32 eee_status; /* 2U */
403 u32 __rsvd_2;
404 u32 __rsvd_3[176]; /* NU: more to add */
405 u32 __rsvd_4[2];
406 u32 sa_lo;
407 u32 sa_hi;
408 u32 ts_ctl;
409 u32 ts_seq_ltype;
410 u32 ts_vlan;
411 u32 ts_ctl_ltype2;
412 u32 ts_ctl2;
413 };
414
415 struct gbenu_host_port_regs {
416 u32 __rsvd_0;
417 u32 control;
418 u32 flow_id_offset; /* 2U */
419 u32 __rsvd_1;
420 u32 blk_cnt;
421 u32 port_vlan;
422 u32 tx_pri_map; /* NU */
423 u32 pri_ctl;
424 u32 rx_pri_map;
425 u32 rx_maxlen;
426 u32 tx_blks_pri; /* NU */
427 u32 __rsvd_2;
428 u32 idle2lpi; /* 2U */
429 u32 lpi2wake; /* 2U */
430 u32 eee_status; /* 2U */
431 u32 __rsvd_3;
432 u32 __rsvd_4[184]; /* NU */
433 u32 host_blks_pri; /* NU */
434 };
435
436 struct gbenu_emac_regs {
437 u32 mac_control;
438 u32 mac_status;
439 u32 soft_reset;
440 u32 boff_test;
441 u32 rx_pause;
442 u32 __rsvd_0[11]; /* NU */
443 u32 tx_pause;
444 u32 __rsvd_1[11]; /* NU */
445 u32 em_control;
446 u32 tx_gap;
447 };
448
449 /* Some hw stat regs are applicable to slave port only.
450 * This is handled by gbenu_et_stats struct. Also some
451 * are for SS version NU and some are for 2U.
452 */
453 struct gbenu_hw_stats {
454 u32 rx_good_frames;
455 u32 rx_broadcast_frames;
456 u32 rx_multicast_frames;
457 u32 rx_pause_frames; /* slave */
458 u32 rx_crc_errors;
459 u32 rx_align_code_errors; /* slave */
460 u32 rx_oversized_frames;
461 u32 rx_jabber_frames; /* slave */
462 u32 rx_undersized_frames;
463 u32 rx_fragments; /* slave */
464 u32 ale_drop;
465 u32 ale_overrun_drop;
466 u32 rx_bytes;
467 u32 tx_good_frames;
468 u32 tx_broadcast_frames;
469 u32 tx_multicast_frames;
470 u32 tx_pause_frames; /* slave */
471 u32 tx_deferred_frames; /* slave */
472 u32 tx_collision_frames; /* slave */
473 u32 tx_single_coll_frames; /* slave */
474 u32 tx_mult_coll_frames; /* slave */
475 u32 tx_excessive_collisions; /* slave */
476 u32 tx_late_collisions; /* slave */
477 u32 rx_ipg_error; /* slave 10G only */
478 u32 tx_carrier_sense_errors; /* slave */
479 u32 tx_bytes;
480 u32 tx_64B_frames;
481 u32 tx_65_to_127B_frames;
482 u32 tx_128_to_255B_frames;
483 u32 tx_256_to_511B_frames;
484 u32 tx_512_to_1023B_frames;
485 u32 tx_1024B_frames;
486 u32 net_bytes;
487 u32 rx_bottom_fifo_drop;
488 u32 rx_port_mask_drop;
489 u32 rx_top_fifo_drop;
490 u32 ale_rate_limit_drop;
491 u32 ale_vid_ingress_drop;
492 u32 ale_da_eq_sa_drop;
493 u32 __rsvd_0[3];
494 u32 ale_unknown_ucast;
495 u32 ale_unknown_ucast_bytes;
496 u32 ale_unknown_mcast;
497 u32 ale_unknown_mcast_bytes;
498 u32 ale_unknown_bcast;
499 u32 ale_unknown_bcast_bytes;
500 u32 ale_pol_match;
501 u32 ale_pol_match_red; /* NU */
502 u32 ale_pol_match_yellow; /* NU */
503 u32 __rsvd_1[44];
504 u32 tx_mem_protect_err;
505 /* following NU only */
506 u32 tx_pri0;
507 u32 tx_pri1;
508 u32 tx_pri2;
509 u32 tx_pri3;
510 u32 tx_pri4;
511 u32 tx_pri5;
512 u32 tx_pri6;
513 u32 tx_pri7;
514 u32 tx_pri0_bcnt;
515 u32 tx_pri1_bcnt;
516 u32 tx_pri2_bcnt;
517 u32 tx_pri3_bcnt;
518 u32 tx_pri4_bcnt;
519 u32 tx_pri5_bcnt;
520 u32 tx_pri6_bcnt;
521 u32 tx_pri7_bcnt;
522 u32 tx_pri0_drop;
523 u32 tx_pri1_drop;
524 u32 tx_pri2_drop;
525 u32 tx_pri3_drop;
526 u32 tx_pri4_drop;
527 u32 tx_pri5_drop;
528 u32 tx_pri6_drop;
529 u32 tx_pri7_drop;
530 u32 tx_pri0_drop_bcnt;
531 u32 tx_pri1_drop_bcnt;
532 u32 tx_pri2_drop_bcnt;
533 u32 tx_pri3_drop_bcnt;
534 u32 tx_pri4_drop_bcnt;
535 u32 tx_pri5_drop_bcnt;
536 u32 tx_pri6_drop_bcnt;
537 u32 tx_pri7_drop_bcnt;
538 };
539
540 #define GBENU_HW_STATS_REG_MAP_SZ 0x200
541
542 struct gbe_ss_regs {
543 u32 id_ver;
544 u32 synce_count;
545 u32 synce_mux;
546 };
547
548 struct gbe_ss_regs_ofs {
549 u16 id_ver;
550 u16 control;
551 };
552
553 struct gbe_switch_regs {
554 u32 id_ver;
555 u32 control;
556 u32 soft_reset;
557 u32 stat_port_en;
558 u32 ptype;
559 u32 soft_idle;
560 u32 thru_rate;
561 u32 gap_thresh;
562 u32 tx_start_wds;
563 u32 flow_control;
564 };
565
566 struct gbe_switch_regs_ofs {
567 u16 id_ver;
568 u16 control;
569 u16 soft_reset;
570 u16 emcontrol;
571 u16 stat_port_en;
572 u16 ptype;
573 u16 flow_control;
574 };
575
576 struct gbe_port_regs {
577 u32 max_blks;
578 u32 blk_cnt;
579 u32 port_vlan;
580 u32 tx_pri_map;
581 u32 sa_lo;
582 u32 sa_hi;
583 u32 ts_ctl;
584 u32 ts_seq_ltype;
585 u32 ts_vlan;
586 u32 ts_ctl_ltype2;
587 u32 ts_ctl2;
588 };
589
590 struct gbe_port_regs_ofs {
591 u16 port_vlan;
592 u16 tx_pri_map;
593 u16 sa_lo;
594 u16 sa_hi;
595 u16 ts_ctl;
596 u16 ts_seq_ltype;
597 u16 ts_vlan;
598 u16 ts_ctl_ltype2;
599 u16 ts_ctl2;
600 u16 rx_maxlen; /* 2U, NU */
601 };
602
603 struct gbe_host_port_regs {
604 u32 src_id;
605 u32 port_vlan;
606 u32 rx_pri_map;
607 u32 rx_maxlen;
608 };
609
610 struct gbe_host_port_regs_ofs {
611 u16 port_vlan;
612 u16 tx_pri_map;
613 u16 rx_maxlen;
614 };
615
616 struct gbe_emac_regs {
617 u32 id_ver;
618 u32 mac_control;
619 u32 mac_status;
620 u32 soft_reset;
621 u32 rx_maxlen;
622 u32 __reserved_0;
623 u32 rx_pause;
624 u32 tx_pause;
625 u32 __reserved_1;
626 u32 rx_pri_map;
627 u32 rsvd[6];
628 };
629
630 struct gbe_emac_regs_ofs {
631 u16 mac_control;
632 u16 soft_reset;
633 u16 rx_maxlen;
634 };
635
636 struct gbe_hw_stats {
637 u32 rx_good_frames;
638 u32 rx_broadcast_frames;
639 u32 rx_multicast_frames;
640 u32 rx_pause_frames;
641 u32 rx_crc_errors;
642 u32 rx_align_code_errors;
643 u32 rx_oversized_frames;
644 u32 rx_jabber_frames;
645 u32 rx_undersized_frames;
646 u32 rx_fragments;
647 u32 __pad_0[2];
648 u32 rx_bytes;
649 u32 tx_good_frames;
650 u32 tx_broadcast_frames;
651 u32 tx_multicast_frames;
652 u32 tx_pause_frames;
653 u32 tx_deferred_frames;
654 u32 tx_collision_frames;
655 u32 tx_single_coll_frames;
656 u32 tx_mult_coll_frames;
657 u32 tx_excessive_collisions;
658 u32 tx_late_collisions;
659 u32 tx_underrun;
660 u32 tx_carrier_sense_errors;
661 u32 tx_bytes;
662 u32 tx_64byte_frames;
663 u32 tx_65_to_127byte_frames;
664 u32 tx_128_to_255byte_frames;
665 u32 tx_256_to_511byte_frames;
666 u32 tx_512_to_1023byte_frames;
667 u32 tx_1024byte_frames;
668 u32 net_bytes;
669 u32 rx_sof_overruns;
670 u32 rx_mof_overruns;
671 u32 rx_dma_overruns;
672 };
673
674 #define GBE_MAX_HW_STAT_MODS 9
675 #define GBE_HW_STATS_REG_MAP_SZ 0x100
676
677 struct ts_ctl {
678 int uni;
679 u8 dst_port_map;
680 u8 maddr_map;
681 u8 ts_mcast_type;
682 };
683
684 struct gbe_slave {
685 void __iomem *port_regs;
686 void __iomem *emac_regs;
687 struct gbe_port_regs_ofs port_regs_ofs;
688 struct gbe_emac_regs_ofs emac_regs_ofs;
689 int slave_num; /* 0 based logical number */
690 int port_num; /* actual port number */
691 atomic_t link_state;
692 bool open;
693 struct phy_device *phy;
694 u32 link_interface;
695 u32 mac_control;
696 u8 phy_port_t;
697 struct device_node *phy_node;
698 struct ts_ctl ts_ctl;
699 struct list_head slave_list;
700 };
701
702 struct gbe_priv {
703 struct device *dev;
704 struct netcp_device *netcp_device;
705 struct timer_list timer;
706 u32 num_slaves;
707 u32 ale_entries;
708 u32 ale_ports;
709 bool enable_ale;
710 u8 max_num_slaves;
711 u8 max_num_ports; /* max_num_slaves + 1 */
712 u8 num_stats_mods;
713 struct netcp_tx_pipe tx_pipe;
714
715 int host_port;
716 u32 rx_packet_max;
717 u32 ss_version;
718 u32 stats_en_mask;
719
720 void __iomem *ss_regs;
721 void __iomem *switch_regs;
722 void __iomem *host_port_regs;
723 void __iomem *ale_reg;
724 void __iomem *cpts_reg;
725 void __iomem *sgmii_port_regs;
726 void __iomem *sgmii_port34_regs;
727 void __iomem *xgbe_serdes_regs;
728 void __iomem *hw_stats_regs[GBE_MAX_HW_STAT_MODS];
729
730 struct gbe_ss_regs_ofs ss_regs_ofs;
731 struct gbe_switch_regs_ofs switch_regs_ofs;
732 struct gbe_host_port_regs_ofs host_port_regs_ofs;
733
734 struct cpsw_ale *ale;
735 unsigned int tx_queue_id;
736 const char *dma_chan_name;
737
738 struct list_head gbe_intf_head;
739 struct list_head secondary_slaves;
740 struct net_device *dummy_ndev;
741
742 u64 *hw_stats;
743 u32 *hw_stats_prev;
744 const struct netcp_ethtool_stat *et_stats;
745 int num_et_stats;
746 /* Lock for updating the hwstats */
747 spinlock_t hw_stats_lock;
748
749 int cpts_registered;
750 struct cpts *cpts;
751 };
752
753 struct gbe_intf {
754 struct net_device *ndev;
755 struct device *dev;
756 struct gbe_priv *gbe_dev;
757 struct netcp_tx_pipe tx_pipe;
758 struct gbe_slave *slave;
759 struct list_head gbe_intf_list;
760 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
761 };
762
763 static struct netcp_module gbe_module;
764 static struct netcp_module xgbe_module;
765
766 /* Statistic management */
767 struct netcp_ethtool_stat {
768 char desc[ETH_GSTRING_LEN];
769 int type;
770 u32 size;
771 int offset;
772 };
773
774 #define GBE_STATSA_INFO(field) \
775 { \
776 "GBE_A:"#field, GBE_STATSA_MODULE, \
777 FIELD_SIZEOF(struct gbe_hw_stats, field), \
778 offsetof(struct gbe_hw_stats, field) \
779 }
780
781 #define GBE_STATSB_INFO(field) \
782 { \
783 "GBE_B:"#field, GBE_STATSB_MODULE, \
784 FIELD_SIZEOF(struct gbe_hw_stats, field), \
785 offsetof(struct gbe_hw_stats, field) \
786 }
787
788 #define GBE_STATSC_INFO(field) \
789 { \
790 "GBE_C:"#field, GBE_STATSC_MODULE, \
791 FIELD_SIZEOF(struct gbe_hw_stats, field), \
792 offsetof(struct gbe_hw_stats, field) \
793 }
794
795 #define GBE_STATSD_INFO(field) \
796 { \
797 "GBE_D:"#field, GBE_STATSD_MODULE, \
798 FIELD_SIZEOF(struct gbe_hw_stats, field), \
799 offsetof(struct gbe_hw_stats, field) \
800 }
801
802 static const struct netcp_ethtool_stat gbe13_et_stats[] = {
803 /* GBE module A */
804 GBE_STATSA_INFO(rx_good_frames),
805 GBE_STATSA_INFO(rx_broadcast_frames),
806 GBE_STATSA_INFO(rx_multicast_frames),
807 GBE_STATSA_INFO(rx_pause_frames),
808 GBE_STATSA_INFO(rx_crc_errors),
809 GBE_STATSA_INFO(rx_align_code_errors),
810 GBE_STATSA_INFO(rx_oversized_frames),
811 GBE_STATSA_INFO(rx_jabber_frames),
812 GBE_STATSA_INFO(rx_undersized_frames),
813 GBE_STATSA_INFO(rx_fragments),
814 GBE_STATSA_INFO(rx_bytes),
815 GBE_STATSA_INFO(tx_good_frames),
816 GBE_STATSA_INFO(tx_broadcast_frames),
817 GBE_STATSA_INFO(tx_multicast_frames),
818 GBE_STATSA_INFO(tx_pause_frames),
819 GBE_STATSA_INFO(tx_deferred_frames),
820 GBE_STATSA_INFO(tx_collision_frames),
821 GBE_STATSA_INFO(tx_single_coll_frames),
822 GBE_STATSA_INFO(tx_mult_coll_frames),
823 GBE_STATSA_INFO(tx_excessive_collisions),
824 GBE_STATSA_INFO(tx_late_collisions),
825 GBE_STATSA_INFO(tx_underrun),
826 GBE_STATSA_INFO(tx_carrier_sense_errors),
827 GBE_STATSA_INFO(tx_bytes),
828 GBE_STATSA_INFO(tx_64byte_frames),
829 GBE_STATSA_INFO(tx_65_to_127byte_frames),
830 GBE_STATSA_INFO(tx_128_to_255byte_frames),
831 GBE_STATSA_INFO(tx_256_to_511byte_frames),
832 GBE_STATSA_INFO(tx_512_to_1023byte_frames),
833 GBE_STATSA_INFO(tx_1024byte_frames),
834 GBE_STATSA_INFO(net_bytes),
835 GBE_STATSA_INFO(rx_sof_overruns),
836 GBE_STATSA_INFO(rx_mof_overruns),
837 GBE_STATSA_INFO(rx_dma_overruns),
838 /* GBE module B */
839 GBE_STATSB_INFO(rx_good_frames),
840 GBE_STATSB_INFO(rx_broadcast_frames),
841 GBE_STATSB_INFO(rx_multicast_frames),
842 GBE_STATSB_INFO(rx_pause_frames),
843 GBE_STATSB_INFO(rx_crc_errors),
844 GBE_STATSB_INFO(rx_align_code_errors),
845 GBE_STATSB_INFO(rx_oversized_frames),
846 GBE_STATSB_INFO(rx_jabber_frames),
847 GBE_STATSB_INFO(rx_undersized_frames),
848 GBE_STATSB_INFO(rx_fragments),
849 GBE_STATSB_INFO(rx_bytes),
850 GBE_STATSB_INFO(tx_good_frames),
851 GBE_STATSB_INFO(tx_broadcast_frames),
852 GBE_STATSB_INFO(tx_multicast_frames),
853 GBE_STATSB_INFO(tx_pause_frames),
854 GBE_STATSB_INFO(tx_deferred_frames),
855 GBE_STATSB_INFO(tx_collision_frames),
856 GBE_STATSB_INFO(tx_single_coll_frames),
857 GBE_STATSB_INFO(tx_mult_coll_frames),
858 GBE_STATSB_INFO(tx_excessive_collisions),
859 GBE_STATSB_INFO(tx_late_collisions),
860 GBE_STATSB_INFO(tx_underrun),
861 GBE_STATSB_INFO(tx_carrier_sense_errors),
862 GBE_STATSB_INFO(tx_bytes),
863 GBE_STATSB_INFO(tx_64byte_frames),
864 GBE_STATSB_INFO(tx_65_to_127byte_frames),
865 GBE_STATSB_INFO(tx_128_to_255byte_frames),
866 GBE_STATSB_INFO(tx_256_to_511byte_frames),
867 GBE_STATSB_INFO(tx_512_to_1023byte_frames),
868 GBE_STATSB_INFO(tx_1024byte_frames),
869 GBE_STATSB_INFO(net_bytes),
870 GBE_STATSB_INFO(rx_sof_overruns),
871 GBE_STATSB_INFO(rx_mof_overruns),
872 GBE_STATSB_INFO(rx_dma_overruns),
873 /* GBE module C */
874 GBE_STATSC_INFO(rx_good_frames),
875 GBE_STATSC_INFO(rx_broadcast_frames),
876 GBE_STATSC_INFO(rx_multicast_frames),
877 GBE_STATSC_INFO(rx_pause_frames),
878 GBE_STATSC_INFO(rx_crc_errors),
879 GBE_STATSC_INFO(rx_align_code_errors),
880 GBE_STATSC_INFO(rx_oversized_frames),
881 GBE_STATSC_INFO(rx_jabber_frames),
882 GBE_STATSC_INFO(rx_undersized_frames),
883 GBE_STATSC_INFO(rx_fragments),
884 GBE_STATSC_INFO(rx_bytes),
885 GBE_STATSC_INFO(tx_good_frames),
886 GBE_STATSC_INFO(tx_broadcast_frames),
887 GBE_STATSC_INFO(tx_multicast_frames),
888 GBE_STATSC_INFO(tx_pause_frames),
889 GBE_STATSC_INFO(tx_deferred_frames),
890 GBE_STATSC_INFO(tx_collision_frames),
891 GBE_STATSC_INFO(tx_single_coll_frames),
892 GBE_STATSC_INFO(tx_mult_coll_frames),
893 GBE_STATSC_INFO(tx_excessive_collisions),
894 GBE_STATSC_INFO(tx_late_collisions),
895 GBE_STATSC_INFO(tx_underrun),
896 GBE_STATSC_INFO(tx_carrier_sense_errors),
897 GBE_STATSC_INFO(tx_bytes),
898 GBE_STATSC_INFO(tx_64byte_frames),
899 GBE_STATSC_INFO(tx_65_to_127byte_frames),
900 GBE_STATSC_INFO(tx_128_to_255byte_frames),
901 GBE_STATSC_INFO(tx_256_to_511byte_frames),
902 GBE_STATSC_INFO(tx_512_to_1023byte_frames),
903 GBE_STATSC_INFO(tx_1024byte_frames),
904 GBE_STATSC_INFO(net_bytes),
905 GBE_STATSC_INFO(rx_sof_overruns),
906 GBE_STATSC_INFO(rx_mof_overruns),
907 GBE_STATSC_INFO(rx_dma_overruns),
908 /* GBE module D */
909 GBE_STATSD_INFO(rx_good_frames),
910 GBE_STATSD_INFO(rx_broadcast_frames),
911 GBE_STATSD_INFO(rx_multicast_frames),
912 GBE_STATSD_INFO(rx_pause_frames),
913 GBE_STATSD_INFO(rx_crc_errors),
914 GBE_STATSD_INFO(rx_align_code_errors),
915 GBE_STATSD_INFO(rx_oversized_frames),
916 GBE_STATSD_INFO(rx_jabber_frames),
917 GBE_STATSD_INFO(rx_undersized_frames),
918 GBE_STATSD_INFO(rx_fragments),
919 GBE_STATSD_INFO(rx_bytes),
920 GBE_STATSD_INFO(tx_good_frames),
921 GBE_STATSD_INFO(tx_broadcast_frames),
922 GBE_STATSD_INFO(tx_multicast_frames),
923 GBE_STATSD_INFO(tx_pause_frames),
924 GBE_STATSD_INFO(tx_deferred_frames),
925 GBE_STATSD_INFO(tx_collision_frames),
926 GBE_STATSD_INFO(tx_single_coll_frames),
927 GBE_STATSD_INFO(tx_mult_coll_frames),
928 GBE_STATSD_INFO(tx_excessive_collisions),
929 GBE_STATSD_INFO(tx_late_collisions),
930 GBE_STATSD_INFO(tx_underrun),
931 GBE_STATSD_INFO(tx_carrier_sense_errors),
932 GBE_STATSD_INFO(tx_bytes),
933 GBE_STATSD_INFO(tx_64byte_frames),
934 GBE_STATSD_INFO(tx_65_to_127byte_frames),
935 GBE_STATSD_INFO(tx_128_to_255byte_frames),
936 GBE_STATSD_INFO(tx_256_to_511byte_frames),
937 GBE_STATSD_INFO(tx_512_to_1023byte_frames),
938 GBE_STATSD_INFO(tx_1024byte_frames),
939 GBE_STATSD_INFO(net_bytes),
940 GBE_STATSD_INFO(rx_sof_overruns),
941 GBE_STATSD_INFO(rx_mof_overruns),
942 GBE_STATSD_INFO(rx_dma_overruns),
943 };
944
945 /* This is the size of entries in GBENU_STATS_HOST */
946 #define GBENU_ET_STATS_HOST_SIZE 52
947
948 #define GBENU_STATS_HOST(field) \
949 { \
950 "GBE_HOST:"#field, GBENU_STATS0_MODULE, \
951 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
952 offsetof(struct gbenu_hw_stats, field) \
953 }
954
955 /* This is the size of entries in GBENU_STATS_PORT */
956 #define GBENU_ET_STATS_PORT_SIZE 65
957
958 #define GBENU_STATS_P1(field) \
959 { \
960 "GBE_P1:"#field, GBENU_STATS1_MODULE, \
961 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
962 offsetof(struct gbenu_hw_stats, field) \
963 }
964
965 #define GBENU_STATS_P2(field) \
966 { \
967 "GBE_P2:"#field, GBENU_STATS2_MODULE, \
968 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
969 offsetof(struct gbenu_hw_stats, field) \
970 }
971
972 #define GBENU_STATS_P3(field) \
973 { \
974 "GBE_P3:"#field, GBENU_STATS3_MODULE, \
975 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
976 offsetof(struct gbenu_hw_stats, field) \
977 }
978
979 #define GBENU_STATS_P4(field) \
980 { \
981 "GBE_P4:"#field, GBENU_STATS4_MODULE, \
982 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
983 offsetof(struct gbenu_hw_stats, field) \
984 }
985
986 #define GBENU_STATS_P5(field) \
987 { \
988 "GBE_P5:"#field, GBENU_STATS5_MODULE, \
989 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
990 offsetof(struct gbenu_hw_stats, field) \
991 }
992
993 #define GBENU_STATS_P6(field) \
994 { \
995 "GBE_P6:"#field, GBENU_STATS6_MODULE, \
996 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
997 offsetof(struct gbenu_hw_stats, field) \
998 }
999
1000 #define GBENU_STATS_P7(field) \
1001 { \
1002 "GBE_P7:"#field, GBENU_STATS7_MODULE, \
1003 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
1004 offsetof(struct gbenu_hw_stats, field) \
1005 }
1006
1007 #define GBENU_STATS_P8(field) \
1008 { \
1009 "GBE_P8:"#field, GBENU_STATS8_MODULE, \
1010 FIELD_SIZEOF(struct gbenu_hw_stats, field), \
1011 offsetof(struct gbenu_hw_stats, field) \
1012 }
1013
1014 static const struct netcp_ethtool_stat gbenu_et_stats[] = {
1015 /* GBENU Host Module */
1016 GBENU_STATS_HOST(rx_good_frames),
1017 GBENU_STATS_HOST(rx_broadcast_frames),
1018 GBENU_STATS_HOST(rx_multicast_frames),
1019 GBENU_STATS_HOST(rx_crc_errors),
1020 GBENU_STATS_HOST(rx_oversized_frames),
1021 GBENU_STATS_HOST(rx_undersized_frames),
1022 GBENU_STATS_HOST(ale_drop),
1023 GBENU_STATS_HOST(ale_overrun_drop),
1024 GBENU_STATS_HOST(rx_bytes),
1025 GBENU_STATS_HOST(tx_good_frames),
1026 GBENU_STATS_HOST(tx_broadcast_frames),
1027 GBENU_STATS_HOST(tx_multicast_frames),
1028 GBENU_STATS_HOST(tx_bytes),
1029 GBENU_STATS_HOST(tx_64B_frames),
1030 GBENU_STATS_HOST(tx_65_to_127B_frames),
1031 GBENU_STATS_HOST(tx_128_to_255B_frames),
1032 GBENU_STATS_HOST(tx_256_to_511B_frames),
1033 GBENU_STATS_HOST(tx_512_to_1023B_frames),
1034 GBENU_STATS_HOST(tx_1024B_frames),
1035 GBENU_STATS_HOST(net_bytes),
1036 GBENU_STATS_HOST(rx_bottom_fifo_drop),
1037 GBENU_STATS_HOST(rx_port_mask_drop),
1038 GBENU_STATS_HOST(rx_top_fifo_drop),
1039 GBENU_STATS_HOST(ale_rate_limit_drop),
1040 GBENU_STATS_HOST(ale_vid_ingress_drop),
1041 GBENU_STATS_HOST(ale_da_eq_sa_drop),
1042 GBENU_STATS_HOST(ale_unknown_ucast),
1043 GBENU_STATS_HOST(ale_unknown_ucast_bytes),
1044 GBENU_STATS_HOST(ale_unknown_mcast),
1045 GBENU_STATS_HOST(ale_unknown_mcast_bytes),
1046 GBENU_STATS_HOST(ale_unknown_bcast),
1047 GBENU_STATS_HOST(ale_unknown_bcast_bytes),
1048 GBENU_STATS_HOST(ale_pol_match),
1049 GBENU_STATS_HOST(ale_pol_match_red),
1050 GBENU_STATS_HOST(ale_pol_match_yellow),
1051 GBENU_STATS_HOST(tx_mem_protect_err),
1052 GBENU_STATS_HOST(tx_pri0_drop),
1053 GBENU_STATS_HOST(tx_pri1_drop),
1054 GBENU_STATS_HOST(tx_pri2_drop),
1055 GBENU_STATS_HOST(tx_pri3_drop),
1056 GBENU_STATS_HOST(tx_pri4_drop),
1057 GBENU_STATS_HOST(tx_pri5_drop),
1058 GBENU_STATS_HOST(tx_pri6_drop),
1059 GBENU_STATS_HOST(tx_pri7_drop),
1060 GBENU_STATS_HOST(tx_pri0_drop_bcnt),
1061 GBENU_STATS_HOST(tx_pri1_drop_bcnt),
1062 GBENU_STATS_HOST(tx_pri2_drop_bcnt),
1063 GBENU_STATS_HOST(tx_pri3_drop_bcnt),
1064 GBENU_STATS_HOST(tx_pri4_drop_bcnt),
1065 GBENU_STATS_HOST(tx_pri5_drop_bcnt),
1066 GBENU_STATS_HOST(tx_pri6_drop_bcnt),
1067 GBENU_STATS_HOST(tx_pri7_drop_bcnt),
1068 /* GBENU Module 1 */
1069 GBENU_STATS_P1(rx_good_frames),
1070 GBENU_STATS_P1(rx_broadcast_frames),
1071 GBENU_STATS_P1(rx_multicast_frames),
1072 GBENU_STATS_P1(rx_pause_frames),
1073 GBENU_STATS_P1(rx_crc_errors),
1074 GBENU_STATS_P1(rx_align_code_errors),
1075 GBENU_STATS_P1(rx_oversized_frames),
1076 GBENU_STATS_P1(rx_jabber_frames),
1077 GBENU_STATS_P1(rx_undersized_frames),
1078 GBENU_STATS_P1(rx_fragments),
1079 GBENU_STATS_P1(ale_drop),
1080 GBENU_STATS_P1(ale_overrun_drop),
1081 GBENU_STATS_P1(rx_bytes),
1082 GBENU_STATS_P1(tx_good_frames),
1083 GBENU_STATS_P1(tx_broadcast_frames),
1084 GBENU_STATS_P1(tx_multicast_frames),
1085 GBENU_STATS_P1(tx_pause_frames),
1086 GBENU_STATS_P1(tx_deferred_frames),
1087 GBENU_STATS_P1(tx_collision_frames),
1088 GBENU_STATS_P1(tx_single_coll_frames),
1089 GBENU_STATS_P1(tx_mult_coll_frames),
1090 GBENU_STATS_P1(tx_excessive_collisions),
1091 GBENU_STATS_P1(tx_late_collisions),
1092 GBENU_STATS_P1(rx_ipg_error),
1093 GBENU_STATS_P1(tx_carrier_sense_errors),
1094 GBENU_STATS_P1(tx_bytes),
1095 GBENU_STATS_P1(tx_64B_frames),
1096 GBENU_STATS_P1(tx_65_to_127B_frames),
1097 GBENU_STATS_P1(tx_128_to_255B_frames),
1098 GBENU_STATS_P1(tx_256_to_511B_frames),
1099 GBENU_STATS_P1(tx_512_to_1023B_frames),
1100 GBENU_STATS_P1(tx_1024B_frames),
1101 GBENU_STATS_P1(net_bytes),
1102 GBENU_STATS_P1(rx_bottom_fifo_drop),
1103 GBENU_STATS_P1(rx_port_mask_drop),
1104 GBENU_STATS_P1(rx_top_fifo_drop),
1105 GBENU_STATS_P1(ale_rate_limit_drop),
1106 GBENU_STATS_P1(ale_vid_ingress_drop),
1107 GBENU_STATS_P1(ale_da_eq_sa_drop),
1108 GBENU_STATS_P1(ale_unknown_ucast),
1109 GBENU_STATS_P1(ale_unknown_ucast_bytes),
1110 GBENU_STATS_P1(ale_unknown_mcast),
1111 GBENU_STATS_P1(ale_unknown_mcast_bytes),
1112 GBENU_STATS_P1(ale_unknown_bcast),
1113 GBENU_STATS_P1(ale_unknown_bcast_bytes),
1114 GBENU_STATS_P1(ale_pol_match),
1115 GBENU_STATS_P1(ale_pol_match_red),
1116 GBENU_STATS_P1(ale_pol_match_yellow),
1117 GBENU_STATS_P1(tx_mem_protect_err),
1118 GBENU_STATS_P1(tx_pri0_drop),
1119 GBENU_STATS_P1(tx_pri1_drop),
1120 GBENU_STATS_P1(tx_pri2_drop),
1121 GBENU_STATS_P1(tx_pri3_drop),
1122 GBENU_STATS_P1(tx_pri4_drop),
1123 GBENU_STATS_P1(tx_pri5_drop),
1124 GBENU_STATS_P1(tx_pri6_drop),
1125 GBENU_STATS_P1(tx_pri7_drop),
1126 GBENU_STATS_P1(tx_pri0_drop_bcnt),
1127 GBENU_STATS_P1(tx_pri1_drop_bcnt),
1128 GBENU_STATS_P1(tx_pri2_drop_bcnt),
1129 GBENU_STATS_P1(tx_pri3_drop_bcnt),
1130 GBENU_STATS_P1(tx_pri4_drop_bcnt),
1131 GBENU_STATS_P1(tx_pri5_drop_bcnt),
1132 GBENU_STATS_P1(tx_pri6_drop_bcnt),
1133 GBENU_STATS_P1(tx_pri7_drop_bcnt),
1134 /* GBENU Module 2 */
1135 GBENU_STATS_P2(rx_good_frames),
1136 GBENU_STATS_P2(rx_broadcast_frames),
1137 GBENU_STATS_P2(rx_multicast_frames),
1138 GBENU_STATS_P2(rx_pause_frames),
1139 GBENU_STATS_P2(rx_crc_errors),
1140 GBENU_STATS_P2(rx_align_code_errors),
1141 GBENU_STATS_P2(rx_oversized_frames),
1142 GBENU_STATS_P2(rx_jabber_frames),
1143 GBENU_STATS_P2(rx_undersized_frames),
1144 GBENU_STATS_P2(rx_fragments),
1145 GBENU_STATS_P2(ale_drop),
1146 GBENU_STATS_P2(ale_overrun_drop),
1147 GBENU_STATS_P2(rx_bytes),
1148 GBENU_STATS_P2(tx_good_frames),
1149 GBENU_STATS_P2(tx_broadcast_frames),
1150 GBENU_STATS_P2(tx_multicast_frames),
1151 GBENU_STATS_P2(tx_pause_frames),
1152 GBENU_STATS_P2(tx_deferred_frames),
1153 GBENU_STATS_P2(tx_collision_frames),
1154 GBENU_STATS_P2(tx_single_coll_frames),
1155 GBENU_STATS_P2(tx_mult_coll_frames),
1156 GBENU_STATS_P2(tx_excessive_collisions),
1157 GBENU_STATS_P2(tx_late_collisions),
1158 GBENU_STATS_P2(rx_ipg_error),
1159 GBENU_STATS_P2(tx_carrier_sense_errors),
1160 GBENU_STATS_P2(tx_bytes),
1161 GBENU_STATS_P2(tx_64B_frames),
1162 GBENU_STATS_P2(tx_65_to_127B_frames),
1163 GBENU_STATS_P2(tx_128_to_255B_frames),
1164 GBENU_STATS_P2(tx_256_to_511B_frames),
1165 GBENU_STATS_P2(tx_512_to_1023B_frames),
1166 GBENU_STATS_P2(tx_1024B_frames),
1167 GBENU_STATS_P2(net_bytes),
1168 GBENU_STATS_P2(rx_bottom_fifo_drop),
1169 GBENU_STATS_P2(rx_port_mask_drop),
1170 GBENU_STATS_P2(rx_top_fifo_drop),
1171 GBENU_STATS_P2(ale_rate_limit_drop),
1172 GBENU_STATS_P2(ale_vid_ingress_drop),
1173 GBENU_STATS_P2(ale_da_eq_sa_drop),
1174 GBENU_STATS_P2(ale_unknown_ucast),
1175 GBENU_STATS_P2(ale_unknown_ucast_bytes),
1176 GBENU_STATS_P2(ale_unknown_mcast),
1177 GBENU_STATS_P2(ale_unknown_mcast_bytes),
1178 GBENU_STATS_P2(ale_unknown_bcast),
1179 GBENU_STATS_P2(ale_unknown_bcast_bytes),
1180 GBENU_STATS_P2(ale_pol_match),
1181 GBENU_STATS_P2(ale_pol_match_red),
1182 GBENU_STATS_P2(ale_pol_match_yellow),
1183 GBENU_STATS_P2(tx_mem_protect_err),
1184 GBENU_STATS_P2(tx_pri0_drop),
1185 GBENU_STATS_P2(tx_pri1_drop),
1186 GBENU_STATS_P2(tx_pri2_drop),
1187 GBENU_STATS_P2(tx_pri3_drop),
1188 GBENU_STATS_P2(tx_pri4_drop),
1189 GBENU_STATS_P2(tx_pri5_drop),
1190 GBENU_STATS_P2(tx_pri6_drop),
1191 GBENU_STATS_P2(tx_pri7_drop),
1192 GBENU_STATS_P2(tx_pri0_drop_bcnt),
1193 GBENU_STATS_P2(tx_pri1_drop_bcnt),
1194 GBENU_STATS_P2(tx_pri2_drop_bcnt),
1195 GBENU_STATS_P2(tx_pri3_drop_bcnt),
1196 GBENU_STATS_P2(tx_pri4_drop_bcnt),
1197 GBENU_STATS_P2(tx_pri5_drop_bcnt),
1198 GBENU_STATS_P2(tx_pri6_drop_bcnt),
1199 GBENU_STATS_P2(tx_pri7_drop_bcnt),
1200 /* GBENU Module 3 */
1201 GBENU_STATS_P3(rx_good_frames),
1202 GBENU_STATS_P3(rx_broadcast_frames),
1203 GBENU_STATS_P3(rx_multicast_frames),
1204 GBENU_STATS_P3(rx_pause_frames),
1205 GBENU_STATS_P3(rx_crc_errors),
1206 GBENU_STATS_P3(rx_align_code_errors),
1207 GBENU_STATS_P3(rx_oversized_frames),
1208 GBENU_STATS_P3(rx_jabber_frames),
1209 GBENU_STATS_P3(rx_undersized_frames),
1210 GBENU_STATS_P3(rx_fragments),
1211 GBENU_STATS_P3(ale_drop),
1212 GBENU_STATS_P3(ale_overrun_drop),
1213 GBENU_STATS_P3(rx_bytes),
1214 GBENU_STATS_P3(tx_good_frames),
1215 GBENU_STATS_P3(tx_broadcast_frames),
1216 GBENU_STATS_P3(tx_multicast_frames),
1217 GBENU_STATS_P3(tx_pause_frames),
1218 GBENU_STATS_P3(tx_deferred_frames),
1219 GBENU_STATS_P3(tx_collision_frames),
1220 GBENU_STATS_P3(tx_single_coll_frames),
1221 GBENU_STATS_P3(tx_mult_coll_frames),
1222 GBENU_STATS_P3(tx_excessive_collisions),
1223 GBENU_STATS_P3(tx_late_collisions),
1224 GBENU_STATS_P3(rx_ipg_error),
1225 GBENU_STATS_P3(tx_carrier_sense_errors),
1226 GBENU_STATS_P3(tx_bytes),
1227 GBENU_STATS_P3(tx_64B_frames),
1228 GBENU_STATS_P3(tx_65_to_127B_frames),
1229 GBENU_STATS_P3(tx_128_to_255B_frames),
1230 GBENU_STATS_P3(tx_256_to_511B_frames),
1231 GBENU_STATS_P3(tx_512_to_1023B_frames),
1232 GBENU_STATS_P3(tx_1024B_frames),
1233 GBENU_STATS_P3(net_bytes),
1234 GBENU_STATS_P3(rx_bottom_fifo_drop),
1235 GBENU_STATS_P3(rx_port_mask_drop),
1236 GBENU_STATS_P3(rx_top_fifo_drop),
1237 GBENU_STATS_P3(ale_rate_limit_drop),
1238 GBENU_STATS_P3(ale_vid_ingress_drop),
1239 GBENU_STATS_P3(ale_da_eq_sa_drop),
1240 GBENU_STATS_P3(ale_unknown_ucast),
1241 GBENU_STATS_P3(ale_unknown_ucast_bytes),
1242 GBENU_STATS_P3(ale_unknown_mcast),
1243 GBENU_STATS_P3(ale_unknown_mcast_bytes),
1244 GBENU_STATS_P3(ale_unknown_bcast),
1245 GBENU_STATS_P3(ale_unknown_bcast_bytes),
1246 GBENU_STATS_P3(ale_pol_match),
1247 GBENU_STATS_P3(ale_pol_match_red),
1248 GBENU_STATS_P3(ale_pol_match_yellow),
1249 GBENU_STATS_P3(tx_mem_protect_err),
1250 GBENU_STATS_P3(tx_pri0_drop),
1251 GBENU_STATS_P3(tx_pri1_drop),
1252 GBENU_STATS_P3(tx_pri2_drop),
1253 GBENU_STATS_P3(tx_pri3_drop),
1254 GBENU_STATS_P3(tx_pri4_drop),
1255 GBENU_STATS_P3(tx_pri5_drop),
1256 GBENU_STATS_P3(tx_pri6_drop),
1257 GBENU_STATS_P3(tx_pri7_drop),
1258 GBENU_STATS_P3(tx_pri0_drop_bcnt),
1259 GBENU_STATS_P3(tx_pri1_drop_bcnt),
1260 GBENU_STATS_P3(tx_pri2_drop_bcnt),
1261 GBENU_STATS_P3(tx_pri3_drop_bcnt),
1262 GBENU_STATS_P3(tx_pri4_drop_bcnt),
1263 GBENU_STATS_P3(tx_pri5_drop_bcnt),
1264 GBENU_STATS_P3(tx_pri6_drop_bcnt),
1265 GBENU_STATS_P3(tx_pri7_drop_bcnt),
1266 /* GBENU Module 4 */
1267 GBENU_STATS_P4(rx_good_frames),
1268 GBENU_STATS_P4(rx_broadcast_frames),
1269 GBENU_STATS_P4(rx_multicast_frames),
1270 GBENU_STATS_P4(rx_pause_frames),
1271 GBENU_STATS_P4(rx_crc_errors),
1272 GBENU_STATS_P4(rx_align_code_errors),
1273 GBENU_STATS_P4(rx_oversized_frames),
1274 GBENU_STATS_P4(rx_jabber_frames),
1275 GBENU_STATS_P4(rx_undersized_frames),
1276 GBENU_STATS_P4(rx_fragments),
1277 GBENU_STATS_P4(ale_drop),
1278 GBENU_STATS_P4(ale_overrun_drop),
1279 GBENU_STATS_P4(rx_bytes),
1280 GBENU_STATS_P4(tx_good_frames),
1281 GBENU_STATS_P4(tx_broadcast_frames),
1282 GBENU_STATS_P4(tx_multicast_frames),
1283 GBENU_STATS_P4(tx_pause_frames),
1284 GBENU_STATS_P4(tx_deferred_frames),
1285 GBENU_STATS_P4(tx_collision_frames),
1286 GBENU_STATS_P4(tx_single_coll_frames),
1287 GBENU_STATS_P4(tx_mult_coll_frames),
1288 GBENU_STATS_P4(tx_excessive_collisions),
1289 GBENU_STATS_P4(tx_late_collisions),
1290 GBENU_STATS_P4(rx_ipg_error),
1291 GBENU_STATS_P4(tx_carrier_sense_errors),
1292 GBENU_STATS_P4(tx_bytes),
1293 GBENU_STATS_P4(tx_64B_frames),
1294 GBENU_STATS_P4(tx_65_to_127B_frames),
1295 GBENU_STATS_P4(tx_128_to_255B_frames),
1296 GBENU_STATS_P4(tx_256_to_511B_frames),
1297 GBENU_STATS_P4(tx_512_to_1023B_frames),
1298 GBENU_STATS_P4(tx_1024B_frames),
1299 GBENU_STATS_P4(net_bytes),
1300 GBENU_STATS_P4(rx_bottom_fifo_drop),
1301 GBENU_STATS_P4(rx_port_mask_drop),
1302 GBENU_STATS_P4(rx_top_fifo_drop),
1303 GBENU_STATS_P4(ale_rate_limit_drop),
1304 GBENU_STATS_P4(ale_vid_ingress_drop),
1305 GBENU_STATS_P4(ale_da_eq_sa_drop),
1306 GBENU_STATS_P4(ale_unknown_ucast),
1307 GBENU_STATS_P4(ale_unknown_ucast_bytes),
1308 GBENU_STATS_P4(ale_unknown_mcast),
1309 GBENU_STATS_P4(ale_unknown_mcast_bytes),
1310 GBENU_STATS_P4(ale_unknown_bcast),
1311 GBENU_STATS_P4(ale_unknown_bcast_bytes),
1312 GBENU_STATS_P4(ale_pol_match),
1313 GBENU_STATS_P4(ale_pol_match_red),
1314 GBENU_STATS_P4(ale_pol_match_yellow),
1315 GBENU_STATS_P4(tx_mem_protect_err),
1316 GBENU_STATS_P4(tx_pri0_drop),
1317 GBENU_STATS_P4(tx_pri1_drop),
1318 GBENU_STATS_P4(tx_pri2_drop),
1319 GBENU_STATS_P4(tx_pri3_drop),
1320 GBENU_STATS_P4(tx_pri4_drop),
1321 GBENU_STATS_P4(tx_pri5_drop),
1322 GBENU_STATS_P4(tx_pri6_drop),
1323 GBENU_STATS_P4(tx_pri7_drop),
1324 GBENU_STATS_P4(tx_pri0_drop_bcnt),
1325 GBENU_STATS_P4(tx_pri1_drop_bcnt),
1326 GBENU_STATS_P4(tx_pri2_drop_bcnt),
1327 GBENU_STATS_P4(tx_pri3_drop_bcnt),
1328 GBENU_STATS_P4(tx_pri4_drop_bcnt),
1329 GBENU_STATS_P4(tx_pri5_drop_bcnt),
1330 GBENU_STATS_P4(tx_pri6_drop_bcnt),
1331 GBENU_STATS_P4(tx_pri7_drop_bcnt),
1332 /* GBENU Module 5 */
1333 GBENU_STATS_P5(rx_good_frames),
1334 GBENU_STATS_P5(rx_broadcast_frames),
1335 GBENU_STATS_P5(rx_multicast_frames),
1336 GBENU_STATS_P5(rx_pause_frames),
1337 GBENU_STATS_P5(rx_crc_errors),
1338 GBENU_STATS_P5(rx_align_code_errors),
1339 GBENU_STATS_P5(rx_oversized_frames),
1340 GBENU_STATS_P5(rx_jabber_frames),
1341 GBENU_STATS_P5(rx_undersized_frames),
1342 GBENU_STATS_P5(rx_fragments),
1343 GBENU_STATS_P5(ale_drop),
1344 GBENU_STATS_P5(ale_overrun_drop),
1345 GBENU_STATS_P5(rx_bytes),
1346 GBENU_STATS_P5(tx_good_frames),
1347 GBENU_STATS_P5(tx_broadcast_frames),
1348 GBENU_STATS_P5(tx_multicast_frames),
1349 GBENU_STATS_P5(tx_pause_frames),
1350 GBENU_STATS_P5(tx_deferred_frames),
1351 GBENU_STATS_P5(tx_collision_frames),
1352 GBENU_STATS_P5(tx_single_coll_frames),
1353 GBENU_STATS_P5(tx_mult_coll_frames),
1354 GBENU_STATS_P5(tx_excessive_collisions),
1355 GBENU_STATS_P5(tx_late_collisions),
1356 GBENU_STATS_P5(rx_ipg_error),
1357 GBENU_STATS_P5(tx_carrier_sense_errors),
1358 GBENU_STATS_P5(tx_bytes),
1359 GBENU_STATS_P5(tx_64B_frames),
1360 GBENU_STATS_P5(tx_65_to_127B_frames),
1361 GBENU_STATS_P5(tx_128_to_255B_frames),
1362 GBENU_STATS_P5(tx_256_to_511B_frames),
1363 GBENU_STATS_P5(tx_512_to_1023B_frames),
1364 GBENU_STATS_P5(tx_1024B_frames),
1365 GBENU_STATS_P5(net_bytes),
1366 GBENU_STATS_P5(rx_bottom_fifo_drop),
1367 GBENU_STATS_P5(rx_port_mask_drop),
1368 GBENU_STATS_P5(rx_top_fifo_drop),
1369 GBENU_STATS_P5(ale_rate_limit_drop),
1370 GBENU_STATS_P5(ale_vid_ingress_drop),
1371 GBENU_STATS_P5(ale_da_eq_sa_drop),
1372 GBENU_STATS_P5(ale_unknown_ucast),
1373 GBENU_STATS_P5(ale_unknown_ucast_bytes),
1374 GBENU_STATS_P5(ale_unknown_mcast),
1375 GBENU_STATS_P5(ale_unknown_mcast_bytes),
1376 GBENU_STATS_P5(ale_unknown_bcast),
1377 GBENU_STATS_P5(ale_unknown_bcast_bytes),
1378 GBENU_STATS_P5(ale_pol_match),
1379 GBENU_STATS_P5(ale_pol_match_red),
1380 GBENU_STATS_P5(ale_pol_match_yellow),
1381 GBENU_STATS_P5(tx_mem_protect_err),
1382 GBENU_STATS_P5(tx_pri0_drop),
1383 GBENU_STATS_P5(tx_pri1_drop),
1384 GBENU_STATS_P5(tx_pri2_drop),
1385 GBENU_STATS_P5(tx_pri3_drop),
1386 GBENU_STATS_P5(tx_pri4_drop),
1387 GBENU_STATS_P5(tx_pri5_drop),
1388 GBENU_STATS_P5(tx_pri6_drop),
1389 GBENU_STATS_P5(tx_pri7_drop),
1390 GBENU_STATS_P5(tx_pri0_drop_bcnt),
1391 GBENU_STATS_P5(tx_pri1_drop_bcnt),
1392 GBENU_STATS_P5(tx_pri2_drop_bcnt),
1393 GBENU_STATS_P5(tx_pri3_drop_bcnt),
1394 GBENU_STATS_P5(tx_pri4_drop_bcnt),
1395 GBENU_STATS_P5(tx_pri5_drop_bcnt),
1396 GBENU_STATS_P5(tx_pri6_drop_bcnt),
1397 GBENU_STATS_P5(tx_pri7_drop_bcnt),
1398 /* GBENU Module 6 */
1399 GBENU_STATS_P6(rx_good_frames),
1400 GBENU_STATS_P6(rx_broadcast_frames),
1401 GBENU_STATS_P6(rx_multicast_frames),
1402 GBENU_STATS_P6(rx_pause_frames),
1403 GBENU_STATS_P6(rx_crc_errors),
1404 GBENU_STATS_P6(rx_align_code_errors),
1405 GBENU_STATS_P6(rx_oversized_frames),
1406 GBENU_STATS_P6(rx_jabber_frames),
1407 GBENU_STATS_P6(rx_undersized_frames),
1408 GBENU_STATS_P6(rx_fragments),
1409 GBENU_STATS_P6(ale_drop),
1410 GBENU_STATS_P6(ale_overrun_drop),
1411 GBENU_STATS_P6(rx_bytes),
1412 GBENU_STATS_P6(tx_good_frames),
1413 GBENU_STATS_P6(tx_broadcast_frames),
1414 GBENU_STATS_P6(tx_multicast_frames),
1415 GBENU_STATS_P6(tx_pause_frames),
1416 GBENU_STATS_P6(tx_deferred_frames),
1417 GBENU_STATS_P6(tx_collision_frames),
1418 GBENU_STATS_P6(tx_single_coll_frames),
1419 GBENU_STATS_P6(tx_mult_coll_frames),
1420 GBENU_STATS_P6(tx_excessive_collisions),
1421 GBENU_STATS_P6(tx_late_collisions),
1422 GBENU_STATS_P6(rx_ipg_error),
1423 GBENU_STATS_P6(tx_carrier_sense_errors),
1424 GBENU_STATS_P6(tx_bytes),
1425 GBENU_STATS_P6(tx_64B_frames),
1426 GBENU_STATS_P6(tx_65_to_127B_frames),
1427 GBENU_STATS_P6(tx_128_to_255B_frames),
1428 GBENU_STATS_P6(tx_256_to_511B_frames),
1429 GBENU_STATS_P6(tx_512_to_1023B_frames),
1430 GBENU_STATS_P6(tx_1024B_frames),
1431 GBENU_STATS_P6(net_bytes),
1432 GBENU_STATS_P6(rx_bottom_fifo_drop),
1433 GBENU_STATS_P6(rx_port_mask_drop),
1434 GBENU_STATS_P6(rx_top_fifo_drop),
1435 GBENU_STATS_P6(ale_rate_limit_drop),
1436 GBENU_STATS_P6(ale_vid_ingress_drop),
1437 GBENU_STATS_P6(ale_da_eq_sa_drop),
1438 GBENU_STATS_P6(ale_unknown_ucast),
1439 GBENU_STATS_P6(ale_unknown_ucast_bytes),
1440 GBENU_STATS_P6(ale_unknown_mcast),
1441 GBENU_STATS_P6(ale_unknown_mcast_bytes),
1442 GBENU_STATS_P6(ale_unknown_bcast),
1443 GBENU_STATS_P6(ale_unknown_bcast_bytes),
1444 GBENU_STATS_P6(ale_pol_match),
1445 GBENU_STATS_P6(ale_pol_match_red),
1446 GBENU_STATS_P6(ale_pol_match_yellow),
1447 GBENU_STATS_P6(tx_mem_protect_err),
1448 GBENU_STATS_P6(tx_pri0_drop),
1449 GBENU_STATS_P6(tx_pri1_drop),
1450 GBENU_STATS_P6(tx_pri2_drop),
1451 GBENU_STATS_P6(tx_pri3_drop),
1452 GBENU_STATS_P6(tx_pri4_drop),
1453 GBENU_STATS_P6(tx_pri5_drop),
1454 GBENU_STATS_P6(tx_pri6_drop),
1455 GBENU_STATS_P6(tx_pri7_drop),
1456 GBENU_STATS_P6(tx_pri0_drop_bcnt),
1457 GBENU_STATS_P6(tx_pri1_drop_bcnt),
1458 GBENU_STATS_P6(tx_pri2_drop_bcnt),
1459 GBENU_STATS_P6(tx_pri3_drop_bcnt),
1460 GBENU_STATS_P6(tx_pri4_drop_bcnt),
1461 GBENU_STATS_P6(tx_pri5_drop_bcnt),
1462 GBENU_STATS_P6(tx_pri6_drop_bcnt),
1463 GBENU_STATS_P6(tx_pri7_drop_bcnt),
1464 /* GBENU Module 7 */
1465 GBENU_STATS_P7(rx_good_frames),
1466 GBENU_STATS_P7(rx_broadcast_frames),
1467 GBENU_STATS_P7(rx_multicast_frames),
1468 GBENU_STATS_P7(rx_pause_frames),
1469 GBENU_STATS_P7(rx_crc_errors),
1470 GBENU_STATS_P7(rx_align_code_errors),
1471 GBENU_STATS_P7(rx_oversized_frames),
1472 GBENU_STATS_P7(rx_jabber_frames),
1473 GBENU_STATS_P7(rx_undersized_frames),
1474 GBENU_STATS_P7(rx_fragments),
1475 GBENU_STATS_P7(ale_drop),
1476 GBENU_STATS_P7(ale_overrun_drop),
1477 GBENU_STATS_P7(rx_bytes),
1478 GBENU_STATS_P7(tx_good_frames),
1479 GBENU_STATS_P7(tx_broadcast_frames),
1480 GBENU_STATS_P7(tx_multicast_frames),
1481 GBENU_STATS_P7(tx_pause_frames),
1482 GBENU_STATS_P7(tx_deferred_frames),
1483 GBENU_STATS_P7(tx_collision_frames),
1484 GBENU_STATS_P7(tx_single_coll_frames),
1485 GBENU_STATS_P7(tx_mult_coll_frames),
1486 GBENU_STATS_P7(tx_excessive_collisions),
1487 GBENU_STATS_P7(tx_late_collisions),
1488 GBENU_STATS_P7(rx_ipg_error),
1489 GBENU_STATS_P7(tx_carrier_sense_errors),
1490 GBENU_STATS_P7(tx_bytes),
1491 GBENU_STATS_P7(tx_64B_frames),
1492 GBENU_STATS_P7(tx_65_to_127B_frames),
1493 GBENU_STATS_P7(tx_128_to_255B_frames),
1494 GBENU_STATS_P7(tx_256_to_511B_frames),
1495 GBENU_STATS_P7(tx_512_to_1023B_frames),
1496 GBENU_STATS_P7(tx_1024B_frames),
1497 GBENU_STATS_P7(net_bytes),
1498 GBENU_STATS_P7(rx_bottom_fifo_drop),
1499 GBENU_STATS_P7(rx_port_mask_drop),
1500 GBENU_STATS_P7(rx_top_fifo_drop),
1501 GBENU_STATS_P7(ale_rate_limit_drop),
1502 GBENU_STATS_P7(ale_vid_ingress_drop),
1503 GBENU_STATS_P7(ale_da_eq_sa_drop),
1504 GBENU_STATS_P7(ale_unknown_ucast),
1505 GBENU_STATS_P7(ale_unknown_ucast_bytes),
1506 GBENU_STATS_P7(ale_unknown_mcast),
1507 GBENU_STATS_P7(ale_unknown_mcast_bytes),
1508 GBENU_STATS_P7(ale_unknown_bcast),
1509 GBENU_STATS_P7(ale_unknown_bcast_bytes),
1510 GBENU_STATS_P7(ale_pol_match),
1511 GBENU_STATS_P7(ale_pol_match_red),
1512 GBENU_STATS_P7(ale_pol_match_yellow),
1513 GBENU_STATS_P7(tx_mem_protect_err),
1514 GBENU_STATS_P7(tx_pri0_drop),
1515 GBENU_STATS_P7(tx_pri1_drop),
1516 GBENU_STATS_P7(tx_pri2_drop),
1517 GBENU_STATS_P7(tx_pri3_drop),
1518 GBENU_STATS_P7(tx_pri4_drop),
1519 GBENU_STATS_P7(tx_pri5_drop),
1520 GBENU_STATS_P7(tx_pri6_drop),
1521 GBENU_STATS_P7(tx_pri7_drop),
1522 GBENU_STATS_P7(tx_pri0_drop_bcnt),
1523 GBENU_STATS_P7(tx_pri1_drop_bcnt),
1524 GBENU_STATS_P7(tx_pri2_drop_bcnt),
1525 GBENU_STATS_P7(tx_pri3_drop_bcnt),
1526 GBENU_STATS_P7(tx_pri4_drop_bcnt),
1527 GBENU_STATS_P7(tx_pri5_drop_bcnt),
1528 GBENU_STATS_P7(tx_pri6_drop_bcnt),
1529 GBENU_STATS_P7(tx_pri7_drop_bcnt),
1530 /* GBENU Module 8 */
1531 GBENU_STATS_P8(rx_good_frames),
1532 GBENU_STATS_P8(rx_broadcast_frames),
1533 GBENU_STATS_P8(rx_multicast_frames),
1534 GBENU_STATS_P8(rx_pause_frames),
1535 GBENU_STATS_P8(rx_crc_errors),
1536 GBENU_STATS_P8(rx_align_code_errors),
1537 GBENU_STATS_P8(rx_oversized_frames),
1538 GBENU_STATS_P8(rx_jabber_frames),
1539 GBENU_STATS_P8(rx_undersized_frames),
1540 GBENU_STATS_P8(rx_fragments),
1541 GBENU_STATS_P8(ale_drop),
1542 GBENU_STATS_P8(ale_overrun_drop),
1543 GBENU_STATS_P8(rx_bytes),
1544 GBENU_STATS_P8(tx_good_frames),
1545 GBENU_STATS_P8(tx_broadcast_frames),
1546 GBENU_STATS_P8(tx_multicast_frames),
1547 GBENU_STATS_P8(tx_pause_frames),
1548 GBENU_STATS_P8(tx_deferred_frames),
1549 GBENU_STATS_P8(tx_collision_frames),
1550 GBENU_STATS_P8(tx_single_coll_frames),
1551 GBENU_STATS_P8(tx_mult_coll_frames),
1552 GBENU_STATS_P8(tx_excessive_collisions),
1553 GBENU_STATS_P8(tx_late_collisions),
1554 GBENU_STATS_P8(rx_ipg_error),
1555 GBENU_STATS_P8(tx_carrier_sense_errors),
1556 GBENU_STATS_P8(tx_bytes),
1557 GBENU_STATS_P8(tx_64B_frames),
1558 GBENU_STATS_P8(tx_65_to_127B_frames),
1559 GBENU_STATS_P8(tx_128_to_255B_frames),
1560 GBENU_STATS_P8(tx_256_to_511B_frames),
1561 GBENU_STATS_P8(tx_512_to_1023B_frames),
1562 GBENU_STATS_P8(tx_1024B_frames),
1563 GBENU_STATS_P8(net_bytes),
1564 GBENU_STATS_P8(rx_bottom_fifo_drop),
1565 GBENU_STATS_P8(rx_port_mask_drop),
1566 GBENU_STATS_P8(rx_top_fifo_drop),
1567 GBENU_STATS_P8(ale_rate_limit_drop),
1568 GBENU_STATS_P8(ale_vid_ingress_drop),
1569 GBENU_STATS_P8(ale_da_eq_sa_drop),
1570 GBENU_STATS_P8(ale_unknown_ucast),
1571 GBENU_STATS_P8(ale_unknown_ucast_bytes),
1572 GBENU_STATS_P8(ale_unknown_mcast),
1573 GBENU_STATS_P8(ale_unknown_mcast_bytes),
1574 GBENU_STATS_P8(ale_unknown_bcast),
1575 GBENU_STATS_P8(ale_unknown_bcast_bytes),
1576 GBENU_STATS_P8(ale_pol_match),
1577 GBENU_STATS_P8(ale_pol_match_red),
1578 GBENU_STATS_P8(ale_pol_match_yellow),
1579 GBENU_STATS_P8(tx_mem_protect_err),
1580 GBENU_STATS_P8(tx_pri0_drop),
1581 GBENU_STATS_P8(tx_pri1_drop),
1582 GBENU_STATS_P8(tx_pri2_drop),
1583 GBENU_STATS_P8(tx_pri3_drop),
1584 GBENU_STATS_P8(tx_pri4_drop),
1585 GBENU_STATS_P8(tx_pri5_drop),
1586 GBENU_STATS_P8(tx_pri6_drop),
1587 GBENU_STATS_P8(tx_pri7_drop),
1588 GBENU_STATS_P8(tx_pri0_drop_bcnt),
1589 GBENU_STATS_P8(tx_pri1_drop_bcnt),
1590 GBENU_STATS_P8(tx_pri2_drop_bcnt),
1591 GBENU_STATS_P8(tx_pri3_drop_bcnt),
1592 GBENU_STATS_P8(tx_pri4_drop_bcnt),
1593 GBENU_STATS_P8(tx_pri5_drop_bcnt),
1594 GBENU_STATS_P8(tx_pri6_drop_bcnt),
1595 GBENU_STATS_P8(tx_pri7_drop_bcnt),
1596 };
1597
1598 #define XGBE_STATS0_INFO(field) \
1599 { \
1600 "GBE_0:"#field, XGBE_STATS0_MODULE, \
1601 FIELD_SIZEOF(struct xgbe_hw_stats, field), \
1602 offsetof(struct xgbe_hw_stats, field) \
1603 }
1604
1605 #define XGBE_STATS1_INFO(field) \
1606 { \
1607 "GBE_1:"#field, XGBE_STATS1_MODULE, \
1608 FIELD_SIZEOF(struct xgbe_hw_stats, field), \
1609 offsetof(struct xgbe_hw_stats, field) \
1610 }
1611
1612 #define XGBE_STATS2_INFO(field) \
1613 { \
1614 "GBE_2:"#field, XGBE_STATS2_MODULE, \
1615 FIELD_SIZEOF(struct xgbe_hw_stats, field), \
1616 offsetof(struct xgbe_hw_stats, field) \
1617 }
1618
1619 static const struct netcp_ethtool_stat xgbe10_et_stats[] = {
1620 /* GBE module 0 */
1621 XGBE_STATS0_INFO(rx_good_frames),
1622 XGBE_STATS0_INFO(rx_broadcast_frames),
1623 XGBE_STATS0_INFO(rx_multicast_frames),
1624 XGBE_STATS0_INFO(rx_oversized_frames),
1625 XGBE_STATS0_INFO(rx_undersized_frames),
1626 XGBE_STATS0_INFO(overrun_type4),
1627 XGBE_STATS0_INFO(overrun_type5),
1628 XGBE_STATS0_INFO(rx_bytes),
1629 XGBE_STATS0_INFO(tx_good_frames),
1630 XGBE_STATS0_INFO(tx_broadcast_frames),
1631 XGBE_STATS0_INFO(tx_multicast_frames),
1632 XGBE_STATS0_INFO(tx_bytes),
1633 XGBE_STATS0_INFO(tx_64byte_frames),
1634 XGBE_STATS0_INFO(tx_65_to_127byte_frames),
1635 XGBE_STATS0_INFO(tx_128_to_255byte_frames),
1636 XGBE_STATS0_INFO(tx_256_to_511byte_frames),
1637 XGBE_STATS0_INFO(tx_512_to_1023byte_frames),
1638 XGBE_STATS0_INFO(tx_1024byte_frames),
1639 XGBE_STATS0_INFO(net_bytes),
1640 XGBE_STATS0_INFO(rx_sof_overruns),
1641 XGBE_STATS0_INFO(rx_mof_overruns),
1642 XGBE_STATS0_INFO(rx_dma_overruns),
1643 /* XGBE module 1 */
1644 XGBE_STATS1_INFO(rx_good_frames),
1645 XGBE_STATS1_INFO(rx_broadcast_frames),
1646 XGBE_STATS1_INFO(rx_multicast_frames),
1647 XGBE_STATS1_INFO(rx_pause_frames),
1648 XGBE_STATS1_INFO(rx_crc_errors),
1649 XGBE_STATS1_INFO(rx_align_code_errors),
1650 XGBE_STATS1_INFO(rx_oversized_frames),
1651 XGBE_STATS1_INFO(rx_jabber_frames),
1652 XGBE_STATS1_INFO(rx_undersized_frames),
1653 XGBE_STATS1_INFO(rx_fragments),
1654 XGBE_STATS1_INFO(overrun_type4),
1655 XGBE_STATS1_INFO(overrun_type5),
1656 XGBE_STATS1_INFO(rx_bytes),
1657 XGBE_STATS1_INFO(tx_good_frames),
1658 XGBE_STATS1_INFO(tx_broadcast_frames),
1659 XGBE_STATS1_INFO(tx_multicast_frames),
1660 XGBE_STATS1_INFO(tx_pause_frames),
1661 XGBE_STATS1_INFO(tx_deferred_frames),
1662 XGBE_STATS1_INFO(tx_collision_frames),
1663 XGBE_STATS1_INFO(tx_single_coll_frames),
1664 XGBE_STATS1_INFO(tx_mult_coll_frames),
1665 XGBE_STATS1_INFO(tx_excessive_collisions),
1666 XGBE_STATS1_INFO(tx_late_collisions),
1667 XGBE_STATS1_INFO(tx_underrun),
1668 XGBE_STATS1_INFO(tx_carrier_sense_errors),
1669 XGBE_STATS1_INFO(tx_bytes),
1670 XGBE_STATS1_INFO(tx_64byte_frames),
1671 XGBE_STATS1_INFO(tx_65_to_127byte_frames),
1672 XGBE_STATS1_INFO(tx_128_to_255byte_frames),
1673 XGBE_STATS1_INFO(tx_256_to_511byte_frames),
1674 XGBE_STATS1_INFO(tx_512_to_1023byte_frames),
1675 XGBE_STATS1_INFO(tx_1024byte_frames),
1676 XGBE_STATS1_INFO(net_bytes),
1677 XGBE_STATS1_INFO(rx_sof_overruns),
1678 XGBE_STATS1_INFO(rx_mof_overruns),
1679 XGBE_STATS1_INFO(rx_dma_overruns),
1680 /* XGBE module 2 */
1681 XGBE_STATS2_INFO(rx_good_frames),
1682 XGBE_STATS2_INFO(rx_broadcast_frames),
1683 XGBE_STATS2_INFO(rx_multicast_frames),
1684 XGBE_STATS2_INFO(rx_pause_frames),
1685 XGBE_STATS2_INFO(rx_crc_errors),
1686 XGBE_STATS2_INFO(rx_align_code_errors),
1687 XGBE_STATS2_INFO(rx_oversized_frames),
1688 XGBE_STATS2_INFO(rx_jabber_frames),
1689 XGBE_STATS2_INFO(rx_undersized_frames),
1690 XGBE_STATS2_INFO(rx_fragments),
1691 XGBE_STATS2_INFO(overrun_type4),
1692 XGBE_STATS2_INFO(overrun_type5),
1693 XGBE_STATS2_INFO(rx_bytes),
1694 XGBE_STATS2_INFO(tx_good_frames),
1695 XGBE_STATS2_INFO(tx_broadcast_frames),
1696 XGBE_STATS2_INFO(tx_multicast_frames),
1697 XGBE_STATS2_INFO(tx_pause_frames),
1698 XGBE_STATS2_INFO(tx_deferred_frames),
1699 XGBE_STATS2_INFO(tx_collision_frames),
1700 XGBE_STATS2_INFO(tx_single_coll_frames),
1701 XGBE_STATS2_INFO(tx_mult_coll_frames),
1702 XGBE_STATS2_INFO(tx_excessive_collisions),
1703 XGBE_STATS2_INFO(tx_late_collisions),
1704 XGBE_STATS2_INFO(tx_underrun),
1705 XGBE_STATS2_INFO(tx_carrier_sense_errors),
1706 XGBE_STATS2_INFO(tx_bytes),
1707 XGBE_STATS2_INFO(tx_64byte_frames),
1708 XGBE_STATS2_INFO(tx_65_to_127byte_frames),
1709 XGBE_STATS2_INFO(tx_128_to_255byte_frames),
1710 XGBE_STATS2_INFO(tx_256_to_511byte_frames),
1711 XGBE_STATS2_INFO(tx_512_to_1023byte_frames),
1712 XGBE_STATS2_INFO(tx_1024byte_frames),
1713 XGBE_STATS2_INFO(net_bytes),
1714 XGBE_STATS2_INFO(rx_sof_overruns),
1715 XGBE_STATS2_INFO(rx_mof_overruns),
1716 XGBE_STATS2_INFO(rx_dma_overruns),
1717 };
1718
1719 #define for_each_intf(i, priv) \
1720 list_for_each_entry((i), &(priv)->gbe_intf_head, gbe_intf_list)
1721
1722 #define for_each_sec_slave(slave, priv) \
1723 list_for_each_entry((slave), &(priv)->secondary_slaves, slave_list)
1724
1725 #define first_sec_slave(priv) \
1726 list_first_entry(&priv->secondary_slaves, \
1727 struct gbe_slave, slave_list)
1728
1729 static void keystone_get_drvinfo(struct net_device *ndev,
1730 struct ethtool_drvinfo *info)
1731 {
1732 strncpy(info->driver, NETCP_DRIVER_NAME, sizeof(info->driver));
1733 strncpy(info->version, NETCP_DRIVER_VERSION, sizeof(info->version));
1734 }
1735
1736 static u32 keystone_get_msglevel(struct net_device *ndev)
1737 {
1738 struct netcp_intf *netcp = netdev_priv(ndev);
1739
1740 return netcp->msg_enable;
1741 }
1742
1743 static void keystone_set_msglevel(struct net_device *ndev, u32 value)
1744 {
1745 struct netcp_intf *netcp = netdev_priv(ndev);
1746
1747 netcp->msg_enable = value;
1748 }
1749
1750 static struct gbe_intf *keystone_get_intf_data(struct netcp_intf *netcp)
1751 {
1752 struct gbe_intf *gbe_intf;
1753
1754 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
1755 if (!gbe_intf)
1756 gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp);
1757
1758 return gbe_intf;
1759 }
1760
1761 static void keystone_get_stat_strings(struct net_device *ndev,
1762 uint32_t stringset, uint8_t *data)
1763 {
1764 struct netcp_intf *netcp = netdev_priv(ndev);
1765 struct gbe_intf *gbe_intf;
1766 struct gbe_priv *gbe_dev;
1767 int i;
1768
1769 gbe_intf = keystone_get_intf_data(netcp);
1770 if (!gbe_intf)
1771 return;
1772 gbe_dev = gbe_intf->gbe_dev;
1773
1774 switch (stringset) {
1775 case ETH_SS_STATS:
1776 for (i = 0; i < gbe_dev->num_et_stats; i++) {
1777 memcpy(data, gbe_dev->et_stats[i].desc,
1778 ETH_GSTRING_LEN);
1779 data += ETH_GSTRING_LEN;
1780 }
1781 break;
1782 case ETH_SS_TEST:
1783 break;
1784 }
1785 }
1786
1787 static int keystone_get_sset_count(struct net_device *ndev, int stringset)
1788 {
1789 struct netcp_intf *netcp = netdev_priv(ndev);
1790 struct gbe_intf *gbe_intf;
1791 struct gbe_priv *gbe_dev;
1792
1793 gbe_intf = keystone_get_intf_data(netcp);
1794 if (!gbe_intf)
1795 return -EINVAL;
1796 gbe_dev = gbe_intf->gbe_dev;
1797
1798 switch (stringset) {
1799 case ETH_SS_TEST:
1800 return 0;
1801 case ETH_SS_STATS:
1802 return gbe_dev->num_et_stats;
1803 default:
1804 return -EINVAL;
1805 }
1806 }
1807
1808 static void gbe_reset_mod_stats(struct gbe_priv *gbe_dev, int stats_mod)
1809 {
1810 void __iomem *base = gbe_dev->hw_stats_regs[stats_mod];
1811 u32 __iomem *p_stats_entry;
1812 int i;
1813
1814 for (i = 0; i < gbe_dev->num_et_stats; i++) {
1815 if (gbe_dev->et_stats[i].type == stats_mod) {
1816 p_stats_entry = base + gbe_dev->et_stats[i].offset;
1817 gbe_dev->hw_stats[i] = 0;
1818 gbe_dev->hw_stats_prev[i] = readl(p_stats_entry);
1819 }
1820 }
1821 }
1822
1823 static inline void gbe_update_hw_stats_entry(struct gbe_priv *gbe_dev,
1824 int et_stats_entry)
1825 {
1826 void __iomem *base = NULL;
1827 u32 __iomem *p_stats_entry;
1828 u32 curr, delta;
1829
1830 /* The hw_stats_regs pointers are already
1831 * properly set to point to the right base:
1832 */
1833 base = gbe_dev->hw_stats_regs[gbe_dev->et_stats[et_stats_entry].type];
1834 p_stats_entry = base + gbe_dev->et_stats[et_stats_entry].offset;
1835 curr = readl(p_stats_entry);
1836 delta = curr - gbe_dev->hw_stats_prev[et_stats_entry];
1837 gbe_dev->hw_stats_prev[et_stats_entry] = curr;
1838 gbe_dev->hw_stats[et_stats_entry] += delta;
1839 }
1840
1841 static void gbe_update_stats(struct gbe_priv *gbe_dev, uint64_t *data)
1842 {
1843 int i;
1844
1845 for (i = 0; i < gbe_dev->num_et_stats; i++) {
1846 gbe_update_hw_stats_entry(gbe_dev, i);
1847
1848 if (data)
1849 data[i] = gbe_dev->hw_stats[i];
1850 }
1851 }
1852
1853 static inline void gbe_stats_mod_visible_ver14(struct gbe_priv *gbe_dev,
1854 int stats_mod)
1855 {
1856 u32 val;
1857
1858 val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
1859
1860 switch (stats_mod) {
1861 case GBE_STATSA_MODULE:
1862 case GBE_STATSB_MODULE:
1863 val &= ~GBE_STATS_CD_SEL;
1864 break;
1865 case GBE_STATSC_MODULE:
1866 case GBE_STATSD_MODULE:
1867 val |= GBE_STATS_CD_SEL;
1868 break;
1869 default:
1870 return;
1871 }
1872
1873 /* make the stat module visible */
1874 writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
1875 }
1876
1877 static void gbe_reset_mod_stats_ver14(struct gbe_priv *gbe_dev, int stats_mod)
1878 {
1879 gbe_stats_mod_visible_ver14(gbe_dev, stats_mod);
1880 gbe_reset_mod_stats(gbe_dev, stats_mod);
1881 }
1882
1883 static void gbe_update_stats_ver14(struct gbe_priv *gbe_dev, uint64_t *data)
1884 {
1885 u32 half_num_et_stats = (gbe_dev->num_et_stats / 2);
1886 int et_entry, j, pair;
1887
1888 for (pair = 0; pair < 2; pair++) {
1889 gbe_stats_mod_visible_ver14(gbe_dev, (pair ?
1890 GBE_STATSC_MODULE :
1891 GBE_STATSA_MODULE));
1892
1893 for (j = 0; j < half_num_et_stats; j++) {
1894 et_entry = pair * half_num_et_stats + j;
1895 gbe_update_hw_stats_entry(gbe_dev, et_entry);
1896
1897 if (data)
1898 data[et_entry] = gbe_dev->hw_stats[et_entry];
1899 }
1900 }
1901 }
1902
1903 static void keystone_get_ethtool_stats(struct net_device *ndev,
1904 struct ethtool_stats *stats,
1905 uint64_t *data)
1906 {
1907 struct netcp_intf *netcp = netdev_priv(ndev);
1908 struct gbe_intf *gbe_intf;
1909 struct gbe_priv *gbe_dev;
1910
1911 gbe_intf = keystone_get_intf_data(netcp);
1912 if (!gbe_intf)
1913 return;
1914
1915 gbe_dev = gbe_intf->gbe_dev;
1916 spin_lock_bh(&gbe_dev->hw_stats_lock);
1917 if (gbe_dev->ss_version == GBE_SS_VERSION_14)
1918 gbe_update_stats_ver14(gbe_dev, data);
1919 else
1920 gbe_update_stats(gbe_dev, data);
1921 spin_unlock_bh(&gbe_dev->hw_stats_lock);
1922 }
1923
1924 static int keystone_get_link_ksettings(struct net_device *ndev,
1925 struct ethtool_link_ksettings *cmd)
1926 {
1927 struct netcp_intf *netcp = netdev_priv(ndev);
1928 struct phy_device *phy = ndev->phydev;
1929 struct gbe_intf *gbe_intf;
1930
1931 if (!phy)
1932 return -EINVAL;
1933
1934 gbe_intf = keystone_get_intf_data(netcp);
1935 if (!gbe_intf)
1936 return -EINVAL;
1937
1938 if (!gbe_intf->slave)
1939 return -EINVAL;
1940
1941 phy_ethtool_ksettings_get(phy, cmd);
1942 cmd->base.port = gbe_intf->slave->phy_port_t;
1943
1944 return 0;
1945 }
1946
1947 static int keystone_set_link_ksettings(struct net_device *ndev,
1948 const struct ethtool_link_ksettings *cmd)
1949 {
1950 struct netcp_intf *netcp = netdev_priv(ndev);
1951 struct phy_device *phy = ndev->phydev;
1952 struct gbe_intf *gbe_intf;
1953 u8 port = cmd->base.port;
1954 u32 advertising, supported;
1955 u32 features;
1956
1957 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1958 cmd->link_modes.advertising);
1959 ethtool_convert_link_mode_to_legacy_u32(&supported,
1960 cmd->link_modes.supported);
1961 features = advertising & supported;
1962
1963 if (!phy)
1964 return -EINVAL;
1965
1966 gbe_intf = keystone_get_intf_data(netcp);
1967 if (!gbe_intf)
1968 return -EINVAL;
1969
1970 if (!gbe_intf->slave)
1971 return -EINVAL;
1972
1973 if (port != gbe_intf->slave->phy_port_t) {
1974 if ((port == PORT_TP) && !(features & ADVERTISED_TP))
1975 return -EINVAL;
1976
1977 if ((port == PORT_AUI) && !(features & ADVERTISED_AUI))
1978 return -EINVAL;
1979
1980 if ((port == PORT_BNC) && !(features & ADVERTISED_BNC))
1981 return -EINVAL;
1982
1983 if ((port == PORT_MII) && !(features & ADVERTISED_MII))
1984 return -EINVAL;
1985
1986 if ((port == PORT_FIBRE) && !(features & ADVERTISED_FIBRE))
1987 return -EINVAL;
1988 }
1989
1990 gbe_intf->slave->phy_port_t = port;
1991 return phy_ethtool_ksettings_set(phy, cmd);
1992 }
1993
1994 #if IS_ENABLED(CONFIG_TI_CPTS)
1995 static int keystone_get_ts_info(struct net_device *ndev,
1996 struct ethtool_ts_info *info)
1997 {
1998 struct netcp_intf *netcp = netdev_priv(ndev);
1999 struct gbe_intf *gbe_intf;
2000
2001 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
2002 if (!gbe_intf || !gbe_intf->gbe_dev->cpts)
2003 return -EINVAL;
2004
2005 info->so_timestamping =
2006 SOF_TIMESTAMPING_TX_HARDWARE |
2007 SOF_TIMESTAMPING_TX_SOFTWARE |
2008 SOF_TIMESTAMPING_RX_HARDWARE |
2009 SOF_TIMESTAMPING_RX_SOFTWARE |
2010 SOF_TIMESTAMPING_SOFTWARE |
2011 SOF_TIMESTAMPING_RAW_HARDWARE;
2012 info->phc_index = gbe_intf->gbe_dev->cpts->phc_index;
2013 info->tx_types =
2014 (1 << HWTSTAMP_TX_OFF) |
2015 (1 << HWTSTAMP_TX_ON);
2016 info->rx_filters =
2017 (1 << HWTSTAMP_FILTER_NONE) |
2018 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2019 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2020 return 0;
2021 }
2022 #else
2023 static int keystone_get_ts_info(struct net_device *ndev,
2024 struct ethtool_ts_info *info)
2025 {
2026 info->so_timestamping =
2027 SOF_TIMESTAMPING_TX_SOFTWARE |
2028 SOF_TIMESTAMPING_RX_SOFTWARE |
2029 SOF_TIMESTAMPING_SOFTWARE;
2030 info->phc_index = -1;
2031 info->tx_types = 0;
2032 info->rx_filters = 0;
2033 return 0;
2034 }
2035 #endif /* CONFIG_TI_CPTS */
2036
2037 static const struct ethtool_ops keystone_ethtool_ops = {
2038 .get_drvinfo = keystone_get_drvinfo,
2039 .get_link = ethtool_op_get_link,
2040 .get_msglevel = keystone_get_msglevel,
2041 .set_msglevel = keystone_set_msglevel,
2042 .get_strings = keystone_get_stat_strings,
2043 .get_sset_count = keystone_get_sset_count,
2044 .get_ethtool_stats = keystone_get_ethtool_stats,
2045 .get_link_ksettings = keystone_get_link_ksettings,
2046 .set_link_ksettings = keystone_set_link_ksettings,
2047 .get_ts_info = keystone_get_ts_info,
2048 };
2049
2050 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
2051 ((mac)[2] << 16) | ((mac)[3] << 24))
2052 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
2053
2054 static void gbe_set_slave_mac(struct gbe_slave *slave,
2055 struct gbe_intf *gbe_intf)
2056 {
2057 struct net_device *ndev = gbe_intf->ndev;
2058
2059 writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi));
2060 writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo));
2061 }
2062
2063 static int gbe_get_slave_port(struct gbe_priv *priv, u32 slave_num)
2064 {
2065 if (priv->host_port == 0)
2066 return slave_num + 1;
2067
2068 return slave_num;
2069 }
2070
2071 static void netcp_ethss_link_state_action(struct gbe_priv *gbe_dev,
2072 struct net_device *ndev,
2073 struct gbe_slave *slave,
2074 int up)
2075 {
2076 struct phy_device *phy = slave->phy;
2077 u32 mac_control = 0;
2078
2079 if (up) {
2080 mac_control = slave->mac_control;
2081 if (phy && (phy->speed == SPEED_1000)) {
2082 mac_control |= MACSL_GIG_MODE;
2083 mac_control &= ~MACSL_XGIG_MODE;
2084 } else if (phy && (phy->speed == SPEED_10000)) {
2085 mac_control |= MACSL_XGIG_MODE;
2086 mac_control &= ~MACSL_GIG_MODE;
2087 }
2088
2089 writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
2090 mac_control));
2091
2092 cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
2093 ALE_PORT_STATE,
2094 ALE_PORT_STATE_FORWARD);
2095
2096 if (ndev && slave->open &&
2097 slave->link_interface != SGMII_LINK_MAC_PHY &&
2098 slave->link_interface != XGMII_LINK_MAC_PHY)
2099 netif_carrier_on(ndev);
2100 } else {
2101 writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
2102 mac_control));
2103 cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
2104 ALE_PORT_STATE,
2105 ALE_PORT_STATE_DISABLE);
2106 if (ndev &&
2107 slave->link_interface != SGMII_LINK_MAC_PHY &&
2108 slave->link_interface != XGMII_LINK_MAC_PHY)
2109 netif_carrier_off(ndev);
2110 }
2111
2112 if (phy)
2113 phy_print_status(phy);
2114 }
2115
2116 static bool gbe_phy_link_status(struct gbe_slave *slave)
2117 {
2118 return !slave->phy || slave->phy->link;
2119 }
2120
2121 static void netcp_ethss_update_link_state(struct gbe_priv *gbe_dev,
2122 struct gbe_slave *slave,
2123 struct net_device *ndev)
2124 {
2125 int sp = slave->slave_num;
2126 int phy_link_state, sgmii_link_state = 1, link_state;
2127
2128 if (!slave->open)
2129 return;
2130
2131 if (!SLAVE_LINK_IS_XGMII(slave)) {
2132 sgmii_link_state =
2133 netcp_sgmii_get_port_link(SGMII_BASE(gbe_dev, sp), sp);
2134 }
2135
2136 phy_link_state = gbe_phy_link_status(slave);
2137 link_state = phy_link_state & sgmii_link_state;
2138
2139 if (atomic_xchg(&slave->link_state, link_state) != link_state)
2140 netcp_ethss_link_state_action(gbe_dev, ndev, slave,
2141 link_state);
2142 }
2143
2144 static void xgbe_adjust_link(struct net_device *ndev)
2145 {
2146 struct netcp_intf *netcp = netdev_priv(ndev);
2147 struct gbe_intf *gbe_intf;
2148
2149 gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp);
2150 if (!gbe_intf)
2151 return;
2152
2153 netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave,
2154 ndev);
2155 }
2156
2157 static void gbe_adjust_link(struct net_device *ndev)
2158 {
2159 struct netcp_intf *netcp = netdev_priv(ndev);
2160 struct gbe_intf *gbe_intf;
2161
2162 gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
2163 if (!gbe_intf)
2164 return;
2165
2166 netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave,
2167 ndev);
2168 }
2169
2170 static void gbe_adjust_link_sec_slaves(struct net_device *ndev)
2171 {
2172 struct gbe_priv *gbe_dev = netdev_priv(ndev);
2173 struct gbe_slave *slave;
2174
2175 for_each_sec_slave(slave, gbe_dev)
2176 netcp_ethss_update_link_state(gbe_dev, slave, NULL);
2177 }
2178
2179 /* Reset EMAC
2180 * Soft reset is set and polled until clear, or until a timeout occurs
2181 */
2182 static int gbe_port_reset(struct gbe_slave *slave)
2183 {
2184 u32 i, v;
2185
2186 /* Set the soft reset bit */
2187 writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset));
2188
2189 /* Wait for the bit to clear */
2190 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
2191 v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset));
2192 if ((v & SOFT_RESET_MASK) != SOFT_RESET)
2193 return 0;
2194 }
2195
2196 /* Timeout on the reset */
2197 return GMACSL_RET_WARN_RESET_INCOMPLETE;
2198 }
2199
2200 /* Configure EMAC */
2201 static void gbe_port_config(struct gbe_priv *gbe_dev, struct gbe_slave *slave,
2202 int max_rx_len)
2203 {
2204 void __iomem *rx_maxlen_reg;
2205 u32 xgmii_mode;
2206
2207 if (max_rx_len > NETCP_MAX_FRAME_SIZE)
2208 max_rx_len = NETCP_MAX_FRAME_SIZE;
2209
2210 /* Enable correct MII mode at SS level */
2211 if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) &&
2212 (slave->link_interface >= XGMII_LINK_MAC_PHY)) {
2213 xgmii_mode = readl(GBE_REG_ADDR(gbe_dev, ss_regs, control));
2214 xgmii_mode |= (1 << slave->slave_num);
2215 writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control));
2216 }
2217
2218 if (IS_SS_ID_MU(gbe_dev))
2219 rx_maxlen_reg = GBE_REG_ADDR(slave, port_regs, rx_maxlen);
2220 else
2221 rx_maxlen_reg = GBE_REG_ADDR(slave, emac_regs, rx_maxlen);
2222
2223 writel(max_rx_len, rx_maxlen_reg);
2224 writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));
2225 }
2226
2227 static void gbe_sgmii_rtreset(struct gbe_priv *priv,
2228 struct gbe_slave *slave, bool set)
2229 {
2230 if (SLAVE_LINK_IS_XGMII(slave))
2231 return;
2232
2233 netcp_sgmii_rtreset(SGMII_BASE(priv, slave->slave_num),
2234 slave->slave_num, set);
2235 }
2236
2237 static void gbe_slave_stop(struct gbe_intf *intf)
2238 {
2239 struct gbe_priv *gbe_dev = intf->gbe_dev;
2240 struct gbe_slave *slave = intf->slave;
2241
2242 gbe_sgmii_rtreset(gbe_dev, slave, true);
2243 gbe_port_reset(slave);
2244 /* Disable forwarding */
2245 cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
2246 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
2247 cpsw_ale_del_mcast(gbe_dev->ale, intf->ndev->broadcast,
2248 1 << slave->port_num, 0, 0);
2249
2250 if (!slave->phy)
2251 return;
2252
2253 phy_stop(slave->phy);
2254 phy_disconnect(slave->phy);
2255 slave->phy = NULL;
2256 }
2257
2258 static void gbe_sgmii_config(struct gbe_priv *priv, struct gbe_slave *slave)
2259 {
2260 if (SLAVE_LINK_IS_XGMII(slave))
2261 return;
2262
2263 netcp_sgmii_reset(SGMII_BASE(priv, slave->slave_num), slave->slave_num);
2264 netcp_sgmii_config(SGMII_BASE(priv, slave->slave_num), slave->slave_num,
2265 slave->link_interface);
2266 }
2267
2268 static int gbe_slave_open(struct gbe_intf *gbe_intf)
2269 {
2270 struct gbe_priv *priv = gbe_intf->gbe_dev;
2271 struct gbe_slave *slave = gbe_intf->slave;
2272 phy_interface_t phy_mode;
2273 bool has_phy = false;
2274
2275 void (*hndlr)(struct net_device *) = gbe_adjust_link;
2276
2277 gbe_sgmii_config(priv, slave);
2278 gbe_port_reset(slave);
2279 gbe_sgmii_rtreset(priv, slave, false);
2280 gbe_port_config(priv, slave, priv->rx_packet_max);
2281 gbe_set_slave_mac(slave, gbe_intf);
2282 /* enable forwarding */
2283 cpsw_ale_control_set(priv->ale, slave->port_num,
2284 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2285 cpsw_ale_add_mcast(priv->ale, gbe_intf->ndev->broadcast,
2286 1 << slave->port_num, 0, 0, ALE_MCAST_FWD_2);
2287
2288 if (slave->link_interface == SGMII_LINK_MAC_PHY) {
2289 has_phy = true;
2290 phy_mode = PHY_INTERFACE_MODE_SGMII;
2291 slave->phy_port_t = PORT_MII;
2292 } else if (slave->link_interface == XGMII_LINK_MAC_PHY) {
2293 has_phy = true;
2294 phy_mode = PHY_INTERFACE_MODE_NA;
2295 slave->phy_port_t = PORT_FIBRE;
2296 }
2297
2298 if (has_phy) {
2299 if (priv->ss_version == XGBE_SS_VERSION_10)
2300 hndlr = xgbe_adjust_link;
2301
2302 slave->phy = of_phy_connect(gbe_intf->ndev,
2303 slave->phy_node,
2304 hndlr, 0,
2305 phy_mode);
2306 if (!slave->phy) {
2307 dev_err(priv->dev, "phy not found on slave %d\n",
2308 slave->slave_num);
2309 return -ENODEV;
2310 }
2311 dev_dbg(priv->dev, "phy found: id is: 0x%s\n",
2312 phydev_name(slave->phy));
2313 phy_start(slave->phy);
2314 }
2315 return 0;
2316 }
2317
2318 static void gbe_init_host_port(struct gbe_priv *priv)
2319 {
2320 int bypass_en = 1;
2321
2322 /* Host Tx Pri */
2323 if (IS_SS_ID_NU(priv) || IS_SS_ID_XGBE(priv))
2324 writel(HOST_TX_PRI_MAP_DEFAULT,
2325 GBE_REG_ADDR(priv, host_port_regs, tx_pri_map));
2326
2327 /* Max length register */
2328 writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs,
2329 rx_maxlen));
2330
2331 cpsw_ale_start(priv->ale);
2332
2333 if (priv->enable_ale)
2334 bypass_en = 0;
2335
2336 cpsw_ale_control_set(priv->ale, 0, ALE_BYPASS, bypass_en);
2337
2338 cpsw_ale_control_set(priv->ale, 0, ALE_NO_PORT_VLAN, 1);
2339
2340 cpsw_ale_control_set(priv->ale, priv->host_port,
2341 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2342
2343 cpsw_ale_control_set(priv->ale, 0,
2344 ALE_PORT_UNKNOWN_VLAN_MEMBER,
2345 GBE_PORT_MASK(priv->ale_ports));
2346
2347 cpsw_ale_control_set(priv->ale, 0,
2348 ALE_PORT_UNKNOWN_MCAST_FLOOD,
2349 GBE_PORT_MASK(priv->ale_ports - 1));
2350
2351 cpsw_ale_control_set(priv->ale, 0,
2352 ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
2353 GBE_PORT_MASK(priv->ale_ports));
2354
2355 cpsw_ale_control_set(priv->ale, 0,
2356 ALE_PORT_UNTAGGED_EGRESS,
2357 GBE_PORT_MASK(priv->ale_ports));
2358 }
2359
2360 static void gbe_add_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2361 {
2362 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2363 u16 vlan_id;
2364
2365 cpsw_ale_add_mcast(gbe_dev->ale, addr,
2366 GBE_PORT_MASK(gbe_dev->ale_ports), 0, 0,
2367 ALE_MCAST_FWD_2);
2368 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
2369 cpsw_ale_add_mcast(gbe_dev->ale, addr,
2370 GBE_PORT_MASK(gbe_dev->ale_ports),
2371 ALE_VLAN, vlan_id, ALE_MCAST_FWD_2);
2372 }
2373 }
2374
2375 static void gbe_add_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2376 {
2377 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2378 u16 vlan_id;
2379
2380 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0);
2381
2382 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID)
2383 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port,
2384 ALE_VLAN, vlan_id);
2385 }
2386
2387 static void gbe_del_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2388 {
2389 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2390 u16 vlan_id;
2391
2392 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, 0, 0);
2393
2394 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
2395 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, ALE_VLAN, vlan_id);
2396 }
2397 }
2398
2399 static void gbe_del_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2400 {
2401 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2402 u16 vlan_id;
2403
2404 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0);
2405
2406 for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
2407 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port,
2408 ALE_VLAN, vlan_id);
2409 }
2410 }
2411
2412 static int gbe_add_addr(void *intf_priv, struct netcp_addr *naddr)
2413 {
2414 struct gbe_intf *gbe_intf = intf_priv;
2415 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2416
2417 dev_dbg(gbe_dev->dev, "ethss adding address %pM, type %d\n",
2418 naddr->addr, naddr->type);
2419
2420 switch (naddr->type) {
2421 case ADDR_MCAST:
2422 case ADDR_BCAST:
2423 gbe_add_mcast_addr(gbe_intf, naddr->addr);
2424 break;
2425 case ADDR_UCAST:
2426 case ADDR_DEV:
2427 gbe_add_ucast_addr(gbe_intf, naddr->addr);
2428 break;
2429 case ADDR_ANY:
2430 /* nothing to do for promiscuous */
2431 default:
2432 break;
2433 }
2434
2435 return 0;
2436 }
2437
2438 static int gbe_del_addr(void *intf_priv, struct netcp_addr *naddr)
2439 {
2440 struct gbe_intf *gbe_intf = intf_priv;
2441 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2442
2443 dev_dbg(gbe_dev->dev, "ethss deleting address %pM, type %d\n",
2444 naddr->addr, naddr->type);
2445
2446 switch (naddr->type) {
2447 case ADDR_MCAST:
2448 case ADDR_BCAST:
2449 gbe_del_mcast_addr(gbe_intf, naddr->addr);
2450 break;
2451 case ADDR_UCAST:
2452 case ADDR_DEV:
2453 gbe_del_ucast_addr(gbe_intf, naddr->addr);
2454 break;
2455 case ADDR_ANY:
2456 /* nothing to do for promiscuous */
2457 default:
2458 break;
2459 }
2460
2461 return 0;
2462 }
2463
2464 static int gbe_add_vid(void *intf_priv, int vid)
2465 {
2466 struct gbe_intf *gbe_intf = intf_priv;
2467 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2468
2469 set_bit(vid, gbe_intf->active_vlans);
2470
2471 cpsw_ale_add_vlan(gbe_dev->ale, vid,
2472 GBE_PORT_MASK(gbe_dev->ale_ports),
2473 GBE_MASK_NO_PORTS,
2474 GBE_PORT_MASK(gbe_dev->ale_ports),
2475 GBE_PORT_MASK(gbe_dev->ale_ports - 1));
2476
2477 return 0;
2478 }
2479
2480 static int gbe_del_vid(void *intf_priv, int vid)
2481 {
2482 struct gbe_intf *gbe_intf = intf_priv;
2483 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2484
2485 cpsw_ale_del_vlan(gbe_dev->ale, vid, 0);
2486 clear_bit(vid, gbe_intf->active_vlans);
2487 return 0;
2488 }
2489
2490 #if IS_ENABLED(CONFIG_TI_CPTS)
2491 #define HAS_PHY_TXTSTAMP(p) ((p)->drv && (p)->drv->txtstamp)
2492 #define HAS_PHY_RXTSTAMP(p) ((p)->drv && (p)->drv->rxtstamp)
2493
2494 static void gbe_txtstamp(void *context, struct sk_buff *skb)
2495 {
2496 struct gbe_intf *gbe_intf = context;
2497 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2498
2499 cpts_tx_timestamp(gbe_dev->cpts, skb);
2500 }
2501
2502 static bool gbe_need_txtstamp(struct gbe_intf *gbe_intf,
2503 const struct netcp_packet *p_info)
2504 {
2505 struct sk_buff *skb = p_info->skb;
2506
2507 return cpts_can_timestamp(gbe_intf->gbe_dev->cpts, skb);
2508 }
2509
2510 static int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf,
2511 struct netcp_packet *p_info)
2512 {
2513 struct phy_device *phydev = p_info->skb->dev->phydev;
2514 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2515
2516 if (!(skb_shinfo(p_info->skb)->tx_flags & SKBTX_HW_TSTAMP) ||
2517 !cpts_is_tx_enabled(gbe_dev->cpts))
2518 return 0;
2519
2520 /* If phy has the txtstamp api, assume it will do it.
2521 * We mark it here because skb_tx_timestamp() is called
2522 * after all the txhooks are called.
2523 */
2524 if (phydev && HAS_PHY_TXTSTAMP(phydev)) {
2525 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
2526 return 0;
2527 }
2528
2529 if (gbe_need_txtstamp(gbe_intf, p_info)) {
2530 p_info->txtstamp = gbe_txtstamp;
2531 p_info->ts_context = (void *)gbe_intf;
2532 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
2533 }
2534
2535 return 0;
2536 }
2537
2538 static int gbe_rxtstamp(struct gbe_intf *gbe_intf, struct netcp_packet *p_info)
2539 {
2540 struct phy_device *phydev = p_info->skb->dev->phydev;
2541 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2542
2543 if (p_info->rxtstamp_complete)
2544 return 0;
2545
2546 if (phydev && HAS_PHY_RXTSTAMP(phydev)) {
2547 p_info->rxtstamp_complete = true;
2548 return 0;
2549 }
2550
2551 cpts_rx_timestamp(gbe_dev->cpts, p_info->skb);
2552 p_info->rxtstamp_complete = true;
2553
2554 return 0;
2555 }
2556
2557 static int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *ifr)
2558 {
2559 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2560 struct cpts *cpts = gbe_dev->cpts;
2561 struct hwtstamp_config cfg;
2562
2563 if (!cpts)
2564 return -EOPNOTSUPP;
2565
2566 cfg.flags = 0;
2567 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
2568 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2569 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
2570 cpts->rx_enable : HWTSTAMP_FILTER_NONE);
2571
2572 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2573 }
2574
2575 static void gbe_hwtstamp(struct gbe_intf *gbe_intf)
2576 {
2577 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2578 struct gbe_slave *slave = gbe_intf->slave;
2579 u32 ts_en, seq_id, ctl;
2580
2581 if (!cpts_is_rx_enabled(gbe_dev->cpts) &&
2582 !cpts_is_tx_enabled(gbe_dev->cpts)) {
2583 writel(0, GBE_REG_ADDR(slave, port_regs, ts_ctl));
2584 return;
2585 }
2586
2587 seq_id = (30 << TS_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2588 ts_en = EVENT_MSG_BITS << TS_MSG_TYPE_EN_SHIFT;
2589 ctl = ETH_P_1588 | TS_TTL_NONZERO |
2590 (slave->ts_ctl.dst_port_map << TS_CTL_DST_PORT_SHIFT) |
2591 (slave->ts_ctl.uni ? TS_UNI_EN :
2592 slave->ts_ctl.maddr_map << TS_CTL_MADDR_SHIFT);
2593
2594 if (cpts_is_tx_enabled(gbe_dev->cpts))
2595 ts_en |= (TS_TX_ANX_ALL_EN | TS_TX_VLAN_LT1_EN);
2596
2597 if (cpts_is_rx_enabled(gbe_dev->cpts))
2598 ts_en |= (TS_RX_ANX_ALL_EN | TS_RX_VLAN_LT1_EN);
2599
2600 writel(ts_en, GBE_REG_ADDR(slave, port_regs, ts_ctl));
2601 writel(seq_id, GBE_REG_ADDR(slave, port_regs, ts_seq_ltype));
2602 writel(ctl, GBE_REG_ADDR(slave, port_regs, ts_ctl_ltype2));
2603 }
2604
2605 static int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *ifr)
2606 {
2607 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2608 struct cpts *cpts = gbe_dev->cpts;
2609 struct hwtstamp_config cfg;
2610
2611 if (!cpts)
2612 return -EOPNOTSUPP;
2613
2614 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2615 return -EFAULT;
2616
2617 /* reserved for future extensions */
2618 if (cfg.flags)
2619 return -EINVAL;
2620
2621 switch (cfg.tx_type) {
2622 case HWTSTAMP_TX_OFF:
2623 cpts_tx_enable(cpts, 0);
2624 break;
2625 case HWTSTAMP_TX_ON:
2626 cpts_tx_enable(cpts, 1);
2627 break;
2628 default:
2629 return -ERANGE;
2630 }
2631
2632 switch (cfg.rx_filter) {
2633 case HWTSTAMP_FILTER_NONE:
2634 cpts_rx_enable(cpts, 0);
2635 break;
2636 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2637 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2638 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2639 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
2640 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2641 break;
2642 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2643 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2644 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2645 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2646 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2647 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2648 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2649 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2650 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2651 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2652 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2653 break;
2654 default:
2655 return -ERANGE;
2656 }
2657
2658 gbe_hwtstamp(gbe_intf);
2659
2660 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2661 }
2662
2663 static void gbe_register_cpts(struct gbe_priv *gbe_dev)
2664 {
2665 if (!gbe_dev->cpts)
2666 return;
2667
2668 if (gbe_dev->cpts_registered > 0)
2669 goto done;
2670
2671 if (cpts_register(gbe_dev->cpts)) {
2672 dev_err(gbe_dev->dev, "error registering cpts device\n");
2673 return;
2674 }
2675
2676 done:
2677 ++gbe_dev->cpts_registered;
2678 }
2679
2680 static void gbe_unregister_cpts(struct gbe_priv *gbe_dev)
2681 {
2682 if (!gbe_dev->cpts || (gbe_dev->cpts_registered <= 0))
2683 return;
2684
2685 if (--gbe_dev->cpts_registered)
2686 return;
2687
2688 cpts_unregister(gbe_dev->cpts);
2689 }
2690 #else
2691 static inline int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf,
2692 struct netcp_packet *p_info)
2693 {
2694 return 0;
2695 }
2696
2697 static inline int gbe_rxtstamp(struct gbe_intf *gbe_intf,
2698 struct netcp_packet *p_info)
2699 {
2700 return 0;
2701 }
2702
2703 static inline int gbe_hwtstamp(struct gbe_intf *gbe_intf,
2704 struct ifreq *ifr, int cmd)
2705 {
2706 return -EOPNOTSUPP;
2707 }
2708
2709 static inline void gbe_register_cpts(struct gbe_priv *gbe_dev)
2710 {
2711 }
2712
2713 static inline void gbe_unregister_cpts(struct gbe_priv *gbe_dev)
2714 {
2715 }
2716
2717 static inline int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *req)
2718 {
2719 return -EOPNOTSUPP;
2720 }
2721
2722 static inline int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *req)
2723 {
2724 return -EOPNOTSUPP;
2725 }
2726 #endif /* CONFIG_TI_CPTS */
2727
2728 static int gbe_ioctl(void *intf_priv, struct ifreq *req, int cmd)
2729 {
2730 struct gbe_intf *gbe_intf = intf_priv;
2731 struct phy_device *phy = gbe_intf->slave->phy;
2732
2733 if (!phy || !phy->drv->hwtstamp) {
2734 switch (cmd) {
2735 case SIOCGHWTSTAMP:
2736 return gbe_hwtstamp_get(gbe_intf, req);
2737 case SIOCSHWTSTAMP:
2738 return gbe_hwtstamp_set(gbe_intf, req);
2739 }
2740 }
2741
2742 if (phy)
2743 return phy_mii_ioctl(phy, req, cmd);
2744
2745 return -EOPNOTSUPP;
2746 }
2747
2748 static void netcp_ethss_timer(struct timer_list *t)
2749 {
2750 struct gbe_priv *gbe_dev = from_timer(gbe_dev, t, timer);
2751 struct gbe_intf *gbe_intf;
2752 struct gbe_slave *slave;
2753
2754 /* Check & update SGMII link state of interfaces */
2755 for_each_intf(gbe_intf, gbe_dev) {
2756 if (!gbe_intf->slave->open)
2757 continue;
2758 netcp_ethss_update_link_state(gbe_dev, gbe_intf->slave,
2759 gbe_intf->ndev);
2760 }
2761
2762 /* Check & update SGMII link state of secondary ports */
2763 for_each_sec_slave(slave, gbe_dev) {
2764 netcp_ethss_update_link_state(gbe_dev, slave, NULL);
2765 }
2766
2767 /* A timer runs as a BH, no need to block them */
2768 spin_lock(&gbe_dev->hw_stats_lock);
2769
2770 if (gbe_dev->ss_version == GBE_SS_VERSION_14)
2771 gbe_update_stats_ver14(gbe_dev, NULL);
2772 else
2773 gbe_update_stats(gbe_dev, NULL);
2774
2775 spin_unlock(&gbe_dev->hw_stats_lock);
2776
2777 gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL;
2778 add_timer(&gbe_dev->timer);
2779 }
2780
2781 static int gbe_txhook(int order, void *data, struct netcp_packet *p_info)
2782 {
2783 struct gbe_intf *gbe_intf = data;
2784
2785 p_info->tx_pipe = &gbe_intf->tx_pipe;
2786
2787 return gbe_txtstamp_mark_pkt(gbe_intf, p_info);
2788 }
2789
2790 static int gbe_rxhook(int order, void *data, struct netcp_packet *p_info)
2791 {
2792 struct gbe_intf *gbe_intf = data;
2793
2794 return gbe_rxtstamp(gbe_intf, p_info);
2795 }
2796
2797 static int gbe_open(void *intf_priv, struct net_device *ndev)
2798 {
2799 struct gbe_intf *gbe_intf = intf_priv;
2800 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2801 struct netcp_intf *netcp = netdev_priv(ndev);
2802 struct gbe_slave *slave = gbe_intf->slave;
2803 int port_num = slave->port_num;
2804 u32 reg, val;
2805 int ret;
2806
2807 reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver));
2808 dev_dbg(gbe_dev->dev, "initializing gbe version %d.%d (%d) GBE identification value 0x%x\n",
2809 GBE_MAJOR_VERSION(reg), GBE_MINOR_VERSION(reg),
2810 GBE_RTL_VERSION(reg), GBE_IDENT(reg));
2811
2812 /* For 10G and on NetCP 1.5, use directed to port */
2813 if ((gbe_dev->ss_version == XGBE_SS_VERSION_10) || IS_SS_ID_MU(gbe_dev))
2814 gbe_intf->tx_pipe.flags = SWITCH_TO_PORT_IN_TAGINFO;
2815
2816 if (gbe_dev->enable_ale)
2817 gbe_intf->tx_pipe.switch_to_port = 0;
2818 else
2819 gbe_intf->tx_pipe.switch_to_port = port_num;
2820
2821 dev_dbg(gbe_dev->dev,
2822 "opened TX channel %s: %p with to port %d, flags %d\n",
2823 gbe_intf->tx_pipe.dma_chan_name,
2824 gbe_intf->tx_pipe.dma_channel,
2825 gbe_intf->tx_pipe.switch_to_port,
2826 gbe_intf->tx_pipe.flags);
2827
2828 gbe_slave_stop(gbe_intf);
2829
2830 /* disable priority elevation and enable statistics on all ports */
2831 writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));
2832
2833 /* Control register */
2834 val = GBE_CTL_P0_ENABLE;
2835 if (IS_SS_ID_MU(gbe_dev)) {
2836 val |= ETH_SW_CTL_P0_TX_CRC_REMOVE;
2837 netcp->hw_cap = ETH_SW_CAN_REMOVE_ETH_FCS;
2838 }
2839 writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, control));
2840
2841 /* All statistics enabled and STAT AB visible by default */
2842 writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,
2843 stat_port_en));
2844
2845 ret = gbe_slave_open(gbe_intf);
2846 if (ret)
2847 goto fail;
2848
2849 netcp_register_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf);
2850 netcp_register_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf);
2851
2852 slave->open = true;
2853 netcp_ethss_update_link_state(gbe_dev, slave, ndev);
2854
2855 gbe_register_cpts(gbe_dev);
2856
2857 return 0;
2858
2859 fail:
2860 gbe_slave_stop(gbe_intf);
2861 return ret;
2862 }
2863
2864 static int gbe_close(void *intf_priv, struct net_device *ndev)
2865 {
2866 struct gbe_intf *gbe_intf = intf_priv;
2867 struct netcp_intf *netcp = netdev_priv(ndev);
2868 struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2869
2870 gbe_unregister_cpts(gbe_dev);
2871
2872 gbe_slave_stop(gbe_intf);
2873
2874 netcp_unregister_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf);
2875 netcp_unregister_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf);
2876
2877 gbe_intf->slave->open = false;
2878 atomic_set(&gbe_intf->slave->link_state, NETCP_LINK_STATE_INVALID);
2879 return 0;
2880 }
2881
2882 #if IS_ENABLED(CONFIG_TI_CPTS)
2883 static void init_slave_ts_ctl(struct gbe_slave *slave)
2884 {
2885 slave->ts_ctl.uni = 1;
2886 slave->ts_ctl.dst_port_map =
2887 (TS_CTL_DST_PORT >> TS_CTL_DST_PORT_SHIFT) & 0x3;
2888 slave->ts_ctl.maddr_map =
2889 (TS_CTL_MADDR_ALL >> TS_CTL_MADDR_SHIFT) & 0x1f;
2890 }
2891
2892 #else
2893 static void init_slave_ts_ctl(struct gbe_slave *slave)
2894 {
2895 }
2896 #endif /* CONFIG_TI_CPTS */
2897
2898 static int init_slave(struct gbe_priv *gbe_dev, struct gbe_slave *slave,
2899 struct device_node *node)
2900 {
2901 int port_reg_num;
2902 u32 port_reg_ofs, emac_reg_ofs;
2903 u32 port_reg_blk_sz, emac_reg_blk_sz;
2904
2905 if (of_property_read_u32(node, "slave-port", &slave->slave_num)) {
2906 dev_err(gbe_dev->dev, "missing slave-port parameter\n");
2907 return -EINVAL;
2908 }
2909
2910 if (of_property_read_u32(node, "link-interface",
2911 &slave->link_interface)) {
2912 dev_warn(gbe_dev->dev,
2913 "missing link-interface value defaulting to 1G mac-phy link\n");
2914 slave->link_interface = SGMII_LINK_MAC_PHY;
2915 }
2916
2917 slave->open = false;
2918 if ((slave->link_interface == SGMII_LINK_MAC_PHY) ||
2919 (slave->link_interface == XGMII_LINK_MAC_PHY))
2920 slave->phy_node = of_parse_phandle(node, "phy-handle", 0);
2921 slave->port_num = gbe_get_slave_port(gbe_dev, slave->slave_num);
2922
2923 if (slave->link_interface >= XGMII_LINK_MAC_PHY)
2924 slave->mac_control = GBE_DEF_10G_MAC_CONTROL;
2925 else
2926 slave->mac_control = GBE_DEF_1G_MAC_CONTROL;
2927
2928 /* Emac regs memmap are contiguous but port regs are not */
2929 port_reg_num = slave->slave_num;
2930 if (gbe_dev->ss_version == GBE_SS_VERSION_14) {
2931 if (slave->slave_num > 1) {
2932 port_reg_ofs = GBE13_SLAVE_PORT2_OFFSET;
2933 port_reg_num -= 2;
2934 } else {
2935 port_reg_ofs = GBE13_SLAVE_PORT_OFFSET;
2936 }
2937 emac_reg_ofs = GBE13_EMAC_OFFSET;
2938 port_reg_blk_sz = 0x30;
2939 emac_reg_blk_sz = 0x40;
2940 } else if (IS_SS_ID_MU(gbe_dev)) {
2941 port_reg_ofs = GBENU_SLAVE_PORT_OFFSET;
2942 emac_reg_ofs = GBENU_EMAC_OFFSET;
2943 port_reg_blk_sz = 0x1000;
2944 emac_reg_blk_sz = 0x1000;
2945 } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) {
2946 port_reg_ofs = XGBE10_SLAVE_PORT_OFFSET;
2947 emac_reg_ofs = XGBE10_EMAC_OFFSET;
2948 port_reg_blk_sz = 0x30;
2949 emac_reg_blk_sz = 0x40;
2950 } else {
2951 dev_err(gbe_dev->dev, "unknown ethss(0x%x)\n",
2952 gbe_dev->ss_version);
2953 return -EINVAL;
2954 }
2955
2956 slave->port_regs = gbe_dev->switch_regs + port_reg_ofs +
2957 (port_reg_blk_sz * port_reg_num);
2958 slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs +
2959 (emac_reg_blk_sz * slave->slave_num);
2960
2961 if (gbe_dev->ss_version == GBE_SS_VERSION_14) {
2962 /* Initialize slave port register offsets */
2963 GBE_SET_REG_OFS(slave, port_regs, port_vlan);
2964 GBE_SET_REG_OFS(slave, port_regs, tx_pri_map);
2965 GBE_SET_REG_OFS(slave, port_regs, sa_lo);
2966 GBE_SET_REG_OFS(slave, port_regs, sa_hi);
2967 GBE_SET_REG_OFS(slave, port_regs, ts_ctl);
2968 GBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
2969 GBE_SET_REG_OFS(slave, port_regs, ts_vlan);
2970 GBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
2971 GBE_SET_REG_OFS(slave, port_regs, ts_ctl2);
2972
2973 /* Initialize EMAC register offsets */
2974 GBE_SET_REG_OFS(slave, emac_regs, mac_control);
2975 GBE_SET_REG_OFS(slave, emac_regs, soft_reset);
2976 GBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);
2977
2978 } else if (IS_SS_ID_MU(gbe_dev)) {
2979 /* Initialize slave port register offsets */
2980 GBENU_SET_REG_OFS(slave, port_regs, port_vlan);
2981 GBENU_SET_REG_OFS(slave, port_regs, tx_pri_map);
2982 GBENU_SET_REG_OFS(slave, port_regs, sa_lo);
2983 GBENU_SET_REG_OFS(slave, port_regs, sa_hi);
2984 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl);
2985 GBENU_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
2986 GBENU_SET_REG_OFS(slave, port_regs, ts_vlan);
2987 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
2988 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl2);
2989 GBENU_SET_REG_OFS(slave, port_regs, rx_maxlen);
2990
2991 /* Initialize EMAC register offsets */
2992 GBENU_SET_REG_OFS(slave, emac_regs, mac_control);
2993 GBENU_SET_REG_OFS(slave, emac_regs, soft_reset);
2994
2995 } else if (gbe_dev->ss_version == XGBE_SS_VERSION_10) {
2996 /* Initialize slave port register offsets */
2997 XGBE_SET_REG_OFS(slave, port_regs, port_vlan);
2998 XGBE_SET_REG_OFS(slave, port_regs, tx_pri_map);
2999 XGBE_SET_REG_OFS(slave, port_regs, sa_lo);
3000 XGBE_SET_REG_OFS(slave, port_regs, sa_hi);
3001 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl);
3002 XGBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
3003 XGBE_SET_REG_OFS(slave, port_regs, ts_vlan);
3004 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
3005 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl2);
3006
3007 /* Initialize EMAC register offsets */
3008 XGBE_SET_REG_OFS(slave, emac_regs, mac_control);
3009 XGBE_SET_REG_OFS(slave, emac_regs, soft_reset);
3010 XGBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);
3011 }
3012
3013 atomic_set(&slave->link_state, NETCP_LINK_STATE_INVALID);
3014
3015 init_slave_ts_ctl(slave);
3016 return 0;
3017 }
3018
3019 static void init_secondary_ports(struct gbe_priv *gbe_dev,
3020 struct device_node *node)
3021 {
3022 struct device *dev = gbe_dev->dev;
3023 phy_interface_t phy_mode;
3024 struct gbe_priv **priv;
3025 struct device_node *port;
3026 struct gbe_slave *slave;
3027 bool mac_phy_link = false;
3028
3029 for_each_child_of_node(node, port) {
3030 slave = devm_kzalloc(dev, sizeof(*slave), GFP_KERNEL);
3031 if (!slave) {
3032 dev_err(dev, "memory alloc failed for secondary port(%s), skipping...\n",
3033 port->name);
3034 continue;
3035 }
3036
3037 if (init_slave(gbe_dev, slave, port)) {
3038 dev_err(dev,
3039 "Failed to initialize secondary port(%s), skipping...\n",
3040 port->name);
3041 devm_kfree(dev, slave);
3042 continue;
3043 }
3044
3045 gbe_sgmii_config(gbe_dev, slave);
3046 gbe_port_reset(slave);
3047 gbe_port_config(gbe_dev, slave, gbe_dev->rx_packet_max);
3048 list_add_tail(&slave->slave_list, &gbe_dev->secondary_slaves);
3049 gbe_dev->num_slaves++;
3050 if ((slave->link_interface == SGMII_LINK_MAC_PHY) ||
3051 (slave->link_interface == XGMII_LINK_MAC_PHY))
3052 mac_phy_link = true;
3053
3054 slave->open = true;
3055 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) {
3056 of_node_put(port);
3057 break;
3058 }
3059 }
3060
3061 /* of_phy_connect() is needed only for MAC-PHY interface */
3062 if (!mac_phy_link)
3063 return;
3064
3065 /* Allocate dummy netdev device for attaching to phy device */
3066 gbe_dev->dummy_ndev = alloc_netdev(sizeof(gbe_dev), "dummy",
3067 NET_NAME_UNKNOWN, ether_setup);
3068 if (!gbe_dev->dummy_ndev) {
3069 dev_err(dev,
3070 "Failed to allocate dummy netdev for secondary ports, skipping phy_connect()...\n");
3071 return;
3072 }
3073 priv = netdev_priv(gbe_dev->dummy_ndev);
3074 *priv = gbe_dev;
3075
3076 if (slave->link_interface == SGMII_LINK_MAC_PHY) {
3077 phy_mode = PHY_INTERFACE_MODE_SGMII;
3078 slave->phy_port_t = PORT_MII;
3079 } else {
3080 phy_mode = PHY_INTERFACE_MODE_NA;
3081 slave->phy_port_t = PORT_FIBRE;
3082 }
3083
3084 for_each_sec_slave(slave, gbe_dev) {
3085 if ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
3086 (slave->link_interface != XGMII_LINK_MAC_PHY))
3087 continue;
3088 slave->phy =
3089 of_phy_connect(gbe_dev->dummy_ndev,
3090 slave->phy_node,
3091 gbe_adjust_link_sec_slaves,
3092 0, phy_mode);
3093 if (!slave->phy) {
3094 dev_err(dev, "phy not found for slave %d\n",
3095 slave->slave_num);
3096 slave->phy = NULL;
3097 } else {
3098 dev_dbg(dev, "phy found: id is: 0x%s\n",
3099 phydev_name(slave->phy));
3100 phy_start(slave->phy);
3101 }
3102 }
3103 }
3104
3105 static void free_secondary_ports(struct gbe_priv *gbe_dev)
3106 {
3107 struct gbe_slave *slave;
3108
3109 while (!list_empty(&gbe_dev->secondary_slaves)) {
3110 slave = first_sec_slave(gbe_dev);
3111
3112 if (slave->phy)
3113 phy_disconnect(slave->phy);
3114 list_del(&slave->slave_list);
3115 }
3116 if (gbe_dev->dummy_ndev)
3117 free_netdev(gbe_dev->dummy_ndev);
3118 }
3119
3120 static int set_xgbe_ethss10_priv(struct gbe_priv *gbe_dev,
3121 struct device_node *node)
3122 {
3123 struct resource res;
3124 void __iomem *regs;
3125 int ret, i;
3126
3127 ret = of_address_to_resource(node, XGBE_SS_REG_INDEX, &res);
3128 if (ret) {
3129 dev_err(gbe_dev->dev,
3130 "Can't xlate xgbe of node(%s) ss address at %d\n",
3131 node->name, XGBE_SS_REG_INDEX);
3132 return ret;
3133 }
3134
3135 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3136 if (IS_ERR(regs)) {
3137 dev_err(gbe_dev->dev, "Failed to map xgbe ss register base\n");
3138 return PTR_ERR(regs);
3139 }
3140 gbe_dev->ss_regs = regs;
3141
3142 ret = of_address_to_resource(node, XGBE_SM_REG_INDEX, &res);
3143 if (ret) {
3144 dev_err(gbe_dev->dev,
3145 "Can't xlate xgbe of node(%s) sm address at %d\n",
3146 node->name, XGBE_SM_REG_INDEX);
3147 return ret;
3148 }
3149
3150 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3151 if (IS_ERR(regs)) {
3152 dev_err(gbe_dev->dev, "Failed to map xgbe sm register base\n");
3153 return PTR_ERR(regs);
3154 }
3155 gbe_dev->switch_regs = regs;
3156
3157 ret = of_address_to_resource(node, XGBE_SERDES_REG_INDEX, &res);
3158 if (ret) {
3159 dev_err(gbe_dev->dev,
3160 "Can't xlate xgbe serdes of node(%s) address at %d\n",
3161 node->name, XGBE_SERDES_REG_INDEX);
3162 return ret;
3163 }
3164
3165 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3166 if (IS_ERR(regs)) {
3167 dev_err(gbe_dev->dev, "Failed to map xgbe serdes register base\n");
3168 return PTR_ERR(regs);
3169 }
3170 gbe_dev->xgbe_serdes_regs = regs;
3171
3172 gbe_dev->num_stats_mods = gbe_dev->max_num_ports;
3173 gbe_dev->et_stats = xgbe10_et_stats;
3174 gbe_dev->num_et_stats = ARRAY_SIZE(xgbe10_et_stats);
3175
3176 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
3177 gbe_dev->num_et_stats * sizeof(u64),
3178 GFP_KERNEL);
3179 if (!gbe_dev->hw_stats) {
3180 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
3181 return -ENOMEM;
3182 }
3183
3184 gbe_dev->hw_stats_prev =
3185 devm_kzalloc(gbe_dev->dev,
3186 gbe_dev->num_et_stats * sizeof(u32),
3187 GFP_KERNEL);
3188 if (!gbe_dev->hw_stats_prev) {
3189 dev_err(gbe_dev->dev,
3190 "hw_stats_prev memory allocation failed\n");
3191 return -ENOMEM;
3192 }
3193
3194 gbe_dev->ss_version = XGBE_SS_VERSION_10;
3195 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs +
3196 XGBE10_SGMII_MODULE_OFFSET;
3197 gbe_dev->host_port_regs = gbe_dev->ss_regs + XGBE10_HOST_PORT_OFFSET;
3198
3199 for (i = 0; i < gbe_dev->max_num_ports; i++)
3200 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +
3201 XGBE10_HW_STATS_OFFSET + (GBE_HW_STATS_REG_MAP_SZ * i);
3202
3203 gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET;
3204 gbe_dev->cpts_reg = gbe_dev->switch_regs + XGBE10_CPTS_OFFSET;
3205 gbe_dev->ale_ports = gbe_dev->max_num_ports;
3206 gbe_dev->host_port = XGBE10_HOST_PORT_NUM;
3207 gbe_dev->ale_entries = XGBE10_NUM_ALE_ENTRIES;
3208 gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1;
3209
3210 /* Subsystem registers */
3211 XGBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
3212 XGBE_SET_REG_OFS(gbe_dev, ss_regs, control);
3213
3214 /* Switch module registers */
3215 XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
3216 XGBE_SET_REG_OFS(gbe_dev, switch_regs, control);
3217 XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);
3218 XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
3219 XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);
3220
3221 /* Host port registers */
3222 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
3223 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);
3224 XGBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
3225 return 0;
3226 }
3227
3228 static int get_gbe_resource_version(struct gbe_priv *gbe_dev,
3229 struct device_node *node)
3230 {
3231 struct resource res;
3232 void __iomem *regs;
3233 int ret;
3234
3235 ret = of_address_to_resource(node, GBE_SS_REG_INDEX, &res);
3236 if (ret) {
3237 dev_err(gbe_dev->dev,
3238 "Can't translate of node(%s) of gbe ss address at %d\n",
3239 node->name, GBE_SS_REG_INDEX);
3240 return ret;
3241 }
3242
3243 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3244 if (IS_ERR(regs)) {
3245 dev_err(gbe_dev->dev, "Failed to map gbe register base\n");
3246 return PTR_ERR(regs);
3247 }
3248 gbe_dev->ss_regs = regs;
3249 gbe_dev->ss_version = readl(gbe_dev->ss_regs);
3250 return 0;
3251 }
3252
3253 static int set_gbe_ethss14_priv(struct gbe_priv *gbe_dev,
3254 struct device_node *node)
3255 {
3256 struct resource res;
3257 void __iomem *regs;
3258 int i, ret;
3259
3260 ret = of_address_to_resource(node, GBE_SGMII34_REG_INDEX, &res);
3261 if (ret) {
3262 dev_err(gbe_dev->dev,
3263 "Can't translate of gbe node(%s) address at index %d\n",
3264 node->name, GBE_SGMII34_REG_INDEX);
3265 return ret;
3266 }
3267
3268 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3269 if (IS_ERR(regs)) {
3270 dev_err(gbe_dev->dev,
3271 "Failed to map gbe sgmii port34 register base\n");
3272 return PTR_ERR(regs);
3273 }
3274 gbe_dev->sgmii_port34_regs = regs;
3275
3276 ret = of_address_to_resource(node, GBE_SM_REG_INDEX, &res);
3277 if (ret) {
3278 dev_err(gbe_dev->dev,
3279 "Can't translate of gbe node(%s) address at index %d\n",
3280 node->name, GBE_SM_REG_INDEX);
3281 return ret;
3282 }
3283
3284 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3285 if (IS_ERR(regs)) {
3286 dev_err(gbe_dev->dev,
3287 "Failed to map gbe switch module register base\n");
3288 return PTR_ERR(regs);
3289 }
3290 gbe_dev->switch_regs = regs;
3291
3292 gbe_dev->num_stats_mods = gbe_dev->max_num_slaves;
3293 gbe_dev->et_stats = gbe13_et_stats;
3294 gbe_dev->num_et_stats = ARRAY_SIZE(gbe13_et_stats);
3295
3296 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
3297 gbe_dev->num_et_stats * sizeof(u64),
3298 GFP_KERNEL);
3299 if (!gbe_dev->hw_stats) {
3300 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
3301 return -ENOMEM;
3302 }
3303
3304 gbe_dev->hw_stats_prev =
3305 devm_kzalloc(gbe_dev->dev,
3306 gbe_dev->num_et_stats * sizeof(u32),
3307 GFP_KERNEL);
3308 if (!gbe_dev->hw_stats_prev) {
3309 dev_err(gbe_dev->dev,
3310 "hw_stats_prev memory allocation failed\n");
3311 return -ENOMEM;
3312 }
3313
3314 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBE13_SGMII_MODULE_OFFSET;
3315 gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET;
3316
3317 /* K2HK has only 2 hw stats modules visible at a time, so
3318 * module 0 & 2 points to one base and
3319 * module 1 & 3 points to the other base
3320 */
3321 for (i = 0; i < gbe_dev->max_num_slaves; i++) {
3322 gbe_dev->hw_stats_regs[i] =
3323 gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET +
3324 (GBE_HW_STATS_REG_MAP_SZ * (i & 0x1));
3325 }
3326
3327 gbe_dev->cpts_reg = gbe_dev->switch_regs + GBE13_CPTS_OFFSET;
3328 gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET;
3329 gbe_dev->ale_ports = gbe_dev->max_num_ports;
3330 gbe_dev->host_port = GBE13_HOST_PORT_NUM;
3331 gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES;
3332 gbe_dev->stats_en_mask = GBE13_REG_VAL_STAT_ENABLE_ALL;
3333
3334 /* Subsystem registers */
3335 GBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
3336
3337 /* Switch module registers */
3338 GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
3339 GBE_SET_REG_OFS(gbe_dev, switch_regs, control);
3340 GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset);
3341 GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
3342 GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);
3343 GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);
3344
3345 /* Host port registers */
3346 GBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
3347 GBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
3348 return 0;
3349 }
3350
3351 static int set_gbenu_ethss_priv(struct gbe_priv *gbe_dev,
3352 struct device_node *node)
3353 {
3354 struct resource res;
3355 void __iomem *regs;
3356 int i, ret;
3357
3358 gbe_dev->num_stats_mods = gbe_dev->max_num_ports;
3359 gbe_dev->et_stats = gbenu_et_stats;
3360
3361 if (IS_SS_ID_NU(gbe_dev))
3362 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE +
3363 (gbe_dev->max_num_slaves * GBENU_ET_STATS_PORT_SIZE);
3364 else
3365 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE +
3366 GBENU_ET_STATS_PORT_SIZE;
3367
3368 gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
3369 gbe_dev->num_et_stats * sizeof(u64),
3370 GFP_KERNEL);
3371 if (!gbe_dev->hw_stats) {
3372 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
3373 return -ENOMEM;
3374 }
3375
3376 gbe_dev->hw_stats_prev =
3377 devm_kzalloc(gbe_dev->dev,
3378 gbe_dev->num_et_stats * sizeof(u32),
3379 GFP_KERNEL);
3380 if (!gbe_dev->hw_stats_prev) {
3381 dev_err(gbe_dev->dev,
3382 "hw_stats_prev memory allocation failed\n");
3383 return -ENOMEM;
3384 }
3385
3386 ret = of_address_to_resource(node, GBENU_SM_REG_INDEX, &res);
3387 if (ret) {
3388 dev_err(gbe_dev->dev,
3389 "Can't translate of gbenu node(%s) addr at index %d\n",
3390 node->name, GBENU_SM_REG_INDEX);
3391 return ret;
3392 }
3393
3394 regs = devm_ioremap_resource(gbe_dev->dev, &res);
3395 if (IS_ERR(regs)) {
3396 dev_err(gbe_dev->dev,
3397 "Failed to map gbenu switch module register base\n");
3398 return PTR_ERR(regs);
3399 }
3400 gbe_dev->switch_regs = regs;
3401
3402 gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBENU_SGMII_MODULE_OFFSET;
3403
3404 /* Although sgmii modules are mem mapped to one contiguous
3405 * region on GBENU devices, setting sgmii_port34_regs allows
3406 * consistent code when accessing sgmii api
3407 */
3408 gbe_dev->sgmii_port34_regs = gbe_dev->sgmii_port_regs +
3409 (2 * GBENU_SGMII_MODULE_SIZE);
3410
3411 gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET;
3412
3413 for (i = 0; i < (gbe_dev->max_num_ports); i++)
3414 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +
3415 GBENU_HW_STATS_OFFSET + (GBENU_HW_STATS_REG_MAP_SZ * i);
3416
3417 gbe_dev->cpts_reg = gbe_dev->switch_regs + GBENU_CPTS_OFFSET;
3418 gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET;
3419 gbe_dev->ale_ports = gbe_dev->max_num_ports;
3420 gbe_dev->host_port = GBENU_HOST_PORT_NUM;
3421 gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1;
3422
3423 /* Subsystem registers */
3424 GBENU_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
3425
3426 /* Switch module registers */
3427 GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
3428 GBENU_SET_REG_OFS(gbe_dev, switch_regs, control);
3429 GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
3430 GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype);
3431
3432 /* Host port registers */
3433 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
3434 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
3435
3436 /* For NU only. 2U does not need tx_pri_map.
3437 * NU cppi port 0 tx pkt streaming interface has (n-1)*8 egress threads
3438 * while 2U has only 1 such thread
3439 */
3440 GBENU_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);
3441 return 0;
3442 }
3443
3444 static int gbe_probe(struct netcp_device *netcp_device, struct device *dev,
3445 struct device_node *node, void **inst_priv)
3446 {
3447 struct device_node *interfaces, *interface;
3448 struct device_node *secondary_ports;
3449 struct cpsw_ale_params ale_params;
3450 struct gbe_priv *gbe_dev;
3451 u32 slave_num;
3452 int i, ret = 0;
3453
3454 if (!node) {
3455 dev_err(dev, "device tree info unavailable\n");
3456 return -ENODEV;
3457 }
3458
3459 gbe_dev = devm_kzalloc(dev, sizeof(struct gbe_priv), GFP_KERNEL);
3460 if (!gbe_dev)
3461 return -ENOMEM;
3462
3463 if (of_device_is_compatible(node, "ti,netcp-gbe-5") ||
3464 of_device_is_compatible(node, "ti,netcp-gbe")) {
3465 gbe_dev->max_num_slaves = 4;
3466 } else if (of_device_is_compatible(node, "ti,netcp-gbe-9")) {
3467 gbe_dev->max_num_slaves = 8;
3468 } else if (of_device_is_compatible(node, "ti,netcp-gbe-2")) {
3469 gbe_dev->max_num_slaves = 1;
3470 } else if (of_device_is_compatible(node, "ti,netcp-xgbe")) {
3471 gbe_dev->max_num_slaves = 2;
3472 } else {
3473 dev_err(dev, "device tree node for unknown device\n");
3474 return -EINVAL;
3475 }
3476 gbe_dev->max_num_ports = gbe_dev->max_num_slaves + 1;
3477
3478 gbe_dev->dev = dev;
3479 gbe_dev->netcp_device = netcp_device;
3480 gbe_dev->rx_packet_max = NETCP_MAX_FRAME_SIZE;
3481
3482 /* init the hw stats lock */
3483 spin_lock_init(&gbe_dev->hw_stats_lock);
3484
3485 if (of_find_property(node, "enable-ale", NULL)) {
3486 gbe_dev->enable_ale = true;
3487 dev_info(dev, "ALE enabled\n");
3488 } else {
3489 gbe_dev->enable_ale = false;
3490 dev_dbg(dev, "ALE bypass enabled*\n");
3491 }
3492
3493 ret = of_property_read_u32(node, "tx-queue",
3494 &gbe_dev->tx_queue_id);
3495 if (ret < 0) {
3496 dev_err(dev, "missing tx_queue parameter\n");
3497 gbe_dev->tx_queue_id = GBE_TX_QUEUE;
3498 }
3499
3500 ret = of_property_read_string(node, "tx-channel",
3501 &gbe_dev->dma_chan_name);
3502 if (ret < 0) {
3503 dev_err(dev, "missing \"tx-channel\" parameter\n");
3504 return -EINVAL;
3505 }
3506
3507 if (!strcmp(node->name, "gbe")) {
3508 ret = get_gbe_resource_version(gbe_dev, node);
3509 if (ret)
3510 return ret;
3511
3512 dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version);
3513
3514 if (gbe_dev->ss_version == GBE_SS_VERSION_14)
3515 ret = set_gbe_ethss14_priv(gbe_dev, node);
3516 else if (IS_SS_ID_MU(gbe_dev))
3517 ret = set_gbenu_ethss_priv(gbe_dev, node);
3518 else
3519 ret = -ENODEV;
3520
3521 } else if (!strcmp(node->name, "xgbe")) {
3522 ret = set_xgbe_ethss10_priv(gbe_dev, node);
3523 if (ret)
3524 return ret;
3525 ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs,
3526 gbe_dev->ss_regs);
3527 } else {
3528 dev_err(dev, "unknown GBE node(%s)\n", node->name);
3529 ret = -ENODEV;
3530 }
3531
3532 if (ret)
3533 return ret;
3534
3535 interfaces = of_get_child_by_name(node, "interfaces");
3536 if (!interfaces)
3537 dev_err(dev, "could not find interfaces\n");
3538
3539 ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device,
3540 gbe_dev->dma_chan_name, gbe_dev->tx_queue_id);
3541 if (ret)
3542 return ret;
3543
3544 ret = netcp_txpipe_open(&gbe_dev->tx_pipe);
3545 if (ret)
3546 return ret;
3547
3548 /* Create network interfaces */
3549 INIT_LIST_HEAD(&gbe_dev->gbe_intf_head);
3550 for_each_child_of_node(interfaces, interface) {
3551 ret = of_property_read_u32(interface, "slave-port", &slave_num);
3552 if (ret) {
3553 dev_err(dev, "missing slave-port parameter, skipping interface configuration for %s\n",
3554 interface->name);
3555 continue;
3556 }
3557 gbe_dev->num_slaves++;
3558 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) {
3559 of_node_put(interface);
3560 break;
3561 }
3562 }
3563 of_node_put(interfaces);
3564
3565 if (!gbe_dev->num_slaves)
3566 dev_warn(dev, "No network interface configured\n");
3567
3568 /* Initialize Secondary slave ports */
3569 secondary_ports = of_get_child_by_name(node, "secondary-slave-ports");
3570 INIT_LIST_HEAD(&gbe_dev->secondary_slaves);
3571 if (secondary_ports && (gbe_dev->num_slaves < gbe_dev->max_num_slaves))
3572 init_secondary_ports(gbe_dev, secondary_ports);
3573 of_node_put(secondary_ports);
3574
3575 if (!gbe_dev->num_slaves) {
3576 dev_err(dev,
3577 "No network interface or secondary ports configured\n");
3578 ret = -ENODEV;
3579 goto free_sec_ports;
3580 }
3581
3582 memset(&ale_params, 0, sizeof(ale_params));
3583 ale_params.dev = gbe_dev->dev;
3584 ale_params.ale_regs = gbe_dev->ale_reg;
3585 ale_params.ale_ageout = GBE_DEFAULT_ALE_AGEOUT;
3586 ale_params.ale_entries = gbe_dev->ale_entries;
3587 ale_params.ale_ports = gbe_dev->ale_ports;
3588 if (IS_SS_ID_MU(gbe_dev)) {
3589 ale_params.major_ver_mask = 0x7;
3590 ale_params.nu_switch_ale = true;
3591 }
3592 gbe_dev->ale = cpsw_ale_create(&ale_params);
3593 if (!gbe_dev->ale) {
3594 dev_err(gbe_dev->dev, "error initializing ale engine\n");
3595 ret = -ENODEV;
3596 goto free_sec_ports;
3597 } else {
3598 dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n");
3599 }
3600
3601 gbe_dev->cpts = cpts_create(gbe_dev->dev, gbe_dev->cpts_reg, node);
3602 if (IS_ENABLED(CONFIG_TI_CPTS) && IS_ERR(gbe_dev->cpts)) {
3603 ret = PTR_ERR(gbe_dev->cpts);
3604 goto free_sec_ports;
3605 }
3606
3607 /* initialize host port */
3608 gbe_init_host_port(gbe_dev);
3609
3610 spin_lock_bh(&gbe_dev->hw_stats_lock);
3611 for (i = 0; i < gbe_dev->num_stats_mods; i++) {
3612 if (gbe_dev->ss_version == GBE_SS_VERSION_14)
3613 gbe_reset_mod_stats_ver14(gbe_dev, i);
3614 else
3615 gbe_reset_mod_stats(gbe_dev, i);
3616 }
3617 spin_unlock_bh(&gbe_dev->hw_stats_lock);
3618
3619 timer_setup(&gbe_dev->timer, netcp_ethss_timer, 0);
3620 gbe_dev->timer.expires = jiffies + GBE_TIMER_INTERVAL;
3621 add_timer(&gbe_dev->timer);
3622 *inst_priv = gbe_dev;
3623 return 0;
3624
3625 free_sec_ports:
3626 free_secondary_ports(gbe_dev);
3627 return ret;
3628 }
3629
3630 static int gbe_attach(void *inst_priv, struct net_device *ndev,
3631 struct device_node *node, void **intf_priv)
3632 {
3633 struct gbe_priv *gbe_dev = inst_priv;
3634 struct gbe_intf *gbe_intf;
3635 int ret;
3636
3637 if (!node) {
3638 dev_err(gbe_dev->dev, "interface node not available\n");
3639 return -ENODEV;
3640 }
3641
3642 gbe_intf = devm_kzalloc(gbe_dev->dev, sizeof(*gbe_intf), GFP_KERNEL);
3643 if (!gbe_intf)
3644 return -ENOMEM;
3645
3646 gbe_intf->ndev = ndev;
3647 gbe_intf->dev = gbe_dev->dev;
3648 gbe_intf->gbe_dev = gbe_dev;
3649
3650 gbe_intf->slave = devm_kzalloc(gbe_dev->dev,
3651 sizeof(*gbe_intf->slave),
3652 GFP_KERNEL);
3653 if (!gbe_intf->slave) {
3654 ret = -ENOMEM;
3655 goto fail;
3656 }
3657
3658 if (init_slave(gbe_dev, gbe_intf->slave, node)) {
3659 ret = -ENODEV;
3660 goto fail;
3661 }
3662
3663 gbe_intf->tx_pipe = gbe_dev->tx_pipe;
3664 ndev->ethtool_ops = &keystone_ethtool_ops;
3665 list_add_tail(&gbe_intf->gbe_intf_list, &gbe_dev->gbe_intf_head);
3666 *intf_priv = gbe_intf;
3667 return 0;
3668
3669 fail:
3670 if (gbe_intf->slave)
3671 devm_kfree(gbe_dev->dev, gbe_intf->slave);
3672 if (gbe_intf)
3673 devm_kfree(gbe_dev->dev, gbe_intf);
3674 return ret;
3675 }
3676
3677 static int gbe_release(void *intf_priv)
3678 {
3679 struct gbe_intf *gbe_intf = intf_priv;
3680
3681 gbe_intf->ndev->ethtool_ops = NULL;
3682 list_del(&gbe_intf->gbe_intf_list);
3683 devm_kfree(gbe_intf->dev, gbe_intf->slave);
3684 devm_kfree(gbe_intf->dev, gbe_intf);
3685 return 0;
3686 }
3687
3688 static int gbe_remove(struct netcp_device *netcp_device, void *inst_priv)
3689 {
3690 struct gbe_priv *gbe_dev = inst_priv;
3691
3692 del_timer_sync(&gbe_dev->timer);
3693 cpts_release(gbe_dev->cpts);
3694 cpsw_ale_stop(gbe_dev->ale);
3695 cpsw_ale_destroy(gbe_dev->ale);
3696 netcp_txpipe_close(&gbe_dev->tx_pipe);
3697 free_secondary_ports(gbe_dev);
3698
3699 if (!list_empty(&gbe_dev->gbe_intf_head))
3700 dev_alert(gbe_dev->dev,
3701 "unreleased ethss interfaces present\n");
3702
3703 return 0;
3704 }
3705
3706 static struct netcp_module gbe_module = {
3707 .name = GBE_MODULE_NAME,
3708 .owner = THIS_MODULE,
3709 .primary = true,
3710 .probe = gbe_probe,
3711 .open = gbe_open,
3712 .close = gbe_close,
3713 .remove = gbe_remove,
3714 .attach = gbe_attach,
3715 .release = gbe_release,
3716 .add_addr = gbe_add_addr,
3717 .del_addr = gbe_del_addr,
3718 .add_vid = gbe_add_vid,
3719 .del_vid = gbe_del_vid,
3720 .ioctl = gbe_ioctl,
3721 };
3722
3723 static struct netcp_module xgbe_module = {
3724 .name = XGBE_MODULE_NAME,
3725 .owner = THIS_MODULE,
3726 .primary = true,
3727 .probe = gbe_probe,
3728 .open = gbe_open,
3729 .close = gbe_close,
3730 .remove = gbe_remove,
3731 .attach = gbe_attach,
3732 .release = gbe_release,
3733 .add_addr = gbe_add_addr,
3734 .del_addr = gbe_del_addr,
3735 .add_vid = gbe_add_vid,
3736 .del_vid = gbe_del_vid,
3737 .ioctl = gbe_ioctl,
3738 };
3739
3740 static int __init keystone_gbe_init(void)
3741 {
3742 int ret;
3743
3744 ret = netcp_register_module(&gbe_module);
3745 if (ret)
3746 return ret;
3747
3748 ret = netcp_register_module(&xgbe_module);
3749 if (ret)
3750 return ret;
3751
3752 return 0;
3753 }
3754 module_init(keystone_gbe_init);
3755
3756 static void __exit keystone_gbe_exit(void)
3757 {
3758 netcp_unregister_module(&gbe_module);
3759 netcp_unregister_module(&xgbe_module);
3760 }
3761 module_exit(keystone_gbe_exit);
3762
3763 MODULE_LICENSE("GPL v2");
3764 MODULE_DESCRIPTION("TI NETCP ETHSS driver for Keystone SOCs");
3765 MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com");
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