2 * This file is provided under a GPLv2 license. When using or
3 * redistributing this file, you may do so under that license.
7 * Copyright (C) 2016 T-Platforms All Rights Reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
16 * Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, one can be found http://www.gnu.org/licenses/.
21 * The full GNU General Public License is included in this distribution in
22 * the file called "COPYING".
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * IDT PCIe-switch NTB Linux driver
38 * Contact Information:
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
42 #include <linux/stddef.h>
43 #include <linux/types.h>
44 #include <linux/kernel.h>
45 #include <linux/bitops.h>
46 #include <linux/sizes.h>
47 #include <linux/module.h>
48 #include <linux/moduleparam.h>
49 #include <linux/init.h>
50 #include <linux/interrupt.h>
51 #include <linux/spinlock.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54 #include <linux/slab.h>
55 #include <linux/list.h>
56 #include <linux/debugfs.h>
57 #include <linux/ntb.h>
59 #include "ntb_hw_idt.h"
61 #define NTB_NAME "ntb_hw_idt"
62 #define NTB_DESC "IDT PCI-E Non-Transparent Bridge Driver"
64 #define NTB_IRQNAME "ntb_irq_idt"
66 MODULE_DESCRIPTION(NTB_DESC
);
67 MODULE_VERSION(NTB_VER
);
68 MODULE_LICENSE("GPL v2");
69 MODULE_AUTHOR("T-platforms");
72 * NT Endpoint registers table simplifying a loop access to the functionally
75 static const struct idt_ntb_regs ntdata_tbl
= {
76 { {IDT_NT_BARSETUP0
, IDT_NT_BARLIMIT0
,
77 IDT_NT_BARLTBASE0
, IDT_NT_BARUTBASE0
},
78 {IDT_NT_BARSETUP1
, IDT_NT_BARLIMIT1
,
79 IDT_NT_BARLTBASE1
, IDT_NT_BARUTBASE1
},
80 {IDT_NT_BARSETUP2
, IDT_NT_BARLIMIT2
,
81 IDT_NT_BARLTBASE2
, IDT_NT_BARUTBASE2
},
82 {IDT_NT_BARSETUP3
, IDT_NT_BARLIMIT3
,
83 IDT_NT_BARLTBASE3
, IDT_NT_BARUTBASE3
},
84 {IDT_NT_BARSETUP4
, IDT_NT_BARLIMIT4
,
85 IDT_NT_BARLTBASE4
, IDT_NT_BARUTBASE4
},
86 {IDT_NT_BARSETUP5
, IDT_NT_BARLIMIT5
,
87 IDT_NT_BARLTBASE5
, IDT_NT_BARUTBASE5
} },
88 { {IDT_NT_INMSG0
, IDT_NT_OUTMSG0
, IDT_NT_INMSGSRC0
},
89 {IDT_NT_INMSG1
, IDT_NT_OUTMSG1
, IDT_NT_INMSGSRC1
},
90 {IDT_NT_INMSG2
, IDT_NT_OUTMSG2
, IDT_NT_INMSGSRC2
},
91 {IDT_NT_INMSG3
, IDT_NT_OUTMSG3
, IDT_NT_INMSGSRC3
} }
95 * NT Endpoint ports data table with the corresponding pcie command, link
96 * status, control and BAR-related registers
98 static const struct idt_ntb_port portdata_tbl
[IDT_MAX_NR_PORTS
] = {
99 /*0*/ { IDT_SW_NTP0_PCIECMDSTS
, IDT_SW_NTP0_PCIELCTLSTS
,
101 IDT_SW_SWPORT0CTL
, IDT_SW_SWPORT0STS
,
102 { {IDT_SW_NTP0_BARSETUP0
, IDT_SW_NTP0_BARLIMIT0
,
103 IDT_SW_NTP0_BARLTBASE0
, IDT_SW_NTP0_BARUTBASE0
},
104 {IDT_SW_NTP0_BARSETUP1
, IDT_SW_NTP0_BARLIMIT1
,
105 IDT_SW_NTP0_BARLTBASE1
, IDT_SW_NTP0_BARUTBASE1
},
106 {IDT_SW_NTP0_BARSETUP2
, IDT_SW_NTP0_BARLIMIT2
,
107 IDT_SW_NTP0_BARLTBASE2
, IDT_SW_NTP0_BARUTBASE2
},
108 {IDT_SW_NTP0_BARSETUP3
, IDT_SW_NTP0_BARLIMIT3
,
109 IDT_SW_NTP0_BARLTBASE3
, IDT_SW_NTP0_BARUTBASE3
},
110 {IDT_SW_NTP0_BARSETUP4
, IDT_SW_NTP0_BARLIMIT4
,
111 IDT_SW_NTP0_BARLTBASE4
, IDT_SW_NTP0_BARUTBASE4
},
112 {IDT_SW_NTP0_BARSETUP5
, IDT_SW_NTP0_BARLIMIT5
,
113 IDT_SW_NTP0_BARLTBASE5
, IDT_SW_NTP0_BARUTBASE5
} } },
115 /*2*/ { IDT_SW_NTP2_PCIECMDSTS
, IDT_SW_NTP2_PCIELCTLSTS
,
117 IDT_SW_SWPORT2CTL
, IDT_SW_SWPORT2STS
,
118 { {IDT_SW_NTP2_BARSETUP0
, IDT_SW_NTP2_BARLIMIT0
,
119 IDT_SW_NTP2_BARLTBASE0
, IDT_SW_NTP2_BARUTBASE0
},
120 {IDT_SW_NTP2_BARSETUP1
, IDT_SW_NTP2_BARLIMIT1
,
121 IDT_SW_NTP2_BARLTBASE1
, IDT_SW_NTP2_BARUTBASE1
},
122 {IDT_SW_NTP2_BARSETUP2
, IDT_SW_NTP2_BARLIMIT2
,
123 IDT_SW_NTP2_BARLTBASE2
, IDT_SW_NTP2_BARUTBASE2
},
124 {IDT_SW_NTP2_BARSETUP3
, IDT_SW_NTP2_BARLIMIT3
,
125 IDT_SW_NTP2_BARLTBASE3
, IDT_SW_NTP2_BARUTBASE3
},
126 {IDT_SW_NTP2_BARSETUP4
, IDT_SW_NTP2_BARLIMIT4
,
127 IDT_SW_NTP2_BARLTBASE4
, IDT_SW_NTP2_BARUTBASE4
},
128 {IDT_SW_NTP2_BARSETUP5
, IDT_SW_NTP2_BARLIMIT5
,
129 IDT_SW_NTP2_BARLTBASE5
, IDT_SW_NTP2_BARUTBASE5
} } },
131 /*4*/ { IDT_SW_NTP4_PCIECMDSTS
, IDT_SW_NTP4_PCIELCTLSTS
,
133 IDT_SW_SWPORT4CTL
, IDT_SW_SWPORT4STS
,
134 { {IDT_SW_NTP4_BARSETUP0
, IDT_SW_NTP4_BARLIMIT0
,
135 IDT_SW_NTP4_BARLTBASE0
, IDT_SW_NTP4_BARUTBASE0
},
136 {IDT_SW_NTP4_BARSETUP1
, IDT_SW_NTP4_BARLIMIT1
,
137 IDT_SW_NTP4_BARLTBASE1
, IDT_SW_NTP4_BARUTBASE1
},
138 {IDT_SW_NTP4_BARSETUP2
, IDT_SW_NTP4_BARLIMIT2
,
139 IDT_SW_NTP4_BARLTBASE2
, IDT_SW_NTP4_BARUTBASE2
},
140 {IDT_SW_NTP4_BARSETUP3
, IDT_SW_NTP4_BARLIMIT3
,
141 IDT_SW_NTP4_BARLTBASE3
, IDT_SW_NTP4_BARUTBASE3
},
142 {IDT_SW_NTP4_BARSETUP4
, IDT_SW_NTP4_BARLIMIT4
,
143 IDT_SW_NTP4_BARLTBASE4
, IDT_SW_NTP4_BARUTBASE4
},
144 {IDT_SW_NTP4_BARSETUP5
, IDT_SW_NTP4_BARLIMIT5
,
145 IDT_SW_NTP4_BARLTBASE5
, IDT_SW_NTP4_BARUTBASE5
} } },
147 /*6*/ { IDT_SW_NTP6_PCIECMDSTS
, IDT_SW_NTP6_PCIELCTLSTS
,
149 IDT_SW_SWPORT6CTL
, IDT_SW_SWPORT6STS
,
150 { {IDT_SW_NTP6_BARSETUP0
, IDT_SW_NTP6_BARLIMIT0
,
151 IDT_SW_NTP6_BARLTBASE0
, IDT_SW_NTP6_BARUTBASE0
},
152 {IDT_SW_NTP6_BARSETUP1
, IDT_SW_NTP6_BARLIMIT1
,
153 IDT_SW_NTP6_BARLTBASE1
, IDT_SW_NTP6_BARUTBASE1
},
154 {IDT_SW_NTP6_BARSETUP2
, IDT_SW_NTP6_BARLIMIT2
,
155 IDT_SW_NTP6_BARLTBASE2
, IDT_SW_NTP6_BARUTBASE2
},
156 {IDT_SW_NTP6_BARSETUP3
, IDT_SW_NTP6_BARLIMIT3
,
157 IDT_SW_NTP6_BARLTBASE3
, IDT_SW_NTP6_BARUTBASE3
},
158 {IDT_SW_NTP6_BARSETUP4
, IDT_SW_NTP6_BARLIMIT4
,
159 IDT_SW_NTP6_BARLTBASE4
, IDT_SW_NTP6_BARUTBASE4
},
160 {IDT_SW_NTP6_BARSETUP5
, IDT_SW_NTP6_BARLIMIT5
,
161 IDT_SW_NTP6_BARLTBASE5
, IDT_SW_NTP6_BARUTBASE5
} } },
163 /*8*/ { IDT_SW_NTP8_PCIECMDSTS
, IDT_SW_NTP8_PCIELCTLSTS
,
165 IDT_SW_SWPORT8CTL
, IDT_SW_SWPORT8STS
,
166 { {IDT_SW_NTP8_BARSETUP0
, IDT_SW_NTP8_BARLIMIT0
,
167 IDT_SW_NTP8_BARLTBASE0
, IDT_SW_NTP8_BARUTBASE0
},
168 {IDT_SW_NTP8_BARSETUP1
, IDT_SW_NTP8_BARLIMIT1
,
169 IDT_SW_NTP8_BARLTBASE1
, IDT_SW_NTP8_BARUTBASE1
},
170 {IDT_SW_NTP8_BARSETUP2
, IDT_SW_NTP8_BARLIMIT2
,
171 IDT_SW_NTP8_BARLTBASE2
, IDT_SW_NTP8_BARUTBASE2
},
172 {IDT_SW_NTP8_BARSETUP3
, IDT_SW_NTP8_BARLIMIT3
,
173 IDT_SW_NTP8_BARLTBASE3
, IDT_SW_NTP8_BARUTBASE3
},
174 {IDT_SW_NTP8_BARSETUP4
, IDT_SW_NTP8_BARLIMIT4
,
175 IDT_SW_NTP8_BARLTBASE4
, IDT_SW_NTP8_BARUTBASE4
},
176 {IDT_SW_NTP8_BARSETUP5
, IDT_SW_NTP8_BARLIMIT5
,
177 IDT_SW_NTP8_BARLTBASE5
, IDT_SW_NTP8_BARUTBASE5
} } },
181 /*12*/ { IDT_SW_NTP12_PCIECMDSTS
, IDT_SW_NTP12_PCIELCTLSTS
,
183 IDT_SW_SWPORT12CTL
, IDT_SW_SWPORT12STS
,
184 { {IDT_SW_NTP12_BARSETUP0
, IDT_SW_NTP12_BARLIMIT0
,
185 IDT_SW_NTP12_BARLTBASE0
, IDT_SW_NTP12_BARUTBASE0
},
186 {IDT_SW_NTP12_BARSETUP1
, IDT_SW_NTP12_BARLIMIT1
,
187 IDT_SW_NTP12_BARLTBASE1
, IDT_SW_NTP12_BARUTBASE1
},
188 {IDT_SW_NTP12_BARSETUP2
, IDT_SW_NTP12_BARLIMIT2
,
189 IDT_SW_NTP12_BARLTBASE2
, IDT_SW_NTP12_BARUTBASE2
},
190 {IDT_SW_NTP12_BARSETUP3
, IDT_SW_NTP12_BARLIMIT3
,
191 IDT_SW_NTP12_BARLTBASE3
, IDT_SW_NTP12_BARUTBASE3
},
192 {IDT_SW_NTP12_BARSETUP4
, IDT_SW_NTP12_BARLIMIT4
,
193 IDT_SW_NTP12_BARLTBASE4
, IDT_SW_NTP12_BARUTBASE4
},
194 {IDT_SW_NTP12_BARSETUP5
, IDT_SW_NTP12_BARLIMIT5
,
195 IDT_SW_NTP12_BARLTBASE5
, IDT_SW_NTP12_BARUTBASE5
} } },
199 /*16*/ { IDT_SW_NTP16_PCIECMDSTS
, IDT_SW_NTP16_PCIELCTLSTS
,
201 IDT_SW_SWPORT16CTL
, IDT_SW_SWPORT16STS
,
202 { {IDT_SW_NTP16_BARSETUP0
, IDT_SW_NTP16_BARLIMIT0
,
203 IDT_SW_NTP16_BARLTBASE0
, IDT_SW_NTP16_BARUTBASE0
},
204 {IDT_SW_NTP16_BARSETUP1
, IDT_SW_NTP16_BARLIMIT1
,
205 IDT_SW_NTP16_BARLTBASE1
, IDT_SW_NTP16_BARUTBASE1
},
206 {IDT_SW_NTP16_BARSETUP2
, IDT_SW_NTP16_BARLIMIT2
,
207 IDT_SW_NTP16_BARLTBASE2
, IDT_SW_NTP16_BARUTBASE2
},
208 {IDT_SW_NTP16_BARSETUP3
, IDT_SW_NTP16_BARLIMIT3
,
209 IDT_SW_NTP16_BARLTBASE3
, IDT_SW_NTP16_BARUTBASE3
},
210 {IDT_SW_NTP16_BARSETUP4
, IDT_SW_NTP16_BARLIMIT4
,
211 IDT_SW_NTP16_BARLTBASE4
, IDT_SW_NTP16_BARUTBASE4
},
212 {IDT_SW_NTP16_BARSETUP5
, IDT_SW_NTP16_BARLIMIT5
,
213 IDT_SW_NTP16_BARLTBASE5
, IDT_SW_NTP16_BARUTBASE5
} } },
217 /*20*/ { IDT_SW_NTP20_PCIECMDSTS
, IDT_SW_NTP20_PCIELCTLSTS
,
219 IDT_SW_SWPORT20CTL
, IDT_SW_SWPORT20STS
,
220 { {IDT_SW_NTP20_BARSETUP0
, IDT_SW_NTP20_BARLIMIT0
,
221 IDT_SW_NTP20_BARLTBASE0
, IDT_SW_NTP20_BARUTBASE0
},
222 {IDT_SW_NTP20_BARSETUP1
, IDT_SW_NTP20_BARLIMIT1
,
223 IDT_SW_NTP20_BARLTBASE1
, IDT_SW_NTP20_BARUTBASE1
},
224 {IDT_SW_NTP20_BARSETUP2
, IDT_SW_NTP20_BARLIMIT2
,
225 IDT_SW_NTP20_BARLTBASE2
, IDT_SW_NTP20_BARUTBASE2
},
226 {IDT_SW_NTP20_BARSETUP3
, IDT_SW_NTP20_BARLIMIT3
,
227 IDT_SW_NTP20_BARLTBASE3
, IDT_SW_NTP20_BARUTBASE3
},
228 {IDT_SW_NTP20_BARSETUP4
, IDT_SW_NTP20_BARLIMIT4
,
229 IDT_SW_NTP20_BARLTBASE4
, IDT_SW_NTP20_BARUTBASE4
},
230 {IDT_SW_NTP20_BARSETUP5
, IDT_SW_NTP20_BARLIMIT5
,
231 IDT_SW_NTP20_BARLTBASE5
, IDT_SW_NTP20_BARUTBASE5
} } },
238 * IDT PCIe-switch partitions table with the corresponding control, status
239 * and messages control registers
241 static const struct idt_ntb_part partdata_tbl
[IDT_MAX_NR_PARTS
] = {
242 /*0*/ { IDT_SW_SWPART0CTL
, IDT_SW_SWPART0STS
,
243 {IDT_SW_SWP0MSGCTL0
, IDT_SW_SWP0MSGCTL1
,
244 IDT_SW_SWP0MSGCTL2
, IDT_SW_SWP0MSGCTL3
} },
245 /*1*/ { IDT_SW_SWPART1CTL
, IDT_SW_SWPART1STS
,
246 {IDT_SW_SWP1MSGCTL0
, IDT_SW_SWP1MSGCTL1
,
247 IDT_SW_SWP1MSGCTL2
, IDT_SW_SWP1MSGCTL3
} },
248 /*2*/ { IDT_SW_SWPART2CTL
, IDT_SW_SWPART2STS
,
249 {IDT_SW_SWP2MSGCTL0
, IDT_SW_SWP2MSGCTL1
,
250 IDT_SW_SWP2MSGCTL2
, IDT_SW_SWP2MSGCTL3
} },
251 /*3*/ { IDT_SW_SWPART3CTL
, IDT_SW_SWPART3STS
,
252 {IDT_SW_SWP3MSGCTL0
, IDT_SW_SWP3MSGCTL1
,
253 IDT_SW_SWP3MSGCTL2
, IDT_SW_SWP3MSGCTL3
} },
254 /*4*/ { IDT_SW_SWPART4CTL
, IDT_SW_SWPART4STS
,
255 {IDT_SW_SWP4MSGCTL0
, IDT_SW_SWP4MSGCTL1
,
256 IDT_SW_SWP4MSGCTL2
, IDT_SW_SWP4MSGCTL3
} },
257 /*5*/ { IDT_SW_SWPART5CTL
, IDT_SW_SWPART5STS
,
258 {IDT_SW_SWP5MSGCTL0
, IDT_SW_SWP5MSGCTL1
,
259 IDT_SW_SWP5MSGCTL2
, IDT_SW_SWP5MSGCTL3
} },
260 /*6*/ { IDT_SW_SWPART6CTL
, IDT_SW_SWPART6STS
,
261 {IDT_SW_SWP6MSGCTL0
, IDT_SW_SWP6MSGCTL1
,
262 IDT_SW_SWP6MSGCTL2
, IDT_SW_SWP6MSGCTL3
} },
263 /*7*/ { IDT_SW_SWPART7CTL
, IDT_SW_SWPART7STS
,
264 {IDT_SW_SWP7MSGCTL0
, IDT_SW_SWP7MSGCTL1
,
265 IDT_SW_SWP7MSGCTL2
, IDT_SW_SWP7MSGCTL3
} }
269 * DebugFS directory to place the driver debug file
271 static struct dentry
*dbgfs_topdir
;
273 /*=============================================================================
274 * 1. IDT PCIe-switch registers IO-functions
276 * Beside ordinary configuration space registers IDT PCIe-switch expose
277 * global configuration registers, which are used to determine state of other
278 * device ports as well as being notified of some switch-related events.
279 * Additionally all the configuration space registers of all the IDT
280 * PCIe-switch functions are mapped to the Global Address space, so each
281 * function can determine a configuration of any other PCI-function.
282 * Functions declared in this chapter are created to encapsulate access
283 * to configuration and global registers, so the driver code just need to
284 * provide IDT NTB hardware descriptor and a register address.
285 *=============================================================================
289 * idt_nt_write() - PCI configuration space registers write method
290 * @ndev: IDT NTB hardware driver descriptor
291 * @reg: Register to write data to
292 * @data: Value to write to the register
294 * IDT PCIe-switch registers are all Little endian.
296 static void idt_nt_write(struct idt_ntb_dev
*ndev
,
297 const unsigned int reg
, const u32 data
)
300 * It's obvious bug to request a register exceeding the maximum possible
301 * value as well as to have it unaligned.
303 if (WARN_ON(reg
> IDT_REG_PCI_MAX
|| !IS_ALIGNED(reg
, IDT_REG_ALIGN
)))
306 /* Just write the value to the specified register */
307 iowrite32(data
, ndev
->cfgspc
+ (ptrdiff_t)reg
);
311 * idt_nt_read() - PCI configuration space registers read method
312 * @ndev: IDT NTB hardware driver descriptor
313 * @reg: Register to write data to
315 * IDT PCIe-switch Global configuration registers are all Little endian.
317 * Return: register value
319 static u32
idt_nt_read(struct idt_ntb_dev
*ndev
, const unsigned int reg
)
322 * It's obvious bug to request a register exceeding the maximum possible
323 * value as well as to have it unaligned.
325 if (WARN_ON(reg
> IDT_REG_PCI_MAX
|| !IS_ALIGNED(reg
, IDT_REG_ALIGN
)))
328 /* Just read the value from the specified register */
329 return ioread32(ndev
->cfgspc
+ (ptrdiff_t)reg
);
333 * idt_sw_write() - Global registers write method
334 * @ndev: IDT NTB hardware driver descriptor
335 * @reg: Register to write data to
336 * @data: Value to write to the register
338 * IDT PCIe-switch Global configuration registers are all Little endian.
340 static void idt_sw_write(struct idt_ntb_dev
*ndev
,
341 const unsigned int reg
, const u32 data
)
343 unsigned long irqflags
;
346 * It's obvious bug to request a register exceeding the maximum possible
347 * value as well as to have it unaligned.
349 if (WARN_ON(reg
> IDT_REG_SW_MAX
|| !IS_ALIGNED(reg
, IDT_REG_ALIGN
)))
352 /* Lock GASA registers operations */
353 spin_lock_irqsave(&ndev
->gasa_lock
, irqflags
);
354 /* Set the global register address */
355 iowrite32((u32
)reg
, ndev
->cfgspc
+ (ptrdiff_t)IDT_NT_GASAADDR
);
356 /* Put the new value of the register */
357 iowrite32(data
, ndev
->cfgspc
+ (ptrdiff_t)IDT_NT_GASADATA
);
358 /* Make sure the PCIe transactions are executed */
360 /* Unlock GASA registers operations */
361 spin_unlock_irqrestore(&ndev
->gasa_lock
, irqflags
);
365 * idt_sw_read() - Global registers read method
366 * @ndev: IDT NTB hardware driver descriptor
367 * @reg: Register to write data to
369 * IDT PCIe-switch Global configuration registers are all Little endian.
371 * Return: register value
373 static u32
idt_sw_read(struct idt_ntb_dev
*ndev
, const unsigned int reg
)
375 unsigned long irqflags
;
379 * It's obvious bug to request a register exceeding the maximum possible
380 * value as well as to have it unaligned.
382 if (WARN_ON(reg
> IDT_REG_SW_MAX
|| !IS_ALIGNED(reg
, IDT_REG_ALIGN
)))
385 /* Lock GASA registers operations */
386 spin_lock_irqsave(&ndev
->gasa_lock
, irqflags
);
387 /* Set the global register address */
388 iowrite32((u32
)reg
, ndev
->cfgspc
+ (ptrdiff_t)IDT_NT_GASAADDR
);
389 /* Get the data of the register (read ops acts as MMIO barrier) */
390 data
= ioread32(ndev
->cfgspc
+ (ptrdiff_t)IDT_NT_GASADATA
);
391 /* Unlock GASA registers operations */
392 spin_unlock_irqrestore(&ndev
->gasa_lock
, irqflags
);
398 * idt_reg_set_bits() - set bits of a passed register
399 * @ndev: IDT NTB hardware driver descriptor
400 * @reg: Register to change bits of
401 * @reg_lock: Register access spin lock
402 * @valid_mask: Mask of valid bits
403 * @set_bits: Bitmask to set
405 * Helper method to check whether a passed bitfield is valid and set
406 * corresponding bits of a register.
408 * WARNING! Make sure the passed register isn't accessed over plane
409 * idt_nt_write() method (read method is ok to be used concurrently).
411 * Return: zero on success, negative error on invalid bitmask.
413 static inline int idt_reg_set_bits(struct idt_ntb_dev
*ndev
, unsigned int reg
,
414 spinlock_t
*reg_lock
,
415 u64 valid_mask
, u64 set_bits
)
417 unsigned long irqflags
;
420 if (set_bits
& ~(u64
)valid_mask
)
423 /* Lock access to the register unless the change is written back */
424 spin_lock_irqsave(reg_lock
, irqflags
);
425 data
= idt_nt_read(ndev
, reg
) | (u32
)set_bits
;
426 idt_nt_write(ndev
, reg
, data
);
427 /* Unlock the register */
428 spin_unlock_irqrestore(reg_lock
, irqflags
);
434 * idt_reg_clear_bits() - clear bits of a passed register
435 * @ndev: IDT NTB hardware driver descriptor
436 * @reg: Register to change bits of
437 * @reg_lock: Register access spin lock
438 * @set_bits: Bitmask to clear
440 * Helper method to check whether a passed bitfield is valid and clear
441 * corresponding bits of a register.
443 * NOTE! Invalid bits are always considered cleared so it's not an error
444 * to clear them over.
446 * WARNING! Make sure the passed register isn't accessed over plane
447 * idt_nt_write() method (read method is ok to use concurrently).
449 static inline void idt_reg_clear_bits(struct idt_ntb_dev
*ndev
,
450 unsigned int reg
, spinlock_t
*reg_lock
,
453 unsigned long irqflags
;
456 /* Lock access to the register unless the change is written back */
457 spin_lock_irqsave(reg_lock
, irqflags
);
458 data
= idt_nt_read(ndev
, reg
) & ~(u32
)clear_bits
;
459 idt_nt_write(ndev
, reg
, data
);
460 /* Unlock the register */
461 spin_unlock_irqrestore(reg_lock
, irqflags
);
464 /*===========================================================================
465 * 2. Ports operations
467 * IDT PCIe-switches can have from 3 up to 8 ports with possible
468 * NT-functions enabled. So all the possible ports need to be scanned looking
469 * for NTB activated. NTB API will have enumerated only the ports with NTB.
470 *===========================================================================
474 * idt_scan_ports() - scan IDT PCIe-switch ports collecting info in the tables
475 * @ndev: Pointer to the PCI device descriptor
477 * Return: zero on success, otherwise a negative error number.
479 static int idt_scan_ports(struct idt_ntb_dev
*ndev
)
481 unsigned char pidx
, port
, part
;
482 u32 data
, portsts
, partsts
;
484 /* Retrieve the local port number */
485 data
= idt_nt_read(ndev
, IDT_NT_PCIELCAP
);
486 ndev
->port
= GET_FIELD(PCIELCAP_PORTNUM
, data
);
488 /* Retrieve the local partition number */
489 portsts
= idt_sw_read(ndev
, portdata_tbl
[ndev
->port
].sts
);
490 ndev
->part
= GET_FIELD(SWPORTxSTS_SWPART
, portsts
);
492 /* Initialize port/partition -> index tables with invalid values */
493 memset(ndev
->port_idx_map
, -EINVAL
, sizeof(ndev
->port_idx_map
));
494 memset(ndev
->part_idx_map
, -EINVAL
, sizeof(ndev
->part_idx_map
));
497 * Walk over all the possible ports checking whether any of them has
498 * NT-function activated
501 for (pidx
= 0; pidx
< ndev
->swcfg
->port_cnt
; pidx
++) {
502 port
= ndev
->swcfg
->ports
[pidx
];
503 /* Skip local port */
504 if (port
== ndev
->port
)
507 /* Read the port status register to get it partition */
508 portsts
= idt_sw_read(ndev
, portdata_tbl
[port
].sts
);
509 part
= GET_FIELD(SWPORTxSTS_SWPART
, portsts
);
511 /* Retrieve the partition status */
512 partsts
= idt_sw_read(ndev
, partdata_tbl
[part
].sts
);
513 /* Check if partition state is active and port has NTB */
514 if (IS_FLD_SET(SWPARTxSTS_STATE
, partsts
, ACT
) &&
515 (IS_FLD_SET(SWPORTxSTS_MODE
, portsts
, NT
) ||
516 IS_FLD_SET(SWPORTxSTS_MODE
, portsts
, USNT
) ||
517 IS_FLD_SET(SWPORTxSTS_MODE
, portsts
, USNTDMA
) ||
518 IS_FLD_SET(SWPORTxSTS_MODE
, portsts
, NTDMA
))) {
519 /* Save the port and partition numbers */
520 ndev
->peers
[ndev
->peer_cnt
].port
= port
;
521 ndev
->peers
[ndev
->peer_cnt
].part
= part
;
522 /* Fill in the port/partition -> index tables */
523 ndev
->port_idx_map
[port
] = ndev
->peer_cnt
;
524 ndev
->part_idx_map
[part
] = ndev
->peer_cnt
;
529 dev_dbg(&ndev
->ntb
.pdev
->dev
, "Local port: %hhu, num of peers: %hhu\n",
530 ndev
->port
, ndev
->peer_cnt
);
532 /* It's useless to have this driver loaded if there is no any peer */
533 if (ndev
->peer_cnt
== 0) {
534 dev_warn(&ndev
->ntb
.pdev
->dev
, "No active peer found\n");
542 * idt_ntb_port_number() - get the local port number
543 * @ntb: NTB device context.
545 * Return: the local port number
547 static int idt_ntb_port_number(struct ntb_dev
*ntb
)
549 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
555 * idt_ntb_peer_port_count() - get the number of peer ports
556 * @ntb: NTB device context.
558 * Return the count of detected peer NT-functions.
560 * Return: number of peer ports
562 static int idt_ntb_peer_port_count(struct ntb_dev
*ntb
)
564 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
566 return ndev
->peer_cnt
;
570 * idt_ntb_peer_port_number() - get peer port by given index
571 * @ntb: NTB device context.
572 * @pidx: Peer port index.
574 * Return: peer port or negative error
576 static int idt_ntb_peer_port_number(struct ntb_dev
*ntb
, int pidx
)
578 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
580 if (pidx
< 0 || ndev
->peer_cnt
<= pidx
)
583 /* Return the detected NT-function port number */
584 return ndev
->peers
[pidx
].port
;
588 * idt_ntb_peer_port_idx() - get peer port index by given port number
589 * @ntb: NTB device context.
590 * @port: Peer port number.
592 * Internal port -> index table is pre-initialized with -EINVAL values,
593 * so we just need to return it value
595 * Return: peer NT-function port index or negative error
597 static int idt_ntb_peer_port_idx(struct ntb_dev
*ntb
, int port
)
599 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
601 if (port
< 0 || IDT_MAX_NR_PORTS
<= port
)
604 return ndev
->port_idx_map
[port
];
607 /*===========================================================================
608 * 3. Link status operations
609 * There is no any ready-to-use method to have peer ports notified if NTB
610 * link is set up or got down. Instead global signal can be used instead.
611 * In case if any one of ports changes local NTB link state, it sends
612 * global signal and clears corresponding global state bit. Then all the ports
613 * receive a notification of that, so to make client driver being aware of
614 * possible NTB link change.
615 * Additionally each of active NT-functions is subscribed to PCIe-link
616 * state changes of peer ports.
617 *===========================================================================
620 static void idt_ntb_local_link_disable(struct idt_ntb_dev
*ndev
);
623 * idt_init_link() - Initialize NTB link state notification subsystem
624 * @ndev: IDT NTB hardware driver descriptor
626 * Function performs the basic initialization of some global registers
627 * needed to enable IRQ-based notifications of PCIe Link Up/Down and
628 * Global Signal events.
629 * NOTE Since it's not possible to determine when all the NTB peer drivers are
630 * unloaded as well as have those registers accessed concurrently, we must
631 * preinitialize them with the same value and leave it uncleared on local
634 static void idt_init_link(struct idt_ntb_dev
*ndev
)
636 u32 part_mask
, port_mask
, se_mask
;
639 /* Initialize spin locker of Mapping Table access registers */
640 spin_lock_init(&ndev
->mtbl_lock
);
642 /* Walk over all detected peers collecting port and partition masks */
643 port_mask
= ~BIT(ndev
->port
);
644 part_mask
= ~BIT(ndev
->part
);
645 for (pidx
= 0; pidx
< ndev
->peer_cnt
; pidx
++) {
646 port_mask
&= ~BIT(ndev
->peers
[pidx
].port
);
647 part_mask
&= ~BIT(ndev
->peers
[pidx
].part
);
650 /* Clean the Link Up/Down and GLobal Signal status registers */
651 idt_sw_write(ndev
, IDT_SW_SELINKUPSTS
, (u32
)-1);
652 idt_sw_write(ndev
, IDT_SW_SELINKDNSTS
, (u32
)-1);
653 idt_sw_write(ndev
, IDT_SW_SEGSIGSTS
, (u32
)-1);
655 /* Unmask NT-activated partitions to receive Global Switch events */
656 idt_sw_write(ndev
, IDT_SW_SEPMSK
, part_mask
);
658 /* Enable PCIe Link Up events of NT-activated ports */
659 idt_sw_write(ndev
, IDT_SW_SELINKUPMSK
, port_mask
);
661 /* Enable PCIe Link Down events of NT-activated ports */
662 idt_sw_write(ndev
, IDT_SW_SELINKDNMSK
, port_mask
);
664 /* Unmask NT-activated partitions to receive Global Signal events */
665 idt_sw_write(ndev
, IDT_SW_SEGSIGMSK
, part_mask
);
667 /* Unmask Link Up/Down and Global Switch Events */
668 se_mask
= ~(IDT_SEMSK_LINKUP
| IDT_SEMSK_LINKDN
| IDT_SEMSK_GSIGNAL
);
669 idt_sw_write(ndev
, IDT_SW_SEMSK
, se_mask
);
671 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB link status events initialized");
675 * idt_deinit_link() - deinitialize link subsystem
676 * @ndev: IDT NTB hardware driver descriptor
678 * Just disable the link back.
680 static void idt_deinit_link(struct idt_ntb_dev
*ndev
)
682 /* Disable the link */
683 idt_ntb_local_link_disable(ndev
);
685 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB link status events deinitialized");
689 * idt_se_isr() - switch events ISR
690 * @ndev: IDT NTB hardware driver descriptor
691 * @ntint_sts: NT-function interrupt status
693 * This driver doesn't support IDT PCIe-switch dynamic reconfigurations,
694 * Failover capability, etc, so switch events are utilized to notify of
695 * PCIe and NTB link events.
696 * The method is called from PCIe ISR bottom-half routine.
698 static void idt_se_isr(struct idt_ntb_dev
*ndev
, u32 ntint_sts
)
702 /* Read Switch Events status */
703 sests
= idt_sw_read(ndev
, IDT_SW_SESTS
);
705 /* Clean the Link Up/Down and Global Signal status registers */
706 idt_sw_write(ndev
, IDT_SW_SELINKUPSTS
, (u32
)-1);
707 idt_sw_write(ndev
, IDT_SW_SELINKDNSTS
, (u32
)-1);
708 idt_sw_write(ndev
, IDT_SW_SEGSIGSTS
, (u32
)-1);
710 /* Clean the corresponding interrupt bit */
711 idt_nt_write(ndev
, IDT_NT_NTINTSTS
, IDT_NTINTSTS_SEVENT
);
713 dev_dbg(&ndev
->ntb
.pdev
->dev
, "SE IRQ detected %#08x (SESTS %#08x)",
716 /* Notify the client driver of possible link state change */
717 ntb_link_event(&ndev
->ntb
);
721 * idt_ntb_local_link_enable() - enable the local NTB link.
722 * @ndev: IDT NTB hardware driver descriptor
724 * In order to enable the NTB link we need:
725 * - enable Completion TLPs translation
726 * - initialize mapping table to enable the Request ID translation
727 * - notify peers of NTB link state change
729 static void idt_ntb_local_link_enable(struct idt_ntb_dev
*ndev
)
731 u32 reqid
, mtbldata
= 0;
732 unsigned long irqflags
;
734 /* Enable the ID protection and Completion TLPs translation */
735 idt_nt_write(ndev
, IDT_NT_NTCTL
, IDT_NTCTL_CPEN
);
737 /* Retrieve the current Requester ID (Bus:Device:Function) */
738 reqid
= idt_nt_read(ndev
, IDT_NT_REQIDCAP
);
741 * Set the corresponding NT Mapping table entry of port partition index
742 * with the data to perform the Request ID translation
744 mtbldata
= SET_FIELD(NTMTBLDATA_REQID
, 0, reqid
) |
745 SET_FIELD(NTMTBLDATA_PART
, 0, ndev
->part
) |
746 IDT_NTMTBLDATA_VALID
;
747 spin_lock_irqsave(&ndev
->mtbl_lock
, irqflags
);
748 idt_nt_write(ndev
, IDT_NT_NTMTBLADDR
, ndev
->part
);
749 idt_nt_write(ndev
, IDT_NT_NTMTBLDATA
, mtbldata
);
751 spin_unlock_irqrestore(&ndev
->mtbl_lock
, irqflags
);
753 /* Notify the peers by setting and clearing the global signal bit */
754 idt_nt_write(ndev
, IDT_NT_NTGSIGNAL
, IDT_NTGSIGNAL_SET
);
755 idt_sw_write(ndev
, IDT_SW_SEGSIGSTS
, (u32
)1 << ndev
->part
);
759 * idt_ntb_local_link_disable() - disable the local NTB link.
760 * @ndev: IDT NTB hardware driver descriptor
762 * In order to enable the NTB link we need:
763 * - disable Completion TLPs translation
764 * - clear corresponding mapping table entry
765 * - notify peers of NTB link state change
767 static void idt_ntb_local_link_disable(struct idt_ntb_dev
*ndev
)
769 unsigned long irqflags
;
771 /* Disable Completion TLPs translation */
772 idt_nt_write(ndev
, IDT_NT_NTCTL
, 0);
774 /* Clear the corresponding NT Mapping table entry */
775 spin_lock_irqsave(&ndev
->mtbl_lock
, irqflags
);
776 idt_nt_write(ndev
, IDT_NT_NTMTBLADDR
, ndev
->part
);
777 idt_nt_write(ndev
, IDT_NT_NTMTBLDATA
, 0);
779 spin_unlock_irqrestore(&ndev
->mtbl_lock
, irqflags
);
781 /* Notify the peers by setting and clearing the global signal bit */
782 idt_nt_write(ndev
, IDT_NT_NTGSIGNAL
, IDT_NTGSIGNAL_SET
);
783 idt_sw_write(ndev
, IDT_SW_SEGSIGSTS
, (u32
)1 << ndev
->part
);
787 * idt_ntb_local_link_is_up() - test wethter local NTB link is up
788 * @ndev: IDT NTB hardware driver descriptor
790 * Local link is up under the following conditions:
791 * - Bus mastering is enabled
792 * - NTCTL has Completion TLPs translation enabled
793 * - Mapping table permits Request TLPs translation
794 * NOTE: We don't need to check PCIe link state since it's obviously
795 * up while we are able to communicate with IDT PCIe-switch
797 * Return: true if link is up, otherwise false
799 static bool idt_ntb_local_link_is_up(struct idt_ntb_dev
*ndev
)
801 unsigned long irqflags
;
804 /* Read the local Bus Master Enable status */
805 data
= idt_nt_read(ndev
, IDT_NT_PCICMDSTS
);
806 if (!(data
& IDT_PCICMDSTS_BME
))
809 /* Read the local Completion TLPs translation enable status */
810 data
= idt_nt_read(ndev
, IDT_NT_NTCTL
);
811 if (!(data
& IDT_NTCTL_CPEN
))
814 /* Read Mapping table entry corresponding to the local partition */
815 spin_lock_irqsave(&ndev
->mtbl_lock
, irqflags
);
816 idt_nt_write(ndev
, IDT_NT_NTMTBLADDR
, ndev
->part
);
817 data
= idt_nt_read(ndev
, IDT_NT_NTMTBLDATA
);
818 spin_unlock_irqrestore(&ndev
->mtbl_lock
, irqflags
);
820 return !!(data
& IDT_NTMTBLDATA_VALID
);
824 * idt_ntb_peer_link_is_up() - test whether peer NTB link is up
825 * @ndev: IDT NTB hardware driver descriptor
826 * @pidx: Peer port index
828 * Peer link is up under the following conditions:
830 * - Bus mastering is enabled
831 * - NTCTL has Completion TLPs translation enabled
832 * - Mapping table permits Request TLPs translation
834 * Return: true if link is up, otherwise false
836 static bool idt_ntb_peer_link_is_up(struct idt_ntb_dev
*ndev
, int pidx
)
838 unsigned long irqflags
;
842 /* Retrieve the device port number */
843 port
= ndev
->peers
[pidx
].port
;
845 /* Check whether PCIe link is up */
846 data
= idt_sw_read(ndev
, portdata_tbl
[port
].sts
);
847 if (!(data
& IDT_SWPORTxSTS_LINKUP
))
850 /* Check whether bus mastering is enabled on the peer port */
851 data
= idt_sw_read(ndev
, portdata_tbl
[port
].pcicmdsts
);
852 if (!(data
& IDT_PCICMDSTS_BME
))
855 /* Check if Completion TLPs translation is enabled on the peer port */
856 data
= idt_sw_read(ndev
, portdata_tbl
[port
].ntctl
);
857 if (!(data
& IDT_NTCTL_CPEN
))
860 /* Read Mapping table entry corresponding to the peer partition */
861 spin_lock_irqsave(&ndev
->mtbl_lock
, irqflags
);
862 idt_nt_write(ndev
, IDT_NT_NTMTBLADDR
, ndev
->peers
[pidx
].part
);
863 data
= idt_nt_read(ndev
, IDT_NT_NTMTBLDATA
);
864 spin_unlock_irqrestore(&ndev
->mtbl_lock
, irqflags
);
866 return !!(data
& IDT_NTMTBLDATA_VALID
);
870 * idt_ntb_link_is_up() - get the current ntb link state (NTB API callback)
871 * @ntb: NTB device context.
872 * @speed: OUT - The link speed expressed as PCIe generation number.
873 * @width: OUT - The link width expressed as the number of PCIe lanes.
875 * Get the bitfield of NTB link states for all peer ports
877 * Return: bitfield of indexed ports link state: bit is set/cleared if the
878 * link is up/down respectively.
880 static u64
idt_ntb_link_is_up(struct ntb_dev
*ntb
,
881 enum ntb_speed
*speed
, enum ntb_width
*width
)
883 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
888 /* Retrieve the local link speed and width */
889 if (speed
!= NULL
|| width
!= NULL
) {
890 data
= idt_nt_read(ndev
, IDT_NT_PCIELCTLSTS
);
892 *speed
= GET_FIELD(PCIELCTLSTS_CLS
, data
);
894 *width
= GET_FIELD(PCIELCTLSTS_NLW
, data
);
897 /* If local NTB link isn't up then all the links are considered down */
898 if (!idt_ntb_local_link_is_up(ndev
))
901 /* Collect all the peer ports link states into the bitfield */
903 for (pidx
= 0; pidx
< ndev
->peer_cnt
; pidx
++) {
904 if (idt_ntb_peer_link_is_up(ndev
, pidx
))
905 status
|= ((u64
)1 << pidx
);
912 * idt_ntb_link_enable() - enable local port ntb link (NTB API callback)
913 * @ntb: NTB device context.
914 * @max_speed: The maximum link speed expressed as PCIe generation number.
915 * @max_width: The maximum link width expressed as the number of PCIe lanes.
917 * Enable just local NTB link. PCIe link parameters are ignored.
919 * Return: always zero.
921 static int idt_ntb_link_enable(struct ntb_dev
*ntb
, enum ntb_speed speed
,
922 enum ntb_width width
)
924 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
926 /* Just enable the local NTB link */
927 idt_ntb_local_link_enable(ndev
);
929 dev_dbg(&ndev
->ntb
.pdev
->dev
, "Local NTB link enabled");
935 * idt_ntb_link_disable() - disable local port ntb link (NTB API callback)
936 * @ntb: NTB device context.
938 * Disable just local NTB link.
940 * Return: always zero.
942 static int idt_ntb_link_disable(struct ntb_dev
*ntb
)
944 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
946 /* Just disable the local NTB link */
947 idt_ntb_local_link_disable(ndev
);
949 dev_dbg(&ndev
->ntb
.pdev
->dev
, "Local NTB link disabled");
954 /*=============================================================================
955 * 4. Memory Window operations
957 * IDT PCIe-switches have two types of memory windows: MWs with direct
958 * address translation and MWs with LUT based translation. The first type of
959 * MWs is simple map of corresponding BAR address space to a memory space
960 * of specified target port. So it implemets just ont-to-one mapping. Lookup
961 * table in its turn can map one BAR address space to up to 24 different
962 * memory spaces of different ports.
963 * NT-functions BARs can be turned on to implement either direct or lookup
964 * table based address translations, so:
965 * BAR0 - NT configuration registers space/direct address translation
966 * BAR1 - direct address translation/upper address of BAR0x64
967 * BAR2 - direct address translation/Lookup table with either 12 or 24 entries
968 * BAR3 - direct address translation/upper address of BAR2x64
969 * BAR4 - direct address translation/Lookup table with either 12 or 24 entries
970 * BAR5 - direct address translation/upper address of BAR4x64
971 * Additionally BAR2 and BAR4 can't have 24-entries LUT enabled at the same
972 * time. Since the BARs setup can be rather complicated this driver implements
973 * a scanning algorithm to have all the possible memory windows configuration
976 * NOTE 1 BAR setup must be done before Linux kernel enumerated NT-function
977 * of any port, so this driver would have memory windows configurations fixed.
978 * In this way all initializations must be performed either by platform BIOS
979 * or using EEPROM connected to IDT PCIe-switch master SMBus.
981 * NOTE 2 This driver expects BAR0 mapping NT-function configuration space.
982 * Easy calculation can give us an upper boundary of 29 possible memory windows
983 * per each NT-function if all the BARs are of 32bit type.
984 *=============================================================================
988 * idt_get_mw_count() - get memory window count
989 * @mw_type: Memory window type
991 * Return: number of memory windows with respect to the BAR type
993 static inline unsigned char idt_get_mw_count(enum idt_mw_type mw_type
)
1010 * idt_get_mw_name() - get memory window name
1011 * @mw_type: Memory window type
1013 * Return: pointer to a string with name
1015 static inline char *idt_get_mw_name(enum idt_mw_type mw_type
)
1032 * idt_scan_mws() - scan memory windows of the port
1033 * @ndev: IDT NTB hardware driver descriptor
1034 * @port: Port to get number of memory windows for
1035 * @mw_cnt: Out - number of memory windows
1037 * It walks over BAR setup registers of the specified port and determines
1038 * the memory windows parameters if any activated.
1040 * Return: array of memory windows
1042 static struct idt_mw_cfg
*idt_scan_mws(struct idt_ntb_dev
*ndev
, int port
,
1043 unsigned char *mw_cnt
)
1045 struct idt_mw_cfg mws
[IDT_MAX_NR_MWS
], *ret_mws
;
1046 const struct idt_ntb_bar
*bars
;
1047 enum idt_mw_type mw_type
;
1048 unsigned char widx
, bidx
, en_cnt
;
1049 bool bar_64bit
= false;
1053 /* Retrieve the array of the BARs registers */
1054 bars
= portdata_tbl
[port
].bars
;
1056 /* Scan all the BARs belonging to the port */
1058 for (bidx
= 0; bidx
< IDT_BAR_CNT
; bidx
+= 1 + bar_64bit
) {
1059 /* Read BARSETUP register value */
1060 data
= idt_sw_read(ndev
, bars
[bidx
].setup
);
1062 /* Skip disabled BARs */
1063 if (!(data
& IDT_BARSETUP_EN
)) {
1068 /* Skip next BARSETUP if current one has 64bit addressing */
1069 bar_64bit
= IS_FLD_SET(BARSETUP_TYPE
, data
, 64);
1071 /* Skip configuration space mapping BARs */
1072 if (data
& IDT_BARSETUP_MODE_CFG
)
1075 /* Retrieve MW type/entries count and aperture size */
1076 mw_type
= GET_FIELD(BARSETUP_ATRAN
, data
);
1077 en_cnt
= idt_get_mw_count(mw_type
);
1078 aprt_size
= (u64
)1 << GET_FIELD(BARSETUP_SIZE
, data
);
1080 /* Save configurations of all available memory windows */
1081 for (widx
= 0; widx
< en_cnt
; widx
++, (*mw_cnt
)++) {
1083 * IDT can expose a limited number of MWs, so it's bug
1084 * to have more than the driver expects
1086 if (*mw_cnt
>= IDT_MAX_NR_MWS
)
1087 return ERR_PTR(-EINVAL
);
1089 /* Save basic MW info */
1090 mws
[*mw_cnt
].type
= mw_type
;
1091 mws
[*mw_cnt
].bar
= bidx
;
1092 mws
[*mw_cnt
].idx
= widx
;
1093 /* It's always DWORD aligned */
1094 mws
[*mw_cnt
].addr_align
= IDT_TRANS_ALIGN
;
1095 /* DIR and LUT approachs differently configure MWs */
1096 if (mw_type
== IDT_MW_DIR
)
1097 mws
[*mw_cnt
].size_max
= aprt_size
;
1098 else if (mw_type
== IDT_MW_LUT12
)
1099 mws
[*mw_cnt
].size_max
= aprt_size
/ 16;
1101 mws
[*mw_cnt
].size_max
= aprt_size
/ 32;
1102 mws
[*mw_cnt
].size_align
= (mw_type
== IDT_MW_DIR
) ?
1103 IDT_DIR_SIZE_ALIGN
: mws
[*mw_cnt
].size_max
;
1107 /* Allocate memory for memory window descriptors */
1108 ret_mws
= devm_kcalloc(&ndev
->ntb
.pdev
->dev
, *mw_cnt
, sizeof(*ret_mws
),
1111 return ERR_PTR(-ENOMEM
);
1113 /* Copy the info of detected memory windows */
1114 memcpy(ret_mws
, mws
, (*mw_cnt
)*sizeof(*ret_mws
));
1120 * idt_init_mws() - initialize memory windows subsystem
1121 * @ndev: IDT NTB hardware driver descriptor
1123 * Scan BAR setup registers of local and peer ports to determine the
1124 * outbound and inbound memory windows parameters
1126 * Return: zero on success, otherwise a negative error number
1128 static int idt_init_mws(struct idt_ntb_dev
*ndev
)
1130 struct idt_ntb_peer
*peer
;
1133 /* Scan memory windows of the local port */
1134 ndev
->mws
= idt_scan_mws(ndev
, ndev
->port
, &ndev
->mw_cnt
);
1135 if (IS_ERR(ndev
->mws
)) {
1136 dev_err(&ndev
->ntb
.pdev
->dev
,
1137 "Failed to scan mws of local port %hhu", ndev
->port
);
1138 return PTR_ERR(ndev
->mws
);
1141 /* Scan memory windows of the peer ports */
1142 for (pidx
= 0; pidx
< ndev
->peer_cnt
; pidx
++) {
1143 peer
= &ndev
->peers
[pidx
];
1144 peer
->mws
= idt_scan_mws(ndev
, peer
->port
, &peer
->mw_cnt
);
1145 if (IS_ERR(peer
->mws
)) {
1146 dev_err(&ndev
->ntb
.pdev
->dev
,
1147 "Failed to scan mws of port %hhu", peer
->port
);
1148 return PTR_ERR(peer
->mws
);
1152 /* Initialize spin locker of the LUT registers */
1153 spin_lock_init(&ndev
->lut_lock
);
1155 dev_dbg(&ndev
->ntb
.pdev
->dev
, "Outbound and inbound MWs initialized");
1161 * idt_ntb_mw_count() - number of inbound memory windows (NTB API callback)
1162 * @ntb: NTB device context.
1163 * @pidx: Port index of peer device.
1165 * The value is returned for the specified peer, so generally speaking it can
1166 * be different for different port depending on the IDT PCIe-switch
1169 * Return: the number of memory windows.
1171 static int idt_ntb_mw_count(struct ntb_dev
*ntb
, int pidx
)
1173 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1175 if (pidx
< 0 || ndev
->peer_cnt
<= pidx
)
1178 return ndev
->peers
[pidx
].mw_cnt
;
1182 * idt_ntb_mw_get_align() - inbound memory window parameters (NTB API callback)
1183 * @ntb: NTB device context.
1184 * @pidx: Port index of peer device.
1185 * @widx: Memory window index.
1186 * @addr_align: OUT - the base alignment for translating the memory window
1187 * @size_align: OUT - the size alignment for translating the memory window
1188 * @size_max: OUT - the maximum size of the memory window
1190 * The peer memory window parameters have already been determined, so just
1191 * return the corresponding values, which mustn't change within session.
1193 * Return: Zero on success, otherwise a negative error number.
1195 static int idt_ntb_mw_get_align(struct ntb_dev
*ntb
, int pidx
, int widx
,
1196 resource_size_t
*addr_align
,
1197 resource_size_t
*size_align
,
1198 resource_size_t
*size_max
)
1200 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1201 struct idt_ntb_peer
*peer
;
1203 if (pidx
< 0 || ndev
->peer_cnt
<= pidx
)
1206 peer
= &ndev
->peers
[pidx
];
1208 if (widx
< 0 || peer
->mw_cnt
<= widx
)
1211 if (addr_align
!= NULL
)
1212 *addr_align
= peer
->mws
[widx
].addr_align
;
1214 if (size_align
!= NULL
)
1215 *size_align
= peer
->mws
[widx
].size_align
;
1217 if (size_max
!= NULL
)
1218 *size_max
= peer
->mws
[widx
].size_max
;
1224 * idt_ntb_peer_mw_count() - number of outbound memory windows
1225 * (NTB API callback)
1226 * @ntb: NTB device context.
1228 * Outbound memory windows parameters have been determined based on the
1229 * BAR setup registers value, which are mostly constants within one session.
1231 * Return: the number of memory windows.
1233 static int idt_ntb_peer_mw_count(struct ntb_dev
*ntb
)
1235 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1237 return ndev
->mw_cnt
;
1241 * idt_ntb_peer_mw_get_addr() - get map address of an outbound memory window
1242 * (NTB API callback)
1243 * @ntb: NTB device context.
1244 * @widx: Memory window index (within ntb_peer_mw_count() return value).
1245 * @base: OUT - the base address of mapping region.
1246 * @size: OUT - the size of mapping region.
1248 * Return just parameters of BAR resources mapping. Size reflects just the size
1251 * Return: Zero on success, otherwise a negative error number.
1253 static int idt_ntb_peer_mw_get_addr(struct ntb_dev
*ntb
, int widx
,
1254 phys_addr_t
*base
, resource_size_t
*size
)
1256 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1258 if (widx
< 0 || ndev
->mw_cnt
<= widx
)
1261 /* Mapping address is just properly shifted BAR resource start */
1263 *base
= pci_resource_start(ntb
->pdev
, ndev
->mws
[widx
].bar
) +
1264 ndev
->mws
[widx
].idx
* ndev
->mws
[widx
].size_max
;
1266 /* Mapping size has already been calculated at MWs scanning */
1268 *size
= ndev
->mws
[widx
].size_max
;
1274 * idt_ntb_peer_mw_set_trans() - set a translation address of a memory window
1275 * (NTB API callback)
1276 * @ntb: NTB device context.
1277 * @pidx: Port index of peer device the translation address received from.
1278 * @widx: Memory window index.
1279 * @addr: The dma address of the shared memory to access.
1280 * @size: The size of the shared memory to access.
1282 * The Direct address translation and LUT base translation is initialized a
1283 * bit differenet. Although the parameters restriction are now determined by
1286 * Return: Zero on success, otherwise an error number.
1288 static int idt_ntb_peer_mw_set_trans(struct ntb_dev
*ntb
, int pidx
, int widx
,
1289 u64 addr
, resource_size_t size
)
1291 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1292 struct idt_mw_cfg
*mw_cfg
;
1293 u32 data
= 0, lutoff
= 0;
1295 if (pidx
< 0 || ndev
->peer_cnt
<= pidx
)
1298 if (widx
< 0 || ndev
->mw_cnt
<= widx
)
1302 * Retrieve the memory window config to make sure the passed arguments
1303 * fit it restrictions
1305 mw_cfg
= &ndev
->mws
[widx
];
1306 if (!IS_ALIGNED(addr
, mw_cfg
->addr_align
))
1308 if (!IS_ALIGNED(size
, mw_cfg
->size_align
) || size
> mw_cfg
->size_max
)
1311 /* DIR and LUT based translations are initialized differently */
1312 if (mw_cfg
->type
== IDT_MW_DIR
) {
1313 const struct idt_ntb_bar
*bar
= &ntdata_tbl
.bars
[mw_cfg
->bar
];
1315 /* Set destination partition of translation */
1316 data
= idt_nt_read(ndev
, bar
->setup
);
1317 data
= SET_FIELD(BARSETUP_TPART
, data
, ndev
->peers
[pidx
].part
);
1318 idt_nt_write(ndev
, bar
->setup
, data
);
1319 /* Set translation base address */
1320 idt_nt_write(ndev
, bar
->ltbase
, (u32
)addr
);
1321 idt_nt_write(ndev
, bar
->utbase
, (u32
)(addr
>> 32));
1322 /* Set the custom BAR aperture limit */
1323 limit
= pci_resource_start(ntb
->pdev
, mw_cfg
->bar
) + size
;
1324 idt_nt_write(ndev
, bar
->limit
, (u32
)limit
);
1325 if (IS_FLD_SET(BARSETUP_TYPE
, data
, 64))
1326 idt_nt_write(ndev
, (bar
+ 1)->limit
, (limit
>> 32));
1328 unsigned long irqflags
;
1329 /* Initialize corresponding LUT entry */
1330 lutoff
= SET_FIELD(LUTOFFSET_INDEX
, 0, mw_cfg
->idx
) |
1331 SET_FIELD(LUTOFFSET_BAR
, 0, mw_cfg
->bar
);
1332 data
= SET_FIELD(LUTUDATA_PART
, 0, ndev
->peers
[pidx
].part
) |
1334 spin_lock_irqsave(&ndev
->lut_lock
, irqflags
);
1335 idt_nt_write(ndev
, IDT_NT_LUTOFFSET
, lutoff
);
1336 idt_nt_write(ndev
, IDT_NT_LUTLDATA
, (u32
)addr
);
1337 idt_nt_write(ndev
, IDT_NT_LUTMDATA
, (u32
)(addr
>> 32));
1338 idt_nt_write(ndev
, IDT_NT_LUTUDATA
, data
);
1340 spin_unlock_irqrestore(&ndev
->lut_lock
, irqflags
);
1341 /* Limit address isn't specified since size is fixed for LUT */
1348 * idt_ntb_peer_mw_clear_trans() - clear the outbound MW translation address
1349 * (NTB API callback)
1350 * @ntb: NTB device context.
1351 * @pidx: Port index of peer device.
1352 * @widx: Memory window index.
1354 * It effectively disables the translation over the specified outbound MW.
1356 * Return: Zero on success, otherwise an error number.
1358 static int idt_ntb_peer_mw_clear_trans(struct ntb_dev
*ntb
, int pidx
,
1361 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1362 struct idt_mw_cfg
*mw_cfg
;
1364 if (pidx
< 0 || ndev
->peer_cnt
<= pidx
)
1367 if (widx
< 0 || ndev
->mw_cnt
<= widx
)
1370 mw_cfg
= &ndev
->mws
[widx
];
1372 /* DIR and LUT based translations are initialized differently */
1373 if (mw_cfg
->type
== IDT_MW_DIR
) {
1374 const struct idt_ntb_bar
*bar
= &ntdata_tbl
.bars
[mw_cfg
->bar
];
1376 /* Read BARSETUP to check BAR type */
1377 data
= idt_nt_read(ndev
, bar
->setup
);
1378 /* Disable translation by specifying zero BAR limit */
1379 idt_nt_write(ndev
, bar
->limit
, 0);
1380 if (IS_FLD_SET(BARSETUP_TYPE
, data
, 64))
1381 idt_nt_write(ndev
, (bar
+ 1)->limit
, 0);
1383 unsigned long irqflags
;
1385 /* Clear the corresponding LUT entry up */
1386 lutoff
= SET_FIELD(LUTOFFSET_INDEX
, 0, mw_cfg
->idx
) |
1387 SET_FIELD(LUTOFFSET_BAR
, 0, mw_cfg
->bar
);
1388 spin_lock_irqsave(&ndev
->lut_lock
, irqflags
);
1389 idt_nt_write(ndev
, IDT_NT_LUTOFFSET
, lutoff
);
1390 idt_nt_write(ndev
, IDT_NT_LUTLDATA
, 0);
1391 idt_nt_write(ndev
, IDT_NT_LUTMDATA
, 0);
1392 idt_nt_write(ndev
, IDT_NT_LUTUDATA
, 0);
1394 spin_unlock_irqrestore(&ndev
->lut_lock
, irqflags
);
1400 /*=============================================================================
1401 * 5. Doorbell operations
1403 * Doorbell functionality of IDT PCIe-switches is pretty unusual. First of
1404 * all there is global doorbell register which state can by changed by any
1405 * NT-function of the IDT device in accordance with global permissions. These
1406 * permissions configs are not supported by NTB API, so it must be done by
1407 * either BIOS or EEPROM settings. In the same way the state of the global
1408 * doorbell is reflected to the NT-functions local inbound doorbell registers.
1409 * It can lead to situations when client driver sets some peer doorbell bits
1410 * and get them bounced back to local inbound doorbell if permissions are
1412 * Secondly there is just one IRQ vector for Doorbell, Message, Temperature
1413 * and Switch events, so if client driver left any of Doorbell bits set and
1414 * some other event occurred, the driver will be notified of Doorbell event
1416 *=============================================================================
1420 * idt_db_isr() - doorbell event ISR
1421 * @ndev: IDT NTB hardware driver descriptor
1422 * @ntint_sts: NT-function interrupt status
1424 * Doorbell event happans when DBELL bit of NTINTSTS switches from 0 to 1.
1425 * It happens only when unmasked doorbell bits are set to ones on completely
1426 * zeroed doorbell register.
1427 * The method is called from PCIe ISR bottom-half routine.
1429 static void idt_db_isr(struct idt_ntb_dev
*ndev
, u32 ntint_sts
)
1432 * Doorbell IRQ status will be cleaned only when client
1433 * driver unsets all the doorbell bits.
1435 dev_dbg(&ndev
->ntb
.pdev
->dev
, "DB IRQ detected %#08x", ntint_sts
);
1437 /* Notify the client driver of possible doorbell state change */
1438 ntb_db_event(&ndev
->ntb
, 0);
1442 * idt_ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb
1443 * (NTB API callback)
1444 * @ntb: NTB device context.
1446 * IDT PCIe-switches expose just one Doorbell register of DWORD size.
1448 * Return: A mask of doorbell bits supported by the ntb.
1450 static u64
idt_ntb_db_valid_mask(struct ntb_dev
*ntb
)
1452 return IDT_DBELL_MASK
;
1456 * idt_ntb_db_read() - read the local doorbell register (NTB API callback)
1457 * @ntb: NTB device context.
1459 * There is just on inbound doorbell register of each NT-function, so
1460 * this method return it value.
1462 * Return: The bits currently set in the local doorbell register.
1464 static u64
idt_ntb_db_read(struct ntb_dev
*ntb
)
1466 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1468 return idt_nt_read(ndev
, IDT_NT_INDBELLSTS
);
1472 * idt_ntb_db_clear() - clear bits in the local doorbell register
1473 * (NTB API callback)
1474 * @ntb: NTB device context.
1475 * @db_bits: Doorbell bits to clear.
1477 * Clear bits of inbound doorbell register by writing ones to it.
1479 * NOTE! Invalid bits are always considered cleared so it's not an error
1480 * to clear them over.
1482 * Return: always zero as success.
1484 static int idt_ntb_db_clear(struct ntb_dev
*ntb
, u64 db_bits
)
1486 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1488 idt_nt_write(ndev
, IDT_NT_INDBELLSTS
, (u32
)db_bits
);
1494 * idt_ntb_db_read_mask() - read the local doorbell mask (NTB API callback)
1495 * @ntb: NTB device context.
1497 * Each inbound doorbell bit can be masked from generating IRQ by setting
1498 * the corresponding bit in inbound doorbell mask. So this method returns
1499 * the value of the register.
1501 * Return: The bits currently set in the local doorbell mask register.
1503 static u64
idt_ntb_db_read_mask(struct ntb_dev
*ntb
)
1505 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1507 return idt_nt_read(ndev
, IDT_NT_INDBELLMSK
);
1511 * idt_ntb_db_set_mask() - set bits in the local doorbell mask
1512 * (NTB API callback)
1513 * @ntb: NTB device context.
1514 * @db_bits: Doorbell mask bits to set.
1516 * The inbound doorbell register mask value must be read, then OR'ed with
1517 * passed field and only then set back.
1519 * Return: zero on success, negative error if invalid argument passed.
1521 static int idt_ntb_db_set_mask(struct ntb_dev
*ntb
, u64 db_bits
)
1523 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1525 return idt_reg_set_bits(ndev
, IDT_NT_INDBELLMSK
, &ndev
->db_mask_lock
,
1526 IDT_DBELL_MASK
, db_bits
);
1530 * idt_ntb_db_clear_mask() - clear bits in the local doorbell mask
1531 * (NTB API callback)
1532 * @ntb: NTB device context.
1533 * @db_bits: Doorbell bits to clear.
1535 * The method just clears the set bits up in accordance with the passed
1536 * bitfield. IDT PCIe-switch shall generate an interrupt if there hasn't
1537 * been any unmasked bit set before current unmasking. Otherwise IRQ won't
1538 * be generated since there is only one IRQ vector for all doorbells.
1540 * Return: always zero as success
1542 static int idt_ntb_db_clear_mask(struct ntb_dev
*ntb
, u64 db_bits
)
1544 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1546 idt_reg_clear_bits(ndev
, IDT_NT_INDBELLMSK
, &ndev
->db_mask_lock
,
1553 * idt_ntb_peer_db_set() - set bits in the peer doorbell register
1554 * (NTB API callback)
1555 * @ntb: NTB device context.
1556 * @db_bits: Doorbell bits to set.
1558 * IDT PCIe-switches exposes local outbound doorbell register to change peer
1559 * inbound doorbell register state.
1561 * Return: zero on success, negative error if invalid argument passed.
1563 static int idt_ntb_peer_db_set(struct ntb_dev
*ntb
, u64 db_bits
)
1565 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1567 if (db_bits
& ~(u64
)IDT_DBELL_MASK
)
1570 idt_nt_write(ndev
, IDT_NT_OUTDBELLSET
, (u32
)db_bits
);
1574 /*=============================================================================
1575 * 6. Messaging operations
1577 * Each NT-function of IDT PCIe-switch has four inbound and four outbound
1578 * message registers. Each outbound message register can be connected to one or
1579 * even more than one peer inbound message registers by setting global
1580 * configurations. Since NTB API permits one-on-one message registers mapping
1581 * only, the driver acts in according with that restriction.
1582 *=============================================================================
1586 * idt_init_msg() - initialize messaging interface
1587 * @ndev: IDT NTB hardware driver descriptor
1589 * Just initialize the message registers routing tables locker.
1591 static void idt_init_msg(struct idt_ntb_dev
*ndev
)
1595 /* Init the messages routing table lockers */
1596 for (midx
= 0; midx
< IDT_MSG_CNT
; midx
++)
1597 spin_lock_init(&ndev
->msg_locks
[midx
]);
1599 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB Messaging initialized");
1603 * idt_msg_isr() - message event ISR
1604 * @ndev: IDT NTB hardware driver descriptor
1605 * @ntint_sts: NT-function interrupt status
1607 * Message event happens when MSG bit of NTINTSTS switches from 0 to 1.
1608 * It happens only when unmasked message status bits are set to ones on
1609 * completely zeroed message status register.
1610 * The method is called from PCIe ISR bottom-half routine.
1612 static void idt_msg_isr(struct idt_ntb_dev
*ndev
, u32 ntint_sts
)
1615 * Message IRQ status will be cleaned only when client
1616 * driver unsets all the message status bits.
1618 dev_dbg(&ndev
->ntb
.pdev
->dev
, "Message IRQ detected %#08x", ntint_sts
);
1620 /* Notify the client driver of possible message status change */
1621 ntb_msg_event(&ndev
->ntb
);
1625 * idt_ntb_msg_count() - get the number of message registers (NTB API callback)
1626 * @ntb: NTB device context.
1628 * IDT PCIe-switches support four message registers.
1630 * Return: the number of message registers.
1632 static int idt_ntb_msg_count(struct ntb_dev
*ntb
)
1638 * idt_ntb_msg_inbits() - get a bitfield of inbound message registers status
1639 * (NTB API callback)
1640 * @ntb: NTB device context.
1642 * NT message status register is shared between inbound and outbound message
1645 * Return: bitfield of inbound message registers.
1647 static u64
idt_ntb_msg_inbits(struct ntb_dev
*ntb
)
1649 return (u64
)IDT_INMSG_MASK
;
1653 * idt_ntb_msg_outbits() - get a bitfield of outbound message registers status
1654 * (NTB API callback)
1655 * @ntb: NTB device context.
1657 * NT message status register is shared between inbound and outbound message
1660 * Return: bitfield of outbound message registers.
1662 static u64
idt_ntb_msg_outbits(struct ntb_dev
*ntb
)
1664 return (u64
)IDT_OUTMSG_MASK
;
1668 * idt_ntb_msg_read_sts() - read the message registers status (NTB API callback)
1669 * @ntb: NTB device context.
1671 * IDT PCIe-switches expose message status registers to notify drivers of
1672 * incoming data and failures in case if peer message register isn't freed.
1674 * Return: status bits of message registers
1676 static u64
idt_ntb_msg_read_sts(struct ntb_dev
*ntb
)
1678 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1680 return idt_nt_read(ndev
, IDT_NT_MSGSTS
);
1684 * idt_ntb_msg_clear_sts() - clear status bits of message registers
1685 * (NTB API callback)
1686 * @ntb: NTB device context.
1687 * @sts_bits: Status bits to clear.
1689 * Clear bits in the status register by writing ones.
1691 * NOTE! Invalid bits are always considered cleared so it's not an error
1692 * to clear them over.
1694 * Return: always zero as success.
1696 static int idt_ntb_msg_clear_sts(struct ntb_dev
*ntb
, u64 sts_bits
)
1698 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1700 idt_nt_write(ndev
, IDT_NT_MSGSTS
, sts_bits
);
1706 * idt_ntb_msg_set_mask() - set mask of message register status bits
1707 * (NTB API callback)
1708 * @ntb: NTB device context.
1709 * @mask_bits: Mask bits.
1711 * Mask the message status bits from raising an IRQ.
1713 * Return: zero on success, negative error if invalid argument passed.
1715 static int idt_ntb_msg_set_mask(struct ntb_dev
*ntb
, u64 mask_bits
)
1717 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1719 return idt_reg_set_bits(ndev
, IDT_NT_MSGSTSMSK
, &ndev
->msg_mask_lock
,
1720 IDT_MSG_MASK
, mask_bits
);
1724 * idt_ntb_msg_clear_mask() - clear message registers mask
1725 * (NTB API callback)
1726 * @ntb: NTB device context.
1727 * @mask_bits: Mask bits.
1729 * Clear mask of message status bits IRQs.
1731 * Return: always zero as success.
1733 static int idt_ntb_msg_clear_mask(struct ntb_dev
*ntb
, u64 mask_bits
)
1735 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1737 idt_reg_clear_bits(ndev
, IDT_NT_MSGSTSMSK
, &ndev
->msg_mask_lock
,
1744 * idt_ntb_msg_read() - read message register with specified index
1745 * (NTB API callback)
1746 * @ntb: NTB device context.
1747 * @midx: Message register index
1748 * @pidx: OUT - Port index of peer device a message retrieved from
1751 * Read data from the specified message register and source register.
1753 * Return: zero on success, negative error if invalid argument passed.
1755 static int idt_ntb_msg_read(struct ntb_dev
*ntb
, int midx
, int *pidx
, u32
*msg
)
1757 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1759 if (midx
< 0 || IDT_MSG_CNT
<= midx
)
1762 /* Retrieve source port index of the message */
1766 srcpart
= idt_nt_read(ndev
, ntdata_tbl
.msgs
[midx
].src
);
1767 *pidx
= ndev
->part_idx_map
[srcpart
];
1769 /* Sanity check partition index (for initial case) */
1770 if (*pidx
== -EINVAL
)
1774 /* Retrieve data of the corresponding message register */
1776 *msg
= idt_nt_read(ndev
, ntdata_tbl
.msgs
[midx
].in
);
1782 * idt_ntb_msg_write() - write data to the specified message register
1783 * (NTB API callback)
1784 * @ntb: NTB device context.
1785 * @midx: Message register index
1786 * @pidx: Port index of peer device a message being sent to
1787 * @msg: Data to send
1789 * Just try to send data to a peer. Message status register should be
1790 * checked by client driver.
1792 * Return: zero on success, negative error if invalid argument passed.
1794 static int idt_ntb_msg_write(struct ntb_dev
*ntb
, int midx
, int pidx
, u32 msg
)
1796 struct idt_ntb_dev
*ndev
= to_ndev_ntb(ntb
);
1797 unsigned long irqflags
;
1800 if (midx
< 0 || IDT_MSG_CNT
<= midx
)
1803 if (pidx
< 0 || ndev
->peer_cnt
<= pidx
)
1806 /* Collect the routing information */
1807 swpmsgctl
= SET_FIELD(SWPxMSGCTL_REG
, 0, midx
) |
1808 SET_FIELD(SWPxMSGCTL_PART
, 0, ndev
->peers
[pidx
].part
);
1810 /* Lock the messages routing table of the specified register */
1811 spin_lock_irqsave(&ndev
->msg_locks
[midx
], irqflags
);
1812 /* Set the route and send the data */
1813 idt_sw_write(ndev
, partdata_tbl
[ndev
->part
].msgctl
[midx
], swpmsgctl
);
1814 idt_nt_write(ndev
, ntdata_tbl
.msgs
[midx
].out
, msg
);
1816 /* Unlock the messages routing table */
1817 spin_unlock_irqrestore(&ndev
->msg_locks
[midx
], irqflags
);
1819 /* Client driver shall check the status register */
1823 /*=============================================================================
1824 * 7. Temperature sensor operations
1826 * IDT PCIe-switch has an embedded temperature sensor, which can be used to
1827 * warn a user-space of possible chip overheating. Since workload temperature
1828 * can be different on different platforms, temperature thresholds as well as
1829 * general sensor settings must be setup in the framework of BIOS/EEPROM
1830 * initializations. It includes the actual sensor enabling as well.
1831 *=============================================================================
1835 * idt_read_temp() - read temperature from chip sensor
1836 * @ntb: NTB device context.
1837 * @val: OUT - integer value of temperature
1838 * @frac: OUT - fraction
1840 static void idt_read_temp(struct idt_ntb_dev
*ndev
, unsigned char *val
,
1841 unsigned char *frac
)
1845 /* Read the data from TEMP field of the TMPSTS register */
1846 data
= idt_sw_read(ndev
, IDT_SW_TMPSTS
);
1847 data
= GET_FIELD(TMPSTS_TEMP
, data
);
1848 /* TEMP field has one fractional bit and seven integer bits */
1850 *frac
= ((data
& 0x1) ? 5 : 0);
1854 * idt_temp_isr() - temperature sensor alarm events ISR
1855 * @ndev: IDT NTB hardware driver descriptor
1856 * @ntint_sts: NT-function interrupt status
1858 * It handles events of temperature crossing alarm thresholds. Since reading
1859 * of TMPALARM register clears it up, the function doesn't analyze the
1860 * read value, instead the current temperature value just warningly printed to
1862 * The method is called from PCIe ISR bottom-half routine.
1864 static void idt_temp_isr(struct idt_ntb_dev
*ndev
, u32 ntint_sts
)
1866 unsigned char val
, frac
;
1868 /* Read the current temperature value */
1869 idt_read_temp(ndev
, &val
, &frac
);
1871 /* Read the temperature alarm to clean the alarm status out */
1872 /*(void)idt_sw_read(ndev, IDT_SW_TMPALARM);*/
1874 /* Clean the corresponding interrupt bit */
1875 idt_nt_write(ndev
, IDT_NT_NTINTSTS
, IDT_NTINTSTS_TMPSENSOR
);
1877 dev_dbg(&ndev
->ntb
.pdev
->dev
,
1878 "Temp sensor IRQ detected %#08x", ntint_sts
);
1880 /* Print temperature value to log */
1881 dev_warn(&ndev
->ntb
.pdev
->dev
, "Temperature %hhu.%hhu", val
, frac
);
1884 /*=============================================================================
1885 * 8. ISRs related operations
1887 * IDT PCIe-switch has strangely developed IRQ system. There is just one
1888 * interrupt vector for doorbell and message registers. So the hardware driver
1889 * can't determine actual source of IRQ if, for example, message event happened
1890 * while any of unmasked doorbell is still set. The similar situation may be if
1891 * switch or temperature sensor events pop up. The difference is that SEVENT
1892 * and TMPSENSOR bits of NT interrupt status register can be cleaned by
1893 * IRQ handler so a next interrupt request won't have false handling of
1894 * corresponding events.
1895 * The hardware driver has only bottom-half handler of the IRQ, since if any
1896 * of events happened the device won't raise it again before the last one is
1897 * handled by clearing of corresponding NTINTSTS bit.
1898 *=============================================================================
1901 static irqreturn_t
idt_thread_isr(int irq
, void *devid
);
1904 * idt_init_isr() - initialize PCIe interrupt handler
1905 * @ndev: IDT NTB hardware driver descriptor
1907 * Return: zero on success, otherwise a negative error number.
1909 static int idt_init_isr(struct idt_ntb_dev
*ndev
)
1911 struct pci_dev
*pdev
= ndev
->ntb
.pdev
;
1915 /* Allocate just one interrupt vector for the ISR */
1916 ret
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_MSI
| PCI_IRQ_LEGACY
);
1918 dev_err(&pdev
->dev
, "Failed to allocate IRQ vector");
1922 /* Retrieve the IRQ vector */
1923 ret
= pci_irq_vector(pdev
, 0);
1925 dev_err(&pdev
->dev
, "Failed to get IRQ vector");
1926 goto err_free_vectors
;
1929 /* Set the IRQ handler */
1930 ret
= devm_request_threaded_irq(&pdev
->dev
, ret
, NULL
, idt_thread_isr
,
1931 IRQF_ONESHOT
, NTB_IRQNAME
, ndev
);
1933 dev_err(&pdev
->dev
, "Failed to set MSI IRQ handler, %d", ret
);
1934 goto err_free_vectors
;
1937 /* Unmask Message/Doorbell/SE/Temperature interrupts */
1938 ntint_mask
= idt_nt_read(ndev
, IDT_NT_NTINTMSK
) & ~IDT_NTINTMSK_ALL
;
1939 idt_nt_write(ndev
, IDT_NT_NTINTMSK
, ntint_mask
);
1941 /* From now on the interrupts are enabled */
1942 dev_dbg(&pdev
->dev
, "NTB interrupts initialized");
1947 pci_free_irq_vectors(pdev
);
1954 * idt_deinit_ist() - deinitialize PCIe interrupt handler
1955 * @ndev: IDT NTB hardware driver descriptor
1957 * Disable corresponding interrupts and free allocated IRQ vectors.
1959 static void idt_deinit_isr(struct idt_ntb_dev
*ndev
)
1961 struct pci_dev
*pdev
= ndev
->ntb
.pdev
;
1964 /* Mask interrupts back */
1965 ntint_mask
= idt_nt_read(ndev
, IDT_NT_NTINTMSK
) | IDT_NTINTMSK_ALL
;
1966 idt_nt_write(ndev
, IDT_NT_NTINTMSK
, ntint_mask
);
1968 /* Manually free IRQ otherwise PCI free irq vectors will fail */
1969 devm_free_irq(&pdev
->dev
, pci_irq_vector(pdev
, 0), ndev
);
1971 /* Free allocated IRQ vectors */
1972 pci_free_irq_vectors(pdev
);
1974 dev_dbg(&pdev
->dev
, "NTB interrupts deinitialized");
1978 * idt_thread_isr() - NT function interrupts handler
1980 * @devid: Custom buffer
1982 * It reads current NT interrupts state register and handles all the event
1984 * The method is bottom-half routine of actual default PCIe IRQ handler.
1986 static irqreturn_t
idt_thread_isr(int irq
, void *devid
)
1988 struct idt_ntb_dev
*ndev
= devid
;
1989 bool handled
= false;
1992 /* Read the NT interrupts status register */
1993 ntint_sts
= idt_nt_read(ndev
, IDT_NT_NTINTSTS
);
1995 /* Handle messaging interrupts */
1996 if (ntint_sts
& IDT_NTINTSTS_MSG
) {
1997 idt_msg_isr(ndev
, ntint_sts
);
2001 /* Handle doorbell interrupts */
2002 if (ntint_sts
& IDT_NTINTSTS_DBELL
) {
2003 idt_db_isr(ndev
, ntint_sts
);
2007 /* Handle switch event interrupts */
2008 if (ntint_sts
& IDT_NTINTSTS_SEVENT
) {
2009 idt_se_isr(ndev
, ntint_sts
);
2013 /* Handle temperature sensor interrupt */
2014 if (ntint_sts
& IDT_NTINTSTS_TMPSENSOR
) {
2015 idt_temp_isr(ndev
, ntint_sts
);
2019 dev_dbg(&ndev
->ntb
.pdev
->dev
, "IDT IRQs 0x%08x handled", ntint_sts
);
2021 return handled
? IRQ_HANDLED
: IRQ_NONE
;
2024 /*===========================================================================
2025 * 9. NTB hardware driver initialization
2026 *===========================================================================
2030 * NTB API operations
2032 static const struct ntb_dev_ops idt_ntb_ops
= {
2033 .port_number
= idt_ntb_port_number
,
2034 .peer_port_count
= idt_ntb_peer_port_count
,
2035 .peer_port_number
= idt_ntb_peer_port_number
,
2036 .peer_port_idx
= idt_ntb_peer_port_idx
,
2037 .link_is_up
= idt_ntb_link_is_up
,
2038 .link_enable
= idt_ntb_link_enable
,
2039 .link_disable
= idt_ntb_link_disable
,
2040 .mw_count
= idt_ntb_mw_count
,
2041 .mw_get_align
= idt_ntb_mw_get_align
,
2042 .peer_mw_count
= idt_ntb_peer_mw_count
,
2043 .peer_mw_get_addr
= idt_ntb_peer_mw_get_addr
,
2044 .peer_mw_set_trans
= idt_ntb_peer_mw_set_trans
,
2045 .peer_mw_clear_trans
= idt_ntb_peer_mw_clear_trans
,
2046 .db_valid_mask
= idt_ntb_db_valid_mask
,
2047 .db_read
= idt_ntb_db_read
,
2048 .db_clear
= idt_ntb_db_clear
,
2049 .db_read_mask
= idt_ntb_db_read_mask
,
2050 .db_set_mask
= idt_ntb_db_set_mask
,
2051 .db_clear_mask
= idt_ntb_db_clear_mask
,
2052 .peer_db_set
= idt_ntb_peer_db_set
,
2053 .msg_count
= idt_ntb_msg_count
,
2054 .msg_inbits
= idt_ntb_msg_inbits
,
2055 .msg_outbits
= idt_ntb_msg_outbits
,
2056 .msg_read_sts
= idt_ntb_msg_read_sts
,
2057 .msg_clear_sts
= idt_ntb_msg_clear_sts
,
2058 .msg_set_mask
= idt_ntb_msg_set_mask
,
2059 .msg_clear_mask
= idt_ntb_msg_clear_mask
,
2060 .msg_read
= idt_ntb_msg_read
,
2061 .msg_write
= idt_ntb_msg_write
2065 * idt_register_device() - register IDT NTB device
2066 * @ndev: IDT NTB hardware driver descriptor
2068 * Return: zero on success, otherwise a negative error number.
2070 static int idt_register_device(struct idt_ntb_dev
*ndev
)
2074 /* Initialize the rest of NTB device structure and register it */
2075 ndev
->ntb
.ops
= &idt_ntb_ops
;
2076 ndev
->ntb
.topo
= NTB_TOPO_PRI
;
2078 ret
= ntb_register_device(&ndev
->ntb
);
2080 dev_err(&ndev
->ntb
.pdev
->dev
, "Failed to register NTB device");
2084 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB device successfully registered");
2090 * idt_unregister_device() - unregister IDT NTB device
2091 * @ndev: IDT NTB hardware driver descriptor
2093 static void idt_unregister_device(struct idt_ntb_dev
*ndev
)
2095 /* Just unregister the NTB device */
2096 ntb_unregister_device(&ndev
->ntb
);
2098 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB device unregistered");
2101 /*=============================================================================
2102 * 10. DebugFS node initialization
2103 *=============================================================================
2106 static ssize_t
idt_dbgfs_info_read(struct file
*filp
, char __user
*ubuf
,
2107 size_t count
, loff_t
*offp
);
2110 * Driver DebugFS info file operations
2112 static const struct file_operations idt_dbgfs_info_ops
= {
2113 .owner
= THIS_MODULE
,
2114 .open
= simple_open
,
2115 .read
= idt_dbgfs_info_read
2119 * idt_dbgfs_info_read() - DebugFS read info node callback
2120 * @file: File node descriptor.
2121 * @ubuf: User-space buffer to put data to
2122 * @count: Size of the buffer
2123 * @offp: Offset within the buffer
2125 static ssize_t
idt_dbgfs_info_read(struct file
*filp
, char __user
*ubuf
,
2126 size_t count
, loff_t
*offp
)
2128 struct idt_ntb_dev
*ndev
= filp
->private_data
;
2129 unsigned char temp
, frac
, idx
, pidx
, cnt
;
2130 ssize_t ret
= 0, off
= 0;
2131 unsigned long irqflags
;
2132 enum ntb_speed speed
;
2133 enum ntb_width width
;
2138 /* Lets limit the buffer size the way the Intel/AMD drivers do */
2139 size
= min_t(size_t, count
, 0x1000U
);
2141 /* Allocate the memory for the buffer */
2142 strbuf
= kmalloc(size
, GFP_KERNEL
);
2146 /* Put the data into the string buffer */
2147 off
+= scnprintf(strbuf
+ off
, size
- off
,
2148 "\n\t\tIDT NTB device Information:\n\n");
2150 /* General local device configurations */
2151 off
+= scnprintf(strbuf
+ off
, size
- off
,
2152 "Local Port %hhu, Partition %hhu\n", ndev
->port
, ndev
->part
);
2154 /* Peer ports information */
2155 off
+= scnprintf(strbuf
+ off
, size
- off
, "Peers:\n");
2156 for (idx
= 0; idx
< ndev
->peer_cnt
; idx
++) {
2157 off
+= scnprintf(strbuf
+ off
, size
- off
,
2158 "\t%hhu. Port %hhu, Partition %hhu\n",
2159 idx
, ndev
->peers
[idx
].port
, ndev
->peers
[idx
].part
);
2163 data
= idt_ntb_link_is_up(&ndev
->ntb
, &speed
, &width
);
2164 off
+= scnprintf(strbuf
+ off
, size
- off
,
2165 "NTB link status\t- 0x%08x, ", data
);
2166 off
+= scnprintf(strbuf
+ off
, size
- off
, "PCIe Gen %d x%d lanes\n",
2169 /* Mapping table entries */
2170 off
+= scnprintf(strbuf
+ off
, size
- off
, "NTB Mapping Table:\n");
2171 for (idx
= 0; idx
< IDT_MTBL_ENTRY_CNT
; idx
++) {
2172 spin_lock_irqsave(&ndev
->mtbl_lock
, irqflags
);
2173 idt_nt_write(ndev
, IDT_NT_NTMTBLADDR
, idx
);
2174 data
= idt_nt_read(ndev
, IDT_NT_NTMTBLDATA
);
2175 spin_unlock_irqrestore(&ndev
->mtbl_lock
, irqflags
);
2177 /* Print valid entries only */
2178 if (data
& IDT_NTMTBLDATA_VALID
) {
2179 off
+= scnprintf(strbuf
+ off
, size
- off
,
2180 "\t%hhu. Partition %d, Requester ID 0x%04x\n",
2181 idx
, GET_FIELD(NTMTBLDATA_PART
, data
),
2182 GET_FIELD(NTMTBLDATA_REQID
, data
));
2185 off
+= scnprintf(strbuf
+ off
, size
- off
, "\n");
2187 /* Outbound memory windows information */
2188 off
+= scnprintf(strbuf
+ off
, size
- off
,
2189 "Outbound Memory Windows:\n");
2190 for (idx
= 0; idx
< ndev
->mw_cnt
; idx
+= cnt
) {
2191 data
= ndev
->mws
[idx
].type
;
2192 cnt
= idt_get_mw_count(data
);
2194 /* Print Memory Window information */
2195 if (data
== IDT_MW_DIR
)
2196 off
+= scnprintf(strbuf
+ off
, size
- off
,
2199 off
+= scnprintf(strbuf
+ off
, size
- off
,
2200 "\t%hhu-%hhu.\t", idx
, idx
+ cnt
- 1);
2202 off
+= scnprintf(strbuf
+ off
, size
- off
, "%s BAR%hhu, ",
2203 idt_get_mw_name(data
), ndev
->mws
[idx
].bar
);
2205 off
+= scnprintf(strbuf
+ off
, size
- off
,
2206 "Address align 0x%08llx, ", ndev
->mws
[idx
].addr_align
);
2208 off
+= scnprintf(strbuf
+ off
, size
- off
,
2209 "Size align 0x%08llx, Size max %llu\n",
2210 ndev
->mws
[idx
].size_align
, ndev
->mws
[idx
].size_max
);
2213 /* Inbound memory windows information */
2214 for (pidx
= 0; pidx
< ndev
->peer_cnt
; pidx
++) {
2215 off
+= scnprintf(strbuf
+ off
, size
- off
,
2216 "Inbound Memory Windows for peer %hhu (Port %hhu):\n",
2217 pidx
, ndev
->peers
[pidx
].port
);
2219 /* Print Memory Windows information */
2220 for (idx
= 0; idx
< ndev
->peers
[pidx
].mw_cnt
; idx
+= cnt
) {
2221 data
= ndev
->peers
[pidx
].mws
[idx
].type
;
2222 cnt
= idt_get_mw_count(data
);
2224 if (data
== IDT_MW_DIR
)
2225 off
+= scnprintf(strbuf
+ off
, size
- off
,
2228 off
+= scnprintf(strbuf
+ off
, size
- off
,
2229 "\t%hhu-%hhu.\t", idx
, idx
+ cnt
- 1);
2231 off
+= scnprintf(strbuf
+ off
, size
- off
,
2232 "%s BAR%hhu, ", idt_get_mw_name(data
),
2233 ndev
->peers
[pidx
].mws
[idx
].bar
);
2235 off
+= scnprintf(strbuf
+ off
, size
- off
,
2236 "Address align 0x%08llx, ",
2237 ndev
->peers
[pidx
].mws
[idx
].addr_align
);
2239 off
+= scnprintf(strbuf
+ off
, size
- off
,
2240 "Size align 0x%08llx, Size max %llu\n",
2241 ndev
->peers
[pidx
].mws
[idx
].size_align
,
2242 ndev
->peers
[pidx
].mws
[idx
].size_max
);
2245 off
+= scnprintf(strbuf
+ off
, size
- off
, "\n");
2247 /* Doorbell information */
2248 data
= idt_sw_read(ndev
, IDT_SW_GDBELLSTS
);
2249 off
+= scnprintf(strbuf
+ off
, size
- off
,
2250 "Global Doorbell state\t- 0x%08x\n", data
);
2251 data
= idt_ntb_db_read(&ndev
->ntb
);
2252 off
+= scnprintf(strbuf
+ off
, size
- off
,
2253 "Local Doorbell state\t- 0x%08x\n", data
);
2254 data
= idt_nt_read(ndev
, IDT_NT_INDBELLMSK
);
2255 off
+= scnprintf(strbuf
+ off
, size
- off
,
2256 "Local Doorbell mask\t- 0x%08x\n", data
);
2257 off
+= scnprintf(strbuf
+ off
, size
- off
, "\n");
2259 /* Messaging information */
2260 off
+= scnprintf(strbuf
+ off
, size
- off
,
2261 "Message event valid\t- 0x%08x\n", IDT_MSG_MASK
);
2262 data
= idt_ntb_msg_read_sts(&ndev
->ntb
);
2263 off
+= scnprintf(strbuf
+ off
, size
- off
,
2264 "Message event status\t- 0x%08x\n", data
);
2265 data
= idt_nt_read(ndev
, IDT_NT_MSGSTSMSK
);
2266 off
+= scnprintf(strbuf
+ off
, size
- off
,
2267 "Message event mask\t- 0x%08x\n", data
);
2268 off
+= scnprintf(strbuf
+ off
, size
- off
,
2270 for (idx
= 0; idx
< IDT_MSG_CNT
; idx
++) {
2272 (void)idt_ntb_msg_read(&ndev
->ntb
, idx
, &src
, &data
);
2273 off
+= scnprintf(strbuf
+ off
, size
- off
,
2274 "\t%hhu. 0x%08x from peer %hhu (Port %hhu)\n",
2275 idx
, data
, src
, ndev
->peers
[src
].port
);
2277 off
+= scnprintf(strbuf
+ off
, size
- off
, "\n");
2279 /* Current temperature */
2280 idt_read_temp(ndev
, &temp
, &frac
);
2281 off
+= scnprintf(strbuf
+ off
, size
- off
,
2282 "Switch temperature\t\t- %hhu.%hhuC\n", temp
, frac
);
2284 /* Copy the buffer to the User Space */
2285 ret
= simple_read_from_buffer(ubuf
, count
, offp
, strbuf
, off
);
2292 * idt_init_dbgfs() - initialize DebugFS node
2293 * @ndev: IDT NTB hardware driver descriptor
2295 * Return: zero on success, otherwise a negative error number.
2297 static int idt_init_dbgfs(struct idt_ntb_dev
*ndev
)
2301 /* If the top directory is not created then do nothing */
2302 if (IS_ERR_OR_NULL(dbgfs_topdir
)) {
2303 dev_info(&ndev
->ntb
.pdev
->dev
, "Top DebugFS directory absent");
2304 return PTR_ERR(dbgfs_topdir
);
2307 /* Create the info file node */
2308 snprintf(devname
, 64, "info:%s", pci_name(ndev
->ntb
.pdev
));
2309 ndev
->dbgfs_info
= debugfs_create_file(devname
, 0400, dbgfs_topdir
,
2310 ndev
, &idt_dbgfs_info_ops
);
2311 if (IS_ERR(ndev
->dbgfs_info
)) {
2312 dev_dbg(&ndev
->ntb
.pdev
->dev
, "Failed to create DebugFS node");
2313 return PTR_ERR(ndev
->dbgfs_info
);
2316 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB device DebugFS node created");
2322 * idt_deinit_dbgfs() - deinitialize DebugFS node
2323 * @ndev: IDT NTB hardware driver descriptor
2325 * Just discard the info node from DebugFS
2327 static void idt_deinit_dbgfs(struct idt_ntb_dev
*ndev
)
2329 debugfs_remove(ndev
->dbgfs_info
);
2331 dev_dbg(&ndev
->ntb
.pdev
->dev
, "NTB device DebugFS node discarded");
2334 /*=============================================================================
2335 * 11. Basic PCIe device initialization
2336 *=============================================================================
2340 * idt_check_setup() - Check whether the IDT PCIe-swtich is properly
2342 * @pdev: Pointer to the PCI device descriptor
2344 * Return: zero on success, otherwise a negative error number.
2346 static int idt_check_setup(struct pci_dev
*pdev
)
2351 /* Read the BARSETUP0 */
2352 ret
= pci_read_config_dword(pdev
, IDT_NT_BARSETUP0
, &data
);
2355 "Failed to read BARSETUP0 config register");
2359 /* Check whether the BAR0 register is enabled to be of config space */
2360 if (!(data
& IDT_BARSETUP_EN
) || !(data
& IDT_BARSETUP_MODE_CFG
)) {
2361 dev_err(&pdev
->dev
, "BAR0 doesn't map config space");
2365 /* Configuration space BAR0 must have certain size */
2366 if ((data
& IDT_BARSETUP_SIZE_MASK
) != IDT_BARSETUP_SIZE_CFG
) {
2367 dev_err(&pdev
->dev
, "Invalid size of config space");
2371 dev_dbg(&pdev
->dev
, "NTB device pre-initialized correctly");
2377 * Create the IDT PCIe-switch driver descriptor
2378 * @pdev: Pointer to the PCI device descriptor
2379 * @id: IDT PCIe-device configuration
2381 * It just allocates a memory for IDT PCIe-switch device structure and
2382 * initializes some commonly used fields.
2384 * No need of release method, since managed device resource is used for
2385 * memory allocation.
2387 * Return: pointer to the descriptor, otherwise a negative error number.
2389 static struct idt_ntb_dev
*idt_create_dev(struct pci_dev
*pdev
,
2390 const struct pci_device_id
*id
)
2392 struct idt_ntb_dev
*ndev
;
2394 /* Allocate memory for the IDT PCIe-device descriptor */
2395 ndev
= devm_kzalloc(&pdev
->dev
, sizeof(*ndev
), GFP_KERNEL
);
2397 dev_err(&pdev
->dev
, "Memory allocation failed for descriptor");
2398 return ERR_PTR(-ENOMEM
);
2401 /* Save the IDT PCIe-switch ports configuration */
2402 ndev
->swcfg
= (struct idt_89hpes_cfg
*)id
->driver_data
;
2403 /* Save the PCI-device pointer inside the NTB device structure */
2404 ndev
->ntb
.pdev
= pdev
;
2406 /* Initialize spin locker of Doorbell, Message and GASA registers */
2407 spin_lock_init(&ndev
->db_mask_lock
);
2408 spin_lock_init(&ndev
->msg_mask_lock
);
2409 spin_lock_init(&ndev
->gasa_lock
);
2411 dev_info(&pdev
->dev
, "IDT %s discovered", ndev
->swcfg
->name
);
2413 dev_dbg(&pdev
->dev
, "NTB device descriptor created");
2419 * idt_init_pci() - initialize the basic PCI-related subsystem
2420 * @ndev: Pointer to the IDT PCIe-switch driver descriptor
2422 * Managed device resources will be freed automatically in case of failure or
2423 * driver detachment.
2425 * Return: zero on success, otherwise negative error number.
2427 static int idt_init_pci(struct idt_ntb_dev
*ndev
)
2429 struct pci_dev
*pdev
= ndev
->ntb
.pdev
;
2432 /* Initialize the bit mask of DMA */
2433 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2435 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2437 dev_err(&pdev
->dev
, "Failed to set DMA bit mask\n");
2440 dev_warn(&pdev
->dev
, "Cannot set DMA highmem bit mask\n");
2442 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2444 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2447 "Failed to set consistent DMA bit mask\n");
2450 dev_warn(&pdev
->dev
,
2451 "Cannot set consistent DMA highmem bit mask\n");
2455 * Enable the device advanced error reporting. It's not critical to
2456 * have AER disabled in the kernel.
2458 ret
= pci_enable_pcie_error_reporting(pdev
);
2460 dev_warn(&pdev
->dev
, "PCIe AER capability disabled\n");
2461 else /* Cleanup uncorrectable error status before getting to init */
2462 pci_cleanup_aer_uncorrect_error_status(pdev
);
2464 /* First enable the PCI device */
2465 ret
= pcim_enable_device(pdev
);
2467 dev_err(&pdev
->dev
, "Failed to enable PCIe device\n");
2468 goto err_disable_aer
;
2472 * Enable the bus mastering, which effectively enables MSI IRQs and
2473 * Request TLPs translation
2475 pci_set_master(pdev
);
2477 /* Request all BARs resources and map BAR0 only */
2478 ret
= pcim_iomap_regions_request_all(pdev
, 1, NTB_NAME
);
2480 dev_err(&pdev
->dev
, "Failed to request resources\n");
2481 goto err_clear_master
;
2484 /* Retrieve virtual address of BAR0 - PCI configuration space */
2485 ndev
->cfgspc
= pcim_iomap_table(pdev
)[0];
2487 /* Put the IDT driver data pointer to the PCI-device private pointer */
2488 pci_set_drvdata(pdev
, ndev
);
2490 dev_dbg(&pdev
->dev
, "NT-function PCIe interface initialized");
2495 pci_clear_master(pdev
);
2497 (void)pci_disable_pcie_error_reporting(pdev
);
2503 * idt_deinit_pci() - deinitialize the basic PCI-related subsystem
2504 * @ndev: Pointer to the IDT PCIe-switch driver descriptor
2506 * Managed resources will be freed on the driver detachment
2508 static void idt_deinit_pci(struct idt_ntb_dev
*ndev
)
2510 struct pci_dev
*pdev
= ndev
->ntb
.pdev
;
2512 /* Clean up the PCI-device private data pointer */
2513 pci_set_drvdata(pdev
, NULL
);
2515 /* Clear the bus master disabling the Request TLPs translation */
2516 pci_clear_master(pdev
);
2518 /* Disable the AER capability */
2519 (void)pci_disable_pcie_error_reporting(pdev
);
2521 dev_dbg(&pdev
->dev
, "NT-function PCIe interface cleared");
2524 /*===========================================================================
2525 * 12. PCI bus callback functions
2526 *===========================================================================
2530 * idt_pci_probe() - PCI device probe callback
2531 * @pdev: Pointer to PCI device structure
2532 * @id: PCIe device custom descriptor
2534 * Return: zero on success, otherwise negative error number
2536 static int idt_pci_probe(struct pci_dev
*pdev
,
2537 const struct pci_device_id
*id
)
2539 struct idt_ntb_dev
*ndev
;
2542 /* Check whether IDT PCIe-switch is properly pre-initialized */
2543 ret
= idt_check_setup(pdev
);
2547 /* Allocate the memory for IDT NTB device data */
2548 ndev
= idt_create_dev(pdev
, id
);
2549 if (IS_ERR_OR_NULL(ndev
))
2550 return PTR_ERR(ndev
);
2552 /* Initialize the basic PCI subsystem of the device */
2553 ret
= idt_init_pci(ndev
);
2557 /* Scan ports of the IDT PCIe-switch */
2558 (void)idt_scan_ports(ndev
);
2560 /* Initialize NTB link events subsystem */
2561 idt_init_link(ndev
);
2563 /* Initialize MWs subsystem */
2564 ret
= idt_init_mws(ndev
);
2566 goto err_deinit_link
;
2568 /* Initialize Messaging subsystem */
2571 /* Initialize IDT interrupts handler */
2572 ret
= idt_init_isr(ndev
);
2574 goto err_deinit_link
;
2576 /* Register IDT NTB devices on the NTB bus */
2577 ret
= idt_register_device(ndev
);
2579 goto err_deinit_isr
;
2581 /* Initialize DebugFS info node */
2582 (void)idt_init_dbgfs(ndev
);
2584 /* IDT PCIe-switch NTB driver is finally initialized */
2585 dev_info(&pdev
->dev
, "IDT NTB device is ready");
2587 /* May the force be with us... */
2591 idt_deinit_isr(ndev
);
2593 idt_deinit_link(ndev
);
2594 idt_deinit_pci(ndev
);
2600 * idt_pci_probe() - PCI device remove callback
2601 * @pdev: Pointer to PCI device structure
2603 static void idt_pci_remove(struct pci_dev
*pdev
)
2605 struct idt_ntb_dev
*ndev
= pci_get_drvdata(pdev
);
2607 /* Deinit the DebugFS node */
2608 idt_deinit_dbgfs(ndev
);
2610 /* Unregister NTB device */
2611 idt_unregister_device(ndev
);
2613 /* Stop the interrupts handling */
2614 idt_deinit_isr(ndev
);
2616 /* Deinitialize link event subsystem */
2617 idt_deinit_link(ndev
);
2619 /* Deinit basic PCI subsystem */
2620 idt_deinit_pci(ndev
);
2622 /* IDT PCIe-switch NTB driver is finally initialized */
2623 dev_info(&pdev
->dev
, "IDT NTB device is removed");
2629 * IDT PCIe-switch models ports configuration structures
2631 static const struct idt_89hpes_cfg idt_89hpes24nt6ag2_config
= {
2632 .name
= "89HPES24NT6AG2",
2633 .port_cnt
= 6, .ports
= {0, 2, 4, 6, 8, 12}
2635 static const struct idt_89hpes_cfg idt_89hpes32nt8ag2_config
= {
2636 .name
= "89HPES32NT8AG2",
2637 .port_cnt
= 8, .ports
= {0, 2, 4, 6, 8, 12, 16, 20}
2639 static const struct idt_89hpes_cfg idt_89hpes32nt8bg2_config
= {
2640 .name
= "89HPES32NT8BG2",
2641 .port_cnt
= 8, .ports
= {0, 2, 4, 6, 8, 12, 16, 20}
2643 static const struct idt_89hpes_cfg idt_89hpes12nt12g2_config
= {
2644 .name
= "89HPES12NT12G2",
2645 .port_cnt
= 3, .ports
= {0, 8, 16}
2647 static const struct idt_89hpes_cfg idt_89hpes16nt16g2_config
= {
2648 .name
= "89HPES16NT16G2",
2649 .port_cnt
= 4, .ports
= {0, 8, 12, 16}
2651 static const struct idt_89hpes_cfg idt_89hpes24nt24g2_config
= {
2652 .name
= "89HPES24NT24G2",
2653 .port_cnt
= 8, .ports
= {0, 2, 4, 6, 8, 12, 16, 20}
2655 static const struct idt_89hpes_cfg idt_89hpes32nt24ag2_config
= {
2656 .name
= "89HPES32NT24AG2",
2657 .port_cnt
= 8, .ports
= {0, 2, 4, 6, 8, 12, 16, 20}
2659 static const struct idt_89hpes_cfg idt_89hpes32nt24bg2_config
= {
2660 .name
= "89HPES32NT24BG2",
2661 .port_cnt
= 8, .ports
= {0, 2, 4, 6, 8, 12, 16, 20}
2665 * PCI-ids table of the supported IDT PCIe-switch devices
2667 static const struct pci_device_id idt_pci_tbl
[] = {
2668 {IDT_PCI_DEVICE_IDS(89HPES24NT6AG2
, idt_89hpes24nt6ag2_config
)},
2669 {IDT_PCI_DEVICE_IDS(89HPES32NT8AG2
, idt_89hpes32nt8ag2_config
)},
2670 {IDT_PCI_DEVICE_IDS(89HPES32NT8BG2
, idt_89hpes32nt8bg2_config
)},
2671 {IDT_PCI_DEVICE_IDS(89HPES12NT12G2
, idt_89hpes12nt12g2_config
)},
2672 {IDT_PCI_DEVICE_IDS(89HPES16NT16G2
, idt_89hpes16nt16g2_config
)},
2673 {IDT_PCI_DEVICE_IDS(89HPES24NT24G2
, idt_89hpes24nt24g2_config
)},
2674 {IDT_PCI_DEVICE_IDS(89HPES32NT24AG2
, idt_89hpes32nt24ag2_config
)},
2675 {IDT_PCI_DEVICE_IDS(89HPES32NT24BG2
, idt_89hpes32nt24bg2_config
)},
2678 MODULE_DEVICE_TABLE(pci
, idt_pci_tbl
);
2681 * IDT PCIe-switch NT-function device driver structure definition
2683 static struct pci_driver idt_pci_driver
= {
2684 .name
= KBUILD_MODNAME
,
2685 .probe
= idt_pci_probe
,
2686 .remove
= idt_pci_remove
,
2687 .id_table
= idt_pci_tbl
,
2690 static int __init
idt_pci_driver_init(void)
2692 pr_info("%s %s\n", NTB_DESC
, NTB_VER
);
2694 /* Create the top DebugFS directory if the FS is initialized */
2695 if (debugfs_initialized())
2696 dbgfs_topdir
= debugfs_create_dir(KBUILD_MODNAME
, NULL
);
2698 /* Register the NTB hardware driver to handle the PCI device */
2699 return pci_register_driver(&idt_pci_driver
);
2701 module_init(idt_pci_driver_init
);
2703 static void __exit
idt_pci_driver_exit(void)
2705 /* Unregister the NTB hardware driver */
2706 pci_unregister_driver(&idt_pci_driver
);
2708 /* Discard the top DebugFS directory */
2709 debugfs_remove_recursive(dbgfs_topdir
);
2711 module_exit(idt_pci_driver_exit
);