2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/blk-mq-pci.h>
19 #include <linux/dmi.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/once.h>
27 #include <linux/pci.h>
28 #include <linux/t10-pi.h>
29 #include <linux/types.h>
30 #include <linux/io-64-nonatomic-lo-hi.h>
31 #include <linux/sed-opal.h>
32 #include <linux/suspend.h>
36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41 static int use_threaded_interrupts
;
42 module_param(use_threaded_interrupts
, int, 0);
44 static bool use_cmb_sqes
= true;
45 module_param(use_cmb_sqes
, bool, 0644);
46 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
48 static unsigned int max_host_mem_size_mb
= 128;
49 module_param(max_host_mem_size_mb
, uint
, 0444);
50 MODULE_PARM_DESC(max_host_mem_size_mb
,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
53 static unsigned int sgl_threshold
= SZ_32K
;
54 module_param(sgl_threshold
, uint
, 0644);
55 MODULE_PARM_DESC(sgl_threshold
,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
59 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
60 static const struct kernel_param_ops io_queue_depth_ops
= {
61 .set
= io_queue_depth_set
,
65 static int io_queue_depth
= 1024;
66 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
67 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
72 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
73 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue
**queues
;
80 struct blk_mq_tag_set tagset
;
81 struct blk_mq_tag_set admin_tagset
;
84 struct dma_pool
*prp_page_pool
;
85 struct dma_pool
*prp_small_pool
;
86 unsigned online_queues
;
91 unsigned long bar_mapped_size
;
92 struct work_struct remove_work
;
93 struct mutex shutdown_lock
;
96 pci_bus_addr_t cmb_bus_addr
;
100 struct nvme_ctrl ctrl
;
101 struct completion ioq_wait
;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr
;
107 dma_addr_t dbbuf_eis_dma_addr
;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs
;
112 dma_addr_t host_mem_descs_dma
;
113 struct nvme_host_mem_buf_desc
*host_mem_descs
;
114 void **host_mem_desc_bufs
;
117 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
121 ret
= kstrtoint(val
, 10, &n
);
122 if (ret
!= 0 || n
< 2)
125 return param_set_int(val
, kp
);
128 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
130 return qid
* 2 * stride
;
133 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
135 return (qid
* 2 + 1) * stride
;
138 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
140 return container_of(ctrl
, struct nvme_dev
, ctrl
);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device
*q_dmadev
;
149 struct nvme_dev
*dev
;
151 struct nvme_command
*sq_cmds
;
152 struct nvme_command __iomem
*sq_cmds_io
;
153 volatile struct nvme_completion
*cqes
;
154 struct blk_mq_tags
**tags
;
155 dma_addr_t sq_dma_addr
;
156 dma_addr_t cq_dma_addr
;
172 * The nvme_iod describes the data in an I/O, including the list of PRP
173 * entries. You can't see it in this data structure because C doesn't let
174 * me express that. Use nvme_init_iod to ensure there's enough space
175 * allocated to store the PRP list.
178 struct nvme_request req
;
179 struct nvme_queue
*nvmeq
;
182 int npages
; /* In the PRP list. 0 means small pool in use */
183 int nents
; /* Used in scatterlist */
184 int length
; /* Of data, in bytes */
185 dma_addr_t first_dma
;
186 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
187 struct scatterlist
*sg
;
188 struct scatterlist inline_sg
[0];
192 * Check we didin't inadvertently grow the command struct
194 static inline void _nvme_check_size(void)
196 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
206 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
208 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
211 static inline unsigned int nvme_dbbuf_size(u32 stride
)
213 return ((num_possible_cpus() + 1) * 8 * stride
);
216 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
218 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
223 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
224 &dev
->dbbuf_dbs_dma_addr
,
228 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
229 &dev
->dbbuf_eis_dma_addr
,
231 if (!dev
->dbbuf_eis
) {
232 dma_free_coherent(dev
->dev
, mem_size
,
233 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
234 dev
->dbbuf_dbs
= NULL
;
241 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
243 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
245 if (dev
->dbbuf_dbs
) {
246 dma_free_coherent(dev
->dev
, mem_size
,
247 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
248 dev
->dbbuf_dbs
= NULL
;
250 if (dev
->dbbuf_eis
) {
251 dma_free_coherent(dev
->dev
, mem_size
,
252 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
253 dev
->dbbuf_eis
= NULL
;
257 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
258 struct nvme_queue
*nvmeq
, int qid
)
260 if (!dev
->dbbuf_dbs
|| !qid
)
263 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
264 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
265 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
266 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
269 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
271 struct nvme_command c
;
276 memset(&c
, 0, sizeof(c
));
277 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
278 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
279 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
281 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
282 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
283 /* Free memory and continue on */
284 nvme_dbbuf_dma_free(dev
);
288 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
290 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
293 /* Update dbbuf and return true if an MMIO is required */
294 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
295 volatile u32
*dbbuf_ei
)
301 * Ensure that the queue is written before updating
302 * the doorbell in memory
306 old_value
= *dbbuf_db
;
310 * Ensure that the doorbell is updated before reading the event
311 * index from memory. The controller needs to provide similar
312 * ordering to ensure the envent index is updated before reading
317 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
325 * Max size of iod being embedded in the request payload
327 #define NVME_INT_PAGES 2
328 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
331 * Will slightly overestimate the number of pages needed. This is OK
332 * as it only leads to a small amount of wasted memory for the lifetime of
335 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
337 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
338 dev
->ctrl
.page_size
);
339 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
343 * Calculates the number of pages needed for the SGL segments. For example a 4k
344 * page can accommodate 256 SGL descriptors.
346 static int nvme_pci_npages_sgl(unsigned int num_seg
)
348 return DIV_ROUND_UP(num_seg
* sizeof(struct nvme_sgl_desc
), PAGE_SIZE
);
351 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev
*dev
,
352 unsigned int size
, unsigned int nseg
, bool use_sgl
)
357 alloc_size
= sizeof(__le64
*) * nvme_pci_npages_sgl(nseg
);
359 alloc_size
= sizeof(__le64
*) * nvme_npages(size
, dev
);
361 return alloc_size
+ sizeof(struct scatterlist
) * nseg
;
364 static unsigned int nvme_pci_cmd_size(struct nvme_dev
*dev
, bool use_sgl
)
366 unsigned int alloc_size
= nvme_pci_iod_alloc_size(dev
,
367 NVME_INT_BYTES(dev
), NVME_INT_PAGES
,
370 return sizeof(struct nvme_iod
) + alloc_size
;
373 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
374 unsigned int hctx_idx
)
376 struct nvme_dev
*dev
= data
;
377 struct nvme_queue
*nvmeq
= dev
->queues
[0];
379 WARN_ON(hctx_idx
!= 0);
380 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
381 WARN_ON(nvmeq
->tags
);
383 hctx
->driver_data
= nvmeq
;
384 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
388 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
390 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
395 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
396 unsigned int hctx_idx
)
398 struct nvme_dev
*dev
= data
;
399 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
402 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
404 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
405 hctx
->driver_data
= nvmeq
;
409 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
410 unsigned int hctx_idx
, unsigned int numa_node
)
412 struct nvme_dev
*dev
= set
->driver_data
;
413 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
414 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
415 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
422 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
424 struct nvme_dev
*dev
= set
->driver_data
;
426 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
430 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
431 * @nvmeq: The queue to use
432 * @cmd: The command to send
434 * Safe to use from interrupt context
436 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
437 struct nvme_command
*cmd
)
439 u16 tail
= nvmeq
->sq_tail
;
441 if (nvmeq
->sq_cmds_io
)
442 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
444 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
446 if (++tail
== nvmeq
->q_depth
)
448 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
450 writel(tail
, nvmeq
->q_db
);
451 nvmeq
->sq_tail
= tail
;
454 static void **nvme_pci_iod_list(struct request
*req
)
456 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
457 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
460 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
462 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
463 int nseg
= blk_rq_nr_phys_segments(req
);
464 unsigned int avg_seg_size
;
469 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
471 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
473 if (!iod
->nvmeq
->qid
)
475 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
480 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
482 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
483 int nseg
= blk_rq_nr_phys_segments(rq
);
484 unsigned int size
= blk_rq_payload_bytes(rq
);
486 iod
->use_sgl
= nvme_pci_use_sgls(dev
, rq
);
488 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
489 size_t alloc_size
= nvme_pci_iod_alloc_size(dev
, size
, nseg
,
492 iod
->sg
= kmalloc(alloc_size
, GFP_ATOMIC
);
494 return BLK_STS_RESOURCE
;
496 iod
->sg
= iod
->inline_sg
;
507 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
509 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
510 const int last_prp
= dev
->ctrl
.page_size
/ sizeof(__le64
) - 1;
511 dma_addr_t dma_addr
= iod
->first_dma
, next_dma_addr
;
515 if (iod
->npages
== 0)
516 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
519 for (i
= 0; i
< iod
->npages
; i
++) {
520 void *addr
= nvme_pci_iod_list(req
)[i
];
523 struct nvme_sgl_desc
*sg_list
= addr
;
526 le64_to_cpu((sg_list
[SGES_PER_PAGE
- 1]).addr
);
528 __le64
*prp_list
= addr
;
530 next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
533 dma_pool_free(dev
->prp_page_pool
, addr
, dma_addr
);
534 dma_addr
= next_dma_addr
;
537 if (iod
->sg
!= iod
->inline_sg
)
541 #ifdef CONFIG_BLK_DEV_INTEGRITY
542 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
544 if (be32_to_cpu(pi
->ref_tag
) == v
)
545 pi
->ref_tag
= cpu_to_be32(p
);
548 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
550 if (be32_to_cpu(pi
->ref_tag
) == p
)
551 pi
->ref_tag
= cpu_to_be32(v
);
555 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
557 * The virtual start sector is the one that was originally submitted by the
558 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
559 * start sector may be different. Remap protection information to match the
560 * physical LBA on writes, and back to the original seed on reads.
562 * Type 0 and 3 do not have a ref tag, so no remapping required.
564 static void nvme_dif_remap(struct request
*req
,
565 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
567 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
568 struct bio_integrity_payload
*bip
;
569 struct t10_pi_tuple
*pi
;
571 u32 i
, nlb
, ts
, phys
, virt
;
573 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
576 bip
= bio_integrity(req
->bio
);
580 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
583 virt
= bip_get_seed(bip
);
584 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
585 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
586 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
588 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
589 pi
= (struct t10_pi_tuple
*)p
;
590 dif_swap(phys
, virt
, pi
);
595 #else /* CONFIG_BLK_DEV_INTEGRITY */
596 static void nvme_dif_remap(struct request
*req
,
597 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
600 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
603 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
608 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
611 struct scatterlist
*sg
;
613 for_each_sg(sgl
, sg
, nents
, i
) {
614 dma_addr_t phys
= sg_phys(sg
);
615 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
616 "dma_address:%pad dma_length:%d\n",
617 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
622 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
623 struct request
*req
, struct nvme_rw_command
*cmnd
)
625 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
626 struct dma_pool
*pool
;
627 int length
= blk_rq_payload_bytes(req
);
628 struct scatterlist
*sg
= iod
->sg
;
629 int dma_len
= sg_dma_len(sg
);
630 u64 dma_addr
= sg_dma_address(sg
);
631 u32 page_size
= dev
->ctrl
.page_size
;
632 int offset
= dma_addr
& (page_size
- 1);
634 void **list
= nvme_pci_iod_list(req
);
638 length
-= (page_size
- offset
);
644 dma_len
-= (page_size
- offset
);
646 dma_addr
+= (page_size
- offset
);
649 dma_addr
= sg_dma_address(sg
);
650 dma_len
= sg_dma_len(sg
);
653 if (length
<= page_size
) {
654 iod
->first_dma
= dma_addr
;
658 nprps
= DIV_ROUND_UP(length
, page_size
);
659 if (nprps
<= (256 / 8)) {
660 pool
= dev
->prp_small_pool
;
663 pool
= dev
->prp_page_pool
;
667 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
669 iod
->first_dma
= dma_addr
;
671 return BLK_STS_RESOURCE
;
674 iod
->first_dma
= prp_dma
;
677 if (i
== page_size
>> 3) {
678 __le64
*old_prp_list
= prp_list
;
679 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
681 return BLK_STS_RESOURCE
;
682 list
[iod
->npages
++] = prp_list
;
683 prp_list
[0] = old_prp_list
[i
- 1];
684 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
687 prp_list
[i
++] = cpu_to_le64(dma_addr
);
688 dma_len
-= page_size
;
689 dma_addr
+= page_size
;
695 if (unlikely(dma_len
< 0))
698 dma_addr
= sg_dma_address(sg
);
699 dma_len
= sg_dma_len(sg
);
703 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
704 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
709 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
710 "Invalid SGL for payload:%d nents:%d\n",
711 blk_rq_payload_bytes(req
), iod
->nents
);
712 return BLK_STS_IOERR
;
715 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
716 struct scatterlist
*sg
)
718 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
719 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
720 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
723 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
724 dma_addr_t dma_addr
, int entries
)
726 sge
->addr
= cpu_to_le64(dma_addr
);
727 if (entries
< SGES_PER_PAGE
) {
728 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
729 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
731 sge
->length
= cpu_to_le32(PAGE_SIZE
);
732 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
736 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
737 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
739 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
740 struct dma_pool
*pool
;
741 struct nvme_sgl_desc
*sg_list
;
742 struct scatterlist
*sg
= iod
->sg
;
746 /* setting the transfer type as SGL */
747 cmd
->flags
= NVME_CMD_SGL_METABUF
;
750 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
754 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
755 pool
= dev
->prp_small_pool
;
758 pool
= dev
->prp_page_pool
;
762 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
765 return BLK_STS_RESOURCE
;
768 nvme_pci_iod_list(req
)[0] = sg_list
;
769 iod
->first_dma
= sgl_dma
;
771 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
774 if (i
== SGES_PER_PAGE
) {
775 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
776 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
778 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
780 return BLK_STS_RESOURCE
;
783 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
784 sg_list
[i
++] = *link
;
785 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
788 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
790 } while (--entries
> 0);
795 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
796 struct nvme_command
*cmnd
)
798 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
799 struct request_queue
*q
= req
->q
;
800 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
801 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
802 blk_status_t ret
= BLK_STS_IOERR
;
805 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
806 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
810 ret
= BLK_STS_RESOURCE
;
811 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
817 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
819 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
821 if (ret
!= BLK_STS_OK
)
825 if (blk_integrity_rq(req
)) {
826 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
829 sg_init_table(&iod
->meta_sg
, 1);
830 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
833 if (req_op(req
) == REQ_OP_WRITE
)
834 nvme_dif_remap(req
, nvme_dif_prep
);
836 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
840 if (blk_integrity_rq(req
))
841 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
845 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
850 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
852 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
853 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
854 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
857 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
858 if (blk_integrity_rq(req
)) {
859 if (req_op(req
) == REQ_OP_READ
)
860 nvme_dif_remap(req
, nvme_dif_complete
);
861 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
865 nvme_cleanup_cmd(req
);
866 nvme_free_iod(dev
, req
);
870 * NOTE: ns is NULL when called on the admin queue.
872 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
873 const struct blk_mq_queue_data
*bd
)
875 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
876 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
877 struct nvme_dev
*dev
= nvmeq
->dev
;
878 struct request
*req
= bd
->rq
;
879 struct nvme_command cmnd
;
882 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
886 ret
= nvme_init_iod(req
, dev
);
890 if (blk_rq_nr_phys_segments(req
)) {
891 ret
= nvme_map_data(dev
, req
, &cmnd
);
893 goto out_cleanup_iod
;
896 blk_mq_start_request(req
);
898 spin_lock_irq(&nvmeq
->q_lock
);
899 if (unlikely(nvmeq
->cq_vector
< 0)) {
901 spin_unlock_irq(&nvmeq
->q_lock
);
902 goto out_cleanup_iod
;
904 __nvme_submit_cmd(nvmeq
, &cmnd
);
905 nvme_process_cq(nvmeq
);
906 spin_unlock_irq(&nvmeq
->q_lock
);
909 nvme_free_iod(dev
, req
);
911 nvme_cleanup_cmd(req
);
915 static void nvme_pci_complete_rq(struct request
*req
)
917 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
919 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
920 nvme_complete_rq(req
);
923 /* We read the CQE phase first to check if the rest of the entry is valid */
924 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
927 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
930 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
932 u16 head
= nvmeq
->cq_head
;
934 if (likely(nvmeq
->cq_vector
>= 0)) {
935 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
937 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
941 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
,
942 struct nvme_completion
*cqe
)
946 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
947 dev_warn(nvmeq
->dev
->ctrl
.device
,
948 "invalid id %d completed on queue %d\n",
949 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
954 * AEN requests are special as they don't time out and can
955 * survive any kind of queue freeze and often don't respond to
956 * aborts. We don't even bother to allocate a struct request
957 * for them but rather special case them here.
959 if (unlikely(nvmeq
->qid
== 0 &&
960 cqe
->command_id
>= NVME_AQ_BLK_MQ_DEPTH
)) {
961 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
962 cqe
->status
, &cqe
->result
);
967 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
968 nvme_end_request(req
, cqe
->status
, cqe
->result
);
971 static inline bool nvme_read_cqe(struct nvme_queue
*nvmeq
,
972 struct nvme_completion
*cqe
)
974 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
975 *cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
977 if (nvmeq
->cq_head
== nvmeq
->q_depth
- 1) {
979 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
988 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
990 struct nvme_completion cqe
;
993 while (nvme_read_cqe(nvmeq
, &cqe
)) {
994 nvme_handle_cqe(nvmeq
, &cqe
);
999 nvme_ring_cq_doorbell(nvmeq
);
1002 static irqreturn_t
nvme_irq(int irq
, void *data
)
1005 struct nvme_queue
*nvmeq
= data
;
1006 spin_lock(&nvmeq
->q_lock
);
1007 nvme_process_cq(nvmeq
);
1008 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
1009 nvmeq
->cqe_seen
= 0;
1010 spin_unlock(&nvmeq
->q_lock
);
1014 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
1016 struct nvme_queue
*nvmeq
= data
;
1017 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
1018 return IRQ_WAKE_THREAD
;
1022 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
1024 struct nvme_completion cqe
;
1025 int found
= 0, consumed
= 0;
1027 if (!nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
1030 spin_lock_irq(&nvmeq
->q_lock
);
1031 while (nvme_read_cqe(nvmeq
, &cqe
)) {
1032 nvme_handle_cqe(nvmeq
, &cqe
);
1035 if (tag
== cqe
.command_id
) {
1042 nvme_ring_cq_doorbell(nvmeq
);
1043 spin_unlock_irq(&nvmeq
->q_lock
);
1048 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
1050 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
1052 return __nvme_poll(nvmeq
, tag
);
1055 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
1057 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1058 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1059 struct nvme_command c
;
1061 memset(&c
, 0, sizeof(c
));
1062 c
.common
.opcode
= nvme_admin_async_event
;
1063 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1065 spin_lock_irq(&nvmeq
->q_lock
);
1066 __nvme_submit_cmd(nvmeq
, &c
);
1067 spin_unlock_irq(&nvmeq
->q_lock
);
1070 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1072 struct nvme_command c
;
1074 memset(&c
, 0, sizeof(c
));
1075 c
.delete_queue
.opcode
= opcode
;
1076 c
.delete_queue
.qid
= cpu_to_le16(id
);
1078 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1081 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1082 struct nvme_queue
*nvmeq
)
1084 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1085 struct nvme_command c
;
1086 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
1089 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1090 * set. Since URGENT priority is zeroes, it makes all queues
1093 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1094 flags
|= NVME_SQ_PRIO_MEDIUM
;
1097 * Note: we (ab)use the fact that the prp fields survive if no data
1098 * is attached to the request.
1100 memset(&c
, 0, sizeof(c
));
1101 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1102 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1103 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1104 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1105 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1106 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
1108 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1111 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1112 struct nvme_queue
*nvmeq
)
1114 struct nvme_command c
;
1115 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1118 * Note: we (ab)use the fact that the prp fields survive if no data
1119 * is attached to the request.
1121 memset(&c
, 0, sizeof(c
));
1122 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1123 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1124 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1125 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1126 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1127 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1129 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1132 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1134 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1137 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1139 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1142 static void abort_endio(struct request
*req
, blk_status_t error
)
1144 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1145 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1147 dev_warn(nvmeq
->dev
->ctrl
.device
,
1148 "Abort status: 0x%x", nvme_req(req
)->status
);
1149 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1150 blk_mq_free_request(req
);
1153 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1156 /* If true, indicates loss of adapter communication, possibly by a
1157 * NVMe Subsystem reset.
1159 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1161 /* If there is a reset ongoing, we shouldn't reset again. */
1162 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
1165 /* We shouldn't reset unless the controller is on fatal error state
1166 * _or_ if we lost the communication with it.
1168 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1174 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1176 /* Read a config register to help see what died. */
1180 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1182 if (result
== PCIBIOS_SUCCESSFUL
)
1183 dev_warn(dev
->ctrl
.device
,
1184 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1187 dev_warn(dev
->ctrl
.device
,
1188 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1192 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1194 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1195 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1196 struct nvme_dev
*dev
= nvmeq
->dev
;
1197 struct request
*abort_req
;
1198 struct nvme_command cmd
;
1199 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1201 /* If PCI error recovery process is happening, we cannot reset or
1202 * the recovery mechanism will surely fail.
1205 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1206 return BLK_EH_RESET_TIMER
;
1209 * Reset immediately if the controller is failed
1211 if (nvme_should_reset(dev
, csts
)) {
1212 nvme_warn_reset(dev
, csts
);
1213 nvme_dev_disable(dev
, false);
1214 nvme_reset_ctrl(&dev
->ctrl
);
1215 return BLK_EH_HANDLED
;
1219 * Did we miss an interrupt?
1221 if (__nvme_poll(nvmeq
, req
->tag
)) {
1222 dev_warn(dev
->ctrl
.device
,
1223 "I/O %d QID %d timeout, completion polled\n",
1224 req
->tag
, nvmeq
->qid
);
1225 return BLK_EH_HANDLED
;
1229 * Shutdown immediately if controller times out while starting. The
1230 * reset work will see the pci device disabled when it gets the forced
1231 * cancellation error. All outstanding requests are completed on
1232 * shutdown, so we return BLK_EH_HANDLED.
1234 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1235 dev_warn(dev
->ctrl
.device
,
1236 "I/O %d QID %d timeout, disable controller\n",
1237 req
->tag
, nvmeq
->qid
);
1238 nvme_dev_disable(dev
, false);
1239 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1240 return BLK_EH_HANDLED
;
1244 * Shutdown the controller immediately and schedule a reset if the
1245 * command was already aborted once before and still hasn't been
1246 * returned to the driver, or if this is the admin queue.
1248 if (!nvmeq
->qid
|| iod
->aborted
) {
1249 dev_warn(dev
->ctrl
.device
,
1250 "I/O %d QID %d timeout, reset controller\n",
1251 req
->tag
, nvmeq
->qid
);
1252 nvme_dev_disable(dev
, false);
1253 nvme_reset_ctrl(&dev
->ctrl
);
1256 * Mark the request as handled, since the inline shutdown
1257 * forces all outstanding requests to complete.
1259 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1260 return BLK_EH_HANDLED
;
1263 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1264 atomic_inc(&dev
->ctrl
.abort_limit
);
1265 return BLK_EH_RESET_TIMER
;
1269 memset(&cmd
, 0, sizeof(cmd
));
1270 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1271 cmd
.abort
.cid
= req
->tag
;
1272 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1274 dev_warn(nvmeq
->dev
->ctrl
.device
,
1275 "I/O %d QID %d timeout, aborting\n",
1276 req
->tag
, nvmeq
->qid
);
1278 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1279 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1280 if (IS_ERR(abort_req
)) {
1281 atomic_inc(&dev
->ctrl
.abort_limit
);
1282 return BLK_EH_RESET_TIMER
;
1285 abort_req
->timeout
= ADMIN_TIMEOUT
;
1286 abort_req
->end_io_data
= NULL
;
1287 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1290 * The aborted req will be completed on receiving the abort req.
1291 * We enable the timer again. If hit twice, it'll cause a device reset,
1292 * as the device then is in a faulty state.
1294 return BLK_EH_RESET_TIMER
;
1297 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1299 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1300 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1302 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1303 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1307 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1311 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1312 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1313 dev
->ctrl
.queue_count
--;
1314 dev
->queues
[i
] = NULL
;
1315 nvme_free_queue(nvmeq
);
1320 * nvme_suspend_queue - put queue into suspended state
1321 * @nvmeq - queue to suspend
1323 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1327 spin_lock_irq(&nvmeq
->q_lock
);
1328 if (nvmeq
->cq_vector
== -1) {
1329 spin_unlock_irq(&nvmeq
->q_lock
);
1332 vector
= nvmeq
->cq_vector
;
1333 nvmeq
->dev
->online_queues
--;
1334 nvmeq
->cq_vector
= -1;
1335 spin_unlock_irq(&nvmeq
->q_lock
);
1337 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1338 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1340 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1345 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1347 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1351 if (nvme_suspend_queue(nvmeq
))
1355 nvme_shutdown_ctrl(&dev
->ctrl
);
1357 nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1359 spin_lock_irq(&nvmeq
->q_lock
);
1360 nvme_process_cq(nvmeq
);
1361 spin_unlock_irq(&nvmeq
->q_lock
);
1364 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1367 int q_depth
= dev
->q_depth
;
1368 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1369 dev
->ctrl
.page_size
);
1371 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1372 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1373 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1374 q_depth
= div_u64(mem_per_q
, entry_size
);
1377 * Ensure the reduced q_depth is above some threshold where it
1378 * would be better to map queues in system memory with the
1388 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1392 /* CMB SQEs will be mapped before creation */
1393 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
))
1396 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1397 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1398 if (!nvmeq
->sq_cmds
)
1404 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1405 int depth
, int node
)
1407 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1412 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1413 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1417 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1420 nvmeq
->q_dmadev
= dev
->dev
;
1422 spin_lock_init(&nvmeq
->q_lock
);
1424 nvmeq
->cq_phase
= 1;
1425 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1426 nvmeq
->q_depth
= depth
;
1428 nvmeq
->cq_vector
= -1;
1429 dev
->queues
[qid
] = nvmeq
;
1430 dev
->ctrl
.queue_count
++;
1435 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1436 nvmeq
->cq_dma_addr
);
1442 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1444 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1445 int nr
= nvmeq
->dev
->ctrl
.instance
;
1447 if (use_threaded_interrupts
) {
1448 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1449 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1451 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1452 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1456 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1458 struct nvme_dev
*dev
= nvmeq
->dev
;
1460 spin_lock_irq(&nvmeq
->q_lock
);
1463 nvmeq
->cq_phase
= 1;
1464 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1465 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1466 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1467 dev
->online_queues
++;
1468 spin_unlock_irq(&nvmeq
->q_lock
);
1471 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1473 struct nvme_dev
*dev
= nvmeq
->dev
;
1476 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1477 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(nvmeq
->q_depth
),
1478 dev
->ctrl
.page_size
);
1479 nvmeq
->sq_dma_addr
= dev
->cmb_bus_addr
+ offset
;
1480 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1483 nvmeq
->cq_vector
= qid
- 1;
1484 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1486 goto release_vector
;
1488 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1492 nvme_init_queue(nvmeq
, qid
);
1493 result
= queue_request_irq(nvmeq
);
1500 dev
->online_queues
--;
1501 adapter_delete_sq(dev
, qid
);
1503 adapter_delete_cq(dev
, qid
);
1505 nvmeq
->cq_vector
= -1;
1509 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1510 .queue_rq
= nvme_queue_rq
,
1511 .complete
= nvme_pci_complete_rq
,
1512 .init_hctx
= nvme_admin_init_hctx
,
1513 .exit_hctx
= nvme_admin_exit_hctx
,
1514 .init_request
= nvme_init_request
,
1515 .timeout
= nvme_timeout
,
1518 static const struct blk_mq_ops nvme_mq_ops
= {
1519 .queue_rq
= nvme_queue_rq
,
1520 .complete
= nvme_pci_complete_rq
,
1521 .init_hctx
= nvme_init_hctx
,
1522 .init_request
= nvme_init_request
,
1523 .map_queues
= nvme_pci_map_queues
,
1524 .timeout
= nvme_timeout
,
1528 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1530 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1532 * If the controller was reset during removal, it's possible
1533 * user requests may be waiting on a stopped queue. Start the
1534 * queue to flush these to completion.
1536 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1537 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1538 blk_mq_free_tag_set(&dev
->admin_tagset
);
1542 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1544 if (!dev
->ctrl
.admin_q
) {
1545 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1546 dev
->admin_tagset
.nr_hw_queues
= 1;
1548 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1549 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1550 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1551 dev
->admin_tagset
.cmd_size
= nvme_pci_cmd_size(dev
, false);
1552 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1553 dev
->admin_tagset
.driver_data
= dev
;
1555 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1557 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1559 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1560 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1561 blk_mq_free_tag_set(&dev
->admin_tagset
);
1564 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1565 nvme_dev_remove_admin(dev
);
1566 dev
->ctrl
.admin_q
= NULL
;
1570 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1575 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1577 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1580 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1582 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1584 if (size
<= dev
->bar_mapped_size
)
1586 if (size
> pci_resource_len(pdev
, 0))
1590 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1592 dev
->bar_mapped_size
= 0;
1595 dev
->bar_mapped_size
= size
;
1596 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1601 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1605 struct nvme_queue
*nvmeq
;
1607 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1611 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1612 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1614 if (dev
->subsystem
&&
1615 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1616 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1618 result
= nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1622 nvmeq
= dev
->queues
[0];
1624 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1625 dev_to_node(dev
->dev
));
1630 aqa
= nvmeq
->q_depth
- 1;
1633 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1634 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1635 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1637 result
= nvme_enable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1641 nvmeq
->cq_vector
= 0;
1642 nvme_init_queue(nvmeq
, 0);
1643 result
= queue_request_irq(nvmeq
);
1645 nvmeq
->cq_vector
= -1;
1652 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1657 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1658 /* vector == qid - 1, match nvme_create_queue */
1659 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1660 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1666 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1667 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1668 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1674 * Ignore failing Create SQ/CQ commands, we can continue with less
1675 * than the desired aount of queues, and even a controller without
1676 * I/O queues an still be used to issue admin commands. This might
1677 * be useful to upgrade a buggy firmware for example.
1679 return ret
>= 0 ? 0 : ret
;
1682 static ssize_t
nvme_cmb_show(struct device
*dev
,
1683 struct device_attribute
*attr
,
1686 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1688 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1689 ndev
->cmbloc
, ndev
->cmbsz
);
1691 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1693 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1695 u64 szu
, size
, offset
;
1696 resource_size_t bar_size
;
1697 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1701 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1702 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1704 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1709 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1710 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1711 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1712 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1713 bar_size
= pci_resource_len(pdev
, bar
);
1715 if (offset
> bar_size
)
1719 * Controllers may support a CMB size larger than their BAR,
1720 * for example, due to being behind a bridge. Reduce the CMB to
1721 * the reported size of the BAR
1723 if (size
> bar_size
- offset
)
1724 size
= bar_size
- offset
;
1726 cmb
= ioremap_wc(pci_resource_start(pdev
, bar
) + offset
, size
);
1730 dev
->cmb_bus_addr
= pci_bus_address(pdev
, bar
) + offset
;
1731 dev
->cmb_size
= size
;
1735 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1740 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1741 &dev_attr_cmb
.attr
, NULL
);
1746 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1748 u64 dma_addr
= dev
->host_mem_descs_dma
;
1749 struct nvme_command c
;
1752 memset(&c
, 0, sizeof(c
));
1753 c
.features
.opcode
= nvme_admin_set_features
;
1754 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1755 c
.features
.dword11
= cpu_to_le32(bits
);
1756 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1757 ilog2(dev
->ctrl
.page_size
));
1758 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1759 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1760 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1762 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1764 dev_warn(dev
->ctrl
.device
,
1765 "failed to set host mem (err %d, flags %#x).\n",
1771 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1775 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1776 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1777 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1779 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1780 le64_to_cpu(desc
->addr
));
1783 kfree(dev
->host_mem_desc_bufs
);
1784 dev
->host_mem_desc_bufs
= NULL
;
1785 dma_free_coherent(dev
->dev
,
1786 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1787 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1788 dev
->host_mem_descs
= NULL
;
1789 dev
->nr_host_mem_descs
= 0;
1792 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1795 struct nvme_host_mem_buf_desc
*descs
;
1796 u32 max_entries
, len
;
1797 dma_addr_t descs_dma
;
1802 tmp
= (preferred
+ chunk_size
- 1);
1803 do_div(tmp
, chunk_size
);
1806 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1807 max_entries
= dev
->ctrl
.hmmaxd
;
1809 descs
= dma_zalloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1810 &descs_dma
, GFP_KERNEL
);
1814 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1816 goto out_free_descs
;
1818 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1819 dma_addr_t dma_addr
;
1821 len
= min_t(u64
, chunk_size
, preferred
- size
);
1822 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1823 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1827 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1828 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1835 dev
->nr_host_mem_descs
= i
;
1836 dev
->host_mem_size
= size
;
1837 dev
->host_mem_descs
= descs
;
1838 dev
->host_mem_descs_dma
= descs_dma
;
1839 dev
->host_mem_desc_bufs
= bufs
;
1844 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1846 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1847 le64_to_cpu(descs
[i
].addr
));
1852 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1855 dev
->host_mem_descs
= NULL
;
1859 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1863 /* start big and work our way down */
1864 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1865 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1867 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1868 if (!min
|| dev
->host_mem_size
>= min
)
1870 nvme_free_host_mem(dev
);
1877 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1879 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1880 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1881 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1882 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1885 preferred
= min(preferred
, max
);
1887 dev_warn(dev
->ctrl
.device
,
1888 "min host memory (%lld MiB) above limit (%d MiB).\n",
1889 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1890 nvme_free_host_mem(dev
);
1895 * If we already have a buffer allocated check if we can reuse it.
1897 if (dev
->host_mem_descs
) {
1898 if (dev
->host_mem_size
>= min
)
1899 enable_bits
|= NVME_HOST_MEM_RETURN
;
1901 nvme_free_host_mem(dev
);
1904 if (!dev
->host_mem_descs
) {
1905 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
1906 dev_warn(dev
->ctrl
.device
,
1907 "failed to allocate host memory buffer.\n");
1908 return 0; /* controller must work without HMB */
1911 dev_info(dev
->ctrl
.device
,
1912 "allocated %lld MiB host memory buffer.\n",
1913 dev
->host_mem_size
>> ilog2(SZ_1M
));
1916 ret
= nvme_set_host_mem(dev
, enable_bits
);
1918 nvme_free_host_mem(dev
);
1922 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1924 struct nvme_queue
*adminq
= dev
->queues
[0];
1925 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1926 int result
, nr_io_queues
;
1929 nr_io_queues
= num_possible_cpus();
1930 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1934 if (nr_io_queues
== 0)
1937 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1938 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1939 sizeof(struct nvme_command
));
1941 dev
->q_depth
= result
;
1943 nvme_release_cmb(dev
);
1947 size
= db_bar_size(dev
, nr_io_queues
);
1948 result
= nvme_remap_bar(dev
, size
);
1951 if (!--nr_io_queues
)
1954 adminq
->q_db
= dev
->dbs
;
1956 /* Deregister the admin queue's interrupt */
1957 pci_free_irq(pdev
, 0, adminq
);
1960 * If we enable msix early due to not intx, disable it again before
1961 * setting up the full range we need.
1963 pci_free_irq_vectors(pdev
);
1964 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1965 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1966 if (nr_io_queues
<= 0)
1968 dev
->max_qid
= nr_io_queues
;
1971 * Should investigate if there's a performance win from allocating
1972 * more queues than interrupt vectors; it might allow the submission
1973 * path to scale better, even if the receive path is limited by the
1974 * number of interrupts.
1977 result
= queue_request_irq(adminq
);
1979 adminq
->cq_vector
= -1;
1982 return nvme_create_io_queues(dev
);
1985 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1987 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1989 blk_mq_free_request(req
);
1990 complete(&nvmeq
->dev
->ioq_wait
);
1993 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1995 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1998 unsigned long flags
;
2001 * We might be called with the AQ q_lock held
2002 * and the I/O queue q_lock should always
2003 * nest inside the AQ one.
2005 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
2006 SINGLE_DEPTH_NESTING
);
2007 nvme_process_cq(nvmeq
);
2008 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
2011 nvme_del_queue_end(req
, error
);
2014 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
2016 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
2017 struct request
*req
;
2018 struct nvme_command cmd
;
2020 memset(&cmd
, 0, sizeof(cmd
));
2021 cmd
.delete_queue
.opcode
= opcode
;
2022 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2024 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
2026 return PTR_ERR(req
);
2028 req
->timeout
= ADMIN_TIMEOUT
;
2029 req
->end_io_data
= nvmeq
;
2031 blk_execute_rq_nowait(q
, NULL
, req
, false,
2032 opcode
== nvme_admin_delete_cq
?
2033 nvme_del_cq_end
: nvme_del_queue_end
);
2037 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
2040 unsigned long timeout
;
2041 u8 opcode
= nvme_admin_delete_sq
;
2043 for (pass
= 0; pass
< 2; pass
++) {
2044 int sent
= 0, i
= queues
;
2046 reinit_completion(&dev
->ioq_wait
);
2048 timeout
= ADMIN_TIMEOUT
;
2049 for (; i
> 0; i
--, sent
++)
2050 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
2054 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
2060 opcode
= nvme_admin_delete_cq
;
2065 * Return: error value if an error occurred setting up the queues or calling
2066 * Identify Device. 0 if these succeeded, even if adding some of the
2067 * namespaces failed. At the moment, these failures are silent. TBD which
2068 * failures should be reported.
2070 static int nvme_dev_add(struct nvme_dev
*dev
)
2072 if (!dev
->ctrl
.tagset
) {
2073 dev
->tagset
.ops
= &nvme_mq_ops
;
2074 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2075 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2076 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
2077 dev
->tagset
.queue_depth
=
2078 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
2079 dev
->tagset
.cmd_size
= nvme_pci_cmd_size(dev
, false);
2080 if ((dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))) && sgl_threshold
) {
2081 dev
->tagset
.cmd_size
= max(dev
->tagset
.cmd_size
,
2082 nvme_pci_cmd_size(dev
, true));
2084 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2085 dev
->tagset
.driver_data
= dev
;
2087 if (blk_mq_alloc_tag_set(&dev
->tagset
))
2089 dev
->ctrl
.tagset
= &dev
->tagset
;
2091 nvme_dbbuf_set(dev
);
2093 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2095 /* Free previously allocated queues that are no longer usable */
2096 nvme_free_queues(dev
, dev
->online_queues
);
2102 static int nvme_pci_enable(struct nvme_dev
*dev
)
2104 int result
= -ENOMEM
;
2105 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2107 if (pci_enable_device_mem(pdev
))
2110 pci_set_master(pdev
);
2112 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
2113 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
2116 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2122 * Some devices and/or platforms don't advertise or work with INTx
2123 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2124 * adjust this later.
2126 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2130 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2132 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2134 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2135 dev
->dbs
= dev
->bar
+ 4096;
2138 * Temporary fix for the Apple controller found in the MacBook8,1 and
2139 * some MacBook7,1 to avoid controller resets and data loss.
2141 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2143 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2144 "set queue depth=%u to work around controller resets\n",
2146 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2147 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2148 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2150 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2151 "set queue depth=%u\n", dev
->q_depth
);
2155 * CMBs can currently only exist on >=1.2 PCIe devices. We only
2156 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
2157 * has no name we can pass NULL as final argument to
2158 * sysfs_add_file_to_group.
2161 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
2162 dev
->cmb
= nvme_map_cmb(dev
);
2164 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
2165 &dev_attr_cmb
.attr
, NULL
))
2166 dev_warn(dev
->ctrl
.device
,
2167 "failed to add sysfs attribute for CMB\n");
2171 pci_enable_pcie_error_reporting(pdev
);
2172 pci_save_state(pdev
);
2176 pci_disable_device(pdev
);
2180 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2184 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2187 static void nvme_pci_disable(struct nvme_dev
*dev
)
2189 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2191 nvme_release_cmb(dev
);
2192 pci_free_irq_vectors(pdev
);
2194 if (pci_is_enabled(pdev
)) {
2195 pci_disable_pcie_error_reporting(pdev
);
2196 pci_disable_device(pdev
);
2200 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2204 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2206 mutex_lock(&dev
->shutdown_lock
);
2207 if (pci_is_enabled(pdev
)) {
2208 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2210 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2211 dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
2212 nvme_start_freeze(&dev
->ctrl
);
2213 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2214 pdev
->error_state
!= pci_channel_io_normal
);
2218 * Give the controller a chance to complete all entered requests if
2219 * doing a safe shutdown.
2223 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2226 * If the controller is still alive tell it to stop using the
2227 * host memory buffer. In theory the shutdown / reset should
2228 * make sure that it doesn't access the host memoery anymore,
2229 * but I'd rather be safe than sorry..
2231 if (dev
->host_mem_descs
)
2232 nvme_set_host_mem(dev
, 0);
2235 nvme_stop_queues(&dev
->ctrl
);
2237 queues
= dev
->online_queues
- 1;
2238 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
2239 nvme_suspend_queue(dev
->queues
[i
]);
2242 /* A device might become IO incapable very soon during
2243 * probe, before the admin queue is configured. Thus,
2244 * queue_count can be 0 here.
2246 if (dev
->ctrl
.queue_count
)
2247 nvme_suspend_queue(dev
->queues
[0]);
2249 nvme_disable_io_queues(dev
, queues
);
2250 nvme_disable_admin_queue(dev
, shutdown
);
2252 nvme_pci_disable(dev
);
2254 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2255 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2258 * The driver will not be starting up queues again if shutting down so
2259 * must flush all entered requests to their failed completion to avoid
2260 * deadlocking blk-mq hot-cpu notifier.
2263 nvme_start_queues(&dev
->ctrl
);
2264 mutex_unlock(&dev
->shutdown_lock
);
2267 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2269 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2270 PAGE_SIZE
, PAGE_SIZE
, 0);
2271 if (!dev
->prp_page_pool
)
2274 /* Optimisation for I/Os between 4k and 128k */
2275 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2277 if (!dev
->prp_small_pool
) {
2278 dma_pool_destroy(dev
->prp_page_pool
);
2284 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2286 dma_pool_destroy(dev
->prp_page_pool
);
2287 dma_pool_destroy(dev
->prp_small_pool
);
2290 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2292 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2294 nvme_dbbuf_dma_free(dev
);
2295 put_device(dev
->dev
);
2296 if (dev
->tagset
.tags
)
2297 blk_mq_free_tag_set(&dev
->tagset
);
2298 if (dev
->ctrl
.admin_q
)
2299 blk_put_queue(dev
->ctrl
.admin_q
);
2301 free_opal_dev(dev
->ctrl
.opal_dev
);
2305 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2307 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2309 nvme_get_ctrl(&dev
->ctrl
);
2310 nvme_dev_disable(dev
, false);
2311 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2312 nvme_put_ctrl(&dev
->ctrl
);
2315 static void nvme_reset_work(struct work_struct
*work
)
2317 struct nvme_dev
*dev
=
2318 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2319 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2320 int result
= -ENODEV
;
2322 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2326 * If we're called to reset a live controller first shut it down before
2329 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2330 nvme_dev_disable(dev
, false);
2332 result
= nvme_pci_enable(dev
);
2336 result
= nvme_pci_configure_admin_queue(dev
);
2340 result
= nvme_alloc_admin_tags(dev
);
2344 result
= nvme_init_identify(&dev
->ctrl
);
2348 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2349 if (!dev
->ctrl
.opal_dev
)
2350 dev
->ctrl
.opal_dev
=
2351 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2352 else if (was_suspend
)
2353 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2355 free_opal_dev(dev
->ctrl
.opal_dev
);
2356 dev
->ctrl
.opal_dev
= NULL
;
2359 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2360 result
= nvme_dbbuf_dma_alloc(dev
);
2363 "unable to allocate dma for dbbuf\n");
2366 if (dev
->ctrl
.hmpre
) {
2367 result
= nvme_setup_host_mem(dev
);
2372 result
= nvme_setup_io_queues(dev
);
2377 * Keep the controller around but remove all namespaces if we don't have
2378 * any working I/O queue.
2380 if (dev
->online_queues
< 2) {
2381 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2382 nvme_kill_queues(&dev
->ctrl
);
2383 nvme_remove_namespaces(&dev
->ctrl
);
2385 nvme_start_queues(&dev
->ctrl
);
2386 nvme_wait_freeze(&dev
->ctrl
);
2388 nvme_unfreeze(&dev
->ctrl
);
2391 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2392 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2396 nvme_start_ctrl(&dev
->ctrl
);
2400 nvme_remove_dead_ctrl(dev
, result
);
2403 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2405 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2406 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2408 nvme_kill_queues(&dev
->ctrl
);
2409 if (pci_get_drvdata(pdev
))
2410 device_release_driver(&pdev
->dev
);
2411 nvme_put_ctrl(&dev
->ctrl
);
2414 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2416 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2420 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2422 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2426 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2428 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2432 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2434 .module
= THIS_MODULE
,
2435 .flags
= NVME_F_METADATA_SUPPORTED
,
2436 .reg_read32
= nvme_pci_reg_read32
,
2437 .reg_write32
= nvme_pci_reg_write32
,
2438 .reg_read64
= nvme_pci_reg_read64
,
2439 .free_ctrl
= nvme_pci_free_ctrl
,
2440 .submit_async_event
= nvme_pci_submit_async_event
,
2443 static int nvme_dev_map(struct nvme_dev
*dev
)
2445 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2447 if (pci_request_mem_regions(pdev
, "nvme"))
2450 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2455 pci_release_mem_regions(pdev
);
2459 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2461 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2463 * Several Samsung devices seem to drop off the PCIe bus
2464 * randomly when APST is on and uses the deepest sleep state.
2465 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2466 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2467 * 950 PRO 256GB", but it seems to be restricted to two Dell
2470 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2471 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2472 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2473 return NVME_QUIRK_NO_DEEPEST_PS
;
2474 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2476 * Samsung SSD 960 EVO drops off the PCIe bus after system
2477 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2478 * within few minutes after bootup on a Coffee Lake board -
2481 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2482 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2483 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2484 return NVME_QUIRK_NO_APST
;
2490 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2492 int node
, result
= -ENOMEM
;
2493 struct nvme_dev
*dev
;
2494 unsigned long quirks
= id
->driver_data
;
2496 node
= dev_to_node(&pdev
->dev
);
2497 if (node
== NUMA_NO_NODE
)
2498 set_dev_node(&pdev
->dev
, first_memory_node
);
2500 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2503 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2508 dev
->dev
= get_device(&pdev
->dev
);
2509 pci_set_drvdata(pdev
, dev
);
2511 result
= nvme_dev_map(dev
);
2515 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2516 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2517 mutex_init(&dev
->shutdown_lock
);
2518 init_completion(&dev
->ioq_wait
);
2520 result
= nvme_setup_prp_pools(dev
);
2524 quirks
|= check_vendor_combination_bug(pdev
);
2526 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2531 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2532 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2534 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2538 nvme_release_prp_pools(dev
);
2540 nvme_dev_unmap(dev
);
2542 put_device(dev
->dev
);
2549 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2551 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2552 nvme_dev_disable(dev
, false);
2555 static void nvme_reset_done(struct pci_dev
*pdev
)
2557 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2558 nvme_reset_ctrl(&dev
->ctrl
);
2561 static void nvme_shutdown(struct pci_dev
*pdev
)
2563 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2564 nvme_dev_disable(dev
, true);
2568 * The driver's remove may be called on a device in a partially initialized
2569 * state. This function must not have any dependencies on the device state in
2572 static void nvme_remove(struct pci_dev
*pdev
)
2574 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2576 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2578 cancel_work_sync(&dev
->ctrl
.reset_work
);
2579 pci_set_drvdata(pdev
, NULL
);
2581 if (!pci_device_is_present(pdev
)) {
2582 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2583 nvme_dev_disable(dev
, false);
2586 flush_work(&dev
->ctrl
.reset_work
);
2587 nvme_stop_ctrl(&dev
->ctrl
);
2588 nvme_remove_namespaces(&dev
->ctrl
);
2589 nvme_dev_disable(dev
, true);
2590 nvme_free_host_mem(dev
);
2591 nvme_dev_remove_admin(dev
);
2592 nvme_free_queues(dev
, 0);
2593 nvme_uninit_ctrl(&dev
->ctrl
);
2594 nvme_release_prp_pools(dev
);
2595 nvme_dev_unmap(dev
);
2596 nvme_put_ctrl(&dev
->ctrl
);
2599 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2604 if (pci_vfs_assigned(pdev
)) {
2605 dev_warn(&pdev
->dev
,
2606 "Cannot disable SR-IOV VFs while assigned\n");
2609 pci_disable_sriov(pdev
);
2613 ret
= pci_enable_sriov(pdev
, numvfs
);
2614 return ret
? ret
: numvfs
;
2617 #ifdef CONFIG_PM_SLEEP
2618 static int nvme_suspend(struct device
*dev
)
2620 struct pci_dev
*pdev
= to_pci_dev(dev
);
2621 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2622 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2624 if (!(pm_suspend_via_s2idle() && (ctrl
->quirks
& NVME_QUIRK_NO_DISABLE
)))
2625 nvme_dev_disable(ndev
, true);
2630 static int nvme_resume(struct device
*dev
)
2632 struct pci_dev
*pdev
= to_pci_dev(dev
);
2633 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2635 nvme_reset_ctrl(&ndev
->ctrl
);
2640 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2642 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2643 pci_channel_state_t state
)
2645 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2648 * A frozen channel requires a reset. When detected, this method will
2649 * shutdown the controller to quiesce. The controller will be restarted
2650 * after the slot reset through driver's slot_reset callback.
2653 case pci_channel_io_normal
:
2654 return PCI_ERS_RESULT_CAN_RECOVER
;
2655 case pci_channel_io_frozen
:
2656 dev_warn(dev
->ctrl
.device
,
2657 "frozen state error detected, reset controller\n");
2658 nvme_dev_disable(dev
, false);
2659 return PCI_ERS_RESULT_NEED_RESET
;
2660 case pci_channel_io_perm_failure
:
2661 dev_warn(dev
->ctrl
.device
,
2662 "failure state error detected, request disconnect\n");
2663 return PCI_ERS_RESULT_DISCONNECT
;
2665 return PCI_ERS_RESULT_NEED_RESET
;
2668 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2670 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2672 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2673 pci_restore_state(pdev
);
2674 nvme_reset_ctrl(&dev
->ctrl
);
2675 return PCI_ERS_RESULT_RECOVERED
;
2678 static void nvme_error_resume(struct pci_dev
*pdev
)
2680 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2682 flush_work(&dev
->ctrl
.reset_work
);
2683 pci_cleanup_aer_uncorrect_error_status(pdev
);
2686 static const struct pci_error_handlers nvme_err_handler
= {
2687 .error_detected
= nvme_error_detected
,
2688 .slot_reset
= nvme_slot_reset
,
2689 .resume
= nvme_error_resume
,
2690 .reset_prepare
= nvme_reset_prepare
,
2691 .reset_done
= nvme_reset_done
,
2694 static const struct pci_device_id nvme_id_table
[] = {
2695 { PCI_VDEVICE(INTEL
, 0x0953),
2696 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2697 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2698 { PCI_VDEVICE(INTEL
, 0x0a53),
2699 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2700 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2701 { PCI_VDEVICE(INTEL
, 0x0a54),
2702 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2703 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2704 { PCI_VDEVICE(INTEL
, 0x0a55),
2705 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2706 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2707 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2708 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
2709 NVME_QUIRK_MEDIUM_PRIO_SQ
},
2710 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
2711 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
2712 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2713 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2714 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2715 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2716 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2717 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2718 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2719 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2720 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2721 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2722 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2723 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2724 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2725 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2726 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2727 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2728 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2729 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2730 { PCI_VDEVICE(SK_HYNIX
, 0x1527), /* Sk Hynix */
2731 .driver_data
= NVME_QUIRK_NO_DISABLE
, },
2732 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2733 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2734 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2737 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2739 static struct pci_driver nvme_driver
= {
2741 .id_table
= nvme_id_table
,
2742 .probe
= nvme_probe
,
2743 .remove
= nvme_remove
,
2744 .shutdown
= nvme_shutdown
,
2746 .pm
= &nvme_dev_pm_ops
,
2748 .sriov_configure
= nvme_pci_sriov_configure
,
2749 .err_handler
= &nvme_err_handler
,
2752 static int __init
nvme_init(void)
2754 return pci_register_driver(&nvme_driver
);
2757 static void __exit
nvme_exit(void)
2759 pci_unregister_driver(&nvme_driver
);
2760 flush_workqueue(nvme_wq
);
2764 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2765 MODULE_LICENSE("GPL");
2766 MODULE_VERSION("1.0");
2767 module_init(nvme_init
);
2768 module_exit(nvme_exit
);