2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/blk-mq-pci.h>
19 #include <linux/dmi.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/once.h>
27 #include <linux/pci.h>
28 #include <linux/suspend.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41 static int use_threaded_interrupts
;
42 module_param(use_threaded_interrupts
, int, 0);
44 static bool use_cmb_sqes
= true;
45 module_param(use_cmb_sqes
, bool, 0644);
46 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
48 static unsigned int max_host_mem_size_mb
= 128;
49 module_param(max_host_mem_size_mb
, uint
, 0444);
50 MODULE_PARM_DESC(max_host_mem_size_mb
,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
53 static unsigned int sgl_threshold
= SZ_32K
;
54 module_param(sgl_threshold
, uint
, 0644);
55 MODULE_PARM_DESC(sgl_threshold
,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
59 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
60 static const struct kernel_param_ops io_queue_depth_ops
= {
61 .set
= io_queue_depth_set
,
65 static int io_queue_depth
= 1024;
66 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
67 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
72 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
73 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue
**queues
;
80 struct blk_mq_tag_set tagset
;
81 struct blk_mq_tag_set admin_tagset
;
84 struct dma_pool
*prp_page_pool
;
85 struct dma_pool
*prp_small_pool
;
86 unsigned online_queues
;
91 unsigned long bar_mapped_size
;
92 struct work_struct remove_work
;
93 struct mutex shutdown_lock
;
96 pci_bus_addr_t cmb_bus_addr
;
100 struct nvme_ctrl ctrl
;
101 struct completion ioq_wait
;
104 /* shadow doorbell buffer support: */
106 dma_addr_t dbbuf_dbs_dma_addr
;
108 dma_addr_t dbbuf_eis_dma_addr
;
110 /* host memory buffer support: */
112 u32 nr_host_mem_descs
;
113 dma_addr_t host_mem_descs_dma
;
114 struct nvme_host_mem_buf_desc
*host_mem_descs
;
115 void **host_mem_desc_bufs
;
118 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
122 ret
= kstrtoint(val
, 10, &n
);
123 if (ret
!= 0 || n
< 2)
126 return param_set_int(val
, kp
);
129 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
131 return qid
* 2 * stride
;
134 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
136 return (qid
* 2 + 1) * stride
;
139 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
141 return container_of(ctrl
, struct nvme_dev
, ctrl
);
145 * An NVM Express queue. Each device has at least two (one for admin
146 * commands and one for I/O commands).
149 struct device
*q_dmadev
;
150 struct nvme_dev
*dev
;
152 struct nvme_command
*sq_cmds
;
153 struct nvme_command __iomem
*sq_cmds_io
;
154 volatile struct nvme_completion
*cqes
;
155 struct blk_mq_tags
**tags
;
156 dma_addr_t sq_dma_addr
;
157 dma_addr_t cq_dma_addr
;
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
175 * me express that. Use nvme_init_iod to ensure there's enough space
176 * allocated to store the PRP list.
179 struct nvme_request req
;
180 struct nvme_queue
*nvmeq
;
183 int npages
; /* In the PRP list. 0 means small pool in use */
184 int nents
; /* Used in scatterlist */
185 int length
; /* Of data, in bytes */
186 dma_addr_t first_dma
;
187 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
188 struct scatterlist
*sg
;
189 struct scatterlist inline_sg
[0];
193 * Check we didin't inadvertently grow the command struct
195 static inline void _nvme_check_size(void)
197 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
206 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
207 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
208 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
209 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
212 static inline unsigned int nvme_dbbuf_size(u32 stride
)
214 return ((num_possible_cpus() + 1) * 8 * stride
);
217 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
219 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
224 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
225 &dev
->dbbuf_dbs_dma_addr
,
229 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
230 &dev
->dbbuf_eis_dma_addr
,
232 if (!dev
->dbbuf_eis
) {
233 dma_free_coherent(dev
->dev
, mem_size
,
234 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
235 dev
->dbbuf_dbs
= NULL
;
242 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
244 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
246 if (dev
->dbbuf_dbs
) {
247 dma_free_coherent(dev
->dev
, mem_size
,
248 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
249 dev
->dbbuf_dbs
= NULL
;
251 if (dev
->dbbuf_eis
) {
252 dma_free_coherent(dev
->dev
, mem_size
,
253 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
254 dev
->dbbuf_eis
= NULL
;
258 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
259 struct nvme_queue
*nvmeq
, int qid
)
261 if (!dev
->dbbuf_dbs
|| !qid
)
264 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
265 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
266 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
267 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
270 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
272 struct nvme_command c
;
277 memset(&c
, 0, sizeof(c
));
278 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
279 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
280 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
282 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
283 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
284 /* Free memory and continue on */
285 nvme_dbbuf_dma_free(dev
);
289 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
291 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
294 /* Update dbbuf and return true if an MMIO is required */
295 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
296 volatile u32
*dbbuf_ei
)
302 * Ensure that the queue is written before updating
303 * the doorbell in memory
307 old_value
= *dbbuf_db
;
311 * Ensure that the doorbell is updated before reading the event
312 * index from memory. The controller needs to provide similar
313 * ordering to ensure the envent index is updated before reading
318 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
326 * Max size of iod being embedded in the request payload
328 #define NVME_INT_PAGES 2
329 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
332 * Will slightly overestimate the number of pages needed. This is OK
333 * as it only leads to a small amount of wasted memory for the lifetime of
336 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
338 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
339 dev
->ctrl
.page_size
);
340 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
344 * Calculates the number of pages needed for the SGL segments. For example a 4k
345 * page can accommodate 256 SGL descriptors.
347 static int nvme_pci_npages_sgl(unsigned int num_seg
)
349 return DIV_ROUND_UP(num_seg
* sizeof(struct nvme_sgl_desc
), PAGE_SIZE
);
352 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev
*dev
,
353 unsigned int size
, unsigned int nseg
, bool use_sgl
)
358 alloc_size
= sizeof(__le64
*) * nvme_pci_npages_sgl(nseg
);
360 alloc_size
= sizeof(__le64
*) * nvme_npages(size
, dev
);
362 return alloc_size
+ sizeof(struct scatterlist
) * nseg
;
365 static unsigned int nvme_pci_cmd_size(struct nvme_dev
*dev
, bool use_sgl
)
367 unsigned int alloc_size
= nvme_pci_iod_alloc_size(dev
,
368 NVME_INT_BYTES(dev
), NVME_INT_PAGES
,
371 return sizeof(struct nvme_iod
) + alloc_size
;
374 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
375 unsigned int hctx_idx
)
377 struct nvme_dev
*dev
= data
;
378 struct nvme_queue
*nvmeq
= dev
->queues
[0];
380 WARN_ON(hctx_idx
!= 0);
381 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
382 WARN_ON(nvmeq
->tags
);
384 hctx
->driver_data
= nvmeq
;
385 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
389 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
391 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
396 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
397 unsigned int hctx_idx
)
399 struct nvme_dev
*dev
= data
;
400 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
403 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
405 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
406 hctx
->driver_data
= nvmeq
;
410 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
411 unsigned int hctx_idx
, unsigned int numa_node
)
413 struct nvme_dev
*dev
= set
->driver_data
;
414 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
415 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
416 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
423 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
425 struct nvme_dev
*dev
= set
->driver_data
;
427 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
431 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
432 * @nvmeq: The queue to use
433 * @cmd: The command to send
435 * Safe to use from interrupt context
437 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
438 struct nvme_command
*cmd
)
440 u16 tail
= nvmeq
->sq_tail
;
442 if (nvmeq
->sq_cmds_io
)
443 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
445 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
447 if (++tail
== nvmeq
->q_depth
)
449 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
451 writel(tail
, nvmeq
->q_db
);
452 nvmeq
->sq_tail
= tail
;
455 static void **nvme_pci_iod_list(struct request
*req
)
457 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
458 return (void **)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
461 static inline bool nvme_pci_use_sgls(struct nvme_dev
*dev
, struct request
*req
)
463 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
464 int nseg
= blk_rq_nr_phys_segments(req
);
465 unsigned int avg_seg_size
;
470 avg_seg_size
= DIV_ROUND_UP(blk_rq_payload_bytes(req
), nseg
);
472 if (!(dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))))
474 if (!iod
->nvmeq
->qid
)
476 if (!sgl_threshold
|| avg_seg_size
< sgl_threshold
)
481 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
483 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
484 int nseg
= blk_rq_nr_phys_segments(rq
);
485 unsigned int size
= blk_rq_payload_bytes(rq
);
487 iod
->use_sgl
= nvme_pci_use_sgls(dev
, rq
);
489 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
490 size_t alloc_size
= nvme_pci_iod_alloc_size(dev
, size
, nseg
,
493 iod
->sg
= kmalloc(alloc_size
, GFP_ATOMIC
);
495 return BLK_STS_RESOURCE
;
497 iod
->sg
= iod
->inline_sg
;
508 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
510 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
511 const int last_prp
= dev
->ctrl
.page_size
/ sizeof(__le64
) - 1;
512 dma_addr_t dma_addr
= iod
->first_dma
, next_dma_addr
;
516 if (iod
->npages
== 0)
517 dma_pool_free(dev
->prp_small_pool
, nvme_pci_iod_list(req
)[0],
520 for (i
= 0; i
< iod
->npages
; i
++) {
521 void *addr
= nvme_pci_iod_list(req
)[i
];
524 struct nvme_sgl_desc
*sg_list
= addr
;
527 le64_to_cpu((sg_list
[SGES_PER_PAGE
- 1]).addr
);
529 __le64
*prp_list
= addr
;
531 next_dma_addr
= le64_to_cpu(prp_list
[last_prp
]);
534 dma_pool_free(dev
->prp_page_pool
, addr
, dma_addr
);
535 dma_addr
= next_dma_addr
;
538 if (iod
->sg
!= iod
->inline_sg
)
542 #ifdef CONFIG_BLK_DEV_INTEGRITY
543 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
545 if (be32_to_cpu(pi
->ref_tag
) == v
)
546 pi
->ref_tag
= cpu_to_be32(p
);
549 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
551 if (be32_to_cpu(pi
->ref_tag
) == p
)
552 pi
->ref_tag
= cpu_to_be32(v
);
556 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
558 * The virtual start sector is the one that was originally submitted by the
559 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
560 * start sector may be different. Remap protection information to match the
561 * physical LBA on writes, and back to the original seed on reads.
563 * Type 0 and 3 do not have a ref tag, so no remapping required.
565 static void nvme_dif_remap(struct request
*req
,
566 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
568 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
569 struct bio_integrity_payload
*bip
;
570 struct t10_pi_tuple
*pi
;
572 u32 i
, nlb
, ts
, phys
, virt
;
574 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
577 bip
= bio_integrity(req
->bio
);
581 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
584 virt
= bip_get_seed(bip
);
585 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
586 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
587 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
589 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
590 pi
= (struct t10_pi_tuple
*)p
;
591 dif_swap(phys
, virt
, pi
);
596 #else /* CONFIG_BLK_DEV_INTEGRITY */
597 static void nvme_dif_remap(struct request
*req
,
598 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
601 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
604 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
609 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
612 struct scatterlist
*sg
;
614 for_each_sg(sgl
, sg
, nents
, i
) {
615 dma_addr_t phys
= sg_phys(sg
);
616 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
617 "dma_address:%pad dma_length:%d\n",
618 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
623 static blk_status_t
nvme_pci_setup_prps(struct nvme_dev
*dev
,
624 struct request
*req
, struct nvme_rw_command
*cmnd
)
626 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
627 struct dma_pool
*pool
;
628 int length
= blk_rq_payload_bytes(req
);
629 struct scatterlist
*sg
= iod
->sg
;
630 int dma_len
= sg_dma_len(sg
);
631 u64 dma_addr
= sg_dma_address(sg
);
632 u32 page_size
= dev
->ctrl
.page_size
;
633 int offset
= dma_addr
& (page_size
- 1);
635 void **list
= nvme_pci_iod_list(req
);
639 length
-= (page_size
- offset
);
645 dma_len
-= (page_size
- offset
);
647 dma_addr
+= (page_size
- offset
);
650 dma_addr
= sg_dma_address(sg
);
651 dma_len
= sg_dma_len(sg
);
654 if (length
<= page_size
) {
655 iod
->first_dma
= dma_addr
;
659 nprps
= DIV_ROUND_UP(length
, page_size
);
660 if (nprps
<= (256 / 8)) {
661 pool
= dev
->prp_small_pool
;
664 pool
= dev
->prp_page_pool
;
668 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
670 iod
->first_dma
= dma_addr
;
672 return BLK_STS_RESOURCE
;
675 iod
->first_dma
= prp_dma
;
678 if (i
== page_size
>> 3) {
679 __le64
*old_prp_list
= prp_list
;
680 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
682 return BLK_STS_RESOURCE
;
683 list
[iod
->npages
++] = prp_list
;
684 prp_list
[0] = old_prp_list
[i
- 1];
685 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
688 prp_list
[i
++] = cpu_to_le64(dma_addr
);
689 dma_len
-= page_size
;
690 dma_addr
+= page_size
;
696 if (unlikely(dma_len
< 0))
699 dma_addr
= sg_dma_address(sg
);
700 dma_len
= sg_dma_len(sg
);
704 cmnd
->dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
705 cmnd
->dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
710 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
711 "Invalid SGL for payload:%d nents:%d\n",
712 blk_rq_payload_bytes(req
), iod
->nents
);
713 return BLK_STS_IOERR
;
716 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc
*sge
,
717 struct scatterlist
*sg
)
719 sge
->addr
= cpu_to_le64(sg_dma_address(sg
));
720 sge
->length
= cpu_to_le32(sg_dma_len(sg
));
721 sge
->type
= NVME_SGL_FMT_DATA_DESC
<< 4;
724 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc
*sge
,
725 dma_addr_t dma_addr
, int entries
)
727 sge
->addr
= cpu_to_le64(dma_addr
);
728 if (entries
< SGES_PER_PAGE
) {
729 sge
->length
= cpu_to_le32(entries
* sizeof(*sge
));
730 sge
->type
= NVME_SGL_FMT_LAST_SEG_DESC
<< 4;
732 sge
->length
= cpu_to_le32(PAGE_SIZE
);
733 sge
->type
= NVME_SGL_FMT_SEG_DESC
<< 4;
737 static blk_status_t
nvme_pci_setup_sgls(struct nvme_dev
*dev
,
738 struct request
*req
, struct nvme_rw_command
*cmd
, int entries
)
740 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
741 struct dma_pool
*pool
;
742 struct nvme_sgl_desc
*sg_list
;
743 struct scatterlist
*sg
= iod
->sg
;
747 /* setting the transfer type as SGL */
748 cmd
->flags
= NVME_CMD_SGL_METABUF
;
751 nvme_pci_sgl_set_data(&cmd
->dptr
.sgl
, sg
);
755 if (entries
<= (256 / sizeof(struct nvme_sgl_desc
))) {
756 pool
= dev
->prp_small_pool
;
759 pool
= dev
->prp_page_pool
;
763 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
766 return BLK_STS_RESOURCE
;
769 nvme_pci_iod_list(req
)[0] = sg_list
;
770 iod
->first_dma
= sgl_dma
;
772 nvme_pci_sgl_set_seg(&cmd
->dptr
.sgl
, sgl_dma
, entries
);
775 if (i
== SGES_PER_PAGE
) {
776 struct nvme_sgl_desc
*old_sg_desc
= sg_list
;
777 struct nvme_sgl_desc
*link
= &old_sg_desc
[i
- 1];
779 sg_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &sgl_dma
);
781 return BLK_STS_RESOURCE
;
784 nvme_pci_iod_list(req
)[iod
->npages
++] = sg_list
;
785 sg_list
[i
++] = *link
;
786 nvme_pci_sgl_set_seg(link
, sgl_dma
, entries
);
789 nvme_pci_sgl_set_data(&sg_list
[i
++], sg
);
791 } while (--entries
> 0);
796 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
797 struct nvme_command
*cmnd
)
799 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
800 struct request_queue
*q
= req
->q
;
801 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
802 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
803 blk_status_t ret
= BLK_STS_IOERR
;
806 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
807 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
811 ret
= BLK_STS_RESOURCE
;
812 nr_mapped
= dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
818 ret
= nvme_pci_setup_sgls(dev
, req
, &cmnd
->rw
, nr_mapped
);
820 ret
= nvme_pci_setup_prps(dev
, req
, &cmnd
->rw
);
822 if (ret
!= BLK_STS_OK
)
826 if (blk_integrity_rq(req
)) {
827 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
830 sg_init_table(&iod
->meta_sg
, 1);
831 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
834 if (req_op(req
) == REQ_OP_WRITE
)
835 nvme_dif_remap(req
, nvme_dif_prep
);
837 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
841 if (blk_integrity_rq(req
))
842 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
846 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
851 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
853 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
854 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
855 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
858 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
859 if (blk_integrity_rq(req
)) {
860 if (req_op(req
) == REQ_OP_READ
)
861 nvme_dif_remap(req
, nvme_dif_complete
);
862 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
866 nvme_cleanup_cmd(req
);
867 nvme_free_iod(dev
, req
);
871 * NOTE: ns is NULL when called on the admin queue.
873 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
874 const struct blk_mq_queue_data
*bd
)
876 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
877 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
878 struct nvme_dev
*dev
= nvmeq
->dev
;
879 struct request
*req
= bd
->rq
;
880 struct nvme_command cmnd
;
883 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
887 ret
= nvme_init_iod(req
, dev
);
891 if (blk_rq_nr_phys_segments(req
)) {
892 ret
= nvme_map_data(dev
, req
, &cmnd
);
894 goto out_cleanup_iod
;
897 blk_mq_start_request(req
);
899 spin_lock_irq(&nvmeq
->q_lock
);
900 if (unlikely(nvmeq
->cq_vector
< 0)) {
902 spin_unlock_irq(&nvmeq
->q_lock
);
903 goto out_cleanup_iod
;
905 __nvme_submit_cmd(nvmeq
, &cmnd
);
906 nvme_process_cq(nvmeq
);
907 spin_unlock_irq(&nvmeq
->q_lock
);
910 nvme_free_iod(dev
, req
);
912 nvme_cleanup_cmd(req
);
916 static void nvme_pci_complete_rq(struct request
*req
)
918 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
920 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
921 nvme_complete_rq(req
);
924 /* We read the CQE phase first to check if the rest of the entry is valid */
925 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
928 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
931 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
933 u16 head
= nvmeq
->cq_head
;
935 if (likely(nvmeq
->cq_vector
>= 0)) {
936 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
938 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
942 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
,
943 struct nvme_completion
*cqe
)
947 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
948 dev_warn(nvmeq
->dev
->ctrl
.device
,
949 "invalid id %d completed on queue %d\n",
950 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
955 * AEN requests are special as they don't time out and can
956 * survive any kind of queue freeze and often don't respond to
957 * aborts. We don't even bother to allocate a struct request
958 * for them but rather special case them here.
960 if (unlikely(nvmeq
->qid
== 0 &&
961 cqe
->command_id
>= NVME_AQ_BLK_MQ_DEPTH
)) {
962 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
963 cqe
->status
, &cqe
->result
);
968 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
969 nvme_end_request(req
, cqe
->status
, cqe
->result
);
972 static inline bool nvme_read_cqe(struct nvme_queue
*nvmeq
,
973 struct nvme_completion
*cqe
)
975 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
976 *cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
978 if (nvmeq
->cq_head
== nvmeq
->q_depth
- 1) {
980 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
989 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
991 struct nvme_completion cqe
;
994 while (nvme_read_cqe(nvmeq
, &cqe
)) {
995 nvme_handle_cqe(nvmeq
, &cqe
);
1000 nvme_ring_cq_doorbell(nvmeq
);
1003 static irqreturn_t
nvme_irq(int irq
, void *data
)
1006 struct nvme_queue
*nvmeq
= data
;
1007 spin_lock(&nvmeq
->q_lock
);
1008 nvme_process_cq(nvmeq
);
1009 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
1010 nvmeq
->cqe_seen
= 0;
1011 spin_unlock(&nvmeq
->q_lock
);
1015 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
1017 struct nvme_queue
*nvmeq
= data
;
1018 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
1019 return IRQ_WAKE_THREAD
;
1023 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
1025 struct nvme_completion cqe
;
1026 int found
= 0, consumed
= 0;
1028 if (!nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
1031 spin_lock_irq(&nvmeq
->q_lock
);
1032 while (nvme_read_cqe(nvmeq
, &cqe
)) {
1033 nvme_handle_cqe(nvmeq
, &cqe
);
1036 if (tag
== cqe
.command_id
) {
1043 nvme_ring_cq_doorbell(nvmeq
);
1044 spin_unlock_irq(&nvmeq
->q_lock
);
1049 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
1051 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
1053 return __nvme_poll(nvmeq
, tag
);
1056 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
)
1058 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1059 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1060 struct nvme_command c
;
1062 memset(&c
, 0, sizeof(c
));
1063 c
.common
.opcode
= nvme_admin_async_event
;
1064 c
.common
.command_id
= NVME_AQ_BLK_MQ_DEPTH
;
1066 spin_lock_irq(&nvmeq
->q_lock
);
1067 __nvme_submit_cmd(nvmeq
, &c
);
1068 spin_unlock_irq(&nvmeq
->q_lock
);
1071 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
1073 struct nvme_command c
;
1075 memset(&c
, 0, sizeof(c
));
1076 c
.delete_queue
.opcode
= opcode
;
1077 c
.delete_queue
.qid
= cpu_to_le16(id
);
1079 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1082 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
1083 struct nvme_queue
*nvmeq
)
1085 struct nvme_ctrl
*ctrl
= &dev
->ctrl
;
1086 struct nvme_command c
;
1087 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
1090 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1091 * set. Since URGENT priority is zeroes, it makes all queues
1094 if (ctrl
->quirks
& NVME_QUIRK_MEDIUM_PRIO_SQ
)
1095 flags
|= NVME_SQ_PRIO_MEDIUM
;
1098 * Note: we (ab)use the fact that the prp fields survive if no data
1099 * is attached to the request.
1101 memset(&c
, 0, sizeof(c
));
1102 c
.create_cq
.opcode
= nvme_admin_create_cq
;
1103 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
1104 c
.create_cq
.cqid
= cpu_to_le16(qid
);
1105 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1106 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
1107 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
1109 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1112 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
1113 struct nvme_queue
*nvmeq
)
1115 struct nvme_command c
;
1116 int flags
= NVME_QUEUE_PHYS_CONTIG
;
1119 * Note: we (ab)use the fact that the prp fields survive if no data
1120 * is attached to the request.
1122 memset(&c
, 0, sizeof(c
));
1123 c
.create_sq
.opcode
= nvme_admin_create_sq
;
1124 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
1125 c
.create_sq
.sqid
= cpu_to_le16(qid
);
1126 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
1127 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
1128 c
.create_sq
.cqid
= cpu_to_le16(qid
);
1130 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1133 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
1135 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
1138 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
1140 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
1143 static void abort_endio(struct request
*req
, blk_status_t error
)
1145 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1146 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1148 dev_warn(nvmeq
->dev
->ctrl
.device
,
1149 "Abort status: 0x%x", nvme_req(req
)->status
);
1150 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
1151 blk_mq_free_request(req
);
1154 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1157 /* If true, indicates loss of adapter communication, possibly by a
1158 * NVMe Subsystem reset.
1160 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1162 /* If there is a reset ongoing, we shouldn't reset again. */
1163 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
1166 /* We shouldn't reset unless the controller is on fatal error state
1167 * _or_ if we lost the communication with it.
1169 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1175 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1177 /* Read a config register to help see what died. */
1181 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1183 if (result
== PCIBIOS_SUCCESSFUL
)
1184 dev_warn(dev
->ctrl
.device
,
1185 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1188 dev_warn(dev
->ctrl
.device
,
1189 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1193 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1195 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1196 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1197 struct nvme_dev
*dev
= nvmeq
->dev
;
1198 struct request
*abort_req
;
1199 struct nvme_command cmd
;
1200 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1202 /* If PCI error recovery process is happening, we cannot reset or
1203 * the recovery mechanism will surely fail.
1206 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1207 return BLK_EH_RESET_TIMER
;
1210 * Reset immediately if the controller is failed
1212 if (nvme_should_reset(dev
, csts
)) {
1213 nvme_warn_reset(dev
, csts
);
1214 nvme_dev_disable(dev
, false);
1215 nvme_reset_ctrl(&dev
->ctrl
);
1216 return BLK_EH_HANDLED
;
1220 * Did we miss an interrupt?
1222 if (__nvme_poll(nvmeq
, req
->tag
)) {
1223 dev_warn(dev
->ctrl
.device
,
1224 "I/O %d QID %d timeout, completion polled\n",
1225 req
->tag
, nvmeq
->qid
);
1226 return BLK_EH_HANDLED
;
1230 * Shutdown immediately if controller times out while starting. The
1231 * reset work will see the pci device disabled when it gets the forced
1232 * cancellation error. All outstanding requests are completed on
1233 * shutdown, so we return BLK_EH_HANDLED.
1235 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1236 dev_warn(dev
->ctrl
.device
,
1237 "I/O %d QID %d timeout, disable controller\n",
1238 req
->tag
, nvmeq
->qid
);
1239 nvme_dev_disable(dev
, false);
1240 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1241 return BLK_EH_HANDLED
;
1245 * Shutdown the controller immediately and schedule a reset if the
1246 * command was already aborted once before and still hasn't been
1247 * returned to the driver, or if this is the admin queue.
1249 if (!nvmeq
->qid
|| iod
->aborted
) {
1250 dev_warn(dev
->ctrl
.device
,
1251 "I/O %d QID %d timeout, reset controller\n",
1252 req
->tag
, nvmeq
->qid
);
1253 nvme_dev_disable(dev
, false);
1254 nvme_reset_ctrl(&dev
->ctrl
);
1257 * Mark the request as handled, since the inline shutdown
1258 * forces all outstanding requests to complete.
1260 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1261 return BLK_EH_HANDLED
;
1264 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1265 atomic_inc(&dev
->ctrl
.abort_limit
);
1266 return BLK_EH_RESET_TIMER
;
1270 memset(&cmd
, 0, sizeof(cmd
));
1271 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1272 cmd
.abort
.cid
= req
->tag
;
1273 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1275 dev_warn(nvmeq
->dev
->ctrl
.device
,
1276 "I/O %d QID %d timeout, aborting\n",
1277 req
->tag
, nvmeq
->qid
);
1279 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1280 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1281 if (IS_ERR(abort_req
)) {
1282 atomic_inc(&dev
->ctrl
.abort_limit
);
1283 return BLK_EH_RESET_TIMER
;
1286 abort_req
->timeout
= ADMIN_TIMEOUT
;
1287 abort_req
->end_io_data
= NULL
;
1288 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1291 * The aborted req will be completed on receiving the abort req.
1292 * We enable the timer again. If hit twice, it'll cause a device reset,
1293 * as the device then is in a faulty state.
1295 return BLK_EH_RESET_TIMER
;
1298 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1300 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1301 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1303 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1304 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1308 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1312 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1313 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1314 dev
->ctrl
.queue_count
--;
1315 dev
->queues
[i
] = NULL
;
1316 nvme_free_queue(nvmeq
);
1321 * nvme_suspend_queue - put queue into suspended state
1322 * @nvmeq - queue to suspend
1324 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1328 spin_lock_irq(&nvmeq
->q_lock
);
1329 if (nvmeq
->cq_vector
== -1) {
1330 spin_unlock_irq(&nvmeq
->q_lock
);
1333 vector
= nvmeq
->cq_vector
;
1334 nvmeq
->dev
->online_queues
--;
1335 nvmeq
->cq_vector
= -1;
1336 spin_unlock_irq(&nvmeq
->q_lock
);
1338 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1339 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1341 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1346 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1348 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1352 if (nvme_suspend_queue(nvmeq
))
1356 nvme_shutdown_ctrl(&dev
->ctrl
);
1358 nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1360 spin_lock_irq(&nvmeq
->q_lock
);
1361 nvme_process_cq(nvmeq
);
1362 spin_unlock_irq(&nvmeq
->q_lock
);
1365 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1368 int q_depth
= dev
->q_depth
;
1369 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1370 dev
->ctrl
.page_size
);
1372 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1373 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1374 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1375 q_depth
= div_u64(mem_per_q
, entry_size
);
1378 * Ensure the reduced q_depth is above some threshold where it
1379 * would be better to map queues in system memory with the
1389 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1393 /* CMB SQEs will be mapped before creation */
1394 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
))
1397 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1398 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1399 if (!nvmeq
->sq_cmds
)
1405 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1406 int depth
, int node
)
1408 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1413 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1414 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1418 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1421 nvmeq
->q_dmadev
= dev
->dev
;
1423 spin_lock_init(&nvmeq
->q_lock
);
1425 nvmeq
->cq_phase
= 1;
1426 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1427 nvmeq
->q_depth
= depth
;
1429 nvmeq
->cq_vector
= -1;
1430 dev
->queues
[qid
] = nvmeq
;
1431 dev
->ctrl
.queue_count
++;
1436 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1437 nvmeq
->cq_dma_addr
);
1443 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1445 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1446 int nr
= nvmeq
->dev
->ctrl
.instance
;
1448 if (use_threaded_interrupts
) {
1449 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1450 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1452 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1453 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1457 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1459 struct nvme_dev
*dev
= nvmeq
->dev
;
1461 spin_lock_irq(&nvmeq
->q_lock
);
1464 nvmeq
->cq_phase
= 1;
1465 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1466 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1467 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1468 dev
->online_queues
++;
1469 spin_unlock_irq(&nvmeq
->q_lock
);
1472 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1474 struct nvme_dev
*dev
= nvmeq
->dev
;
1477 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1478 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(nvmeq
->q_depth
),
1479 dev
->ctrl
.page_size
);
1480 nvmeq
->sq_dma_addr
= dev
->cmb_bus_addr
+ offset
;
1481 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1484 nvmeq
->cq_vector
= qid
- 1;
1485 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1487 goto release_vector
;
1489 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1493 nvme_init_queue(nvmeq
, qid
);
1494 result
= queue_request_irq(nvmeq
);
1501 dev
->online_queues
--;
1502 adapter_delete_sq(dev
, qid
);
1504 adapter_delete_cq(dev
, qid
);
1506 nvmeq
->cq_vector
= -1;
1510 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1511 .queue_rq
= nvme_queue_rq
,
1512 .complete
= nvme_pci_complete_rq
,
1513 .init_hctx
= nvme_admin_init_hctx
,
1514 .exit_hctx
= nvme_admin_exit_hctx
,
1515 .init_request
= nvme_init_request
,
1516 .timeout
= nvme_timeout
,
1519 static const struct blk_mq_ops nvme_mq_ops
= {
1520 .queue_rq
= nvme_queue_rq
,
1521 .complete
= nvme_pci_complete_rq
,
1522 .init_hctx
= nvme_init_hctx
,
1523 .init_request
= nvme_init_request
,
1524 .map_queues
= nvme_pci_map_queues
,
1525 .timeout
= nvme_timeout
,
1529 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1531 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1533 * If the controller was reset during removal, it's possible
1534 * user requests may be waiting on a stopped queue. Start the
1535 * queue to flush these to completion.
1537 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1538 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1539 blk_mq_free_tag_set(&dev
->admin_tagset
);
1543 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1545 if (!dev
->ctrl
.admin_q
) {
1546 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1547 dev
->admin_tagset
.nr_hw_queues
= 1;
1549 dev
->admin_tagset
.queue_depth
= NVME_AQ_MQ_TAG_DEPTH
;
1550 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1551 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1552 dev
->admin_tagset
.cmd_size
= nvme_pci_cmd_size(dev
, false);
1553 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1554 dev
->admin_tagset
.driver_data
= dev
;
1556 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1558 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1560 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1561 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1562 blk_mq_free_tag_set(&dev
->admin_tagset
);
1565 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1566 nvme_dev_remove_admin(dev
);
1567 dev
->ctrl
.admin_q
= NULL
;
1571 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1576 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1578 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1581 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1583 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1585 if (size
<= dev
->bar_mapped_size
)
1587 if (size
> pci_resource_len(pdev
, 0))
1591 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1593 dev
->bar_mapped_size
= 0;
1596 dev
->bar_mapped_size
= size
;
1597 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1602 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1606 struct nvme_queue
*nvmeq
;
1608 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1612 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1613 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1615 if (dev
->subsystem
&&
1616 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1617 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1619 result
= nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1623 nvmeq
= dev
->queues
[0];
1625 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1626 dev_to_node(dev
->dev
));
1631 aqa
= nvmeq
->q_depth
- 1;
1634 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1635 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1636 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1638 result
= nvme_enable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1642 nvmeq
->cq_vector
= 0;
1643 nvme_init_queue(nvmeq
, 0);
1644 result
= queue_request_irq(nvmeq
);
1646 nvmeq
->cq_vector
= -1;
1653 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1658 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1659 /* vector == qid - 1, match nvme_create_queue */
1660 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1661 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1667 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1668 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1669 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1675 * Ignore failing Create SQ/CQ commands, we can continue with less
1676 * than the desired aount of queues, and even a controller without
1677 * I/O queues an still be used to issue admin commands. This might
1678 * be useful to upgrade a buggy firmware for example.
1680 return ret
>= 0 ? 0 : ret
;
1683 static ssize_t
nvme_cmb_show(struct device
*dev
,
1684 struct device_attribute
*attr
,
1687 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1689 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1690 ndev
->cmbloc
, ndev
->cmbsz
);
1692 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1694 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1696 u64 szu
, size
, offset
;
1697 resource_size_t bar_size
;
1698 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1702 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1703 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1705 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1710 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1711 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1712 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1713 bar
= NVME_CMB_BIR(dev
->cmbloc
);
1714 bar_size
= pci_resource_len(pdev
, bar
);
1716 if (offset
> bar_size
)
1720 * Controllers may support a CMB size larger than their BAR,
1721 * for example, due to being behind a bridge. Reduce the CMB to
1722 * the reported size of the BAR
1724 if (size
> bar_size
- offset
)
1725 size
= bar_size
- offset
;
1727 cmb
= ioremap_wc(pci_resource_start(pdev
, bar
) + offset
, size
);
1731 dev
->cmb_bus_addr
= pci_bus_address(pdev
, bar
) + offset
;
1732 dev
->cmb_size
= size
;
1736 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1741 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1742 &dev_attr_cmb
.attr
, NULL
);
1747 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1749 u64 dma_addr
= dev
->host_mem_descs_dma
;
1750 struct nvme_command c
;
1753 memset(&c
, 0, sizeof(c
));
1754 c
.features
.opcode
= nvme_admin_set_features
;
1755 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1756 c
.features
.dword11
= cpu_to_le32(bits
);
1757 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1758 ilog2(dev
->ctrl
.page_size
));
1759 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1760 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1761 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1763 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1765 dev_warn(dev
->ctrl
.device
,
1766 "failed to set host mem (err %d, flags %#x).\n",
1772 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1776 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1777 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1778 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1780 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1781 le64_to_cpu(desc
->addr
));
1784 kfree(dev
->host_mem_desc_bufs
);
1785 dev
->host_mem_desc_bufs
= NULL
;
1786 dma_free_coherent(dev
->dev
,
1787 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1788 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1789 dev
->host_mem_descs
= NULL
;
1790 dev
->nr_host_mem_descs
= 0;
1793 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1796 struct nvme_host_mem_buf_desc
*descs
;
1797 u32 max_entries
, len
;
1798 dma_addr_t descs_dma
;
1803 tmp
= (preferred
+ chunk_size
- 1);
1804 do_div(tmp
, chunk_size
);
1807 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1808 max_entries
= dev
->ctrl
.hmmaxd
;
1810 descs
= dma_zalloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1811 &descs_dma
, GFP_KERNEL
);
1815 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1817 goto out_free_descs
;
1819 for (size
= 0; size
< preferred
&& i
< max_entries
; size
+= len
) {
1820 dma_addr_t dma_addr
;
1822 len
= min_t(u64
, chunk_size
, preferred
- size
);
1823 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1824 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1828 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1829 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1836 dev
->nr_host_mem_descs
= i
;
1837 dev
->host_mem_size
= size
;
1838 dev
->host_mem_descs
= descs
;
1839 dev
->host_mem_descs_dma
= descs_dma
;
1840 dev
->host_mem_desc_bufs
= bufs
;
1845 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1847 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1848 le64_to_cpu(descs
[i
].addr
));
1853 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1856 dev
->host_mem_descs
= NULL
;
1860 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1864 /* start big and work our way down */
1865 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1866 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1868 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1869 if (!min
|| dev
->host_mem_size
>= min
)
1871 nvme_free_host_mem(dev
);
1878 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1880 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1881 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1882 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1883 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1886 preferred
= min(preferred
, max
);
1888 dev_warn(dev
->ctrl
.device
,
1889 "min host memory (%lld MiB) above limit (%d MiB).\n",
1890 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1891 nvme_free_host_mem(dev
);
1896 * If we already have a buffer allocated check if we can reuse it.
1898 if (dev
->host_mem_descs
) {
1899 if (dev
->host_mem_size
>= min
)
1900 enable_bits
|= NVME_HOST_MEM_RETURN
;
1902 nvme_free_host_mem(dev
);
1905 if (!dev
->host_mem_descs
) {
1906 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
1907 dev_warn(dev
->ctrl
.device
,
1908 "failed to allocate host memory buffer.\n");
1909 return 0; /* controller must work without HMB */
1912 dev_info(dev
->ctrl
.device
,
1913 "allocated %lld MiB host memory buffer.\n",
1914 dev
->host_mem_size
>> ilog2(SZ_1M
));
1917 ret
= nvme_set_host_mem(dev
, enable_bits
);
1919 nvme_free_host_mem(dev
);
1923 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1925 struct nvme_queue
*adminq
= dev
->queues
[0];
1926 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1927 int result
, nr_io_queues
;
1930 nr_io_queues
= num_possible_cpus();
1931 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1935 if (nr_io_queues
== 0)
1938 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1939 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1940 sizeof(struct nvme_command
));
1942 dev
->q_depth
= result
;
1944 nvme_release_cmb(dev
);
1948 size
= db_bar_size(dev
, nr_io_queues
);
1949 result
= nvme_remap_bar(dev
, size
);
1952 if (!--nr_io_queues
)
1955 adminq
->q_db
= dev
->dbs
;
1957 /* Deregister the admin queue's interrupt */
1958 pci_free_irq(pdev
, 0, adminq
);
1961 * If we enable msix early due to not intx, disable it again before
1962 * setting up the full range we need.
1964 pci_free_irq_vectors(pdev
);
1965 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1966 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1967 if (nr_io_queues
<= 0)
1969 dev
->max_qid
= nr_io_queues
;
1972 * Should investigate if there's a performance win from allocating
1973 * more queues than interrupt vectors; it might allow the submission
1974 * path to scale better, even if the receive path is limited by the
1975 * number of interrupts.
1978 result
= queue_request_irq(adminq
);
1980 adminq
->cq_vector
= -1;
1983 return nvme_create_io_queues(dev
);
1986 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1988 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1990 blk_mq_free_request(req
);
1991 complete(&nvmeq
->dev
->ioq_wait
);
1994 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1996 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1999 unsigned long flags
;
2002 * We might be called with the AQ q_lock held
2003 * and the I/O queue q_lock should always
2004 * nest inside the AQ one.
2006 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
2007 SINGLE_DEPTH_NESTING
);
2008 nvme_process_cq(nvmeq
);
2009 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
2012 nvme_del_queue_end(req
, error
);
2015 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
2017 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
2018 struct request
*req
;
2019 struct nvme_command cmd
;
2021 memset(&cmd
, 0, sizeof(cmd
));
2022 cmd
.delete_queue
.opcode
= opcode
;
2023 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
2025 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
2027 return PTR_ERR(req
);
2029 req
->timeout
= ADMIN_TIMEOUT
;
2030 req
->end_io_data
= nvmeq
;
2032 blk_execute_rq_nowait(q
, NULL
, req
, false,
2033 opcode
== nvme_admin_delete_cq
?
2034 nvme_del_cq_end
: nvme_del_queue_end
);
2038 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
2041 unsigned long timeout
;
2042 u8 opcode
= nvme_admin_delete_sq
;
2044 for (pass
= 0; pass
< 2; pass
++) {
2045 int sent
= 0, i
= queues
;
2047 reinit_completion(&dev
->ioq_wait
);
2049 timeout
= ADMIN_TIMEOUT
;
2050 for (; i
> 0; i
--, sent
++)
2051 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
2055 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
2061 opcode
= nvme_admin_delete_cq
;
2066 * Return: error value if an error occurred setting up the queues or calling
2067 * Identify Device. 0 if these succeeded, even if adding some of the
2068 * namespaces failed. At the moment, these failures are silent. TBD which
2069 * failures should be reported.
2071 static int nvme_dev_add(struct nvme_dev
*dev
)
2073 if (!dev
->ctrl
.tagset
) {
2074 dev
->tagset
.ops
= &nvme_mq_ops
;
2075 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
2076 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
2077 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
2078 dev
->tagset
.queue_depth
=
2079 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
2080 dev
->tagset
.cmd_size
= nvme_pci_cmd_size(dev
, false);
2081 if ((dev
->ctrl
.sgls
& ((1 << 0) | (1 << 1))) && sgl_threshold
) {
2082 dev
->tagset
.cmd_size
= max(dev
->tagset
.cmd_size
,
2083 nvme_pci_cmd_size(dev
, true));
2085 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
2086 dev
->tagset
.driver_data
= dev
;
2088 if (blk_mq_alloc_tag_set(&dev
->tagset
))
2090 dev
->ctrl
.tagset
= &dev
->tagset
;
2092 nvme_dbbuf_set(dev
);
2094 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
2096 /* Free previously allocated queues that are no longer usable */
2097 nvme_free_queues(dev
, dev
->online_queues
);
2103 static int nvme_pci_enable(struct nvme_dev
*dev
)
2105 int result
= -ENOMEM
;
2106 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2108 if (pci_enable_device_mem(pdev
))
2111 pci_set_master(pdev
);
2113 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
2114 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
2117 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
2123 * Some devices and/or platforms don't advertise or work with INTx
2124 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2125 * adjust this later.
2127 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
2131 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
2133 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
2135 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
2136 dev
->dbs
= dev
->bar
+ 4096;
2139 * Temporary fix for the Apple controller found in the MacBook8,1 and
2140 * some MacBook7,1 to avoid controller resets and data loss.
2142 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
2144 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
2145 "set queue depth=%u to work around controller resets\n",
2147 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
2148 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
2149 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
2151 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
2152 "set queue depth=%u\n", dev
->q_depth
);
2156 * CMBs can currently only exist on >=1.2 PCIe devices. We only
2157 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
2158 * has no name we can pass NULL as final argument to
2159 * sysfs_add_file_to_group.
2162 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
2163 dev
->cmb
= nvme_map_cmb(dev
);
2165 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
2166 &dev_attr_cmb
.attr
, NULL
))
2167 dev_warn(dev
->ctrl
.device
,
2168 "failed to add sysfs attribute for CMB\n");
2172 pci_enable_pcie_error_reporting(pdev
);
2173 pci_save_state(pdev
);
2177 pci_disable_device(pdev
);
2181 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2185 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2188 static void nvme_pci_disable(struct nvme_dev
*dev
)
2190 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2192 nvme_release_cmb(dev
);
2193 pci_free_irq_vectors(pdev
);
2195 if (pci_is_enabled(pdev
)) {
2196 pci_disable_pcie_error_reporting(pdev
);
2197 pci_disable_device(pdev
);
2201 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2205 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2207 mutex_lock(&dev
->shutdown_lock
);
2208 if (pci_is_enabled(pdev
)) {
2209 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2211 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2212 dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
2213 nvme_start_freeze(&dev
->ctrl
);
2214 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2215 pdev
->error_state
!= pci_channel_io_normal
);
2219 * Give the controller a chance to complete all entered requests if
2220 * doing a safe shutdown.
2224 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2227 * If the controller is still alive tell it to stop using the
2228 * host memory buffer. In theory the shutdown / reset should
2229 * make sure that it doesn't access the host memoery anymore,
2230 * but I'd rather be safe than sorry..
2232 if (dev
->host_mem_descs
)
2233 nvme_set_host_mem(dev
, 0);
2236 nvme_stop_queues(&dev
->ctrl
);
2238 queues
= dev
->online_queues
- 1;
2239 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
2240 nvme_suspend_queue(dev
->queues
[i
]);
2243 /* A device might become IO incapable very soon during
2244 * probe, before the admin queue is configured. Thus,
2245 * queue_count can be 0 here.
2247 if (dev
->ctrl
.queue_count
)
2248 nvme_suspend_queue(dev
->queues
[0]);
2250 nvme_disable_io_queues(dev
, queues
);
2251 nvme_disable_admin_queue(dev
, shutdown
);
2253 nvme_pci_disable(dev
);
2255 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2256 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2259 * The driver will not be starting up queues again if shutting down so
2260 * must flush all entered requests to their failed completion to avoid
2261 * deadlocking blk-mq hot-cpu notifier.
2264 nvme_start_queues(&dev
->ctrl
);
2265 mutex_unlock(&dev
->shutdown_lock
);
2268 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2270 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2271 PAGE_SIZE
, PAGE_SIZE
, 0);
2272 if (!dev
->prp_page_pool
)
2275 /* Optimisation for I/Os between 4k and 128k */
2276 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2278 if (!dev
->prp_small_pool
) {
2279 dma_pool_destroy(dev
->prp_page_pool
);
2285 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2287 dma_pool_destroy(dev
->prp_page_pool
);
2288 dma_pool_destroy(dev
->prp_small_pool
);
2291 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2293 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2295 nvme_dbbuf_dma_free(dev
);
2296 put_device(dev
->dev
);
2297 if (dev
->tagset
.tags
)
2298 blk_mq_free_tag_set(&dev
->tagset
);
2299 if (dev
->ctrl
.admin_q
)
2300 blk_put_queue(dev
->ctrl
.admin_q
);
2302 free_opal_dev(dev
->ctrl
.opal_dev
);
2306 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2308 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2310 nvme_get_ctrl(&dev
->ctrl
);
2311 nvme_dev_disable(dev
, false);
2312 if (!queue_work(nvme_wq
, &dev
->remove_work
))
2313 nvme_put_ctrl(&dev
->ctrl
);
2316 static void nvme_reset_work(struct work_struct
*work
)
2318 struct nvme_dev
*dev
=
2319 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2320 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2321 int result
= -ENODEV
;
2323 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2327 * If we're called to reset a live controller first shut it down before
2330 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2331 nvme_dev_disable(dev
, false);
2332 nvme_sync_queues(&dev
->ctrl
);
2334 result
= nvme_pci_enable(dev
);
2338 result
= nvme_pci_configure_admin_queue(dev
);
2342 result
= nvme_alloc_admin_tags(dev
);
2346 result
= nvme_init_identify(&dev
->ctrl
);
2350 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2351 if (!dev
->ctrl
.opal_dev
)
2352 dev
->ctrl
.opal_dev
=
2353 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2354 else if (was_suspend
)
2355 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2357 free_opal_dev(dev
->ctrl
.opal_dev
);
2358 dev
->ctrl
.opal_dev
= NULL
;
2361 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2362 result
= nvme_dbbuf_dma_alloc(dev
);
2365 "unable to allocate dma for dbbuf\n");
2368 if (dev
->ctrl
.hmpre
) {
2369 result
= nvme_setup_host_mem(dev
);
2374 result
= nvme_setup_io_queues(dev
);
2379 * Keep the controller around but remove all namespaces if we don't have
2380 * any working I/O queue.
2382 if (dev
->online_queues
< 2) {
2383 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2384 nvme_kill_queues(&dev
->ctrl
);
2385 nvme_remove_namespaces(&dev
->ctrl
);
2387 nvme_start_queues(&dev
->ctrl
);
2388 nvme_wait_freeze(&dev
->ctrl
);
2390 nvme_unfreeze(&dev
->ctrl
);
2393 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2394 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2398 nvme_start_ctrl(&dev
->ctrl
);
2402 nvme_remove_dead_ctrl(dev
, result
);
2405 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2407 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2408 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2410 nvme_kill_queues(&dev
->ctrl
);
2411 if (pci_get_drvdata(pdev
))
2412 device_release_driver(&pdev
->dev
);
2413 nvme_put_ctrl(&dev
->ctrl
);
2416 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2418 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2422 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2424 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2428 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2430 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2434 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2436 .module
= THIS_MODULE
,
2437 .flags
= NVME_F_METADATA_SUPPORTED
,
2438 .reg_read32
= nvme_pci_reg_read32
,
2439 .reg_write32
= nvme_pci_reg_write32
,
2440 .reg_read64
= nvme_pci_reg_read64
,
2441 .free_ctrl
= nvme_pci_free_ctrl
,
2442 .submit_async_event
= nvme_pci_submit_async_event
,
2445 static int nvme_dev_map(struct nvme_dev
*dev
)
2447 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2449 if (pci_request_mem_regions(pdev
, "nvme"))
2452 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2457 pci_release_mem_regions(pdev
);
2461 static unsigned long check_vendor_combination_bug(struct pci_dev
*pdev
)
2463 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2465 * Several Samsung devices seem to drop off the PCIe bus
2466 * randomly when APST is on and uses the deepest sleep state.
2467 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2468 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2469 * 950 PRO 256GB", but it seems to be restricted to two Dell
2472 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2473 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2474 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2475 return NVME_QUIRK_NO_DEEPEST_PS
;
2476 } else if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa804) {
2478 * Samsung SSD 960 EVO drops off the PCIe bus after system
2479 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2480 * within few minutes after bootup on a Coffee Lake board -
2483 if (dmi_match(DMI_BOARD_VENDOR
, "ASUSTeK COMPUTER INC.") &&
2484 (dmi_match(DMI_BOARD_NAME
, "PRIME B350M-A") ||
2485 dmi_match(DMI_BOARD_NAME
, "PRIME Z370-A")))
2486 return NVME_QUIRK_NO_APST
;
2492 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2494 int node
, result
= -ENOMEM
;
2495 struct nvme_dev
*dev
;
2496 unsigned long quirks
= id
->driver_data
;
2498 node
= dev_to_node(&pdev
->dev
);
2499 if (node
== NUMA_NO_NODE
)
2500 set_dev_node(&pdev
->dev
, first_memory_node
);
2502 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2505 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2510 dev
->dev
= get_device(&pdev
->dev
);
2511 pci_set_drvdata(pdev
, dev
);
2513 result
= nvme_dev_map(dev
);
2517 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2518 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2519 mutex_init(&dev
->shutdown_lock
);
2520 init_completion(&dev
->ioq_wait
);
2522 result
= nvme_setup_prp_pools(dev
);
2526 quirks
|= check_vendor_combination_bug(pdev
);
2528 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2533 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2534 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2536 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2540 nvme_release_prp_pools(dev
);
2542 nvme_dev_unmap(dev
);
2544 put_device(dev
->dev
);
2551 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2553 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2554 nvme_dev_disable(dev
, false);
2557 static void nvme_reset_done(struct pci_dev
*pdev
)
2559 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2560 nvme_reset_ctrl(&dev
->ctrl
);
2563 static void nvme_shutdown(struct pci_dev
*pdev
)
2565 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2566 nvme_dev_disable(dev
, true);
2570 * The driver's remove may be called on a device in a partially initialized
2571 * state. This function must not have any dependencies on the device state in
2574 static void nvme_remove(struct pci_dev
*pdev
)
2576 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2578 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2580 cancel_work_sync(&dev
->ctrl
.reset_work
);
2581 pci_set_drvdata(pdev
, NULL
);
2583 if (!pci_device_is_present(pdev
)) {
2584 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2585 nvme_dev_disable(dev
, false);
2588 flush_work(&dev
->ctrl
.reset_work
);
2589 nvme_stop_ctrl(&dev
->ctrl
);
2590 nvme_remove_namespaces(&dev
->ctrl
);
2591 nvme_dev_disable(dev
, true);
2592 nvme_free_host_mem(dev
);
2593 nvme_dev_remove_admin(dev
);
2594 nvme_free_queues(dev
, 0);
2595 nvme_uninit_ctrl(&dev
->ctrl
);
2596 nvme_release_prp_pools(dev
);
2597 nvme_dev_unmap(dev
);
2598 nvme_put_ctrl(&dev
->ctrl
);
2601 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2606 if (pci_vfs_assigned(pdev
)) {
2607 dev_warn(&pdev
->dev
,
2608 "Cannot disable SR-IOV VFs while assigned\n");
2611 pci_disable_sriov(pdev
);
2615 ret
= pci_enable_sriov(pdev
, numvfs
);
2616 return ret
? ret
: numvfs
;
2619 #ifdef CONFIG_PM_SLEEP
2620 static int nvme_get_power_state(struct nvme_ctrl
*ctrl
, u32
*ps
)
2622 return nvme_get_features(ctrl
, NVME_FEAT_POWER_MGMT
, 0, NULL
, 0, ps
);
2625 static int nvme_set_power_state(struct nvme_ctrl
*ctrl
, u32 ps
)
2627 return nvme_set_features(ctrl
, NVME_FEAT_POWER_MGMT
, ps
, NULL
, 0, NULL
);
2630 static int nvme_resume(struct device
*dev
)
2632 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2633 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2635 if (pm_resume_via_firmware() || !ctrl
->npss
||
2636 nvme_set_power_state(ctrl
, ndev
->last_ps
) != 0)
2637 nvme_reset_ctrl(ctrl
);
2641 static int nvme_suspend(struct device
*dev
)
2643 struct pci_dev
*pdev
= to_pci_dev(dev
);
2644 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2645 struct nvme_ctrl
*ctrl
= &ndev
->ctrl
;
2649 * The platform does not remove power for a kernel managed suspend so
2650 * use host managed nvme power settings for lowest idle power if
2651 * possible. This should have quicker resume latency than a full device
2652 * shutdown. But if the firmware is involved after the suspend or the
2653 * device does not support any non-default power states, shut down the
2656 if (pm_suspend_via_firmware() || !ctrl
->npss
) {
2657 nvme_dev_disable(ndev
, true);
2661 nvme_start_freeze(ctrl
);
2662 nvme_wait_freeze(ctrl
);
2663 nvme_sync_queues(ctrl
);
2665 if (ctrl
->state
!= NVME_CTRL_LIVE
)
2669 ret
= nvme_get_power_state(ctrl
, &ndev
->last_ps
);
2673 ret
= nvme_set_power_state(ctrl
, ctrl
->npss
);
2679 * Clearing npss forces a controller reset on resume. The
2680 * correct value will be resdicovered then.
2682 nvme_dev_disable(ndev
, true);
2688 * A saved state prevents pci pm from generically controlling the
2689 * device's power. If we're using protocol specific settings, we don't
2690 * want pci interfering.
2692 pci_save_state(pdev
);
2694 nvme_unfreeze(ctrl
);
2698 static int nvme_simple_suspend(struct device
*dev
)
2700 struct nvme_dev
*ndev
= pci_get_drvdata(to_pci_dev(dev
));
2702 nvme_dev_disable(ndev
, true);
2706 static int nvme_simple_resume(struct device
*dev
)
2708 struct pci_dev
*pdev
= to_pci_dev(dev
);
2709 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2711 nvme_reset_ctrl(&ndev
->ctrl
);
2715 const struct dev_pm_ops nvme_dev_pm_ops
= {
2716 .suspend
= nvme_suspend
,
2717 .resume
= nvme_resume
,
2718 .freeze
= nvme_simple_suspend
,
2719 .thaw
= nvme_simple_resume
,
2720 .poweroff
= nvme_simple_suspend
,
2721 .restore
= nvme_simple_resume
,
2725 #define nvme_dev_pm_ops NULL
2728 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2729 pci_channel_state_t state
)
2731 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2734 * A frozen channel requires a reset. When detected, this method will
2735 * shutdown the controller to quiesce. The controller will be restarted
2736 * after the slot reset through driver's slot_reset callback.
2739 case pci_channel_io_normal
:
2740 return PCI_ERS_RESULT_CAN_RECOVER
;
2741 case pci_channel_io_frozen
:
2742 dev_warn(dev
->ctrl
.device
,
2743 "frozen state error detected, reset controller\n");
2744 nvme_dev_disable(dev
, false);
2745 return PCI_ERS_RESULT_NEED_RESET
;
2746 case pci_channel_io_perm_failure
:
2747 dev_warn(dev
->ctrl
.device
,
2748 "failure state error detected, request disconnect\n");
2749 return PCI_ERS_RESULT_DISCONNECT
;
2751 return PCI_ERS_RESULT_NEED_RESET
;
2754 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2756 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2758 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2759 pci_restore_state(pdev
);
2760 nvme_reset_ctrl(&dev
->ctrl
);
2761 return PCI_ERS_RESULT_RECOVERED
;
2764 static void nvme_error_resume(struct pci_dev
*pdev
)
2766 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2768 flush_work(&dev
->ctrl
.reset_work
);
2769 pci_cleanup_aer_uncorrect_error_status(pdev
);
2772 static const struct pci_error_handlers nvme_err_handler
= {
2773 .error_detected
= nvme_error_detected
,
2774 .slot_reset
= nvme_slot_reset
,
2775 .resume
= nvme_error_resume
,
2776 .reset_prepare
= nvme_reset_prepare
,
2777 .reset_done
= nvme_reset_done
,
2780 static const struct pci_device_id nvme_id_table
[] = {
2781 { PCI_VDEVICE(INTEL
, 0x0953),
2782 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2783 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2784 { PCI_VDEVICE(INTEL
, 0x0a53),
2785 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2786 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2787 { PCI_VDEVICE(INTEL
, 0x0a54),
2788 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2789 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2790 { PCI_VDEVICE(INTEL
, 0x0a55),
2791 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2792 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2793 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2794 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
|
2795 NVME_QUIRK_MEDIUM_PRIO_SQ
},
2796 { PCI_VDEVICE(INTEL
, 0xf1a6), /* Intel 760p/Pro 7600p */
2797 .driver_data
= NVME_QUIRK_IGNORE_DEV_SUBNQN
, },
2798 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2799 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2800 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2801 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2802 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2803 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2804 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2805 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2806 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2807 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2808 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2809 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2810 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2811 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2812 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2813 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2814 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2815 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2816 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2817 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2818 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2821 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2823 static struct pci_driver nvme_driver
= {
2825 .id_table
= nvme_id_table
,
2826 .probe
= nvme_probe
,
2827 .remove
= nvme_remove
,
2828 .shutdown
= nvme_shutdown
,
2830 .pm
= &nvme_dev_pm_ops
,
2832 .sriov_configure
= nvme_pci_sriov_configure
,
2833 .err_handler
= &nvme_err_handler
,
2836 static int __init
nvme_init(void)
2838 return pci_register_driver(&nvme_driver
);
2841 static void __exit
nvme_exit(void)
2843 pci_unregister_driver(&nvme_driver
);
2844 flush_workqueue(nvme_wq
);
2848 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2849 MODULE_LICENSE("GPL");
2850 MODULE_VERSION("1.0");
2851 module_init(nvme_init
);
2852 module_exit(nvme_exit
);