]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/pci/quirks.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
UBUNTU: SAUCE: pci/nvme: prevent WDC PC SN720 NVMe from entering D3 and being disabled
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains work-arounds for many known PCI hardware
4 * bugs. Devices present only on certain architectures (host
5 * bridges et cetera) should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the
12 * USB quirks file, where their drivers can access reuse it.
13 */
14
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/kallsyms.h>
23 #include <linux/dmi.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/ktime.h>
28 #include <linux/mm.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <asm/dma.h> /* isa_dma_bridge_buggy */
31 #include "pci.h"
32
33 /*
34 * Decoding should be disabled for a PCI device during BAR sizing to avoid
35 * conflict. But doing so may cause problems on host bridge and perhaps other
36 * key system devices. For devices that need to have mmio decoding always-on,
37 * we need to set the dev->mmio_always_on bit.
38 */
39 static void quirk_mmio_always_on(struct pci_dev *dev)
40 {
41 dev->mmio_always_on = 1;
42 }
43 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
44 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
45
46 /* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed
47 * by IO resource file, and need to skip the files
48 */
49 static void quirk_marvell_mask_bar(struct pci_dev *dev)
50 {
51 int i;
52
53 for (i = 0; i < 5; i++)
54 if (dev->resource[i].start)
55 dev->resource[i].start =
56 dev->resource[i].end = 0;
57 }
58 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
59 quirk_marvell_mask_bar);
60
61 /* The Mellanox Tavor device gives false positive parity errors
62 * Mark this device with a broken_parity_status, to allow
63 * PCI scanning code to "skip" this now blacklisted device.
64 */
65 static void quirk_mellanox_tavor(struct pci_dev *dev)
66 {
67 dev->broken_parity_status = 1; /* This device gives false positives */
68 }
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
70 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
71
72 /* Deal with broken BIOSes that neglect to enable passive release,
73 which can cause problems in combination with the 82441FX/PPro MTRRs */
74 static void quirk_passive_release(struct pci_dev *dev)
75 {
76 struct pci_dev *d = NULL;
77 unsigned char dlc;
78
79 /* We have to make sure a particular bit is set in the PIIX3
80 ISA bridge, so we have to go out and find it. */
81 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
82 pci_read_config_byte(d, 0x82, &dlc);
83 if (!(dlc & 1<<1)) {
84 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
85 dlc |= 1<<1;
86 pci_write_config_byte(d, 0x82, dlc);
87 }
88 }
89 }
90 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
91 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
92
93 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
94 but VIA don't answer queries. If you happen to have good contacts at VIA
95 ask them for me please -- Alan
96
97 This appears to be BIOS not version dependent. So presumably there is a
98 chipset level fix */
99
100 static void quirk_isa_dma_hangs(struct pci_dev *dev)
101 {
102 if (!isa_dma_bridge_buggy) {
103 isa_dma_bridge_buggy = 1;
104 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
105 }
106 }
107 /*
108 * Its not totally clear which chipsets are the problematic ones
109 * We know 82C586 and 82C596 variants are affected.
110 */
111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
118
119 /*
120 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
121 * for some HT machines to use C4 w/o hanging.
122 */
123 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
124 {
125 u32 pmbase;
126 u16 pm1a;
127
128 pci_read_config_dword(dev, 0x40, &pmbase);
129 pmbase = pmbase & 0xff80;
130 pm1a = inw(pmbase);
131
132 if (pm1a & 0x10) {
133 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
134 outw(0x10, pmbase);
135 }
136 }
137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
138
139 /*
140 * Chipsets where PCI->PCI transfers vanish or hang
141 */
142 static void quirk_nopcipci(struct pci_dev *dev)
143 {
144 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
145 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
146 pci_pci_problems |= PCIPCI_FAIL;
147 }
148 }
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
151
152 static void quirk_nopciamd(struct pci_dev *dev)
153 {
154 u8 rev;
155 pci_read_config_byte(dev, 0x08, &rev);
156 if (rev == 0x13) {
157 /* Erratum 24 */
158 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
159 pci_pci_problems |= PCIAGP_FAIL;
160 }
161 }
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
163
164 /*
165 * Triton requires workarounds to be used by the drivers
166 */
167 static void quirk_triton(struct pci_dev *dev)
168 {
169 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
170 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
171 pci_pci_problems |= PCIPCI_TRITON;
172 }
173 }
174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
178
179 /*
180 * VIA Apollo KT133 needs PCI latency patch
181 * Made according to a windows driver based patch by George E. Breese
182 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
183 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
184 * the info on which Mr Breese based his work.
185 *
186 * Updated based on further information from the site and also on
187 * information provided by VIA
188 */
189 static void quirk_vialatency(struct pci_dev *dev)
190 {
191 struct pci_dev *p;
192 u8 busarb;
193 /* Ok we have a potential problem chipset here. Now see if we have
194 a buggy southbridge */
195
196 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
197 if (p != NULL) {
198 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
199 /* Check for buggy part revisions */
200 if (p->revision < 0x40 || p->revision > 0x42)
201 goto exit;
202 } else {
203 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
204 if (p == NULL) /* No problem parts */
205 goto exit;
206 /* Check for buggy part revisions */
207 if (p->revision < 0x10 || p->revision > 0x12)
208 goto exit;
209 }
210
211 /*
212 * Ok we have the problem. Now set the PCI master grant to
213 * occur every master grant. The apparent bug is that under high
214 * PCI load (quite common in Linux of course) you can get data
215 * loss when the CPU is held off the bus for 3 bus master requests
216 * This happens to include the IDE controllers....
217 *
218 * VIA only apply this fix when an SB Live! is present but under
219 * both Linux and Windows this isn't enough, and we have seen
220 * corruption without SB Live! but with things like 3 UDMA IDE
221 * controllers. So we ignore that bit of the VIA recommendation..
222 */
223
224 pci_read_config_byte(dev, 0x76, &busarb);
225 /* Set bit 4 and bi 5 of byte 76 to 0x01
226 "Master priority rotation on every PCI master grant */
227 busarb &= ~(1<<5);
228 busarb |= (1<<4);
229 pci_write_config_byte(dev, 0x76, busarb);
230 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
231 exit:
232 pci_dev_put(p);
233 }
234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
237 /* Must restore this on a resume from RAM */
238 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
240 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
241
242 /*
243 * VIA Apollo VP3 needs ETBF on BT848/878
244 */
245 static void quirk_viaetbf(struct pci_dev *dev)
246 {
247 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
248 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
249 pci_pci_problems |= PCIPCI_VIAETBF;
250 }
251 }
252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
253
254 static void quirk_vsfx(struct pci_dev *dev)
255 {
256 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
257 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
258 pci_pci_problems |= PCIPCI_VSFX;
259 }
260 }
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
262
263 /*
264 * Ali Magik requires workarounds to be used by the drivers
265 * that DMA to AGP space. Latency must be set to 0xA and triton
266 * workaround applied too
267 * [Info kindly provided by ALi]
268 */
269 static void quirk_alimagik(struct pci_dev *dev)
270 {
271 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
272 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
273 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
274 }
275 }
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
278
279 /*
280 * Natoma has some interesting boundary conditions with Zoran stuff
281 * at least
282 */
283 static void quirk_natoma(struct pci_dev *dev)
284 {
285 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
286 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
287 pci_pci_problems |= PCIPCI_NATOMA;
288 }
289 }
290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
296
297 /*
298 * This chip can cause PCI parity errors if config register 0xA0 is read
299 * while DMAs are occurring.
300 */
301 static void quirk_citrine(struct pci_dev *dev)
302 {
303 dev->cfg_size = 0xA0;
304 }
305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
306
307 /*
308 * This chip can cause bus lockups if config addresses above 0x600
309 * are read or written.
310 */
311 static void quirk_nfp6000(struct pci_dev *dev)
312 {
313 dev->cfg_size = 0x600;
314 }
315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
318
319 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
320 static void quirk_extend_bar_to_page(struct pci_dev *dev)
321 {
322 int i;
323
324 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
325 struct resource *r = &dev->resource[i];
326
327 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
328 r->end = PAGE_SIZE - 1;
329 r->start = 0;
330 r->flags |= IORESOURCE_UNSET;
331 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
332 i, r);
333 }
334 }
335 }
336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
337
338 /*
339 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
340 * If it's needed, re-allocate the region.
341 */
342 static void quirk_s3_64M(struct pci_dev *dev)
343 {
344 struct resource *r = &dev->resource[0];
345
346 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
347 r->flags |= IORESOURCE_UNSET;
348 r->start = 0;
349 r->end = 0x3ffffff;
350 }
351 }
352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
354
355 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
356 const char *name)
357 {
358 u32 region;
359 struct pci_bus_region bus_region;
360 struct resource *res = dev->resource + pos;
361
362 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
363
364 if (!region)
365 return;
366
367 res->name = pci_name(dev);
368 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
369 res->flags |=
370 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
371 region &= ~(size - 1);
372
373 /* Convert from PCI bus to resource space */
374 bus_region.start = region;
375 bus_region.end = region + size - 1;
376 pcibios_bus_to_resource(dev->bus, res, &bus_region);
377
378 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
379 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
380 }
381
382 /*
383 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
384 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
385 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
386 * (which conflicts w/ BAR1's memory range).
387 *
388 * CS553x's ISA PCI BARs may also be read-only (ref:
389 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
390 */
391 static void quirk_cs5536_vsa(struct pci_dev *dev)
392 {
393 static char *name = "CS5536 ISA bridge";
394
395 if (pci_resource_len(dev, 0) != 8) {
396 quirk_io(dev, 0, 8, name); /* SMB */
397 quirk_io(dev, 1, 256, name); /* GPIO */
398 quirk_io(dev, 2, 64, name); /* MFGPT */
399 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
400 name);
401 }
402 }
403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
404
405 static void quirk_io_region(struct pci_dev *dev, int port,
406 unsigned size, int nr, const char *name)
407 {
408 u16 region;
409 struct pci_bus_region bus_region;
410 struct resource *res = dev->resource + nr;
411
412 pci_read_config_word(dev, port, &region);
413 region &= ~(size - 1);
414
415 if (!region)
416 return;
417
418 res->name = pci_name(dev);
419 res->flags = IORESOURCE_IO;
420
421 /* Convert from PCI bus to resource space */
422 bus_region.start = region;
423 bus_region.end = region + size - 1;
424 pcibios_bus_to_resource(dev->bus, res, &bus_region);
425
426 if (!pci_claim_resource(dev, nr))
427 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
428 }
429
430 /*
431 * ATI Northbridge setups MCE the processor if you even
432 * read somewhere between 0x3b0->0x3bb or read 0x3d3
433 */
434 static void quirk_ati_exploding_mce(struct pci_dev *dev)
435 {
436 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
437 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
438 request_region(0x3b0, 0x0C, "RadeonIGP");
439 request_region(0x3d3, 0x01, "RadeonIGP");
440 }
441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
442
443 /*
444 * In the AMD NL platform, this device ([1022:7912]) has a class code of
445 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
446 * claim it.
447 * But the dwc3 driver is a more specific driver for this device, and we'd
448 * prefer to use it instead of xhci. To prevent xhci from claiming the
449 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
450 * defines as "USB device (not host controller)". The dwc3 driver can then
451 * claim it based on its Vendor and Device ID.
452 */
453 static void quirk_amd_nl_class(struct pci_dev *pdev)
454 {
455 u32 class = pdev->class;
456
457 /* Use "USB Device (not host controller)" class */
458 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
459 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
460 class, pdev->class);
461 }
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
463 quirk_amd_nl_class);
464
465 /*
466 * Let's make the southbridge information explicit instead
467 * of having to worry about people probing the ACPI areas,
468 * for example.. (Yes, it happens, and if you read the wrong
469 * ACPI register it will put the machine to sleep with no
470 * way of waking it up again. Bummer).
471 *
472 * ALI M7101: Two IO regions pointed to by words at
473 * 0xE0 (64 bytes of ACPI registers)
474 * 0xE2 (32 bytes of SMB registers)
475 */
476 static void quirk_ali7101_acpi(struct pci_dev *dev)
477 {
478 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
479 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
480 }
481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
482
483 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
484 {
485 u32 devres;
486 u32 mask, size, base;
487
488 pci_read_config_dword(dev, port, &devres);
489 if ((devres & enable) != enable)
490 return;
491 mask = (devres >> 16) & 15;
492 base = devres & 0xffff;
493 size = 16;
494 for (;;) {
495 unsigned bit = size >> 1;
496 if ((bit & mask) == bit)
497 break;
498 size = bit;
499 }
500 /*
501 * For now we only print it out. Eventually we'll want to
502 * reserve it (at least if it's in the 0x1000+ range), but
503 * let's get enough confirmation reports first.
504 */
505 base &= -size;
506 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
507 base + size - 1);
508 }
509
510 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
511 {
512 u32 devres;
513 u32 mask, size, base;
514
515 pci_read_config_dword(dev, port, &devres);
516 if ((devres & enable) != enable)
517 return;
518 base = devres & 0xffff0000;
519 mask = (devres & 0x3f) << 16;
520 size = 128 << 16;
521 for (;;) {
522 unsigned bit = size >> 1;
523 if ((bit & mask) == bit)
524 break;
525 size = bit;
526 }
527 /*
528 * For now we only print it out. Eventually we'll want to
529 * reserve it, but let's get enough confirmation reports first.
530 */
531 base &= -size;
532 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
533 base + size - 1);
534 }
535
536 /*
537 * PIIX4 ACPI: Two IO regions pointed to by longwords at
538 * 0x40 (64 bytes of ACPI registers)
539 * 0x90 (16 bytes of SMB registers)
540 * and a few strange programmable PIIX4 device resources.
541 */
542 static void quirk_piix4_acpi(struct pci_dev *dev)
543 {
544 u32 res_a;
545
546 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
547 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
548
549 /* Device resource A has enables for some of the other ones */
550 pci_read_config_dword(dev, 0x5c, &res_a);
551
552 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
553 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
554
555 /* Device resource D is just bitfields for static resources */
556
557 /* Device 12 enabled? */
558 if (res_a & (1 << 29)) {
559 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
560 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
561 }
562 /* Device 13 enabled? */
563 if (res_a & (1 << 30)) {
564 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
565 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
566 }
567 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
568 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
569 }
570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
572
573 #define ICH_PMBASE 0x40
574 #define ICH_ACPI_CNTL 0x44
575 #define ICH4_ACPI_EN 0x10
576 #define ICH6_ACPI_EN 0x80
577 #define ICH4_GPIOBASE 0x58
578 #define ICH4_GPIO_CNTL 0x5c
579 #define ICH4_GPIO_EN 0x10
580 #define ICH6_GPIOBASE 0x48
581 #define ICH6_GPIO_CNTL 0x4c
582 #define ICH6_GPIO_EN 0x10
583
584 /*
585 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
586 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
587 * 0x58 (64 bytes of GPIO I/O space)
588 */
589 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
590 {
591 u8 enable;
592
593 /*
594 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
595 * with low legacy (and fixed) ports. We don't know the decoding
596 * priority and can't tell whether the legacy device or the one created
597 * here is really at that address. This happens on boards with broken
598 * BIOSes.
599 */
600
601 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
602 if (enable & ICH4_ACPI_EN)
603 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
604 "ICH4 ACPI/GPIO/TCO");
605
606 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
607 if (enable & ICH4_GPIO_EN)
608 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
609 "ICH4 GPIO");
610 }
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
621
622 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
623 {
624 u8 enable;
625
626 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
627 if (enable & ICH6_ACPI_EN)
628 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
629 "ICH6 ACPI/GPIO/TCO");
630
631 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
632 if (enable & ICH6_GPIO_EN)
633 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
634 "ICH6 GPIO");
635 }
636
637 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
638 {
639 u32 val;
640 u32 size, base;
641
642 pci_read_config_dword(dev, reg, &val);
643
644 /* Enabled? */
645 if (!(val & 1))
646 return;
647 base = val & 0xfffc;
648 if (dynsize) {
649 /*
650 * This is not correct. It is 16, 32 or 64 bytes depending on
651 * register D31:F0:ADh bits 5:4.
652 *
653 * But this gets us at least _part_ of it.
654 */
655 size = 16;
656 } else {
657 size = 128;
658 }
659 base &= ~(size-1);
660
661 /* Just print it out for now. We should reserve it after more debugging */
662 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
663 }
664
665 static void quirk_ich6_lpc(struct pci_dev *dev)
666 {
667 /* Shared ACPI/GPIO decode with all ICH6+ */
668 ich6_lpc_acpi_gpio(dev);
669
670 /* ICH6-specific generic IO decode */
671 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
672 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
673 }
674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
676
677 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
678 {
679 u32 val;
680 u32 mask, base;
681
682 pci_read_config_dword(dev, reg, &val);
683
684 /* Enabled? */
685 if (!(val & 1))
686 return;
687
688 /*
689 * IO base in bits 15:2, mask in bits 23:18, both
690 * are dword-based
691 */
692 base = val & 0xfffc;
693 mask = (val >> 16) & 0xfc;
694 mask |= 3;
695
696 /* Just print it out for now. We should reserve it after more debugging */
697 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
698 }
699
700 /* ICH7-10 has the same common LPC generic IO decode registers */
701 static void quirk_ich7_lpc(struct pci_dev *dev)
702 {
703 /* We share the common ACPI/GPIO decode with ICH6 */
704 ich6_lpc_acpi_gpio(dev);
705
706 /* And have 4 ICH7+ generic decodes */
707 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
708 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
709 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
710 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
711 }
712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
713 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
725
726 /*
727 * VIA ACPI: One IO region pointed to by longword at
728 * 0x48 or 0x20 (256 bytes of ACPI registers)
729 */
730 static void quirk_vt82c586_acpi(struct pci_dev *dev)
731 {
732 if (dev->revision & 0x10)
733 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
734 "vt82c586 ACPI");
735 }
736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
737
738 /*
739 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
740 * 0x48 (256 bytes of ACPI registers)
741 * 0x70 (128 bytes of hardware monitoring register)
742 * 0x90 (16 bytes of SMB registers)
743 */
744 static void quirk_vt82c686_acpi(struct pci_dev *dev)
745 {
746 quirk_vt82c586_acpi(dev);
747
748 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
749 "vt82c686 HW-mon");
750
751 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
752 }
753 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
754
755 /*
756 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
757 * 0x88 (128 bytes of power management registers)
758 * 0xd0 (16 bytes of SMB registers)
759 */
760 static void quirk_vt8235_acpi(struct pci_dev *dev)
761 {
762 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
763 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
764 }
765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
766
767 /*
768 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
769 * Disable fast back-to-back on the secondary bus segment
770 */
771 static void quirk_xio2000a(struct pci_dev *dev)
772 {
773 struct pci_dev *pdev;
774 u16 command;
775
776 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
777 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
778 pci_read_config_word(pdev, PCI_COMMAND, &command);
779 if (command & PCI_COMMAND_FAST_BACK)
780 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
781 }
782 }
783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
784 quirk_xio2000a);
785
786 #ifdef CONFIG_X86_IO_APIC
787
788 #include <asm/io_apic.h>
789
790 /*
791 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
792 * devices to the external APIC.
793 *
794 * TODO: When we have device-specific interrupt routers,
795 * this code will go away from quirks.
796 */
797 static void quirk_via_ioapic(struct pci_dev *dev)
798 {
799 u8 tmp;
800
801 if (nr_ioapics < 1)
802 tmp = 0; /* nothing routed to external APIC */
803 else
804 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
805
806 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
807 tmp == 0 ? "Disa" : "Ena");
808
809 /* Offset 0x58: External APIC IRQ output control */
810 pci_write_config_byte(dev, 0x58, tmp);
811 }
812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
813 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
814
815 /*
816 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
817 * This leads to doubled level interrupt rates.
818 * Set this bit to get rid of cycle wastage.
819 * Otherwise uncritical.
820 */
821 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
822 {
823 u8 misc_control2;
824 #define BYPASS_APIC_DEASSERT 8
825
826 pci_read_config_byte(dev, 0x5B, &misc_control2);
827 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
828 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
829 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
830 }
831 }
832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
833 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
834
835 /*
836 * The AMD io apic can hang the box when an apic irq is masked.
837 * We check all revs >= B0 (yet not in the pre production!) as the bug
838 * is currently marked NoFix
839 *
840 * We have multiple reports of hangs with this chipset that went away with
841 * noapic specified. For the moment we assume it's the erratum. We may be wrong
842 * of course. However the advice is demonstrably good even if so..
843 */
844 static void quirk_amd_ioapic(struct pci_dev *dev)
845 {
846 if (dev->revision >= 0x02) {
847 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
848 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
849 }
850 }
851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
852 #endif /* CONFIG_X86_IO_APIC */
853
854 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
855
856 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
857 {
858 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
859 if (dev->subsystem_device == 0xa118)
860 dev->sriov->link = dev->devfn;
861 }
862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
863 #endif
864
865 /*
866 * Some settings of MMRBC can lead to data corruption so block changes.
867 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
868 */
869 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
870 {
871 if (dev->subordinate && dev->revision <= 0x12) {
872 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
873 dev->revision);
874 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
875 }
876 }
877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
878
879 /*
880 * FIXME: it is questionable that quirk_via_acpi
881 * is needed. It shows up as an ISA bridge, and does not
882 * support the PCI_INTERRUPT_LINE register at all. Therefore
883 * it seems like setting the pci_dev's 'irq' to the
884 * value of the ACPI SCI interrupt is only done for convenience.
885 * -jgarzik
886 */
887 static void quirk_via_acpi(struct pci_dev *d)
888 {
889 /*
890 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
891 */
892 u8 irq;
893 pci_read_config_byte(d, 0x42, &irq);
894 irq &= 0xf;
895 if (irq && (irq != 2))
896 d->irq = irq;
897 }
898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
900
901
902 /*
903 * VIA bridges which have VLink
904 */
905
906 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
907
908 static void quirk_via_bridge(struct pci_dev *dev)
909 {
910 /* See what bridge we have and find the device ranges */
911 switch (dev->device) {
912 case PCI_DEVICE_ID_VIA_82C686:
913 /* The VT82C686 is special, it attaches to PCI and can have
914 any device number. All its subdevices are functions of
915 that single device. */
916 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
917 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
918 break;
919 case PCI_DEVICE_ID_VIA_8237:
920 case PCI_DEVICE_ID_VIA_8237A:
921 via_vlink_dev_lo = 15;
922 break;
923 case PCI_DEVICE_ID_VIA_8235:
924 via_vlink_dev_lo = 16;
925 break;
926 case PCI_DEVICE_ID_VIA_8231:
927 case PCI_DEVICE_ID_VIA_8233_0:
928 case PCI_DEVICE_ID_VIA_8233A:
929 case PCI_DEVICE_ID_VIA_8233C_0:
930 via_vlink_dev_lo = 17;
931 break;
932 }
933 }
934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
942
943 /**
944 * quirk_via_vlink - VIA VLink IRQ number update
945 * @dev: PCI device
946 *
947 * If the device we are dealing with is on a PIC IRQ we need to
948 * ensure that the IRQ line register which usually is not relevant
949 * for PCI cards, is actually written so that interrupts get sent
950 * to the right place.
951 * We only do this on systems where a VIA south bridge was detected,
952 * and only for VIA devices on the motherboard (see quirk_via_bridge
953 * above).
954 */
955
956 static void quirk_via_vlink(struct pci_dev *dev)
957 {
958 u8 irq, new_irq;
959
960 /* Check if we have VLink at all */
961 if (via_vlink_dev_lo == -1)
962 return;
963
964 new_irq = dev->irq;
965
966 /* Don't quirk interrupts outside the legacy IRQ range */
967 if (!new_irq || new_irq > 15)
968 return;
969
970 /* Internal device ? */
971 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
972 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
973 return;
974
975 /* This is an internal VLink device on a PIC interrupt. The BIOS
976 ought to have set this but may not have, so we redo it */
977
978 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
979 if (new_irq != irq) {
980 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
981 irq, new_irq);
982 udelay(15); /* unknown if delay really needed */
983 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
984 }
985 }
986 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
987
988 /*
989 * VIA VT82C598 has its device ID settable and many BIOSes
990 * set it to the ID of VT82C597 for backward compatibility.
991 * We need to switch it off to be able to recognize the real
992 * type of the chip.
993 */
994 static void quirk_vt82c598_id(struct pci_dev *dev)
995 {
996 pci_write_config_byte(dev, 0xfc, 0);
997 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
998 }
999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1000
1001 /*
1002 * CardBus controllers have a legacy base address that enables them
1003 * to respond as i82365 pcmcia controllers. We don't want them to
1004 * do this even if the Linux CardBus driver is not loaded, because
1005 * the Linux i82365 driver does not (and should not) handle CardBus.
1006 */
1007 static void quirk_cardbus_legacy(struct pci_dev *dev)
1008 {
1009 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1010 }
1011 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1012 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1013 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1014 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1015
1016 /*
1017 * Following the PCI ordering rules is optional on the AMD762. I'm not
1018 * sure what the designers were smoking but let's not inhale...
1019 *
1020 * To be fair to AMD, it follows the spec by default, its BIOS people
1021 * who turn it off!
1022 */
1023 static void quirk_amd_ordering(struct pci_dev *dev)
1024 {
1025 u32 pcic;
1026 pci_read_config_dword(dev, 0x4C, &pcic);
1027 if ((pcic & 6) != 6) {
1028 pcic |= 6;
1029 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1030 pci_write_config_dword(dev, 0x4C, pcic);
1031 pci_read_config_dword(dev, 0x84, &pcic);
1032 pcic |= (1 << 23); /* Required in this mode */
1033 pci_write_config_dword(dev, 0x84, pcic);
1034 }
1035 }
1036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1037 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1038
1039 /*
1040 * DreamWorks provided workaround for Dunord I-3000 problem
1041 *
1042 * This card decodes and responds to addresses not apparently
1043 * assigned to it. We force a larger allocation to ensure that
1044 * nothing gets put too close to it.
1045 */
1046 static void quirk_dunord(struct pci_dev *dev)
1047 {
1048 struct resource *r = &dev->resource[1];
1049
1050 r->flags |= IORESOURCE_UNSET;
1051 r->start = 0;
1052 r->end = 0xffffff;
1053 }
1054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1055
1056 /*
1057 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1058 * is subtractive decoding (transparent), and does indicate this
1059 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1060 * instead of 0x01.
1061 */
1062 static void quirk_transparent_bridge(struct pci_dev *dev)
1063 {
1064 dev->transparent = 1;
1065 }
1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1068
1069 /*
1070 * Common misconfiguration of the MediaGX/Geode PCI master that will
1071 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1072 * datasheets found at http://www.national.com/analog for info on what
1073 * these bits do. <christer@weinigel.se>
1074 */
1075 static void quirk_mediagx_master(struct pci_dev *dev)
1076 {
1077 u8 reg;
1078
1079 pci_read_config_byte(dev, 0x41, &reg);
1080 if (reg & 2) {
1081 reg &= ~2;
1082 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1083 reg);
1084 pci_write_config_byte(dev, 0x41, reg);
1085 }
1086 }
1087 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1088 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1089
1090 /*
1091 * Ensure C0 rev restreaming is off. This is normally done by
1092 * the BIOS but in the odd case it is not the results are corruption
1093 * hence the presence of a Linux check
1094 */
1095 static void quirk_disable_pxb(struct pci_dev *pdev)
1096 {
1097 u16 config;
1098
1099 if (pdev->revision != 0x04) /* Only C0 requires this */
1100 return;
1101 pci_read_config_word(pdev, 0x40, &config);
1102 if (config & (1<<6)) {
1103 config &= ~(1<<6);
1104 pci_write_config_word(pdev, 0x40, config);
1105 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1106 }
1107 }
1108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1109 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1110
1111 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1112 {
1113 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1114 u8 tmp;
1115
1116 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1117 if (tmp == 0x01) {
1118 pci_read_config_byte(pdev, 0x40, &tmp);
1119 pci_write_config_byte(pdev, 0x40, tmp|1);
1120 pci_write_config_byte(pdev, 0x9, 1);
1121 pci_write_config_byte(pdev, 0xa, 6);
1122 pci_write_config_byte(pdev, 0x40, tmp);
1123
1124 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1125 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1126 }
1127 }
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1129 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1131 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1133 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1135 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1136
1137 /*
1138 * Serverworks CSB5 IDE does not fully support native mode
1139 */
1140 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1141 {
1142 u8 prog;
1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1144 if (prog & 5) {
1145 prog &= ~5;
1146 pdev->class &= ~5;
1147 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1148 /* PCI layer will sort out resources */
1149 }
1150 }
1151 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1152
1153 /*
1154 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1155 */
1156 static void quirk_ide_samemode(struct pci_dev *pdev)
1157 {
1158 u8 prog;
1159
1160 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1161
1162 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1163 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1164 prog &= ~5;
1165 pdev->class &= ~5;
1166 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1167 }
1168 }
1169 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1170
1171 /*
1172 * Some ATA devices break if put into D3
1173 */
1174
1175 static void quirk_no_ata_d3(struct pci_dev *pdev)
1176 {
1177 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1178 }
1179 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1180 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1181 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1182 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1183 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1184 /* ALi loses some register settings that we cannot then restore */
1185 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1186 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1187 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1188 occur when mode detecting */
1189 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1190 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1191 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SK_HYNIX, 0x1527, quirk_no_ata_d3);
1192 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xf1a6, quirk_no_ata_d3);
1193 DECLARE_PCI_FIXUP_EARLY(0x15b7, 0x5002, quirk_no_ata_d3);
1194
1195 /* This was originally an Alpha specific thing, but it really fits here.
1196 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1197 */
1198 static void quirk_eisa_bridge(struct pci_dev *dev)
1199 {
1200 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1201 }
1202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1203
1204
1205 /*
1206 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1207 * is not activated. The myth is that Asus said that they do not want the
1208 * users to be irritated by just another PCI Device in the Win98 device
1209 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1210 * package 2.7.0 for details)
1211 *
1212 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1213 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1214 * becomes necessary to do this tweak in two steps -- the chosen trigger
1215 * is either the Host bridge (preferred) or on-board VGA controller.
1216 *
1217 * Note that we used to unhide the SMBus that way on Toshiba laptops
1218 * (Satellite A40 and Tecra M2) but then found that the thermal management
1219 * was done by SMM code, which could cause unsynchronized concurrent
1220 * accesses to the SMBus registers, with potentially bad effects. Thus you
1221 * should be very careful when adding new entries: if SMM is accessing the
1222 * Intel SMBus, this is a very good reason to leave it hidden.
1223 *
1224 * Likewise, many recent laptops use ACPI for thermal management. If the
1225 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1226 * natively, and keeping the SMBus hidden is the right thing to do. If you
1227 * are about to add an entry in the table below, please first disassemble
1228 * the DSDT and double-check that there is no code accessing the SMBus.
1229 */
1230 static int asus_hides_smbus;
1231
1232 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1233 {
1234 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1235 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1236 switch (dev->subsystem_device) {
1237 case 0x8025: /* P4B-LX */
1238 case 0x8070: /* P4B */
1239 case 0x8088: /* P4B533 */
1240 case 0x1626: /* L3C notebook */
1241 asus_hides_smbus = 1;
1242 }
1243 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1244 switch (dev->subsystem_device) {
1245 case 0x80b1: /* P4GE-V */
1246 case 0x80b2: /* P4PE */
1247 case 0x8093: /* P4B533-V */
1248 asus_hides_smbus = 1;
1249 }
1250 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1251 switch (dev->subsystem_device) {
1252 case 0x8030: /* P4T533 */
1253 asus_hides_smbus = 1;
1254 }
1255 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1256 switch (dev->subsystem_device) {
1257 case 0x8070: /* P4G8X Deluxe */
1258 asus_hides_smbus = 1;
1259 }
1260 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1261 switch (dev->subsystem_device) {
1262 case 0x80c9: /* PU-DLS */
1263 asus_hides_smbus = 1;
1264 }
1265 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1266 switch (dev->subsystem_device) {
1267 case 0x1751: /* M2N notebook */
1268 case 0x1821: /* M5N notebook */
1269 case 0x1897: /* A6L notebook */
1270 asus_hides_smbus = 1;
1271 }
1272 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1273 switch (dev->subsystem_device) {
1274 case 0x184b: /* W1N notebook */
1275 case 0x186a: /* M6Ne notebook */
1276 asus_hides_smbus = 1;
1277 }
1278 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1279 switch (dev->subsystem_device) {
1280 case 0x80f2: /* P4P800-X */
1281 asus_hides_smbus = 1;
1282 }
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x1882: /* M6V notebook */
1286 case 0x1977: /* A6VA notebook */
1287 asus_hides_smbus = 1;
1288 }
1289 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1290 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1291 switch (dev->subsystem_device) {
1292 case 0x088C: /* HP Compaq nc8000 */
1293 case 0x0890: /* HP Compaq nc6000 */
1294 asus_hides_smbus = 1;
1295 }
1296 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1297 switch (dev->subsystem_device) {
1298 case 0x12bc: /* HP D330L */
1299 case 0x12bd: /* HP D530 */
1300 case 0x006a: /* HP Compaq nx9500 */
1301 asus_hides_smbus = 1;
1302 }
1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1304 switch (dev->subsystem_device) {
1305 case 0x12bf: /* HP xw4100 */
1306 asus_hides_smbus = 1;
1307 }
1308 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1309 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1310 switch (dev->subsystem_device) {
1311 case 0xC00C: /* Samsung P35 notebook */
1312 asus_hides_smbus = 1;
1313 }
1314 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1315 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1316 switch (dev->subsystem_device) {
1317 case 0x0058: /* Compaq Evo N620c */
1318 asus_hides_smbus = 1;
1319 }
1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1321 switch (dev->subsystem_device) {
1322 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1323 /* Motherboard doesn't have Host bridge
1324 * subvendor/subdevice IDs, therefore checking
1325 * its on-board VGA controller */
1326 asus_hides_smbus = 1;
1327 }
1328 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1329 switch (dev->subsystem_device) {
1330 case 0x00b8: /* Compaq Evo D510 CMT */
1331 case 0x00b9: /* Compaq Evo D510 SFF */
1332 case 0x00ba: /* Compaq Evo D510 USDT */
1333 /* Motherboard doesn't have Host bridge
1334 * subvendor/subdevice IDs and on-board VGA
1335 * controller is disabled if an AGP card is
1336 * inserted, therefore checking USB UHCI
1337 * Controller #1 */
1338 asus_hides_smbus = 1;
1339 }
1340 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1341 switch (dev->subsystem_device) {
1342 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1343 /* Motherboard doesn't have host bridge
1344 * subvendor/subdevice IDs, therefore checking
1345 * its on-board VGA controller */
1346 asus_hides_smbus = 1;
1347 }
1348 }
1349 }
1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1360
1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1364
1365 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1366 {
1367 u16 val;
1368
1369 if (likely(!asus_hides_smbus))
1370 return;
1371
1372 pci_read_config_word(dev, 0xF2, &val);
1373 if (val & 0x8) {
1374 pci_write_config_word(dev, 0xF2, val & (~0x8));
1375 pci_read_config_word(dev, 0xF2, &val);
1376 if (val & 0x8)
1377 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1378 val);
1379 else
1380 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1381 }
1382 }
1383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1390 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1392 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1393 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1394 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1396 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1397
1398 /* It appears we just have one such device. If not, we have a warning */
1399 static void __iomem *asus_rcba_base;
1400 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1401 {
1402 u32 rcba;
1403
1404 if (likely(!asus_hides_smbus))
1405 return;
1406 WARN_ON(asus_rcba_base);
1407
1408 pci_read_config_dword(dev, 0xF0, &rcba);
1409 /* use bits 31:14, 16 kB aligned */
1410 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1411 if (asus_rcba_base == NULL)
1412 return;
1413 }
1414
1415 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1416 {
1417 u32 val;
1418
1419 if (likely(!asus_hides_smbus || !asus_rcba_base))
1420 return;
1421 /* read the Function Disable register, dword mode only */
1422 val = readl(asus_rcba_base + 0x3418);
1423 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1424 }
1425
1426 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1427 {
1428 if (likely(!asus_hides_smbus || !asus_rcba_base))
1429 return;
1430 iounmap(asus_rcba_base);
1431 asus_rcba_base = NULL;
1432 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1433 }
1434
1435 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1436 {
1437 asus_hides_smbus_lpc_ich6_suspend(dev);
1438 asus_hides_smbus_lpc_ich6_resume_early(dev);
1439 asus_hides_smbus_lpc_ich6_resume(dev);
1440 }
1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1442 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1443 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1445
1446 /*
1447 * SiS 96x south bridge: BIOS typically hides SMBus device...
1448 */
1449 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1450 {
1451 u8 val = 0;
1452 pci_read_config_byte(dev, 0x77, &val);
1453 if (val & 0x10) {
1454 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1455 pci_write_config_byte(dev, 0x77, val & ~0x10);
1456 }
1457 }
1458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1462 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1463 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1464 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1465 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1466
1467 /*
1468 * ... This is further complicated by the fact that some SiS96x south
1469 * bridges pretend to be 85C503/5513 instead. In that case see if we
1470 * spotted a compatible north bridge to make sure.
1471 * (pci_find_device doesn't work yet)
1472 *
1473 * We can also enable the sis96x bit in the discovery register..
1474 */
1475 #define SIS_DETECT_REGISTER 0x40
1476
1477 static void quirk_sis_503(struct pci_dev *dev)
1478 {
1479 u8 reg;
1480 u16 devid;
1481
1482 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1483 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1484 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1485 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1486 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1487 return;
1488 }
1489
1490 /*
1491 * Ok, it now shows up as a 96x.. run the 96x quirk by
1492 * hand in case it has already been processed.
1493 * (depends on link order, which is apparently not guaranteed)
1494 */
1495 dev->device = devid;
1496 quirk_sis_96x_smbus(dev);
1497 }
1498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1499 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1500
1501
1502 /*
1503 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1504 * and MC97 modem controller are disabled when a second PCI soundcard is
1505 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1506 * -- bjd
1507 */
1508 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1509 {
1510 u8 val;
1511 int asus_hides_ac97 = 0;
1512
1513 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1514 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1515 asus_hides_ac97 = 1;
1516 }
1517
1518 if (!asus_hides_ac97)
1519 return;
1520
1521 pci_read_config_byte(dev, 0x50, &val);
1522 if (val & 0xc0) {
1523 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1524 pci_read_config_byte(dev, 0x50, &val);
1525 if (val & 0xc0)
1526 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1527 val);
1528 else
1529 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1530 }
1531 }
1532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1534
1535 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1536
1537 /*
1538 * If we are using libata we can drive this chip properly but must
1539 * do this early on to make the additional device appear during
1540 * the PCI scanning.
1541 */
1542 static void quirk_jmicron_ata(struct pci_dev *pdev)
1543 {
1544 u32 conf1, conf5, class;
1545 u8 hdr;
1546
1547 /* Only poke fn 0 */
1548 if (PCI_FUNC(pdev->devfn))
1549 return;
1550
1551 pci_read_config_dword(pdev, 0x40, &conf1);
1552 pci_read_config_dword(pdev, 0x80, &conf5);
1553
1554 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1555 conf5 &= ~(1 << 24); /* Clear bit 24 */
1556
1557 switch (pdev->device) {
1558 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1559 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1560 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1561 /* The controller should be in single function ahci mode */
1562 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1563 break;
1564
1565 case PCI_DEVICE_ID_JMICRON_JMB365:
1566 case PCI_DEVICE_ID_JMICRON_JMB366:
1567 /* Redirect IDE second PATA port to the right spot */
1568 conf5 |= (1 << 24);
1569 /* Fall through */
1570 case PCI_DEVICE_ID_JMICRON_JMB361:
1571 case PCI_DEVICE_ID_JMICRON_JMB363:
1572 case PCI_DEVICE_ID_JMICRON_JMB369:
1573 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1574 /* Set the class codes correctly and then direct IDE 0 */
1575 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1576 break;
1577
1578 case PCI_DEVICE_ID_JMICRON_JMB368:
1579 /* The controller should be in single function IDE mode */
1580 conf1 |= 0x00C00000; /* Set 22, 23 */
1581 break;
1582 }
1583
1584 pci_write_config_dword(pdev, 0x40, conf1);
1585 pci_write_config_dword(pdev, 0x80, conf5);
1586
1587 /* Update pdev accordingly */
1588 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1589 pdev->hdr_type = hdr & 0x7f;
1590 pdev->multifunction = !!(hdr & 0x80);
1591
1592 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1593 pdev->class = class >> 8;
1594 }
1595 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1596 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1597 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1598 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1599 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1600 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1601 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1602 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1603 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1604 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1605 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1606 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1609 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1610 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1611 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1612 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1613
1614 #endif
1615
1616 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1617 {
1618 if (dev->multifunction) {
1619 device_disable_async_suspend(&dev->dev);
1620 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1621 }
1622 }
1623 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1624 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1627
1628 #ifdef CONFIG_X86_IO_APIC
1629 static void quirk_alder_ioapic(struct pci_dev *pdev)
1630 {
1631 int i;
1632
1633 if ((pdev->class >> 8) != 0xff00)
1634 return;
1635
1636 /* the first BAR is the location of the IO APIC...we must
1637 * not touch this (and it's already covered by the fixmap), so
1638 * forcibly insert it into the resource tree */
1639 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1640 insert_resource(&iomem_resource, &pdev->resource[0]);
1641
1642 /* The next five BARs all seem to be rubbish, so just clean
1643 * them out */
1644 for (i = 1; i < 6; i++)
1645 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1646 }
1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1648 #endif
1649
1650 static void quirk_pcie_mch(struct pci_dev *pdev)
1651 {
1652 pdev->no_msi = 1;
1653 }
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1657
1658 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1659
1660 /*
1661 * It's possible for the MSI to get corrupted if shpc and acpi
1662 * are used together on certain PXH-based systems.
1663 */
1664 static void quirk_pcie_pxh(struct pci_dev *dev)
1665 {
1666 dev->no_msi = 1;
1667 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1668 }
1669 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1670 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1671 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1672 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1673 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1674
1675 /*
1676 * Some Intel PCI Express chipsets have trouble with downstream
1677 * device power management.
1678 */
1679 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1680 {
1681 pci_pm_d3_delay = 120;
1682 dev->no_d1d2 = 1;
1683 }
1684
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1706
1707 static void quirk_radeon_pm(struct pci_dev *dev)
1708 {
1709 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1710 dev->subsystem_device == 0x00e2) {
1711 if (dev->d3_delay < 20) {
1712 dev->d3_delay = 20;
1713 dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n",
1714 dev->d3_delay);
1715 }
1716 }
1717 }
1718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1719
1720 #ifdef CONFIG_X86_IO_APIC
1721 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1722 {
1723 noioapicreroute = 1;
1724 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1725
1726 return 0;
1727 }
1728
1729 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1730 /*
1731 * Systems to exclude from boot interrupt reroute quirks
1732 */
1733 {
1734 .callback = dmi_disable_ioapicreroute,
1735 .ident = "ASUSTek Computer INC. M2N-LR",
1736 .matches = {
1737 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1738 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1739 },
1740 },
1741 {}
1742 };
1743
1744 /*
1745 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1746 * remap the original interrupt in the linux kernel to the boot interrupt, so
1747 * that a PCI device's interrupt handler is installed on the boot interrupt
1748 * line instead.
1749 */
1750 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1751 {
1752 dmi_check_system(boot_interrupt_dmi_table);
1753 if (noioapicquirk || noioapicreroute)
1754 return;
1755
1756 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1757 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1758 dev->vendor, dev->device);
1759 }
1760 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1762 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1764 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1767 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1768 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1769 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1770 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1771 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1772 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1773 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1774 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1775 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1776
1777 /*
1778 * On some chipsets we can disable the generation of legacy INTx boot
1779 * interrupts.
1780 */
1781
1782 /*
1783 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1784 * 300641-004US, section 5.7.3.
1785 */
1786 #define INTEL_6300_IOAPIC_ABAR 0x40
1787 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1788
1789 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1790 {
1791 u16 pci_config_word;
1792
1793 if (noioapicquirk)
1794 return;
1795
1796 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1797 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1798 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1799
1800 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1801 dev->vendor, dev->device);
1802 }
1803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1804 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1805
1806 /*
1807 * disable boot interrupts on HT-1000
1808 */
1809 #define BC_HT1000_FEATURE_REG 0x64
1810 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1811 #define BC_HT1000_MAP_IDX 0xC00
1812 #define BC_HT1000_MAP_DATA 0xC01
1813
1814 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1815 {
1816 u32 pci_config_dword;
1817 u8 irq;
1818
1819 if (noioapicquirk)
1820 return;
1821
1822 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1823 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1824 BC_HT1000_PIC_REGS_ENABLE);
1825
1826 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1827 outb(irq, BC_HT1000_MAP_IDX);
1828 outb(0x00, BC_HT1000_MAP_DATA);
1829 }
1830
1831 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1832
1833 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1834 dev->vendor, dev->device);
1835 }
1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1837 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1838
1839 /*
1840 * disable boot interrupts on AMD and ATI chipsets
1841 */
1842 /*
1843 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1844 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1845 * (due to an erratum).
1846 */
1847 #define AMD_813X_MISC 0x40
1848 #define AMD_813X_NOIOAMODE (1<<0)
1849 #define AMD_813X_REV_B1 0x12
1850 #define AMD_813X_REV_B2 0x13
1851
1852 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1853 {
1854 u32 pci_config_dword;
1855
1856 if (noioapicquirk)
1857 return;
1858 if ((dev->revision == AMD_813X_REV_B1) ||
1859 (dev->revision == AMD_813X_REV_B2))
1860 return;
1861
1862 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1863 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1864 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1865
1866 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1867 dev->vendor, dev->device);
1868 }
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1870 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1872 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1873
1874 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1875
1876 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1877 {
1878 u16 pci_config_word;
1879
1880 if (noioapicquirk)
1881 return;
1882
1883 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1884 if (!pci_config_word) {
1885 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1886 dev->vendor, dev->device);
1887 return;
1888 }
1889 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1890 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1891 dev->vendor, dev->device);
1892 }
1893 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1894 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1895 #endif /* CONFIG_X86_IO_APIC */
1896
1897 /*
1898 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1899 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1900 * Re-allocate the region if needed...
1901 */
1902 static void quirk_tc86c001_ide(struct pci_dev *dev)
1903 {
1904 struct resource *r = &dev->resource[0];
1905
1906 if (r->start & 0x8) {
1907 r->flags |= IORESOURCE_UNSET;
1908 r->start = 0;
1909 r->end = 0xf;
1910 }
1911 }
1912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1913 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1914 quirk_tc86c001_ide);
1915
1916 /*
1917 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1918 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1919 * being read correctly if bit 7 of the base address is set.
1920 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1921 * Re-allocate the regions to a 256-byte boundary if necessary.
1922 */
1923 static void quirk_plx_pci9050(struct pci_dev *dev)
1924 {
1925 unsigned int bar;
1926
1927 /* Fixed in revision 2 (PCI 9052). */
1928 if (dev->revision >= 2)
1929 return;
1930 for (bar = 0; bar <= 1; bar++)
1931 if (pci_resource_len(dev, bar) == 0x80 &&
1932 (pci_resource_start(dev, bar) & 0x80)) {
1933 struct resource *r = &dev->resource[bar];
1934 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1935 bar);
1936 r->flags |= IORESOURCE_UNSET;
1937 r->start = 0;
1938 r->end = 0xff;
1939 }
1940 }
1941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1942 quirk_plx_pci9050);
1943 /*
1944 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1945 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1946 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1947 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1948 *
1949 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1950 * driver.
1951 */
1952 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1953 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1954
1955 static void quirk_netmos(struct pci_dev *dev)
1956 {
1957 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1958 unsigned int num_serial = dev->subsystem_device & 0xf;
1959
1960 /*
1961 * These Netmos parts are multiport serial devices with optional
1962 * parallel ports. Even when parallel ports are present, they
1963 * are identified as class SERIAL, which means the serial driver
1964 * will claim them. To prevent this, mark them as class OTHER.
1965 * These combo devices should be claimed by parport_serial.
1966 *
1967 * The subdevice ID is of the form 0x00PS, where <P> is the number
1968 * of parallel ports and <S> is the number of serial ports.
1969 */
1970 switch (dev->device) {
1971 case PCI_DEVICE_ID_NETMOS_9835:
1972 /* Well, this rule doesn't hold for the following 9835 device */
1973 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1974 dev->subsystem_device == 0x0299)
1975 return;
1976 case PCI_DEVICE_ID_NETMOS_9735:
1977 case PCI_DEVICE_ID_NETMOS_9745:
1978 case PCI_DEVICE_ID_NETMOS_9845:
1979 case PCI_DEVICE_ID_NETMOS_9855:
1980 if (num_parallel) {
1981 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1982 dev->device, num_parallel, num_serial);
1983 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1984 (dev->class & 0xff);
1985 }
1986 }
1987 }
1988 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1989 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1990
1991 /*
1992 * Quirk non-zero PCI functions to route VPD access through function 0 for
1993 * devices that share VPD resources between functions. The functions are
1994 * expected to be identical devices.
1995 */
1996 static void quirk_f0_vpd_link(struct pci_dev *dev)
1997 {
1998 struct pci_dev *f0;
1999
2000 if (!PCI_FUNC(dev->devfn))
2001 return;
2002
2003 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
2004 if (!f0)
2005 return;
2006
2007 if (f0->vpd && dev->class == f0->class &&
2008 dev->vendor == f0->vendor && dev->device == f0->device)
2009 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
2010
2011 pci_dev_put(f0);
2012 }
2013 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2014 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
2015
2016 static void quirk_e100_interrupt(struct pci_dev *dev)
2017 {
2018 u16 command, pmcsr;
2019 u8 __iomem *csr;
2020 u8 cmd_hi;
2021
2022 switch (dev->device) {
2023 /* PCI IDs taken from drivers/net/e100.c */
2024 case 0x1029:
2025 case 0x1030 ... 0x1034:
2026 case 0x1038 ... 0x103E:
2027 case 0x1050 ... 0x1057:
2028 case 0x1059:
2029 case 0x1064 ... 0x106B:
2030 case 0x1091 ... 0x1095:
2031 case 0x1209:
2032 case 0x1229:
2033 case 0x2449:
2034 case 0x2459:
2035 case 0x245D:
2036 case 0x27DC:
2037 break;
2038 default:
2039 return;
2040 }
2041
2042 /*
2043 * Some firmware hands off the e100 with interrupts enabled,
2044 * which can cause a flood of interrupts if packets are
2045 * received before the driver attaches to the device. So
2046 * disable all e100 interrupts here. The driver will
2047 * re-enable them when it's ready.
2048 */
2049 pci_read_config_word(dev, PCI_COMMAND, &command);
2050
2051 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2052 return;
2053
2054 /*
2055 * Check that the device is in the D0 power state. If it's not,
2056 * there is no point to look any further.
2057 */
2058 if (dev->pm_cap) {
2059 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2060 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2061 return;
2062 }
2063
2064 /* Convert from PCI bus to resource space. */
2065 csr = ioremap(pci_resource_start(dev, 0), 8);
2066 if (!csr) {
2067 dev_warn(&dev->dev, "Can't map e100 registers\n");
2068 return;
2069 }
2070
2071 cmd_hi = readb(csr + 3);
2072 if (cmd_hi == 0) {
2073 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2074 writeb(1, csr + 3);
2075 }
2076
2077 iounmap(csr);
2078 }
2079 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2080 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2081
2082 /*
2083 * The 82575 and 82598 may experience data corruption issues when transitioning
2084 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2085 */
2086 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2087 {
2088 dev_info(&dev->dev, "Disabling L0s\n");
2089 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2090 }
2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2105
2106 static void fixup_rev1_53c810(struct pci_dev *dev)
2107 {
2108 u32 class = dev->class;
2109
2110 /*
2111 * rev 1 ncr53c810 chips don't set the class at all which means
2112 * they don't get their resources remapped. Fix that here.
2113 */
2114 if (class)
2115 return;
2116
2117 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2118 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2119 class, dev->class);
2120 }
2121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2122
2123 /* Enable 1k I/O space granularity on the Intel P64H2 */
2124 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2125 {
2126 u16 en1k;
2127
2128 pci_read_config_word(dev, 0x40, &en1k);
2129
2130 if (en1k & 0x200) {
2131 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2132 dev->io_window_1k = 1;
2133 }
2134 }
2135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2136
2137 /* Under some circumstances, AER is not linked with extended capabilities.
2138 * Force it to be linked by setting the corresponding control bit in the
2139 * config space.
2140 */
2141 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2142 {
2143 uint8_t b;
2144 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2145 if (!(b & 0x20)) {
2146 pci_write_config_byte(dev, 0xf41, b | 0x20);
2147 dev_info(&dev->dev, "Linking AER extended capability\n");
2148 }
2149 }
2150 }
2151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2152 quirk_nvidia_ck804_pcie_aer_ext_cap);
2153 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2154 quirk_nvidia_ck804_pcie_aer_ext_cap);
2155
2156 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2157 {
2158 /*
2159 * Disable PCI Bus Parking and PCI Master read caching on CX700
2160 * which causes unspecified timing errors with a VT6212L on the PCI
2161 * bus leading to USB2.0 packet loss.
2162 *
2163 * This quirk is only enabled if a second (on the external PCI bus)
2164 * VT6212L is found -- the CX700 core itself also contains a USB
2165 * host controller with the same PCI ID as the VT6212L.
2166 */
2167
2168 /* Count VT6212L instances */
2169 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2170 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2171 uint8_t b;
2172
2173 /* p should contain the first (internal) VT6212L -- see if we have
2174 an external one by searching again */
2175 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2176 if (!p)
2177 return;
2178 pci_dev_put(p);
2179
2180 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2181 if (b & 0x40) {
2182 /* Turn off PCI Bus Parking */
2183 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2184
2185 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2186 }
2187 }
2188
2189 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2190 if (b != 0) {
2191 /* Turn off PCI Master read caching */
2192 pci_write_config_byte(dev, 0x72, 0x0);
2193
2194 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2195 pci_write_config_byte(dev, 0x75, 0x1);
2196
2197 /* Disable "Read FIFO Timer" */
2198 pci_write_config_byte(dev, 0x77, 0x0);
2199
2200 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2201 }
2202 }
2203 }
2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2205
2206 /*
2207 * If a device follows the VPD format spec, the PCI core will not read or
2208 * write past the VPD End Tag. But some vendors do not follow the VPD
2209 * format spec, so we can't tell how much data is safe to access. Devices
2210 * may behave unpredictably if we access too much. Blacklist these devices
2211 * so we don't touch VPD at all.
2212 */
2213 static void quirk_blacklist_vpd(struct pci_dev *dev)
2214 {
2215 if (dev->vpd) {
2216 dev->vpd->len = 0;
2217 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2218 }
2219 }
2220
2221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2233 quirk_blacklist_vpd);
2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2235
2236 /*
2237 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2238 * VPD end tag will hang the device. This problem was initially
2239 * observed when a vpd entry was created in sysfs
2240 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2241 * will dump 32k of data. Reading a full 32k will cause an access
2242 * beyond the VPD end tag causing the device to hang. Once the device
2243 * is hung, the bnx2 driver will not be able to reset the device.
2244 * We believe that it is legal to read beyond the end tag and
2245 * therefore the solution is to limit the read/write length.
2246 */
2247 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2248 {
2249 /*
2250 * Only disable the VPD capability for 5706, 5706S, 5708,
2251 * 5708S and 5709 rev. A
2252 */
2253 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2254 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2255 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2256 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2257 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2258 (dev->revision & 0xf0) == 0x0)) {
2259 if (dev->vpd)
2260 dev->vpd->len = 0x80;
2261 }
2262 }
2263
2264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2265 PCI_DEVICE_ID_NX2_5706,
2266 quirk_brcm_570x_limit_vpd);
2267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2268 PCI_DEVICE_ID_NX2_5706S,
2269 quirk_brcm_570x_limit_vpd);
2270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2271 PCI_DEVICE_ID_NX2_5708,
2272 quirk_brcm_570x_limit_vpd);
2273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2274 PCI_DEVICE_ID_NX2_5708S,
2275 quirk_brcm_570x_limit_vpd);
2276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2277 PCI_DEVICE_ID_NX2_5709,
2278 quirk_brcm_570x_limit_vpd);
2279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2280 PCI_DEVICE_ID_NX2_5709S,
2281 quirk_brcm_570x_limit_vpd);
2282
2283 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2284 {
2285 u32 rev;
2286
2287 pci_read_config_dword(dev, 0xf4, &rev);
2288
2289 /* Only CAP the MRRS if the device is a 5719 A0 */
2290 if (rev == 0x05719000) {
2291 int readrq = pcie_get_readrq(dev);
2292 if (readrq > 2048)
2293 pcie_set_readrq(dev, 2048);
2294 }
2295 }
2296
2297 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2298 PCI_DEVICE_ID_TIGON3_5719,
2299 quirk_brcm_5719_limit_mrrs);
2300
2301 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2302 static void quirk_paxc_bridge(struct pci_dev *pdev)
2303 {
2304 /* The PCI config space is shared with the PAXC root port and the first
2305 * Ethernet device. So, we need to workaround this by telling the PCI
2306 * code that the bridge is not an Ethernet device.
2307 */
2308 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2309 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2310
2311 /* MPSS is not being set properly (as it is currently 0). This is
2312 * because that area of the PCI config space is hard coded to zero, and
2313 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2314 * so that the MPS can be set to the real max value.
2315 */
2316 pdev->pcie_mpss = 2;
2317 }
2318 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2320 #endif
2321
2322 /* Originally in EDAC sources for i82875P:
2323 * Intel tells BIOS developers to hide device 6 which
2324 * configures the overflow device access containing
2325 * the DRBs - this is where we expose device 6.
2326 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2327 */
2328 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2329 {
2330 u8 reg;
2331
2332 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2333 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2334 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2335 }
2336 }
2337
2338 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2339 quirk_unhide_mch_dev6);
2340 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2341 quirk_unhide_mch_dev6);
2342
2343 #ifdef CONFIG_TILEPRO
2344 /*
2345 * The Tilera TILEmpower tilepro platform needs to set the link speed
2346 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2347 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2348 * capability register of the PEX8624 PCIe switch. The switch
2349 * supports link speed auto negotiation, but falsely sets
2350 * the link speed to 5GT/s.
2351 */
2352 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2353 {
2354 if (tile_plx_gen1) {
2355 pci_write_config_dword(dev, 0x98, 0x1);
2356 mdelay(50);
2357 }
2358 }
2359 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2360 #endif /* CONFIG_TILEPRO */
2361
2362 #ifdef CONFIG_PCI_MSI
2363 /* Some chipsets do not support MSI. We cannot easily rely on setting
2364 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2365 * some other buses controlled by the chipset even if Linux is not
2366 * aware of it. Instead of setting the flag on all buses in the
2367 * machine, simply disable MSI globally.
2368 */
2369 static void quirk_disable_all_msi(struct pci_dev *dev)
2370 {
2371 pci_no_msi();
2372 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2373 }
2374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2382
2383 /* Disable MSI on chipsets that are known to not support it */
2384 static void quirk_disable_msi(struct pci_dev *dev)
2385 {
2386 if (dev->subordinate) {
2387 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2388 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2389 }
2390 }
2391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2394
2395 /*
2396 * The APC bridge device in AMD 780 family northbridges has some random
2397 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2398 * we use the possible vendor/device IDs of the host bridge for the
2399 * declared quirk, and search for the APC bridge by slot number.
2400 */
2401 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2402 {
2403 struct pci_dev *apc_bridge;
2404
2405 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2406 if (apc_bridge) {
2407 if (apc_bridge->device == 0x9602)
2408 quirk_disable_msi(apc_bridge);
2409 pci_dev_put(apc_bridge);
2410 }
2411 }
2412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2414
2415 /* Go through the list of Hypertransport capabilities and
2416 * return 1 if a HT MSI capability is found and enabled */
2417 static int msi_ht_cap_enabled(struct pci_dev *dev)
2418 {
2419 int pos, ttl = PCI_FIND_CAP_TTL;
2420
2421 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2422 while (pos && ttl--) {
2423 u8 flags;
2424
2425 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2426 &flags) == 0) {
2427 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2428 flags & HT_MSI_FLAGS_ENABLE ?
2429 "enabled" : "disabled");
2430 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2431 }
2432
2433 pos = pci_find_next_ht_capability(dev, pos,
2434 HT_CAPTYPE_MSI_MAPPING);
2435 }
2436 return 0;
2437 }
2438
2439 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2440 static void quirk_msi_ht_cap(struct pci_dev *dev)
2441 {
2442 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2443 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2444 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2445 }
2446 }
2447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2448 quirk_msi_ht_cap);
2449
2450 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2451 * MSI are supported if the MSI capability set in any of these mappings.
2452 */
2453 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2454 {
2455 struct pci_dev *pdev;
2456
2457 if (!dev->subordinate)
2458 return;
2459
2460 /* check HT MSI cap on this chipset and the root one.
2461 * a single one having MSI is enough to be sure that MSI are supported.
2462 */
2463 pdev = pci_get_slot(dev->bus, 0);
2464 if (!pdev)
2465 return;
2466 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2467 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2468 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2469 }
2470 pci_dev_put(pdev);
2471 }
2472 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2473 quirk_nvidia_ck804_msi_ht_cap);
2474
2475 /* Force enable MSI mapping capability on HT bridges */
2476 static void ht_enable_msi_mapping(struct pci_dev *dev)
2477 {
2478 int pos, ttl = PCI_FIND_CAP_TTL;
2479
2480 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2481 while (pos && ttl--) {
2482 u8 flags;
2483
2484 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2485 &flags) == 0) {
2486 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2487
2488 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2489 flags | HT_MSI_FLAGS_ENABLE);
2490 }
2491 pos = pci_find_next_ht_capability(dev, pos,
2492 HT_CAPTYPE_MSI_MAPPING);
2493 }
2494 }
2495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2496 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2497 ht_enable_msi_mapping);
2498
2499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2500 ht_enable_msi_mapping);
2501
2502 /* The P5N32-SLI motherboards from Asus have a problem with msi
2503 * for the MCP55 NIC. It is not yet determined whether the msi problem
2504 * also affects other devices. As for now, turn off msi for this device.
2505 */
2506 static void nvenet_msi_disable(struct pci_dev *dev)
2507 {
2508 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2509
2510 if (board_name &&
2511 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2512 strstr(board_name, "P5N32-E SLI"))) {
2513 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2514 dev->no_msi = 1;
2515 }
2516 }
2517 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2518 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2519 nvenet_msi_disable);
2520
2521 /*
2522 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2523 * config register. This register controls the routing of legacy
2524 * interrupts from devices that route through the MCP55. If this register
2525 * is misprogrammed, interrupts are only sent to the BSP, unlike
2526 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2527 * having this register set properly prevents kdump from booting up
2528 * properly, so let's make sure that we have it set correctly.
2529 * Note that this is an undocumented register.
2530 */
2531 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2532 {
2533 u32 cfg;
2534
2535 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2536 return;
2537
2538 pci_read_config_dword(dev, 0x74, &cfg);
2539
2540 if (cfg & ((1 << 2) | (1 << 15))) {
2541 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2542 cfg &= ~((1 << 2) | (1 << 15));
2543 pci_write_config_dword(dev, 0x74, cfg);
2544 }
2545 }
2546
2547 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2548 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2549 nvbridge_check_legacy_irq_routing);
2550
2551 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2552 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2553 nvbridge_check_legacy_irq_routing);
2554
2555 static int ht_check_msi_mapping(struct pci_dev *dev)
2556 {
2557 int pos, ttl = PCI_FIND_CAP_TTL;
2558 int found = 0;
2559
2560 /* check if there is HT MSI cap or enabled on this device */
2561 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2562 while (pos && ttl--) {
2563 u8 flags;
2564
2565 if (found < 1)
2566 found = 1;
2567 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2568 &flags) == 0) {
2569 if (flags & HT_MSI_FLAGS_ENABLE) {
2570 if (found < 2) {
2571 found = 2;
2572 break;
2573 }
2574 }
2575 }
2576 pos = pci_find_next_ht_capability(dev, pos,
2577 HT_CAPTYPE_MSI_MAPPING);
2578 }
2579
2580 return found;
2581 }
2582
2583 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2584 {
2585 struct pci_dev *dev;
2586 int pos;
2587 int i, dev_no;
2588 int found = 0;
2589
2590 dev_no = host_bridge->devfn >> 3;
2591 for (i = dev_no + 1; i < 0x20; i++) {
2592 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2593 if (!dev)
2594 continue;
2595
2596 /* found next host bridge ?*/
2597 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2598 if (pos != 0) {
2599 pci_dev_put(dev);
2600 break;
2601 }
2602
2603 if (ht_check_msi_mapping(dev)) {
2604 found = 1;
2605 pci_dev_put(dev);
2606 break;
2607 }
2608 pci_dev_put(dev);
2609 }
2610
2611 return found;
2612 }
2613
2614 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2615 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2616
2617 static int is_end_of_ht_chain(struct pci_dev *dev)
2618 {
2619 int pos, ctrl_off;
2620 int end = 0;
2621 u16 flags, ctrl;
2622
2623 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2624
2625 if (!pos)
2626 goto out;
2627
2628 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2629
2630 ctrl_off = ((flags >> 10) & 1) ?
2631 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2632 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2633
2634 if (ctrl & (1 << 6))
2635 end = 1;
2636
2637 out:
2638 return end;
2639 }
2640
2641 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2642 {
2643 struct pci_dev *host_bridge;
2644 int pos;
2645 int i, dev_no;
2646 int found = 0;
2647
2648 dev_no = dev->devfn >> 3;
2649 for (i = dev_no; i >= 0; i--) {
2650 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2651 if (!host_bridge)
2652 continue;
2653
2654 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2655 if (pos != 0) {
2656 found = 1;
2657 break;
2658 }
2659 pci_dev_put(host_bridge);
2660 }
2661
2662 if (!found)
2663 return;
2664
2665 /* don't enable end_device/host_bridge with leaf directly here */
2666 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2667 host_bridge_with_leaf(host_bridge))
2668 goto out;
2669
2670 /* root did that ! */
2671 if (msi_ht_cap_enabled(host_bridge))
2672 goto out;
2673
2674 ht_enable_msi_mapping(dev);
2675
2676 out:
2677 pci_dev_put(host_bridge);
2678 }
2679
2680 static void ht_disable_msi_mapping(struct pci_dev *dev)
2681 {
2682 int pos, ttl = PCI_FIND_CAP_TTL;
2683
2684 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2685 while (pos && ttl--) {
2686 u8 flags;
2687
2688 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2689 &flags) == 0) {
2690 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2691
2692 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2693 flags & ~HT_MSI_FLAGS_ENABLE);
2694 }
2695 pos = pci_find_next_ht_capability(dev, pos,
2696 HT_CAPTYPE_MSI_MAPPING);
2697 }
2698 }
2699
2700 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2701 {
2702 struct pci_dev *host_bridge;
2703 int pos;
2704 int found;
2705
2706 if (!pci_msi_enabled())
2707 return;
2708
2709 /* check if there is HT MSI cap or enabled on this device */
2710 found = ht_check_msi_mapping(dev);
2711
2712 /* no HT MSI CAP */
2713 if (found == 0)
2714 return;
2715
2716 /*
2717 * HT MSI mapping should be disabled on devices that are below
2718 * a non-Hypertransport host bridge. Locate the host bridge...
2719 */
2720 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2721 if (host_bridge == NULL) {
2722 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2723 return;
2724 }
2725
2726 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2727 if (pos != 0) {
2728 /* Host bridge is to HT */
2729 if (found == 1) {
2730 /* it is not enabled, try to enable it */
2731 if (all)
2732 ht_enable_msi_mapping(dev);
2733 else
2734 nv_ht_enable_msi_mapping(dev);
2735 }
2736 goto out;
2737 }
2738
2739 /* HT MSI is not enabled */
2740 if (found == 1)
2741 goto out;
2742
2743 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2744 ht_disable_msi_mapping(dev);
2745
2746 out:
2747 pci_dev_put(host_bridge);
2748 }
2749
2750 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2751 {
2752 return __nv_msi_ht_cap_quirk(dev, 1);
2753 }
2754
2755 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2756 {
2757 return __nv_msi_ht_cap_quirk(dev, 0);
2758 }
2759
2760 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2761 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2762
2763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2764 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2765
2766 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2767 {
2768 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2769 }
2770 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2771 {
2772 struct pci_dev *p;
2773
2774 /* SB700 MSI issue will be fixed at HW level from revision A21,
2775 * we need check PCI REVISION ID of SMBus controller to get SB700
2776 * revision.
2777 */
2778 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2779 NULL);
2780 if (!p)
2781 return;
2782
2783 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2784 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2785 pci_dev_put(p);
2786 }
2787 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2788 {
2789 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2790 if (dev->revision < 0x18) {
2791 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2792 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2793 }
2794 }
2795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2796 PCI_DEVICE_ID_TIGON3_5780,
2797 quirk_msi_intx_disable_bug);
2798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2799 PCI_DEVICE_ID_TIGON3_5780S,
2800 quirk_msi_intx_disable_bug);
2801 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2802 PCI_DEVICE_ID_TIGON3_5714,
2803 quirk_msi_intx_disable_bug);
2804 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2805 PCI_DEVICE_ID_TIGON3_5714S,
2806 quirk_msi_intx_disable_bug);
2807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2808 PCI_DEVICE_ID_TIGON3_5715,
2809 quirk_msi_intx_disable_bug);
2810 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2811 PCI_DEVICE_ID_TIGON3_5715S,
2812 quirk_msi_intx_disable_bug);
2813
2814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2815 quirk_msi_intx_disable_ati_bug);
2816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2817 quirk_msi_intx_disable_ati_bug);
2818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2819 quirk_msi_intx_disable_ati_bug);
2820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2821 quirk_msi_intx_disable_ati_bug);
2822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2823 quirk_msi_intx_disable_ati_bug);
2824
2825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2826 quirk_msi_intx_disable_bug);
2827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2828 quirk_msi_intx_disable_bug);
2829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2830 quirk_msi_intx_disable_bug);
2831
2832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2833 quirk_msi_intx_disable_bug);
2834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2835 quirk_msi_intx_disable_bug);
2836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2837 quirk_msi_intx_disable_bug);
2838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2839 quirk_msi_intx_disable_bug);
2840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2841 quirk_msi_intx_disable_bug);
2842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2843 quirk_msi_intx_disable_bug);
2844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2845 quirk_msi_intx_disable_qca_bug);
2846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2847 quirk_msi_intx_disable_qca_bug);
2848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2849 quirk_msi_intx_disable_qca_bug);
2850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2851 quirk_msi_intx_disable_qca_bug);
2852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2853 quirk_msi_intx_disable_qca_bug);
2854 #endif /* CONFIG_PCI_MSI */
2855
2856 /* Allow manual resource allocation for PCI hotplug bridges
2857 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2858 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2859 * kernel fails to allocate resources when hotplug device is
2860 * inserted and PCI bus is rescanned.
2861 */
2862 static void quirk_hotplug_bridge(struct pci_dev *dev)
2863 {
2864 dev->is_hotplug_bridge = 1;
2865 }
2866
2867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2868
2869 /*
2870 * This is a quirk for the Ricoh MMC controller found as a part of
2871 * some mulifunction chips.
2872
2873 * This is very similar and based on the ricoh_mmc driver written by
2874 * Philip Langdale. Thank you for these magic sequences.
2875 *
2876 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2877 * and one or both of cardbus or firewire.
2878 *
2879 * It happens that they implement SD and MMC
2880 * support as separate controllers (and PCI functions). The linux SDHCI
2881 * driver supports MMC cards but the chip detects MMC cards in hardware
2882 * and directs them to the MMC controller - so the SDHCI driver never sees
2883 * them.
2884 *
2885 * To get around this, we must disable the useless MMC controller.
2886 * At that point, the SDHCI controller will start seeing them
2887 * It seems to be the case that the relevant PCI registers to deactivate the
2888 * MMC controller live on PCI function 0, which might be the cardbus controller
2889 * or the firewire controller, depending on the particular chip in question
2890 *
2891 * This has to be done early, because as soon as we disable the MMC controller
2892 * other pci functions shift up one level, e.g. function #2 becomes function
2893 * #1, and this will confuse the pci core.
2894 */
2895
2896 #ifdef CONFIG_MMC_RICOH_MMC
2897 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2898 {
2899 /* disable via cardbus interface */
2900 u8 write_enable;
2901 u8 write_target;
2902 u8 disable;
2903
2904 /* disable must be done via function #0 */
2905 if (PCI_FUNC(dev->devfn))
2906 return;
2907
2908 pci_read_config_byte(dev, 0xB7, &disable);
2909 if (disable & 0x02)
2910 return;
2911
2912 pci_read_config_byte(dev, 0x8E, &write_enable);
2913 pci_write_config_byte(dev, 0x8E, 0xAA);
2914 pci_read_config_byte(dev, 0x8D, &write_target);
2915 pci_write_config_byte(dev, 0x8D, 0xB7);
2916 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2917 pci_write_config_byte(dev, 0x8E, write_enable);
2918 pci_write_config_byte(dev, 0x8D, write_target);
2919
2920 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2921 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2922 }
2923 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2924 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2925
2926 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2927 {
2928 /* disable via firewire interface */
2929 u8 write_enable;
2930 u8 disable;
2931
2932 /* disable must be done via function #0 */
2933 if (PCI_FUNC(dev->devfn))
2934 return;
2935 /*
2936 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2937 * certain types of SD/MMC cards. Lowering the SD base
2938 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2939 *
2940 * 0x150 - SD2.0 mode enable for changing base clock
2941 * frequency to 50Mhz
2942 * 0xe1 - Base clock frequency
2943 * 0x32 - 50Mhz new clock frequency
2944 * 0xf9 - Key register for 0x150
2945 * 0xfc - key register for 0xe1
2946 */
2947 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2948 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2949 pci_write_config_byte(dev, 0xf9, 0xfc);
2950 pci_write_config_byte(dev, 0x150, 0x10);
2951 pci_write_config_byte(dev, 0xf9, 0x00);
2952 pci_write_config_byte(dev, 0xfc, 0x01);
2953 pci_write_config_byte(dev, 0xe1, 0x32);
2954 pci_write_config_byte(dev, 0xfc, 0x00);
2955
2956 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2957 }
2958
2959 pci_read_config_byte(dev, 0xCB, &disable);
2960
2961 if (disable & 0x02)
2962 return;
2963
2964 pci_read_config_byte(dev, 0xCA, &write_enable);
2965 pci_write_config_byte(dev, 0xCA, 0x57);
2966 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2967 pci_write_config_byte(dev, 0xCA, write_enable);
2968
2969 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2970 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2971
2972 }
2973 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2974 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2975 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2976 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2977 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2978 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2979 #endif /*CONFIG_MMC_RICOH_MMC*/
2980
2981 #ifdef CONFIG_DMAR_TABLE
2982 #define VTUNCERRMSK_REG 0x1ac
2983 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2984 /*
2985 * This is a quirk for masking vt-d spec defined errors to platform error
2986 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2987 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2988 * on the RAS config settings of the platform) when a vt-d fault happens.
2989 * The resulting SMI caused the system to hang.
2990 *
2991 * VT-d spec related errors are already handled by the VT-d OS code, so no
2992 * need to report the same error through other channels.
2993 */
2994 static void vtd_mask_spec_errors(struct pci_dev *dev)
2995 {
2996 u32 word;
2997
2998 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2999 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3000 }
3001 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3002 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3003 #endif
3004
3005 static void fixup_ti816x_class(struct pci_dev *dev)
3006 {
3007 u32 class = dev->class;
3008
3009 /* TI 816x devices do not have class code set when in PCIe boot mode */
3010 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3011 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
3012 class, dev->class);
3013 }
3014 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3015 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3016
3017 /* Some PCIe devices do not work reliably with the claimed maximum
3018 * payload size supported.
3019 */
3020 static void fixup_mpss_256(struct pci_dev *dev)
3021 {
3022 dev->pcie_mpss = 1; /* 256 bytes */
3023 }
3024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3025 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3027 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3029 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3030
3031 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
3032 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3033 * Since there is no way of knowing what the PCIE MPS on each fabric will be
3034 * until all of the devices are discovered and buses walked, read completion
3035 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3036 * it is possible to hotplug a device with MPS of 256B.
3037 */
3038 static void quirk_intel_mc_errata(struct pci_dev *dev)
3039 {
3040 int err;
3041 u16 rcc;
3042
3043 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3044 pcie_bus_config == PCIE_BUS_DEFAULT)
3045 return;
3046
3047 /* Intel errata specifies bits to change but does not say what they are.
3048 * Keeping them magical until such time as the registers and values can
3049 * be explained.
3050 */
3051 err = pci_read_config_word(dev, 0x48, &rcc);
3052 if (err) {
3053 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3054 return;
3055 }
3056
3057 if (!(rcc & (1 << 10)))
3058 return;
3059
3060 rcc &= ~(1 << 10);
3061
3062 err = pci_write_config_word(dev, 0x48, rcc);
3063 if (err) {
3064 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3065 return;
3066 }
3067
3068 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3069 }
3070 /* Intel 5000 series memory controllers and ports 2-7 */
3071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3085 /* Intel 5100 series memory controllers and ports 2-7 */
3086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3097
3098
3099 /*
3100 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3101 * work around this, query the size it should be configured to by the device and
3102 * modify the resource end to correspond to this new size.
3103 */
3104 static void quirk_intel_ntb(struct pci_dev *dev)
3105 {
3106 int rc;
3107 u8 val;
3108
3109 rc = pci_read_config_byte(dev, 0x00D0, &val);
3110 if (rc)
3111 return;
3112
3113 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3114
3115 rc = pci_read_config_byte(dev, 0x00D1, &val);
3116 if (rc)
3117 return;
3118
3119 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3120 }
3121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3123
3124 static ktime_t fixup_debug_start(struct pci_dev *dev,
3125 void (*fn)(struct pci_dev *dev))
3126 {
3127 ktime_t calltime = 0;
3128
3129 dev_dbg(&dev->dev, "calling %pF\n", fn);
3130 if (initcall_debug) {
3131 pr_debug("calling %pF @ %i for %s\n",
3132 fn, task_pid_nr(current), dev_name(&dev->dev));
3133 calltime = ktime_get();
3134 }
3135
3136 return calltime;
3137 }
3138
3139 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3140 void (*fn)(struct pci_dev *dev))
3141 {
3142 ktime_t delta, rettime;
3143 unsigned long long duration;
3144
3145 if (initcall_debug) {
3146 rettime = ktime_get();
3147 delta = ktime_sub(rettime, calltime);
3148 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3149 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3150 fn, duration, dev_name(&dev->dev));
3151 }
3152 }
3153
3154 /*
3155 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3156 * even though no one is handling them (f.e. i915 driver is never loaded).
3157 * Additionally the interrupt destination is not set up properly
3158 * and the interrupt ends up -somewhere-.
3159 *
3160 * These spurious interrupts are "sticky" and the kernel disables
3161 * the (shared) interrupt line after 100.000+ generated interrupts.
3162 *
3163 * Fix it by disabling the still enabled interrupts.
3164 * This resolves crashes often seen on monitor unplug.
3165 */
3166 #define I915_DEIER_REG 0x4400c
3167 static void disable_igfx_irq(struct pci_dev *dev)
3168 {
3169 void __iomem *regs = pci_iomap(dev, 0, 0);
3170 if (regs == NULL) {
3171 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3172 return;
3173 }
3174
3175 /* Check if any interrupt line is still enabled */
3176 if (readl(regs + I915_DEIER_REG) != 0) {
3177 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3178
3179 writel(0, regs + I915_DEIER_REG);
3180 }
3181
3182 pci_iounmap(dev, regs);
3183 }
3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3187
3188 /*
3189 * PCI devices which are on Intel chips can skip the 10ms delay
3190 * before entering D3 mode.
3191 */
3192 static void quirk_remove_d3_delay(struct pci_dev *dev)
3193 {
3194 dev->d3_delay = 0;
3195 }
3196 /* C600 Series devices do not need 10ms d3_delay */
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3200 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3212 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3222
3223 /*
3224 * Some devices may pass our check in pci_intx_mask_supported() if
3225 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3226 * support this feature.
3227 */
3228 static void quirk_broken_intx_masking(struct pci_dev *dev)
3229 {
3230 dev->broken_intx_masking = 1;
3231 }
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3233 quirk_broken_intx_masking);
3234 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3235 quirk_broken_intx_masking);
3236
3237 /*
3238 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3239 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3240 *
3241 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3242 */
3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3244 quirk_broken_intx_masking);
3245
3246 /*
3247 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3248 * DisINTx can be set but the interrupt status bit is non-functional.
3249 */
3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3251 quirk_broken_intx_masking);
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3253 quirk_broken_intx_masking);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3255 quirk_broken_intx_masking);
3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3257 quirk_broken_intx_masking);
3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3259 quirk_broken_intx_masking);
3260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3261 quirk_broken_intx_masking);
3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3263 quirk_broken_intx_masking);
3264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3265 quirk_broken_intx_masking);
3266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3267 quirk_broken_intx_masking);
3268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3269 quirk_broken_intx_masking);
3270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3271 quirk_broken_intx_masking);
3272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3273 quirk_broken_intx_masking);
3274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3275 quirk_broken_intx_masking);
3276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3277 quirk_broken_intx_masking);
3278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3279 quirk_broken_intx_masking);
3280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3281 quirk_broken_intx_masking);
3282
3283 static u16 mellanox_broken_intx_devs[] = {
3284 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3285 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3286 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3287 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3288 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3289 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3290 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3291 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3292 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3293 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3294 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3295 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3296 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3297 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3298 };
3299
3300 #define CONNECTX_4_CURR_MAX_MINOR 99
3301 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3302
3303 /*
3304 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3305 * If so, don't mark it as broken.
3306 * FW minor > 99 means older FW version format and no INTx masking support.
3307 * FW minor < 14 means new FW version format and no INTx masking support.
3308 */
3309 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3310 {
3311 __be32 __iomem *fw_ver;
3312 u16 fw_major;
3313 u16 fw_minor;
3314 u16 fw_subminor;
3315 u32 fw_maj_min;
3316 u32 fw_sub_min;
3317 int i;
3318
3319 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3320 if (pdev->device == mellanox_broken_intx_devs[i]) {
3321 pdev->broken_intx_masking = 1;
3322 return;
3323 }
3324 }
3325
3326 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3327 * support so shouldn't be checked further
3328 */
3329 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3330 return;
3331
3332 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3333 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3334 return;
3335
3336 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3337 if (pci_enable_device_mem(pdev)) {
3338 dev_warn(&pdev->dev, "Can't enable device memory\n");
3339 return;
3340 }
3341
3342 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3343 if (!fw_ver) {
3344 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3345 goto out;
3346 }
3347
3348 /* Reading from resource space should be 32b aligned */
3349 fw_maj_min = ioread32be(fw_ver);
3350 fw_sub_min = ioread32be(fw_ver + 1);
3351 fw_major = fw_maj_min & 0xffff;
3352 fw_minor = fw_maj_min >> 16;
3353 fw_subminor = fw_sub_min & 0xffff;
3354 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3355 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3356 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3357 fw_major, fw_minor, fw_subminor, pdev->device ==
3358 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3359 pdev->broken_intx_masking = 1;
3360 }
3361
3362 iounmap(fw_ver);
3363
3364 out:
3365 pci_disable_device(pdev);
3366 }
3367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3368 mellanox_check_broken_intx_masking);
3369
3370 static void quirk_no_bus_reset(struct pci_dev *dev)
3371 {
3372 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3373 }
3374
3375 /*
3376 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3377 * The device will throw a Link Down error on AER-capable systems and
3378 * regardless of AER, config space of the device is never accessible again
3379 * and typically causes the system to hang or reset when access is attempted.
3380 * http://www.spinics.net/lists/linux-pci/msg34797.html
3381 */
3382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3386
3387 /*
3388 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3389 * reset when used with certain child devices. After the reset, config
3390 * accesses to the child may fail.
3391 */
3392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3393
3394 static void quirk_no_pm_reset(struct pci_dev *dev)
3395 {
3396 /*
3397 * We can't do a bus reset on root bus devices, but an ineffective
3398 * PM reset may be better than nothing.
3399 */
3400 if (!pci_is_root_bus(dev->bus))
3401 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3402 }
3403
3404 /*
3405 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3406 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3407 * to have no effect on the device: it retains the framebuffer contents and
3408 * monitor sync. Advertising this support makes other layers, like VFIO,
3409 * assume pci_reset_function() is viable for this device. Mark it as
3410 * unavailable to skip it when testing reset methods.
3411 */
3412 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3413 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3414
3415 /*
3416 * Thunderbolt controllers with broken MSI hotplug signaling:
3417 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3418 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3419 */
3420 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3421 {
3422 if (pdev->is_hotplug_bridge &&
3423 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3424 pdev->revision <= 1))
3425 pdev->no_msi = 1;
3426 }
3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3428 quirk_thunderbolt_hotplug_msi);
3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3430 quirk_thunderbolt_hotplug_msi);
3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3432 quirk_thunderbolt_hotplug_msi);
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3434 quirk_thunderbolt_hotplug_msi);
3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3436 quirk_thunderbolt_hotplug_msi);
3437
3438 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3439 {
3440 int chip = (dev->device & 0xf000) >> 12;
3441 int func = (dev->device & 0x0f00) >> 8;
3442 int prod = (dev->device & 0x00ff) >> 0;
3443
3444 /*
3445 * If this is a T3-based adapter, there's a 1KB VPD area at offset
3446 * 0xc00 which contains the preferred VPD values. If this is a T4 or
3447 * later based adapter, the special VPD is at offset 0x400 for the
3448 * Physical Functions (the SR-IOV Virtual Functions have no VPD
3449 * Capabilities). The PCI VPD Access core routines will normally
3450 * compute the size of the VPD by parsing the VPD Data Structure at
3451 * offset 0x000. This will result in silent failures when attempting
3452 * to accesses these other VPD areas which are beyond those computed
3453 * limits.
3454 */
3455 if (chip == 0x0 && prod >= 0x20)
3456 pci_set_vpd_size(dev, 8192);
3457 else if (chip >= 0x4 && func < 0x8)
3458 pci_set_vpd_size(dev, 2048);
3459 }
3460
3461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3462 quirk_chelsio_extend_vpd);
3463
3464 #ifdef CONFIG_ACPI
3465 /*
3466 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3467 *
3468 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3469 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3470 * be present after resume if a device was plugged in before suspend.
3471 *
3472 * The thunderbolt controller consists of a pcie switch with downstream
3473 * bridges leading to the NHI and to the tunnel pci bridges.
3474 *
3475 * This quirk cuts power to the whole chip. Therefore we have to apply it
3476 * during suspend_noirq of the upstream bridge.
3477 *
3478 * Power is automagically restored before resume. No action is needed.
3479 */
3480 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3481 {
3482 acpi_handle bridge, SXIO, SXFP, SXLV;
3483
3484 if (!x86_apple_machine)
3485 return;
3486 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3487 return;
3488 bridge = ACPI_HANDLE(&dev->dev);
3489 if (!bridge)
3490 return;
3491 /*
3492 * SXIO and SXLV are present only on machines requiring this quirk.
3493 * TB bridges in external devices might have the same device id as those
3494 * on the host, but they will not have the associated ACPI methods. This
3495 * implicitly checks that we are at the right bridge.
3496 */
3497 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3498 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3499 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3500 return;
3501 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3502
3503 /* magic sequence */
3504 acpi_execute_simple_method(SXIO, NULL, 1);
3505 acpi_execute_simple_method(SXFP, NULL, 0);
3506 msleep(300);
3507 acpi_execute_simple_method(SXLV, NULL, 0);
3508 acpi_execute_simple_method(SXIO, NULL, 0);
3509 acpi_execute_simple_method(SXLV, NULL, 0);
3510 }
3511 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3512 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3513 quirk_apple_poweroff_thunderbolt);
3514
3515 /*
3516 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3517 *
3518 * During suspend the thunderbolt controller is reset and all pci
3519 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3520 * during resume. We have to manually wait for the NHI since there is
3521 * no parent child relationship between the NHI and the tunneled
3522 * bridges.
3523 */
3524 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3525 {
3526 struct pci_dev *sibling = NULL;
3527 struct pci_dev *nhi = NULL;
3528
3529 if (!x86_apple_machine)
3530 return;
3531 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3532 return;
3533 /*
3534 * Find the NHI and confirm that we are a bridge on the tb host
3535 * controller and not on a tb endpoint.
3536 */
3537 sibling = pci_get_slot(dev->bus, 0x0);
3538 if (sibling == dev)
3539 goto out; /* we are the downstream bridge to the NHI */
3540 if (!sibling || !sibling->subordinate)
3541 goto out;
3542 nhi = pci_get_slot(sibling->subordinate, 0x0);
3543 if (!nhi)
3544 goto out;
3545 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3546 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3547 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3548 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3549 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3550 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3551 goto out;
3552 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3553 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3554 out:
3555 pci_dev_put(nhi);
3556 pci_dev_put(sibling);
3557 }
3558 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3559 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3560 quirk_apple_wait_for_thunderbolt);
3561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3562 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3563 quirk_apple_wait_for_thunderbolt);
3564 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3565 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3566 quirk_apple_wait_for_thunderbolt);
3567 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3568 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3569 quirk_apple_wait_for_thunderbolt);
3570 #endif
3571
3572 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3573 struct pci_fixup *end)
3574 {
3575 ktime_t calltime;
3576
3577 for (; f < end; f++)
3578 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3579 f->class == (u32) PCI_ANY_ID) &&
3580 (f->vendor == dev->vendor ||
3581 f->vendor == (u16) PCI_ANY_ID) &&
3582 (f->device == dev->device ||
3583 f->device == (u16) PCI_ANY_ID)) {
3584 calltime = fixup_debug_start(dev, f->hook);
3585 f->hook(dev);
3586 fixup_debug_report(dev, calltime, f->hook);
3587 }
3588 }
3589
3590 extern struct pci_fixup __start_pci_fixups_early[];
3591 extern struct pci_fixup __end_pci_fixups_early[];
3592 extern struct pci_fixup __start_pci_fixups_header[];
3593 extern struct pci_fixup __end_pci_fixups_header[];
3594 extern struct pci_fixup __start_pci_fixups_final[];
3595 extern struct pci_fixup __end_pci_fixups_final[];
3596 extern struct pci_fixup __start_pci_fixups_enable[];
3597 extern struct pci_fixup __end_pci_fixups_enable[];
3598 extern struct pci_fixup __start_pci_fixups_resume[];
3599 extern struct pci_fixup __end_pci_fixups_resume[];
3600 extern struct pci_fixup __start_pci_fixups_resume_early[];
3601 extern struct pci_fixup __end_pci_fixups_resume_early[];
3602 extern struct pci_fixup __start_pci_fixups_suspend[];
3603 extern struct pci_fixup __end_pci_fixups_suspend[];
3604 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3605 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3606
3607 static bool pci_apply_fixup_final_quirks;
3608
3609 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3610 {
3611 struct pci_fixup *start, *end;
3612
3613 switch (pass) {
3614 case pci_fixup_early:
3615 start = __start_pci_fixups_early;
3616 end = __end_pci_fixups_early;
3617 break;
3618
3619 case pci_fixup_header:
3620 start = __start_pci_fixups_header;
3621 end = __end_pci_fixups_header;
3622 break;
3623
3624 case pci_fixup_final:
3625 if (!pci_apply_fixup_final_quirks)
3626 return;
3627 start = __start_pci_fixups_final;
3628 end = __end_pci_fixups_final;
3629 break;
3630
3631 case pci_fixup_enable:
3632 start = __start_pci_fixups_enable;
3633 end = __end_pci_fixups_enable;
3634 break;
3635
3636 case pci_fixup_resume:
3637 start = __start_pci_fixups_resume;
3638 end = __end_pci_fixups_resume;
3639 break;
3640
3641 case pci_fixup_resume_early:
3642 start = __start_pci_fixups_resume_early;
3643 end = __end_pci_fixups_resume_early;
3644 break;
3645
3646 case pci_fixup_suspend:
3647 start = __start_pci_fixups_suspend;
3648 end = __end_pci_fixups_suspend;
3649 break;
3650
3651 case pci_fixup_suspend_late:
3652 start = __start_pci_fixups_suspend_late;
3653 end = __end_pci_fixups_suspend_late;
3654 break;
3655
3656 default:
3657 /* stupid compiler warning, you would think with an enum... */
3658 return;
3659 }
3660 pci_do_fixups(dev, start, end);
3661 }
3662 EXPORT_SYMBOL(pci_fixup_device);
3663
3664
3665 static int __init pci_apply_final_quirks(void)
3666 {
3667 struct pci_dev *dev = NULL;
3668 u8 cls = 0;
3669 u8 tmp;
3670
3671 if (pci_cache_line_size)
3672 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3673 pci_cache_line_size << 2);
3674
3675 pci_apply_fixup_final_quirks = true;
3676 for_each_pci_dev(dev) {
3677 pci_fixup_device(pci_fixup_final, dev);
3678 /*
3679 * If arch hasn't set it explicitly yet, use the CLS
3680 * value shared by all PCI devices. If there's a
3681 * mismatch, fall back to the default value.
3682 */
3683 if (!pci_cache_line_size) {
3684 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3685 if (!cls)
3686 cls = tmp;
3687 if (!tmp || cls == tmp)
3688 continue;
3689
3690 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3691 cls << 2, tmp << 2,
3692 pci_dfl_cache_line_size << 2);
3693 pci_cache_line_size = pci_dfl_cache_line_size;
3694 }
3695 }
3696
3697 if (!pci_cache_line_size) {
3698 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3699 cls << 2, pci_dfl_cache_line_size << 2);
3700 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3701 }
3702
3703 return 0;
3704 }
3705
3706 fs_initcall_sync(pci_apply_final_quirks);
3707
3708 /*
3709 * Following are device-specific reset methods which can be used to
3710 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3711 * not available.
3712 */
3713 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3714 {
3715 /*
3716 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3717 *
3718 * The 82599 supports FLR on VFs, but FLR support is reported only
3719 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3720 * Thus we must call pcie_flr() directly without first checking if it is
3721 * supported.
3722 */
3723 if (!probe)
3724 pcie_flr(dev);
3725 return 0;
3726 }
3727
3728 #define SOUTH_CHICKEN2 0xc2004
3729 #define PCH_PP_STATUS 0xc7200
3730 #define PCH_PP_CONTROL 0xc7204
3731 #define MSG_CTL 0x45010
3732 #define NSDE_PWR_STATE 0xd0100
3733 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3734
3735 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3736 {
3737 void __iomem *mmio_base;
3738 unsigned long timeout;
3739 u32 val;
3740
3741 if (probe)
3742 return 0;
3743
3744 mmio_base = pci_iomap(dev, 0, 0);
3745 if (!mmio_base)
3746 return -ENOMEM;
3747
3748 iowrite32(0x00000002, mmio_base + MSG_CTL);
3749
3750 /*
3751 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3752 * driver loaded sets the right bits. However, this's a reset and
3753 * the bits have been set by i915 previously, so we clobber
3754 * SOUTH_CHICKEN2 register directly here.
3755 */
3756 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3757
3758 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3759 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3760
3761 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3762 do {
3763 val = ioread32(mmio_base + PCH_PP_STATUS);
3764 if ((val & 0xb0000000) == 0)
3765 goto reset_complete;
3766 msleep(10);
3767 } while (time_before(jiffies, timeout));
3768 dev_warn(&dev->dev, "timeout during reset\n");
3769
3770 reset_complete:
3771 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3772
3773 pci_iounmap(dev, mmio_base);
3774 return 0;
3775 }
3776
3777 /*
3778 * Device-specific reset method for Chelsio T4-based adapters.
3779 */
3780 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3781 {
3782 u16 old_command;
3783 u16 msix_flags;
3784
3785 /*
3786 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3787 * that we have no device-specific reset method.
3788 */
3789 if ((dev->device & 0xf000) != 0x4000)
3790 return -ENOTTY;
3791
3792 /*
3793 * If this is the "probe" phase, return 0 indicating that we can
3794 * reset this device.
3795 */
3796 if (probe)
3797 return 0;
3798
3799 /*
3800 * T4 can wedge if there are DMAs in flight within the chip and Bus
3801 * Master has been disabled. We need to have it on till the Function
3802 * Level Reset completes. (BUS_MASTER is disabled in
3803 * pci_reset_function()).
3804 */
3805 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3806 pci_write_config_word(dev, PCI_COMMAND,
3807 old_command | PCI_COMMAND_MASTER);
3808
3809 /*
3810 * Perform the actual device function reset, saving and restoring
3811 * configuration information around the reset.
3812 */
3813 pci_save_state(dev);
3814
3815 /*
3816 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3817 * are disabled when an MSI-X interrupt message needs to be delivered.
3818 * So we briefly re-enable MSI-X interrupts for the duration of the
3819 * FLR. The pci_restore_state() below will restore the original
3820 * MSI-X state.
3821 */
3822 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3823 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3824 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3825 msix_flags |
3826 PCI_MSIX_FLAGS_ENABLE |
3827 PCI_MSIX_FLAGS_MASKALL);
3828
3829 pcie_flr(dev);
3830
3831 /*
3832 * Restore the configuration information (BAR values, etc.) including
3833 * the original PCI Configuration Space Command word, and return
3834 * success.
3835 */
3836 pci_restore_state(dev);
3837 pci_write_config_word(dev, PCI_COMMAND, old_command);
3838 return 0;
3839 }
3840
3841 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3842 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3843 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3844
3845 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3846 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3847 reset_intel_82599_sfp_virtfn },
3848 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3849 reset_ivb_igd },
3850 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3851 reset_ivb_igd },
3852 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3853 reset_chelsio_generic_dev },
3854 { 0 }
3855 };
3856
3857 /*
3858 * These device-specific reset methods are here rather than in a driver
3859 * because when a host assigns a device to a guest VM, the host may need
3860 * to reset the device but probably doesn't have a driver for it.
3861 */
3862 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3863 {
3864 const struct pci_dev_reset_methods *i;
3865
3866 for (i = pci_dev_reset_methods; i->reset; i++) {
3867 if ((i->vendor == dev->vendor ||
3868 i->vendor == (u16)PCI_ANY_ID) &&
3869 (i->device == dev->device ||
3870 i->device == (u16)PCI_ANY_ID))
3871 return i->reset(dev, probe);
3872 }
3873
3874 return -ENOTTY;
3875 }
3876
3877 static void quirk_dma_func0_alias(struct pci_dev *dev)
3878 {
3879 if (PCI_FUNC(dev->devfn) != 0)
3880 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3881 }
3882
3883 /*
3884 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3885 *
3886 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3887 */
3888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3890
3891 static void quirk_dma_func1_alias(struct pci_dev *dev)
3892 {
3893 if (PCI_FUNC(dev->devfn) != 1)
3894 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3895 }
3896
3897 /*
3898 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3899 * SKUs function 1 is present and is a legacy IDE controller, in other
3900 * SKUs this function is not present, making this a ghost requester.
3901 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3902 */
3903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3904 quirk_dma_func1_alias);
3905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3906 quirk_dma_func1_alias);
3907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3908 quirk_dma_func1_alias);
3909 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3911 quirk_dma_func1_alias);
3912 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3914 quirk_dma_func1_alias);
3915 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3917 quirk_dma_func1_alias);
3918 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3920 quirk_dma_func1_alias);
3921 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3923 quirk_dma_func1_alias);
3924 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3926 quirk_dma_func1_alias);
3927 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3928 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3929 quirk_dma_func1_alias);
3930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3931 quirk_dma_func1_alias);
3932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3933 quirk_dma_func1_alias);
3934 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3936 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3937 quirk_dma_func1_alias);
3938 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3939 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3940 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3941 quirk_dma_func1_alias);
3942
3943 /*
3944 * Some devices DMA with the wrong devfn, not just the wrong function.
3945 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3946 * the alias is "fixed" and independent of the device devfn.
3947 *
3948 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3949 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3950 * single device on the secondary bus. In reality, the single exposed
3951 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3952 * that provides a bridge to the internal bus of the I/O processor. The
3953 * controller supports private devices, which can be hidden from PCI config
3954 * space. In the case of the Adaptec 3405, a private device at 01.0
3955 * appears to be the DMA engine, which therefore needs to become a DMA
3956 * alias for the device.
3957 */
3958 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3959 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3960 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3961 .driver_data = PCI_DEVFN(1, 0) },
3962 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3963 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3964 .driver_data = PCI_DEVFN(1, 0) },
3965 { 0 }
3966 };
3967
3968 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3969 {
3970 const struct pci_device_id *id;
3971
3972 id = pci_match_id(fixed_dma_alias_tbl, dev);
3973 if (id)
3974 pci_add_dma_alias(dev, id->driver_data);
3975 }
3976
3977 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3978
3979 /*
3980 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3981 * using the wrong DMA alias for the device. Some of these devices can be
3982 * used as either forward or reverse bridges, so we need to test whether the
3983 * device is operating in the correct mode. We could probably apply this
3984 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3985 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3986 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3987 */
3988 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3989 {
3990 if (!pci_is_root_bus(pdev->bus) &&
3991 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3992 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3993 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3994 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3995 }
3996 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3998 quirk_use_pcie_bridge_dma_alias);
3999 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4000 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4001 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4002 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4003 /* ITE 8893 has the same problem as the 8892 */
4004 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4005 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4006 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4007
4008 /*
4009 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4010 * be added as aliases to the DMA device in order to allow buffer access
4011 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4012 * programmed in the EEPROM.
4013 */
4014 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4015 {
4016 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
4017 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
4018 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
4019 }
4020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4022
4023 /*
4024 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4025 * associated not at the root bus, but at a bridge below. This quirk avoids
4026 * generating invalid DMA aliases.
4027 */
4028 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4029 {
4030 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4031 }
4032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4033 quirk_bridge_cavm_thrx2_pcie_root);
4034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4035 quirk_bridge_cavm_thrx2_pcie_root);
4036
4037 /*
4038 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4039 * class code. Fix it.
4040 */
4041 static void quirk_tw686x_class(struct pci_dev *pdev)
4042 {
4043 u32 class = pdev->class;
4044
4045 /* Use "Multimedia controller" class */
4046 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4047 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4048 class, pdev->class);
4049 }
4050 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4051 quirk_tw686x_class);
4052 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4053 quirk_tw686x_class);
4054 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4055 quirk_tw686x_class);
4056 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4057 quirk_tw686x_class);
4058
4059 /*
4060 * Some devices have problems with Transaction Layer Packets with the Relaxed
4061 * Ordering Attribute set. Such devices should mark themselves and other
4062 * Device Drivers should check before sending TLPs with RO set.
4063 */
4064 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4065 {
4066 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4067 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4068 }
4069
4070 /*
4071 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4072 * Complex has a Flow Control Credit issue which can cause performance
4073 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4074 */
4075 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4076 quirk_relaxedordering_disable);
4077 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4078 quirk_relaxedordering_disable);
4079 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4080 quirk_relaxedordering_disable);
4081 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4082 quirk_relaxedordering_disable);
4083 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4084 quirk_relaxedordering_disable);
4085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4086 quirk_relaxedordering_disable);
4087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4088 quirk_relaxedordering_disable);
4089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4090 quirk_relaxedordering_disable);
4091 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4092 quirk_relaxedordering_disable);
4093 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4094 quirk_relaxedordering_disable);
4095 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4096 quirk_relaxedordering_disable);
4097 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4098 quirk_relaxedordering_disable);
4099 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4100 quirk_relaxedordering_disable);
4101 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4102 quirk_relaxedordering_disable);
4103 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4104 quirk_relaxedordering_disable);
4105 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4106 quirk_relaxedordering_disable);
4107 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4108 quirk_relaxedordering_disable);
4109 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4110 quirk_relaxedordering_disable);
4111 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4112 quirk_relaxedordering_disable);
4113 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4114 quirk_relaxedordering_disable);
4115 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4116 quirk_relaxedordering_disable);
4117 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4118 quirk_relaxedordering_disable);
4119 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4120 quirk_relaxedordering_disable);
4121 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4122 quirk_relaxedordering_disable);
4123 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4124 quirk_relaxedordering_disable);
4125 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4126 quirk_relaxedordering_disable);
4127 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4128 quirk_relaxedordering_disable);
4129 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4130 quirk_relaxedordering_disable);
4131
4132 /*
4133 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4134 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4135 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4136 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4137 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4138 * November 10, 2010). As a result, on this platform we can't use Relaxed
4139 * Ordering for Upstream TLPs.
4140 */
4141 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4142 quirk_relaxedordering_disable);
4143 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4144 quirk_relaxedordering_disable);
4145 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4146 quirk_relaxedordering_disable);
4147
4148 /*
4149 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4150 * values for the Attribute as were supplied in the header of the
4151 * corresponding Request, except as explicitly allowed when IDO is used."
4152 *
4153 * If a non-compliant device generates a completion with a different
4154 * attribute than the request, the receiver may accept it (which itself
4155 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4156 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4157 * device access timeout.
4158 *
4159 * If the non-compliant device generates completions with zero attributes
4160 * (instead of copying the attributes from the request), we can work around
4161 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4162 * upstream devices so they always generate requests with zero attributes.
4163 *
4164 * This affects other devices under the same Root Port, but since these
4165 * attributes are performance hints, there should be no functional problem.
4166 *
4167 * Note that Configuration Space accesses are never supposed to have TLP
4168 * Attributes, so we're safe waiting till after any Configuration Space
4169 * accesses to do the Root Port fixup.
4170 */
4171 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4172 {
4173 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4174
4175 if (!root_port) {
4176 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4177 return;
4178 }
4179
4180 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4181 dev_name(&pdev->dev));
4182 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4183 PCI_EXP_DEVCTL_RELAX_EN |
4184 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4185 }
4186
4187 /*
4188 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4189 * Completion it generates.
4190 */
4191 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4192 {
4193 /*
4194 * This mask/compare operation selects for Physical Function 4 on a
4195 * T5. We only need to fix up the Root Port once for any of the
4196 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4197 * 0x54xx so we use that one,
4198 */
4199 if ((pdev->device & 0xff00) == 0x5400)
4200 quirk_disable_root_port_attributes(pdev);
4201 }
4202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4203 quirk_chelsio_T5_disable_root_port_attributes);
4204
4205 /*
4206 * AMD has indicated that the devices below do not support peer-to-peer
4207 * in any system where they are found in the southbridge with an AMD
4208 * IOMMU in the system. Multifunction devices that do not support
4209 * peer-to-peer between functions can claim to support a subset of ACS.
4210 * Such devices effectively enable request redirect (RR) and completion
4211 * redirect (CR) since all transactions are redirected to the upstream
4212 * root complex.
4213 *
4214 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4215 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4216 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4217 *
4218 * 1002:4385 SBx00 SMBus Controller
4219 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4220 * 1002:4383 SBx00 Azalia (Intel HDA)
4221 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4222 * 1002:4384 SBx00 PCI to PCI Bridge
4223 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4224 *
4225 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4226 *
4227 * 1022:780f [AMD] FCH PCI Bridge
4228 * 1022:7809 [AMD] FCH USB OHCI Controller
4229 */
4230 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4231 {
4232 #ifdef CONFIG_ACPI
4233 struct acpi_table_header *header = NULL;
4234 acpi_status status;
4235
4236 /* Targeting multifunction devices on the SB (appears on root bus) */
4237 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4238 return -ENODEV;
4239
4240 /* The IVRS table describes the AMD IOMMU */
4241 status = acpi_get_table("IVRS", 0, &header);
4242 if (ACPI_FAILURE(status))
4243 return -ENODEV;
4244
4245 /* Filter out flags not applicable to multifunction */
4246 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4247
4248 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4249 #else
4250 return -ENODEV;
4251 #endif
4252 }
4253
4254 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4255 {
4256 /*
4257 * Effectively selects all downstream ports for whole ThunderX 1
4258 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4259 * bits of device ID are used to indicate which subdevice is used
4260 * within the SoC.
4261 */
4262 return (pci_is_pcie(dev) &&
4263 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4264 ((dev->device & 0xf800) == 0xa000));
4265 }
4266
4267 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4268 {
4269 /*
4270 * Cavium root ports don't advertise an ACS capability. However,
4271 * the RTL internally implements similar protection as if ACS had
4272 * Request Redirection, Completion Redirection, Source Validation,
4273 * and Upstream Forwarding features enabled. Assert that the
4274 * hardware implements and enables equivalent ACS functionality for
4275 * these flags.
4276 */
4277 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4278
4279 if (!pci_quirk_cavium_acs_match(dev))
4280 return -ENOTTY;
4281
4282 return acs_flags ? 0 : 1;
4283 }
4284
4285 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4286 {
4287 /*
4288 * X-Gene root matching this quirk do not allow peer-to-peer
4289 * transactions with others, allowing masking out these bits as if they
4290 * were unimplemented in the ACS capability.
4291 */
4292 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4293
4294 return acs_flags ? 0 : 1;
4295 }
4296
4297 /*
4298 * Many Intel PCH root ports do provide ACS-like features to disable peer
4299 * transactions and validate bus numbers in requests, but do not provide an
4300 * actual PCIe ACS capability. This is the list of device IDs known to fall
4301 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4302 */
4303 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4304 /* Ibexpeak PCH */
4305 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4306 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4307 /* Cougarpoint PCH */
4308 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4309 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4310 /* Pantherpoint PCH */
4311 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4312 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4313 /* Lynxpoint-H PCH */
4314 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4315 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4316 /* Lynxpoint-LP PCH */
4317 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4318 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4319 /* Wildcat PCH */
4320 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4321 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4322 /* Patsburg (X79) PCH */
4323 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4324 /* Wellsburg (X99) PCH */
4325 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4326 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4327 /* Lynx Point (9 series) PCH */
4328 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4329 };
4330
4331 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4332 {
4333 int i;
4334
4335 /* Filter out a few obvious non-matches first */
4336 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4337 return false;
4338
4339 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4340 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4341 return true;
4342
4343 return false;
4344 }
4345
4346 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4347
4348 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4349 {
4350 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4351 INTEL_PCH_ACS_FLAGS : 0;
4352
4353 if (!pci_quirk_intel_pch_acs_match(dev))
4354 return -ENOTTY;
4355
4356 return acs_flags & ~flags ? 0 : 1;
4357 }
4358
4359 /*
4360 * These QCOM root ports do provide ACS-like features to disable peer
4361 * transactions and validate bus numbers in requests, but do not provide an
4362 * actual PCIe ACS capability. Hardware supports source validation but it
4363 * will report the issue as Completer Abort instead of ACS Violation.
4364 * Hardware doesn't support peer-to-peer and each root port is a root
4365 * complex with unique segment numbers. It is not possible for one root
4366 * port to pass traffic to another root port. All PCIe transactions are
4367 * terminated inside the root port.
4368 */
4369 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4370 {
4371 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4372 int ret = acs_flags & ~flags ? 0 : 1;
4373
4374 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4375
4376 return ret;
4377 }
4378
4379 /*
4380 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4381 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4382 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4383 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4384 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4385 * control register is at offset 8 instead of 6 and we should probably use
4386 * dword accesses to them. This applies to the following PCI Device IDs, as
4387 * found in volume 1 of the datasheet[2]:
4388 *
4389 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4390 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4391 *
4392 * N.B. This doesn't fix what lspci shows.
4393 *
4394 * The 100 series chipset specification update includes this as errata #23[3].
4395 *
4396 * The 200 series chipset (Union Point) has the same bug according to the
4397 * specification update (Intel 200 Series Chipset Family Platform Controller
4398 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4399 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4400 * chipset include:
4401 *
4402 * 0xa290-0xa29f PCI Express Root port #{0-16}
4403 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4404 *
4405 * Mobile chipsets are also affected, 7th & 8th Generation
4406 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4407 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4408 * Processor Family I/O for U Quad Core Platforms Specification Update,
4409 * August 2017, Revision 002, Document#: 334660-002)[6]
4410 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4411 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4412 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4413 *
4414 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4415 *
4416 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4417 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4418 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4419 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4420 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4421 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4422 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4423 */
4424 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4425 {
4426 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4427 return false;
4428
4429 switch (dev->device) {
4430 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4431 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4432 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4433 return true;
4434 }
4435
4436 return false;
4437 }
4438
4439 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4440
4441 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4442 {
4443 int pos;
4444 u32 cap, ctrl;
4445
4446 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4447 return -ENOTTY;
4448
4449 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4450 if (!pos)
4451 return -ENOTTY;
4452
4453 /* see pci_acs_flags_enabled() */
4454 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4455 acs_flags &= (cap | PCI_ACS_EC);
4456
4457 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4458
4459 return acs_flags & ~ctrl ? 0 : 1;
4460 }
4461
4462 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4463 {
4464 /*
4465 * SV, TB, and UF are not relevant to multifunction endpoints.
4466 *
4467 * Multifunction devices are only required to implement RR, CR, and DT
4468 * in their ACS capability if they support peer-to-peer transactions.
4469 * Devices matching this quirk have been verified by the vendor to not
4470 * perform peer-to-peer with other functions, allowing us to mask out
4471 * these bits as if they were unimplemented in the ACS capability.
4472 */
4473 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4474 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4475
4476 return acs_flags ? 0 : 1;
4477 }
4478
4479 static const struct pci_dev_acs_enabled {
4480 u16 vendor;
4481 u16 device;
4482 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4483 } pci_dev_acs_enabled[] = {
4484 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4485 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4486 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4487 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4488 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4489 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4490 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4491 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4492 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4493 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4494 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4495 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4496 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4497 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4498 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4499 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4500 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4501 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4502 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4503 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4504 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4505 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4506 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4507 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4508 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4509 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4510 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4511 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4512 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4513 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4514 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4515 /* 82580 */
4516 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4517 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4518 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4519 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4520 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4521 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4522 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4523 /* 82576 */
4524 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4525 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4526 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4527 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4528 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4529 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4530 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4531 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4532 /* 82575 */
4533 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4534 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4535 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4536 /* I350 */
4537 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4538 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4539 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4540 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4541 /* 82571 (Quads omitted due to non-ACS switch) */
4542 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4543 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4544 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4545 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4546 /* I219 */
4547 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4548 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4549 /* QCOM QDF2xxx root ports */
4550 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4551 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4552 /* Intel PCH root ports */
4553 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4554 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4555 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4556 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4557 /* Cavium ThunderX */
4558 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4559 /* APM X-Gene */
4560 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4561 { 0 }
4562 };
4563
4564 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4565 {
4566 const struct pci_dev_acs_enabled *i;
4567 int ret;
4568
4569 /*
4570 * Allow devices that do not expose standard PCIe ACS capabilities
4571 * or control to indicate their support here. Multi-function express
4572 * devices which do not allow internal peer-to-peer between functions,
4573 * but do not implement PCIe ACS may wish to return true here.
4574 */
4575 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4576 if ((i->vendor == dev->vendor ||
4577 i->vendor == (u16)PCI_ANY_ID) &&
4578 (i->device == dev->device ||
4579 i->device == (u16)PCI_ANY_ID)) {
4580 ret = i->acs_enabled(dev, acs_flags);
4581 if (ret >= 0)
4582 return ret;
4583 }
4584 }
4585
4586 return -ENOTTY;
4587 }
4588
4589 /* Config space offset of Root Complex Base Address register */
4590 #define INTEL_LPC_RCBA_REG 0xf0
4591 /* 31:14 RCBA address */
4592 #define INTEL_LPC_RCBA_MASK 0xffffc000
4593 /* RCBA Enable */
4594 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4595
4596 /* Backbone Scratch Pad Register */
4597 #define INTEL_BSPR_REG 0x1104
4598 /* Backbone Peer Non-Posted Disable */
4599 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4600 /* Backbone Peer Posted Disable */
4601 #define INTEL_BSPR_REG_BPPD (1 << 9)
4602
4603 /* Upstream Peer Decode Configuration Register */
4604 #define INTEL_UPDCR_REG 0x1114
4605 /* 5:0 Peer Decode Enable bits */
4606 #define INTEL_UPDCR_REG_MASK 0x3f
4607
4608 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4609 {
4610 u32 rcba, bspr, updcr;
4611 void __iomem *rcba_mem;
4612
4613 /*
4614 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4615 * are D28:F* and therefore get probed before LPC, thus we can't
4616 * use pci_get_slot/pci_read_config_dword here.
4617 */
4618 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4619 INTEL_LPC_RCBA_REG, &rcba);
4620 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4621 return -EINVAL;
4622
4623 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4624 PAGE_ALIGN(INTEL_UPDCR_REG));
4625 if (!rcba_mem)
4626 return -ENOMEM;
4627
4628 /*
4629 * The BSPR can disallow peer cycles, but it's set by soft strap and
4630 * therefore read-only. If both posted and non-posted peer cycles are
4631 * disallowed, we're ok. If either are allowed, then we need to use
4632 * the UPDCR to disable peer decodes for each port. This provides the
4633 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4634 */
4635 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4636 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4637 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4638 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4639 if (updcr & INTEL_UPDCR_REG_MASK) {
4640 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4641 updcr &= ~INTEL_UPDCR_REG_MASK;
4642 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4643 }
4644 }
4645
4646 iounmap(rcba_mem);
4647 return 0;
4648 }
4649
4650 /* Miscellaneous Port Configuration register */
4651 #define INTEL_MPC_REG 0xd8
4652 /* MPC: Invalid Receive Bus Number Check Enable */
4653 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4654
4655 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4656 {
4657 u32 mpc;
4658
4659 /*
4660 * When enabled, the IRBNCE bit of the MPC register enables the
4661 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4662 * ensures that requester IDs fall within the bus number range
4663 * of the bridge. Enable if not already.
4664 */
4665 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4666 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4667 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4668 mpc |= INTEL_MPC_REG_IRBNCE;
4669 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4670 }
4671 }
4672
4673 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4674 {
4675 if (!pci_quirk_intel_pch_acs_match(dev))
4676 return -ENOTTY;
4677
4678 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4679 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4680 return 0;
4681 }
4682
4683 pci_quirk_enable_intel_rp_mpc_acs(dev);
4684
4685 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4686
4687 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4688
4689 return 0;
4690 }
4691
4692 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4693 {
4694 int pos;
4695 u32 cap, ctrl;
4696
4697 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4698 return -ENOTTY;
4699
4700 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4701 if (!pos)
4702 return -ENOTTY;
4703
4704 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4705 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4706
4707 ctrl |= (cap & PCI_ACS_SV);
4708 ctrl |= (cap & PCI_ACS_RR);
4709 ctrl |= (cap & PCI_ACS_CR);
4710 ctrl |= (cap & PCI_ACS_UF);
4711
4712 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4713
4714 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4715
4716 return 0;
4717 }
4718
4719 static const struct pci_dev_enable_acs {
4720 u16 vendor;
4721 u16 device;
4722 int (*enable_acs)(struct pci_dev *dev);
4723 } pci_dev_enable_acs[] = {
4724 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4725 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4726 { 0 }
4727 };
4728
4729 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4730 {
4731 const struct pci_dev_enable_acs *i;
4732 int ret;
4733
4734 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4735 if ((i->vendor == dev->vendor ||
4736 i->vendor == (u16)PCI_ANY_ID) &&
4737 (i->device == dev->device ||
4738 i->device == (u16)PCI_ANY_ID)) {
4739 ret = i->enable_acs(dev);
4740 if (ret >= 0)
4741 return ret;
4742 }
4743 }
4744
4745 return -ENOTTY;
4746 }
4747
4748 /*
4749 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4750 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4751 * Next Capability pointer in the MSI Capability Structure should point to
4752 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4753 * the list.
4754 */
4755 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4756 {
4757 int pos, i = 0;
4758 u8 next_cap;
4759 u16 reg16, *cap;
4760 struct pci_cap_saved_state *state;
4761
4762 /* Bail if the hardware bug is fixed */
4763 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4764 return;
4765
4766 /* Bail if MSI Capability Structure is not found for some reason */
4767 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4768 if (!pos)
4769 return;
4770
4771 /*
4772 * Bail if Next Capability pointer in the MSI Capability Structure
4773 * is not the expected incorrect 0x00.
4774 */
4775 pci_read_config_byte(pdev, pos + 1, &next_cap);
4776 if (next_cap)
4777 return;
4778
4779 /*
4780 * PCIe Capability Structure is expected to be at 0x50 and should
4781 * terminate the list (Next Capability pointer is 0x00). Verify
4782 * Capability Id and Next Capability pointer is as expected.
4783 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4784 * to correctly set kernel data structures which have already been
4785 * set incorrectly due to the hardware bug.
4786 */
4787 pos = 0x50;
4788 pci_read_config_word(pdev, pos, &reg16);
4789 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4790 u32 status;
4791 #ifndef PCI_EXP_SAVE_REGS
4792 #define PCI_EXP_SAVE_REGS 7
4793 #endif
4794 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4795
4796 pdev->pcie_cap = pos;
4797 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4798 pdev->pcie_flags_reg = reg16;
4799 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4800 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4801
4802 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4803 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4804 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4805 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4806
4807 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4808 return;
4809
4810 /*
4811 * Save PCIE cap
4812 */
4813 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4814 if (!state)
4815 return;
4816
4817 state->cap.cap_nr = PCI_CAP_ID_EXP;
4818 state->cap.cap_extended = 0;
4819 state->cap.size = size;
4820 cap = (u16 *)&state->cap.data[0];
4821 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4822 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4823 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4824 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4825 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4826 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4827 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4828 hlist_add_head(&state->next, &pdev->saved_cap_space);
4829 }
4830 }
4831 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4832
4833 /* FLR may cause some 82579 devices to hang. */
4834 static void quirk_intel_no_flr(struct pci_dev *dev)
4835 {
4836 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4837 }
4838 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4839 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4840
4841 static void quirk_intel_th_rtit_bar(struct pci_dev *dev)
4842 {
4843 struct resource *r = &dev->resource[4];
4844
4845 /*
4846 * Hello, Denverton!
4847 * Denverton reports 2k of RTIT_BAR (resource 4), which can't be
4848 * right given the 16 threads. When Intel TH gets enabled, the
4849 * actual resource overlaps the XHCI MMIO space and causes it
4850 * to die.
4851 * We're not really using RTIT_BAR at all at the moment, so it's
4852 * a safe choice to disable this resource.
4853 */
4854 if (r->end == r->start + 0x7ff) {
4855 r->flags = 0;
4856 r->start = 0;
4857 r->end = 0;
4858 }
4859 }
4860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_rtit_bar);
4861
4862 static void quirk_no_ext_tags(struct pci_dev *pdev)
4863 {
4864 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4865
4866 if (!bridge)
4867 return;
4868
4869 bridge->no_ext_tags = 1;
4870 dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n");
4871
4872 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4873 }
4874 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
4875 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
4876 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
4877 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
4878 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
4879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
4880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
4881
4882 #ifdef CONFIG_PCI_ATS
4883 /*
4884 * Some devices have a broken ATS implementation causing IOMMU stalls.
4885 * Don't use ATS for those devices.
4886 */
4887 static void quirk_no_ats(struct pci_dev *pdev)
4888 {
4889 dev_info(&pdev->dev, "disabling ATS (broken on this device)\n");
4890 pdev->ats_cap = 0;
4891 }
4892
4893 /* AMD Stoney platform GPU */
4894 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
4895 #endif /* CONFIG_PCI_ATS */
4896
4897 /* Freescale PCIe doesn't support MSI in RC mode */
4898 static void quirk_fsl_no_msi(struct pci_dev *pdev)
4899 {
4900 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
4901 pdev->no_msi = 1;
4902 }
4903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
ubuntu-bionic-kernel mirror