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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / arcmsr / arcmsr_hba.c
1 /*
2 *******************************************************************************
3 ** O.S : Linux
4 ** FILE NAME : arcmsr_hba.c
5 ** BY : Nick Cheng, C.L. Huang
6 ** Description: SCSI RAID Device Driver for Areca RAID Controller
7 *******************************************************************************
8 ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
9 **
10 ** Web site: www.areca.com.tw
11 ** E-mail: support@areca.com.tw
12 **
13 ** This program is free software; you can redistribute it and/or modify
14 ** it under the terms of the GNU General Public License version 2 as
15 ** published by the Free Software Foundation.
16 ** This program is distributed in the hope that it will be useful,
17 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ** GNU General Public License for more details.
20 *******************************************************************************
21 ** Redistribution and use in source and binary forms, with or without
22 ** modification, are permitted provided that the following conditions
23 ** are met:
24 ** 1. Redistributions of source code must retain the above copyright
25 ** notice, this list of conditions and the following disclaimer.
26 ** 2. Redistributions in binary form must reproduce the above copyright
27 ** notice, this list of conditions and the following disclaimer in the
28 ** documentation and/or other materials provided with the distribution.
29 ** 3. The name of the author may not be used to endorse or promote products
30 ** derived from this software without specific prior written permission.
31 **
32 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
37 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
39 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
41 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *******************************************************************************
43 ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
44 ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
45 *******************************************************************************
46 */
47 #include <linux/module.h>
48 #include <linux/reboot.h>
49 #include <linux/spinlock.h>
50 #include <linux/pci_ids.h>
51 #include <linux/interrupt.h>
52 #include <linux/moduleparam.h>
53 #include <linux/errno.h>
54 #include <linux/types.h>
55 #include <linux/delay.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/timer.h>
58 #include <linux/slab.h>
59 #include <linux/pci.h>
60 #include <linux/aer.h>
61 #include <linux/circ_buf.h>
62 #include <asm/dma.h>
63 #include <asm/io.h>
64 #include <linux/uaccess.h>
65 #include <scsi/scsi_host.h>
66 #include <scsi/scsi.h>
67 #include <scsi/scsi_cmnd.h>
68 #include <scsi/scsi_tcq.h>
69 #include <scsi/scsi_device.h>
70 #include <scsi/scsi_transport.h>
71 #include <scsi/scsicam.h>
72 #include "arcmsr.h"
73 MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
74 MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
75 MODULE_LICENSE("Dual BSD/GPL");
76 MODULE_VERSION(ARCMSR_DRIVER_VERSION);
77
78 #define ARCMSR_SLEEPTIME 10
79 #define ARCMSR_RETRYCOUNT 12
80
81 static wait_queue_head_t wait_q;
82 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
83 struct scsi_cmnd *cmd);
84 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
85 static int arcmsr_abort(struct scsi_cmnd *);
86 static int arcmsr_bus_reset(struct scsi_cmnd *);
87 static int arcmsr_bios_param(struct scsi_device *sdev,
88 struct block_device *bdev, sector_t capacity, int *info);
89 static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
90 static int arcmsr_probe(struct pci_dev *pdev,
91 const struct pci_device_id *id);
92 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
93 static int arcmsr_resume(struct pci_dev *pdev);
94 static void arcmsr_remove(struct pci_dev *pdev);
95 static void arcmsr_shutdown(struct pci_dev *pdev);
96 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
97 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
98 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
99 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
100 u32 intmask_org);
101 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
102 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
103 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
104 static void arcmsr_request_device_map(unsigned long pacb);
105 static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb);
106 static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb);
107 static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb);
108 static void arcmsr_message_isr_bh_fn(struct work_struct *work);
109 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
110 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
111 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
112 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
113 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
114 static const char *arcmsr_info(struct Scsi_Host *);
115 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
116 static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
117 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
118 static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
119 {
120 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
121 queue_depth = ARCMSR_MAX_CMD_PERLUN;
122 return scsi_change_queue_depth(sdev, queue_depth);
123 }
124
125 static struct scsi_host_template arcmsr_scsi_host_template = {
126 .module = THIS_MODULE,
127 .name = "Areca SAS/SATA RAID driver",
128 .info = arcmsr_info,
129 .queuecommand = arcmsr_queue_command,
130 .eh_abort_handler = arcmsr_abort,
131 .eh_bus_reset_handler = arcmsr_bus_reset,
132 .bios_param = arcmsr_bios_param,
133 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
134 .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
135 .this_id = ARCMSR_SCSI_INITIATOR_ID,
136 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
137 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
138 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
139 .use_clustering = ENABLE_CLUSTERING,
140 .shost_attrs = arcmsr_host_attrs,
141 .no_write_same = 1,
142 };
143
144 static struct pci_device_id arcmsr_device_id_table[] = {
145 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
146 .driver_data = ACB_ADAPTER_TYPE_A},
147 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
148 .driver_data = ACB_ADAPTER_TYPE_A},
149 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
150 .driver_data = ACB_ADAPTER_TYPE_A},
151 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
152 .driver_data = ACB_ADAPTER_TYPE_A},
153 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
154 .driver_data = ACB_ADAPTER_TYPE_A},
155 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
156 .driver_data = ACB_ADAPTER_TYPE_B},
157 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
158 .driver_data = ACB_ADAPTER_TYPE_B},
159 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
160 .driver_data = ACB_ADAPTER_TYPE_B},
161 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
162 .driver_data = ACB_ADAPTER_TYPE_B},
163 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
164 .driver_data = ACB_ADAPTER_TYPE_A},
165 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
166 .driver_data = ACB_ADAPTER_TYPE_D},
167 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
168 .driver_data = ACB_ADAPTER_TYPE_A},
169 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
170 .driver_data = ACB_ADAPTER_TYPE_A},
171 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
172 .driver_data = ACB_ADAPTER_TYPE_A},
173 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
174 .driver_data = ACB_ADAPTER_TYPE_A},
175 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
176 .driver_data = ACB_ADAPTER_TYPE_A},
177 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
178 .driver_data = ACB_ADAPTER_TYPE_A},
179 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
180 .driver_data = ACB_ADAPTER_TYPE_A},
181 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
182 .driver_data = ACB_ADAPTER_TYPE_A},
183 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
184 .driver_data = ACB_ADAPTER_TYPE_A},
185 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
186 .driver_data = ACB_ADAPTER_TYPE_C},
187 {0, 0}, /* Terminating entry */
188 };
189 MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
190
191 static struct pci_driver arcmsr_pci_driver = {
192 .name = "arcmsr",
193 .id_table = arcmsr_device_id_table,
194 .probe = arcmsr_probe,
195 .remove = arcmsr_remove,
196 .suspend = arcmsr_suspend,
197 .resume = arcmsr_resume,
198 .shutdown = arcmsr_shutdown,
199 };
200 /*
201 ****************************************************************************
202 ****************************************************************************
203 */
204
205 static void arcmsr_free_mu(struct AdapterControlBlock *acb)
206 {
207 switch (acb->adapter_type) {
208 case ACB_ADAPTER_TYPE_B:
209 case ACB_ADAPTER_TYPE_D: {
210 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
211 acb->dma_coherent2, acb->dma_coherent_handle2);
212 break;
213 }
214 }
215 }
216
217 static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
218 {
219 struct pci_dev *pdev = acb->pdev;
220 switch (acb->adapter_type){
221 case ACB_ADAPTER_TYPE_A:{
222 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
223 if (!acb->pmuA) {
224 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
225 return false;
226 }
227 break;
228 }
229 case ACB_ADAPTER_TYPE_B:{
230 void __iomem *mem_base0, *mem_base1;
231 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
232 if (!mem_base0) {
233 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
234 return false;
235 }
236 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
237 if (!mem_base1) {
238 iounmap(mem_base0);
239 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
240 return false;
241 }
242 acb->mem_base0 = mem_base0;
243 acb->mem_base1 = mem_base1;
244 break;
245 }
246 case ACB_ADAPTER_TYPE_C:{
247 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
248 if (!acb->pmuC) {
249 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
250 return false;
251 }
252 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
253 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
254 return true;
255 }
256 break;
257 }
258 case ACB_ADAPTER_TYPE_D: {
259 void __iomem *mem_base0;
260 unsigned long addr, range, flags;
261
262 addr = (unsigned long)pci_resource_start(pdev, 0);
263 range = pci_resource_len(pdev, 0);
264 flags = pci_resource_flags(pdev, 0);
265 mem_base0 = ioremap(addr, range);
266 if (!mem_base0) {
267 pr_notice("arcmsr%d: memory mapping region fail\n",
268 acb->host->host_no);
269 return false;
270 }
271 acb->mem_base0 = mem_base0;
272 break;
273 }
274 }
275 return true;
276 }
277
278 static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
279 {
280 switch (acb->adapter_type) {
281 case ACB_ADAPTER_TYPE_A:{
282 iounmap(acb->pmuA);
283 }
284 break;
285 case ACB_ADAPTER_TYPE_B:{
286 iounmap(acb->mem_base0);
287 iounmap(acb->mem_base1);
288 }
289
290 break;
291 case ACB_ADAPTER_TYPE_C:{
292 iounmap(acb->pmuC);
293 }
294 break;
295 case ACB_ADAPTER_TYPE_D:
296 iounmap(acb->mem_base0);
297 break;
298 }
299 }
300
301 static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
302 {
303 irqreturn_t handle_state;
304 struct AdapterControlBlock *acb = dev_id;
305
306 handle_state = arcmsr_interrupt(acb);
307 return handle_state;
308 }
309
310 static int arcmsr_bios_param(struct scsi_device *sdev,
311 struct block_device *bdev, sector_t capacity, int *geom)
312 {
313 int ret, heads, sectors, cylinders, total_capacity;
314 unsigned char *buffer;/* return copy of block device's partition table */
315
316 buffer = scsi_bios_ptable(bdev);
317 if (buffer) {
318 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
319 kfree(buffer);
320 if (ret != -1)
321 return ret;
322 }
323 total_capacity = capacity;
324 heads = 64;
325 sectors = 32;
326 cylinders = total_capacity / (heads * sectors);
327 if (cylinders > 1024) {
328 heads = 255;
329 sectors = 63;
330 cylinders = total_capacity / (heads * sectors);
331 }
332 geom[0] = heads;
333 geom[1] = sectors;
334 geom[2] = cylinders;
335 return 0;
336 }
337
338 static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
339 {
340 struct MessageUnit_A __iomem *reg = acb->pmuA;
341 int i;
342
343 for (i = 0; i < 2000; i++) {
344 if (readl(&reg->outbound_intstatus) &
345 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
346 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
347 &reg->outbound_intstatus);
348 return true;
349 }
350 msleep(10);
351 } /* max 20 seconds */
352
353 return false;
354 }
355
356 static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
357 {
358 struct MessageUnit_B *reg = acb->pmuB;
359 int i;
360
361 for (i = 0; i < 2000; i++) {
362 if (readl(reg->iop2drv_doorbell)
363 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
364 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
365 reg->iop2drv_doorbell);
366 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
367 reg->drv2iop_doorbell);
368 return true;
369 }
370 msleep(10);
371 } /* max 20 seconds */
372
373 return false;
374 }
375
376 static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
377 {
378 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
379 int i;
380
381 for (i = 0; i < 2000; i++) {
382 if (readl(&phbcmu->outbound_doorbell)
383 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
384 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
385 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
386 return true;
387 }
388 msleep(10);
389 } /* max 20 seconds */
390
391 return false;
392 }
393
394 static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
395 {
396 struct MessageUnit_D *reg = pACB->pmuD;
397 int i;
398
399 for (i = 0; i < 2000; i++) {
400 if (readl(reg->outbound_doorbell)
401 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
402 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
403 reg->outbound_doorbell);
404 return true;
405 }
406 msleep(10);
407 } /* max 20 seconds */
408 return false;
409 }
410
411 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
412 {
413 struct MessageUnit_A __iomem *reg = acb->pmuA;
414 int retry_count = 30;
415 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
416 do {
417 if (arcmsr_hbaA_wait_msgint_ready(acb))
418 break;
419 else {
420 retry_count--;
421 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
422 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
423 }
424 } while (retry_count != 0);
425 }
426
427 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
428 {
429 struct MessageUnit_B *reg = acb->pmuB;
430 int retry_count = 30;
431 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
432 do {
433 if (arcmsr_hbaB_wait_msgint_ready(acb))
434 break;
435 else {
436 retry_count--;
437 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
438 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
439 }
440 } while (retry_count != 0);
441 }
442
443 static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
444 {
445 struct MessageUnit_C __iomem *reg = pACB->pmuC;
446 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
447 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
448 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
449 do {
450 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
451 break;
452 } else {
453 retry_count--;
454 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
455 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
456 }
457 } while (retry_count != 0);
458 return;
459 }
460
461 static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
462 {
463 int retry_count = 15;
464 struct MessageUnit_D *reg = pACB->pmuD;
465
466 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
467 do {
468 if (arcmsr_hbaD_wait_msgint_ready(pACB))
469 break;
470
471 retry_count--;
472 pr_notice("arcmsr%d: wait 'flush adapter "
473 "cache' timeout, retry count down = %d\n",
474 pACB->host->host_no, retry_count);
475 } while (retry_count != 0);
476 }
477
478 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
479 {
480 switch (acb->adapter_type) {
481
482 case ACB_ADAPTER_TYPE_A: {
483 arcmsr_hbaA_flush_cache(acb);
484 }
485 break;
486
487 case ACB_ADAPTER_TYPE_B: {
488 arcmsr_hbaB_flush_cache(acb);
489 }
490 break;
491 case ACB_ADAPTER_TYPE_C: {
492 arcmsr_hbaC_flush_cache(acb);
493 }
494 break;
495 case ACB_ADAPTER_TYPE_D:
496 arcmsr_hbaD_flush_cache(acb);
497 break;
498 }
499 }
500
501 static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
502 {
503 bool rtn = true;
504 void *dma_coherent;
505 dma_addr_t dma_coherent_handle;
506 struct pci_dev *pdev = acb->pdev;
507
508 switch (acb->adapter_type) {
509 case ACB_ADAPTER_TYPE_B: {
510 struct MessageUnit_B *reg;
511 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
512 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
513 &dma_coherent_handle, GFP_KERNEL);
514 if (!dma_coherent) {
515 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
516 return false;
517 }
518 acb->dma_coherent_handle2 = dma_coherent_handle;
519 acb->dma_coherent2 = dma_coherent;
520 reg = (struct MessageUnit_B *)dma_coherent;
521 acb->pmuB = reg;
522 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
523 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
524 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
525 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
526 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
527 } else {
528 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
529 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
530 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
531 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
532 }
533 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
534 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
535 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
536 }
537 break;
538 case ACB_ADAPTER_TYPE_D: {
539 struct MessageUnit_D *reg;
540
541 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
542 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
543 &dma_coherent_handle, GFP_KERNEL);
544 if (!dma_coherent) {
545 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
546 return false;
547 }
548 acb->dma_coherent_handle2 = dma_coherent_handle;
549 acb->dma_coherent2 = dma_coherent;
550 reg = (struct MessageUnit_D *)dma_coherent;
551 acb->pmuD = reg;
552 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
553 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
554 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
555 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
556 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
557 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
558 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
559 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
560 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
561 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
562 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
563 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
564 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
565 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
566 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
567 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
568 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
569 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
570 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
571 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
572 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
573 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
574 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
575 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
576 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
577 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
578 }
579 break;
580 default:
581 break;
582 }
583 return rtn;
584 }
585
586 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
587 {
588 struct pci_dev *pdev = acb->pdev;
589 void *dma_coherent;
590 dma_addr_t dma_coherent_handle;
591 struct CommandControlBlock *ccb_tmp;
592 int i = 0, j = 0;
593 dma_addr_t cdb_phyaddr;
594 unsigned long roundup_ccbsize;
595 unsigned long max_xfer_len;
596 unsigned long max_sg_entrys;
597 uint32_t firm_config_version;
598
599 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
600 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
601 acb->devstate[i][j] = ARECA_RAID_GONE;
602
603 max_xfer_len = ARCMSR_MAX_XFER_LEN;
604 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
605 firm_config_version = acb->firm_cfg_version;
606 if((firm_config_version & 0xFF) >= 3){
607 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
608 max_sg_entrys = (max_xfer_len/4096);
609 }
610 acb->host->max_sectors = max_xfer_len/512;
611 acb->host->sg_tablesize = max_sg_entrys;
612 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
613 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
614 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
615 if(!dma_coherent){
616 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
617 return -ENOMEM;
618 }
619 acb->dma_coherent = dma_coherent;
620 acb->dma_coherent_handle = dma_coherent_handle;
621 memset(dma_coherent, 0, acb->uncache_size);
622 ccb_tmp = dma_coherent;
623 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
624 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
625 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
626 switch (acb->adapter_type) {
627 case ACB_ADAPTER_TYPE_A:
628 case ACB_ADAPTER_TYPE_B:
629 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
630 break;
631 case ACB_ADAPTER_TYPE_C:
632 case ACB_ADAPTER_TYPE_D:
633 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
634 break;
635 }
636 acb->pccb_pool[i] = ccb_tmp;
637 ccb_tmp->acb = acb;
638 INIT_LIST_HEAD(&ccb_tmp->list);
639 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
640 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
641 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
642 }
643 return 0;
644 }
645
646 static void arcmsr_message_isr_bh_fn(struct work_struct *work)
647 {
648 struct AdapterControlBlock *acb = container_of(work,
649 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
650 char *acb_dev_map = (char *)acb->device_map;
651 uint32_t __iomem *signature = NULL;
652 char __iomem *devicemap = NULL;
653 int target, lun;
654 struct scsi_device *psdev;
655 char diff, temp;
656
657 switch (acb->adapter_type) {
658 case ACB_ADAPTER_TYPE_A: {
659 struct MessageUnit_A __iomem *reg = acb->pmuA;
660
661 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
662 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
663 break;
664 }
665 case ACB_ADAPTER_TYPE_B: {
666 struct MessageUnit_B *reg = acb->pmuB;
667
668 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
669 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
670 break;
671 }
672 case ACB_ADAPTER_TYPE_C: {
673 struct MessageUnit_C __iomem *reg = acb->pmuC;
674
675 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
676 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
677 break;
678 }
679 case ACB_ADAPTER_TYPE_D: {
680 struct MessageUnit_D *reg = acb->pmuD;
681
682 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
683 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
684 break;
685 }
686 }
687 atomic_inc(&acb->rq_map_token);
688 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
689 return;
690 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
691 target++) {
692 temp = readb(devicemap);
693 diff = (*acb_dev_map) ^ temp;
694 if (diff != 0) {
695 *acb_dev_map = temp;
696 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
697 lun++) {
698 if ((diff & 0x01) == 1 &&
699 (temp & 0x01) == 1) {
700 scsi_add_device(acb->host,
701 0, target, lun);
702 } else if ((diff & 0x01) == 1
703 && (temp & 0x01) == 0) {
704 psdev = scsi_device_lookup(acb->host,
705 0, target, lun);
706 if (psdev != NULL) {
707 scsi_remove_device(psdev);
708 scsi_device_put(psdev);
709 }
710 }
711 temp >>= 1;
712 diff >>= 1;
713 }
714 }
715 devicemap++;
716 acb_dev_map++;
717 }
718 }
719
720 static int
721 arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
722 {
723 unsigned long flags;
724 int nvec, i;
725
726 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
727 PCI_IRQ_MSIX);
728 if (nvec > 0) {
729 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
730 flags = 0;
731 } else {
732 nvec = pci_alloc_irq_vectors(pdev, 1, 1,
733 PCI_IRQ_MSI | PCI_IRQ_LEGACY);
734 if (nvec < 1)
735 return FAILED;
736
737 flags = IRQF_SHARED;
738 }
739
740 acb->vector_count = nvec;
741 for (i = 0; i < nvec; i++) {
742 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
743 flags, "arcmsr", acb)) {
744 pr_warn("arcmsr%d: request_irq =%d failed!\n",
745 acb->host->host_no, pci_irq_vector(pdev, i));
746 goto out_free_irq;
747 }
748 }
749
750 return SUCCESS;
751 out_free_irq:
752 while (--i >= 0)
753 free_irq(pci_irq_vector(pdev, i), acb);
754 pci_free_irq_vectors(pdev);
755 return FAILED;
756 }
757
758 static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
759 {
760 struct Scsi_Host *host;
761 struct AdapterControlBlock *acb;
762 uint8_t bus,dev_fun;
763 int error;
764 error = pci_enable_device(pdev);
765 if(error){
766 return -ENODEV;
767 }
768 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
769 if(!host){
770 goto pci_disable_dev;
771 }
772 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
773 if(error){
774 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
775 if(error){
776 printk(KERN_WARNING
777 "scsi%d: No suitable DMA mask available\n",
778 host->host_no);
779 goto scsi_host_release;
780 }
781 }
782 init_waitqueue_head(&wait_q);
783 bus = pdev->bus->number;
784 dev_fun = pdev->devfn;
785 acb = (struct AdapterControlBlock *) host->hostdata;
786 memset(acb,0,sizeof(struct AdapterControlBlock));
787 acb->pdev = pdev;
788 acb->host = host;
789 host->max_lun = ARCMSR_MAX_TARGETLUN;
790 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
791 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
792 host->can_queue = ARCMSR_MAX_OUTSTANDING_CMD;
793 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
794 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
795 host->unique_id = (bus << 8) | dev_fun;
796 pci_set_drvdata(pdev, host);
797 pci_set_master(pdev);
798 error = pci_request_regions(pdev, "arcmsr");
799 if(error){
800 goto scsi_host_release;
801 }
802 spin_lock_init(&acb->eh_lock);
803 spin_lock_init(&acb->ccblist_lock);
804 spin_lock_init(&acb->postq_lock);
805 spin_lock_init(&acb->doneq_lock);
806 spin_lock_init(&acb->rqbuffer_lock);
807 spin_lock_init(&acb->wqbuffer_lock);
808 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
809 ACB_F_MESSAGE_RQBUFFER_CLEARED |
810 ACB_F_MESSAGE_WQBUFFER_READED);
811 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
812 INIT_LIST_HEAD(&acb->ccb_free_list);
813 acb->adapter_type = id->driver_data;
814 error = arcmsr_remap_pciregion(acb);
815 if(!error){
816 goto pci_release_regs;
817 }
818 error = arcmsr_alloc_io_queue(acb);
819 if (!error)
820 goto unmap_pci_region;
821 error = arcmsr_get_firmware_spec(acb);
822 if(!error){
823 goto free_hbb_mu;
824 }
825 error = arcmsr_alloc_ccb_pool(acb);
826 if(error){
827 goto free_hbb_mu;
828 }
829 error = scsi_add_host(host, &pdev->dev);
830 if(error){
831 goto free_ccb_pool;
832 }
833 if (arcmsr_request_irq(pdev, acb) == FAILED)
834 goto scsi_host_remove;
835 arcmsr_iop_init(acb);
836 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
837 atomic_set(&acb->rq_map_token, 16);
838 atomic_set(&acb->ante_token_value, 16);
839 acb->fw_flag = FW_NORMAL;
840 setup_timer(&acb->eternal_timer, &arcmsr_request_device_map,
841 (unsigned long)acb);
842 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
843 add_timer(&acb->eternal_timer);
844 if(arcmsr_alloc_sysfs_attr(acb))
845 goto out_free_sysfs;
846 scsi_scan_host(host);
847 return 0;
848 out_free_sysfs:
849 del_timer_sync(&acb->eternal_timer);
850 flush_work(&acb->arcmsr_do_message_isr_bh);
851 arcmsr_stop_adapter_bgrb(acb);
852 arcmsr_flush_adapter_cache(acb);
853 arcmsr_free_irq(pdev, acb);
854 scsi_host_remove:
855 scsi_remove_host(host);
856 free_ccb_pool:
857 arcmsr_free_ccb_pool(acb);
858 free_hbb_mu:
859 arcmsr_free_mu(acb);
860 unmap_pci_region:
861 arcmsr_unmap_pciregion(acb);
862 pci_release_regs:
863 pci_release_regions(pdev);
864 scsi_host_release:
865 scsi_host_put(host);
866 pci_disable_dev:
867 pci_disable_device(pdev);
868 return -ENODEV;
869 }
870
871 static void arcmsr_free_irq(struct pci_dev *pdev,
872 struct AdapterControlBlock *acb)
873 {
874 int i;
875
876 for (i = 0; i < acb->vector_count; i++)
877 free_irq(pci_irq_vector(pdev, i), acb);
878 pci_free_irq_vectors(pdev);
879 }
880
881 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
882 {
883 uint32_t intmask_org;
884 struct Scsi_Host *host = pci_get_drvdata(pdev);
885 struct AdapterControlBlock *acb =
886 (struct AdapterControlBlock *)host->hostdata;
887
888 intmask_org = arcmsr_disable_outbound_ints(acb);
889 arcmsr_free_irq(pdev, acb);
890 del_timer_sync(&acb->eternal_timer);
891 flush_work(&acb->arcmsr_do_message_isr_bh);
892 arcmsr_stop_adapter_bgrb(acb);
893 arcmsr_flush_adapter_cache(acb);
894 pci_set_drvdata(pdev, host);
895 pci_save_state(pdev);
896 pci_disable_device(pdev);
897 pci_set_power_state(pdev, pci_choose_state(pdev, state));
898 return 0;
899 }
900
901 static int arcmsr_resume(struct pci_dev *pdev)
902 {
903 int error;
904 struct Scsi_Host *host = pci_get_drvdata(pdev);
905 struct AdapterControlBlock *acb =
906 (struct AdapterControlBlock *)host->hostdata;
907
908 pci_set_power_state(pdev, PCI_D0);
909 pci_enable_wake(pdev, PCI_D0, 0);
910 pci_restore_state(pdev);
911 if (pci_enable_device(pdev)) {
912 pr_warn("%s: pci_enable_device error\n", __func__);
913 return -ENODEV;
914 }
915 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
916 if (error) {
917 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
918 if (error) {
919 pr_warn("scsi%d: No suitable DMA mask available\n",
920 host->host_no);
921 goto controller_unregister;
922 }
923 }
924 pci_set_master(pdev);
925 if (arcmsr_request_irq(pdev, acb) == FAILED)
926 goto controller_stop;
927 arcmsr_iop_init(acb);
928 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
929 atomic_set(&acb->rq_map_token, 16);
930 atomic_set(&acb->ante_token_value, 16);
931 acb->fw_flag = FW_NORMAL;
932 setup_timer(&acb->eternal_timer, &arcmsr_request_device_map,
933 (unsigned long)acb);
934 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
935 add_timer(&acb->eternal_timer);
936 return 0;
937 controller_stop:
938 arcmsr_stop_adapter_bgrb(acb);
939 arcmsr_flush_adapter_cache(acb);
940 controller_unregister:
941 scsi_remove_host(host);
942 arcmsr_free_ccb_pool(acb);
943 arcmsr_unmap_pciregion(acb);
944 pci_release_regions(pdev);
945 scsi_host_put(host);
946 pci_disable_device(pdev);
947 return -ENODEV;
948 }
949
950 static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
951 {
952 struct MessageUnit_A __iomem *reg = acb->pmuA;
953 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
954 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
955 printk(KERN_NOTICE
956 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
957 , acb->host->host_no);
958 return false;
959 }
960 return true;
961 }
962
963 static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
964 {
965 struct MessageUnit_B *reg = acb->pmuB;
966
967 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
968 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
969 printk(KERN_NOTICE
970 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
971 , acb->host->host_no);
972 return false;
973 }
974 return true;
975 }
976 static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
977 {
978 struct MessageUnit_C __iomem *reg = pACB->pmuC;
979 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
980 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
981 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
982 printk(KERN_NOTICE
983 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
984 , pACB->host->host_no);
985 return false;
986 }
987 return true;
988 }
989
990 static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
991 {
992 struct MessageUnit_D *reg = pACB->pmuD;
993
994 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
995 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
996 pr_notice("arcmsr%d: wait 'abort all outstanding "
997 "command' timeout\n", pACB->host->host_no);
998 return false;
999 }
1000 return true;
1001 }
1002
1003 static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1004 {
1005 uint8_t rtnval = 0;
1006 switch (acb->adapter_type) {
1007 case ACB_ADAPTER_TYPE_A: {
1008 rtnval = arcmsr_hbaA_abort_allcmd(acb);
1009 }
1010 break;
1011
1012 case ACB_ADAPTER_TYPE_B: {
1013 rtnval = arcmsr_hbaB_abort_allcmd(acb);
1014 }
1015 break;
1016
1017 case ACB_ADAPTER_TYPE_C: {
1018 rtnval = arcmsr_hbaC_abort_allcmd(acb);
1019 }
1020 break;
1021
1022 case ACB_ADAPTER_TYPE_D:
1023 rtnval = arcmsr_hbaD_abort_allcmd(acb);
1024 break;
1025 }
1026 return rtnval;
1027 }
1028
1029 static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
1030 {
1031 struct scsi_cmnd *pcmd = ccb->pcmd;
1032
1033 scsi_dma_unmap(pcmd);
1034 }
1035
1036 static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1037 {
1038 struct AdapterControlBlock *acb = ccb->acb;
1039 struct scsi_cmnd *pcmd = ccb->pcmd;
1040 unsigned long flags;
1041 atomic_dec(&acb->ccboutstandingcount);
1042 arcmsr_pci_unmap_dma(ccb);
1043 ccb->startdone = ARCMSR_CCB_DONE;
1044 spin_lock_irqsave(&acb->ccblist_lock, flags);
1045 list_add_tail(&ccb->list, &acb->ccb_free_list);
1046 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1047 pcmd->scsi_done(pcmd);
1048 }
1049
1050 static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
1051 {
1052
1053 struct scsi_cmnd *pcmd = ccb->pcmd;
1054 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1055 pcmd->result = DID_OK << 16;
1056 if (sensebuffer) {
1057 int sense_data_length =
1058 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
1059 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
1060 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1061 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
1062 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1063 sensebuffer->Valid = 1;
1064 }
1065 }
1066
1067 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
1068 {
1069 u32 orig_mask = 0;
1070 switch (acb->adapter_type) {
1071 case ACB_ADAPTER_TYPE_A : {
1072 struct MessageUnit_A __iomem *reg = acb->pmuA;
1073 orig_mask = readl(&reg->outbound_intmask);
1074 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1075 &reg->outbound_intmask);
1076 }
1077 break;
1078 case ACB_ADAPTER_TYPE_B : {
1079 struct MessageUnit_B *reg = acb->pmuB;
1080 orig_mask = readl(reg->iop2drv_doorbell_mask);
1081 writel(0, reg->iop2drv_doorbell_mask);
1082 }
1083 break;
1084 case ACB_ADAPTER_TYPE_C:{
1085 struct MessageUnit_C __iomem *reg = acb->pmuC;
1086 /* disable all outbound interrupt */
1087 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
1088 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
1089 }
1090 break;
1091 case ACB_ADAPTER_TYPE_D: {
1092 struct MessageUnit_D *reg = acb->pmuD;
1093 /* disable all outbound interrupt */
1094 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1095 }
1096 break;
1097 }
1098 return orig_mask;
1099 }
1100
1101 static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1102 struct CommandControlBlock *ccb, bool error)
1103 {
1104 uint8_t id, lun;
1105 id = ccb->pcmd->device->id;
1106 lun = ccb->pcmd->device->lun;
1107 if (!error) {
1108 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1109 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1110 ccb->pcmd->result = DID_OK << 16;
1111 arcmsr_ccb_complete(ccb);
1112 }else{
1113 switch (ccb->arcmsr_cdb.DeviceStatus) {
1114 case ARCMSR_DEV_SELECT_TIMEOUT: {
1115 acb->devstate[id][lun] = ARECA_RAID_GONE;
1116 ccb->pcmd->result = DID_NO_CONNECT << 16;
1117 arcmsr_ccb_complete(ccb);
1118 }
1119 break;
1120
1121 case ARCMSR_DEV_ABORTED:
1122
1123 case ARCMSR_DEV_INIT_FAIL: {
1124 acb->devstate[id][lun] = ARECA_RAID_GONE;
1125 ccb->pcmd->result = DID_BAD_TARGET << 16;
1126 arcmsr_ccb_complete(ccb);
1127 }
1128 break;
1129
1130 case ARCMSR_DEV_CHECK_CONDITION: {
1131 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1132 arcmsr_report_sense_info(ccb);
1133 arcmsr_ccb_complete(ccb);
1134 }
1135 break;
1136
1137 default:
1138 printk(KERN_NOTICE
1139 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1140 but got unknown DeviceStatus = 0x%x \n"
1141 , acb->host->host_no
1142 , id
1143 , lun
1144 , ccb->arcmsr_cdb.DeviceStatus);
1145 acb->devstate[id][lun] = ARECA_RAID_GONE;
1146 ccb->pcmd->result = DID_NO_CONNECT << 16;
1147 arcmsr_ccb_complete(ccb);
1148 break;
1149 }
1150 }
1151 }
1152
1153 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1154 {
1155 int id, lun;
1156 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1157 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1158 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1159 if (abortcmd) {
1160 id = abortcmd->device->id;
1161 lun = abortcmd->device->lun;
1162 abortcmd->result |= DID_ABORT << 16;
1163 arcmsr_ccb_complete(pCCB);
1164 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1165 acb->host->host_no, pCCB);
1166 }
1167 return;
1168 }
1169 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1170 done acb = '0x%p'"
1171 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1172 " ccboutstandingcount = %d \n"
1173 , acb->host->host_no
1174 , acb
1175 , pCCB
1176 , pCCB->acb
1177 , pCCB->startdone
1178 , atomic_read(&acb->ccboutstandingcount));
1179 return;
1180 }
1181 arcmsr_report_ccb_state(acb, pCCB, error);
1182 }
1183
1184 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1185 {
1186 int i = 0;
1187 uint32_t flag_ccb, ccb_cdb_phy;
1188 struct ARCMSR_CDB *pARCMSR_CDB;
1189 bool error;
1190 struct CommandControlBlock *pCCB;
1191 switch (acb->adapter_type) {
1192
1193 case ACB_ADAPTER_TYPE_A: {
1194 struct MessageUnit_A __iomem *reg = acb->pmuA;
1195 uint32_t outbound_intstatus;
1196 outbound_intstatus = readl(&reg->outbound_intstatus) &
1197 acb->outbound_int_enable;
1198 /*clear and abort all outbound posted Q*/
1199 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
1200 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1201 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1202 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1203 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1204 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1205 arcmsr_drain_donequeue(acb, pCCB, error);
1206 }
1207 }
1208 break;
1209
1210 case ACB_ADAPTER_TYPE_B: {
1211 struct MessageUnit_B *reg = acb->pmuB;
1212 /*clear all outbound posted Q*/
1213 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1214 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1215 flag_ccb = reg->done_qbuffer[i];
1216 if (flag_ccb != 0) {
1217 reg->done_qbuffer[i] = 0;
1218 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1219 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1220 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1221 arcmsr_drain_donequeue(acb, pCCB, error);
1222 }
1223 reg->post_qbuffer[i] = 0;
1224 }
1225 reg->doneq_index = 0;
1226 reg->postq_index = 0;
1227 }
1228 break;
1229 case ACB_ADAPTER_TYPE_C: {
1230 struct MessageUnit_C __iomem *reg = acb->pmuC;
1231 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1232 /*need to do*/
1233 flag_ccb = readl(&reg->outbound_queueport_low);
1234 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1235 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
1236 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1237 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1238 arcmsr_drain_donequeue(acb, pCCB, error);
1239 }
1240 }
1241 break;
1242 case ACB_ADAPTER_TYPE_D: {
1243 struct MessageUnit_D *pmu = acb->pmuD;
1244 uint32_t outbound_write_pointer;
1245 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1246 unsigned long flags;
1247
1248 residual = atomic_read(&acb->ccboutstandingcount);
1249 for (i = 0; i < residual; i++) {
1250 spin_lock_irqsave(&acb->doneq_lock, flags);
1251 outbound_write_pointer =
1252 pmu->done_qbuffer[0].addressLow + 1;
1253 doneq_index = pmu->doneq_index;
1254 if ((doneq_index & 0xFFF) !=
1255 (outbound_write_pointer & 0xFFF)) {
1256 toggle = doneq_index & 0x4000;
1257 index_stripped = (doneq_index & 0xFFF) + 1;
1258 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1259 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1260 ((toggle ^ 0x4000) + 1);
1261 doneq_index = pmu->doneq_index;
1262 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1263 addressLow = pmu->done_qbuffer[doneq_index &
1264 0xFFF].addressLow;
1265 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1266 pARCMSR_CDB = (struct ARCMSR_CDB *)
1267 (acb->vir2phy_offset + ccb_cdb_phy);
1268 pCCB = container_of(pARCMSR_CDB,
1269 struct CommandControlBlock, arcmsr_cdb);
1270 error = (addressLow &
1271 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1272 true : false;
1273 arcmsr_drain_donequeue(acb, pCCB, error);
1274 writel(doneq_index,
1275 pmu->outboundlist_read_pointer);
1276 } else {
1277 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1278 mdelay(10);
1279 }
1280 }
1281 pmu->postq_index = 0;
1282 pmu->doneq_index = 0x40FF;
1283 }
1284 break;
1285 }
1286 }
1287
1288 static void arcmsr_remove(struct pci_dev *pdev)
1289 {
1290 struct Scsi_Host *host = pci_get_drvdata(pdev);
1291 struct AdapterControlBlock *acb =
1292 (struct AdapterControlBlock *) host->hostdata;
1293 int poll_count = 0;
1294 arcmsr_free_sysfs_attr(acb);
1295 scsi_remove_host(host);
1296 flush_work(&acb->arcmsr_do_message_isr_bh);
1297 del_timer_sync(&acb->eternal_timer);
1298 arcmsr_disable_outbound_ints(acb);
1299 arcmsr_stop_adapter_bgrb(acb);
1300 arcmsr_flush_adapter_cache(acb);
1301 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1302 acb->acb_flags &= ~ACB_F_IOP_INITED;
1303
1304 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1305 if (!atomic_read(&acb->ccboutstandingcount))
1306 break;
1307 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1308 msleep(25);
1309 }
1310
1311 if (atomic_read(&acb->ccboutstandingcount)) {
1312 int i;
1313
1314 arcmsr_abort_allcmd(acb);
1315 arcmsr_done4abort_postqueue(acb);
1316 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1317 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1318 if (ccb->startdone == ARCMSR_CCB_START) {
1319 ccb->startdone = ARCMSR_CCB_ABORTED;
1320 ccb->pcmd->result = DID_ABORT << 16;
1321 arcmsr_ccb_complete(ccb);
1322 }
1323 }
1324 }
1325 arcmsr_free_irq(pdev, acb);
1326 arcmsr_free_ccb_pool(acb);
1327 arcmsr_free_mu(acb);
1328 arcmsr_unmap_pciregion(acb);
1329 pci_release_regions(pdev);
1330 scsi_host_put(host);
1331 pci_disable_device(pdev);
1332 }
1333
1334 static void arcmsr_shutdown(struct pci_dev *pdev)
1335 {
1336 struct Scsi_Host *host = pci_get_drvdata(pdev);
1337 struct AdapterControlBlock *acb =
1338 (struct AdapterControlBlock *)host->hostdata;
1339 del_timer_sync(&acb->eternal_timer);
1340 arcmsr_disable_outbound_ints(acb);
1341 arcmsr_free_irq(pdev, acb);
1342 flush_work(&acb->arcmsr_do_message_isr_bh);
1343 arcmsr_stop_adapter_bgrb(acb);
1344 arcmsr_flush_adapter_cache(acb);
1345 }
1346
1347 static int arcmsr_module_init(void)
1348 {
1349 int error = 0;
1350 error = pci_register_driver(&arcmsr_pci_driver);
1351 return error;
1352 }
1353
1354 static void arcmsr_module_exit(void)
1355 {
1356 pci_unregister_driver(&arcmsr_pci_driver);
1357 }
1358 module_init(arcmsr_module_init);
1359 module_exit(arcmsr_module_exit);
1360
1361 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1362 u32 intmask_org)
1363 {
1364 u32 mask;
1365 switch (acb->adapter_type) {
1366
1367 case ACB_ADAPTER_TYPE_A: {
1368 struct MessageUnit_A __iomem *reg = acb->pmuA;
1369 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
1370 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1371 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1372 writel(mask, &reg->outbound_intmask);
1373 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1374 }
1375 break;
1376
1377 case ACB_ADAPTER_TYPE_B: {
1378 struct MessageUnit_B *reg = acb->pmuB;
1379 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1380 ARCMSR_IOP2DRV_DATA_READ_OK |
1381 ARCMSR_IOP2DRV_CDB_DONE |
1382 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
1383 writel(mask, reg->iop2drv_doorbell_mask);
1384 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1385 }
1386 break;
1387 case ACB_ADAPTER_TYPE_C: {
1388 struct MessageUnit_C __iomem *reg = acb->pmuC;
1389 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1390 writel(intmask_org & mask, &reg->host_int_mask);
1391 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1392 }
1393 break;
1394 case ACB_ADAPTER_TYPE_D: {
1395 struct MessageUnit_D *reg = acb->pmuD;
1396
1397 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1398 writel(intmask_org | mask, reg->pcief0_int_enable);
1399 break;
1400 }
1401 }
1402 }
1403
1404 static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1405 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1406 {
1407 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1408 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
1409 __le32 address_lo, address_hi;
1410 int arccdbsize = 0x30;
1411 __le32 length = 0;
1412 int i;
1413 struct scatterlist *sg;
1414 int nseg;
1415 ccb->pcmd = pcmd;
1416 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1417 arcmsr_cdb->TargetID = pcmd->device->id;
1418 arcmsr_cdb->LUN = pcmd->device->lun;
1419 arcmsr_cdb->Function = 1;
1420 arcmsr_cdb->msgContext = 0;
1421 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
1422
1423 nseg = scsi_dma_map(pcmd);
1424 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
1425 return FAILED;
1426 scsi_for_each_sg(pcmd, sg, nseg, i) {
1427 /* Get the physical address of the current data pointer */
1428 length = cpu_to_le32(sg_dma_len(sg));
1429 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1430 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1431 if (address_hi == 0) {
1432 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1433
1434 pdma_sg->address = address_lo;
1435 pdma_sg->length = length;
1436 psge += sizeof (struct SG32ENTRY);
1437 arccdbsize += sizeof (struct SG32ENTRY);
1438 } else {
1439 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1440
1441 pdma_sg->addresshigh = address_hi;
1442 pdma_sg->address = address_lo;
1443 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1444 psge += sizeof (struct SG64ENTRY);
1445 arccdbsize += sizeof (struct SG64ENTRY);
1446 }
1447 }
1448 arcmsr_cdb->sgcount = (uint8_t)nseg;
1449 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
1450 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
1451 if ( arccdbsize > 256)
1452 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1453 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1454 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1455 ccb->arc_cdb_size = arccdbsize;
1456 return SUCCESS;
1457 }
1458
1459 static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1460 {
1461 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1462 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1463 atomic_inc(&acb->ccboutstandingcount);
1464 ccb->startdone = ARCMSR_CCB_START;
1465 switch (acb->adapter_type) {
1466 case ACB_ADAPTER_TYPE_A: {
1467 struct MessageUnit_A __iomem *reg = acb->pmuA;
1468
1469 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
1470 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1471 &reg->inbound_queueport);
1472 else
1473 writel(cdb_phyaddr, &reg->inbound_queueport);
1474 break;
1475 }
1476
1477 case ACB_ADAPTER_TYPE_B: {
1478 struct MessageUnit_B *reg = acb->pmuB;
1479 uint32_t ending_index, index = reg->postq_index;
1480
1481 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1482 reg->post_qbuffer[ending_index] = 0;
1483 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1484 reg->post_qbuffer[index] =
1485 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
1486 } else {
1487 reg->post_qbuffer[index] = cdb_phyaddr;
1488 }
1489 index++;
1490 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1491 reg->postq_index = index;
1492 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1493 }
1494 break;
1495 case ACB_ADAPTER_TYPE_C: {
1496 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1497 uint32_t ccb_post_stamp, arc_cdb_size;
1498
1499 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1500 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
1501 if (acb->cdb_phyaddr_hi32) {
1502 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1503 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1504 } else {
1505 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1506 }
1507 }
1508 break;
1509 case ACB_ADAPTER_TYPE_D: {
1510 struct MessageUnit_D *pmu = acb->pmuD;
1511 u16 index_stripped;
1512 u16 postq_index, toggle;
1513 unsigned long flags;
1514 struct InBound_SRB *pinbound_srb;
1515
1516 spin_lock_irqsave(&acb->postq_lock, flags);
1517 postq_index = pmu->postq_index;
1518 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
1519 pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
1520 pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
1521 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1522 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
1523 toggle = postq_index & 0x4000;
1524 index_stripped = postq_index + 1;
1525 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1526 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1527 (toggle ^ 0x4000);
1528 writel(postq_index, pmu->inboundlist_write_pointer);
1529 spin_unlock_irqrestore(&acb->postq_lock, flags);
1530 break;
1531 }
1532 }
1533 }
1534
1535 static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1536 {
1537 struct MessageUnit_A __iomem *reg = acb->pmuA;
1538 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1539 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1540 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1541 printk(KERN_NOTICE
1542 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1543 , acb->host->host_no);
1544 }
1545 }
1546
1547 static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1548 {
1549 struct MessageUnit_B *reg = acb->pmuB;
1550 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1551 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1552
1553 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1554 printk(KERN_NOTICE
1555 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1556 , acb->host->host_no);
1557 }
1558 }
1559
1560 static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
1561 {
1562 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1563 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1564 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1565 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
1566 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
1567 printk(KERN_NOTICE
1568 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1569 , pACB->host->host_no);
1570 }
1571 return;
1572 }
1573
1574 static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
1575 {
1576 struct MessageUnit_D *reg = pACB->pmuD;
1577
1578 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1579 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
1580 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
1581 pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
1582 "timeout\n", pACB->host->host_no);
1583 }
1584
1585 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1586 {
1587 switch (acb->adapter_type) {
1588 case ACB_ADAPTER_TYPE_A: {
1589 arcmsr_hbaA_stop_bgrb(acb);
1590 }
1591 break;
1592
1593 case ACB_ADAPTER_TYPE_B: {
1594 arcmsr_hbaB_stop_bgrb(acb);
1595 }
1596 break;
1597 case ACB_ADAPTER_TYPE_C: {
1598 arcmsr_hbaC_stop_bgrb(acb);
1599 }
1600 break;
1601 case ACB_ADAPTER_TYPE_D:
1602 arcmsr_hbaD_stop_bgrb(acb);
1603 break;
1604 }
1605 }
1606
1607 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1608 {
1609 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1610 }
1611
1612 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1613 {
1614 switch (acb->adapter_type) {
1615 case ACB_ADAPTER_TYPE_A: {
1616 struct MessageUnit_A __iomem *reg = acb->pmuA;
1617 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1618 }
1619 break;
1620
1621 case ACB_ADAPTER_TYPE_B: {
1622 struct MessageUnit_B *reg = acb->pmuB;
1623 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1624 }
1625 break;
1626 case ACB_ADAPTER_TYPE_C: {
1627 struct MessageUnit_C __iomem *reg = acb->pmuC;
1628
1629 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1630 }
1631 break;
1632 case ACB_ADAPTER_TYPE_D: {
1633 struct MessageUnit_D *reg = acb->pmuD;
1634 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
1635 reg->inbound_doorbell);
1636 }
1637 break;
1638 }
1639 }
1640
1641 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1642 {
1643 switch (acb->adapter_type) {
1644 case ACB_ADAPTER_TYPE_A: {
1645 struct MessageUnit_A __iomem *reg = acb->pmuA;
1646 /*
1647 ** push inbound doorbell tell iop, driver data write ok
1648 ** and wait reply on next hwinterrupt for next Qbuffer post
1649 */
1650 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1651 }
1652 break;
1653
1654 case ACB_ADAPTER_TYPE_B: {
1655 struct MessageUnit_B *reg = acb->pmuB;
1656 /*
1657 ** push inbound doorbell tell iop, driver data write ok
1658 ** and wait reply on next hwinterrupt for next Qbuffer post
1659 */
1660 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1661 }
1662 break;
1663 case ACB_ADAPTER_TYPE_C: {
1664 struct MessageUnit_C __iomem *reg = acb->pmuC;
1665 /*
1666 ** push inbound doorbell tell iop, driver data write ok
1667 ** and wait reply on next hwinterrupt for next Qbuffer post
1668 */
1669 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1670 }
1671 break;
1672 case ACB_ADAPTER_TYPE_D: {
1673 struct MessageUnit_D *reg = acb->pmuD;
1674 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
1675 reg->inbound_doorbell);
1676 }
1677 break;
1678 }
1679 }
1680
1681 struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1682 {
1683 struct QBUFFER __iomem *qbuffer = NULL;
1684 switch (acb->adapter_type) {
1685
1686 case ACB_ADAPTER_TYPE_A: {
1687 struct MessageUnit_A __iomem *reg = acb->pmuA;
1688 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1689 }
1690 break;
1691
1692 case ACB_ADAPTER_TYPE_B: {
1693 struct MessageUnit_B *reg = acb->pmuB;
1694 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1695 }
1696 break;
1697 case ACB_ADAPTER_TYPE_C: {
1698 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1699 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1700 }
1701 break;
1702 case ACB_ADAPTER_TYPE_D: {
1703 struct MessageUnit_D *reg = acb->pmuD;
1704 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1705 }
1706 break;
1707 }
1708 return qbuffer;
1709 }
1710
1711 static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1712 {
1713 struct QBUFFER __iomem *pqbuffer = NULL;
1714 switch (acb->adapter_type) {
1715
1716 case ACB_ADAPTER_TYPE_A: {
1717 struct MessageUnit_A __iomem *reg = acb->pmuA;
1718 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1719 }
1720 break;
1721
1722 case ACB_ADAPTER_TYPE_B: {
1723 struct MessageUnit_B *reg = acb->pmuB;
1724 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1725 }
1726 break;
1727 case ACB_ADAPTER_TYPE_C: {
1728 struct MessageUnit_C __iomem *reg = acb->pmuC;
1729 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
1730 }
1731 break;
1732 case ACB_ADAPTER_TYPE_D: {
1733 struct MessageUnit_D *reg = acb->pmuD;
1734 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1735 }
1736 break;
1737 }
1738 return pqbuffer;
1739 }
1740
1741 static uint32_t
1742 arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
1743 struct QBUFFER __iomem *prbuffer)
1744 {
1745 uint8_t *pQbuffer;
1746 uint8_t *buf1 = NULL;
1747 uint32_t __iomem *iop_data;
1748 uint32_t iop_len, data_len, *buf2 = NULL;
1749
1750 iop_data = (uint32_t __iomem *)prbuffer->data;
1751 iop_len = readl(&prbuffer->data_len);
1752 if (iop_len > 0) {
1753 buf1 = kmalloc(128, GFP_ATOMIC);
1754 buf2 = (uint32_t *)buf1;
1755 if (buf1 == NULL)
1756 return 0;
1757 data_len = iop_len;
1758 while (data_len >= 4) {
1759 *buf2++ = readl(iop_data);
1760 iop_data++;
1761 data_len -= 4;
1762 }
1763 if (data_len)
1764 *buf2 = readl(iop_data);
1765 buf2 = (uint32_t *)buf1;
1766 }
1767 while (iop_len > 0) {
1768 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
1769 *pQbuffer = *buf1;
1770 acb->rqbuf_putIndex++;
1771 /* if last, index number set it to 0 */
1772 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
1773 buf1++;
1774 iop_len--;
1775 }
1776 kfree(buf2);
1777 /* let IOP know data has been read */
1778 arcmsr_iop_message_read(acb);
1779 return 1;
1780 }
1781
1782 uint32_t
1783 arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1784 struct QBUFFER __iomem *prbuffer) {
1785
1786 uint8_t *pQbuffer;
1787 uint8_t __iomem *iop_data;
1788 uint32_t iop_len;
1789
1790 if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D))
1791 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
1792 iop_data = (uint8_t __iomem *)prbuffer->data;
1793 iop_len = readl(&prbuffer->data_len);
1794 while (iop_len > 0) {
1795 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
1796 *pQbuffer = readb(iop_data);
1797 acb->rqbuf_putIndex++;
1798 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
1799 iop_data++;
1800 iop_len--;
1801 }
1802 arcmsr_iop_message_read(acb);
1803 return 1;
1804 }
1805
1806 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1807 {
1808 unsigned long flags;
1809 struct QBUFFER __iomem *prbuffer;
1810 int32_t buf_empty_len;
1811
1812 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
1813 prbuffer = arcmsr_get_iop_rqbuffer(acb);
1814 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
1815 (ARCMSR_MAX_QBUFFER - 1);
1816 if (buf_empty_len >= readl(&prbuffer->data_len)) {
1817 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1818 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1819 } else
1820 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1821 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
1822 }
1823
1824 static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
1825 {
1826 uint8_t *pQbuffer;
1827 struct QBUFFER __iomem *pwbuffer;
1828 uint8_t *buf1 = NULL;
1829 uint32_t __iomem *iop_data;
1830 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
1831
1832 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1833 buf1 = kmalloc(128, GFP_ATOMIC);
1834 buf2 = (uint32_t *)buf1;
1835 if (buf1 == NULL)
1836 return;
1837
1838 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1839 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1840 iop_data = (uint32_t __iomem *)pwbuffer->data;
1841 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
1842 && (allxfer_len < 124)) {
1843 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
1844 *buf1 = *pQbuffer;
1845 acb->wqbuf_getIndex++;
1846 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1847 buf1++;
1848 allxfer_len++;
1849 }
1850 data_len = allxfer_len;
1851 buf1 = (uint8_t *)buf2;
1852 while (data_len >= 4) {
1853 data = *buf2++;
1854 writel(data, iop_data);
1855 iop_data++;
1856 data_len -= 4;
1857 }
1858 if (data_len) {
1859 data = *buf2;
1860 writel(data, iop_data);
1861 }
1862 writel(allxfer_len, &pwbuffer->data_len);
1863 kfree(buf1);
1864 arcmsr_iop_message_wrote(acb);
1865 }
1866 }
1867
1868 void
1869 arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
1870 {
1871 uint8_t *pQbuffer;
1872 struct QBUFFER __iomem *pwbuffer;
1873 uint8_t __iomem *iop_data;
1874 int32_t allxfer_len = 0;
1875
1876 if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1877 arcmsr_write_ioctldata2iop_in_DWORD(acb);
1878 return;
1879 }
1880 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1881 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1882 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1883 iop_data = (uint8_t __iomem *)pwbuffer->data;
1884 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
1885 && (allxfer_len < 124)) {
1886 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
1887 writeb(*pQbuffer, iop_data);
1888 acb->wqbuf_getIndex++;
1889 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1890 iop_data++;
1891 allxfer_len++;
1892 }
1893 writel(allxfer_len, &pwbuffer->data_len);
1894 arcmsr_iop_message_wrote(acb);
1895 }
1896 }
1897
1898 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1899 {
1900 unsigned long flags;
1901
1902 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
1903 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
1904 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
1905 arcmsr_write_ioctldata2iop(acb);
1906 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
1907 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1908 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
1909 }
1910
1911 static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
1912 {
1913 uint32_t outbound_doorbell;
1914 struct MessageUnit_A __iomem *reg = acb->pmuA;
1915 outbound_doorbell = readl(&reg->outbound_doorbell);
1916 do {
1917 writel(outbound_doorbell, &reg->outbound_doorbell);
1918 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
1919 arcmsr_iop2drv_data_wrote_handle(acb);
1920 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
1921 arcmsr_iop2drv_data_read_handle(acb);
1922 outbound_doorbell = readl(&reg->outbound_doorbell);
1923 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
1924 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
1925 }
1926 static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
1927 {
1928 uint32_t outbound_doorbell;
1929 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1930 /*
1931 *******************************************************************
1932 ** Maybe here we need to check wrqbuffer_lock is lock or not
1933 ** DOORBELL: din! don!
1934 ** check if there are any mail need to pack from firmware
1935 *******************************************************************
1936 */
1937 outbound_doorbell = readl(&reg->outbound_doorbell);
1938 do {
1939 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
1940 readl(&reg->outbound_doorbell_clear);
1941 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
1942 arcmsr_iop2drv_data_wrote_handle(pACB);
1943 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
1944 arcmsr_iop2drv_data_read_handle(pACB);
1945 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
1946 arcmsr_hbaC_message_isr(pACB);
1947 outbound_doorbell = readl(&reg->outbound_doorbell);
1948 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
1949 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
1950 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
1951 }
1952
1953 static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
1954 {
1955 uint32_t outbound_doorbell;
1956 struct MessageUnit_D *pmu = pACB->pmuD;
1957
1958 outbound_doorbell = readl(pmu->outbound_doorbell);
1959 do {
1960 writel(outbound_doorbell, pmu->outbound_doorbell);
1961 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
1962 arcmsr_hbaD_message_isr(pACB);
1963 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
1964 arcmsr_iop2drv_data_wrote_handle(pACB);
1965 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
1966 arcmsr_iop2drv_data_read_handle(pACB);
1967 outbound_doorbell = readl(pmu->outbound_doorbell);
1968 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
1969 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
1970 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
1971 }
1972
1973 static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
1974 {
1975 uint32_t flag_ccb;
1976 struct MessageUnit_A __iomem *reg = acb->pmuA;
1977 struct ARCMSR_CDB *pARCMSR_CDB;
1978 struct CommandControlBlock *pCCB;
1979 bool error;
1980 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
1981 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1982 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1983 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1984 arcmsr_drain_donequeue(acb, pCCB, error);
1985 }
1986 }
1987 static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
1988 {
1989 uint32_t index;
1990 uint32_t flag_ccb;
1991 struct MessageUnit_B *reg = acb->pmuB;
1992 struct ARCMSR_CDB *pARCMSR_CDB;
1993 struct CommandControlBlock *pCCB;
1994 bool error;
1995 index = reg->doneq_index;
1996 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
1997 reg->done_qbuffer[index] = 0;
1998 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1999 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2000 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2001 arcmsr_drain_donequeue(acb, pCCB, error);
2002 index++;
2003 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2004 reg->doneq_index = index;
2005 }
2006 }
2007
2008 static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
2009 {
2010 struct MessageUnit_C __iomem *phbcmu;
2011 struct ARCMSR_CDB *arcmsr_cdb;
2012 struct CommandControlBlock *ccb;
2013 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
2014 int error;
2015
2016 phbcmu = acb->pmuC;
2017 /* areca cdb command done */
2018 /* Use correct offset and size for syncing */
2019
2020 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
2021 0xFFFFFFFF) {
2022 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2023 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2024 + ccb_cdb_phy);
2025 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
2026 arcmsr_cdb);
2027 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2028 ? true : false;
2029 /* check if command done with no error */
2030 arcmsr_drain_donequeue(acb, ccb, error);
2031 throttling++;
2032 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2033 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
2034 &phbcmu->inbound_doorbell);
2035 throttling = 0;
2036 }
2037 }
2038 }
2039
2040 static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
2041 {
2042 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
2043 uint32_t addressLow, ccb_cdb_phy;
2044 int error;
2045 struct MessageUnit_D *pmu;
2046 struct ARCMSR_CDB *arcmsr_cdb;
2047 struct CommandControlBlock *ccb;
2048 unsigned long flags;
2049
2050 spin_lock_irqsave(&acb->doneq_lock, flags);
2051 pmu = acb->pmuD;
2052 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
2053 doneq_index = pmu->doneq_index;
2054 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
2055 do {
2056 toggle = doneq_index & 0x4000;
2057 index_stripped = (doneq_index & 0xFFF) + 1;
2058 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
2059 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
2060 ((toggle ^ 0x4000) + 1);
2061 doneq_index = pmu->doneq_index;
2062 addressLow = pmu->done_qbuffer[doneq_index &
2063 0xFFF].addressLow;
2064 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
2065 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2066 + ccb_cdb_phy);
2067 ccb = container_of(arcmsr_cdb,
2068 struct CommandControlBlock, arcmsr_cdb);
2069 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2070 ? true : false;
2071 arcmsr_drain_donequeue(acb, ccb, error);
2072 writel(doneq_index, pmu->outboundlist_read_pointer);
2073 } while ((doneq_index & 0xFFF) !=
2074 (outbound_write_pointer & 0xFFF));
2075 }
2076 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2077 pmu->outboundlist_interrupt_cause);
2078 readl(pmu->outboundlist_interrupt_cause);
2079 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2080 }
2081
2082 /*
2083 **********************************************************************************
2084 ** Handle a message interrupt
2085 **
2086 ** The only message interrupt we expect is in response to a query for the current adapter config.
2087 ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2088 **********************************************************************************
2089 */
2090 static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
2091 {
2092 struct MessageUnit_A __iomem *reg = acb->pmuA;
2093 /*clear interrupt and message state*/
2094 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
2095 schedule_work(&acb->arcmsr_do_message_isr_bh);
2096 }
2097 static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
2098 {
2099 struct MessageUnit_B *reg = acb->pmuB;
2100
2101 /*clear interrupt and message state*/
2102 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2103 schedule_work(&acb->arcmsr_do_message_isr_bh);
2104 }
2105 /*
2106 **********************************************************************************
2107 ** Handle a message interrupt
2108 **
2109 ** The only message interrupt we expect is in response to a query for the
2110 ** current adapter config.
2111 ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2112 **********************************************************************************
2113 */
2114 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
2115 {
2116 struct MessageUnit_C __iomem *reg = acb->pmuC;
2117 /*clear interrupt and message state*/
2118 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
2119 schedule_work(&acb->arcmsr_do_message_isr_bh);
2120 }
2121
2122 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2123 {
2124 struct MessageUnit_D *reg = acb->pmuD;
2125
2126 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2127 readl(reg->outbound_doorbell);
2128 schedule_work(&acb->arcmsr_do_message_isr_bh);
2129 }
2130
2131 static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
2132 {
2133 uint32_t outbound_intstatus;
2134 struct MessageUnit_A __iomem *reg = acb->pmuA;
2135 outbound_intstatus = readl(&reg->outbound_intstatus) &
2136 acb->outbound_int_enable;
2137 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2138 return IRQ_NONE;
2139 do {
2140 writel(outbound_intstatus, &reg->outbound_intstatus);
2141 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
2142 arcmsr_hbaA_doorbell_isr(acb);
2143 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
2144 arcmsr_hbaA_postqueue_isr(acb);
2145 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
2146 arcmsr_hbaA_message_isr(acb);
2147 outbound_intstatus = readl(&reg->outbound_intstatus) &
2148 acb->outbound_int_enable;
2149 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2150 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2151 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2152 return IRQ_HANDLED;
2153 }
2154
2155 static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
2156 {
2157 uint32_t outbound_doorbell;
2158 struct MessageUnit_B *reg = acb->pmuB;
2159 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2160 acb->outbound_int_enable;
2161 if (!outbound_doorbell)
2162 return IRQ_NONE;
2163 do {
2164 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2165 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2166 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2167 arcmsr_iop2drv_data_wrote_handle(acb);
2168 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2169 arcmsr_iop2drv_data_read_handle(acb);
2170 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
2171 arcmsr_hbaB_postqueue_isr(acb);
2172 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
2173 arcmsr_hbaB_message_isr(acb);
2174 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2175 acb->outbound_int_enable;
2176 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2177 | ARCMSR_IOP2DRV_DATA_READ_OK
2178 | ARCMSR_IOP2DRV_CDB_DONE
2179 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2180 return IRQ_HANDLED;
2181 }
2182
2183 static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
2184 {
2185 uint32_t host_interrupt_status;
2186 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
2187 /*
2188 *********************************************
2189 ** check outbound intstatus
2190 *********************************************
2191 */
2192 host_interrupt_status = readl(&phbcmu->host_int_status) &
2193 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2194 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2195 if (!host_interrupt_status)
2196 return IRQ_NONE;
2197 do {
2198 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
2199 arcmsr_hbaC_doorbell_isr(pACB);
2200 /* MU post queue interrupts*/
2201 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
2202 arcmsr_hbaC_postqueue_isr(pACB);
2203 host_interrupt_status = readl(&phbcmu->host_int_status);
2204 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2205 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2206 return IRQ_HANDLED;
2207 }
2208
2209 static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2210 {
2211 u32 host_interrupt_status;
2212 struct MessageUnit_D *pmu = pACB->pmuD;
2213
2214 host_interrupt_status = readl(pmu->host_int_status) &
2215 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2216 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2217 if (!host_interrupt_status)
2218 return IRQ_NONE;
2219 do {
2220 /* MU post queue interrupts*/
2221 if (host_interrupt_status &
2222 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2223 arcmsr_hbaD_postqueue_isr(pACB);
2224 if (host_interrupt_status &
2225 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2226 arcmsr_hbaD_doorbell_isr(pACB);
2227 host_interrupt_status = readl(pmu->host_int_status);
2228 } while (host_interrupt_status &
2229 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2230 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2231 return IRQ_HANDLED;
2232 }
2233
2234 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2235 {
2236 switch (acb->adapter_type) {
2237 case ACB_ADAPTER_TYPE_A:
2238 return arcmsr_hbaA_handle_isr(acb);
2239 break;
2240 case ACB_ADAPTER_TYPE_B:
2241 return arcmsr_hbaB_handle_isr(acb);
2242 break;
2243 case ACB_ADAPTER_TYPE_C:
2244 return arcmsr_hbaC_handle_isr(acb);
2245 case ACB_ADAPTER_TYPE_D:
2246 return arcmsr_hbaD_handle_isr(acb);
2247 default:
2248 return IRQ_NONE;
2249 }
2250 }
2251
2252 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2253 {
2254 if (acb) {
2255 /* stop adapter background rebuild */
2256 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
2257 uint32_t intmask_org;
2258 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
2259 intmask_org = arcmsr_disable_outbound_ints(acb);
2260 arcmsr_stop_adapter_bgrb(acb);
2261 arcmsr_flush_adapter_cache(acb);
2262 arcmsr_enable_outbound_ints(acb, intmask_org);
2263 }
2264 }
2265 }
2266
2267
2268 void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
2269 {
2270 uint32_t i;
2271
2272 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2273 for (i = 0; i < 15; i++) {
2274 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2275 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2276 acb->rqbuf_getIndex = 0;
2277 acb->rqbuf_putIndex = 0;
2278 arcmsr_iop_message_read(acb);
2279 mdelay(30);
2280 } else if (acb->rqbuf_getIndex !=
2281 acb->rqbuf_putIndex) {
2282 acb->rqbuf_getIndex = 0;
2283 acb->rqbuf_putIndex = 0;
2284 mdelay(30);
2285 } else
2286 break;
2287 }
2288 }
2289 }
2290
2291 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
2292 struct scsi_cmnd *cmd)
2293 {
2294 char *buffer;
2295 unsigned short use_sg;
2296 int retvalue = 0, transfer_len = 0;
2297 unsigned long flags;
2298 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2299 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
2300 (uint32_t)cmd->cmnd[6] << 16 |
2301 (uint32_t)cmd->cmnd[7] << 8 |
2302 (uint32_t)cmd->cmnd[8];
2303 struct scatterlist *sg;
2304
2305 use_sg = scsi_sg_count(cmd);
2306 sg = scsi_sglist(cmd);
2307 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2308 if (use_sg > 1) {
2309 retvalue = ARCMSR_MESSAGE_FAIL;
2310 goto message_out;
2311 }
2312 transfer_len += sg->length;
2313 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2314 retvalue = ARCMSR_MESSAGE_FAIL;
2315 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
2316 goto message_out;
2317 }
2318 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
2319 switch (controlcode) {
2320 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2321 unsigned char *ver_addr;
2322 uint8_t *ptmpQbuffer;
2323 uint32_t allxfer_len = 0;
2324 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2325 if (!ver_addr) {
2326 retvalue = ARCMSR_MESSAGE_FAIL;
2327 pr_info("%s: memory not enough!\n", __func__);
2328 goto message_out;
2329 }
2330 ptmpQbuffer = ver_addr;
2331 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2332 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
2333 unsigned int tail = acb->rqbuf_getIndex;
2334 unsigned int head = acb->rqbuf_putIndex;
2335 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
2336
2337 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
2338 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
2339 allxfer_len = ARCMSR_API_DATA_BUFLEN;
2340
2341 if (allxfer_len <= cnt_to_end)
2342 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
2343 else {
2344 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
2345 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
2346 }
2347 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
2348 }
2349 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
2350 allxfer_len);
2351 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2352 struct QBUFFER __iomem *prbuffer;
2353 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2354 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2355 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2356 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2357 }
2358 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2359 kfree(ver_addr);
2360 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2361 if (acb->fw_flag == FW_DEADLOCK)
2362 pcmdmessagefld->cmdmessage.ReturnCode =
2363 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2364 else
2365 pcmdmessagefld->cmdmessage.ReturnCode =
2366 ARCMSR_MESSAGE_RETURNCODE_OK;
2367 break;
2368 }
2369 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2370 unsigned char *ver_addr;
2371 uint32_t user_len;
2372 int32_t cnt2end;
2373 uint8_t *pQbuffer, *ptmpuserbuffer;
2374
2375 user_len = pcmdmessagefld->cmdmessage.Length;
2376 if (user_len > ARCMSR_API_DATA_BUFLEN) {
2377 retvalue = ARCMSR_MESSAGE_FAIL;
2378 goto message_out;
2379 }
2380
2381 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2382 if (!ver_addr) {
2383 retvalue = ARCMSR_MESSAGE_FAIL;
2384 goto message_out;
2385 }
2386 ptmpuserbuffer = ver_addr;
2387
2388 memcpy(ptmpuserbuffer,
2389 pcmdmessagefld->messagedatabuffer, user_len);
2390 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2391 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
2392 struct SENSE_DATA *sensebuffer =
2393 (struct SENSE_DATA *)cmd->sense_buffer;
2394 arcmsr_write_ioctldata2iop(acb);
2395 /* has error report sensedata */
2396 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
2397 sensebuffer->SenseKey = ILLEGAL_REQUEST;
2398 sensebuffer->AdditionalSenseLength = 0x0A;
2399 sensebuffer->AdditionalSenseCode = 0x20;
2400 sensebuffer->Valid = 1;
2401 retvalue = ARCMSR_MESSAGE_FAIL;
2402 } else {
2403 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
2404 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
2405 if (user_len > cnt2end) {
2406 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
2407 ptmpuserbuffer += cnt2end;
2408 user_len -= cnt2end;
2409 acb->wqbuf_putIndex = 0;
2410 pQbuffer = acb->wqbuffer;
2411 }
2412 memcpy(pQbuffer, ptmpuserbuffer, user_len);
2413 acb->wqbuf_putIndex += user_len;
2414 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2415 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2416 acb->acb_flags &=
2417 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2418 arcmsr_write_ioctldata2iop(acb);
2419 }
2420 }
2421 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2422 kfree(ver_addr);
2423 if (acb->fw_flag == FW_DEADLOCK)
2424 pcmdmessagefld->cmdmessage.ReturnCode =
2425 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2426 else
2427 pcmdmessagefld->cmdmessage.ReturnCode =
2428 ARCMSR_MESSAGE_RETURNCODE_OK;
2429 break;
2430 }
2431 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2432 uint8_t *pQbuffer = acb->rqbuffer;
2433
2434 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2435 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2436 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2437 acb->rqbuf_getIndex = 0;
2438 acb->rqbuf_putIndex = 0;
2439 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2440 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2441 if (acb->fw_flag == FW_DEADLOCK)
2442 pcmdmessagefld->cmdmessage.ReturnCode =
2443 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2444 else
2445 pcmdmessagefld->cmdmessage.ReturnCode =
2446 ARCMSR_MESSAGE_RETURNCODE_OK;
2447 break;
2448 }
2449 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2450 uint8_t *pQbuffer = acb->wqbuffer;
2451 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2452 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2453 ACB_F_MESSAGE_WQBUFFER_READED);
2454 acb->wqbuf_getIndex = 0;
2455 acb->wqbuf_putIndex = 0;
2456 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2457 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2458 if (acb->fw_flag == FW_DEADLOCK)
2459 pcmdmessagefld->cmdmessage.ReturnCode =
2460 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2461 else
2462 pcmdmessagefld->cmdmessage.ReturnCode =
2463 ARCMSR_MESSAGE_RETURNCODE_OK;
2464 break;
2465 }
2466 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2467 uint8_t *pQbuffer;
2468 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2469 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2470 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2471 acb->rqbuf_getIndex = 0;
2472 acb->rqbuf_putIndex = 0;
2473 pQbuffer = acb->rqbuffer;
2474 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2475 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2476 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2477 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2478 ACB_F_MESSAGE_WQBUFFER_READED);
2479 acb->wqbuf_getIndex = 0;
2480 acb->wqbuf_putIndex = 0;
2481 pQbuffer = acb->wqbuffer;
2482 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2483 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2484 if (acb->fw_flag == FW_DEADLOCK)
2485 pcmdmessagefld->cmdmessage.ReturnCode =
2486 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2487 else
2488 pcmdmessagefld->cmdmessage.ReturnCode =
2489 ARCMSR_MESSAGE_RETURNCODE_OK;
2490 break;
2491 }
2492 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
2493 if (acb->fw_flag == FW_DEADLOCK)
2494 pcmdmessagefld->cmdmessage.ReturnCode =
2495 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2496 else
2497 pcmdmessagefld->cmdmessage.ReturnCode =
2498 ARCMSR_MESSAGE_RETURNCODE_3F;
2499 break;
2500 }
2501 case ARCMSR_MESSAGE_SAY_HELLO: {
2502 int8_t *hello_string = "Hello! I am ARCMSR";
2503 if (acb->fw_flag == FW_DEADLOCK)
2504 pcmdmessagefld->cmdmessage.ReturnCode =
2505 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2506 else
2507 pcmdmessagefld->cmdmessage.ReturnCode =
2508 ARCMSR_MESSAGE_RETURNCODE_OK;
2509 memcpy(pcmdmessagefld->messagedatabuffer,
2510 hello_string, (int16_t)strlen(hello_string));
2511 break;
2512 }
2513 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2514 if (acb->fw_flag == FW_DEADLOCK)
2515 pcmdmessagefld->cmdmessage.ReturnCode =
2516 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2517 else
2518 pcmdmessagefld->cmdmessage.ReturnCode =
2519 ARCMSR_MESSAGE_RETURNCODE_OK;
2520 arcmsr_iop_parking(acb);
2521 break;
2522 }
2523 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2524 if (acb->fw_flag == FW_DEADLOCK)
2525 pcmdmessagefld->cmdmessage.ReturnCode =
2526 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2527 else
2528 pcmdmessagefld->cmdmessage.ReturnCode =
2529 ARCMSR_MESSAGE_RETURNCODE_OK;
2530 arcmsr_flush_adapter_cache(acb);
2531 break;
2532 }
2533 default:
2534 retvalue = ARCMSR_MESSAGE_FAIL;
2535 pr_info("%s: unknown controlcode!\n", __func__);
2536 }
2537 message_out:
2538 if (use_sg) {
2539 struct scatterlist *sg = scsi_sglist(cmd);
2540 kunmap_atomic(buffer - sg->offset);
2541 }
2542 return retvalue;
2543 }
2544
2545 static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
2546 {
2547 struct list_head *head = &acb->ccb_free_list;
2548 struct CommandControlBlock *ccb = NULL;
2549 unsigned long flags;
2550 spin_lock_irqsave(&acb->ccblist_lock, flags);
2551 if (!list_empty(head)) {
2552 ccb = list_entry(head->next, struct CommandControlBlock, list);
2553 list_del_init(&ccb->list);
2554 }else{
2555 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2556 return NULL;
2557 }
2558 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2559 return ccb;
2560 }
2561
2562 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2563 struct scsi_cmnd *cmd)
2564 {
2565 switch (cmd->cmnd[0]) {
2566 case INQUIRY: {
2567 unsigned char inqdata[36];
2568 char *buffer;
2569 struct scatterlist *sg;
2570
2571 if (cmd->device->lun) {
2572 cmd->result = (DID_TIME_OUT << 16);
2573 cmd->scsi_done(cmd);
2574 return;
2575 }
2576 inqdata[0] = TYPE_PROCESSOR;
2577 /* Periph Qualifier & Periph Dev Type */
2578 inqdata[1] = 0;
2579 /* rem media bit & Dev Type Modifier */
2580 inqdata[2] = 0;
2581 /* ISO, ECMA, & ANSI versions */
2582 inqdata[4] = 31;
2583 /* length of additional data */
2584 strncpy(&inqdata[8], "Areca ", 8);
2585 /* Vendor Identification */
2586 strncpy(&inqdata[16], "RAID controller ", 16);
2587 /* Product Identification */
2588 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2589
2590 sg = scsi_sglist(cmd);
2591 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2592
2593 memcpy(buffer, inqdata, sizeof(inqdata));
2594 sg = scsi_sglist(cmd);
2595 kunmap_atomic(buffer - sg->offset);
2596
2597 cmd->scsi_done(cmd);
2598 }
2599 break;
2600 case WRITE_BUFFER:
2601 case READ_BUFFER: {
2602 if (arcmsr_iop_message_xfer(acb, cmd))
2603 cmd->result = (DID_ERROR << 16);
2604 cmd->scsi_done(cmd);
2605 }
2606 break;
2607 default:
2608 cmd->scsi_done(cmd);
2609 }
2610 }
2611
2612 static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
2613 void (* done)(struct scsi_cmnd *))
2614 {
2615 struct Scsi_Host *host = cmd->device->host;
2616 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
2617 struct CommandControlBlock *ccb;
2618 int target = cmd->device->id;
2619 cmd->scsi_done = done;
2620 cmd->host_scribble = NULL;
2621 cmd->result = 0;
2622 if (target == 16) {
2623 /* virtual device for iop message transfer */
2624 arcmsr_handle_virtual_command(acb, cmd);
2625 return 0;
2626 }
2627 ccb = arcmsr_get_freeccb(acb);
2628 if (!ccb)
2629 return SCSI_MLQUEUE_HOST_BUSY;
2630 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
2631 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2632 cmd->scsi_done(cmd);
2633 return 0;
2634 }
2635 arcmsr_post_ccb(acb, ccb);
2636 return 0;
2637 }
2638
2639 static DEF_SCSI_QCMD(arcmsr_queue_command)
2640
2641 static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
2642 {
2643 struct MessageUnit_A __iomem *reg = acb->pmuA;
2644 char *acb_firm_model = acb->firm_model;
2645 char *acb_firm_version = acb->firm_version;
2646 char *acb_device_map = acb->device_map;
2647 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2648 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
2649 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
2650 int count;
2651 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2652 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
2653 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2654 miscellaneous data' timeout \n", acb->host->host_no);
2655 return false;
2656 }
2657 count = 8;
2658 while (count){
2659 *acb_firm_model = readb(iop_firm_model);
2660 acb_firm_model++;
2661 iop_firm_model++;
2662 count--;
2663 }
2664
2665 count = 16;
2666 while (count){
2667 *acb_firm_version = readb(iop_firm_version);
2668 acb_firm_version++;
2669 iop_firm_version++;
2670 count--;
2671 }
2672
2673 count=16;
2674 while(count){
2675 *acb_device_map = readb(iop_device_map);
2676 acb_device_map++;
2677 iop_device_map++;
2678 count--;
2679 }
2680 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2681 acb->host->host_no,
2682 acb->firm_model,
2683 acb->firm_version);
2684 acb->signature = readl(&reg->message_rwbuffer[0]);
2685 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2686 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2687 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2688 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
2689 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2690 return true;
2691 }
2692 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
2693 {
2694 struct MessageUnit_B *reg = acb->pmuB;
2695 char *acb_firm_model = acb->firm_model;
2696 char *acb_firm_version = acb->firm_version;
2697 char *acb_device_map = acb->device_map;
2698 char __iomem *iop_firm_model;
2699 /*firm_model,15,60-67*/
2700 char __iomem *iop_firm_version;
2701 /*firm_version,17,68-83*/
2702 char __iomem *iop_device_map;
2703 /*firm_version,21,84-99*/
2704 int count;
2705
2706 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2707 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2708 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2709
2710 arcmsr_wait_firmware_ready(acb);
2711 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
2712 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
2713 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
2714 return false;
2715 }
2716 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
2717 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
2718 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2719 miscellaneous data' timeout \n", acb->host->host_no);
2720 return false;
2721 }
2722 count = 8;
2723 while (count){
2724 *acb_firm_model = readb(iop_firm_model);
2725 acb_firm_model++;
2726 iop_firm_model++;
2727 count--;
2728 }
2729 count = 16;
2730 while (count){
2731 *acb_firm_version = readb(iop_firm_version);
2732 acb_firm_version++;
2733 iop_firm_version++;
2734 count--;
2735 }
2736
2737 count = 16;
2738 while(count){
2739 *acb_device_map = readb(iop_device_map);
2740 acb_device_map++;
2741 iop_device_map++;
2742 count--;
2743 }
2744
2745 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2746 acb->host->host_no,
2747 acb->firm_model,
2748 acb->firm_version);
2749
2750 acb->signature = readl(&reg->message_rwbuffer[0]);
2751 /*firm_signature,1,00-03*/
2752 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2753 /*firm_request_len,1,04-07*/
2754 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2755 /*firm_numbers_queue,2,08-11*/
2756 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2757 /*firm_sdram_size,3,12-15*/
2758 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
2759 /*firm_ide_channels,4,16-19*/
2760 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2761 /*firm_ide_channels,4,16-19*/
2762 return true;
2763 }
2764
2765 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
2766 {
2767 uint32_t intmask_org, Index, firmware_state = 0;
2768 struct MessageUnit_C __iomem *reg = pACB->pmuC;
2769 char *acb_firm_model = pACB->firm_model;
2770 char *acb_firm_version = pACB->firm_version;
2771 char __iomem *iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2772 char __iomem *iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
2773 int count;
2774 /* disable all outbound interrupt */
2775 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2776 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2777 /* wait firmware ready */
2778 do {
2779 firmware_state = readl(&reg->outbound_msgaddr1);
2780 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2781 /* post "get config" instruction */
2782 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2783 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2784 /* wait message ready */
2785 for (Index = 0; Index < 2000; Index++) {
2786 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2787 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2788 break;
2789 }
2790 udelay(10);
2791 } /*max 1 seconds*/
2792 if (Index >= 2000) {
2793 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2794 miscellaneous data' timeout \n", pACB->host->host_no);
2795 return false;
2796 }
2797 count = 8;
2798 while (count) {
2799 *acb_firm_model = readb(iop_firm_model);
2800 acb_firm_model++;
2801 iop_firm_model++;
2802 count--;
2803 }
2804 count = 16;
2805 while (count) {
2806 *acb_firm_version = readb(iop_firm_version);
2807 acb_firm_version++;
2808 iop_firm_version++;
2809 count--;
2810 }
2811 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2812 pACB->host->host_no,
2813 pACB->firm_model,
2814 pACB->firm_version);
2815 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2816 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2817 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2818 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2819 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2820 /*all interrupt service will be enable at arcmsr_iop_init*/
2821 return true;
2822 }
2823
2824 static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
2825 {
2826 char *acb_firm_model = acb->firm_model;
2827 char *acb_firm_version = acb->firm_version;
2828 char *acb_device_map = acb->device_map;
2829 char __iomem *iop_firm_model;
2830 char __iomem *iop_firm_version;
2831 char __iomem *iop_device_map;
2832 u32 count;
2833 struct MessageUnit_D *reg = acb->pmuD;
2834
2835 iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]);
2836 iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]);
2837 iop_device_map = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
2838 if (readl(acb->pmuD->outbound_doorbell) &
2839 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
2840 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
2841 acb->pmuD->outbound_doorbell);/*clear interrupt*/
2842 }
2843 /* post "get config" instruction */
2844 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
2845 /* wait message ready */
2846 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
2847 pr_notice("arcmsr%d: wait get adapter firmware "
2848 "miscellaneous data timeout\n", acb->host->host_no);
2849 return false;
2850 }
2851 count = 8;
2852 while (count) {
2853 *acb_firm_model = readb(iop_firm_model);
2854 acb_firm_model++;
2855 iop_firm_model++;
2856 count--;
2857 }
2858 count = 16;
2859 while (count) {
2860 *acb_firm_version = readb(iop_firm_version);
2861 acb_firm_version++;
2862 iop_firm_version++;
2863 count--;
2864 }
2865 count = 16;
2866 while (count) {
2867 *acb_device_map = readb(iop_device_map);
2868 acb_device_map++;
2869 iop_device_map++;
2870 count--;
2871 }
2872 acb->signature = readl(&reg->msgcode_rwbuffer[0]);
2873 /*firm_signature,1,00-03*/
2874 acb->firm_request_len = readl(&reg->msgcode_rwbuffer[1]);
2875 /*firm_request_len,1,04-07*/
2876 acb->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]);
2877 /*firm_numbers_queue,2,08-11*/
2878 acb->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]);
2879 /*firm_sdram_size,3,12-15*/
2880 acb->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]);
2881 /*firm_hd_channels,4,16-19*/
2882 acb->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]);
2883 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2884 acb->host->host_no,
2885 acb->firm_model,
2886 acb->firm_version);
2887 return true;
2888 }
2889
2890 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
2891 {
2892 bool rtn = false;
2893
2894 switch (acb->adapter_type) {
2895 case ACB_ADAPTER_TYPE_A:
2896 rtn = arcmsr_hbaA_get_config(acb);
2897 break;
2898 case ACB_ADAPTER_TYPE_B:
2899 rtn = arcmsr_hbaB_get_config(acb);
2900 break;
2901 case ACB_ADAPTER_TYPE_C:
2902 rtn = arcmsr_hbaC_get_config(acb);
2903 break;
2904 case ACB_ADAPTER_TYPE_D:
2905 rtn = arcmsr_hbaD_get_config(acb);
2906 break;
2907 default:
2908 break;
2909 }
2910 if (acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
2911 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD;
2912 else
2913 acb->maxOutstanding = acb->firm_numbers_queue - 1;
2914 acb->host->can_queue = acb->maxOutstanding;
2915 return rtn;
2916 }
2917
2918 static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
2919 struct CommandControlBlock *poll_ccb)
2920 {
2921 struct MessageUnit_A __iomem *reg = acb->pmuA;
2922 struct CommandControlBlock *ccb;
2923 struct ARCMSR_CDB *arcmsr_cdb;
2924 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
2925 int rtn;
2926 bool error;
2927 polling_hba_ccb_retry:
2928 poll_count++;
2929 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
2930 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2931 while (1) {
2932 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
2933 if (poll_ccb_done){
2934 rtn = SUCCESS;
2935 break;
2936 }else {
2937 msleep(25);
2938 if (poll_count > 100){
2939 rtn = FAILED;
2940 break;
2941 }
2942 goto polling_hba_ccb_retry;
2943 }
2944 }
2945 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2946 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
2947 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
2948 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2949 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2950 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2951 " poll command abort successfully \n"
2952 , acb->host->host_no
2953 , ccb->pcmd->device->id
2954 , (u32)ccb->pcmd->device->lun
2955 , ccb);
2956 ccb->pcmd->result = DID_ABORT << 16;
2957 arcmsr_ccb_complete(ccb);
2958 continue;
2959 }
2960 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2961 " command done ccb = '0x%p'"
2962 "ccboutstandingcount = %d \n"
2963 , acb->host->host_no
2964 , ccb
2965 , atomic_read(&acb->ccboutstandingcount));
2966 continue;
2967 }
2968 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2969 arcmsr_report_ccb_state(acb, ccb, error);
2970 }
2971 return rtn;
2972 }
2973
2974 static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
2975 struct CommandControlBlock *poll_ccb)
2976 {
2977 struct MessageUnit_B *reg = acb->pmuB;
2978 struct ARCMSR_CDB *arcmsr_cdb;
2979 struct CommandControlBlock *ccb;
2980 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
2981 int index, rtn;
2982 bool error;
2983 polling_hbb_ccb_retry:
2984
2985 poll_count++;
2986 /* clear doorbell interrupt */
2987 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2988 while(1){
2989 index = reg->doneq_index;
2990 flag_ccb = reg->done_qbuffer[index];
2991 if (flag_ccb == 0) {
2992 if (poll_ccb_done){
2993 rtn = SUCCESS;
2994 break;
2995 }else {
2996 msleep(25);
2997 if (poll_count > 100){
2998 rtn = FAILED;
2999 break;
3000 }
3001 goto polling_hbb_ccb_retry;
3002 }
3003 }
3004 reg->done_qbuffer[index] = 0;
3005 index++;
3006 /*if last index number set it to 0 */
3007 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3008 reg->doneq_index = index;
3009 /* check if command done with no error*/
3010 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
3011 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3012 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
3013 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3014 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3015 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3016 " poll command abort successfully \n"
3017 ,acb->host->host_no
3018 ,ccb->pcmd->device->id
3019 ,(u32)ccb->pcmd->device->lun
3020 ,ccb);
3021 ccb->pcmd->result = DID_ABORT << 16;
3022 arcmsr_ccb_complete(ccb);
3023 continue;
3024 }
3025 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3026 " command done ccb = '0x%p'"
3027 "ccboutstandingcount = %d \n"
3028 , acb->host->host_no
3029 , ccb
3030 , atomic_read(&acb->ccboutstandingcount));
3031 continue;
3032 }
3033 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3034 arcmsr_report_ccb_state(acb, ccb, error);
3035 }
3036 return rtn;
3037 }
3038
3039 static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3040 struct CommandControlBlock *poll_ccb)
3041 {
3042 struct MessageUnit_C __iomem *reg = acb->pmuC;
3043 uint32_t flag_ccb, ccb_cdb_phy;
3044 struct ARCMSR_CDB *arcmsr_cdb;
3045 bool error;
3046 struct CommandControlBlock *pCCB;
3047 uint32_t poll_ccb_done = 0, poll_count = 0;
3048 int rtn;
3049 polling_hbc_ccb_retry:
3050 poll_count++;
3051 while (1) {
3052 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3053 if (poll_ccb_done) {
3054 rtn = SUCCESS;
3055 break;
3056 } else {
3057 msleep(25);
3058 if (poll_count > 100) {
3059 rtn = FAILED;
3060 break;
3061 }
3062 goto polling_hbc_ccb_retry;
3063 }
3064 }
3065 flag_ccb = readl(&reg->outbound_queueport_low);
3066 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3067 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
3068 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3069 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3070 /* check ifcommand done with no error*/
3071 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3072 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3073 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3074 " poll command abort successfully \n"
3075 , acb->host->host_no
3076 , pCCB->pcmd->device->id
3077 , (u32)pCCB->pcmd->device->lun
3078 , pCCB);
3079 pCCB->pcmd->result = DID_ABORT << 16;
3080 arcmsr_ccb_complete(pCCB);
3081 continue;
3082 }
3083 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3084 " command done ccb = '0x%p'"
3085 "ccboutstandingcount = %d \n"
3086 , acb->host->host_no
3087 , pCCB
3088 , atomic_read(&acb->ccboutstandingcount));
3089 continue;
3090 }
3091 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3092 arcmsr_report_ccb_state(acb, pCCB, error);
3093 }
3094 return rtn;
3095 }
3096
3097 static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3098 struct CommandControlBlock *poll_ccb)
3099 {
3100 bool error;
3101 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
3102 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
3103 unsigned long flags;
3104 struct ARCMSR_CDB *arcmsr_cdb;
3105 struct CommandControlBlock *pCCB;
3106 struct MessageUnit_D *pmu = acb->pmuD;
3107
3108 polling_hbaD_ccb_retry:
3109 poll_count++;
3110 while (1) {
3111 spin_lock_irqsave(&acb->doneq_lock, flags);
3112 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3113 doneq_index = pmu->doneq_index;
3114 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3115 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3116 if (poll_ccb_done) {
3117 rtn = SUCCESS;
3118 break;
3119 } else {
3120 msleep(25);
3121 if (poll_count > 40) {
3122 rtn = FAILED;
3123 break;
3124 }
3125 goto polling_hbaD_ccb_retry;
3126 }
3127 }
3128 toggle = doneq_index & 0x4000;
3129 index_stripped = (doneq_index & 0xFFF) + 1;
3130 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3131 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3132 ((toggle ^ 0x4000) + 1);
3133 doneq_index = pmu->doneq_index;
3134 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3135 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3136 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3137 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3138 ccb_cdb_phy);
3139 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3140 arcmsr_cdb);
3141 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3142 if ((pCCB->acb != acb) ||
3143 (pCCB->startdone != ARCMSR_CCB_START)) {
3144 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3145 pr_notice("arcmsr%d: scsi id = %d "
3146 "lun = %d ccb = '0x%p' poll command "
3147 "abort successfully\n"
3148 , acb->host->host_no
3149 , pCCB->pcmd->device->id
3150 , (u32)pCCB->pcmd->device->lun
3151 , pCCB);
3152 pCCB->pcmd->result = DID_ABORT << 16;
3153 arcmsr_ccb_complete(pCCB);
3154 continue;
3155 }
3156 pr_notice("arcmsr%d: polling an illegal "
3157 "ccb command done ccb = '0x%p' "
3158 "ccboutstandingcount = %d\n"
3159 , acb->host->host_no
3160 , pCCB
3161 , atomic_read(&acb->ccboutstandingcount));
3162 continue;
3163 }
3164 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3165 ? true : false;
3166 arcmsr_report_ccb_state(acb, pCCB, error);
3167 }
3168 return rtn;
3169 }
3170
3171 static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
3172 struct CommandControlBlock *poll_ccb)
3173 {
3174 int rtn = 0;
3175 switch (acb->adapter_type) {
3176
3177 case ACB_ADAPTER_TYPE_A: {
3178 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
3179 }
3180 break;
3181
3182 case ACB_ADAPTER_TYPE_B: {
3183 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
3184 }
3185 break;
3186 case ACB_ADAPTER_TYPE_C: {
3187 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
3188 }
3189 break;
3190 case ACB_ADAPTER_TYPE_D:
3191 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3192 break;
3193 }
3194 return rtn;
3195 }
3196
3197 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3198 {
3199 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
3200 dma_addr_t dma_coherent_handle;
3201
3202 /*
3203 ********************************************************************
3204 ** here we need to tell iop 331 our freeccb.HighPart
3205 ** if freeccb.HighPart is not zero
3206 ********************************************************************
3207 */
3208 switch (acb->adapter_type) {
3209 case ACB_ADAPTER_TYPE_B:
3210 case ACB_ADAPTER_TYPE_D:
3211 dma_coherent_handle = acb->dma_coherent_handle2;
3212 break;
3213 default:
3214 dma_coherent_handle = acb->dma_coherent_handle;
3215 break;
3216 }
3217 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
3218 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
3219 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
3220 /*
3221 ***********************************************************************
3222 ** if adapter type B, set window of "post command Q"
3223 ***********************************************************************
3224 */
3225 switch (acb->adapter_type) {
3226
3227 case ACB_ADAPTER_TYPE_A: {
3228 if (cdb_phyaddr_hi32 != 0) {
3229 struct MessageUnit_A __iomem *reg = acb->pmuA;
3230 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
3231 &reg->message_rwbuffer[0]);
3232 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
3233 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
3234 &reg->inbound_msgaddr0);
3235 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3236 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
3237 part physical address timeout\n",
3238 acb->host->host_no);
3239 return 1;
3240 }
3241 }
3242 }
3243 break;
3244
3245 case ACB_ADAPTER_TYPE_B: {
3246 uint32_t __iomem *rwbuffer;
3247
3248 struct MessageUnit_B *reg = acb->pmuB;
3249 reg->postq_index = 0;
3250 reg->doneq_index = 0;
3251 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
3252 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3253 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
3254 acb->host->host_no);
3255 return 1;
3256 }
3257 rwbuffer = reg->message_rwbuffer;
3258 /* driver "set config" signature */
3259 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3260 /* normal should be zero */
3261 writel(cdb_phyaddr_hi32, rwbuffer++);
3262 /* postQ size (256 + 8)*4 */
3263 writel(cdb_phyaddr, rwbuffer++);
3264 /* doneQ size (256 + 8)*4 */
3265 writel(cdb_phyaddr + 1056, rwbuffer++);
3266 /* ccb maxQ size must be --> [(256 + 8)*4]*/
3267 writel(1056, rwbuffer);
3268
3269 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
3270 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3271 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3272 timeout \n",acb->host->host_no);
3273 return 1;
3274 }
3275 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3276 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3277 pr_err("arcmsr%d: can't set driver mode.\n",
3278 acb->host->host_no);
3279 return 1;
3280 }
3281 }
3282 break;
3283 case ACB_ADAPTER_TYPE_C: {
3284 if (cdb_phyaddr_hi32 != 0) {
3285 struct MessageUnit_C __iomem *reg = acb->pmuC;
3286
3287 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
3288 acb->adapter_index, cdb_phyaddr_hi32);
3289 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
3290 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
3291 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
3292 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3293 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
3294 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3295 timeout \n", acb->host->host_no);
3296 return 1;
3297 }
3298 }
3299 }
3300 break;
3301 case ACB_ADAPTER_TYPE_D: {
3302 uint32_t __iomem *rwbuffer;
3303 struct MessageUnit_D *reg = acb->pmuD;
3304 reg->postq_index = 0;
3305 reg->doneq_index = 0;
3306 rwbuffer = reg->msgcode_rwbuffer;
3307 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3308 writel(cdb_phyaddr_hi32, rwbuffer++);
3309 writel(cdb_phyaddr, rwbuffer++);
3310 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
3311 sizeof(struct InBound_SRB)), rwbuffer++);
3312 writel(0x100, rwbuffer);
3313 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
3314 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3315 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
3316 acb->host->host_no);
3317 return 1;
3318 }
3319 }
3320 break;
3321 }
3322 return 0;
3323 }
3324
3325 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
3326 {
3327 uint32_t firmware_state = 0;
3328 switch (acb->adapter_type) {
3329
3330 case ACB_ADAPTER_TYPE_A: {
3331 struct MessageUnit_A __iomem *reg = acb->pmuA;
3332 do {
3333 firmware_state = readl(&reg->outbound_msgaddr1);
3334 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
3335 }
3336 break;
3337
3338 case ACB_ADAPTER_TYPE_B: {
3339 struct MessageUnit_B *reg = acb->pmuB;
3340 do {
3341 firmware_state = readl(reg->iop2drv_doorbell);
3342 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
3343 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
3344 }
3345 break;
3346 case ACB_ADAPTER_TYPE_C: {
3347 struct MessageUnit_C __iomem *reg = acb->pmuC;
3348 do {
3349 firmware_state = readl(&reg->outbound_msgaddr1);
3350 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
3351 }
3352 break;
3353 case ACB_ADAPTER_TYPE_D: {
3354 struct MessageUnit_D *reg = acb->pmuD;
3355 do {
3356 firmware_state = readl(reg->outbound_msgaddr1);
3357 } while ((firmware_state &
3358 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
3359 }
3360 break;
3361 }
3362 }
3363
3364 static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb)
3365 {
3366 struct MessageUnit_A __iomem *reg = acb->pmuA;
3367 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
3368 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3369 return;
3370 } else {
3371 acb->fw_flag = FW_NORMAL;
3372 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
3373 atomic_set(&acb->rq_map_token, 16);
3374 }
3375 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
3376 if (atomic_dec_and_test(&acb->rq_map_token)) {
3377 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3378 return;
3379 }
3380 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3381 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3382 }
3383 return;
3384 }
3385
3386 static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb)
3387 {
3388 struct MessageUnit_B *reg = acb->pmuB;
3389 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
3390 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3391 return;
3392 } else {
3393 acb->fw_flag = FW_NORMAL;
3394 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
3395 atomic_set(&acb->rq_map_token, 16);
3396 }
3397 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
3398 if (atomic_dec_and_test(&acb->rq_map_token)) {
3399 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3400 return;
3401 }
3402 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3403 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3404 }
3405 return;
3406 }
3407
3408 static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb)
3409 {
3410 struct MessageUnit_C __iomem *reg = acb->pmuC;
3411 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
3412 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3413 return;
3414 } else {
3415 acb->fw_flag = FW_NORMAL;
3416 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
3417 atomic_set(&acb->rq_map_token, 16);
3418 }
3419 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
3420 if (atomic_dec_and_test(&acb->rq_map_token)) {
3421 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3422 return;
3423 }
3424 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3425 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3426 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3427 }
3428 return;
3429 }
3430
3431 static void arcmsr_hbaD_request_device_map(struct AdapterControlBlock *acb)
3432 {
3433 struct MessageUnit_D *reg = acb->pmuD;
3434
3435 if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
3436 ((acb->acb_flags & ACB_F_BUS_RESET) != 0) ||
3437 ((acb->acb_flags & ACB_F_ABORT) != 0)) {
3438 mod_timer(&acb->eternal_timer,
3439 jiffies + msecs_to_jiffies(6 * HZ));
3440 } else {
3441 acb->fw_flag = FW_NORMAL;
3442 if (atomic_read(&acb->ante_token_value) ==
3443 atomic_read(&acb->rq_map_token)) {
3444 atomic_set(&acb->rq_map_token, 16);
3445 }
3446 atomic_set(&acb->ante_token_value,
3447 atomic_read(&acb->rq_map_token));
3448 if (atomic_dec_and_test(&acb->rq_map_token)) {
3449 mod_timer(&acb->eternal_timer, jiffies +
3450 msecs_to_jiffies(6 * HZ));
3451 return;
3452 }
3453 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG,
3454 reg->inbound_msgaddr0);
3455 mod_timer(&acb->eternal_timer, jiffies +
3456 msecs_to_jiffies(6 * HZ));
3457 }
3458 }
3459
3460 static void arcmsr_request_device_map(unsigned long pacb)
3461 {
3462 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
3463 switch (acb->adapter_type) {
3464 case ACB_ADAPTER_TYPE_A: {
3465 arcmsr_hbaA_request_device_map(acb);
3466 }
3467 break;
3468 case ACB_ADAPTER_TYPE_B: {
3469 arcmsr_hbaB_request_device_map(acb);
3470 }
3471 break;
3472 case ACB_ADAPTER_TYPE_C: {
3473 arcmsr_hbaC_request_device_map(acb);
3474 }
3475 break;
3476 case ACB_ADAPTER_TYPE_D:
3477 arcmsr_hbaD_request_device_map(acb);
3478 break;
3479 }
3480 }
3481
3482 static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
3483 {
3484 struct MessageUnit_A __iomem *reg = acb->pmuA;
3485 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3486 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
3487 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3488 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3489 rebulid' timeout \n", acb->host->host_no);
3490 }
3491 }
3492
3493 static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
3494 {
3495 struct MessageUnit_B *reg = acb->pmuB;
3496 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3497 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
3498 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3499 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3500 rebulid' timeout \n",acb->host->host_no);
3501 }
3502 }
3503
3504 static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
3505 {
3506 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
3507 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3508 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
3509 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
3510 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
3511 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3512 rebulid' timeout \n", pACB->host->host_no);
3513 }
3514 return;
3515 }
3516
3517 static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
3518 {
3519 struct MessageUnit_D *pmu = pACB->pmuD;
3520
3521 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3522 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
3523 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
3524 pr_notice("arcmsr%d: wait 'start adapter "
3525 "background rebulid' timeout\n", pACB->host->host_no);
3526 }
3527 }
3528
3529 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3530 {
3531 switch (acb->adapter_type) {
3532 case ACB_ADAPTER_TYPE_A:
3533 arcmsr_hbaA_start_bgrb(acb);
3534 break;
3535 case ACB_ADAPTER_TYPE_B:
3536 arcmsr_hbaB_start_bgrb(acb);
3537 break;
3538 case ACB_ADAPTER_TYPE_C:
3539 arcmsr_hbaC_start_bgrb(acb);
3540 break;
3541 case ACB_ADAPTER_TYPE_D:
3542 arcmsr_hbaD_start_bgrb(acb);
3543 break;
3544 }
3545 }
3546
3547 static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
3548 {
3549 switch (acb->adapter_type) {
3550 case ACB_ADAPTER_TYPE_A: {
3551 struct MessageUnit_A __iomem *reg = acb->pmuA;
3552 uint32_t outbound_doorbell;
3553 /* empty doorbell Qbuffer if door bell ringed */
3554 outbound_doorbell = readl(&reg->outbound_doorbell);
3555 /*clear doorbell interrupt */
3556 writel(outbound_doorbell, &reg->outbound_doorbell);
3557 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
3558 }
3559 break;
3560
3561 case ACB_ADAPTER_TYPE_B: {
3562 struct MessageUnit_B *reg = acb->pmuB;
3563 /*clear interrupt and message state*/
3564 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
3565 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
3566 /* let IOP know data has been read */
3567 }
3568 break;
3569 case ACB_ADAPTER_TYPE_C: {
3570 struct MessageUnit_C __iomem *reg = acb->pmuC;
3571 uint32_t outbound_doorbell, i;
3572 /* empty doorbell Qbuffer if door bell ringed */
3573 outbound_doorbell = readl(&reg->outbound_doorbell);
3574 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
3575 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
3576 for (i = 0; i < 200; i++) {
3577 msleep(20);
3578 outbound_doorbell = readl(&reg->outbound_doorbell);
3579 if (outbound_doorbell &
3580 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
3581 writel(outbound_doorbell,
3582 &reg->outbound_doorbell_clear);
3583 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
3584 &reg->inbound_doorbell);
3585 } else
3586 break;
3587 }
3588 }
3589 break;
3590 case ACB_ADAPTER_TYPE_D: {
3591 struct MessageUnit_D *reg = acb->pmuD;
3592 uint32_t outbound_doorbell, i;
3593 /* empty doorbell Qbuffer if door bell ringed */
3594 outbound_doorbell = readl(reg->outbound_doorbell);
3595 writel(outbound_doorbell, reg->outbound_doorbell);
3596 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
3597 reg->inbound_doorbell);
3598 for (i = 0; i < 200; i++) {
3599 msleep(20);
3600 outbound_doorbell = readl(reg->outbound_doorbell);
3601 if (outbound_doorbell &
3602 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
3603 writel(outbound_doorbell,
3604 reg->outbound_doorbell);
3605 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
3606 reg->inbound_doorbell);
3607 } else
3608 break;
3609 }
3610 }
3611 break;
3612 }
3613 }
3614
3615 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3616 {
3617 switch (acb->adapter_type) {
3618 case ACB_ADAPTER_TYPE_A:
3619 return;
3620 case ACB_ADAPTER_TYPE_B:
3621 {
3622 struct MessageUnit_B *reg = acb->pmuB;
3623 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
3624 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3625 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
3626 return;
3627 }
3628 }
3629 break;
3630 case ACB_ADAPTER_TYPE_C:
3631 return;
3632 }
3633 return;
3634 }
3635
3636 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
3637 {
3638 uint8_t value[64];
3639 int i, count = 0;
3640 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
3641 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
3642 struct MessageUnit_D *pmuD = acb->pmuD;
3643
3644 /* backup pci config data */
3645 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
3646 for (i = 0; i < 64; i++) {
3647 pci_read_config_byte(acb->pdev, i, &value[i]);
3648 }
3649 /* hardware reset signal */
3650 if ((acb->dev_id == 0x1680)) {
3651 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
3652 } else if ((acb->dev_id == 0x1880)) {
3653 do {
3654 count++;
3655 writel(0xF, &pmuC->write_sequence);
3656 writel(0x4, &pmuC->write_sequence);
3657 writel(0xB, &pmuC->write_sequence);
3658 writel(0x2, &pmuC->write_sequence);
3659 writel(0x7, &pmuC->write_sequence);
3660 writel(0xD, &pmuC->write_sequence);
3661 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
3662 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
3663 } else if ((acb->dev_id == 0x1214)) {
3664 writel(0x20, pmuD->reset_request);
3665 } else {
3666 pci_write_config_byte(acb->pdev, 0x84, 0x20);
3667 }
3668 msleep(2000);
3669 /* write back pci config data */
3670 for (i = 0; i < 64; i++) {
3671 pci_write_config_byte(acb->pdev, i, value[i]);
3672 }
3673 msleep(1000);
3674 return;
3675 }
3676 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3677 {
3678 uint32_t intmask_org;
3679 /* disable all outbound interrupt */
3680 intmask_org = arcmsr_disable_outbound_ints(acb);
3681 arcmsr_wait_firmware_ready(acb);
3682 arcmsr_iop_confirm(acb);
3683 /*start background rebuild*/
3684 arcmsr_start_adapter_bgrb(acb);
3685 /* empty doorbell Qbuffer if door bell ringed */
3686 arcmsr_clear_doorbell_queue_buffer(acb);
3687 arcmsr_enable_eoi_mode(acb);
3688 /* enable outbound Post Queue,outbound doorbell Interrupt */
3689 arcmsr_enable_outbound_ints(acb, intmask_org);
3690 acb->acb_flags |= ACB_F_IOP_INITED;
3691 }
3692
3693 static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
3694 {
3695 struct CommandControlBlock *ccb;
3696 uint32_t intmask_org;
3697 uint8_t rtnval = 0x00;
3698 int i = 0;
3699 unsigned long flags;
3700
3701 if (atomic_read(&acb->ccboutstandingcount) != 0) {
3702 /* disable all outbound interrupt */
3703 intmask_org = arcmsr_disable_outbound_ints(acb);
3704 /* talk to iop 331 outstanding command aborted */
3705 rtnval = arcmsr_abort_allcmd(acb);
3706 /* clear all outbound posted Q */
3707 arcmsr_done4abort_postqueue(acb);
3708 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3709 ccb = acb->pccb_pool[i];
3710 if (ccb->startdone == ARCMSR_CCB_START) {
3711 scsi_dma_unmap(ccb->pcmd);
3712 ccb->startdone = ARCMSR_CCB_DONE;
3713 ccb->ccb_flags = 0;
3714 spin_lock_irqsave(&acb->ccblist_lock, flags);
3715 list_add_tail(&ccb->list, &acb->ccb_free_list);
3716 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
3717 }
3718 }
3719 atomic_set(&acb->ccboutstandingcount, 0);
3720 /* enable all outbound interrupt */
3721 arcmsr_enable_outbound_ints(acb, intmask_org);
3722 return rtnval;
3723 }
3724 return rtnval;
3725 }
3726
3727 static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
3728 {
3729 struct AdapterControlBlock *acb;
3730 uint32_t intmask_org, outbound_doorbell;
3731 int retry_count = 0;
3732 int rtn = FAILED;
3733 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
3734 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
3735 acb->num_resets++;
3736
3737 switch(acb->adapter_type){
3738 case ACB_ADAPTER_TYPE_A:{
3739 if (acb->acb_flags & ACB_F_BUS_RESET){
3740 long timeout;
3741 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3742 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3743 if (timeout) {
3744 return SUCCESS;
3745 }
3746 }
3747 acb->acb_flags |= ACB_F_BUS_RESET;
3748 if (!arcmsr_iop_reset(acb)) {
3749 struct MessageUnit_A __iomem *reg;
3750 reg = acb->pmuA;
3751 arcmsr_hardware_reset(acb);
3752 acb->acb_flags &= ~ACB_F_IOP_INITED;
3753 sleep_again:
3754 ssleep(ARCMSR_SLEEPTIME);
3755 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
3756 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3757 if (retry_count > ARCMSR_RETRYCOUNT) {
3758 acb->fw_flag = FW_DEADLOCK;
3759 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
3760 return FAILED;
3761 }
3762 retry_count++;
3763 goto sleep_again;
3764 }
3765 acb->acb_flags |= ACB_F_IOP_INITED;
3766 /* disable all outbound interrupt */
3767 intmask_org = arcmsr_disable_outbound_ints(acb);
3768 arcmsr_get_firmware_spec(acb);
3769 arcmsr_start_adapter_bgrb(acb);
3770 /* clear Qbuffer if door bell ringed */
3771 outbound_doorbell = readl(&reg->outbound_doorbell);
3772 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
3773 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
3774 /* enable outbound Post Queue,outbound doorbell Interrupt */
3775 arcmsr_enable_outbound_ints(acb, intmask_org);
3776 atomic_set(&acb->rq_map_token, 16);
3777 atomic_set(&acb->ante_token_value, 16);
3778 acb->fw_flag = FW_NORMAL;
3779 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3780 acb->acb_flags &= ~ACB_F_BUS_RESET;
3781 rtn = SUCCESS;
3782 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3783 } else {
3784 acb->acb_flags &= ~ACB_F_BUS_RESET;
3785 atomic_set(&acb->rq_map_token, 16);
3786 atomic_set(&acb->ante_token_value, 16);
3787 acb->fw_flag = FW_NORMAL;
3788 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3789 rtn = SUCCESS;
3790 }
3791 break;
3792 }
3793 case ACB_ADAPTER_TYPE_B:{
3794 acb->acb_flags |= ACB_F_BUS_RESET;
3795 if (!arcmsr_iop_reset(acb)) {
3796 acb->acb_flags &= ~ACB_F_BUS_RESET;
3797 rtn = FAILED;
3798 } else {
3799 acb->acb_flags &= ~ACB_F_BUS_RESET;
3800 atomic_set(&acb->rq_map_token, 16);
3801 atomic_set(&acb->ante_token_value, 16);
3802 acb->fw_flag = FW_NORMAL;
3803 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3804 rtn = SUCCESS;
3805 }
3806 break;
3807 }
3808 case ACB_ADAPTER_TYPE_C:{
3809 if (acb->acb_flags & ACB_F_BUS_RESET) {
3810 long timeout;
3811 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3812 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3813 if (timeout) {
3814 return SUCCESS;
3815 }
3816 }
3817 acb->acb_flags |= ACB_F_BUS_RESET;
3818 if (!arcmsr_iop_reset(acb)) {
3819 struct MessageUnit_C __iomem *reg;
3820 reg = acb->pmuC;
3821 arcmsr_hardware_reset(acb);
3822 acb->acb_flags &= ~ACB_F_IOP_INITED;
3823 sleep:
3824 ssleep(ARCMSR_SLEEPTIME);
3825 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
3826 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3827 if (retry_count > ARCMSR_RETRYCOUNT) {
3828 acb->fw_flag = FW_DEADLOCK;
3829 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
3830 return FAILED;
3831 }
3832 retry_count++;
3833 goto sleep;
3834 }
3835 acb->acb_flags |= ACB_F_IOP_INITED;
3836 /* disable all outbound interrupt */
3837 intmask_org = arcmsr_disable_outbound_ints(acb);
3838 arcmsr_get_firmware_spec(acb);
3839 arcmsr_start_adapter_bgrb(acb);
3840 /* clear Qbuffer if door bell ringed */
3841 arcmsr_clear_doorbell_queue_buffer(acb);
3842 /* enable outbound Post Queue,outbound doorbell Interrupt */
3843 arcmsr_enable_outbound_ints(acb, intmask_org);
3844 atomic_set(&acb->rq_map_token, 16);
3845 atomic_set(&acb->ante_token_value, 16);
3846 acb->fw_flag = FW_NORMAL;
3847 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3848 acb->acb_flags &= ~ACB_F_BUS_RESET;
3849 rtn = SUCCESS;
3850 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3851 } else {
3852 acb->acb_flags &= ~ACB_F_BUS_RESET;
3853 atomic_set(&acb->rq_map_token, 16);
3854 atomic_set(&acb->ante_token_value, 16);
3855 acb->fw_flag = FW_NORMAL;
3856 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3857 rtn = SUCCESS;
3858 }
3859 break;
3860 }
3861 case ACB_ADAPTER_TYPE_D: {
3862 if (acb->acb_flags & ACB_F_BUS_RESET) {
3863 long timeout;
3864 pr_notice("arcmsr: there is an bus reset"
3865 " eh proceeding.......\n");
3866 timeout = wait_event_timeout(wait_q, (acb->acb_flags
3867 & ACB_F_BUS_RESET) == 0, 220 * HZ);
3868 if (timeout)
3869 return SUCCESS;
3870 }
3871 acb->acb_flags |= ACB_F_BUS_RESET;
3872 if (!arcmsr_iop_reset(acb)) {
3873 struct MessageUnit_D *reg;
3874 reg = acb->pmuD;
3875 arcmsr_hardware_reset(acb);
3876 acb->acb_flags &= ~ACB_F_IOP_INITED;
3877 nap:
3878 ssleep(ARCMSR_SLEEPTIME);
3879 if ((readl(reg->sample_at_reset) & 0x80) != 0) {
3880 pr_err("arcmsr%d: waiting for "
3881 "hw bus reset return, retry=%d\n",
3882 acb->host->host_no, retry_count);
3883 if (retry_count > ARCMSR_RETRYCOUNT) {
3884 acb->fw_flag = FW_DEADLOCK;
3885 pr_err("arcmsr%d: waiting for hw bus"
3886 " reset return, "
3887 "RETRY TERMINATED!!\n",
3888 acb->host->host_no);
3889 return FAILED;
3890 }
3891 retry_count++;
3892 goto nap;
3893 }
3894 acb->acb_flags |= ACB_F_IOP_INITED;
3895 /* disable all outbound interrupt */
3896 intmask_org = arcmsr_disable_outbound_ints(acb);
3897 arcmsr_get_firmware_spec(acb);
3898 arcmsr_start_adapter_bgrb(acb);
3899 arcmsr_clear_doorbell_queue_buffer(acb);
3900 arcmsr_enable_outbound_ints(acb, intmask_org);
3901 atomic_set(&acb->rq_map_token, 16);
3902 atomic_set(&acb->ante_token_value, 16);
3903 acb->fw_flag = FW_NORMAL;
3904 mod_timer(&acb->eternal_timer,
3905 jiffies + msecs_to_jiffies(6 * HZ));
3906 acb->acb_flags &= ~ACB_F_BUS_RESET;
3907 rtn = SUCCESS;
3908 pr_err("arcmsr: scsi bus reset "
3909 "eh returns with success\n");
3910 } else {
3911 acb->acb_flags &= ~ACB_F_BUS_RESET;
3912 atomic_set(&acb->rq_map_token, 16);
3913 atomic_set(&acb->ante_token_value, 16);
3914 acb->fw_flag = FW_NORMAL;
3915 mod_timer(&acb->eternal_timer,
3916 jiffies + msecs_to_jiffies(6 * HZ));
3917 rtn = SUCCESS;
3918 }
3919 break;
3920 }
3921 }
3922 return rtn;
3923 }
3924
3925 static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
3926 struct CommandControlBlock *ccb)
3927 {
3928 int rtn;
3929 rtn = arcmsr_polling_ccbdone(acb, ccb);
3930 return rtn;
3931 }
3932
3933 static int arcmsr_abort(struct scsi_cmnd *cmd)
3934 {
3935 struct AdapterControlBlock *acb =
3936 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3937 int i = 0;
3938 int rtn = FAILED;
3939 uint32_t intmask_org;
3940
3941 printk(KERN_NOTICE
3942 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
3943 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
3944 acb->acb_flags |= ACB_F_ABORT;
3945 acb->num_aborts++;
3946 /*
3947 ************************************************
3948 ** the all interrupt service routine is locked
3949 ** we need to handle it as soon as possible and exit
3950 ************************************************
3951 */
3952 if (!atomic_read(&acb->ccboutstandingcount)) {
3953 acb->acb_flags &= ~ACB_F_ABORT;
3954 return rtn;
3955 }
3956
3957 intmask_org = arcmsr_disable_outbound_ints(acb);
3958 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3959 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3960 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
3961 ccb->startdone = ARCMSR_CCB_ABORTED;
3962 rtn = arcmsr_abort_one_cmd(acb, ccb);
3963 break;
3964 }
3965 }
3966 acb->acb_flags &= ~ACB_F_ABORT;
3967 arcmsr_enable_outbound_ints(acb, intmask_org);
3968 return rtn;
3969 }
3970
3971 static const char *arcmsr_info(struct Scsi_Host *host)
3972 {
3973 struct AdapterControlBlock *acb =
3974 (struct AdapterControlBlock *) host->hostdata;
3975 static char buf[256];
3976 char *type;
3977 int raid6 = 1;
3978 switch (acb->pdev->device) {
3979 case PCI_DEVICE_ID_ARECA_1110:
3980 case PCI_DEVICE_ID_ARECA_1200:
3981 case PCI_DEVICE_ID_ARECA_1202:
3982 case PCI_DEVICE_ID_ARECA_1210:
3983 raid6 = 0;
3984 /*FALLTHRU*/
3985 case PCI_DEVICE_ID_ARECA_1120:
3986 case PCI_DEVICE_ID_ARECA_1130:
3987 case PCI_DEVICE_ID_ARECA_1160:
3988 case PCI_DEVICE_ID_ARECA_1170:
3989 case PCI_DEVICE_ID_ARECA_1201:
3990 case PCI_DEVICE_ID_ARECA_1203:
3991 case PCI_DEVICE_ID_ARECA_1220:
3992 case PCI_DEVICE_ID_ARECA_1230:
3993 case PCI_DEVICE_ID_ARECA_1260:
3994 case PCI_DEVICE_ID_ARECA_1270:
3995 case PCI_DEVICE_ID_ARECA_1280:
3996 type = "SATA";
3997 break;
3998 case PCI_DEVICE_ID_ARECA_1214:
3999 case PCI_DEVICE_ID_ARECA_1380:
4000 case PCI_DEVICE_ID_ARECA_1381:
4001 case PCI_DEVICE_ID_ARECA_1680:
4002 case PCI_DEVICE_ID_ARECA_1681:
4003 case PCI_DEVICE_ID_ARECA_1880:
4004 type = "SAS/SATA";
4005 break;
4006 default:
4007 type = "unknown";
4008 raid6 = 0;
4009 break;
4010 }
4011 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4012 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4013 return buf;
4014 }
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