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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF 0
251 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
253 #define PORT_DFX0 (PORT_BASE + 0x258)
254 #define LINK_DFX2 (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF 0
269 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF 0
272 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
273
274 #define AXI_CFG (0x5100)
275 #define AM_CFG_MAX_TRANS (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
277
278 #define AXI_MASTER_CFG_BASE (0x5000)
279 #define AM_CTRL_GLOBAL (0x0)
280 #define AM_CURR_TRANS_RETURN (0x150)
281
282 /* HW dma structures */
283 /* Delivery queue header */
284 /* dw0 */
285 #define CMD_HDR_ABORT_FLAG_OFF 0
286 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF 5
290 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF 6
292 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF 18
294 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF 27
296 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF 29
298 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
299 /* dw1 */
300 #define CMD_HDR_DIR_OFF 5
301 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF 7
303 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF 10
305 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF 11
307 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF 16
309 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
310 /* dw2 */
311 #define CMD_HDR_CFL_OFF 0
312 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF 10
314 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF 15
316 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF 24
318 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF 26
320 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
321 /* dw3 */
322 #define CMD_HDR_IPTT_OFF 0
323 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
324 /* dw6 */
325 #define CMD_HDR_DIF_SGL_LEN_OFF 0
326 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF 16
328 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF 16
330 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
331
332 /* Completion header */
333 /* dw0 */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF 12
339 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF 13
341 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
342 /* abort_stat */
343 #define STAT_IO_NOT_VALID 0x1
344 #define STAT_IO_NO_DEVICE 0x2
345 #define STAT_IO_COMPLETE 0x3
346 #define STAT_IO_ABORTED 0x4
347 /* dw1 */
348 #define CMPLT_HDR_IPTT_OFF 0
349 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF 16
351 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
352
353 /* ITCT header */
354 /* qw0 */
355 #define ITCT_HDR_DEV_TYPE_OFF 0
356 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF 2
358 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF 5
360 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF 9
362 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
364 #define ITCT_HDR_SMP_TIMEOUT_8US 1
365 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
366 250) /* 2ms */
367 #define ITCT_HDR_AWT_CONTINUE_OFF 25
368 #define ITCT_HDR_PORT_ID_OFF 28
369 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
370 /* qw2 */
371 #define ITCT_HDR_INLT_OFF 0
372 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF 16
374 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF 32
376 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF 48
378 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
379
380 #define HISI_SAS_FATAL_INT_NR 2
381
382 struct hisi_sas_complete_v2_hdr {
383 __le32 dw0;
384 __le32 dw1;
385 __le32 act;
386 __le32 dw3;
387 };
388
389 struct hisi_sas_err_record_v2 {
390 /* dw0 */
391 __le32 trans_tx_fail_type;
392
393 /* dw1 */
394 __le32 trans_rx_fail_type;
395
396 /* dw2 */
397 __le16 dma_tx_err_type;
398 __le16 sipc_rx_err_type;
399
400 /* dw3 */
401 __le32 dma_rx_err_type;
402 };
403
404 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
405 {
406 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
407 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
408 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
409 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
410 .reg = HGC_DQE_ECC_ADDR,
411 },
412 {
413 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
414 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
415 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
416 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
417 .reg = HGC_IOST_ECC_ADDR,
418 },
419 {
420 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
421 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
422 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
423 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
424 .reg = HGC_ITCT_ECC_ADDR,
425 },
426 {
427 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
428 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
429 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
430 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
431 .reg = HGC_LM_DFX_STATUS2,
432 },
433 {
434 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
435 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
436 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
437 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
438 .reg = HGC_LM_DFX_STATUS2,
439 },
440 {
441 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
442 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
443 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
444 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
445 .reg = HGC_CQE_ECC_ADDR,
446 },
447 {
448 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
449 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
450 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
451 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
452 .reg = HGC_RXM_DFX_STATUS14,
453 },
454 {
455 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
456 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
457 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
458 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
459 .reg = HGC_RXM_DFX_STATUS14,
460 },
461 {
462 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
463 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
464 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
465 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
466 .reg = HGC_RXM_DFX_STATUS14,
467 },
468 {
469 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
470 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
471 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
472 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
473 .reg = HGC_RXM_DFX_STATUS15,
474 },
475 };
476
477 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
478 {
479 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
480 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
481 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
482 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
483 .reg = HGC_DQE_ECC_ADDR,
484 },
485 {
486 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
487 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
488 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
489 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
490 .reg = HGC_IOST_ECC_ADDR,
491 },
492 {
493 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
494 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
495 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
496 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
497 .reg = HGC_ITCT_ECC_ADDR,
498 },
499 {
500 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
501 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
502 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
503 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
504 .reg = HGC_LM_DFX_STATUS2,
505 },
506 {
507 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
508 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
509 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
510 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
511 .reg = HGC_LM_DFX_STATUS2,
512 },
513 {
514 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
515 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
516 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
517 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
518 .reg = HGC_CQE_ECC_ADDR,
519 },
520 {
521 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
522 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
523 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
524 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
525 .reg = HGC_RXM_DFX_STATUS14,
526 },
527 {
528 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
529 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
530 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
531 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
532 .reg = HGC_RXM_DFX_STATUS14,
533 },
534 {
535 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
536 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
537 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
538 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
539 .reg = HGC_RXM_DFX_STATUS14,
540 },
541 {
542 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
543 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
544 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
545 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
546 .reg = HGC_RXM_DFX_STATUS15,
547 },
548 };
549
550 enum {
551 HISI_SAS_PHY_PHY_UPDOWN,
552 HISI_SAS_PHY_CHNL_INT,
553 HISI_SAS_PHY_INT_NR
554 };
555
556 enum {
557 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
558 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
559 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
560 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
561 DMA_RX_ERR_BASE = 0x60, /* dw3 */
562
563 /* trans tx*/
564 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
565 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
566 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
567 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
568 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
569 RESERVED0, /* 0x5 */
570 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
571 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
572 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
573 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
574 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
575 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
576 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
577 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
578 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
579 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
580 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
581 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
582 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
583 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
584 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
585 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
586 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
587 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
588 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
589 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
590 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
591 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
592 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
593 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
594 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
595 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
596 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
597 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
598 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
599
600 /* trans rx */
601 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
602 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
603 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
604 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
605 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
606 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
607 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
608 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
609 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
610 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
611 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
612 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
613 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
614 RESERVED1, /* 0x2b */
615 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
616 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
617 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
618 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
619 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
620 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
621 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
622 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
623 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
624 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
625 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
626 RESERVED2, /* 0x34 */
627 RESERVED3, /* 0x35 */
628 RESERVED4, /* 0x36 */
629 RESERVED5, /* 0x37 */
630 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
631 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
632 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
633 RESERVED6, /* 0x3b */
634 RESERVED7, /* 0x3c */
635 RESERVED8, /* 0x3d */
636 RESERVED9, /* 0x3e */
637 TRANS_RX_R_ERR, /* 0x3f */
638
639 /* dma tx */
640 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
641 DMA_TX_DIF_APP_ERR, /* 0x41 */
642 DMA_TX_DIF_RPP_ERR, /* 0x42 */
643 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
644 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
645 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
646 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
647 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
648 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
649 DMA_TX_RAM_ECC_ERR, /* 0x49 */
650 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
651 DMA_TX_MAX_ERR_CODE,
652
653 /* sipc rx */
654 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
655 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
656 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
657 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
658 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
659 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
660 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
661 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
662 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
663 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
664 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
665 SIPC_RX_MAX_ERR_CODE,
666
667 /* dma rx */
668 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
669 DMA_RX_DIF_APP_ERR, /* 0x61 */
670 DMA_RX_DIF_RPP_ERR, /* 0x62 */
671 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
672 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
673 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
674 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
675 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
676 RESERVED10, /* 0x68 */
677 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
678 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
679 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
680 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
681 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
682 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
683 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
684 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
685 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
686 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
687 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
688 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
689 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
690 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
691 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
692 DMA_RX_RAM_ECC_ERR, /* 0x78 */
693 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
694 DMA_RX_MAX_ERR_CODE,
695 };
696
697 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
698 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
699
700 #define DIR_NO_DATA 0
701 #define DIR_TO_INI 1
702 #define DIR_TO_DEVICE 2
703 #define DIR_RESERVED 3
704
705 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
706 err_phase == 0x4 || err_phase == 0x8 ||\
707 err_phase == 0x6 || err_phase == 0xa)
708 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
709 err_phase == 0x20 || err_phase == 0x40)
710
711 static void link_timeout_disable_link(struct timer_list *t);
712
713 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
714 {
715 void __iomem *regs = hisi_hba->regs + off;
716
717 return readl(regs);
718 }
719
720 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
721 {
722 void __iomem *regs = hisi_hba->regs + off;
723
724 return readl_relaxed(regs);
725 }
726
727 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
728 {
729 void __iomem *regs = hisi_hba->regs + off;
730
731 writel(val, regs);
732 }
733
734 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
735 u32 off, u32 val)
736 {
737 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
738
739 writel(val, regs);
740 }
741
742 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
743 int phy_no, u32 off)
744 {
745 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
746
747 return readl(regs);
748 }
749
750 /* This function needs to be protected from pre-emption. */
751 static int
752 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
753 struct domain_device *device)
754 {
755 int sata_dev = dev_is_sata(device);
756 void *bitmap = hisi_hba->slot_index_tags;
757 struct hisi_sas_device *sas_dev = device->lldd_dev;
758 int sata_idx = sas_dev->sata_idx;
759 int start, end;
760
761 if (!sata_dev) {
762 /*
763 * STP link SoC bug workaround: index starts from 1.
764 * additionally, we can only allocate odd IPTT(1~4095)
765 * for SAS/SMP device.
766 */
767 start = 1;
768 end = hisi_hba->slot_index_count;
769 } else {
770 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
771 return -EINVAL;
772
773 /*
774 * For SATA device: allocate even IPTT in this interval
775 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
776 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
777 * SoC bug workaround. So we ignore the first 32 even IPTTs.
778 */
779 start = 64 * (sata_idx + 1);
780 end = 64 * (sata_idx + 2);
781 }
782
783 while (1) {
784 start = find_next_zero_bit(bitmap,
785 hisi_hba->slot_index_count, start);
786 if (start >= end)
787 return -SAS_QUEUE_FULL;
788 /*
789 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
790 */
791 if (sata_dev ^ (start & 1))
792 break;
793 start++;
794 }
795
796 set_bit(start, bitmap);
797 *slot_idx = start;
798 return 0;
799 }
800
801 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
802 {
803 unsigned int index;
804 struct device *dev = hisi_hba->dev;
805 void *bitmap = hisi_hba->sata_dev_bitmap;
806
807 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
808 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
809 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
810 return false;
811 }
812
813 set_bit(index, bitmap);
814 *idx = index;
815 return true;
816 }
817
818
819 static struct
820 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
821 {
822 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
823 struct hisi_sas_device *sas_dev = NULL;
824 int i, sata_dev = dev_is_sata(device);
825 int sata_idx = -1;
826 unsigned long flags;
827
828 spin_lock_irqsave(&hisi_hba->lock, flags);
829
830 if (sata_dev)
831 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
832 goto out;
833
834 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
835 /*
836 * SATA device id bit0 should be 0
837 */
838 if (sata_dev && (i & 1))
839 continue;
840 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
841 int queue = i % hisi_hba->queue_count;
842 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
843
844 hisi_hba->devices[i].device_id = i;
845 sas_dev = &hisi_hba->devices[i];
846 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
847 sas_dev->dev_type = device->dev_type;
848 sas_dev->hisi_hba = hisi_hba;
849 sas_dev->sas_device = device;
850 sas_dev->sata_idx = sata_idx;
851 sas_dev->dq = dq;
852 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
853 break;
854 }
855 }
856
857 out:
858 spin_unlock_irqrestore(&hisi_hba->lock, flags);
859
860 return sas_dev;
861 }
862
863 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
864 {
865 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
866
867 cfg &= ~PHY_CFG_DC_OPT_MSK;
868 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
869 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
870 }
871
872 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
873 {
874 struct sas_identify_frame identify_frame;
875 u32 *identify_buffer;
876
877 memset(&identify_frame, 0, sizeof(identify_frame));
878 identify_frame.dev_type = SAS_END_DEVICE;
879 identify_frame.frame_type = 0;
880 identify_frame._un1 = 1;
881 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
882 identify_frame.target_bits = SAS_PROTOCOL_NONE;
883 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
884 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
885 identify_frame.phy_id = phy_no;
886 identify_buffer = (u32 *)(&identify_frame);
887
888 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
889 __swab32(identify_buffer[0]));
890 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
891 __swab32(identify_buffer[1]));
892 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
893 __swab32(identify_buffer[2]));
894 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
895 __swab32(identify_buffer[3]));
896 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
897 __swab32(identify_buffer[4]));
898 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
899 __swab32(identify_buffer[5]));
900 }
901
902 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
903 struct hisi_sas_device *sas_dev)
904 {
905 struct domain_device *device = sas_dev->sas_device;
906 struct device *dev = hisi_hba->dev;
907 u64 qw0, device_id = sas_dev->device_id;
908 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
909 struct domain_device *parent_dev = device->parent;
910 struct asd_sas_port *sas_port = device->port;
911 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
912
913 memset(itct, 0, sizeof(*itct));
914
915 /* qw0 */
916 qw0 = 0;
917 switch (sas_dev->dev_type) {
918 case SAS_END_DEVICE:
919 case SAS_EDGE_EXPANDER_DEVICE:
920 case SAS_FANOUT_EXPANDER_DEVICE:
921 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
922 break;
923 case SAS_SATA_DEV:
924 case SAS_SATA_PENDING:
925 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
926 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
927 else
928 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
929 break;
930 default:
931 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
932 sas_dev->dev_type);
933 }
934
935 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
936 (device->linkrate << ITCT_HDR_MCR_OFF) |
937 (1 << ITCT_HDR_VLN_OFF) |
938 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
939 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
940 (port->id << ITCT_HDR_PORT_ID_OFF));
941 itct->qw0 = cpu_to_le64(qw0);
942
943 /* qw1 */
944 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
945 itct->sas_addr = __swab64(itct->sas_addr);
946
947 /* qw2 */
948 if (!dev_is_sata(device))
949 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
950 (0x1ULL << ITCT_HDR_BITLT_OFF) |
951 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
952 (0x1ULL << ITCT_HDR_RTOLT_OFF));
953 }
954
955 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
956 struct hisi_sas_device *sas_dev)
957 {
958 DECLARE_COMPLETION_ONSTACK(completion);
959 u64 dev_id = sas_dev->device_id;
960 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
961 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
962 int i;
963
964 sas_dev->completion = &completion;
965
966 /* SoC bug workaround */
967 if (dev_is_sata(sas_dev->sas_device))
968 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
969
970 /* clear the itct interrupt state */
971 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
972 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
973 ENT_INT_SRC3_ITC_INT_MSK);
974
975 for (i = 0; i < 2; i++) {
976 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
977 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
978 wait_for_completion(sas_dev->completion);
979
980 memset(itct, 0, sizeof(struct hisi_sas_itct));
981 }
982 }
983
984 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
985 {
986 int i, reset_val;
987 u32 val;
988 unsigned long end_time;
989 struct device *dev = hisi_hba->dev;
990
991 /* The mask needs to be set depending on the number of phys */
992 if (hisi_hba->n_phy == 9)
993 reset_val = 0x1fffff;
994 else
995 reset_val = 0x7ffff;
996
997 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
998
999 /* Disable all of the PHYs */
1000 for (i = 0; i < hisi_hba->n_phy; i++) {
1001 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1002
1003 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1004 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1005 }
1006 udelay(50);
1007
1008 /* Ensure DMA tx & rx idle */
1009 for (i = 0; i < hisi_hba->n_phy; i++) {
1010 u32 dma_tx_status, dma_rx_status;
1011
1012 end_time = jiffies + msecs_to_jiffies(1000);
1013
1014 while (1) {
1015 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1016 DMA_TX_STATUS);
1017 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1018 DMA_RX_STATUS);
1019
1020 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1021 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1022 break;
1023
1024 msleep(20);
1025 if (time_after(jiffies, end_time))
1026 return -EIO;
1027 }
1028 }
1029
1030 /* Ensure axi bus idle */
1031 end_time = jiffies + msecs_to_jiffies(1000);
1032 while (1) {
1033 u32 axi_status =
1034 hisi_sas_read32(hisi_hba, AXI_CFG);
1035
1036 if (axi_status == 0)
1037 break;
1038
1039 msleep(20);
1040 if (time_after(jiffies, end_time))
1041 return -EIO;
1042 }
1043
1044 if (ACPI_HANDLE(dev)) {
1045 acpi_status s;
1046
1047 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1048 if (ACPI_FAILURE(s)) {
1049 dev_err(dev, "Reset failed\n");
1050 return -EIO;
1051 }
1052 } else if (hisi_hba->ctrl) {
1053 /* reset and disable clock*/
1054 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1055 reset_val);
1056 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1057 reset_val);
1058 msleep(1);
1059 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1060 if (reset_val != (val & reset_val)) {
1061 dev_err(dev, "SAS reset fail.\n");
1062 return -EIO;
1063 }
1064
1065 /* De-reset and enable clock*/
1066 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1067 reset_val);
1068 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1069 reset_val);
1070 msleep(1);
1071 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1072 &val);
1073 if (val & reset_val) {
1074 dev_err(dev, "SAS de-reset fail.\n");
1075 return -EIO;
1076 }
1077 } else
1078 dev_warn(dev, "no reset method\n");
1079
1080 return 0;
1081 }
1082
1083 /* This function needs to be called after resetting SAS controller. */
1084 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1085 {
1086 u32 cfg;
1087 int phy_no;
1088
1089 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1090 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1091 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1092 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1093 continue;
1094
1095 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1096 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1097 }
1098 }
1099
1100 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1101 {
1102 int phy_no;
1103 u32 dma_tx_dfx1;
1104
1105 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1106 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1107 continue;
1108
1109 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1110 DMA_TX_DFX1);
1111 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1112 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1113 phy_no, CON_CONTROL);
1114
1115 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1116 hisi_sas_phy_write32(hisi_hba, phy_no,
1117 CON_CONTROL, cfg);
1118 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1119 }
1120 }
1121 }
1122
1123 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1124 {
1125 struct device *dev = hisi_hba->dev;
1126 int i;
1127
1128 /* Global registers init */
1129
1130 /* Deal with am-max-transmissions quirk */
1131 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1132 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1133 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1134 0x2020);
1135 } /* Else, use defaults -> do nothing */
1136
1137 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1138 (u32)((1ULL << hisi_hba->queue_count) - 1));
1139 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1140 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1141 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1142 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1143 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1144 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1145 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1146 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1147 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1148 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1149 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1150 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1151 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1152 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1153 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1154 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1155 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1156 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1157 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1158 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1159 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1160 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1161 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1162 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1163 for (i = 0; i < hisi_hba->queue_count; i++)
1164 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1165
1166 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1167 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1168
1169 for (i = 0; i < hisi_hba->n_phy; i++) {
1170 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1171 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1172 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1173 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1174 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1175 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1176 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1177 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1178 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1179 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1180 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1181 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1182 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1183 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1184 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1185 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1186 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1187 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1188 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1189 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1190 if (hisi_hba->refclk_frequency_mhz == 66)
1191 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1192 /* else, do nothing -> leave it how you found it */
1193 }
1194
1195 for (i = 0; i < hisi_hba->queue_count; i++) {
1196 /* Delivery queue */
1197 hisi_sas_write32(hisi_hba,
1198 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1199 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1200
1201 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1202 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1203
1204 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1205 HISI_SAS_QUEUE_SLOTS);
1206
1207 /* Completion queue */
1208 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1209 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1210
1211 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1212 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1213
1214 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1215 HISI_SAS_QUEUE_SLOTS);
1216 }
1217
1218 /* itct */
1219 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1220 lower_32_bits(hisi_hba->itct_dma));
1221
1222 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1223 upper_32_bits(hisi_hba->itct_dma));
1224
1225 /* iost */
1226 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1227 lower_32_bits(hisi_hba->iost_dma));
1228
1229 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1230 upper_32_bits(hisi_hba->iost_dma));
1231
1232 /* breakpoint */
1233 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1234 lower_32_bits(hisi_hba->breakpoint_dma));
1235
1236 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1237 upper_32_bits(hisi_hba->breakpoint_dma));
1238
1239 /* SATA broken msg */
1240 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1241 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1242
1243 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1244 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1245
1246 /* SATA initial fis */
1247 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1248 lower_32_bits(hisi_hba->initial_fis_dma));
1249
1250 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1251 upper_32_bits(hisi_hba->initial_fis_dma));
1252 }
1253
1254 static void link_timeout_enable_link(struct timer_list *t)
1255 {
1256 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1257 int i, reg_val;
1258
1259 for (i = 0; i < hisi_hba->n_phy; i++) {
1260 if (hisi_hba->reject_stp_links_msk & BIT(i))
1261 continue;
1262
1263 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1264 if (!(reg_val & BIT(0))) {
1265 hisi_sas_phy_write32(hisi_hba, i,
1266 CON_CONTROL, 0x7);
1267 break;
1268 }
1269 }
1270
1271 hisi_hba->timer.function = (TIMER_FUNC_TYPE)link_timeout_disable_link;
1272 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1273 }
1274
1275 static void link_timeout_disable_link(struct timer_list *t)
1276 {
1277 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1278 int i, reg_val;
1279
1280 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1281 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1282 if (hisi_hba->reject_stp_links_msk & BIT(i))
1283 continue;
1284
1285 if (reg_val & BIT(i)) {
1286 hisi_sas_phy_write32(hisi_hba, i,
1287 CON_CONTROL, 0x6);
1288 break;
1289 }
1290 }
1291
1292 hisi_hba->timer.function = (TIMER_FUNC_TYPE)link_timeout_enable_link;
1293 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1294 }
1295
1296 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1297 {
1298 hisi_hba->timer.function = (TIMER_FUNC_TYPE)link_timeout_disable_link;
1299 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1300 add_timer(&hisi_hba->timer);
1301 }
1302
1303 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1304 {
1305 struct device *dev = hisi_hba->dev;
1306 int rc;
1307
1308 rc = reset_hw_v2_hw(hisi_hba);
1309 if (rc) {
1310 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1311 return rc;
1312 }
1313
1314 msleep(100);
1315 init_reg_v2_hw(hisi_hba);
1316
1317 return 0;
1318 }
1319
1320 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1321 {
1322 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1323
1324 cfg |= PHY_CFG_ENA_MSK;
1325 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1326 }
1327
1328 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1329 {
1330 u32 context;
1331
1332 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1333 if (context & (1 << phy_no))
1334 return true;
1335
1336 return false;
1337 }
1338
1339 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1340 {
1341 u32 dfx_val;
1342
1343 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1344
1345 if (dfx_val & BIT(16))
1346 return false;
1347
1348 return true;
1349 }
1350
1351 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1352 {
1353 int i, max_loop = 1000;
1354 struct device *dev = hisi_hba->dev;
1355 u32 status, axi_status, dfx_val, dfx_tx_val;
1356
1357 for (i = 0; i < max_loop; i++) {
1358 status = hisi_sas_read32_relaxed(hisi_hba,
1359 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1360
1361 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1362 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1363 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1364 phy_no, DMA_TX_FIFO_DFX0);
1365
1366 if ((status == 0x3) && (axi_status == 0x0) &&
1367 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1368 return true;
1369 udelay(10);
1370 }
1371 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1372 phy_no, status, axi_status,
1373 dfx_val, dfx_tx_val);
1374 return false;
1375 }
1376
1377 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1378 {
1379 int i, max_loop = 1000;
1380 struct device *dev = hisi_hba->dev;
1381 u32 status, tx_dfx0;
1382
1383 for (i = 0; i < max_loop; i++) {
1384 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1385 status = (status & 0x3fc0) >> 6;
1386
1387 if (status != 0x1)
1388 return true;
1389
1390 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1391 if ((tx_dfx0 & 0x1ff) == 0x2)
1392 return true;
1393 udelay(10);
1394 }
1395 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1396 phy_no, status, tx_dfx0);
1397 return false;
1398 }
1399
1400 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1401 {
1402 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1403 return true;
1404
1405 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1406 return false;
1407
1408 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1409 return false;
1410
1411 return true;
1412 }
1413
1414
1415 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1416 {
1417 u32 cfg, axi_val, dfx0_val, txid_auto;
1418 struct device *dev = hisi_hba->dev;
1419
1420 /* Close axi bus. */
1421 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1422 AM_CTRL_GLOBAL);
1423 axi_val |= 0x1;
1424 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1425 AM_CTRL_GLOBAL, axi_val);
1426
1427 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1428 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1429 goto do_disable;
1430
1431 /* Reset host controller. */
1432 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1433 return;
1434 }
1435
1436 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1437 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1438 if (dfx0_val != 0x4)
1439 goto do_disable;
1440
1441 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1442 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1443 phy_no);
1444 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1445 TXID_AUTO);
1446 txid_auto |= TXID_AUTO_CTB_MSK;
1447 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1448 txid_auto);
1449 }
1450
1451 do_disable:
1452 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1453 cfg &= ~PHY_CFG_ENA_MSK;
1454 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1455
1456 /* Open axi bus. */
1457 axi_val &= ~0x1;
1458 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1459 AM_CTRL_GLOBAL, axi_val);
1460 }
1461
1462 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1463 {
1464 config_id_frame_v2_hw(hisi_hba, phy_no);
1465 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1466 enable_phy_v2_hw(hisi_hba, phy_no);
1467 }
1468
1469 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1470 {
1471 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1472 u32 txid_auto;
1473
1474 disable_phy_v2_hw(hisi_hba, phy_no);
1475 if (phy->identify.device_type == SAS_END_DEVICE) {
1476 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1477 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1478 txid_auto | TX_HARDRST_MSK);
1479 }
1480 msleep(100);
1481 start_phy_v2_hw(hisi_hba, phy_no);
1482 }
1483
1484 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1485 {
1486 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1487 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1488 struct sas_phy *sphy = sas_phy->phy;
1489 u32 err4_reg_val, err6_reg_val;
1490
1491 /* loss dword syn, phy reset problem */
1492 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1493
1494 /* disparity err, invalid dword */
1495 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1496
1497 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1498 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1499 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1500 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1501 }
1502
1503 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1504 {
1505 int i;
1506
1507 for (i = 0; i < hisi_hba->n_phy; i++) {
1508 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1509 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1510
1511 if (!sas_phy->phy->enabled)
1512 continue;
1513
1514 start_phy_v2_hw(hisi_hba, i);
1515 }
1516 }
1517
1518 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1519 {
1520 u32 sl_control;
1521
1522 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1523 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1524 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1525 msleep(1);
1526 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1527 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1528 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1529 }
1530
1531 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1532 {
1533 return SAS_LINK_RATE_12_0_GBPS;
1534 }
1535
1536 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1537 struct sas_phy_linkrates *r)
1538 {
1539 u32 prog_phy_link_rate =
1540 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1541 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1542 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1543 int i;
1544 enum sas_linkrate min, max;
1545 u32 rate_mask = 0;
1546
1547 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1548 max = sas_phy->phy->maximum_linkrate;
1549 min = r->minimum_linkrate;
1550 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1551 max = r->maximum_linkrate;
1552 min = sas_phy->phy->minimum_linkrate;
1553 } else
1554 return;
1555
1556 sas_phy->phy->maximum_linkrate = max;
1557 sas_phy->phy->minimum_linkrate = min;
1558
1559 min -= SAS_LINK_RATE_1_5_GBPS;
1560 max -= SAS_LINK_RATE_1_5_GBPS;
1561
1562 for (i = 0; i <= max; i++)
1563 rate_mask |= 1 << (i * 2);
1564
1565 prog_phy_link_rate &= ~0xff;
1566 prog_phy_link_rate |= rate_mask;
1567
1568 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1569 prog_phy_link_rate);
1570
1571 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1572 }
1573
1574 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1575 {
1576 int i, bitmap = 0;
1577 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1578 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1579
1580 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1581 if (phy_state & 1 << i)
1582 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1583 bitmap |= 1 << i;
1584
1585 if (hisi_hba->n_phy == 9) {
1586 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1587
1588 if (phy_state & 1 << 8)
1589 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1590 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1591 bitmap |= 1 << 9;
1592 }
1593
1594 return bitmap;
1595 }
1596
1597 /*
1598 * The callpath to this function and upto writing the write
1599 * queue pointer should be safe from interruption.
1600 */
1601 static int
1602 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1603 {
1604 struct device *dev = hisi_hba->dev;
1605 int queue = dq->id;
1606 u32 r, w;
1607
1608 w = dq->wr_point;
1609 r = hisi_sas_read32_relaxed(hisi_hba,
1610 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1611 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1612 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1613 queue, r, w);
1614 return -EAGAIN;
1615 }
1616
1617 return 0;
1618 }
1619
1620 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1621 {
1622 struct hisi_hba *hisi_hba = dq->hisi_hba;
1623 int dlvry_queue = dq->slot_prep->dlvry_queue;
1624 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1625
1626 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1627 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1628 dq->wr_point);
1629 }
1630
1631 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1632 struct hisi_sas_slot *slot,
1633 struct hisi_sas_cmd_hdr *hdr,
1634 struct scatterlist *scatter,
1635 int n_elem)
1636 {
1637 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1638 struct device *dev = hisi_hba->dev;
1639 struct scatterlist *sg;
1640 int i;
1641
1642 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1643 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1644 n_elem);
1645 return -EINVAL;
1646 }
1647
1648 for_each_sg(scatter, sg, n_elem, i) {
1649 struct hisi_sas_sge *entry = &sge_page->sge[i];
1650
1651 entry->addr = cpu_to_le64(sg_dma_address(sg));
1652 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1653 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1654 entry->data_off = 0;
1655 }
1656
1657 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1658
1659 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1660
1661 return 0;
1662 }
1663
1664 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1665 struct hisi_sas_slot *slot)
1666 {
1667 struct sas_task *task = slot->task;
1668 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1669 struct domain_device *device = task->dev;
1670 struct device *dev = hisi_hba->dev;
1671 struct hisi_sas_port *port = slot->port;
1672 struct scatterlist *sg_req, *sg_resp;
1673 struct hisi_sas_device *sas_dev = device->lldd_dev;
1674 dma_addr_t req_dma_addr;
1675 unsigned int req_len, resp_len;
1676 int elem, rc;
1677
1678 /*
1679 * DMA-map SMP request, response buffers
1680 */
1681 /* req */
1682 sg_req = &task->smp_task.smp_req;
1683 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1684 if (!elem)
1685 return -ENOMEM;
1686 req_len = sg_dma_len(sg_req);
1687 req_dma_addr = sg_dma_address(sg_req);
1688
1689 /* resp */
1690 sg_resp = &task->smp_task.smp_resp;
1691 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1692 if (!elem) {
1693 rc = -ENOMEM;
1694 goto err_out_req;
1695 }
1696 resp_len = sg_dma_len(sg_resp);
1697 if ((req_len & 0x3) || (resp_len & 0x3)) {
1698 rc = -EINVAL;
1699 goto err_out_resp;
1700 }
1701
1702 /* create header */
1703 /* dw0 */
1704 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1705 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1706 (2 << CMD_HDR_CMD_OFF)); /* smp */
1707
1708 /* map itct entry */
1709 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1710 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1711 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1712
1713 /* dw2 */
1714 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1715 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1716 CMD_HDR_MRFL_OFF));
1717
1718 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1719
1720 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1721 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1722
1723 return 0;
1724
1725 err_out_resp:
1726 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1727 DMA_FROM_DEVICE);
1728 err_out_req:
1729 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1730 DMA_TO_DEVICE);
1731 return rc;
1732 }
1733
1734 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1735 struct hisi_sas_slot *slot, int is_tmf,
1736 struct hisi_sas_tmf_task *tmf)
1737 {
1738 struct sas_task *task = slot->task;
1739 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1740 struct domain_device *device = task->dev;
1741 struct hisi_sas_device *sas_dev = device->lldd_dev;
1742 struct hisi_sas_port *port = slot->port;
1743 struct sas_ssp_task *ssp_task = &task->ssp_task;
1744 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1745 int has_data = 0, rc, priority = is_tmf;
1746 u8 *buf_cmd;
1747 u32 dw1 = 0, dw2 = 0;
1748
1749 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1750 (2 << CMD_HDR_TLR_CTRL_OFF) |
1751 (port->id << CMD_HDR_PORT_OFF) |
1752 (priority << CMD_HDR_PRIORITY_OFF) |
1753 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1754
1755 dw1 = 1 << CMD_HDR_VDTL_OFF;
1756 if (is_tmf) {
1757 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1758 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1759 } else {
1760 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1761 switch (scsi_cmnd->sc_data_direction) {
1762 case DMA_TO_DEVICE:
1763 has_data = 1;
1764 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1765 break;
1766 case DMA_FROM_DEVICE:
1767 has_data = 1;
1768 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1769 break;
1770 default:
1771 dw1 &= ~CMD_HDR_DIR_MSK;
1772 }
1773 }
1774
1775 /* map itct entry */
1776 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1777 hdr->dw1 = cpu_to_le32(dw1);
1778
1779 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1780 + 3) / 4) << CMD_HDR_CFL_OFF) |
1781 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1782 (2 << CMD_HDR_SG_MOD_OFF);
1783 hdr->dw2 = cpu_to_le32(dw2);
1784
1785 hdr->transfer_tags = cpu_to_le32(slot->idx);
1786
1787 if (has_data) {
1788 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1789 slot->n_elem);
1790 if (rc)
1791 return rc;
1792 }
1793
1794 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1795 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1796 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1797
1798 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1799 sizeof(struct ssp_frame_hdr);
1800
1801 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1802 if (!is_tmf) {
1803 buf_cmd[9] = task->ssp_task.task_attr |
1804 (task->ssp_task.task_prio << 3);
1805 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1806 task->ssp_task.cmd->cmd_len);
1807 } else {
1808 buf_cmd[10] = tmf->tmf;
1809 switch (tmf->tmf) {
1810 case TMF_ABORT_TASK:
1811 case TMF_QUERY_TASK:
1812 buf_cmd[12] =
1813 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1814 buf_cmd[13] =
1815 tmf->tag_of_task_to_be_managed & 0xff;
1816 break;
1817 default:
1818 break;
1819 }
1820 }
1821
1822 return 0;
1823 }
1824
1825 #define TRANS_TX_ERR 0
1826 #define TRANS_RX_ERR 1
1827 #define DMA_TX_ERR 2
1828 #define SIPC_RX_ERR 3
1829 #define DMA_RX_ERR 4
1830
1831 #define DMA_TX_ERR_OFF 0
1832 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1833 #define SIPC_RX_ERR_OFF 16
1834 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1835
1836 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1837 {
1838 static const u8 trans_tx_err_code_prio[] = {
1839 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1840 TRANS_TX_ERR_PHY_NOT_ENABLE,
1841 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1842 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1843 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1844 RESERVED0,
1845 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1846 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1847 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1848 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1849 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1850 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1851 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1852 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1853 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1854 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1855 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1856 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1857 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1858 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1859 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1860 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1861 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1862 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1863 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1864 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1865 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1866 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1867 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1868 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1869 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1870 };
1871 int index, i;
1872
1873 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1874 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1875 if (err_msk & (1 << index))
1876 return trans_tx_err_code_prio[i];
1877 }
1878 return -1;
1879 }
1880
1881 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1882 {
1883 static const u8 trans_rx_err_code_prio[] = {
1884 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1885 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1886 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1887 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1888 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1889 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1890 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1891 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1892 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1893 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1894 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1895 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1896 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1897 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1898 RESERVED1,
1899 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1900 TRANS_RX_ERR_WITH_DATA_LEN0,
1901 TRANS_RX_ERR_WITH_BAD_HASH,
1902 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1903 TRANS_RX_SSP_FRM_LEN_ERR,
1904 RESERVED2,
1905 RESERVED3,
1906 RESERVED4,
1907 RESERVED5,
1908 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1909 TRANS_RX_SMP_FRM_LEN_ERR,
1910 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1911 RESERVED6,
1912 RESERVED7,
1913 RESERVED8,
1914 RESERVED9,
1915 TRANS_RX_R_ERR,
1916 };
1917 int index, i;
1918
1919 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1920 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1921 if (err_msk & (1 << index))
1922 return trans_rx_err_code_prio[i];
1923 }
1924 return -1;
1925 }
1926
1927 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1928 {
1929 static const u8 dma_tx_err_code_prio[] = {
1930 DMA_TX_UNEXP_XFER_ERR,
1931 DMA_TX_UNEXP_RETRANS_ERR,
1932 DMA_TX_XFER_LEN_OVERFLOW,
1933 DMA_TX_XFER_OFFSET_ERR,
1934 DMA_TX_RAM_ECC_ERR,
1935 DMA_TX_DIF_LEN_ALIGN_ERR,
1936 DMA_TX_DIF_CRC_ERR,
1937 DMA_TX_DIF_APP_ERR,
1938 DMA_TX_DIF_RPP_ERR,
1939 DMA_TX_DATA_SGL_OVERFLOW,
1940 DMA_TX_DIF_SGL_OVERFLOW,
1941 };
1942 int index, i;
1943
1944 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1945 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1946 err_msk = err_msk & DMA_TX_ERR_MSK;
1947 if (err_msk & (1 << index))
1948 return dma_tx_err_code_prio[i];
1949 }
1950 return -1;
1951 }
1952
1953 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1954 {
1955 static const u8 sipc_rx_err_code_prio[] = {
1956 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1957 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1958 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1959 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1960 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1961 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1962 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1963 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1964 SIPC_RX_SATA_UNEXP_FIS_ERR,
1965 SIPC_RX_WRSETUP_ESTATUS_ERR,
1966 SIPC_RX_DATA_UNDERFLOW_ERR,
1967 };
1968 int index, i;
1969
1970 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1971 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1972 err_msk = err_msk & SIPC_RX_ERR_MSK;
1973 if (err_msk & (1 << (index + 0x10)))
1974 return sipc_rx_err_code_prio[i];
1975 }
1976 return -1;
1977 }
1978
1979 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1980 {
1981 static const u8 dma_rx_err_code_prio[] = {
1982 DMA_RX_UNKNOWN_FRM_ERR,
1983 DMA_RX_DATA_LEN_OVERFLOW,
1984 DMA_RX_DATA_LEN_UNDERFLOW,
1985 DMA_RX_DATA_OFFSET_ERR,
1986 RESERVED10,
1987 DMA_RX_SATA_FRAME_TYPE_ERR,
1988 DMA_RX_RESP_BUF_OVERFLOW,
1989 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1990 DMA_RX_UNEXP_NORM_RESP_ERR,
1991 DMA_RX_UNEXP_RDFRAME_ERR,
1992 DMA_RX_PIO_DATA_LEN_ERR,
1993 DMA_RX_RDSETUP_STATUS_ERR,
1994 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
1995 DMA_RX_RDSETUP_STATUS_BSY_ERR,
1996 DMA_RX_RDSETUP_LEN_ODD_ERR,
1997 DMA_RX_RDSETUP_LEN_ZERO_ERR,
1998 DMA_RX_RDSETUP_LEN_OVER_ERR,
1999 DMA_RX_RDSETUP_OFFSET_ERR,
2000 DMA_RX_RDSETUP_ACTIVE_ERR,
2001 DMA_RX_RDSETUP_ESTATUS_ERR,
2002 DMA_RX_RAM_ECC_ERR,
2003 DMA_RX_DIF_CRC_ERR,
2004 DMA_RX_DIF_APP_ERR,
2005 DMA_RX_DIF_RPP_ERR,
2006 DMA_RX_DATA_SGL_OVERFLOW,
2007 DMA_RX_DIF_SGL_OVERFLOW,
2008 };
2009 int index, i;
2010
2011 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2012 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2013 if (err_msk & (1 << index))
2014 return dma_rx_err_code_prio[i];
2015 }
2016 return -1;
2017 }
2018
2019 /* by default, task resp is complete */
2020 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2021 struct sas_task *task,
2022 struct hisi_sas_slot *slot,
2023 int err_phase)
2024 {
2025 struct task_status_struct *ts = &task->task_status;
2026 struct hisi_sas_err_record_v2 *err_record =
2027 hisi_sas_status_buf_addr_mem(slot);
2028 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2029 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2030 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2031 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2032 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2033 int error = -1;
2034
2035 if (err_phase == 1) {
2036 /* error in TX phase, the priority of error is: DW2 > DW0 */
2037 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2038 if (error == -1)
2039 error = parse_trans_tx_err_code_v2_hw(
2040 trans_tx_fail_type);
2041 } else if (err_phase == 2) {
2042 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2043 error = parse_trans_rx_err_code_v2_hw(
2044 trans_rx_fail_type);
2045 if (error == -1) {
2046 error = parse_dma_rx_err_code_v2_hw(
2047 dma_rx_err_type);
2048 if (error == -1)
2049 error = parse_sipc_rx_err_code_v2_hw(
2050 sipc_rx_err_type);
2051 }
2052 }
2053
2054 switch (task->task_proto) {
2055 case SAS_PROTOCOL_SSP:
2056 {
2057 switch (error) {
2058 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2059 {
2060 ts->stat = SAS_OPEN_REJECT;
2061 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2062 break;
2063 }
2064 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2065 {
2066 ts->stat = SAS_OPEN_REJECT;
2067 ts->open_rej_reason = SAS_OREJ_EPROTO;
2068 break;
2069 }
2070 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2071 {
2072 ts->stat = SAS_OPEN_REJECT;
2073 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2074 break;
2075 }
2076 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2077 {
2078 ts->stat = SAS_OPEN_REJECT;
2079 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2080 break;
2081 }
2082 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2083 {
2084 ts->stat = SAS_OPEN_REJECT;
2085 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2086 break;
2087 }
2088 case DMA_RX_UNEXP_NORM_RESP_ERR:
2089 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2090 case DMA_RX_RESP_BUF_OVERFLOW:
2091 {
2092 ts->stat = SAS_OPEN_REJECT;
2093 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2094 break;
2095 }
2096 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2097 {
2098 /* not sure */
2099 ts->stat = SAS_DEV_NO_RESPONSE;
2100 break;
2101 }
2102 case DMA_RX_DATA_LEN_OVERFLOW:
2103 {
2104 ts->stat = SAS_DATA_OVERRUN;
2105 ts->residual = 0;
2106 break;
2107 }
2108 case DMA_RX_DATA_LEN_UNDERFLOW:
2109 {
2110 ts->residual = trans_tx_fail_type;
2111 ts->stat = SAS_DATA_UNDERRUN;
2112 break;
2113 }
2114 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2115 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2116 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2117 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2118 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2119 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2120 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2121 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2122 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2123 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2124 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2125 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2126 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2127 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2128 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2129 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2130 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2131 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2132 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2133 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2134 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2135 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2136 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2137 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2138 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2139 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2140 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2141 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2142 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2143 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2144 case TRANS_TX_ERR_FRAME_TXED:
2145 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2146 case TRANS_RX_ERR_WITH_DATA_LEN0:
2147 case TRANS_RX_ERR_WITH_BAD_HASH:
2148 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2149 case TRANS_RX_SSP_FRM_LEN_ERR:
2150 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2151 case DMA_TX_DATA_SGL_OVERFLOW:
2152 case DMA_TX_UNEXP_XFER_ERR:
2153 case DMA_TX_UNEXP_RETRANS_ERR:
2154 case DMA_TX_XFER_LEN_OVERFLOW:
2155 case DMA_TX_XFER_OFFSET_ERR:
2156 case SIPC_RX_DATA_UNDERFLOW_ERR:
2157 case DMA_RX_DATA_SGL_OVERFLOW:
2158 case DMA_RX_DATA_OFFSET_ERR:
2159 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2160 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2161 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2162 case DMA_RX_SATA_FRAME_TYPE_ERR:
2163 case DMA_RX_UNKNOWN_FRM_ERR:
2164 {
2165 /* This will request a retry */
2166 ts->stat = SAS_QUEUE_FULL;
2167 slot->abort = 1;
2168 break;
2169 }
2170 default:
2171 break;
2172 }
2173 }
2174 break;
2175 case SAS_PROTOCOL_SMP:
2176 ts->stat = SAM_STAT_CHECK_CONDITION;
2177 break;
2178
2179 case SAS_PROTOCOL_SATA:
2180 case SAS_PROTOCOL_STP:
2181 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2182 {
2183 switch (error) {
2184 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2185 {
2186 ts->stat = SAS_OPEN_REJECT;
2187 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2188 break;
2189 }
2190 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2191 {
2192 ts->resp = SAS_TASK_UNDELIVERED;
2193 ts->stat = SAS_DEV_NO_RESPONSE;
2194 break;
2195 }
2196 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2197 {
2198 ts->stat = SAS_OPEN_REJECT;
2199 ts->open_rej_reason = SAS_OREJ_EPROTO;
2200 break;
2201 }
2202 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2203 {
2204 ts->stat = SAS_OPEN_REJECT;
2205 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2206 break;
2207 }
2208 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2209 {
2210 ts->stat = SAS_OPEN_REJECT;
2211 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2212 break;
2213 }
2214 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2215 {
2216 ts->stat = SAS_OPEN_REJECT;
2217 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2218 break;
2219 }
2220 case DMA_RX_RESP_BUF_OVERFLOW:
2221 case DMA_RX_UNEXP_NORM_RESP_ERR:
2222 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2223 {
2224 ts->stat = SAS_OPEN_REJECT;
2225 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2226 break;
2227 }
2228 case DMA_RX_DATA_LEN_OVERFLOW:
2229 {
2230 ts->stat = SAS_DATA_OVERRUN;
2231 ts->residual = 0;
2232 break;
2233 }
2234 case DMA_RX_DATA_LEN_UNDERFLOW:
2235 {
2236 ts->residual = trans_tx_fail_type;
2237 ts->stat = SAS_DATA_UNDERRUN;
2238 break;
2239 }
2240 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2241 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2242 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2243 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2244 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2245 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2246 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2247 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2248 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2249 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2250 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2251 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2252 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2253 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2254 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2255 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2256 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2257 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2258 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2259 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2260 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2261 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2262 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2263 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2264 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2265 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2266 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2267 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2268 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2269 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2270 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2271 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2272 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2273 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2274 case TRANS_RX_ERR_WITH_DATA_LEN0:
2275 case TRANS_RX_ERR_WITH_BAD_HASH:
2276 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2277 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2278 case DMA_TX_DATA_SGL_OVERFLOW:
2279 case DMA_TX_UNEXP_XFER_ERR:
2280 case DMA_TX_UNEXP_RETRANS_ERR:
2281 case DMA_TX_XFER_LEN_OVERFLOW:
2282 case DMA_TX_XFER_OFFSET_ERR:
2283 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2284 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2285 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2286 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2287 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2288 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2289 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2290 case DMA_RX_DATA_SGL_OVERFLOW:
2291 case DMA_RX_DATA_OFFSET_ERR:
2292 case DMA_RX_SATA_FRAME_TYPE_ERR:
2293 case DMA_RX_UNEXP_RDFRAME_ERR:
2294 case DMA_RX_PIO_DATA_LEN_ERR:
2295 case DMA_RX_RDSETUP_STATUS_ERR:
2296 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2297 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2298 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2299 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2300 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2301 case DMA_RX_RDSETUP_OFFSET_ERR:
2302 case DMA_RX_RDSETUP_ACTIVE_ERR:
2303 case DMA_RX_RDSETUP_ESTATUS_ERR:
2304 case DMA_RX_UNKNOWN_FRM_ERR:
2305 case TRANS_RX_SSP_FRM_LEN_ERR:
2306 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2307 {
2308 slot->abort = 1;
2309 ts->stat = SAS_PHY_DOWN;
2310 break;
2311 }
2312 default:
2313 {
2314 ts->stat = SAS_PROTO_RESPONSE;
2315 break;
2316 }
2317 }
2318 hisi_sas_sata_done(task, slot);
2319 }
2320 break;
2321 default:
2322 break;
2323 }
2324 }
2325
2326 static int
2327 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2328 {
2329 struct sas_task *task = slot->task;
2330 struct hisi_sas_device *sas_dev;
2331 struct device *dev = hisi_hba->dev;
2332 struct task_status_struct *ts;
2333 struct domain_device *device;
2334 enum exec_status sts;
2335 struct hisi_sas_complete_v2_hdr *complete_queue =
2336 hisi_hba->complete_hdr[slot->cmplt_queue];
2337 struct hisi_sas_complete_v2_hdr *complete_hdr =
2338 &complete_queue[slot->cmplt_queue_slot];
2339 unsigned long flags;
2340 int aborted;
2341
2342 if (unlikely(!task || !task->lldd_task || !task->dev))
2343 return -EINVAL;
2344
2345 ts = &task->task_status;
2346 device = task->dev;
2347 sas_dev = device->lldd_dev;
2348
2349 spin_lock_irqsave(&task->task_state_lock, flags);
2350 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2351 task->task_state_flags &=
2352 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2353 spin_unlock_irqrestore(&task->task_state_lock, flags);
2354
2355 memset(ts, 0, sizeof(*ts));
2356 ts->resp = SAS_TASK_COMPLETE;
2357
2358 if (unlikely(aborted)) {
2359 ts->stat = SAS_ABORTED_TASK;
2360 spin_lock_irqsave(&hisi_hba->lock, flags);
2361 hisi_sas_slot_task_free(hisi_hba, task, slot);
2362 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2363 return -1;
2364 }
2365
2366 if (unlikely(!sas_dev)) {
2367 dev_dbg(dev, "slot complete: port has no device\n");
2368 ts->stat = SAS_PHY_DOWN;
2369 goto out;
2370 }
2371
2372 /* Use SAS+TMF status codes */
2373 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2374 >> CMPLT_HDR_ABORT_STAT_OFF) {
2375 case STAT_IO_ABORTED:
2376 /* this io has been aborted by abort command */
2377 ts->stat = SAS_ABORTED_TASK;
2378 goto out;
2379 case STAT_IO_COMPLETE:
2380 /* internal abort command complete */
2381 ts->stat = TMF_RESP_FUNC_SUCC;
2382 del_timer(&slot->internal_abort_timer);
2383 goto out;
2384 case STAT_IO_NO_DEVICE:
2385 ts->stat = TMF_RESP_FUNC_COMPLETE;
2386 del_timer(&slot->internal_abort_timer);
2387 goto out;
2388 case STAT_IO_NOT_VALID:
2389 /* abort single io, controller don't find
2390 * the io need to abort
2391 */
2392 ts->stat = TMF_RESP_FUNC_FAILED;
2393 del_timer(&slot->internal_abort_timer);
2394 goto out;
2395 default:
2396 break;
2397 }
2398
2399 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2400 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2401 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2402 >> CMPLT_HDR_ERR_PHASE_OFF;
2403
2404 /* Analyse error happens on which phase TX or RX */
2405 if (ERR_ON_TX_PHASE(err_phase))
2406 slot_err_v2_hw(hisi_hba, task, slot, 1);
2407 else if (ERR_ON_RX_PHASE(err_phase))
2408 slot_err_v2_hw(hisi_hba, task, slot, 2);
2409
2410 if (unlikely(slot->abort))
2411 return ts->stat;
2412 goto out;
2413 }
2414
2415 switch (task->task_proto) {
2416 case SAS_PROTOCOL_SSP:
2417 {
2418 struct hisi_sas_status_buffer *status_buffer =
2419 hisi_sas_status_buf_addr_mem(slot);
2420 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2421 &status_buffer->iu[0];
2422
2423 sas_ssp_task_response(dev, task, iu);
2424 break;
2425 }
2426 case SAS_PROTOCOL_SMP:
2427 {
2428 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2429 void *to;
2430
2431 ts->stat = SAM_STAT_GOOD;
2432 to = kmap_atomic(sg_page(sg_resp));
2433
2434 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2435 DMA_FROM_DEVICE);
2436 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2437 DMA_TO_DEVICE);
2438 memcpy(to + sg_resp->offset,
2439 hisi_sas_status_buf_addr_mem(slot) +
2440 sizeof(struct hisi_sas_err_record),
2441 sg_dma_len(sg_resp));
2442 kunmap_atomic(to);
2443 break;
2444 }
2445 case SAS_PROTOCOL_SATA:
2446 case SAS_PROTOCOL_STP:
2447 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2448 {
2449 ts->stat = SAM_STAT_GOOD;
2450 hisi_sas_sata_done(task, slot);
2451 break;
2452 }
2453 default:
2454 ts->stat = SAM_STAT_CHECK_CONDITION;
2455 break;
2456 }
2457
2458 if (!slot->port->port_attached) {
2459 dev_err(dev, "slot complete: port %d has removed\n",
2460 slot->port->sas_port.id);
2461 ts->stat = SAS_PHY_DOWN;
2462 }
2463
2464 out:
2465 spin_lock_irqsave(&task->task_state_lock, flags);
2466 task->task_state_flags |= SAS_TASK_STATE_DONE;
2467 spin_unlock_irqrestore(&task->task_state_lock, flags);
2468 spin_lock_irqsave(&hisi_hba->lock, flags);
2469 hisi_sas_slot_task_free(hisi_hba, task, slot);
2470 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2471 sts = ts->stat;
2472
2473 if (task->task_done)
2474 task->task_done(task);
2475
2476 return sts;
2477 }
2478
2479 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2480 struct hisi_sas_slot *slot)
2481 {
2482 struct sas_task *task = slot->task;
2483 struct domain_device *device = task->dev;
2484 struct domain_device *parent_dev = device->parent;
2485 struct hisi_sas_device *sas_dev = device->lldd_dev;
2486 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2487 struct asd_sas_port *sas_port = device->port;
2488 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2489 u8 *buf_cmd;
2490 int has_data = 0, rc = 0, hdr_tag = 0;
2491 u32 dw1 = 0, dw2 = 0;
2492
2493 /* create header */
2494 /* dw0 */
2495 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2496 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2497 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2498 else
2499 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2500
2501 /* dw1 */
2502 switch (task->data_dir) {
2503 case DMA_TO_DEVICE:
2504 has_data = 1;
2505 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2506 break;
2507 case DMA_FROM_DEVICE:
2508 has_data = 1;
2509 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2510 break;
2511 default:
2512 dw1 &= ~CMD_HDR_DIR_MSK;
2513 }
2514
2515 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2516 (task->ata_task.fis.control & ATA_SRST))
2517 dw1 |= 1 << CMD_HDR_RESET_OFF;
2518
2519 dw1 |= (hisi_sas_get_ata_protocol(
2520 task->ata_task.fis.command, task->data_dir))
2521 << CMD_HDR_FRAME_TYPE_OFF;
2522 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2523 hdr->dw1 = cpu_to_le32(dw1);
2524
2525 /* dw2 */
2526 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2527 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2528 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2529 }
2530
2531 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2532 2 << CMD_HDR_SG_MOD_OFF;
2533 hdr->dw2 = cpu_to_le32(dw2);
2534
2535 /* dw3 */
2536 hdr->transfer_tags = cpu_to_le32(slot->idx);
2537
2538 if (has_data) {
2539 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2540 slot->n_elem);
2541 if (rc)
2542 return rc;
2543 }
2544
2545 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2546 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2547 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2548
2549 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2550
2551 if (likely(!task->ata_task.device_control_reg_update))
2552 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2553 /* fill in command FIS */
2554 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2555
2556 return 0;
2557 }
2558
2559 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2560 {
2561 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2562 struct hisi_sas_port *port = slot->port;
2563 struct asd_sas_port *asd_sas_port;
2564 struct asd_sas_phy *sas_phy;
2565
2566 if (!port)
2567 return;
2568
2569 asd_sas_port = &port->sas_port;
2570
2571 /* Kick the hardware - send break command */
2572 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2573 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2574 struct hisi_hba *hisi_hba = phy->hisi_hba;
2575 int phy_no = sas_phy->id;
2576 u32 link_dfx2;
2577
2578 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2579 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2580 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2581 u32 txid_auto;
2582
2583 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2584 TXID_AUTO);
2585 txid_auto |= TXID_AUTO_CTB_MSK;
2586 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2587 txid_auto);
2588 return;
2589 }
2590 }
2591 }
2592
2593 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2594 struct hisi_sas_slot *slot,
2595 int device_id, int abort_flag, int tag_to_abort)
2596 {
2597 struct sas_task *task = slot->task;
2598 struct domain_device *dev = task->dev;
2599 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2600 struct hisi_sas_port *port = slot->port;
2601 struct timer_list *timer = &slot->internal_abort_timer;
2602
2603 /* setup the quirk timer */
2604 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2605 /* Set the timeout to 10ms less than internal abort timeout */
2606 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2607
2608 /* dw0 */
2609 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2610 (port->id << CMD_HDR_PORT_OFF) |
2611 ((dev_is_sata(dev) ? 1:0) <<
2612 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2613 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2614
2615 /* dw1 */
2616 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2617
2618 /* dw7 */
2619 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2620 hdr->transfer_tags = cpu_to_le32(slot->idx);
2621
2622 return 0;
2623 }
2624
2625 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2626 {
2627 int i, res = IRQ_HANDLED;
2628 u32 port_id, link_rate, hard_phy_linkrate;
2629 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2630 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2631 struct device *dev = hisi_hba->dev;
2632 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2633 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2634
2635 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2636
2637 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2638 goto end;
2639
2640 if (phy_no == 8) {
2641 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2642
2643 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2644 PORT_STATE_PHY8_PORT_NUM_OFF;
2645 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2646 PORT_STATE_PHY8_CONN_RATE_OFF;
2647 } else {
2648 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2649 port_id = (port_id >> (4 * phy_no)) & 0xf;
2650 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2651 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2652 }
2653
2654 if (port_id == 0xf) {
2655 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2656 res = IRQ_NONE;
2657 goto end;
2658 }
2659
2660 for (i = 0; i < 6; i++) {
2661 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2662 RX_IDAF_DWORD0 + (i * 4));
2663 frame_rcvd[i] = __swab32(idaf);
2664 }
2665
2666 sas_phy->linkrate = link_rate;
2667 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2668 HARD_PHY_LINKRATE);
2669 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2670 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2671
2672 sas_phy->oob_mode = SAS_OOB_MODE;
2673 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2674 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2675 phy->port_id = port_id;
2676 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2677 phy->phy_type |= PORT_TYPE_SAS;
2678 phy->phy_attached = 1;
2679 phy->identify.device_type = id->dev_type;
2680 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2681 if (phy->identify.device_type == SAS_END_DEVICE)
2682 phy->identify.target_port_protocols =
2683 SAS_PROTOCOL_SSP;
2684 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2685 phy->identify.target_port_protocols =
2686 SAS_PROTOCOL_SMP;
2687 if (!timer_pending(&hisi_hba->timer))
2688 set_link_timer_quirk(hisi_hba);
2689 }
2690 queue_work(hisi_hba->wq, &phy->phyup_ws);
2691
2692 end:
2693 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2694 CHL_INT0_SL_PHY_ENABLE_MSK);
2695 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2696
2697 return res;
2698 }
2699
2700 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2701 {
2702 u32 port_state;
2703
2704 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2705 if (port_state & 0x1ff)
2706 return true;
2707
2708 return false;
2709 }
2710
2711 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2712 {
2713 u32 phy_state, sl_ctrl, txid_auto;
2714 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2715 struct hisi_sas_port *port = phy->port;
2716
2717 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2718
2719 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2720 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2721
2722 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2723 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2724 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2725 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2726 if (!check_any_wideports_v2_hw(hisi_hba) &&
2727 timer_pending(&hisi_hba->timer))
2728 del_timer(&hisi_hba->timer);
2729
2730 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2731 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2732 txid_auto | TXID_AUTO_CT3_MSK);
2733
2734 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2735 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2736
2737 return IRQ_HANDLED;
2738 }
2739
2740 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2741 {
2742 struct hisi_hba *hisi_hba = p;
2743 u32 irq_msk;
2744 int phy_no = 0;
2745 irqreturn_t res = IRQ_NONE;
2746
2747 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2748 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2749 while (irq_msk) {
2750 if (irq_msk & 1) {
2751 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2752 CHL_INT0);
2753
2754 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2755 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2756
2757 case CHL_INT0_SL_PHY_ENABLE_MSK:
2758 /* phy up */
2759 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2760 IRQ_HANDLED)
2761 res = IRQ_HANDLED;
2762 break;
2763
2764 case CHL_INT0_NOT_RDY_MSK:
2765 /* phy down */
2766 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2767 IRQ_HANDLED)
2768 res = IRQ_HANDLED;
2769 break;
2770
2771 case (CHL_INT0_NOT_RDY_MSK |
2772 CHL_INT0_SL_PHY_ENABLE_MSK):
2773 reg_value = hisi_sas_read32(hisi_hba,
2774 PHY_STATE);
2775 if (reg_value & BIT(phy_no)) {
2776 /* phy up */
2777 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2778 IRQ_HANDLED)
2779 res = IRQ_HANDLED;
2780 } else {
2781 /* phy down */
2782 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2783 IRQ_HANDLED)
2784 res = IRQ_HANDLED;
2785 }
2786 break;
2787
2788 default:
2789 break;
2790 }
2791
2792 }
2793 irq_msk >>= 1;
2794 phy_no++;
2795 }
2796
2797 return res;
2798 }
2799
2800 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2801 {
2802 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2803 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2804 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2805 u32 bcast_status;
2806
2807 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2808 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2809 if (bcast_status & RX_BCAST_CHG_MSK)
2810 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2811 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2812 CHL_INT0_SL_RX_BCST_ACK_MSK);
2813 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2814 }
2815
2816 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2817 {
2818 struct hisi_hba *hisi_hba = p;
2819 struct device *dev = hisi_hba->dev;
2820 u32 ent_msk, ent_tmp, irq_msk;
2821 int phy_no = 0;
2822
2823 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2824 ent_tmp = ent_msk;
2825 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2826 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2827
2828 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2829 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2830
2831 while (irq_msk) {
2832 if (irq_msk & (1 << phy_no)) {
2833 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2834 CHL_INT0);
2835 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2836 CHL_INT1);
2837 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2838 CHL_INT2);
2839
2840 if (irq_value1) {
2841 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2842 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2843 panic("%s: DMAC RX/TX ecc bad error!\
2844 (0x%x)",
2845 dev_name(dev), irq_value1);
2846
2847 hisi_sas_phy_write32(hisi_hba, phy_no,
2848 CHL_INT1, irq_value1);
2849 }
2850
2851 if (irq_value2)
2852 hisi_sas_phy_write32(hisi_hba, phy_no,
2853 CHL_INT2, irq_value2);
2854
2855
2856 if (irq_value0) {
2857 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2858 phy_bcast_v2_hw(phy_no, hisi_hba);
2859
2860 hisi_sas_phy_write32(hisi_hba, phy_no,
2861 CHL_INT0, irq_value0
2862 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2863 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2864 & (~CHL_INT0_NOT_RDY_MSK));
2865 }
2866 }
2867 irq_msk &= ~(1 << phy_no);
2868 phy_no++;
2869 }
2870
2871 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2872
2873 return IRQ_HANDLED;
2874 }
2875
2876 static void
2877 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2878 {
2879 struct device *dev = hisi_hba->dev;
2880 const struct hisi_sas_hw_error *ecc_error;
2881 u32 val;
2882 int i;
2883
2884 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2885 ecc_error = &one_bit_ecc_errors[i];
2886 if (irq_value & ecc_error->irq_msk) {
2887 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2888 val &= ecc_error->msk;
2889 val >>= ecc_error->shift;
2890 dev_warn(dev, ecc_error->msg, val);
2891 }
2892 }
2893 }
2894
2895 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2896 u32 irq_value)
2897 {
2898 struct device *dev = hisi_hba->dev;
2899 const struct hisi_sas_hw_error *ecc_error;
2900 u32 val;
2901 int i;
2902
2903 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2904 ecc_error = &multi_bit_ecc_errors[i];
2905 if (irq_value & ecc_error->irq_msk) {
2906 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2907 val &= ecc_error->msk;
2908 val >>= ecc_error->shift;
2909 dev_warn(dev, ecc_error->msg, irq_value, val);
2910 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2911 }
2912 }
2913
2914 return;
2915 }
2916
2917 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2918 {
2919 struct hisi_hba *hisi_hba = p;
2920 u32 irq_value, irq_msk;
2921
2922 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2923 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2924
2925 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2926 if (irq_value) {
2927 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2928 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2929 }
2930
2931 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2932 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2933
2934 return IRQ_HANDLED;
2935 }
2936
2937 static const struct hisi_sas_hw_error axi_error[] = {
2938 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2939 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2940 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2941 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2942 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2943 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2944 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2945 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2946 {},
2947 };
2948
2949 static const struct hisi_sas_hw_error fifo_error[] = {
2950 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
2951 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
2952 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
2953 { .msk = BIT(11), .msg = "CMDP_FIFO" },
2954 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2955 {},
2956 };
2957
2958 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
2959 {
2960 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2961 .msg = "write pointer and depth",
2962 },
2963 {
2964 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2965 .msg = "iptt no match slot",
2966 },
2967 {
2968 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2969 .msg = "read pointer and depth",
2970 },
2971 {
2972 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2973 .reg = HGC_AXI_FIFO_ERR_INFO,
2974 .sub = axi_error,
2975 },
2976 {
2977 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2978 .reg = HGC_AXI_FIFO_ERR_INFO,
2979 .sub = fifo_error,
2980 },
2981 {
2982 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2983 .msg = "LM add/fetch list",
2984 },
2985 {
2986 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2987 .msg = "SAS_HGC_ABT fetch LM list",
2988 },
2989 };
2990
2991 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2992 {
2993 struct hisi_hba *hisi_hba = p;
2994 u32 irq_value, irq_msk, err_value;
2995 struct device *dev = hisi_hba->dev;
2996 const struct hisi_sas_hw_error *axi_error;
2997 int i;
2998
2999 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3000 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3001
3002 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3003
3004 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3005 axi_error = &fatal_axi_errors[i];
3006 if (!(irq_value & axi_error->irq_msk))
3007 continue;
3008
3009 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3010 1 << axi_error->shift);
3011 if (axi_error->sub) {
3012 const struct hisi_sas_hw_error *sub = axi_error->sub;
3013
3014 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3015 for (; sub->msk || sub->msg; sub++) {
3016 if (!(err_value & sub->msk))
3017 continue;
3018 dev_warn(dev, "%s (0x%x) found!\n",
3019 sub->msg, irq_value);
3020 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3021 }
3022 } else {
3023 dev_warn(dev, "%s (0x%x) found!\n",
3024 axi_error->msg, irq_value);
3025 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3026 }
3027 }
3028
3029 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3030 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3031 u32 dev_id = reg_val & ITCT_DEV_MSK;
3032 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3033
3034 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3035 dev_dbg(dev, "clear ITCT ok\n");
3036 complete(sas_dev->completion);
3037 }
3038
3039 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3040 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3041
3042 return IRQ_HANDLED;
3043 }
3044
3045 static void cq_tasklet_v2_hw(unsigned long val)
3046 {
3047 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3048 struct hisi_hba *hisi_hba = cq->hisi_hba;
3049 struct hisi_sas_slot *slot;
3050 struct hisi_sas_itct *itct;
3051 struct hisi_sas_complete_v2_hdr *complete_queue;
3052 u32 rd_point = cq->rd_point, wr_point, dev_id;
3053 int queue = cq->id;
3054 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3055
3056 if (unlikely(hisi_hba->reject_stp_links_msk))
3057 phys_try_accept_stp_links_v2_hw(hisi_hba);
3058
3059 complete_queue = hisi_hba->complete_hdr[queue];
3060
3061 spin_lock(&dq->lock);
3062 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3063 (0x14 * queue));
3064
3065 while (rd_point != wr_point) {
3066 struct hisi_sas_complete_v2_hdr *complete_hdr;
3067 int iptt;
3068
3069 complete_hdr = &complete_queue[rd_point];
3070
3071 /* Check for NCQ completion */
3072 if (complete_hdr->act) {
3073 u32 act_tmp = complete_hdr->act;
3074 int ncq_tag_count = ffs(act_tmp);
3075
3076 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3077 CMPLT_HDR_DEV_ID_OFF;
3078 itct = &hisi_hba->itct[dev_id];
3079
3080 /* The NCQ tags are held in the itct header */
3081 while (ncq_tag_count) {
3082 __le64 *ncq_tag = &itct->qw4_15[0];
3083
3084 ncq_tag_count -= 1;
3085 iptt = (ncq_tag[ncq_tag_count / 5]
3086 >> (ncq_tag_count % 5) * 12) & 0xfff;
3087
3088 slot = &hisi_hba->slot_info[iptt];
3089 slot->cmplt_queue_slot = rd_point;
3090 slot->cmplt_queue = queue;
3091 slot_complete_v2_hw(hisi_hba, slot);
3092
3093 act_tmp &= ~(1 << ncq_tag_count);
3094 ncq_tag_count = ffs(act_tmp);
3095 }
3096 } else {
3097 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3098 slot = &hisi_hba->slot_info[iptt];
3099 slot->cmplt_queue_slot = rd_point;
3100 slot->cmplt_queue = queue;
3101 slot_complete_v2_hw(hisi_hba, slot);
3102 }
3103
3104 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3105 rd_point = 0;
3106 }
3107
3108 /* update rd_point */
3109 cq->rd_point = rd_point;
3110 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3111 spin_unlock(&dq->lock);
3112 }
3113
3114 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3115 {
3116 struct hisi_sas_cq *cq = p;
3117 struct hisi_hba *hisi_hba = cq->hisi_hba;
3118 int queue = cq->id;
3119
3120 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3121
3122 tasklet_schedule(&cq->tasklet);
3123
3124 return IRQ_HANDLED;
3125 }
3126
3127 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3128 {
3129 struct hisi_sas_phy *phy = p;
3130 struct hisi_hba *hisi_hba = phy->hisi_hba;
3131 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3132 struct device *dev = hisi_hba->dev;
3133 struct hisi_sas_initial_fis *initial_fis;
3134 struct dev_to_host_fis *fis;
3135 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3136 irqreturn_t res = IRQ_HANDLED;
3137 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3138 int phy_no, offset;
3139
3140 phy_no = sas_phy->id;
3141 initial_fis = &hisi_hba->initial_fis[phy_no];
3142 fis = &initial_fis->fis;
3143
3144 offset = 4 * (phy_no / 4);
3145 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3146 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3147 ent_msk | 1 << ((phy_no % 4) * 8));
3148
3149 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3150 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3151 (phy_no % 4)));
3152 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3153 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3154 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3155 res = IRQ_NONE;
3156 goto end;
3157 }
3158
3159 /* check ERR bit of Status Register */
3160 if (fis->status & ATA_ERR) {
3161 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3162 fis->status);
3163 disable_phy_v2_hw(hisi_hba, phy_no);
3164 enable_phy_v2_hw(hisi_hba, phy_no);
3165 res = IRQ_NONE;
3166 goto end;
3167 }
3168
3169 if (unlikely(phy_no == 8)) {
3170 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3171
3172 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3173 PORT_STATE_PHY8_PORT_NUM_OFF;
3174 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3175 PORT_STATE_PHY8_CONN_RATE_OFF;
3176 } else {
3177 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3178 port_id = (port_id >> (4 * phy_no)) & 0xf;
3179 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3180 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3181 }
3182
3183 if (port_id == 0xf) {
3184 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3185 res = IRQ_NONE;
3186 goto end;
3187 }
3188
3189 sas_phy->linkrate = link_rate;
3190 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3191 HARD_PHY_LINKRATE);
3192 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3193 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3194
3195 sas_phy->oob_mode = SATA_OOB_MODE;
3196 /* Make up some unique SAS address */
3197 attached_sas_addr[0] = 0x50;
3198 attached_sas_addr[7] = phy_no;
3199 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3200 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3201 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3202 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3203 phy->port_id = port_id;
3204 phy->phy_type |= PORT_TYPE_SATA;
3205 phy->phy_attached = 1;
3206 phy->identify.device_type = SAS_SATA_DEV;
3207 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3208 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3209 queue_work(hisi_hba->wq, &phy->phyup_ws);
3210
3211 end:
3212 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3213 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3214
3215 return res;
3216 }
3217
3218 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3219 int_phy_updown_v2_hw,
3220 int_chnl_int_v2_hw,
3221 };
3222
3223 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3224 fatal_ecc_int_v2_hw,
3225 fatal_axi_int_v2_hw
3226 };
3227
3228 /**
3229 * There is a limitation in the hip06 chipset that we need
3230 * to map in all mbigen interrupts, even if they are not used.
3231 */
3232 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3233 {
3234 struct platform_device *pdev = hisi_hba->platform_dev;
3235 struct device *dev = &pdev->dev;
3236 int irq, rc, irq_map[128];
3237 int i, phy_no, fatal_no, queue_no, k;
3238
3239 for (i = 0; i < 128; i++)
3240 irq_map[i] = platform_get_irq(pdev, i);
3241
3242 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3243 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3244 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3245 DRV_NAME " phy", hisi_hba);
3246 if (rc) {
3247 dev_err(dev, "irq init: could not request "
3248 "phy interrupt %d, rc=%d\n",
3249 irq, rc);
3250 rc = -ENOENT;
3251 goto free_phy_int_irqs;
3252 }
3253 }
3254
3255 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3256 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3257
3258 irq = irq_map[phy_no + 72];
3259 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3260 DRV_NAME " sata", phy);
3261 if (rc) {
3262 dev_err(dev, "irq init: could not request "
3263 "sata interrupt %d, rc=%d\n",
3264 irq, rc);
3265 rc = -ENOENT;
3266 goto free_sata_int_irqs;
3267 }
3268 }
3269
3270 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3271 irq = irq_map[fatal_no + 81];
3272 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3273 DRV_NAME " fatal", hisi_hba);
3274 if (rc) {
3275 dev_err(dev,
3276 "irq init: could not request fatal interrupt %d, rc=%d\n",
3277 irq, rc);
3278 rc = -ENOENT;
3279 goto free_fatal_int_irqs;
3280 }
3281 }
3282
3283 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3284 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3285 struct tasklet_struct *t = &cq->tasklet;
3286
3287 irq = irq_map[queue_no + 96];
3288 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3289 DRV_NAME " cq", cq);
3290 if (rc) {
3291 dev_err(dev,
3292 "irq init: could not request cq interrupt %d, rc=%d\n",
3293 irq, rc);
3294 rc = -ENOENT;
3295 goto free_cq_int_irqs;
3296 }
3297 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3298 }
3299
3300 return 0;
3301
3302 free_cq_int_irqs:
3303 for (k = 0; k < queue_no; k++) {
3304 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3305
3306 free_irq(irq_map[k + 96], cq);
3307 tasklet_kill(&cq->tasklet);
3308 }
3309 free_fatal_int_irqs:
3310 for (k = 0; k < fatal_no; k++)
3311 free_irq(irq_map[k + 81], hisi_hba);
3312 free_sata_int_irqs:
3313 for (k = 0; k < phy_no; k++) {
3314 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3315
3316 free_irq(irq_map[k + 72], phy);
3317 }
3318 free_phy_int_irqs:
3319 for (k = 0; k < i; k++)
3320 free_irq(irq_map[k + 1], hisi_hba);
3321 return rc;
3322 }
3323
3324 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3325 {
3326 int rc;
3327
3328 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3329
3330 rc = hw_init_v2_hw(hisi_hba);
3331 if (rc)
3332 return rc;
3333
3334 rc = interrupt_init_v2_hw(hisi_hba);
3335 if (rc)
3336 return rc;
3337
3338 return 0;
3339 }
3340
3341 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3342 {
3343 struct platform_device *pdev = hisi_hba->platform_dev;
3344 int i;
3345
3346 for (i = 0; i < hisi_hba->queue_count; i++)
3347 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3348
3349 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3350 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3351 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3352 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3353
3354 for (i = 0; i < hisi_hba->n_phy; i++) {
3355 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3356 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3357 }
3358
3359 for (i = 0; i < 128; i++)
3360 synchronize_irq(platform_get_irq(pdev, i));
3361 }
3362
3363
3364 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3365 {
3366 return hisi_sas_read32(hisi_hba, PHY_STATE);
3367 }
3368
3369 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3370 {
3371 struct device *dev = hisi_hba->dev;
3372 int rc, cnt;
3373
3374 interrupt_disable_v2_hw(hisi_hba);
3375 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3376 hisi_sas_kill_tasklets(hisi_hba);
3377
3378 hisi_sas_stop_phys(hisi_hba);
3379
3380 mdelay(10);
3381
3382 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3383
3384 /* wait until bus idle */
3385 cnt = 0;
3386 while (1) {
3387 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3388 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3389
3390 if (status == 0x3)
3391 break;
3392
3393 udelay(10);
3394 if (cnt++ > 10) {
3395 dev_info(dev, "wait axi bus state to idle timeout!\n");
3396 return -1;
3397 }
3398 }
3399
3400 hisi_sas_init_mem(hisi_hba);
3401
3402 rc = hw_init_v2_hw(hisi_hba);
3403 if (rc)
3404 return rc;
3405
3406 phys_reject_stp_links_v2_hw(hisi_hba);
3407
3408 return 0;
3409 }
3410
3411 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3412 .hw_init = hisi_sas_v2_init,
3413 .setup_itct = setup_itct_v2_hw,
3414 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3415 .alloc_dev = alloc_dev_quirk_v2_hw,
3416 .sl_notify = sl_notify_v2_hw,
3417 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3418 .free_device = free_device_v2_hw,
3419 .prep_smp = prep_smp_v2_hw,
3420 .prep_ssp = prep_ssp_v2_hw,
3421 .prep_stp = prep_ata_v2_hw,
3422 .prep_abort = prep_abort_v2_hw,
3423 .get_free_slot = get_free_slot_v2_hw,
3424 .start_delivery = start_delivery_v2_hw,
3425 .slot_complete = slot_complete_v2_hw,
3426 .phys_init = phys_init_v2_hw,
3427 .phy_start = start_phy_v2_hw,
3428 .phy_disable = disable_phy_v2_hw,
3429 .phy_hard_reset = phy_hard_reset_v2_hw,
3430 .get_events = phy_get_events_v2_hw,
3431 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3432 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3433 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3434 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3435 .soft_reset = soft_reset_v2_hw,
3436 .get_phys_state = get_phys_state_v2_hw,
3437 };
3438
3439 static int hisi_sas_v2_probe(struct platform_device *pdev)
3440 {
3441 /*
3442 * Check if we should defer the probe before we probe the
3443 * upper layer, as it's hard to defer later on.
3444 */
3445 int ret = platform_get_irq(pdev, 0);
3446
3447 if (ret < 0) {
3448 if (ret != -EPROBE_DEFER)
3449 dev_err(&pdev->dev, "cannot obtain irq\n");
3450 return ret;
3451 }
3452
3453 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3454 }
3455
3456 static int hisi_sas_v2_remove(struct platform_device *pdev)
3457 {
3458 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3459 struct hisi_hba *hisi_hba = sha->lldd_ha;
3460
3461 if (timer_pending(&hisi_hba->timer))
3462 del_timer(&hisi_hba->timer);
3463
3464 hisi_sas_kill_tasklets(hisi_hba);
3465
3466 return hisi_sas_remove(pdev);
3467 }
3468
3469 static const struct of_device_id sas_v2_of_match[] = {
3470 { .compatible = "hisilicon,hip06-sas-v2",},
3471 { .compatible = "hisilicon,hip07-sas-v2",},
3472 {},
3473 };
3474 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3475
3476 static const struct acpi_device_id sas_v2_acpi_match[] = {
3477 { "HISI0162", 0 },
3478 { }
3479 };
3480
3481 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3482
3483 static struct platform_driver hisi_sas_v2_driver = {
3484 .probe = hisi_sas_v2_probe,
3485 .remove = hisi_sas_v2_remove,
3486 .driver = {
3487 .name = DRV_NAME,
3488 .of_match_table = sas_v2_of_match,
3489 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3490 },
3491 };
3492
3493 module_platform_driver(hisi_sas_v2_driver);
3494
3495 MODULE_LICENSE("GPL");
3496 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3497 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3498 MODULE_ALIAS("platform:" DRV_NAME);
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