1 // SPDX-License-Identifier: GPL-2.0+
3 * Application UART driver for:
4 * Freescale STMP37XX/STMP378X
7 * Author: dmitry pervushin <dimka@embeddedalley.com>
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
10 * Provide Alphascale ASM9260 support.
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
15 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/wait.h>
27 #include <linux/tty.h>
28 #include <linux/tty_driver.h>
29 #include <linux/tty_flip.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/platform_device.h>
33 #include <linux/device.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
37 #include <linux/of_device.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
41 #include <asm/cacheflush.h>
43 #include <linux/gpio.h>
44 #include <linux/gpio/consumer.h>
45 #include <linux/err.h>
46 #include <linux/irq.h>
47 #include "serial_mctrl_gpio.h"
49 #define MXS_AUART_PORTS 5
50 #define MXS_AUART_FIFO_SIZE 16
56 #define AUART_CTRL0 0x00000000
57 #define AUART_CTRL1 0x00000010
58 #define AUART_CTRL2 0x00000020
59 #define AUART_LINECTRL 0x00000030
60 #define AUART_LINECTRL2 0x00000040
61 #define AUART_INTR 0x00000050
62 #define AUART_DATA 0x00000060
63 #define AUART_STAT 0x00000070
64 #define AUART_DEBUG 0x00000080
65 #define AUART_VERSION 0x00000090
66 #define AUART_AUTOBAUD 0x000000a0
68 #define AUART_CTRL0_SFTRST (1 << 31)
69 #define AUART_CTRL0_CLKGATE (1 << 30)
70 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
71 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
72 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
74 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
76 #define AUART_CTRL2_DMAONERR (1 << 26)
77 #define AUART_CTRL2_TXDMAE (1 << 25)
78 #define AUART_CTRL2_RXDMAE (1 << 24)
80 #define AUART_CTRL2_CTSEN (1 << 15)
81 #define AUART_CTRL2_RTSEN (1 << 14)
82 #define AUART_CTRL2_RTS (1 << 11)
83 #define AUART_CTRL2_RXE (1 << 9)
84 #define AUART_CTRL2_TXE (1 << 8)
85 #define AUART_CTRL2_UARTEN (1 << 0)
87 #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
88 #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
89 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
90 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
91 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
92 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
93 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
94 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
95 #define AUART_LINECTRL_SPS (1 << 7)
96 #define AUART_LINECTRL_WLEN_MASK 0x00000060
97 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
98 #define AUART_LINECTRL_FEN (1 << 4)
99 #define AUART_LINECTRL_STP2 (1 << 3)
100 #define AUART_LINECTRL_EPS (1 << 2)
101 #define AUART_LINECTRL_PEN (1 << 1)
102 #define AUART_LINECTRL_BRK (1 << 0)
104 #define AUART_INTR_RTIEN (1 << 22)
105 #define AUART_INTR_TXIEN (1 << 21)
106 #define AUART_INTR_RXIEN (1 << 20)
107 #define AUART_INTR_CTSMIEN (1 << 17)
108 #define AUART_INTR_RTIS (1 << 6)
109 #define AUART_INTR_TXIS (1 << 5)
110 #define AUART_INTR_RXIS (1 << 4)
111 #define AUART_INTR_CTSMIS (1 << 1)
113 #define AUART_STAT_BUSY (1 << 29)
114 #define AUART_STAT_CTS (1 << 28)
115 #define AUART_STAT_TXFE (1 << 27)
116 #define AUART_STAT_TXFF (1 << 25)
117 #define AUART_STAT_RXFE (1 << 24)
118 #define AUART_STAT_OERR (1 << 19)
119 #define AUART_STAT_BERR (1 << 18)
120 #define AUART_STAT_PERR (1 << 17)
121 #define AUART_STAT_FERR (1 << 16)
122 #define AUART_STAT_RXCOUNT_MASK 0xffff
125 * Start of Alphascale asm9260 defines
126 * This list contains only differences of existing bits
127 * between imx2x and asm9260
129 #define ASM9260_HW_CTRL0 0x0000
131 * RW. Tell the UART to execute the RX DMA Command. The
132 * UART will clear this bit at the end of receive execution.
134 #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
135 /* RW. 0 use FIFO for status register; 1 use DMA */
136 #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
138 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
139 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
140 * operation. If this bit is set to 1, a receive timeout will cause the receive
141 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
143 #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
145 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
146 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
147 * input is idle, then the watchdog counter will decrement each bit-time. Note
148 * 7-bit-time is added to the programmed value, so a value of zero will set
149 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
150 * note that the counter is reloaded at the end of each frame, so if the frame
151 * is 10 bits long and the timeout counter value is zero, then timeout will
152 * occur (when FIFO is not empty) even if the RX input is not idle. The default
153 * value is 0x3 (31 bit-time).
155 #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
156 /* TIMEOUT = (100*7+1)*(1/BAUD) */
157 #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
159 /* TX ctrl register */
160 #define ASM9260_HW_CTRL1 0x0010
162 * RW. Tell the UART to execute the TX DMA Command. The
163 * UART will clear this bit at the end of transmit execution.
165 #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
167 #define ASM9260_HW_CTRL2 0x0020
169 * RW. Receive Interrupt FIFO Level Select.
170 * The trigger points for the receive interrupt are as follows:
171 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
172 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
173 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
174 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
175 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
177 #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
178 #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
179 /* RW. Same as RXIFLSEL */
180 #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
181 #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
182 /* RW. Set DTR. When this bit is 1, the output is 0. */
183 #define ASM9260_BM_CTRL2_DTR BIT(10)
184 /* RW. Loop Back Enable */
185 #define ASM9260_BM_CTRL2_LBE BIT(7)
186 #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
188 #define ASM9260_HW_LINECTRL 0x0030
190 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
191 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
192 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
193 * bit is cleared stick parity is disabled.
195 #define ASM9260_BM_LCTRL_SPS BIT(7)
196 /* RW. Word length */
197 #define ASM9260_BM_LCTRL_WLEN (3 << 5)
198 #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
199 #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
200 #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
201 #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
204 * Interrupt register.
205 * contains the interrupt enables and the interrupt status bits
207 #define ASM9260_HW_INTR 0x0040
208 /* Tx FIFO EMPTY Raw Interrupt enable */
209 #define ASM9260_BM_INTR_TFEIEN BIT(27)
210 /* Overrun Error Interrupt Enable. */
211 #define ASM9260_BM_INTR_OEIEN BIT(26)
212 /* Break Error Interrupt Enable. */
213 #define ASM9260_BM_INTR_BEIEN BIT(25)
214 /* Parity Error Interrupt Enable. */
215 #define ASM9260_BM_INTR_PEIEN BIT(24)
216 /* Framing Error Interrupt Enable. */
217 #define ASM9260_BM_INTR_FEIEN BIT(23)
219 /* nUARTDSR Modem Interrupt Enable. */
220 #define ASM9260_BM_INTR_DSRMIEN BIT(19)
221 /* nUARTDCD Modem Interrupt Enable. */
222 #define ASM9260_BM_INTR_DCDMIEN BIT(18)
223 /* nUARTRI Modem Interrupt Enable. */
224 #define ASM9260_BM_INTR_RIMIEN BIT(16)
225 /* Auto-Boud Timeout */
226 #define ASM9260_BM_INTR_ABTO BIT(13)
227 #define ASM9260_BM_INTR_ABEO BIT(12)
228 /* Tx FIFO EMPTY Raw Interrupt state */
229 #define ASM9260_BM_INTR_TFEIS BIT(11)
231 #define ASM9260_BM_INTR_OEIS BIT(10)
233 #define ASM9260_BM_INTR_BEIS BIT(9)
235 #define ASM9260_BM_INTR_PEIS BIT(8)
237 #define ASM9260_BM_INTR_FEIS BIT(7)
238 #define ASM9260_BM_INTR_DSRMIS BIT(3)
239 #define ASM9260_BM_INTR_DCDMIS BIT(2)
240 #define ASM9260_BM_INTR_RIMIS BIT(0)
243 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
244 * time. In PIO mode, only one character can be accessed at a time. The status
245 * register contains the receive data flags and valid bits.
247 #define ASM9260_HW_DATA 0x0050
249 #define ASM9260_HW_STAT 0x0060
250 /* RO. If 1, UARTAPP is present in this product. */
251 #define ASM9260_BM_STAT_PRESENT BIT(31)
252 /* RO. If 1, HISPEED is present in this product. */
253 #define ASM9260_BM_STAT_HISPEED BIT(30)
254 /* RO. Receive FIFO Full. */
255 #define ASM9260_BM_STAT_RXFULL BIT(26)
257 /* RO. The UART Debug Register contains the state of the DMA signals. */
258 #define ASM9260_HW_DEBUG 0x0070
259 /* DMA Command Run Status */
260 #define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
261 #define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
262 /* DMA Command End Status */
263 #define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
264 #define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
265 /* DMA Request Status */
266 #define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
267 #define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
269 #define ASM9260_HW_ILPR 0x0080
271 #define ASM9260_HW_RS485CTRL 0x0090
273 * RW. This bit reverses the polarity of the direction control signal on the RTS
275 * If 0, The direction control pin will be driven to logic ‘0’ when the
276 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
277 * last bit of data has been transmitted.
279 #define ASM9260_BM_RS485CTRL_ONIV BIT(5)
280 /* RW. Enable Auto Direction Control. */
281 #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
283 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
284 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
286 #define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
287 /* RW. Enable Auto Address Detect (AAD). */
288 #define ASM9260_BM_RS485CTRL_AADEN BIT(2)
289 /* RW. Disable receiver. */
290 #define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
291 /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
292 #define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
294 #define ASM9260_HW_RS485ADRMATCH 0x00a0
295 /* Contains the address match value. */
296 #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
298 #define ASM9260_HW_RS485DLY 0x00b0
300 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
301 * is in periods of the baud clock.
303 #define ASM9260_BM_RS485DLY_MASK (0xff << 0)
305 #define ASM9260_HW_AUTOBAUD 0x00c0
306 /* WO. Auto-baud time-out interrupt clear bit. */
307 #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
308 /* WO. End of auto-baud interrupt clear bit. */
309 #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
310 /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
311 #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
312 /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
313 #define ASM9260_BM_AUTOBAUD_MODE BIT(1)
315 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
316 * automatically cleared after auto-baud completion.
318 #define ASM9260_BM_AUTOBAUD_START BIT(0)
320 #define ASM9260_HW_CTRL3 0x00d0
321 #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
323 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
326 #define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
327 /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
328 #define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
329 /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
330 #define ASM9260_BM_CTRL3_MSBF BIT(2)
331 /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
332 #define ASM9260_BM_CTRL3_BAUD8 BIT(1)
333 /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
334 #define ASM9260_BM_CTRL3_9BIT BIT(0)
336 #define ASM9260_HW_ISO7816_CTRL 0x00e0
337 /* RW. Enable High Speed mode. */
338 #define ASM9260_BM_ISO7816CTRL_HS BIT(12)
339 /* Disable Successive Receive NACK */
340 #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
341 #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
342 /* Receive NACK Inhibit */
343 #define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
344 #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
345 /* RW. 1 - ISO7816 mode; 0 - USART mode */
346 #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
348 #define ASM9260_HW_ISO7816_ERRCNT 0x00f0
349 /* Parity error counter. Will be cleared after reading */
350 #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
352 #define ASM9260_HW_ISO7816_STATUS 0x0100
353 /* Max number of Repetitions Reached */
354 #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
356 /* End of Alphascale asm9260 defines */
358 static struct uart_driver auart_driver
;
360 enum mxs_auart_type
{
367 const u16
*reg_offset
;
383 /* The size of the array - must be last */
387 static const u16 mxs_asm9260_offsets
[REG_ARRAY_SIZE
] = {
388 [REG_CTRL0
] = ASM9260_HW_CTRL0
,
389 [REG_CTRL1
] = ASM9260_HW_CTRL1
,
390 [REG_CTRL2
] = ASM9260_HW_CTRL2
,
391 [REG_LINECTRL
] = ASM9260_HW_LINECTRL
,
392 [REG_INTR
] = ASM9260_HW_INTR
,
393 [REG_DATA
] = ASM9260_HW_DATA
,
394 [REG_STAT
] = ASM9260_HW_STAT
,
395 [REG_DEBUG
] = ASM9260_HW_DEBUG
,
396 [REG_AUTOBAUD
] = ASM9260_HW_AUTOBAUD
,
399 static const u16 mxs_stmp37xx_offsets
[REG_ARRAY_SIZE
] = {
400 [REG_CTRL0
] = AUART_CTRL0
,
401 [REG_CTRL1
] = AUART_CTRL1
,
402 [REG_CTRL2
] = AUART_CTRL2
,
403 [REG_LINECTRL
] = AUART_LINECTRL
,
404 [REG_LINECTRL2
] = AUART_LINECTRL2
,
405 [REG_INTR
] = AUART_INTR
,
406 [REG_DATA
] = AUART_DATA
,
407 [REG_STAT
] = AUART_STAT
,
408 [REG_DEBUG
] = AUART_DEBUG
,
409 [REG_VERSION
] = AUART_VERSION
,
410 [REG_AUTOBAUD
] = AUART_AUTOBAUD
,
413 static const struct vendor_data vendor_alphascale_asm9260
= {
414 .reg_offset
= mxs_asm9260_offsets
,
417 static const struct vendor_data vendor_freescale_stmp37xx
= {
418 .reg_offset
= mxs_stmp37xx_offsets
,
421 struct mxs_auart_port
{
422 struct uart_port port
;
424 #define MXS_AUART_DMA_ENABLED 0x2
425 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
426 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
427 #define MXS_AUART_RTSCTS 4 /* bit 4 */
429 unsigned int mctrl_prev
;
430 enum mxs_auart_type devtype
;
431 const struct vendor_data
*vendor
;
438 struct scatterlist tx_sgl
;
439 struct dma_chan
*tx_dma_chan
;
442 struct scatterlist rx_sgl
;
443 struct dma_chan
*rx_dma_chan
;
446 struct mctrl_gpios
*gpios
;
447 int gpio_irq
[UART_GPIO_MAX
];
451 static const struct platform_device_id mxs_auart_devtype
[] = {
452 { .name
= "mxs-auart-imx23", .driver_data
= IMX23_AUART
},
453 { .name
= "mxs-auart-imx28", .driver_data
= IMX28_AUART
},
454 { .name
= "as-auart-asm9260", .driver_data
= ASM9260_AUART
},
457 MODULE_DEVICE_TABLE(platform
, mxs_auart_devtype
);
459 static const struct of_device_id mxs_auart_dt_ids
[] = {
461 .compatible
= "fsl,imx28-auart",
462 .data
= &mxs_auart_devtype
[IMX28_AUART
]
464 .compatible
= "fsl,imx23-auart",
465 .data
= &mxs_auart_devtype
[IMX23_AUART
]
467 .compatible
= "alphascale,asm9260-auart",
468 .data
= &mxs_auart_devtype
[ASM9260_AUART
]
469 }, { /* sentinel */ }
471 MODULE_DEVICE_TABLE(of
, mxs_auart_dt_ids
);
473 static inline int is_imx28_auart(struct mxs_auart_port
*s
)
475 return s
->devtype
== IMX28_AUART
;
478 static inline int is_asm9260_auart(struct mxs_auart_port
*s
)
480 return s
->devtype
== ASM9260_AUART
;
483 static inline bool auart_dma_enabled(struct mxs_auart_port
*s
)
485 return s
->flags
& MXS_AUART_DMA_ENABLED
;
488 static unsigned int mxs_reg_to_offset(const struct mxs_auart_port
*uap
,
491 return uap
->vendor
->reg_offset
[reg
];
494 static unsigned int mxs_read(const struct mxs_auart_port
*uap
,
497 void __iomem
*addr
= uap
->port
.membase
+ mxs_reg_to_offset(uap
, reg
);
499 return readl_relaxed(addr
);
502 static void mxs_write(unsigned int val
, struct mxs_auart_port
*uap
,
505 void __iomem
*addr
= uap
->port
.membase
+ mxs_reg_to_offset(uap
, reg
);
507 writel_relaxed(val
, addr
);
510 static void mxs_set(unsigned int val
, struct mxs_auart_port
*uap
,
513 void __iomem
*addr
= uap
->port
.membase
+ mxs_reg_to_offset(uap
, reg
);
515 writel_relaxed(val
, addr
+ SET_REG
);
518 static void mxs_clr(unsigned int val
, struct mxs_auart_port
*uap
,
521 void __iomem
*addr
= uap
->port
.membase
+ mxs_reg_to_offset(uap
, reg
);
523 writel_relaxed(val
, addr
+ CLR_REG
);
526 static void mxs_auart_stop_tx(struct uart_port
*u
);
528 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
530 static void mxs_auart_tx_chars(struct mxs_auart_port
*s
);
532 static void dma_tx_callback(void *param
)
534 struct mxs_auart_port
*s
= param
;
535 struct circ_buf
*xmit
= &s
->port
.state
->xmit
;
537 dma_unmap_sg(s
->dev
, &s
->tx_sgl
, 1, DMA_TO_DEVICE
);
539 /* clear the bit used to serialize the DMA tx. */
540 clear_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
);
541 smp_mb__after_atomic();
543 /* wake up the possible processes. */
544 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
545 uart_write_wakeup(&s
->port
);
547 mxs_auart_tx_chars(s
);
550 static int mxs_auart_dma_tx(struct mxs_auart_port
*s
, int size
)
552 struct dma_async_tx_descriptor
*desc
;
553 struct scatterlist
*sgl
= &s
->tx_sgl
;
554 struct dma_chan
*channel
= s
->tx_dma_chan
;
557 /* [1] : send PIO. Note, the first pio word is CTRL1. */
558 pio
= AUART_CTRL1_XFER_COUNT(size
);
559 desc
= dmaengine_prep_slave_sg(channel
, (struct scatterlist
*)&pio
,
560 1, DMA_TRANS_NONE
, 0);
562 dev_err(s
->dev
, "step 1 error\n");
566 /* [2] : set DMA buffer. */
567 sg_init_one(sgl
, s
->tx_dma_buf
, size
);
568 dma_map_sg(s
->dev
, sgl
, 1, DMA_TO_DEVICE
);
569 desc
= dmaengine_prep_slave_sg(channel
, sgl
,
570 1, DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
572 dev_err(s
->dev
, "step 2 error\n");
576 /* [3] : submit the DMA */
577 desc
->callback
= dma_tx_callback
;
578 desc
->callback_param
= s
;
579 dmaengine_submit(desc
);
580 dma_async_issue_pending(channel
);
584 static void mxs_auart_tx_chars(struct mxs_auart_port
*s
)
586 struct circ_buf
*xmit
= &s
->port
.state
->xmit
;
588 if (auart_dma_enabled(s
)) {
591 void *buffer
= s
->tx_dma_buf
;
593 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
))
596 while (!uart_circ_empty(xmit
) && !uart_tx_stopped(&s
->port
)) {
597 size
= min_t(u32
, UART_XMIT_SIZE
- i
,
598 CIRC_CNT_TO_END(xmit
->head
,
601 memcpy(buffer
+ i
, xmit
->buf
+ xmit
->tail
, size
);
602 xmit
->tail
= (xmit
->tail
+ size
) & (UART_XMIT_SIZE
- 1);
605 if (i
>= UART_XMIT_SIZE
)
609 if (uart_tx_stopped(&s
->port
))
610 mxs_auart_stop_tx(&s
->port
);
613 mxs_auart_dma_tx(s
, i
);
615 clear_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
);
616 smp_mb__after_atomic();
622 while (!(mxs_read(s
, REG_STAT
) & AUART_STAT_TXFF
)) {
623 if (s
->port
.x_char
) {
625 mxs_write(s
->port
.x_char
, s
, REG_DATA
);
629 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&s
->port
)) {
631 mxs_write(xmit
->buf
[xmit
->tail
], s
, REG_DATA
);
632 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
636 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
637 uart_write_wakeup(&s
->port
);
639 if (uart_circ_empty(&(s
->port
.state
->xmit
)))
640 mxs_clr(AUART_INTR_TXIEN
, s
, REG_INTR
);
642 mxs_set(AUART_INTR_TXIEN
, s
, REG_INTR
);
644 if (uart_tx_stopped(&s
->port
))
645 mxs_auart_stop_tx(&s
->port
);
648 static void mxs_auart_rx_char(struct mxs_auart_port
*s
)
654 c
= mxs_read(s
, REG_DATA
);
655 stat
= mxs_read(s
, REG_STAT
);
660 if (stat
& AUART_STAT_BERR
) {
661 s
->port
.icount
.brk
++;
662 if (uart_handle_break(&s
->port
))
664 } else if (stat
& AUART_STAT_PERR
) {
665 s
->port
.icount
.parity
++;
666 } else if (stat
& AUART_STAT_FERR
) {
667 s
->port
.icount
.frame
++;
671 * Mask off conditions which should be ingored.
673 stat
&= s
->port
.read_status_mask
;
675 if (stat
& AUART_STAT_BERR
) {
677 } else if (stat
& AUART_STAT_PERR
)
679 else if (stat
& AUART_STAT_FERR
)
682 if (stat
& AUART_STAT_OERR
)
683 s
->port
.icount
.overrun
++;
685 if (uart_handle_sysrq_char(&s
->port
, c
))
688 uart_insert_char(&s
->port
, stat
, AUART_STAT_OERR
, c
, flag
);
690 mxs_write(stat
, s
, REG_STAT
);
693 static void mxs_auart_rx_chars(struct mxs_auart_port
*s
)
698 stat
= mxs_read(s
, REG_STAT
);
699 if (stat
& AUART_STAT_RXFE
)
701 mxs_auart_rx_char(s
);
704 mxs_write(stat
, s
, REG_STAT
);
705 tty_flip_buffer_push(&s
->port
.state
->port
);
708 static int mxs_auart_request_port(struct uart_port
*u
)
713 static int mxs_auart_verify_port(struct uart_port
*u
,
714 struct serial_struct
*ser
)
716 if (u
->type
!= PORT_UNKNOWN
&& u
->type
!= PORT_IMX
)
721 static void mxs_auart_config_port(struct uart_port
*u
, int flags
)
725 static const char *mxs_auart_type(struct uart_port
*u
)
727 struct mxs_auart_port
*s
= to_auart_port(u
);
729 return dev_name(s
->dev
);
732 static void mxs_auart_release_port(struct uart_port
*u
)
736 static void mxs_auart_set_mctrl(struct uart_port
*u
, unsigned mctrl
)
738 struct mxs_auart_port
*s
= to_auart_port(u
);
740 u32 ctrl
= mxs_read(s
, REG_CTRL2
);
742 ctrl
&= ~(AUART_CTRL2_RTSEN
| AUART_CTRL2_RTS
);
743 if (mctrl
& TIOCM_RTS
) {
744 if (uart_cts_enabled(u
))
745 ctrl
|= AUART_CTRL2_RTSEN
;
747 ctrl
|= AUART_CTRL2_RTS
;
750 mxs_write(ctrl
, s
, REG_CTRL2
);
752 mctrl_gpio_set(s
->gpios
, mctrl
);
755 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
756 static u32
mxs_auart_modem_status(struct mxs_auart_port
*s
, u32 mctrl
)
760 mctrl_diff
= mctrl
^ s
->mctrl_prev
;
761 s
->mctrl_prev
= mctrl
;
762 if (mctrl_diff
& MCTRL_ANY_DELTA
&& s
->ms_irq_enabled
&&
763 s
->port
.state
!= NULL
) {
764 if (mctrl_diff
& TIOCM_RI
)
765 s
->port
.icount
.rng
++;
766 if (mctrl_diff
& TIOCM_DSR
)
767 s
->port
.icount
.dsr
++;
768 if (mctrl_diff
& TIOCM_CD
)
769 uart_handle_dcd_change(&s
->port
, mctrl
& TIOCM_CD
);
770 if (mctrl_diff
& TIOCM_CTS
)
771 uart_handle_cts_change(&s
->port
, mctrl
& TIOCM_CTS
);
773 wake_up_interruptible(&s
->port
.state
->port
.delta_msr_wait
);
778 static u32
mxs_auart_get_mctrl(struct uart_port
*u
)
780 struct mxs_auart_port
*s
= to_auart_port(u
);
781 u32 stat
= mxs_read(s
, REG_STAT
);
784 if (stat
& AUART_STAT_CTS
)
787 return mctrl_gpio_get(s
->gpios
, &mctrl
);
791 * Enable modem status interrupts
793 static void mxs_auart_enable_ms(struct uart_port
*port
)
795 struct mxs_auart_port
*s
= to_auart_port(port
);
798 * Interrupt should not be enabled twice
800 if (s
->ms_irq_enabled
)
803 s
->ms_irq_enabled
= true;
805 if (s
->gpio_irq
[UART_GPIO_CTS
] >= 0)
806 enable_irq(s
->gpio_irq
[UART_GPIO_CTS
]);
807 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
809 if (s
->gpio_irq
[UART_GPIO_DSR
] >= 0)
810 enable_irq(s
->gpio_irq
[UART_GPIO_DSR
]);
812 if (s
->gpio_irq
[UART_GPIO_RI
] >= 0)
813 enable_irq(s
->gpio_irq
[UART_GPIO_RI
]);
815 if (s
->gpio_irq
[UART_GPIO_DCD
] >= 0)
816 enable_irq(s
->gpio_irq
[UART_GPIO_DCD
]);
820 * Disable modem status interrupts
822 static void mxs_auart_disable_ms(struct uart_port
*port
)
824 struct mxs_auart_port
*s
= to_auart_port(port
);
827 * Interrupt should not be disabled twice
829 if (!s
->ms_irq_enabled
)
832 s
->ms_irq_enabled
= false;
834 if (s
->gpio_irq
[UART_GPIO_CTS
] >= 0)
835 disable_irq(s
->gpio_irq
[UART_GPIO_CTS
]);
836 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
838 if (s
->gpio_irq
[UART_GPIO_DSR
] >= 0)
839 disable_irq(s
->gpio_irq
[UART_GPIO_DSR
]);
841 if (s
->gpio_irq
[UART_GPIO_RI
] >= 0)
842 disable_irq(s
->gpio_irq
[UART_GPIO_RI
]);
844 if (s
->gpio_irq
[UART_GPIO_DCD
] >= 0)
845 disable_irq(s
->gpio_irq
[UART_GPIO_DCD
]);
848 static int mxs_auart_dma_prep_rx(struct mxs_auart_port
*s
);
849 static void dma_rx_callback(void *arg
)
851 struct mxs_auart_port
*s
= (struct mxs_auart_port
*) arg
;
852 struct tty_port
*port
= &s
->port
.state
->port
;
856 dma_unmap_sg(s
->dev
, &s
->rx_sgl
, 1, DMA_FROM_DEVICE
);
858 stat
= mxs_read(s
, REG_STAT
);
859 stat
&= ~(AUART_STAT_OERR
| AUART_STAT_BERR
|
860 AUART_STAT_PERR
| AUART_STAT_FERR
);
862 count
= stat
& AUART_STAT_RXCOUNT_MASK
;
863 tty_insert_flip_string(port
, s
->rx_dma_buf
, count
);
865 mxs_write(stat
, s
, REG_STAT
);
866 tty_flip_buffer_push(port
);
868 /* start the next DMA for RX. */
869 mxs_auart_dma_prep_rx(s
);
872 static int mxs_auart_dma_prep_rx(struct mxs_auart_port
*s
)
874 struct dma_async_tx_descriptor
*desc
;
875 struct scatterlist
*sgl
= &s
->rx_sgl
;
876 struct dma_chan
*channel
= s
->rx_dma_chan
;
880 pio
[0] = AUART_CTRL0_RXTO_ENABLE
881 | AUART_CTRL0_RXTIMEOUT(0x80)
882 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE
);
883 desc
= dmaengine_prep_slave_sg(channel
, (struct scatterlist
*)pio
,
884 1, DMA_TRANS_NONE
, 0);
886 dev_err(s
->dev
, "step 1 error\n");
890 /* [2] : send DMA request */
891 sg_init_one(sgl
, s
->rx_dma_buf
, UART_XMIT_SIZE
);
892 dma_map_sg(s
->dev
, sgl
, 1, DMA_FROM_DEVICE
);
893 desc
= dmaengine_prep_slave_sg(channel
, sgl
, 1, DMA_DEV_TO_MEM
,
894 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
896 dev_err(s
->dev
, "step 2 error\n");
900 /* [3] : submit the DMA, but do not issue it. */
901 desc
->callback
= dma_rx_callback
;
902 desc
->callback_param
= s
;
903 dmaengine_submit(desc
);
904 dma_async_issue_pending(channel
);
908 static void mxs_auart_dma_exit_channel(struct mxs_auart_port
*s
)
910 if (s
->tx_dma_chan
) {
911 dma_release_channel(s
->tx_dma_chan
);
912 s
->tx_dma_chan
= NULL
;
914 if (s
->rx_dma_chan
) {
915 dma_release_channel(s
->rx_dma_chan
);
916 s
->rx_dma_chan
= NULL
;
919 kfree(s
->tx_dma_buf
);
920 kfree(s
->rx_dma_buf
);
921 s
->tx_dma_buf
= NULL
;
922 s
->rx_dma_buf
= NULL
;
925 static void mxs_auart_dma_exit(struct mxs_auart_port
*s
)
928 mxs_clr(AUART_CTRL2_TXDMAE
| AUART_CTRL2_RXDMAE
| AUART_CTRL2_DMAONERR
,
931 mxs_auart_dma_exit_channel(s
);
932 s
->flags
&= ~MXS_AUART_DMA_ENABLED
;
933 clear_bit(MXS_AUART_DMA_TX_SYNC
, &s
->flags
);
934 clear_bit(MXS_AUART_DMA_RX_READY
, &s
->flags
);
937 static int mxs_auart_dma_init(struct mxs_auart_port
*s
)
939 if (auart_dma_enabled(s
))
943 s
->rx_dma_chan
= dma_request_slave_channel(s
->dev
, "rx");
946 s
->rx_dma_buf
= kzalloc(UART_XMIT_SIZE
, GFP_KERNEL
| GFP_DMA
);
951 s
->tx_dma_chan
= dma_request_slave_channel(s
->dev
, "tx");
954 s
->tx_dma_buf
= kzalloc(UART_XMIT_SIZE
, GFP_KERNEL
| GFP_DMA
);
959 s
->flags
|= MXS_AUART_DMA_ENABLED
;
960 dev_dbg(s
->dev
, "enabled the DMA support.");
962 /* The DMA buffer is now the FIFO the TTY subsystem can use */
963 s
->port
.fifosize
= UART_XMIT_SIZE
;
968 mxs_auart_dma_exit_channel(s
);
973 #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
975 #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
977 static void mxs_auart_settermios(struct uart_port
*u
,
978 struct ktermios
*termios
,
979 struct ktermios
*old
)
981 struct mxs_auart_port
*s
= to_auart_port(u
);
982 u32 bm
, ctrl
, ctrl2
, div
;
983 unsigned int cflag
, baud
, baud_min
, baud_max
;
985 cflag
= termios
->c_cflag
;
987 ctrl
= AUART_LINECTRL_FEN
;
988 ctrl2
= mxs_read(s
, REG_CTRL2
);
991 switch (cflag
& CSIZE
) {
1008 ctrl
|= AUART_LINECTRL_WLEN(bm
);
1011 if (cflag
& PARENB
) {
1012 ctrl
|= AUART_LINECTRL_PEN
;
1013 if ((cflag
& PARODD
) == 0)
1014 ctrl
|= AUART_LINECTRL_EPS
;
1016 ctrl
|= AUART_LINECTRL_SPS
;
1019 u
->read_status_mask
= AUART_STAT_OERR
;
1021 if (termios
->c_iflag
& INPCK
)
1022 u
->read_status_mask
|= AUART_STAT_PERR
;
1023 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1024 u
->read_status_mask
|= AUART_STAT_BERR
;
1027 * Characters to ignore
1029 u
->ignore_status_mask
= 0;
1030 if (termios
->c_iflag
& IGNPAR
)
1031 u
->ignore_status_mask
|= AUART_STAT_PERR
;
1032 if (termios
->c_iflag
& IGNBRK
) {
1033 u
->ignore_status_mask
|= AUART_STAT_BERR
;
1035 * If we're ignoring parity and break indicators,
1036 * ignore overruns too (for real raw support).
1038 if (termios
->c_iflag
& IGNPAR
)
1039 u
->ignore_status_mask
|= AUART_STAT_OERR
;
1043 * ignore all characters if CREAD is not set
1046 ctrl2
|= AUART_CTRL2_RXE
;
1048 ctrl2
&= ~AUART_CTRL2_RXE
;
1050 /* figure out the stop bits requested */
1052 ctrl
|= AUART_LINECTRL_STP2
;
1054 /* figure out the hardware flow control settings */
1055 ctrl2
&= ~(AUART_CTRL2_CTSEN
| AUART_CTRL2_RTSEN
);
1056 if (cflag
& CRTSCTS
) {
1058 * The DMA has a bug(see errata:2836) in mx23.
1059 * So we can not implement the DMA for auart in mx23,
1060 * we can only implement the DMA support for auart
1063 if (is_imx28_auart(s
)
1064 && test_bit(MXS_AUART_RTSCTS
, &s
->flags
)) {
1065 if (!mxs_auart_dma_init(s
))
1066 /* enable DMA tranfer */
1067 ctrl2
|= AUART_CTRL2_TXDMAE
| AUART_CTRL2_RXDMAE
1068 | AUART_CTRL2_DMAONERR
;
1070 /* Even if RTS is GPIO line RTSEN can be enabled because
1071 * the pinctrl configuration decides about RTS pin function */
1072 ctrl2
|= AUART_CTRL2_RTSEN
;
1074 ctrl2
|= AUART_CTRL2_CTSEN
;
1078 if (is_asm9260_auart(s
)) {
1079 baud
= uart_get_baud_rate(u
, termios
, old
,
1080 u
->uartclk
* 4 / 0x3FFFFF,
1082 div
= u
->uartclk
* 4 / baud
;
1084 baud_min
= DIV_ROUND_UP(u
->uartclk
* 32,
1085 AUART_LINECTRL_BAUD_DIV_MAX
);
1086 baud_max
= u
->uartclk
* 32 / AUART_LINECTRL_BAUD_DIV_MIN
;
1087 baud
= uart_get_baud_rate(u
, termios
, old
, baud_min
, baud_max
);
1088 div
= DIV_ROUND_CLOSEST(u
->uartclk
* 32, baud
);
1091 ctrl
|= AUART_LINECTRL_BAUD_DIVFRAC(div
& 0x3F);
1092 ctrl
|= AUART_LINECTRL_BAUD_DIVINT(div
>> 6);
1093 mxs_write(ctrl
, s
, REG_LINECTRL
);
1095 mxs_write(ctrl2
, s
, REG_CTRL2
);
1097 uart_update_timeout(u
, termios
->c_cflag
, baud
);
1099 /* prepare for the DMA RX. */
1100 if (auart_dma_enabled(s
) &&
1101 !test_and_set_bit(MXS_AUART_DMA_RX_READY
, &s
->flags
)) {
1102 if (!mxs_auart_dma_prep_rx(s
)) {
1103 /* Disable the normal RX interrupt. */
1104 mxs_clr(AUART_INTR_RXIEN
| AUART_INTR_RTIEN
,
1107 mxs_auart_dma_exit(s
);
1108 dev_err(s
->dev
, "We can not start up the DMA.\n");
1112 /* CTS flow-control and modem-status interrupts */
1113 if (UART_ENABLE_MS(u
, termios
->c_cflag
))
1114 mxs_auart_enable_ms(u
);
1116 mxs_auart_disable_ms(u
);
1119 static void mxs_auart_set_ldisc(struct uart_port
*port
,
1120 struct ktermios
*termios
)
1122 if (termios
->c_line
== N_PPS
) {
1123 port
->flags
|= UPF_HARDPPS_CD
;
1124 mxs_auart_enable_ms(port
);
1126 port
->flags
&= ~UPF_HARDPPS_CD
;
1130 static irqreturn_t
mxs_auart_irq_handle(int irq
, void *context
)
1133 struct mxs_auart_port
*s
= context
;
1134 u32 mctrl_temp
= s
->mctrl_prev
;
1135 u32 stat
= mxs_read(s
, REG_STAT
);
1137 istat
= mxs_read(s
, REG_INTR
);
1140 mxs_clr(istat
& (AUART_INTR_RTIS
| AUART_INTR_TXIS
| AUART_INTR_RXIS
1141 | AUART_INTR_CTSMIS
), s
, REG_INTR
);
1144 * Dealing with GPIO interrupt
1146 if (irq
== s
->gpio_irq
[UART_GPIO_CTS
] ||
1147 irq
== s
->gpio_irq
[UART_GPIO_DCD
] ||
1148 irq
== s
->gpio_irq
[UART_GPIO_DSR
] ||
1149 irq
== s
->gpio_irq
[UART_GPIO_RI
])
1150 mxs_auart_modem_status(s
,
1151 mctrl_gpio_get(s
->gpios
, &mctrl_temp
));
1153 if (istat
& AUART_INTR_CTSMIS
) {
1154 if (CTS_AT_AUART() && s
->ms_irq_enabled
)
1155 uart_handle_cts_change(&s
->port
,
1156 stat
& AUART_STAT_CTS
);
1157 mxs_clr(AUART_INTR_CTSMIS
, s
, REG_INTR
);
1158 istat
&= ~AUART_INTR_CTSMIS
;
1161 if (istat
& (AUART_INTR_RTIS
| AUART_INTR_RXIS
)) {
1162 if (!auart_dma_enabled(s
))
1163 mxs_auart_rx_chars(s
);
1164 istat
&= ~(AUART_INTR_RTIS
| AUART_INTR_RXIS
);
1167 if (istat
& AUART_INTR_TXIS
) {
1168 mxs_auart_tx_chars(s
);
1169 istat
&= ~AUART_INTR_TXIS
;
1175 static void mxs_auart_reset_deassert(struct mxs_auart_port
*s
)
1180 mxs_clr(AUART_CTRL0_SFTRST
, s
, REG_CTRL0
);
1182 for (i
= 0; i
< 10000; i
++) {
1183 reg
= mxs_read(s
, REG_CTRL0
);
1184 if (!(reg
& AUART_CTRL0_SFTRST
))
1188 mxs_clr(AUART_CTRL0_CLKGATE
, s
, REG_CTRL0
);
1191 static void mxs_auart_reset_assert(struct mxs_auart_port
*s
)
1196 reg
= mxs_read(s
, REG_CTRL0
);
1197 /* if already in reset state, keep it untouched */
1198 if (reg
& AUART_CTRL0_SFTRST
)
1201 mxs_clr(AUART_CTRL0_CLKGATE
, s
, REG_CTRL0
);
1202 mxs_set(AUART_CTRL0_SFTRST
, s
, REG_CTRL0
);
1204 for (i
= 0; i
< 1000; i
++) {
1205 reg
= mxs_read(s
, REG_CTRL0
);
1206 /* reset is finished when the clock is gated */
1207 if (reg
& AUART_CTRL0_CLKGATE
)
1212 dev_err(s
->dev
, "Failed to reset the unit.");
1215 static int mxs_auart_startup(struct uart_port
*u
)
1218 struct mxs_auart_port
*s
= to_auart_port(u
);
1220 ret
= clk_prepare_enable(s
->clk
);
1224 if (uart_console(u
)) {
1225 mxs_clr(AUART_CTRL0_CLKGATE
, s
, REG_CTRL0
);
1227 /* reset the unit to a well known state */
1228 mxs_auart_reset_assert(s
);
1229 mxs_auart_reset_deassert(s
);
1232 mxs_set(AUART_CTRL2_UARTEN
, s
, REG_CTRL2
);
1234 mxs_write(AUART_INTR_RXIEN
| AUART_INTR_RTIEN
| AUART_INTR_CTSMIEN
,
1237 /* Reset FIFO size (it could have changed if DMA was enabled) */
1238 u
->fifosize
= MXS_AUART_FIFO_SIZE
;
1241 * Enable fifo so all four bytes of a DMA word are written to
1242 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1244 mxs_set(AUART_LINECTRL_FEN
, s
, REG_LINECTRL
);
1246 /* get initial status of modem lines */
1247 mctrl_gpio_get(s
->gpios
, &s
->mctrl_prev
);
1249 s
->ms_irq_enabled
= false;
1253 static void mxs_auart_shutdown(struct uart_port
*u
)
1255 struct mxs_auart_port
*s
= to_auart_port(u
);
1257 mxs_auart_disable_ms(u
);
1259 if (auart_dma_enabled(s
))
1260 mxs_auart_dma_exit(s
);
1262 if (uart_console(u
)) {
1263 mxs_clr(AUART_CTRL2_UARTEN
, s
, REG_CTRL2
);
1265 mxs_clr(AUART_INTR_RXIEN
| AUART_INTR_RTIEN
|
1266 AUART_INTR_CTSMIEN
, s
, REG_INTR
);
1267 mxs_set(AUART_CTRL0_CLKGATE
, s
, REG_CTRL0
);
1269 mxs_auart_reset_assert(s
);
1272 clk_disable_unprepare(s
->clk
);
1275 static unsigned int mxs_auart_tx_empty(struct uart_port
*u
)
1277 struct mxs_auart_port
*s
= to_auart_port(u
);
1279 if ((mxs_read(s
, REG_STAT
) &
1280 (AUART_STAT_TXFE
| AUART_STAT_BUSY
)) == AUART_STAT_TXFE
)
1281 return TIOCSER_TEMT
;
1286 static void mxs_auart_start_tx(struct uart_port
*u
)
1288 struct mxs_auart_port
*s
= to_auart_port(u
);
1290 /* enable transmitter */
1291 mxs_set(AUART_CTRL2_TXE
, s
, REG_CTRL2
);
1293 mxs_auart_tx_chars(s
);
1296 static void mxs_auart_stop_tx(struct uart_port
*u
)
1298 struct mxs_auart_port
*s
= to_auart_port(u
);
1300 mxs_clr(AUART_CTRL2_TXE
, s
, REG_CTRL2
);
1303 static void mxs_auart_stop_rx(struct uart_port
*u
)
1305 struct mxs_auart_port
*s
= to_auart_port(u
);
1307 mxs_clr(AUART_CTRL2_RXE
, s
, REG_CTRL2
);
1310 static void mxs_auart_break_ctl(struct uart_port
*u
, int ctl
)
1312 struct mxs_auart_port
*s
= to_auart_port(u
);
1315 mxs_set(AUART_LINECTRL_BRK
, s
, REG_LINECTRL
);
1317 mxs_clr(AUART_LINECTRL_BRK
, s
, REG_LINECTRL
);
1320 static const struct uart_ops mxs_auart_ops
= {
1321 .tx_empty
= mxs_auart_tx_empty
,
1322 .start_tx
= mxs_auart_start_tx
,
1323 .stop_tx
= mxs_auart_stop_tx
,
1324 .stop_rx
= mxs_auart_stop_rx
,
1325 .enable_ms
= mxs_auart_enable_ms
,
1326 .break_ctl
= mxs_auart_break_ctl
,
1327 .set_mctrl
= mxs_auart_set_mctrl
,
1328 .get_mctrl
= mxs_auart_get_mctrl
,
1329 .startup
= mxs_auart_startup
,
1330 .shutdown
= mxs_auart_shutdown
,
1331 .set_termios
= mxs_auart_settermios
,
1332 .set_ldisc
= mxs_auart_set_ldisc
,
1333 .type
= mxs_auart_type
,
1334 .release_port
= mxs_auart_release_port
,
1335 .request_port
= mxs_auart_request_port
,
1336 .config_port
= mxs_auart_config_port
,
1337 .verify_port
= mxs_auart_verify_port
,
1340 static struct mxs_auart_port
*auart_port
[MXS_AUART_PORTS
];
1342 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1343 static void mxs_auart_console_putchar(struct uart_port
*port
, int ch
)
1345 struct mxs_auart_port
*s
= to_auart_port(port
);
1346 unsigned int to
= 1000;
1348 while (mxs_read(s
, REG_STAT
) & AUART_STAT_TXFF
) {
1354 mxs_write(ch
, s
, REG_DATA
);
1358 auart_console_write(struct console
*co
, const char *str
, unsigned int count
)
1360 struct mxs_auart_port
*s
;
1361 struct uart_port
*port
;
1362 unsigned int old_ctrl0
, old_ctrl2
;
1363 unsigned int to
= 20000;
1365 if (co
->index
>= MXS_AUART_PORTS
|| co
->index
< 0)
1368 s
= auart_port
[co
->index
];
1373 /* First save the CR then disable the interrupts */
1374 old_ctrl2
= mxs_read(s
, REG_CTRL2
);
1375 old_ctrl0
= mxs_read(s
, REG_CTRL0
);
1377 mxs_clr(AUART_CTRL0_CLKGATE
, s
, REG_CTRL0
);
1378 mxs_set(AUART_CTRL2_UARTEN
| AUART_CTRL2_TXE
, s
, REG_CTRL2
);
1380 uart_console_write(port
, str
, count
, mxs_auart_console_putchar
);
1382 /* Finally, wait for transmitter to become empty ... */
1383 while (mxs_read(s
, REG_STAT
) & AUART_STAT_BUSY
) {
1390 * ... and restore the TCR if we waited long enough for the transmitter
1391 * to be idle. This might keep the transmitter enabled although it is
1392 * unused, but that is better than to disable it while it is still
1395 if (!(mxs_read(s
, REG_STAT
) & AUART_STAT_BUSY
)) {
1396 mxs_write(old_ctrl0
, s
, REG_CTRL0
);
1397 mxs_write(old_ctrl2
, s
, REG_CTRL2
);
1400 clk_disable(s
->clk
);
1404 auart_console_get_options(struct mxs_auart_port
*s
, int *baud
,
1405 int *parity
, int *bits
)
1407 struct uart_port
*port
= &s
->port
;
1408 unsigned int lcr_h
, quot
;
1410 if (!(mxs_read(s
, REG_CTRL2
) & AUART_CTRL2_UARTEN
))
1413 lcr_h
= mxs_read(s
, REG_LINECTRL
);
1416 if (lcr_h
& AUART_LINECTRL_PEN
) {
1417 if (lcr_h
& AUART_LINECTRL_EPS
)
1423 if ((lcr_h
& AUART_LINECTRL_WLEN_MASK
) == AUART_LINECTRL_WLEN(2))
1428 quot
= ((mxs_read(s
, REG_LINECTRL
) & AUART_LINECTRL_BAUD_DIVINT_MASK
))
1429 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT
- 6);
1430 quot
|= ((mxs_read(s
, REG_LINECTRL
) & AUART_LINECTRL_BAUD_DIVFRAC_MASK
))
1431 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT
;
1435 *baud
= (port
->uartclk
<< 2) / quot
;
1439 auart_console_setup(struct console
*co
, char *options
)
1441 struct mxs_auart_port
*s
;
1449 * Check whether an invalid uart number has been specified, and
1450 * if so, search for the first available port that does have
1453 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(auart_port
))
1455 s
= auart_port
[co
->index
];
1459 ret
= clk_prepare_enable(s
->clk
);
1464 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1466 auart_console_get_options(s
, &baud
, &parity
, &bits
);
1468 ret
= uart_set_options(&s
->port
, co
, baud
, parity
, bits
, flow
);
1470 clk_disable_unprepare(s
->clk
);
1475 static struct console auart_console
= {
1477 .write
= auart_console_write
,
1478 .device
= uart_console_device
,
1479 .setup
= auart_console_setup
,
1480 .flags
= CON_PRINTBUFFER
,
1482 .data
= &auart_driver
,
1486 static struct uart_driver auart_driver
= {
1487 .owner
= THIS_MODULE
,
1488 .driver_name
= "ttyAPP",
1489 .dev_name
= "ttyAPP",
1492 .nr
= MXS_AUART_PORTS
,
1493 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1494 .cons
= &auart_console
,
1498 static void mxs_init_regs(struct mxs_auart_port
*s
)
1500 if (is_asm9260_auart(s
))
1501 s
->vendor
= &vendor_alphascale_asm9260
;
1503 s
->vendor
= &vendor_freescale_stmp37xx
;
1506 static int mxs_get_clks(struct mxs_auart_port
*s
,
1507 struct platform_device
*pdev
)
1511 if (!is_asm9260_auart(s
)) {
1512 s
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1513 return PTR_ERR_OR_ZERO(s
->clk
);
1516 s
->clk
= devm_clk_get(s
->dev
, "mod");
1517 if (IS_ERR(s
->clk
)) {
1518 dev_err(s
->dev
, "Failed to get \"mod\" clk\n");
1519 return PTR_ERR(s
->clk
);
1522 s
->clk_ahb
= devm_clk_get(s
->dev
, "ahb");
1523 if (IS_ERR(s
->clk_ahb
)) {
1524 dev_err(s
->dev
, "Failed to get \"ahb\" clk\n");
1525 return PTR_ERR(s
->clk_ahb
);
1528 err
= clk_prepare_enable(s
->clk_ahb
);
1530 dev_err(s
->dev
, "Failed to enable ahb_clk!\n");
1534 err
= clk_set_rate(s
->clk
, clk_get_rate(s
->clk_ahb
));
1536 dev_err(s
->dev
, "Failed to set rate!\n");
1537 goto disable_clk_ahb
;
1540 err
= clk_prepare_enable(s
->clk
);
1542 dev_err(s
->dev
, "Failed to enable clk!\n");
1543 goto disable_clk_ahb
;
1549 clk_disable_unprepare(s
->clk_ahb
);
1554 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1555 * could successfully get all information from dt or a negative errno.
1557 static int serial_mxs_probe_dt(struct mxs_auart_port
*s
,
1558 struct platform_device
*pdev
)
1560 struct device_node
*np
= pdev
->dev
.of_node
;
1564 /* no device tree device */
1567 ret
= of_alias_get_id(np
, "serial");
1569 dev_err(&pdev
->dev
, "failed to get alias id: %d\n", ret
);
1574 if (of_get_property(np
, "uart-has-rtscts", NULL
) ||
1575 of_get_property(np
, "fsl,uart-has-rtscts", NULL
) /* deprecated */)
1576 set_bit(MXS_AUART_RTSCTS
, &s
->flags
);
1581 static int mxs_auart_init_gpios(struct mxs_auart_port
*s
, struct device
*dev
)
1583 enum mctrl_gpio_idx i
;
1584 struct gpio_desc
*gpiod
;
1586 s
->gpios
= mctrl_gpio_init_noauto(dev
, 0);
1587 if (IS_ERR(s
->gpios
))
1588 return PTR_ERR(s
->gpios
);
1590 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1591 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1592 if (test_bit(MXS_AUART_RTSCTS
, &s
->flags
))
1594 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1595 clear_bit(MXS_AUART_RTSCTS
, &s
->flags
);
1598 for (i
= 0; i
< UART_GPIO_MAX
; i
++) {
1599 gpiod
= mctrl_gpio_to_gpiod(s
->gpios
, i
);
1600 if (gpiod
&& (gpiod_get_direction(gpiod
) == GPIOF_DIR_IN
))
1601 s
->gpio_irq
[i
] = gpiod_to_irq(gpiod
);
1603 s
->gpio_irq
[i
] = -EINVAL
;
1609 static void mxs_auart_free_gpio_irq(struct mxs_auart_port
*s
)
1611 enum mctrl_gpio_idx i
;
1613 for (i
= 0; i
< UART_GPIO_MAX
; i
++)
1614 if (s
->gpio_irq
[i
] >= 0)
1615 free_irq(s
->gpio_irq
[i
], s
);
1618 static int mxs_auart_request_gpio_irq(struct mxs_auart_port
*s
)
1620 int *irq
= s
->gpio_irq
;
1621 enum mctrl_gpio_idx i
;
1624 for (i
= 0; (i
< UART_GPIO_MAX
) && !err
; i
++) {
1628 irq_set_status_flags(irq
[i
], IRQ_NOAUTOEN
);
1629 err
= request_irq(irq
[i
], mxs_auart_irq_handle
,
1630 IRQ_TYPE_EDGE_BOTH
, dev_name(s
->dev
), s
);
1632 dev_err(s
->dev
, "%s - Can't get %d irq\n",
1637 * If something went wrong, rollback.
1639 while (err
&& (--i
>= 0))
1641 free_irq(irq
[i
], s
);
1646 static int mxs_auart_probe(struct platform_device
*pdev
)
1648 const struct of_device_id
*of_id
=
1649 of_match_device(mxs_auart_dt_ids
, &pdev
->dev
);
1650 struct mxs_auart_port
*s
;
1655 s
= devm_kzalloc(&pdev
->dev
, sizeof(*s
), GFP_KERNEL
);
1659 s
->port
.dev
= &pdev
->dev
;
1660 s
->dev
= &pdev
->dev
;
1662 ret
= serial_mxs_probe_dt(s
, pdev
);
1664 s
->port
.line
= pdev
->id
< 0 ? 0 : pdev
->id
;
1669 pdev
->id_entry
= of_id
->data
;
1670 s
->devtype
= pdev
->id_entry
->driver_data
;
1673 ret
= mxs_get_clks(s
, pdev
);
1677 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1681 s
->port
.mapbase
= r
->start
;
1682 s
->port
.membase
= ioremap(r
->start
, resource_size(r
));
1683 s
->port
.ops
= &mxs_auart_ops
;
1684 s
->port
.iotype
= UPIO_MEM
;
1685 s
->port
.fifosize
= MXS_AUART_FIFO_SIZE
;
1686 s
->port
.uartclk
= clk_get_rate(s
->clk
);
1687 s
->port
.type
= PORT_IMX
;
1693 irq
= platform_get_irq(pdev
, 0);
1698 ret
= devm_request_irq(&pdev
->dev
, irq
, mxs_auart_irq_handle
, 0,
1699 dev_name(&pdev
->dev
), s
);
1703 platform_set_drvdata(pdev
, s
);
1705 ret
= mxs_auart_init_gpios(s
, &pdev
->dev
);
1707 dev_err(&pdev
->dev
, "Failed to initialize GPIOs.\n");
1712 * Get the GPIO lines IRQ
1714 ret
= mxs_auart_request_gpio_irq(s
);
1718 auart_port
[s
->port
.line
] = s
;
1720 mxs_auart_reset_deassert(s
);
1722 ret
= uart_add_one_port(&auart_driver
, &s
->port
);
1724 goto out_free_gpio_irq
;
1726 /* ASM9260 don't have version reg */
1727 if (is_asm9260_auart(s
)) {
1728 dev_info(&pdev
->dev
, "Found APPUART ASM9260\n");
1730 version
= mxs_read(s
, REG_VERSION
);
1731 dev_info(&pdev
->dev
, "Found APPUART %d.%d.%d\n",
1732 (version
>> 24) & 0xff,
1733 (version
>> 16) & 0xff, version
& 0xffff);
1739 mxs_auart_free_gpio_irq(s
);
1740 auart_port
[pdev
->id
] = NULL
;
1744 static int mxs_auart_remove(struct platform_device
*pdev
)
1746 struct mxs_auart_port
*s
= platform_get_drvdata(pdev
);
1748 uart_remove_one_port(&auart_driver
, &s
->port
);
1749 auart_port
[pdev
->id
] = NULL
;
1750 mxs_auart_free_gpio_irq(s
);
1755 static struct platform_driver mxs_auart_driver
= {
1756 .probe
= mxs_auart_probe
,
1757 .remove
= mxs_auart_remove
,
1759 .name
= "mxs-auart",
1760 .of_match_table
= mxs_auart_dt_ids
,
1764 static int __init
mxs_auart_init(void)
1768 r
= uart_register_driver(&auart_driver
);
1772 r
= platform_driver_register(&mxs_auart_driver
);
1778 uart_unregister_driver(&auart_driver
);
1783 static void __exit
mxs_auart_exit(void)
1785 platform_driver_unregister(&mxs_auart_driver
);
1786 uart_unregister_driver(&auart_driver
);
1789 module_init(mxs_auart_init
);
1790 module_exit(mxs_auart_exit
);
1791 MODULE_LICENSE("GPL");
1792 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1793 MODULE_ALIAS("platform:mxs-auart");