1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the core HCD code, and implements the Linux hc_driver
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 static void dwc2_port_resume(struct dwc2_hsotg
*hsotg
);
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
71 * @hsotg: Programming view of the DWC_otg controller
73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg
*hsotg
)
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
80 /* Clear any pending interrupts */
81 dwc2_writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
83 /* Enable the interrupts in the GINTMSK */
84 intmsk
= GINTSTS_MODEMIS
| GINTSTS_OTGINT
;
86 if (!hsotg
->params
.host_dma
)
87 intmsk
|= GINTSTS_RXFLVL
;
88 if (!hsotg
->params
.external_id_pin_ctl
)
89 intmsk
|= GINTSTS_CONIDSTSCHNG
;
91 intmsk
|= GINTSTS_WKUPINT
| GINTSTS_USBSUSP
|
94 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
98 * Initializes the FSLSPClkSel field of the HCFG register depending on the
101 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg
)
105 if ((hsotg
->hw_params
.hs_phy_type
== GHWCFG2_HS_PHY_TYPE_ULPI
&&
106 hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
&&
107 hsotg
->params
.ulpi_fs_ls
) ||
108 hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
) {
110 val
= HCFG_FSLSPCLKSEL_48_MHZ
;
112 /* High speed PHY running at full speed or high speed */
113 val
= HCFG_FSLSPCLKSEL_30_60_MHZ
;
116 dev_dbg(hsotg
->dev
, "Initializing HCFG.FSLSPClkSel to %08x\n", val
);
117 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
118 hcfg
&= ~HCFG_FSLSPCLKSEL_MASK
;
119 hcfg
|= val
<< HCFG_FSLSPCLKSEL_SHIFT
;
120 dwc2_writel(hcfg
, hsotg
->regs
+ HCFG
);
123 static int dwc2_fs_phy_init(struct dwc2_hsotg
*hsotg
, bool select_phy
)
125 u32 usbcfg
, ggpio
, i2cctl
;
129 * core_init() is now called on every switch so only call the
130 * following for the first time through
133 dev_dbg(hsotg
->dev
, "FS PHY selected\n");
135 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
136 if (!(usbcfg
& GUSBCFG_PHYSEL
)) {
137 usbcfg
|= GUSBCFG_PHYSEL
;
138 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
140 /* Reset after a PHY select */
141 retval
= dwc2_core_reset_and_force_dr_mode(hsotg
);
145 "%s: Reset failed, aborting", __func__
);
150 if (hsotg
->params
.activate_stm_fs_transceiver
) {
151 ggpio
= dwc2_readl(hsotg
->regs
+ GGPIO
);
152 if (!(ggpio
& GGPIO_STM32_OTG_GCCFG_PWRDWN
)) {
153 dev_dbg(hsotg
->dev
, "Activating transceiver\n");
155 * STM32F4x9 uses the GGPIO register as general
156 * core configuration register.
158 ggpio
|= GGPIO_STM32_OTG_GCCFG_PWRDWN
;
159 dwc2_writel(ggpio
, hsotg
->regs
+ GGPIO
);
165 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
166 * do this on HNP Dev/Host mode switches (done in dev_init and
169 if (dwc2_is_host_mode(hsotg
))
170 dwc2_init_fs_ls_pclk_sel(hsotg
);
172 if (hsotg
->params
.i2c_enable
) {
173 dev_dbg(hsotg
->dev
, "FS PHY enabling I2C\n");
175 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
176 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
177 usbcfg
|= GUSBCFG_OTG_UTMI_FS_SEL
;
178 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
180 /* Program GI2CCTL.I2CEn */
181 i2cctl
= dwc2_readl(hsotg
->regs
+ GI2CCTL
);
182 i2cctl
&= ~GI2CCTL_I2CDEVADDR_MASK
;
183 i2cctl
|= 1 << GI2CCTL_I2CDEVADDR_SHIFT
;
184 i2cctl
&= ~GI2CCTL_I2CEN
;
185 dwc2_writel(i2cctl
, hsotg
->regs
+ GI2CCTL
);
186 i2cctl
|= GI2CCTL_I2CEN
;
187 dwc2_writel(i2cctl
, hsotg
->regs
+ GI2CCTL
);
193 static int dwc2_hs_phy_init(struct dwc2_hsotg
*hsotg
, bool select_phy
)
195 u32 usbcfg
, usbcfg_old
;
201 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
205 * HS PHY parameters. These parameters are preserved during soft reset
206 * so only program the first time. Do a soft reset immediately after
209 switch (hsotg
->params
.phy_type
) {
210 case DWC2_PHY_TYPE_PARAM_ULPI
:
212 dev_dbg(hsotg
->dev
, "HS ULPI PHY selected\n");
213 usbcfg
|= GUSBCFG_ULPI_UTMI_SEL
;
214 usbcfg
&= ~(GUSBCFG_PHYIF16
| GUSBCFG_DDRSEL
);
215 if (hsotg
->params
.phy_ulpi_ddr
)
216 usbcfg
|= GUSBCFG_DDRSEL
;
218 /* Set external VBUS indicator as needed. */
219 if (hsotg
->params
.oc_disable
)
220 usbcfg
|= (GUSBCFG_ULPI_INT_VBUS_IND
|
221 GUSBCFG_INDICATORPASSTHROUGH
);
223 case DWC2_PHY_TYPE_PARAM_UTMI
:
224 /* UTMI+ interface */
225 dev_dbg(hsotg
->dev
, "HS UTMI+ PHY selected\n");
226 usbcfg
&= ~(GUSBCFG_ULPI_UTMI_SEL
| GUSBCFG_PHYIF16
);
227 if (hsotg
->params
.phy_utmi_width
== 16)
228 usbcfg
|= GUSBCFG_PHYIF16
;
231 dev_err(hsotg
->dev
, "FS PHY selected at HS!\n");
235 if (usbcfg
!= usbcfg_old
) {
236 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
238 /* Reset after setting the PHY parameters */
239 retval
= dwc2_core_reset_and_force_dr_mode(hsotg
);
242 "%s: Reset failed, aborting", __func__
);
250 static int dwc2_phy_init(struct dwc2_hsotg
*hsotg
, bool select_phy
)
255 if ((hsotg
->params
.speed
== DWC2_SPEED_PARAM_FULL
||
256 hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
) &&
257 hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
) {
258 /* If FS/LS mode with FS/LS PHY */
259 retval
= dwc2_fs_phy_init(hsotg
, select_phy
);
264 retval
= dwc2_hs_phy_init(hsotg
, select_phy
);
269 if (hsotg
->hw_params
.hs_phy_type
== GHWCFG2_HS_PHY_TYPE_ULPI
&&
270 hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
&&
271 hsotg
->params
.ulpi_fs_ls
) {
272 dev_dbg(hsotg
->dev
, "Setting ULPI FSLS\n");
273 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
274 usbcfg
|= GUSBCFG_ULPI_FS_LS
;
275 usbcfg
|= GUSBCFG_ULPI_CLK_SUSP_M
;
276 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
278 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
279 usbcfg
&= ~GUSBCFG_ULPI_FS_LS
;
280 usbcfg
&= ~GUSBCFG_ULPI_CLK_SUSP_M
;
281 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
287 static int dwc2_gahbcfg_init(struct dwc2_hsotg
*hsotg
)
289 u32 ahbcfg
= dwc2_readl(hsotg
->regs
+ GAHBCFG
);
291 switch (hsotg
->hw_params
.arch
) {
292 case GHWCFG2_EXT_DMA_ARCH
:
293 dev_err(hsotg
->dev
, "External DMA Mode not supported\n");
296 case GHWCFG2_INT_DMA_ARCH
:
297 dev_dbg(hsotg
->dev
, "Internal DMA Mode\n");
298 if (hsotg
->params
.ahbcfg
!= -1) {
299 ahbcfg
&= GAHBCFG_CTRL_MASK
;
300 ahbcfg
|= hsotg
->params
.ahbcfg
&
305 case GHWCFG2_SLAVE_ONLY_ARCH
:
307 dev_dbg(hsotg
->dev
, "Slave Only Mode\n");
311 dev_dbg(hsotg
->dev
, "host_dma:%d dma_desc_enable:%d\n",
312 hsotg
->params
.host_dma
,
313 hsotg
->params
.dma_desc_enable
);
315 if (hsotg
->params
.host_dma
) {
316 if (hsotg
->params
.dma_desc_enable
)
317 dev_dbg(hsotg
->dev
, "Using Descriptor DMA mode\n");
319 dev_dbg(hsotg
->dev
, "Using Buffer DMA mode\n");
321 dev_dbg(hsotg
->dev
, "Using Slave mode\n");
322 hsotg
->params
.dma_desc_enable
= false;
325 if (hsotg
->params
.host_dma
)
326 ahbcfg
|= GAHBCFG_DMA_EN
;
328 dwc2_writel(ahbcfg
, hsotg
->regs
+ GAHBCFG
);
333 static void dwc2_gusbcfg_init(struct dwc2_hsotg
*hsotg
)
337 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
338 usbcfg
&= ~(GUSBCFG_HNPCAP
| GUSBCFG_SRPCAP
);
340 switch (hsotg
->hw_params
.op_mode
) {
341 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE
:
342 if (hsotg
->params
.otg_cap
==
343 DWC2_CAP_PARAM_HNP_SRP_CAPABLE
)
344 usbcfg
|= GUSBCFG_HNPCAP
;
345 if (hsotg
->params
.otg_cap
!=
346 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
)
347 usbcfg
|= GUSBCFG_SRPCAP
;
350 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE
:
351 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
:
352 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST
:
353 if (hsotg
->params
.otg_cap
!=
354 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE
)
355 usbcfg
|= GUSBCFG_SRPCAP
;
358 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE
:
359 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE
:
360 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST
:
365 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
369 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
371 * @hsotg: Programming view of DWC_otg controller
373 static void dwc2_enable_host_interrupts(struct dwc2_hsotg
*hsotg
)
377 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
379 /* Disable all interrupts */
380 dwc2_writel(0, hsotg
->regs
+ GINTMSK
);
381 dwc2_writel(0, hsotg
->regs
+ HAINTMSK
);
383 /* Enable the common interrupts */
384 dwc2_enable_common_interrupts(hsotg
);
386 /* Enable host mode interrupts without disturbing common interrupts */
387 intmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
388 intmsk
|= GINTSTS_DISCONNINT
| GINTSTS_PRTINT
| GINTSTS_HCHINT
;
389 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
393 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
395 * @hsotg: Programming view of DWC_otg controller
397 static void dwc2_disable_host_interrupts(struct dwc2_hsotg
*hsotg
)
399 u32 intmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
401 /* Disable host mode interrupts without disturbing common interrupts */
402 intmsk
&= ~(GINTSTS_SOF
| GINTSTS_PRTINT
| GINTSTS_HCHINT
|
403 GINTSTS_PTXFEMP
| GINTSTS_NPTXFEMP
| GINTSTS_DISCONNINT
);
404 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
408 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
409 * For system that have a total fifo depth that is smaller than the default
412 * @hsotg: Programming view of DWC_otg controller
414 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg
*hsotg
)
416 struct dwc2_core_params
*params
= &hsotg
->params
;
417 struct dwc2_hw_params
*hw
= &hsotg
->hw_params
;
418 u32 rxfsiz
, nptxfsiz
, ptxfsiz
, total_fifo_size
;
420 total_fifo_size
= hw
->total_fifo_size
;
421 rxfsiz
= params
->host_rx_fifo_size
;
422 nptxfsiz
= params
->host_nperio_tx_fifo_size
;
423 ptxfsiz
= params
->host_perio_tx_fifo_size
;
426 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
427 * allocation with support for high bandwidth endpoints. Synopsys
428 * defines MPS(Max Packet size) for a periodic EP=1024, and for
429 * non-periodic as 512.
431 if (total_fifo_size
< (rxfsiz
+ nptxfsiz
+ ptxfsiz
)) {
433 * For Buffer DMA mode/Scatter Gather DMA mode
434 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
435 * with n = number of host channel.
436 * 2 * ((1024/4) + 2) = 516
438 rxfsiz
= 516 + hw
->host_channels
;
441 * min non-periodic tx fifo depth
442 * 2 * (largest non-periodic USB packet used / 4)
448 * min periodic tx fifo depth
449 * (largest packet size*MC)/4
454 params
->host_rx_fifo_size
= rxfsiz
;
455 params
->host_nperio_tx_fifo_size
= nptxfsiz
;
456 params
->host_perio_tx_fifo_size
= ptxfsiz
;
460 * If the summation of RX, NPTX and PTX fifo sizes is still
461 * bigger than the total_fifo_size, then we have a problem.
463 * We won't be able to allocate as many endpoints. Right now,
464 * we're just printing an error message, but ideally this FIFO
465 * allocation algorithm would be improved in the future.
467 * FIXME improve this FIFO allocation algorithm.
469 if (unlikely(total_fifo_size
< (rxfsiz
+ nptxfsiz
+ ptxfsiz
)))
470 dev_err(hsotg
->dev
, "invalid fifo sizes\n");
473 static void dwc2_config_fifos(struct dwc2_hsotg
*hsotg
)
475 struct dwc2_core_params
*params
= &hsotg
->params
;
476 u32 nptxfsiz
, hptxfsiz
, dfifocfg
, grxfsiz
;
478 if (!params
->enable_dynamic_fifo
)
481 dwc2_calculate_dynamic_fifo(hsotg
);
484 grxfsiz
= dwc2_readl(hsotg
->regs
+ GRXFSIZ
);
485 dev_dbg(hsotg
->dev
, "initial grxfsiz=%08x\n", grxfsiz
);
486 grxfsiz
&= ~GRXFSIZ_DEPTH_MASK
;
487 grxfsiz
|= params
->host_rx_fifo_size
<<
488 GRXFSIZ_DEPTH_SHIFT
& GRXFSIZ_DEPTH_MASK
;
489 dwc2_writel(grxfsiz
, hsotg
->regs
+ GRXFSIZ
);
490 dev_dbg(hsotg
->dev
, "new grxfsiz=%08x\n",
491 dwc2_readl(hsotg
->regs
+ GRXFSIZ
));
493 /* Non-periodic Tx FIFO */
494 dev_dbg(hsotg
->dev
, "initial gnptxfsiz=%08x\n",
495 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
496 nptxfsiz
= params
->host_nperio_tx_fifo_size
<<
497 FIFOSIZE_DEPTH_SHIFT
& FIFOSIZE_DEPTH_MASK
;
498 nptxfsiz
|= params
->host_rx_fifo_size
<<
499 FIFOSIZE_STARTADDR_SHIFT
& FIFOSIZE_STARTADDR_MASK
;
500 dwc2_writel(nptxfsiz
, hsotg
->regs
+ GNPTXFSIZ
);
501 dev_dbg(hsotg
->dev
, "new gnptxfsiz=%08x\n",
502 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
504 /* Periodic Tx FIFO */
505 dev_dbg(hsotg
->dev
, "initial hptxfsiz=%08x\n",
506 dwc2_readl(hsotg
->regs
+ HPTXFSIZ
));
507 hptxfsiz
= params
->host_perio_tx_fifo_size
<<
508 FIFOSIZE_DEPTH_SHIFT
& FIFOSIZE_DEPTH_MASK
;
509 hptxfsiz
|= (params
->host_rx_fifo_size
+
510 params
->host_nperio_tx_fifo_size
) <<
511 FIFOSIZE_STARTADDR_SHIFT
& FIFOSIZE_STARTADDR_MASK
;
512 dwc2_writel(hptxfsiz
, hsotg
->regs
+ HPTXFSIZ
);
513 dev_dbg(hsotg
->dev
, "new hptxfsiz=%08x\n",
514 dwc2_readl(hsotg
->regs
+ HPTXFSIZ
));
516 if (hsotg
->params
.en_multiple_tx_fifo
&&
517 hsotg
->hw_params
.snpsid
>= DWC2_CORE_REV_2_91a
) {
519 * This feature was implemented in 2.91a version
520 * Global DFIFOCFG calculation for Host mode -
521 * include RxFIFO, NPTXFIFO and HPTXFIFO
523 dfifocfg
= dwc2_readl(hsotg
->regs
+ GDFIFOCFG
);
524 dfifocfg
&= ~GDFIFOCFG_EPINFOBASE_MASK
;
525 dfifocfg
|= (params
->host_rx_fifo_size
+
526 params
->host_nperio_tx_fifo_size
+
527 params
->host_perio_tx_fifo_size
) <<
528 GDFIFOCFG_EPINFOBASE_SHIFT
&
529 GDFIFOCFG_EPINFOBASE_MASK
;
530 dwc2_writel(dfifocfg
, hsotg
->regs
+ GDFIFOCFG
);
535 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
536 * the HFIR register according to PHY type and speed
538 * @hsotg: Programming view of DWC_otg controller
540 * NOTE: The caller can modify the value of the HFIR register only after the
541 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
544 u32
dwc2_calc_frame_interval(struct dwc2_hsotg
*hsotg
)
548 int clock
= 60; /* default value */
550 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
551 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
553 if (!(usbcfg
& GUSBCFG_PHYSEL
) && (usbcfg
& GUSBCFG_ULPI_UTMI_SEL
) &&
554 !(usbcfg
& GUSBCFG_PHYIF16
))
556 if ((usbcfg
& GUSBCFG_PHYSEL
) && hsotg
->hw_params
.fs_phy_type
==
557 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI
)
559 if (!(usbcfg
& GUSBCFG_PHY_LP_CLK_SEL
) && !(usbcfg
& GUSBCFG_PHYSEL
) &&
560 !(usbcfg
& GUSBCFG_ULPI_UTMI_SEL
) && (usbcfg
& GUSBCFG_PHYIF16
))
562 if (!(usbcfg
& GUSBCFG_PHY_LP_CLK_SEL
) && !(usbcfg
& GUSBCFG_PHYSEL
) &&
563 !(usbcfg
& GUSBCFG_ULPI_UTMI_SEL
) && !(usbcfg
& GUSBCFG_PHYIF16
))
565 if ((usbcfg
& GUSBCFG_PHY_LP_CLK_SEL
) && !(usbcfg
& GUSBCFG_PHYSEL
) &&
566 !(usbcfg
& GUSBCFG_ULPI_UTMI_SEL
) && (usbcfg
& GUSBCFG_PHYIF16
))
568 if ((usbcfg
& GUSBCFG_PHYSEL
) && !(usbcfg
& GUSBCFG_PHYIF16
) &&
569 hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_SHARED_UTMI
)
571 if ((usbcfg
& GUSBCFG_PHYSEL
) &&
572 hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
)
575 if ((hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
== HPRT0_SPD_HIGH_SPEED
)
576 /* High speed case */
577 return 125 * clock
- 1;
580 return 1000 * clock
- 1;
584 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
587 * @core_if: Programming view of DWC_otg controller
588 * @dest: Destination buffer for the packet
589 * @bytes: Number of bytes to copy to the destination
591 void dwc2_read_packet(struct dwc2_hsotg
*hsotg
, u8
*dest
, u16 bytes
)
593 u32 __iomem
*fifo
= hsotg
->regs
+ HCFIFO(0);
594 u32
*data_buf
= (u32
*)dest
;
595 int word_count
= (bytes
+ 3) / 4;
599 * Todo: Account for the case where dest is not dword aligned. This
600 * requires reading data from the FIFO into a u32 temp buffer, then
601 * moving it into the data buffer.
604 dev_vdbg(hsotg
->dev
, "%s(%p,%p,%d)\n", __func__
, hsotg
, dest
, bytes
);
606 for (i
= 0; i
< word_count
; i
++, data_buf
++)
607 *data_buf
= dwc2_readl(fifo
);
611 * dwc2_dump_channel_info() - Prints the state of a host channel
613 * @hsotg: Programming view of DWC_otg controller
614 * @chan: Pointer to the channel to dump
616 * Must be called with interrupt disabled and spinlock held
618 * NOTE: This function will be removed once the peripheral controller code
619 * is integrated and the driver is stable
621 static void dwc2_dump_channel_info(struct dwc2_hsotg
*hsotg
,
622 struct dwc2_host_chan
*chan
)
625 int num_channels
= hsotg
->params
.host_channels
;
636 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
637 hcsplt
= dwc2_readl(hsotg
->regs
+ HCSPLT(chan
->hc_num
));
638 hctsiz
= dwc2_readl(hsotg
->regs
+ HCTSIZ(chan
->hc_num
));
639 hc_dma
= dwc2_readl(hsotg
->regs
+ HCDMA(chan
->hc_num
));
641 dev_dbg(hsotg
->dev
, " Assigned to channel %p:\n", chan
);
642 dev_dbg(hsotg
->dev
, " hcchar 0x%08x, hcsplt 0x%08x\n",
644 dev_dbg(hsotg
->dev
, " hctsiz 0x%08x, hc_dma 0x%08x\n",
646 dev_dbg(hsotg
->dev
, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
647 chan
->dev_addr
, chan
->ep_num
, chan
->ep_is_in
);
648 dev_dbg(hsotg
->dev
, " ep_type: %d\n", chan
->ep_type
);
649 dev_dbg(hsotg
->dev
, " max_packet: %d\n", chan
->max_packet
);
650 dev_dbg(hsotg
->dev
, " data_pid_start: %d\n", chan
->data_pid_start
);
651 dev_dbg(hsotg
->dev
, " xfer_started: %d\n", chan
->xfer_started
);
652 dev_dbg(hsotg
->dev
, " halt_status: %d\n", chan
->halt_status
);
653 dev_dbg(hsotg
->dev
, " xfer_buf: %p\n", chan
->xfer_buf
);
654 dev_dbg(hsotg
->dev
, " xfer_dma: %08lx\n",
655 (unsigned long)chan
->xfer_dma
);
656 dev_dbg(hsotg
->dev
, " xfer_len: %d\n", chan
->xfer_len
);
657 dev_dbg(hsotg
->dev
, " qh: %p\n", chan
->qh
);
658 dev_dbg(hsotg
->dev
, " NP inactive sched:\n");
659 list_for_each_entry(qh
, &hsotg
->non_periodic_sched_inactive
,
661 dev_dbg(hsotg
->dev
, " %p\n", qh
);
662 dev_dbg(hsotg
->dev
, " NP active sched:\n");
663 list_for_each_entry(qh
, &hsotg
->non_periodic_sched_active
,
665 dev_dbg(hsotg
->dev
, " %p\n", qh
);
666 dev_dbg(hsotg
->dev
, " Channels:\n");
667 for (i
= 0; i
< num_channels
; i
++) {
668 struct dwc2_host_chan
*chan
= hsotg
->hc_ptr_array
[i
];
670 dev_dbg(hsotg
->dev
, " %2d: %p\n", i
, chan
);
672 #endif /* VERBOSE_DEBUG */
675 static int _dwc2_hcd_start(struct usb_hcd
*hcd
);
677 static void dwc2_host_start(struct dwc2_hsotg
*hsotg
)
679 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
681 hcd
->self
.is_b_host
= dwc2_hcd_is_b_host(hsotg
);
682 _dwc2_hcd_start(hcd
);
685 static void dwc2_host_disconnect(struct dwc2_hsotg
*hsotg
)
687 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
689 hcd
->self
.is_b_host
= 0;
692 static void dwc2_host_hub_info(struct dwc2_hsotg
*hsotg
, void *context
,
693 int *hub_addr
, int *hub_port
)
695 struct urb
*urb
= context
;
698 *hub_addr
= urb
->dev
->tt
->hub
->devnum
;
701 *hub_port
= urb
->dev
->ttport
;
705 * =========================================================================
706 * Low Level Host Channel Access Functions
707 * =========================================================================
710 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg
*hsotg
,
711 struct dwc2_host_chan
*chan
)
713 u32 hcintmsk
= HCINTMSK_CHHLTD
;
715 switch (chan
->ep_type
) {
716 case USB_ENDPOINT_XFER_CONTROL
:
717 case USB_ENDPOINT_XFER_BULK
:
718 dev_vdbg(hsotg
->dev
, "control/bulk\n");
719 hcintmsk
|= HCINTMSK_XFERCOMPL
;
720 hcintmsk
|= HCINTMSK_STALL
;
721 hcintmsk
|= HCINTMSK_XACTERR
;
722 hcintmsk
|= HCINTMSK_DATATGLERR
;
723 if (chan
->ep_is_in
) {
724 hcintmsk
|= HCINTMSK_BBLERR
;
726 hcintmsk
|= HCINTMSK_NAK
;
727 hcintmsk
|= HCINTMSK_NYET
;
729 hcintmsk
|= HCINTMSK_ACK
;
732 if (chan
->do_split
) {
733 hcintmsk
|= HCINTMSK_NAK
;
734 if (chan
->complete_split
)
735 hcintmsk
|= HCINTMSK_NYET
;
737 hcintmsk
|= HCINTMSK_ACK
;
740 if (chan
->error_state
)
741 hcintmsk
|= HCINTMSK_ACK
;
744 case USB_ENDPOINT_XFER_INT
:
746 dev_vdbg(hsotg
->dev
, "intr\n");
747 hcintmsk
|= HCINTMSK_XFERCOMPL
;
748 hcintmsk
|= HCINTMSK_NAK
;
749 hcintmsk
|= HCINTMSK_STALL
;
750 hcintmsk
|= HCINTMSK_XACTERR
;
751 hcintmsk
|= HCINTMSK_DATATGLERR
;
752 hcintmsk
|= HCINTMSK_FRMOVRUN
;
755 hcintmsk
|= HCINTMSK_BBLERR
;
756 if (chan
->error_state
)
757 hcintmsk
|= HCINTMSK_ACK
;
758 if (chan
->do_split
) {
759 if (chan
->complete_split
)
760 hcintmsk
|= HCINTMSK_NYET
;
762 hcintmsk
|= HCINTMSK_ACK
;
766 case USB_ENDPOINT_XFER_ISOC
:
768 dev_vdbg(hsotg
->dev
, "isoc\n");
769 hcintmsk
|= HCINTMSK_XFERCOMPL
;
770 hcintmsk
|= HCINTMSK_FRMOVRUN
;
771 hcintmsk
|= HCINTMSK_ACK
;
773 if (chan
->ep_is_in
) {
774 hcintmsk
|= HCINTMSK_XACTERR
;
775 hcintmsk
|= HCINTMSK_BBLERR
;
779 dev_err(hsotg
->dev
, "## Unknown EP type ##\n");
783 dwc2_writel(hcintmsk
, hsotg
->regs
+ HCINTMSK(chan
->hc_num
));
785 dev_vdbg(hsotg
->dev
, "set HCINTMSK to %08x\n", hcintmsk
);
788 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg
*hsotg
,
789 struct dwc2_host_chan
*chan
)
791 u32 hcintmsk
= HCINTMSK_CHHLTD
;
794 * For Descriptor DMA mode core halts the channel on AHB error.
795 * Interrupt is not required.
797 if (!hsotg
->params
.dma_desc_enable
) {
799 dev_vdbg(hsotg
->dev
, "desc DMA disabled\n");
800 hcintmsk
|= HCINTMSK_AHBERR
;
803 dev_vdbg(hsotg
->dev
, "desc DMA enabled\n");
804 if (chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
805 hcintmsk
|= HCINTMSK_XFERCOMPL
;
808 if (chan
->error_state
&& !chan
->do_split
&&
809 chan
->ep_type
!= USB_ENDPOINT_XFER_ISOC
) {
811 dev_vdbg(hsotg
->dev
, "setting ACK\n");
812 hcintmsk
|= HCINTMSK_ACK
;
813 if (chan
->ep_is_in
) {
814 hcintmsk
|= HCINTMSK_DATATGLERR
;
815 if (chan
->ep_type
!= USB_ENDPOINT_XFER_INT
)
816 hcintmsk
|= HCINTMSK_NAK
;
820 dwc2_writel(hcintmsk
, hsotg
->regs
+ HCINTMSK(chan
->hc_num
));
822 dev_vdbg(hsotg
->dev
, "set HCINTMSK to %08x\n", hcintmsk
);
825 static void dwc2_hc_enable_ints(struct dwc2_hsotg
*hsotg
,
826 struct dwc2_host_chan
*chan
)
830 if (hsotg
->params
.host_dma
) {
832 dev_vdbg(hsotg
->dev
, "DMA enabled\n");
833 dwc2_hc_enable_dma_ints(hsotg
, chan
);
836 dev_vdbg(hsotg
->dev
, "DMA disabled\n");
837 dwc2_hc_enable_slave_ints(hsotg
, chan
);
840 /* Enable the top level host channel interrupt */
841 intmsk
= dwc2_readl(hsotg
->regs
+ HAINTMSK
);
842 intmsk
|= 1 << chan
->hc_num
;
843 dwc2_writel(intmsk
, hsotg
->regs
+ HAINTMSK
);
845 dev_vdbg(hsotg
->dev
, "set HAINTMSK to %08x\n", intmsk
);
847 /* Make sure host channel interrupts are enabled */
848 intmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
849 intmsk
|= GINTSTS_HCHINT
;
850 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
852 dev_vdbg(hsotg
->dev
, "set GINTMSK to %08x\n", intmsk
);
856 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
857 * a specific endpoint
859 * @hsotg: Programming view of DWC_otg controller
860 * @chan: Information needed to initialize the host channel
862 * The HCCHARn register is set up with the characteristics specified in chan.
863 * Host channel interrupts that may need to be serviced while this transfer is
864 * in progress are enabled.
866 static void dwc2_hc_init(struct dwc2_hsotg
*hsotg
, struct dwc2_host_chan
*chan
)
868 u8 hc_num
= chan
->hc_num
;
874 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
876 /* Clear old interrupt conditions for this host channel */
877 hcintmsk
= 0xffffffff;
878 hcintmsk
&= ~HCINTMSK_RESERVED14_31
;
879 dwc2_writel(hcintmsk
, hsotg
->regs
+ HCINT(hc_num
));
881 /* Enable channel interrupts required for this transfer */
882 dwc2_hc_enable_ints(hsotg
, chan
);
885 * Program the HCCHARn register with the endpoint characteristics for
886 * the current transfer
888 hcchar
= chan
->dev_addr
<< HCCHAR_DEVADDR_SHIFT
& HCCHAR_DEVADDR_MASK
;
889 hcchar
|= chan
->ep_num
<< HCCHAR_EPNUM_SHIFT
& HCCHAR_EPNUM_MASK
;
891 hcchar
|= HCCHAR_EPDIR
;
892 if (chan
->speed
== USB_SPEED_LOW
)
893 hcchar
|= HCCHAR_LSPDDEV
;
894 hcchar
|= chan
->ep_type
<< HCCHAR_EPTYPE_SHIFT
& HCCHAR_EPTYPE_MASK
;
895 hcchar
|= chan
->max_packet
<< HCCHAR_MPS_SHIFT
& HCCHAR_MPS_MASK
;
896 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(hc_num
));
898 dev_vdbg(hsotg
->dev
, "set HCCHAR(%d) to %08x\n",
901 dev_vdbg(hsotg
->dev
, "%s: Channel %d\n",
903 dev_vdbg(hsotg
->dev
, " Dev Addr: %d\n",
905 dev_vdbg(hsotg
->dev
, " Ep Num: %d\n",
907 dev_vdbg(hsotg
->dev
, " Is In: %d\n",
909 dev_vdbg(hsotg
->dev
, " Is Low Speed: %d\n",
910 chan
->speed
== USB_SPEED_LOW
);
911 dev_vdbg(hsotg
->dev
, " Ep Type: %d\n",
913 dev_vdbg(hsotg
->dev
, " Max Pkt: %d\n",
917 /* Program the HCSPLT register for SPLITs */
918 if (chan
->do_split
) {
921 "Programming HC %d with split --> %s\n",
923 chan
->complete_split
? "CSPLIT" : "SSPLIT");
924 if (chan
->complete_split
)
925 hcsplt
|= HCSPLT_COMPSPLT
;
926 hcsplt
|= chan
->xact_pos
<< HCSPLT_XACTPOS_SHIFT
&
928 hcsplt
|= chan
->hub_addr
<< HCSPLT_HUBADDR_SHIFT
&
930 hcsplt
|= chan
->hub_port
<< HCSPLT_PRTADDR_SHIFT
&
933 dev_vdbg(hsotg
->dev
, " comp split %d\n",
934 chan
->complete_split
);
935 dev_vdbg(hsotg
->dev
, " xact pos %d\n",
937 dev_vdbg(hsotg
->dev
, " hub addr %d\n",
939 dev_vdbg(hsotg
->dev
, " hub port %d\n",
941 dev_vdbg(hsotg
->dev
, " is_in %d\n",
943 dev_vdbg(hsotg
->dev
, " Max Pkt %d\n",
945 dev_vdbg(hsotg
->dev
, " xferlen %d\n",
950 dwc2_writel(hcsplt
, hsotg
->regs
+ HCSPLT(hc_num
));
954 * dwc2_hc_halt() - Attempts to halt a host channel
956 * @hsotg: Controller register interface
957 * @chan: Host channel to halt
958 * @halt_status: Reason for halting the channel
960 * This function should only be called in Slave mode or to abort a transfer in
961 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
962 * controller halts the channel when the transfer is complete or a condition
963 * occurs that requires application intervention.
965 * In slave mode, checks for a free request queue entry, then sets the Channel
966 * Enable and Channel Disable bits of the Host Channel Characteristics
967 * register of the specified channel to intiate the halt. If there is no free
968 * request queue entry, sets only the Channel Disable bit of the HCCHARn
969 * register to flush requests for this channel. In the latter case, sets a
970 * flag to indicate that the host channel needs to be halted when a request
971 * queue slot is open.
973 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
974 * HCCHARn register. The controller ensures there is space in the request
975 * queue before submitting the halt request.
977 * Some time may elapse before the core flushes any posted requests for this
978 * host channel and halts. The Channel Halted interrupt handler completes the
979 * deactivation of the host channel.
981 void dwc2_hc_halt(struct dwc2_hsotg
*hsotg
, struct dwc2_host_chan
*chan
,
982 enum dwc2_halt_status halt_status
)
984 u32 nptxsts
, hptxsts
, hcchar
;
987 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
988 if (halt_status
== DWC2_HC_XFER_NO_HALT_STATUS
)
989 dev_err(hsotg
->dev
, "!!! halt_status = %d !!!\n", halt_status
);
991 if (halt_status
== DWC2_HC_XFER_URB_DEQUEUE
||
992 halt_status
== DWC2_HC_XFER_AHB_ERR
) {
994 * Disable all channel interrupts except Ch Halted. The QTD
995 * and QH state associated with this transfer has been cleared
996 * (in the case of URB_DEQUEUE), so the channel needs to be
997 * shut down carefully to prevent crashes.
999 u32 hcintmsk
= HCINTMSK_CHHLTD
;
1001 dev_vdbg(hsotg
->dev
, "dequeue/error\n");
1002 dwc2_writel(hcintmsk
, hsotg
->regs
+ HCINTMSK(chan
->hc_num
));
1005 * Make sure no other interrupts besides halt are currently
1006 * pending. Handling another interrupt could cause a crash due
1007 * to the QTD and QH state.
1009 dwc2_writel(~hcintmsk
, hsotg
->regs
+ HCINT(chan
->hc_num
));
1012 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1013 * even if the channel was already halted for some other
1016 chan
->halt_status
= halt_status
;
1018 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1019 if (!(hcchar
& HCCHAR_CHENA
)) {
1021 * The channel is either already halted or it hasn't
1022 * started yet. In DMA mode, the transfer may halt if
1023 * it finishes normally or a condition occurs that
1024 * requires driver intervention. Don't want to halt
1025 * the channel again. In either Slave or DMA mode,
1026 * it's possible that the transfer has been assigned
1027 * to a channel, but not started yet when an URB is
1028 * dequeued. Don't want to halt a channel that hasn't
1034 if (chan
->halt_pending
) {
1036 * A halt has already been issued for this channel. This might
1037 * happen when a transfer is aborted by a higher level in
1040 dev_vdbg(hsotg
->dev
,
1041 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1042 __func__
, chan
->hc_num
);
1046 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1048 /* No need to set the bit in DDMA for disabling the channel */
1049 /* TODO check it everywhere channel is disabled */
1050 if (!hsotg
->params
.dma_desc_enable
) {
1052 dev_vdbg(hsotg
->dev
, "desc DMA disabled\n");
1053 hcchar
|= HCCHAR_CHENA
;
1056 dev_dbg(hsotg
->dev
, "desc DMA enabled\n");
1058 hcchar
|= HCCHAR_CHDIS
;
1060 if (!hsotg
->params
.host_dma
) {
1062 dev_vdbg(hsotg
->dev
, "DMA not enabled\n");
1063 hcchar
|= HCCHAR_CHENA
;
1065 /* Check for space in the request queue to issue the halt */
1066 if (chan
->ep_type
== USB_ENDPOINT_XFER_CONTROL
||
1067 chan
->ep_type
== USB_ENDPOINT_XFER_BULK
) {
1068 dev_vdbg(hsotg
->dev
, "control/bulk\n");
1069 nptxsts
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
1070 if ((nptxsts
& TXSTS_QSPCAVAIL_MASK
) == 0) {
1071 dev_vdbg(hsotg
->dev
, "Disabling channel\n");
1072 hcchar
&= ~HCCHAR_CHENA
;
1076 dev_vdbg(hsotg
->dev
, "isoc/intr\n");
1077 hptxsts
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
1078 if ((hptxsts
& TXSTS_QSPCAVAIL_MASK
) == 0 ||
1079 hsotg
->queuing_high_bandwidth
) {
1081 dev_vdbg(hsotg
->dev
, "Disabling channel\n");
1082 hcchar
&= ~HCCHAR_CHENA
;
1087 dev_vdbg(hsotg
->dev
, "DMA enabled\n");
1090 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1091 chan
->halt_status
= halt_status
;
1093 if (hcchar
& HCCHAR_CHENA
) {
1095 dev_vdbg(hsotg
->dev
, "Channel enabled\n");
1096 chan
->halt_pending
= 1;
1097 chan
->halt_on_queue
= 0;
1100 dev_vdbg(hsotg
->dev
, "Channel disabled\n");
1101 chan
->halt_on_queue
= 1;
1105 dev_vdbg(hsotg
->dev
, "%s: Channel %d\n", __func__
,
1107 dev_vdbg(hsotg
->dev
, " hcchar: 0x%08x\n",
1109 dev_vdbg(hsotg
->dev
, " halt_pending: %d\n",
1110 chan
->halt_pending
);
1111 dev_vdbg(hsotg
->dev
, " halt_on_queue: %d\n",
1112 chan
->halt_on_queue
);
1113 dev_vdbg(hsotg
->dev
, " halt_status: %d\n",
1119 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1121 * @hsotg: Programming view of DWC_otg controller
1122 * @chan: Identifies the host channel to clean up
1124 * This function is normally called after a transfer is done and the host
1125 * channel is being released
1127 void dwc2_hc_cleanup(struct dwc2_hsotg
*hsotg
, struct dwc2_host_chan
*chan
)
1131 chan
->xfer_started
= 0;
1133 list_del_init(&chan
->split_order_list_entry
);
1136 * Clear channel interrupt enables and any unhandled channel interrupt
1139 dwc2_writel(0, hsotg
->regs
+ HCINTMSK(chan
->hc_num
));
1140 hcintmsk
= 0xffffffff;
1141 hcintmsk
&= ~HCINTMSK_RESERVED14_31
;
1142 dwc2_writel(hcintmsk
, hsotg
->regs
+ HCINT(chan
->hc_num
));
1146 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1147 * which frame a periodic transfer should occur
1149 * @hsotg: Programming view of DWC_otg controller
1150 * @chan: Identifies the host channel to set up and its properties
1151 * @hcchar: Current value of the HCCHAR register for the specified host channel
1153 * This function has no effect on non-periodic transfers
1155 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg
*hsotg
,
1156 struct dwc2_host_chan
*chan
, u32
*hcchar
)
1158 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
1159 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
) {
1169 * Try to figure out if we're an even or odd frame. If we set
1170 * even and the current frame number is even the the transfer
1171 * will happen immediately. Similar if both are odd. If one is
1172 * even and the other is odd then the transfer will happen when
1173 * the frame number ticks.
1175 * There's a bit of a balancing act to get this right.
1176 * Sometimes we may want to send data in the current frame (AK
1177 * right away). We might want to do this if the frame number
1178 * _just_ ticked, but we might also want to do this in order
1179 * to continue a split transaction that happened late in a
1180 * microframe (so we didn't know to queue the next transfer
1181 * until the frame number had ticked). The problem is that we
1182 * need a lot of knowledge to know if there's actually still
1183 * time to send things or if it would be better to wait until
1186 * We can look at how much time is left in the current frame
1187 * and make a guess about whether we'll have time to transfer.
1191 /* Get speed host is running at */
1192 host_speed
= (chan
->speed
!= USB_SPEED_HIGH
&&
1193 !chan
->do_split
) ? chan
->speed
: USB_SPEED_HIGH
;
1195 /* See how many bytes are in the periodic FIFO right now */
1196 fifo_space
= (dwc2_readl(hsotg
->regs
+ HPTXSTS
) &
1197 TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
;
1198 bytes_in_fifo
= sizeof(u32
) *
1199 (hsotg
->params
.host_perio_tx_fifo_size
-
1203 * Roughly estimate bus time for everything in the periodic
1204 * queue + our new transfer. This is "rough" because we're
1205 * using a function that makes takes into account IN/OUT
1206 * and INT/ISO and we're just slamming in one value for all
1207 * transfers. This should be an over-estimate and that should
1208 * be OK, but we can probably tighten it.
1210 xfer_ns
= usb_calc_bus_time(host_speed
, false, false,
1211 chan
->xfer_len
+ bytes_in_fifo
);
1212 xfer_us
= NS_TO_US(xfer_ns
);
1214 /* See what frame number we'll be at by the time we finish */
1215 frame_number
= dwc2_hcd_get_future_frame_number(hsotg
, xfer_us
);
1217 /* This is when we were scheduled to be on the wire */
1218 wire_frame
= dwc2_frame_num_inc(chan
->qh
->next_active_frame
, 1);
1221 * If we'd finish _after_ the frame we're scheduled in then
1222 * it's hopeless. Just schedule right away and hope for the
1223 * best. Note that it _might_ be wise to call back into the
1224 * scheduler to pick a better frame, but this is better than
1227 if (dwc2_frame_num_gt(frame_number
, wire_frame
)) {
1228 dwc2_sch_vdbg(hsotg
,
1229 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1230 chan
->qh
, wire_frame
, frame_number
,
1231 dwc2_frame_num_dec(frame_number
,
1233 wire_frame
= frame_number
;
1236 * We picked a different frame number; communicate this
1237 * back to the scheduler so it doesn't try to schedule
1238 * another in the same frame.
1240 * Remember that next_active_frame is 1 before the wire
1243 chan
->qh
->next_active_frame
=
1244 dwc2_frame_num_dec(frame_number
, 1);
1248 *hcchar
|= HCCHAR_ODDFRM
;
1250 *hcchar
&= ~HCCHAR_ODDFRM
;
1254 static void dwc2_set_pid_isoc(struct dwc2_host_chan
*chan
)
1256 /* Set up the initial PID for the transfer */
1257 if (chan
->speed
== USB_SPEED_HIGH
) {
1258 if (chan
->ep_is_in
) {
1259 if (chan
->multi_count
== 1)
1260 chan
->data_pid_start
= DWC2_HC_PID_DATA0
;
1261 else if (chan
->multi_count
== 2)
1262 chan
->data_pid_start
= DWC2_HC_PID_DATA1
;
1264 chan
->data_pid_start
= DWC2_HC_PID_DATA2
;
1266 if (chan
->multi_count
== 1)
1267 chan
->data_pid_start
= DWC2_HC_PID_DATA0
;
1269 chan
->data_pid_start
= DWC2_HC_PID_MDATA
;
1272 chan
->data_pid_start
= DWC2_HC_PID_DATA0
;
1277 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1280 * @hsotg: Programming view of DWC_otg controller
1281 * @chan: Information needed to initialize the host channel
1283 * This function should only be called in Slave mode. For a channel associated
1284 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1285 * associated with a periodic EP, the periodic Tx FIFO is written.
1287 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1288 * the number of bytes written to the Tx FIFO.
1290 static void dwc2_hc_write_packet(struct dwc2_hsotg
*hsotg
,
1291 struct dwc2_host_chan
*chan
)
1294 u32 remaining_count
;
1297 u32 __iomem
*data_fifo
;
1298 u32
*data_buf
= (u32
*)chan
->xfer_buf
;
1301 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
1303 data_fifo
= (u32 __iomem
*)(hsotg
->regs
+ HCFIFO(chan
->hc_num
));
1305 remaining_count
= chan
->xfer_len
- chan
->xfer_count
;
1306 if (remaining_count
> chan
->max_packet
)
1307 byte_count
= chan
->max_packet
;
1309 byte_count
= remaining_count
;
1311 dword_count
= (byte_count
+ 3) / 4;
1313 if (((unsigned long)data_buf
& 0x3) == 0) {
1314 /* xfer_buf is DWORD aligned */
1315 for (i
= 0; i
< dword_count
; i
++, data_buf
++)
1316 dwc2_writel(*data_buf
, data_fifo
);
1318 /* xfer_buf is not DWORD aligned */
1319 for (i
= 0; i
< dword_count
; i
++, data_buf
++) {
1320 u32 data
= data_buf
[0] | data_buf
[1] << 8 |
1321 data_buf
[2] << 16 | data_buf
[3] << 24;
1322 dwc2_writel(data
, data_fifo
);
1326 chan
->xfer_count
+= byte_count
;
1327 chan
->xfer_buf
+= byte_count
;
1331 * dwc2_hc_do_ping() - Starts a PING transfer
1333 * @hsotg: Programming view of DWC_otg controller
1334 * @chan: Information needed to initialize the host channel
1336 * This function should only be called in Slave mode. The Do Ping bit is set in
1337 * the HCTSIZ register, then the channel is enabled.
1339 static void dwc2_hc_do_ping(struct dwc2_hsotg
*hsotg
,
1340 struct dwc2_host_chan
*chan
)
1346 dev_vdbg(hsotg
->dev
, "%s: Channel %d\n", __func__
,
1349 hctsiz
= TSIZ_DOPNG
;
1350 hctsiz
|= 1 << TSIZ_PKTCNT_SHIFT
;
1351 dwc2_writel(hctsiz
, hsotg
->regs
+ HCTSIZ(chan
->hc_num
));
1353 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1354 hcchar
|= HCCHAR_CHENA
;
1355 hcchar
&= ~HCCHAR_CHDIS
;
1356 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1360 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1361 * channel and starts the transfer
1363 * @hsotg: Programming view of DWC_otg controller
1364 * @chan: Information needed to initialize the host channel. The xfer_len value
1365 * may be reduced to accommodate the max widths of the XferSize and
1366 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1367 * changed to reflect the final xfer_len value.
1369 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1370 * the caller must ensure that there is sufficient space in the request queue
1373 * For an OUT transfer in Slave mode, it loads a data packet into the
1374 * appropriate FIFO. If necessary, additional data packets are loaded in the
1377 * For an IN transfer in Slave mode, a data packet is requested. The data
1378 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1379 * additional data packets are requested in the Host ISR.
1381 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1382 * register along with a packet count of 1 and the channel is enabled. This
1383 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1384 * simply set to 0 since no data transfer occurs in this case.
1386 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1387 * all the information required to perform the subsequent data transfer. In
1388 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1389 * controller performs the entire PING protocol, then starts the data
1392 static void dwc2_hc_start_transfer(struct dwc2_hsotg
*hsotg
,
1393 struct dwc2_host_chan
*chan
)
1395 u32 max_hc_xfer_size
= hsotg
->params
.max_transfer_size
;
1396 u16 max_hc_pkt_count
= hsotg
->params
.max_packet_count
;
1403 dev_vdbg(hsotg
->dev
, "%s()\n", __func__
);
1405 if (chan
->do_ping
) {
1406 if (!hsotg
->params
.host_dma
) {
1408 dev_vdbg(hsotg
->dev
, "ping, no DMA\n");
1409 dwc2_hc_do_ping(hsotg
, chan
);
1410 chan
->xfer_started
= 1;
1415 dev_vdbg(hsotg
->dev
, "ping, DMA\n");
1417 hctsiz
|= TSIZ_DOPNG
;
1420 if (chan
->do_split
) {
1422 dev_vdbg(hsotg
->dev
, "split\n");
1425 if (chan
->complete_split
&& !chan
->ep_is_in
)
1427 * For CSPLIT OUT Transfer, set the size to 0 so the
1428 * core doesn't expect any data written to the FIFO
1431 else if (chan
->ep_is_in
|| chan
->xfer_len
> chan
->max_packet
)
1432 chan
->xfer_len
= chan
->max_packet
;
1433 else if (!chan
->ep_is_in
&& chan
->xfer_len
> 188)
1434 chan
->xfer_len
= 188;
1436 hctsiz
|= chan
->xfer_len
<< TSIZ_XFERSIZE_SHIFT
&
1439 /* For split set ec_mc for immediate retries */
1440 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
1441 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
1447 dev_vdbg(hsotg
->dev
, "no split\n");
1449 * Ensure that the transfer length and packet count will fit
1450 * in the widths allocated for them in the HCTSIZn register
1452 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
1453 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
) {
1455 * Make sure the transfer size is no larger than one
1456 * (micro)frame's worth of data. (A check was done
1457 * when the periodic transfer was accepted to ensure
1458 * that a (micro)frame's worth of data can be
1459 * programmed into a channel.)
1461 u32 max_periodic_len
=
1462 chan
->multi_count
* chan
->max_packet
;
1464 if (chan
->xfer_len
> max_periodic_len
)
1465 chan
->xfer_len
= max_periodic_len
;
1466 } else if (chan
->xfer_len
> max_hc_xfer_size
) {
1468 * Make sure that xfer_len is a multiple of max packet
1472 max_hc_xfer_size
- chan
->max_packet
+ 1;
1475 if (chan
->xfer_len
> 0) {
1476 num_packets
= (chan
->xfer_len
+ chan
->max_packet
- 1) /
1478 if (num_packets
> max_hc_pkt_count
) {
1479 num_packets
= max_hc_pkt_count
;
1480 chan
->xfer_len
= num_packets
* chan
->max_packet
;
1483 /* Need 1 packet for transfer length of 0 */
1489 * Always program an integral # of max packets for IN
1492 chan
->xfer_len
= num_packets
* chan
->max_packet
;
1494 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
1495 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
1497 * Make sure that the multi_count field matches the
1498 * actual transfer length
1500 chan
->multi_count
= num_packets
;
1502 if (chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
1503 dwc2_set_pid_isoc(chan
);
1505 hctsiz
|= chan
->xfer_len
<< TSIZ_XFERSIZE_SHIFT
&
1508 /* The ec_mc gets the multi_count for non-split */
1509 ec_mc
= chan
->multi_count
;
1512 chan
->start_pkt_count
= num_packets
;
1513 hctsiz
|= num_packets
<< TSIZ_PKTCNT_SHIFT
& TSIZ_PKTCNT_MASK
;
1514 hctsiz
|= chan
->data_pid_start
<< TSIZ_SC_MC_PID_SHIFT
&
1515 TSIZ_SC_MC_PID_MASK
;
1516 dwc2_writel(hctsiz
, hsotg
->regs
+ HCTSIZ(chan
->hc_num
));
1518 dev_vdbg(hsotg
->dev
, "Wrote %08x to HCTSIZ(%d)\n",
1519 hctsiz
, chan
->hc_num
);
1521 dev_vdbg(hsotg
->dev
, "%s: Channel %d\n", __func__
,
1523 dev_vdbg(hsotg
->dev
, " Xfer Size: %d\n",
1524 (hctsiz
& TSIZ_XFERSIZE_MASK
) >>
1525 TSIZ_XFERSIZE_SHIFT
);
1526 dev_vdbg(hsotg
->dev
, " Num Pkts: %d\n",
1527 (hctsiz
& TSIZ_PKTCNT_MASK
) >>
1529 dev_vdbg(hsotg
->dev
, " Start PID: %d\n",
1530 (hctsiz
& TSIZ_SC_MC_PID_MASK
) >>
1531 TSIZ_SC_MC_PID_SHIFT
);
1534 if (hsotg
->params
.host_dma
) {
1535 dwc2_writel((u32
)chan
->xfer_dma
,
1536 hsotg
->regs
+ HCDMA(chan
->hc_num
));
1538 dev_vdbg(hsotg
->dev
, "Wrote %08lx to HCDMA(%d)\n",
1539 (unsigned long)chan
->xfer_dma
, chan
->hc_num
);
1542 /* Start the split */
1543 if (chan
->do_split
) {
1544 u32 hcsplt
= dwc2_readl(hsotg
->regs
+ HCSPLT(chan
->hc_num
));
1546 hcsplt
|= HCSPLT_SPLTENA
;
1547 dwc2_writel(hcsplt
, hsotg
->regs
+ HCSPLT(chan
->hc_num
));
1550 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1551 hcchar
&= ~HCCHAR_MULTICNT_MASK
;
1552 hcchar
|= (ec_mc
<< HCCHAR_MULTICNT_SHIFT
) & HCCHAR_MULTICNT_MASK
;
1553 dwc2_hc_set_even_odd_frame(hsotg
, chan
, &hcchar
);
1555 if (hcchar
& HCCHAR_CHDIS
)
1556 dev_warn(hsotg
->dev
,
1557 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1558 __func__
, chan
->hc_num
, hcchar
);
1560 /* Set host channel enable after all other setup is complete */
1561 hcchar
|= HCCHAR_CHENA
;
1562 hcchar
&= ~HCCHAR_CHDIS
;
1565 dev_vdbg(hsotg
->dev
, " Multi Cnt: %d\n",
1566 (hcchar
& HCCHAR_MULTICNT_MASK
) >>
1567 HCCHAR_MULTICNT_SHIFT
);
1569 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1571 dev_vdbg(hsotg
->dev
, "Wrote %08x to HCCHAR(%d)\n", hcchar
,
1574 chan
->xfer_started
= 1;
1577 if (!hsotg
->params
.host_dma
&&
1578 !chan
->ep_is_in
&& chan
->xfer_len
> 0)
1579 /* Load OUT packet into the appropriate Tx FIFO */
1580 dwc2_hc_write_packet(hsotg
, chan
);
1584 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1585 * host channel and starts the transfer in Descriptor DMA mode
1587 * @hsotg: Programming view of DWC_otg controller
1588 * @chan: Information needed to initialize the host channel
1590 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1591 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1592 * with micro-frame bitmap.
1594 * Initializes HCDMA register with descriptor list address and CTD value then
1595 * starts the transfer via enabling the channel.
1597 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg
*hsotg
,
1598 struct dwc2_host_chan
*chan
)
1604 hctsiz
|= TSIZ_DOPNG
;
1606 if (chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
1607 dwc2_set_pid_isoc(chan
);
1609 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1610 hctsiz
|= chan
->data_pid_start
<< TSIZ_SC_MC_PID_SHIFT
&
1611 TSIZ_SC_MC_PID_MASK
;
1613 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1614 hctsiz
|= (chan
->ntd
- 1) << TSIZ_NTD_SHIFT
& TSIZ_NTD_MASK
;
1616 /* Non-zero only for high-speed interrupt endpoints */
1617 hctsiz
|= chan
->schinfo
<< TSIZ_SCHINFO_SHIFT
& TSIZ_SCHINFO_MASK
;
1620 dev_vdbg(hsotg
->dev
, "%s: Channel %d\n", __func__
,
1622 dev_vdbg(hsotg
->dev
, " Start PID: %d\n",
1623 chan
->data_pid_start
);
1624 dev_vdbg(hsotg
->dev
, " NTD: %d\n", chan
->ntd
- 1);
1627 dwc2_writel(hctsiz
, hsotg
->regs
+ HCTSIZ(chan
->hc_num
));
1629 dma_sync_single_for_device(hsotg
->dev
, chan
->desc_list_addr
,
1630 chan
->desc_list_sz
, DMA_TO_DEVICE
);
1632 dwc2_writel(chan
->desc_list_addr
, hsotg
->regs
+ HCDMA(chan
->hc_num
));
1635 dev_vdbg(hsotg
->dev
, "Wrote %pad to HCDMA(%d)\n",
1636 &chan
->desc_list_addr
, chan
->hc_num
);
1638 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1639 hcchar
&= ~HCCHAR_MULTICNT_MASK
;
1640 hcchar
|= chan
->multi_count
<< HCCHAR_MULTICNT_SHIFT
&
1641 HCCHAR_MULTICNT_MASK
;
1643 if (hcchar
& HCCHAR_CHDIS
)
1644 dev_warn(hsotg
->dev
,
1645 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1646 __func__
, chan
->hc_num
, hcchar
);
1648 /* Set host channel enable after all other setup is complete */
1649 hcchar
|= HCCHAR_CHENA
;
1650 hcchar
&= ~HCCHAR_CHDIS
;
1653 dev_vdbg(hsotg
->dev
, " Multi Cnt: %d\n",
1654 (hcchar
& HCCHAR_MULTICNT_MASK
) >>
1655 HCCHAR_MULTICNT_SHIFT
);
1657 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1659 dev_vdbg(hsotg
->dev
, "Wrote %08x to HCCHAR(%d)\n", hcchar
,
1662 chan
->xfer_started
= 1;
1667 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1668 * a previous call to dwc2_hc_start_transfer()
1670 * @hsotg: Programming view of DWC_otg controller
1671 * @chan: Information needed to initialize the host channel
1673 * The caller must ensure there is sufficient space in the request queue and Tx
1674 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1675 * the controller acts autonomously to complete transfers programmed to a host
1678 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1679 * if there is any data remaining to be queued. For an IN transfer, another
1680 * data packet is always requested. For the SETUP phase of a control transfer,
1681 * this function does nothing.
1683 * Return: 1 if a new request is queued, 0 if no more requests are required
1686 static int dwc2_hc_continue_transfer(struct dwc2_hsotg
*hsotg
,
1687 struct dwc2_host_chan
*chan
)
1690 dev_vdbg(hsotg
->dev
, "%s: Channel %d\n", __func__
,
1694 /* SPLITs always queue just once per channel */
1697 if (chan
->data_pid_start
== DWC2_HC_PID_SETUP
)
1698 /* SETUPs are queued only once since they can't be NAK'd */
1701 if (chan
->ep_is_in
) {
1703 * Always queue another request for other IN transfers. If
1704 * back-to-back INs are issued and NAKs are received for both,
1705 * the driver may still be processing the first NAK when the
1706 * second NAK is received. When the interrupt handler clears
1707 * the NAK interrupt for the first NAK, the second NAK will
1708 * not be seen. So we can't depend on the NAK interrupt
1709 * handler to requeue a NAK'd request. Instead, IN requests
1710 * are issued each time this function is called. When the
1711 * transfer completes, the extra requests for the channel will
1714 u32 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1716 dwc2_hc_set_even_odd_frame(hsotg
, chan
, &hcchar
);
1717 hcchar
|= HCCHAR_CHENA
;
1718 hcchar
&= ~HCCHAR_CHDIS
;
1720 dev_vdbg(hsotg
->dev
, " IN xfer: hcchar = 0x%08x\n",
1722 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(chan
->hc_num
));
1729 if (chan
->xfer_count
< chan
->xfer_len
) {
1730 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
1731 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
) {
1732 u32 hcchar
= dwc2_readl(hsotg
->regs
+
1733 HCCHAR(chan
->hc_num
));
1735 dwc2_hc_set_even_odd_frame(hsotg
, chan
,
1739 /* Load OUT packet into the appropriate Tx FIFO */
1740 dwc2_hc_write_packet(hsotg
, chan
);
1749 * =========================================================================
1751 * =========================================================================
1755 * Processes all the URBs in a single list of QHs. Completes them with
1756 * -ETIMEDOUT and frees the QTD.
1758 * Must be called with interrupt disabled and spinlock held
1760 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg
*hsotg
,
1761 struct list_head
*qh_list
)
1763 struct dwc2_qh
*qh
, *qh_tmp
;
1764 struct dwc2_qtd
*qtd
, *qtd_tmp
;
1766 list_for_each_entry_safe(qh
, qh_tmp
, qh_list
, qh_list_entry
) {
1767 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
,
1769 dwc2_host_complete(hsotg
, qtd
, -ECONNRESET
);
1770 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
1775 static void dwc2_qh_list_free(struct dwc2_hsotg
*hsotg
,
1776 struct list_head
*qh_list
)
1778 struct dwc2_qtd
*qtd
, *qtd_tmp
;
1779 struct dwc2_qh
*qh
, *qh_tmp
;
1780 unsigned long flags
;
1783 /* The list hasn't been initialized yet */
1786 spin_lock_irqsave(&hsotg
->lock
, flags
);
1788 /* Ensure there are no QTDs or URBs left */
1789 dwc2_kill_urbs_in_qh_list(hsotg
, qh_list
);
1791 list_for_each_entry_safe(qh
, qh_tmp
, qh_list
, qh_list_entry
) {
1792 dwc2_hcd_qh_unlink(hsotg
, qh
);
1794 /* Free each QTD in the QH's QTD list */
1795 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
,
1797 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
1799 if (qh
->channel
&& qh
->channel
->qh
== qh
)
1800 qh
->channel
->qh
= NULL
;
1802 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1803 dwc2_hcd_qh_free(hsotg
, qh
);
1804 spin_lock_irqsave(&hsotg
->lock
, flags
);
1807 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1811 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1812 * and periodic schedules. The QTD associated with each URB is removed from
1813 * the schedule and freed. This function may be called when a disconnect is
1814 * detected or when the HCD is being stopped.
1816 * Must be called with interrupt disabled and spinlock held
1818 static void dwc2_kill_all_urbs(struct dwc2_hsotg
*hsotg
)
1820 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->non_periodic_sched_inactive
);
1821 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->non_periodic_sched_active
);
1822 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_inactive
);
1823 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_ready
);
1824 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_assigned
);
1825 dwc2_kill_urbs_in_qh_list(hsotg
, &hsotg
->periodic_sched_queued
);
1829 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1831 * @hsotg: Pointer to struct dwc2_hsotg
1833 void dwc2_hcd_start(struct dwc2_hsotg
*hsotg
)
1837 if (hsotg
->op_state
== OTG_STATE_B_HOST
) {
1839 * Reset the port. During a HNP mode switch the reset
1840 * needs to occur within 1ms and have a duration of at
1843 hprt0
= dwc2_read_hprt0(hsotg
);
1845 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
1848 queue_delayed_work(hsotg
->wq_otg
, &hsotg
->start_work
,
1849 msecs_to_jiffies(50));
1852 /* Must be called with interrupt disabled and spinlock held */
1853 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg
*hsotg
)
1855 int num_channels
= hsotg
->params
.host_channels
;
1856 struct dwc2_host_chan
*channel
;
1860 if (!hsotg
->params
.host_dma
) {
1861 /* Flush out any channel requests in slave mode */
1862 for (i
= 0; i
< num_channels
; i
++) {
1863 channel
= hsotg
->hc_ptr_array
[i
];
1864 if (!list_empty(&channel
->hc_list_entry
))
1866 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
1867 if (hcchar
& HCCHAR_CHENA
) {
1868 hcchar
&= ~(HCCHAR_CHENA
| HCCHAR_EPDIR
);
1869 hcchar
|= HCCHAR_CHDIS
;
1870 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
1875 for (i
= 0; i
< num_channels
; i
++) {
1876 channel
= hsotg
->hc_ptr_array
[i
];
1877 if (!list_empty(&channel
->hc_list_entry
))
1879 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
1880 if (hcchar
& HCCHAR_CHENA
) {
1881 /* Halt the channel */
1882 hcchar
|= HCCHAR_CHDIS
;
1883 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
1886 dwc2_hc_cleanup(hsotg
, channel
);
1887 list_add_tail(&channel
->hc_list_entry
, &hsotg
->free_hc_list
);
1889 * Added for Descriptor DMA to prevent channel double cleanup in
1890 * release_channel_ddma(), which is called from ep_disable when
1891 * device disconnects
1895 /* All channels have been freed, mark them available */
1896 if (hsotg
->params
.uframe_sched
) {
1897 hsotg
->available_host_channels
=
1898 hsotg
->params
.host_channels
;
1900 hsotg
->non_periodic_channels
= 0;
1901 hsotg
->periodic_channels
= 0;
1906 * dwc2_hcd_connect() - Handles connect of the HCD
1908 * @hsotg: Pointer to struct dwc2_hsotg
1910 * Must be called with interrupt disabled and spinlock held
1912 void dwc2_hcd_connect(struct dwc2_hsotg
*hsotg
)
1914 if (hsotg
->lx_state
!= DWC2_L0
)
1915 usb_hcd_resume_root_hub(hsotg
->priv
);
1917 hsotg
->flags
.b
.port_connect_status_change
= 1;
1918 hsotg
->flags
.b
.port_connect_status
= 1;
1922 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1924 * @hsotg: Pointer to struct dwc2_hsotg
1925 * @force: If true, we won't try to reconnect even if we see device connected.
1927 * Must be called with interrupt disabled and spinlock held
1929 void dwc2_hcd_disconnect(struct dwc2_hsotg
*hsotg
, bool force
)
1934 /* Set status flags for the hub driver */
1935 hsotg
->flags
.b
.port_connect_status_change
= 1;
1936 hsotg
->flags
.b
.port_connect_status
= 0;
1939 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1940 * interrupt mask and status bits and disabling subsequent host
1941 * channel interrupts.
1943 intr
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
1944 intr
&= ~(GINTSTS_NPTXFEMP
| GINTSTS_PTXFEMP
| GINTSTS_HCHINT
);
1945 dwc2_writel(intr
, hsotg
->regs
+ GINTMSK
);
1946 intr
= GINTSTS_NPTXFEMP
| GINTSTS_PTXFEMP
| GINTSTS_HCHINT
;
1947 dwc2_writel(intr
, hsotg
->regs
+ GINTSTS
);
1950 * Turn off the vbus power only if the core has transitioned to device
1951 * mode. If still in host mode, need to keep power on to detect a
1954 if (dwc2_is_device_mode(hsotg
)) {
1955 if (hsotg
->op_state
!= OTG_STATE_A_SUSPEND
) {
1956 dev_dbg(hsotg
->dev
, "Disconnect: PortPower off\n");
1957 dwc2_writel(0, hsotg
->regs
+ HPRT0
);
1960 dwc2_disable_host_interrupts(hsotg
);
1963 /* Respond with an error status to all URBs in the schedule */
1964 dwc2_kill_all_urbs(hsotg
);
1966 if (dwc2_is_host_mode(hsotg
))
1967 /* Clean up any host channels that were in use */
1968 dwc2_hcd_cleanup_channels(hsotg
);
1970 dwc2_host_disconnect(hsotg
);
1973 * Add an extra check here to see if we're actually connected but
1974 * we don't have a detection interrupt pending. This can happen if:
1975 * 1. hardware sees connect
1976 * 2. hardware sees disconnect
1977 * 3. hardware sees connect
1978 * 4. dwc2_port_intr() - clears connect interrupt
1979 * 5. dwc2_handle_common_intr() - calls here
1981 * Without the extra check here we will end calling disconnect
1982 * and won't get any future interrupts to handle the connect.
1985 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
1986 if (!(hprt0
& HPRT0_CONNDET
) && (hprt0
& HPRT0_CONNSTS
))
1987 dwc2_hcd_connect(hsotg
);
1992 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1994 * @hsotg: Pointer to struct dwc2_hsotg
1996 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg
*hsotg
)
1998 if (hsotg
->bus_suspended
) {
1999 hsotg
->flags
.b
.port_suspend_change
= 1;
2000 usb_hcd_resume_root_hub(hsotg
->priv
);
2003 if (hsotg
->lx_state
== DWC2_L1
)
2004 hsotg
->flags
.b
.port_l1_change
= 1;
2008 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2010 * @hsotg: Pointer to struct dwc2_hsotg
2012 * Must be called with interrupt disabled and spinlock held
2014 void dwc2_hcd_stop(struct dwc2_hsotg
*hsotg
)
2016 dev_dbg(hsotg
->dev
, "DWC OTG HCD STOP\n");
2019 * The root hub should be disconnected before this function is called.
2020 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2021 * and the QH lists (via ..._hcd_endpoint_disable).
2024 /* Turn off all host-specific interrupts */
2025 dwc2_disable_host_interrupts(hsotg
);
2027 /* Turn off the vbus power */
2028 dev_dbg(hsotg
->dev
, "PortPower off\n");
2029 dwc2_writel(0, hsotg
->regs
+ HPRT0
);
2032 /* Caller must hold driver lock */
2033 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg
*hsotg
,
2034 struct dwc2_hcd_urb
*urb
, struct dwc2_qh
*qh
,
2035 struct dwc2_qtd
*qtd
)
2041 if (!hsotg
->flags
.b
.port_connect_status
) {
2042 /* No longer connected */
2043 dev_err(hsotg
->dev
, "Not connected\n");
2047 dev_speed
= dwc2_host_get_speed(hsotg
, urb
->priv
);
2049 /* Some configurations cannot support LS traffic on a FS root port */
2050 if ((dev_speed
== USB_SPEED_LOW
) &&
2051 (hsotg
->hw_params
.fs_phy_type
== GHWCFG2_FS_PHY_TYPE_DEDICATED
) &&
2052 (hsotg
->hw_params
.hs_phy_type
== GHWCFG2_HS_PHY_TYPE_UTMI
)) {
2053 u32 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
2054 u32 prtspd
= (hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
2056 if (prtspd
== HPRT0_SPD_FULL_SPEED
)
2063 dwc2_hcd_qtd_init(qtd
, urb
);
2064 retval
= dwc2_hcd_qtd_add(hsotg
, qtd
, qh
);
2067 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2072 intr_mask
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
2073 if (!(intr_mask
& GINTSTS_SOF
)) {
2074 enum dwc2_transaction_type tr_type
;
2076 if (qtd
->qh
->ep_type
== USB_ENDPOINT_XFER_BULK
&&
2077 !(qtd
->urb
->flags
& URB_GIVEBACK_ASAP
))
2079 * Do not schedule SG transactions until qtd has
2080 * URB_GIVEBACK_ASAP set
2084 tr_type
= dwc2_hcd_select_transactions(hsotg
);
2085 if (tr_type
!= DWC2_TRANSACTION_NONE
)
2086 dwc2_hcd_queue_transactions(hsotg
, tr_type
);
2092 /* Must be called with interrupt disabled and spinlock held */
2093 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg
*hsotg
,
2094 struct dwc2_hcd_urb
*urb
)
2097 struct dwc2_qtd
*urb_qtd
;
2101 dev_dbg(hsotg
->dev
, "## Urb QTD is NULL ##\n");
2107 dev_dbg(hsotg
->dev
, "## Urb QTD QH is NULL ##\n");
2113 if (urb_qtd
->in_process
&& qh
->channel
) {
2114 dwc2_dump_channel_info(hsotg
, qh
->channel
);
2116 /* The QTD is in process (it has been assigned to a channel) */
2117 if (hsotg
->flags
.b
.port_connect_status
)
2119 * If still connected (i.e. in host mode), halt the
2120 * channel so it can be used for other transfers. If
2121 * no longer connected, the host registers can't be
2122 * written to halt the channel since the core is in
2125 dwc2_hc_halt(hsotg
, qh
->channel
,
2126 DWC2_HC_XFER_URB_DEQUEUE
);
2130 * Free the QTD and clean up the associated QH. Leave the QH in the
2131 * schedule if it has any remaining QTDs.
2133 if (!hsotg
->params
.dma_desc_enable
) {
2134 u8 in_process
= urb_qtd
->in_process
;
2136 dwc2_hcd_qtd_unlink_and_free(hsotg
, urb_qtd
, qh
);
2138 dwc2_hcd_qh_deactivate(hsotg
, qh
, 0);
2140 } else if (list_empty(&qh
->qtd_list
)) {
2141 dwc2_hcd_qh_unlink(hsotg
, qh
);
2144 dwc2_hcd_qtd_unlink_and_free(hsotg
, urb_qtd
, qh
);
2150 /* Must NOT be called with interrupt disabled or spinlock held */
2151 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg
*hsotg
,
2152 struct usb_host_endpoint
*ep
, int retry
)
2154 struct dwc2_qtd
*qtd
, *qtd_tmp
;
2156 unsigned long flags
;
2159 spin_lock_irqsave(&hsotg
->lock
, flags
);
2167 while (!list_empty(&qh
->qtd_list
) && retry
--) {
2170 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2175 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2177 spin_lock_irqsave(&hsotg
->lock
, flags
);
2185 dwc2_hcd_qh_unlink(hsotg
, qh
);
2187 /* Free each QTD in the QH's QTD list */
2188 list_for_each_entry_safe(qtd
, qtd_tmp
, &qh
->qtd_list
, qtd_list_entry
)
2189 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd
, qh
);
2193 if (qh
->channel
&& qh
->channel
->qh
== qh
)
2194 qh
->channel
->qh
= NULL
;
2196 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2198 dwc2_hcd_qh_free(hsotg
, qh
);
2204 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2209 /* Must be called with interrupt disabled and spinlock held */
2210 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg
*hsotg
,
2211 struct usb_host_endpoint
*ep
)
2213 struct dwc2_qh
*qh
= ep
->hcpriv
;
2218 qh
->data_toggle
= DWC2_HC_PID_DATA0
;
2224 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2225 * prepares the core for device mode or host mode operation
2227 * @hsotg: Programming view of the DWC_otg controller
2228 * @initial_setup: If true then this is the first init for this instance.
2230 static int dwc2_core_init(struct dwc2_hsotg
*hsotg
, bool initial_setup
)
2235 dev_dbg(hsotg
->dev
, "%s(%p)\n", __func__
, hsotg
);
2237 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
2239 /* Set ULPI External VBUS bit if needed */
2240 usbcfg
&= ~GUSBCFG_ULPI_EXT_VBUS_DRV
;
2241 if (hsotg
->params
.phy_ulpi_ext_vbus
)
2242 usbcfg
|= GUSBCFG_ULPI_EXT_VBUS_DRV
;
2244 /* Set external TS Dline pulsing bit if needed */
2245 usbcfg
&= ~GUSBCFG_TERMSELDLPULSE
;
2246 if (hsotg
->params
.ts_dline
)
2247 usbcfg
|= GUSBCFG_TERMSELDLPULSE
;
2249 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
2252 * Reset the Controller
2254 * We only need to reset the controller if this is a re-init.
2255 * For the first init we know for sure that earlier code reset us (it
2256 * needed to in order to properly detect various parameters).
2258 if (!initial_setup
) {
2259 retval
= dwc2_core_reset_and_force_dr_mode(hsotg
);
2261 dev_err(hsotg
->dev
, "%s(): Reset failed, aborting\n",
2268 * This needs to happen in FS mode before any other programming occurs
2270 retval
= dwc2_phy_init(hsotg
, initial_setup
);
2274 /* Program the GAHBCFG Register */
2275 retval
= dwc2_gahbcfg_init(hsotg
);
2279 /* Program the GUSBCFG register */
2280 dwc2_gusbcfg_init(hsotg
);
2282 /* Program the GOTGCTL register */
2283 otgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
2284 otgctl
&= ~GOTGCTL_OTGVER
;
2285 dwc2_writel(otgctl
, hsotg
->regs
+ GOTGCTL
);
2287 /* Clear the SRP success bit for FS-I2c */
2288 hsotg
->srp_success
= 0;
2290 /* Enable common interrupts */
2291 dwc2_enable_common_interrupts(hsotg
);
2294 * Do device or host initialization based on mode during PCD and
2295 * HCD initialization
2297 if (dwc2_is_host_mode(hsotg
)) {
2298 dev_dbg(hsotg
->dev
, "Host Mode\n");
2299 hsotg
->op_state
= OTG_STATE_A_HOST
;
2301 dev_dbg(hsotg
->dev
, "Device Mode\n");
2302 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
2309 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2312 * @hsotg: Programming view of DWC_otg controller
2314 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2315 * request queues. Host channels are reset to ensure that they are ready for
2316 * performing transfers.
2318 static void dwc2_core_host_init(struct dwc2_hsotg
*hsotg
)
2320 u32 hcfg
, hfir
, otgctl
;
2322 dev_dbg(hsotg
->dev
, "%s(%p)\n", __func__
, hsotg
);
2324 /* Restart the Phy Clock */
2325 dwc2_writel(0, hsotg
->regs
+ PCGCTL
);
2327 /* Initialize Host Configuration Register */
2328 dwc2_init_fs_ls_pclk_sel(hsotg
);
2329 if (hsotg
->params
.speed
== DWC2_SPEED_PARAM_FULL
||
2330 hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
) {
2331 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
2332 hcfg
|= HCFG_FSLSSUPP
;
2333 dwc2_writel(hcfg
, hsotg
->regs
+ HCFG
);
2337 * This bit allows dynamic reloading of the HFIR register during
2338 * runtime. This bit needs to be programmed during initial configuration
2339 * and its value must not be changed during runtime.
2341 if (hsotg
->params
.reload_ctl
) {
2342 hfir
= dwc2_readl(hsotg
->regs
+ HFIR
);
2343 hfir
|= HFIR_RLDCTRL
;
2344 dwc2_writel(hfir
, hsotg
->regs
+ HFIR
);
2347 if (hsotg
->params
.dma_desc_enable
) {
2348 u32 op_mode
= hsotg
->hw_params
.op_mode
;
2350 if (hsotg
->hw_params
.snpsid
< DWC2_CORE_REV_2_90a
||
2351 !hsotg
->hw_params
.dma_desc_enable
||
2352 op_mode
== GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
||
2353 op_mode
== GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE
||
2354 op_mode
== GHWCFG2_OP_MODE_UNDEFINED
) {
2356 "Hardware does not support descriptor DMA mode -\n");
2358 "falling back to buffer DMA mode.\n");
2359 hsotg
->params
.dma_desc_enable
= false;
2361 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
2362 hcfg
|= HCFG_DESCDMA
;
2363 dwc2_writel(hcfg
, hsotg
->regs
+ HCFG
);
2367 /* Configure data FIFO sizes */
2368 dwc2_config_fifos(hsotg
);
2370 /* TODO - check this */
2371 /* Clear Host Set HNP Enable in the OTG Control Register */
2372 otgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
2373 otgctl
&= ~GOTGCTL_HSTSETHNPEN
;
2374 dwc2_writel(otgctl
, hsotg
->regs
+ GOTGCTL
);
2376 /* Make sure the FIFOs are flushed */
2377 dwc2_flush_tx_fifo(hsotg
, 0x10 /* all TX FIFOs */);
2378 dwc2_flush_rx_fifo(hsotg
);
2380 /* Clear Host Set HNP Enable in the OTG Control Register */
2381 otgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
2382 otgctl
&= ~GOTGCTL_HSTSETHNPEN
;
2383 dwc2_writel(otgctl
, hsotg
->regs
+ GOTGCTL
);
2385 if (!hsotg
->params
.dma_desc_enable
) {
2386 int num_channels
, i
;
2389 /* Flush out any leftover queued requests */
2390 num_channels
= hsotg
->params
.host_channels
;
2391 for (i
= 0; i
< num_channels
; i
++) {
2392 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
2393 hcchar
&= ~HCCHAR_CHENA
;
2394 hcchar
|= HCCHAR_CHDIS
;
2395 hcchar
&= ~HCCHAR_EPDIR
;
2396 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
2399 /* Halt all channels to put them into a known state */
2400 for (i
= 0; i
< num_channels
; i
++) {
2403 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
2404 hcchar
|= HCCHAR_CHENA
| HCCHAR_CHDIS
;
2405 hcchar
&= ~HCCHAR_EPDIR
;
2406 dwc2_writel(hcchar
, hsotg
->regs
+ HCCHAR(i
));
2407 dev_dbg(hsotg
->dev
, "%s: Halt channel %d\n",
2410 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
2411 if (++count
> 1000) {
2413 "Unable to clear enable on channel %d\n",
2418 } while (hcchar
& HCCHAR_CHENA
);
2422 /* Turn on the vbus power */
2423 dev_dbg(hsotg
->dev
, "Init: Port Power? op_state=%d\n", hsotg
->op_state
);
2424 if (hsotg
->op_state
== OTG_STATE_A_HOST
) {
2425 u32 hprt0
= dwc2_read_hprt0(hsotg
);
2427 dev_dbg(hsotg
->dev
, "Init: Power Port (%d)\n",
2428 !!(hprt0
& HPRT0_PWR
));
2429 if (!(hprt0
& HPRT0_PWR
)) {
2431 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
2435 dwc2_enable_host_interrupts(hsotg
);
2439 * Initializes dynamic portions of the DWC_otg HCD state
2441 * Must be called with interrupt disabled and spinlock held
2443 static void dwc2_hcd_reinit(struct dwc2_hsotg
*hsotg
)
2445 struct dwc2_host_chan
*chan
, *chan_tmp
;
2449 hsotg
->flags
.d32
= 0;
2450 hsotg
->non_periodic_qh_ptr
= &hsotg
->non_periodic_sched_active
;
2452 if (hsotg
->params
.uframe_sched
) {
2453 hsotg
->available_host_channels
=
2454 hsotg
->params
.host_channels
;
2456 hsotg
->non_periodic_channels
= 0;
2457 hsotg
->periodic_channels
= 0;
2461 * Put all channels in the free channel list and clean up channel
2464 list_for_each_entry_safe(chan
, chan_tmp
, &hsotg
->free_hc_list
,
2466 list_del_init(&chan
->hc_list_entry
);
2468 num_channels
= hsotg
->params
.host_channels
;
2469 for (i
= 0; i
< num_channels
; i
++) {
2470 chan
= hsotg
->hc_ptr_array
[i
];
2471 list_add_tail(&chan
->hc_list_entry
, &hsotg
->free_hc_list
);
2472 dwc2_hc_cleanup(hsotg
, chan
);
2475 /* Initialize the DWC core for host mode operation */
2476 dwc2_core_host_init(hsotg
);
2479 static void dwc2_hc_init_split(struct dwc2_hsotg
*hsotg
,
2480 struct dwc2_host_chan
*chan
,
2481 struct dwc2_qtd
*qtd
, struct dwc2_hcd_urb
*urb
)
2483 int hub_addr
, hub_port
;
2486 chan
->xact_pos
= qtd
->isoc_split_pos
;
2487 chan
->complete_split
= qtd
->complete_split
;
2488 dwc2_host_hub_info(hsotg
, urb
->priv
, &hub_addr
, &hub_port
);
2489 chan
->hub_addr
= (u8
)hub_addr
;
2490 chan
->hub_port
= (u8
)hub_port
;
2493 static void dwc2_hc_init_xfer(struct dwc2_hsotg
*hsotg
,
2494 struct dwc2_host_chan
*chan
,
2495 struct dwc2_qtd
*qtd
)
2497 struct dwc2_hcd_urb
*urb
= qtd
->urb
;
2498 struct dwc2_hcd_iso_packet_desc
*frame_desc
;
2500 switch (dwc2_hcd_get_pipe_type(&urb
->pipe_info
)) {
2501 case USB_ENDPOINT_XFER_CONTROL
:
2502 chan
->ep_type
= USB_ENDPOINT_XFER_CONTROL
;
2504 switch (qtd
->control_phase
) {
2505 case DWC2_CONTROL_SETUP
:
2506 dev_vdbg(hsotg
->dev
, " Control setup transaction\n");
2509 chan
->data_pid_start
= DWC2_HC_PID_SETUP
;
2510 if (hsotg
->params
.host_dma
)
2511 chan
->xfer_dma
= urb
->setup_dma
;
2513 chan
->xfer_buf
= urb
->setup_packet
;
2517 case DWC2_CONTROL_DATA
:
2518 dev_vdbg(hsotg
->dev
, " Control data transaction\n");
2519 chan
->data_pid_start
= qtd
->data_toggle
;
2522 case DWC2_CONTROL_STATUS
:
2524 * Direction is opposite of data direction or IN if no
2527 dev_vdbg(hsotg
->dev
, " Control status transaction\n");
2528 if (urb
->length
== 0)
2532 dwc2_hcd_is_pipe_out(&urb
->pipe_info
);
2535 chan
->data_pid_start
= DWC2_HC_PID_DATA1
;
2537 if (hsotg
->params
.host_dma
)
2538 chan
->xfer_dma
= hsotg
->status_buf_dma
;
2540 chan
->xfer_buf
= hsotg
->status_buf
;
2545 case USB_ENDPOINT_XFER_BULK
:
2546 chan
->ep_type
= USB_ENDPOINT_XFER_BULK
;
2549 case USB_ENDPOINT_XFER_INT
:
2550 chan
->ep_type
= USB_ENDPOINT_XFER_INT
;
2553 case USB_ENDPOINT_XFER_ISOC
:
2554 chan
->ep_type
= USB_ENDPOINT_XFER_ISOC
;
2555 if (hsotg
->params
.dma_desc_enable
)
2558 frame_desc
= &urb
->iso_descs
[qtd
->isoc_frame_index
];
2559 frame_desc
->status
= 0;
2561 if (hsotg
->params
.host_dma
) {
2562 chan
->xfer_dma
= urb
->dma
;
2563 chan
->xfer_dma
+= frame_desc
->offset
+
2564 qtd
->isoc_split_offset
;
2566 chan
->xfer_buf
= urb
->buf
;
2567 chan
->xfer_buf
+= frame_desc
->offset
+
2568 qtd
->isoc_split_offset
;
2571 chan
->xfer_len
= frame_desc
->length
- qtd
->isoc_split_offset
;
2573 if (chan
->xact_pos
== DWC2_HCSPLT_XACTPOS_ALL
) {
2574 if (chan
->xfer_len
<= 188)
2575 chan
->xact_pos
= DWC2_HCSPLT_XACTPOS_ALL
;
2577 chan
->xact_pos
= DWC2_HCSPLT_XACTPOS_BEGIN
;
2583 #define DWC2_USB_DMA_ALIGN 4
2585 struct dma_aligned_buffer
{
2587 void *old_xfer_buffer
;
2591 static void dwc2_free_dma_aligned_buffer(struct urb
*urb
)
2593 struct dma_aligned_buffer
*temp
;
2595 if (!(urb
->transfer_flags
& URB_ALIGNED_TEMP_BUFFER
))
2598 temp
= container_of(urb
->transfer_buffer
,
2599 struct dma_aligned_buffer
, data
);
2601 if (usb_urb_dir_in(urb
))
2602 memcpy(temp
->old_xfer_buffer
, temp
->data
,
2603 urb
->transfer_buffer_length
);
2604 urb
->transfer_buffer
= temp
->old_xfer_buffer
;
2605 kfree(temp
->kmalloc_ptr
);
2607 urb
->transfer_flags
&= ~URB_ALIGNED_TEMP_BUFFER
;
2610 static int dwc2_alloc_dma_aligned_buffer(struct urb
*urb
, gfp_t mem_flags
)
2612 struct dma_aligned_buffer
*temp
, *kmalloc_ptr
;
2613 size_t kmalloc_size
;
2615 if (urb
->num_sgs
|| urb
->sg
||
2616 urb
->transfer_buffer_length
== 0 ||
2617 !((uintptr_t)urb
->transfer_buffer
& (DWC2_USB_DMA_ALIGN
- 1)))
2620 /* Allocate a buffer with enough padding for alignment */
2621 kmalloc_size
= urb
->transfer_buffer_length
+
2622 sizeof(struct dma_aligned_buffer
) + DWC2_USB_DMA_ALIGN
- 1;
2624 kmalloc_ptr
= kmalloc(kmalloc_size
, mem_flags
);
2628 /* Position our struct dma_aligned_buffer such that data is aligned */
2629 temp
= PTR_ALIGN(kmalloc_ptr
+ 1, DWC2_USB_DMA_ALIGN
) - 1;
2630 temp
->kmalloc_ptr
= kmalloc_ptr
;
2631 temp
->old_xfer_buffer
= urb
->transfer_buffer
;
2632 if (usb_urb_dir_out(urb
))
2633 memcpy(temp
->data
, urb
->transfer_buffer
,
2634 urb
->transfer_buffer_length
);
2635 urb
->transfer_buffer
= temp
->data
;
2637 urb
->transfer_flags
|= URB_ALIGNED_TEMP_BUFFER
;
2642 static int dwc2_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
2647 /* We assume setup_dma is always aligned; warn if not */
2648 WARN_ON_ONCE(urb
->setup_dma
&&
2649 (urb
->setup_dma
& (DWC2_USB_DMA_ALIGN
- 1)));
2651 ret
= dwc2_alloc_dma_aligned_buffer(urb
, mem_flags
);
2655 ret
= usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
2657 dwc2_free_dma_aligned_buffer(urb
);
2662 static void dwc2_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
2664 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
2665 dwc2_free_dma_aligned_buffer(urb
);
2669 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2670 * channel and initializes the host channel to perform the transactions. The
2671 * host channel is removed from the free list.
2673 * @hsotg: The HCD state structure
2674 * @qh: Transactions from the first QTD for this QH are selected and assigned
2675 * to a free host channel
2677 static int dwc2_assign_and_init_hc(struct dwc2_hsotg
*hsotg
, struct dwc2_qh
*qh
)
2679 struct dwc2_host_chan
*chan
;
2680 struct dwc2_hcd_urb
*urb
;
2681 struct dwc2_qtd
*qtd
;
2684 dev_vdbg(hsotg
->dev
, "%s(%p,%p)\n", __func__
, hsotg
, qh
);
2686 if (list_empty(&qh
->qtd_list
)) {
2687 dev_dbg(hsotg
->dev
, "No QTDs in QH list\n");
2691 if (list_empty(&hsotg
->free_hc_list
)) {
2692 dev_dbg(hsotg
->dev
, "No free channel to assign\n");
2696 chan
= list_first_entry(&hsotg
->free_hc_list
, struct dwc2_host_chan
,
2699 /* Remove host channel from free list */
2700 list_del_init(&chan
->hc_list_entry
);
2702 qtd
= list_first_entry(&qh
->qtd_list
, struct dwc2_qtd
, qtd_list_entry
);
2705 qtd
->in_process
= 1;
2708 * Use usb_pipedevice to determine device address. This address is
2709 * 0 before the SET_ADDRESS command and the correct address afterward.
2711 chan
->dev_addr
= dwc2_hcd_get_dev_addr(&urb
->pipe_info
);
2712 chan
->ep_num
= dwc2_hcd_get_ep_num(&urb
->pipe_info
);
2713 chan
->speed
= qh
->dev_speed
;
2714 chan
->max_packet
= dwc2_max_packet(qh
->maxp
);
2716 chan
->xfer_started
= 0;
2717 chan
->halt_status
= DWC2_HC_XFER_NO_HALT_STATUS
;
2718 chan
->error_state
= (qtd
->error_count
> 0);
2719 chan
->halt_on_queue
= 0;
2720 chan
->halt_pending
= 0;
2724 * The following values may be modified in the transfer type section
2725 * below. The xfer_len value may be reduced when the transfer is
2726 * started to accommodate the max widths of the XferSize and PktCnt
2727 * fields in the HCTSIZn register.
2730 chan
->ep_is_in
= (dwc2_hcd_is_pipe_in(&urb
->pipe_info
) != 0);
2734 chan
->do_ping
= qh
->ping_state
;
2736 chan
->data_pid_start
= qh
->data_toggle
;
2737 chan
->multi_count
= 1;
2739 if (urb
->actual_length
> urb
->length
&&
2740 !dwc2_hcd_is_pipe_in(&urb
->pipe_info
))
2741 urb
->actual_length
= urb
->length
;
2743 if (hsotg
->params
.host_dma
)
2744 chan
->xfer_dma
= urb
->dma
+ urb
->actual_length
;
2746 chan
->xfer_buf
= (u8
*)urb
->buf
+ urb
->actual_length
;
2748 chan
->xfer_len
= urb
->length
- urb
->actual_length
;
2749 chan
->xfer_count
= 0;
2751 /* Set the split attributes if required */
2753 dwc2_hc_init_split(hsotg
, chan
, qtd
, urb
);
2757 /* Set the transfer attributes */
2758 dwc2_hc_init_xfer(hsotg
, chan
, qtd
);
2760 if (chan
->ep_type
== USB_ENDPOINT_XFER_INT
||
2761 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
)
2763 * This value may be modified when the transfer is started
2764 * to reflect the actual transfer length
2766 chan
->multi_count
= dwc2_hb_mult(qh
->maxp
);
2768 if (hsotg
->params
.dma_desc_enable
) {
2769 chan
->desc_list_addr
= qh
->desc_list_dma
;
2770 chan
->desc_list_sz
= qh
->desc_list_sz
;
2773 dwc2_hc_init(hsotg
, chan
);
2780 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2781 * schedule and assigns them to available host channels. Called from the HCD
2782 * interrupt handler functions.
2784 * @hsotg: The HCD state structure
2786 * Return: The types of new transactions that were assigned to host channels
2788 enum dwc2_transaction_type
dwc2_hcd_select_transactions(
2789 struct dwc2_hsotg
*hsotg
)
2791 enum dwc2_transaction_type ret_val
= DWC2_TRANSACTION_NONE
;
2792 struct list_head
*qh_ptr
;
2796 #ifdef DWC2_DEBUG_SOF
2797 dev_vdbg(hsotg
->dev
, " Select Transactions\n");
2800 /* Process entries in the periodic ready list */
2801 qh_ptr
= hsotg
->periodic_sched_ready
.next
;
2802 while (qh_ptr
!= &hsotg
->periodic_sched_ready
) {
2803 if (list_empty(&hsotg
->free_hc_list
))
2805 if (hsotg
->params
.uframe_sched
) {
2806 if (hsotg
->available_host_channels
<= 1)
2808 hsotg
->available_host_channels
--;
2810 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
2811 if (dwc2_assign_and_init_hc(hsotg
, qh
))
2815 * Move the QH from the periodic ready schedule to the
2816 * periodic assigned schedule
2818 qh_ptr
= qh_ptr
->next
;
2819 list_move_tail(&qh
->qh_list_entry
,
2820 &hsotg
->periodic_sched_assigned
);
2821 ret_val
= DWC2_TRANSACTION_PERIODIC
;
2825 * Process entries in the inactive portion of the non-periodic
2826 * schedule. Some free host channels may not be used if they are
2827 * reserved for periodic transfers.
2829 num_channels
= hsotg
->params
.host_channels
;
2830 qh_ptr
= hsotg
->non_periodic_sched_inactive
.next
;
2831 while (qh_ptr
!= &hsotg
->non_periodic_sched_inactive
) {
2832 if (!hsotg
->params
.uframe_sched
&&
2833 hsotg
->non_periodic_channels
>= num_channels
-
2834 hsotg
->periodic_channels
)
2836 if (list_empty(&hsotg
->free_hc_list
))
2838 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
2839 if (hsotg
->params
.uframe_sched
) {
2840 if (hsotg
->available_host_channels
< 1)
2842 hsotg
->available_host_channels
--;
2845 if (dwc2_assign_and_init_hc(hsotg
, qh
))
2849 * Move the QH from the non-periodic inactive schedule to the
2850 * non-periodic active schedule
2852 qh_ptr
= qh_ptr
->next
;
2853 list_move_tail(&qh
->qh_list_entry
,
2854 &hsotg
->non_periodic_sched_active
);
2856 if (ret_val
== DWC2_TRANSACTION_NONE
)
2857 ret_val
= DWC2_TRANSACTION_NON_PERIODIC
;
2859 ret_val
= DWC2_TRANSACTION_ALL
;
2861 if (!hsotg
->params
.uframe_sched
)
2862 hsotg
->non_periodic_channels
++;
2869 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2870 * a host channel associated with either a periodic or non-periodic transfer
2872 * @hsotg: The HCD state structure
2873 * @chan: Host channel descriptor associated with either a periodic or
2874 * non-periodic transfer
2875 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2876 * for periodic transfers or the non-periodic Tx FIFO
2877 * for non-periodic transfers
2879 * Return: 1 if a request is queued and more requests may be needed to
2880 * complete the transfer, 0 if no more requests are required for this
2881 * transfer, -1 if there is insufficient space in the Tx FIFO
2883 * This function assumes that there is space available in the appropriate
2884 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2885 * it checks whether space is available in the appropriate Tx FIFO.
2887 * Must be called with interrupt disabled and spinlock held
2889 static int dwc2_queue_transaction(struct dwc2_hsotg
*hsotg
,
2890 struct dwc2_host_chan
*chan
,
2891 u16 fifo_dwords_avail
)
2896 /* Put ourselves on the list to keep order straight */
2897 list_move_tail(&chan
->split_order_list_entry
,
2898 &hsotg
->split_order
);
2900 if (hsotg
->params
.host_dma
) {
2901 if (hsotg
->params
.dma_desc_enable
) {
2902 if (!chan
->xfer_started
||
2903 chan
->ep_type
== USB_ENDPOINT_XFER_ISOC
) {
2904 dwc2_hcd_start_xfer_ddma(hsotg
, chan
->qh
);
2905 chan
->qh
->ping_state
= 0;
2907 } else if (!chan
->xfer_started
) {
2908 dwc2_hc_start_transfer(hsotg
, chan
);
2909 chan
->qh
->ping_state
= 0;
2911 } else if (chan
->halt_pending
) {
2912 /* Don't queue a request if the channel has been halted */
2913 } else if (chan
->halt_on_queue
) {
2914 dwc2_hc_halt(hsotg
, chan
, chan
->halt_status
);
2915 } else if (chan
->do_ping
) {
2916 if (!chan
->xfer_started
)
2917 dwc2_hc_start_transfer(hsotg
, chan
);
2918 } else if (!chan
->ep_is_in
||
2919 chan
->data_pid_start
== DWC2_HC_PID_SETUP
) {
2920 if ((fifo_dwords_avail
* 4) >= chan
->max_packet
) {
2921 if (!chan
->xfer_started
) {
2922 dwc2_hc_start_transfer(hsotg
, chan
);
2925 retval
= dwc2_hc_continue_transfer(hsotg
, chan
);
2931 if (!chan
->xfer_started
) {
2932 dwc2_hc_start_transfer(hsotg
, chan
);
2935 retval
= dwc2_hc_continue_transfer(hsotg
, chan
);
2943 * Processes periodic channels for the next frame and queues transactions for
2944 * these channels to the DWC_otg controller. After queueing transactions, the
2945 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2946 * to queue as Periodic Tx FIFO or request queue space becomes available.
2947 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2949 * Must be called with interrupt disabled and spinlock held
2951 static void dwc2_process_periodic_channels(struct dwc2_hsotg
*hsotg
)
2953 struct list_head
*qh_ptr
;
2959 bool no_queue_space
= false;
2960 bool no_fifo_space
= false;
2963 /* If empty list then just adjust interrupt enables */
2964 if (list_empty(&hsotg
->periodic_sched_assigned
))
2968 dev_vdbg(hsotg
->dev
, "Queue periodic transactions\n");
2970 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
2971 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
2972 TXSTS_QSPCAVAIL_SHIFT
;
2973 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
2974 TXSTS_FSPCAVAIL_SHIFT
;
2977 dev_vdbg(hsotg
->dev
, " P Tx Req Queue Space Avail (before queue): %d\n",
2979 dev_vdbg(hsotg
->dev
, " P Tx FIFO Space Avail (before queue): %d\n",
2983 qh_ptr
= hsotg
->periodic_sched_assigned
.next
;
2984 while (qh_ptr
!= &hsotg
->periodic_sched_assigned
) {
2985 tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
2986 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
2987 TXSTS_QSPCAVAIL_SHIFT
;
2988 if (qspcavail
== 0) {
2989 no_queue_space
= true;
2993 qh
= list_entry(qh_ptr
, struct dwc2_qh
, qh_list_entry
);
2995 qh_ptr
= qh_ptr
->next
;
2999 /* Make sure EP's TT buffer is clean before queueing qtds */
3000 if (qh
->tt_buffer_dirty
) {
3001 qh_ptr
= qh_ptr
->next
;
3006 * Set a flag if we're queuing high-bandwidth in slave mode.
3007 * The flag prevents any halts to get into the request queue in
3008 * the middle of multiple high-bandwidth packets getting queued.
3010 if (!hsotg
->params
.host_dma
&&
3011 qh
->channel
->multi_count
> 1)
3012 hsotg
->queuing_high_bandwidth
= 1;
3014 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
3015 TXSTS_FSPCAVAIL_SHIFT
;
3016 status
= dwc2_queue_transaction(hsotg
, qh
->channel
, fspcavail
);
3018 no_fifo_space
= true;
3023 * In Slave mode, stay on the current transfer until there is
3024 * nothing more to do or the high-bandwidth request count is
3025 * reached. In DMA mode, only need to queue one request. The
3026 * controller automatically handles multiple packets for
3027 * high-bandwidth transfers.
3029 if (hsotg
->params
.host_dma
|| status
== 0 ||
3030 qh
->channel
->requests
== qh
->channel
->multi_count
) {
3031 qh_ptr
= qh_ptr
->next
;
3033 * Move the QH from the periodic assigned schedule to
3034 * the periodic queued schedule
3036 list_move_tail(&qh
->qh_list_entry
,
3037 &hsotg
->periodic_sched_queued
);
3039 /* done queuing high bandwidth */
3040 hsotg
->queuing_high_bandwidth
= 0;
3045 if (no_queue_space
|| no_fifo_space
||
3046 (!hsotg
->params
.host_dma
&&
3047 !list_empty(&hsotg
->periodic_sched_assigned
))) {
3049 * May need to queue more transactions as the request
3050 * queue or Tx FIFO empties. Enable the periodic Tx
3051 * FIFO empty interrupt. (Always use the half-empty
3052 * level to ensure that new requests are loaded as
3053 * soon as possible.)
3055 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3056 if (!(gintmsk
& GINTSTS_PTXFEMP
)) {
3057 gintmsk
|= GINTSTS_PTXFEMP
;
3058 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3062 * Disable the Tx FIFO empty interrupt since there are
3063 * no more transactions that need to be queued right
3064 * now. This function is called from interrupt
3065 * handlers to queue more transactions as transfer
3068 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3069 if (gintmsk
& GINTSTS_PTXFEMP
) {
3070 gintmsk
&= ~GINTSTS_PTXFEMP
;
3071 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3077 * Processes active non-periodic channels and queues transactions for these
3078 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3079 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3080 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3081 * FIFO Empty interrupt is disabled.
3083 * Must be called with interrupt disabled and spinlock held
3085 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg
*hsotg
)
3087 struct list_head
*orig_qh_ptr
;
3094 int no_queue_space
= 0;
3095 int no_fifo_space
= 0;
3098 dev_vdbg(hsotg
->dev
, "Queue non-periodic transactions\n");
3100 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
3101 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
3102 TXSTS_QSPCAVAIL_SHIFT
;
3103 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
3104 TXSTS_FSPCAVAIL_SHIFT
;
3105 dev_vdbg(hsotg
->dev
, " NP Tx Req Queue Space Avail (before queue): %d\n",
3107 dev_vdbg(hsotg
->dev
, " NP Tx FIFO Space Avail (before queue): %d\n",
3111 * Keep track of the starting point. Skip over the start-of-list
3114 if (hsotg
->non_periodic_qh_ptr
== &hsotg
->non_periodic_sched_active
)
3115 hsotg
->non_periodic_qh_ptr
= hsotg
->non_periodic_qh_ptr
->next
;
3116 orig_qh_ptr
= hsotg
->non_periodic_qh_ptr
;
3119 * Process once through the active list or until no more space is
3120 * available in the request queue or the Tx FIFO
3123 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
3124 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
3125 TXSTS_QSPCAVAIL_SHIFT
;
3126 if (!hsotg
->params
.host_dma
&& qspcavail
== 0) {
3131 qh
= list_entry(hsotg
->non_periodic_qh_ptr
, struct dwc2_qh
,
3136 /* Make sure EP's TT buffer is clean before queueing qtds */
3137 if (qh
->tt_buffer_dirty
)
3140 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
3141 TXSTS_FSPCAVAIL_SHIFT
;
3142 status
= dwc2_queue_transaction(hsotg
, qh
->channel
, fspcavail
);
3146 } else if (status
< 0) {
3151 /* Advance to next QH, skipping start-of-list entry */
3152 hsotg
->non_periodic_qh_ptr
= hsotg
->non_periodic_qh_ptr
->next
;
3153 if (hsotg
->non_periodic_qh_ptr
==
3154 &hsotg
->non_periodic_sched_active
)
3155 hsotg
->non_periodic_qh_ptr
=
3156 hsotg
->non_periodic_qh_ptr
->next
;
3157 } while (hsotg
->non_periodic_qh_ptr
!= orig_qh_ptr
);
3159 if (!hsotg
->params
.host_dma
) {
3160 tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
3161 qspcavail
= (tx_status
& TXSTS_QSPCAVAIL_MASK
) >>
3162 TXSTS_QSPCAVAIL_SHIFT
;
3163 fspcavail
= (tx_status
& TXSTS_FSPCAVAIL_MASK
) >>
3164 TXSTS_FSPCAVAIL_SHIFT
;
3165 dev_vdbg(hsotg
->dev
,
3166 " NP Tx Req Queue Space Avail (after queue): %d\n",
3168 dev_vdbg(hsotg
->dev
,
3169 " NP Tx FIFO Space Avail (after queue): %d\n",
3172 if (more_to_do
|| no_queue_space
|| no_fifo_space
) {
3174 * May need to queue more transactions as the request
3175 * queue or Tx FIFO empties. Enable the non-periodic
3176 * Tx FIFO empty interrupt. (Always use the half-empty
3177 * level to ensure that new requests are loaded as
3178 * soon as possible.)
3180 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3181 gintmsk
|= GINTSTS_NPTXFEMP
;
3182 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3185 * Disable the Tx FIFO empty interrupt since there are
3186 * no more transactions that need to be queued right
3187 * now. This function is called from interrupt
3188 * handlers to queue more transactions as transfer
3191 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3192 gintmsk
&= ~GINTSTS_NPTXFEMP
;
3193 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3199 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3200 * and queues transactions for these channels to the DWC_otg controller. Called
3201 * from the HCD interrupt handler functions.
3203 * @hsotg: The HCD state structure
3204 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3207 * Must be called with interrupt disabled and spinlock held
3209 void dwc2_hcd_queue_transactions(struct dwc2_hsotg
*hsotg
,
3210 enum dwc2_transaction_type tr_type
)
3212 #ifdef DWC2_DEBUG_SOF
3213 dev_vdbg(hsotg
->dev
, "Queue Transactions\n");
3215 /* Process host channels associated with periodic transfers */
3216 if (tr_type
== DWC2_TRANSACTION_PERIODIC
||
3217 tr_type
== DWC2_TRANSACTION_ALL
)
3218 dwc2_process_periodic_channels(hsotg
);
3220 /* Process host channels associated with non-periodic transfers */
3221 if (tr_type
== DWC2_TRANSACTION_NON_PERIODIC
||
3222 tr_type
== DWC2_TRANSACTION_ALL
) {
3223 if (!list_empty(&hsotg
->non_periodic_sched_active
)) {
3224 dwc2_process_non_periodic_channels(hsotg
);
3227 * Ensure NP Tx FIFO empty interrupt is disabled when
3228 * there are no non-periodic transfers to process
3230 u32 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3232 gintmsk
&= ~GINTSTS_NPTXFEMP
;
3233 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3238 static void dwc2_conn_id_status_change(struct work_struct
*work
)
3240 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
3244 unsigned long flags
;
3246 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
3248 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
3249 dev_dbg(hsotg
->dev
, "gotgctl=%0x\n", gotgctl
);
3250 dev_dbg(hsotg
->dev
, "gotgctl.b.conidsts=%d\n",
3251 !!(gotgctl
& GOTGCTL_CONID_B
));
3253 /* B-Device connector (Device Mode) */
3254 if (gotgctl
& GOTGCTL_CONID_B
) {
3255 /* Wait for switch to device mode */
3256 dev_dbg(hsotg
->dev
, "connId B\n");
3257 if (hsotg
->bus_suspended
) {
3258 dev_info(hsotg
->dev
,
3259 "Do port resume before switching to device mode\n");
3260 dwc2_port_resume(hsotg
);
3262 while (!dwc2_is_device_mode(hsotg
)) {
3263 dev_info(hsotg
->dev
,
3264 "Waiting for Peripheral Mode, Mode=%s\n",
3265 dwc2_is_host_mode(hsotg
) ? "Host" :
3269 * Sometimes the initial GOTGCTRL read is wrong, so
3270 * check it again and jump to host mode if that was
3273 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
3274 if (!(gotgctl
& GOTGCTL_CONID_B
))
3281 "Connection id status change timed out\n");
3282 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
3283 dwc2_core_init(hsotg
, false);
3284 dwc2_enable_global_interrupts(hsotg
);
3285 spin_lock_irqsave(&hsotg
->lock
, flags
);
3286 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3287 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3288 dwc2_hsotg_core_connect(hsotg
);
3291 /* A-Device connector (Host Mode) */
3292 dev_dbg(hsotg
->dev
, "connId A\n");
3293 while (!dwc2_is_host_mode(hsotg
)) {
3294 dev_info(hsotg
->dev
, "Waiting for Host Mode, Mode=%s\n",
3295 dwc2_is_host_mode(hsotg
) ?
3296 "Host" : "Peripheral");
3303 "Connection id status change timed out\n");
3305 spin_lock_irqsave(&hsotg
->lock
, flags
);
3306 dwc2_hsotg_disconnect(hsotg
);
3307 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3309 hsotg
->op_state
= OTG_STATE_A_HOST
;
3310 /* Initialize the Core for Host mode */
3311 dwc2_core_init(hsotg
, false);
3312 dwc2_enable_global_interrupts(hsotg
);
3313 dwc2_hcd_start(hsotg
);
3317 static void dwc2_wakeup_detected(unsigned long data
)
3319 struct dwc2_hsotg
*hsotg
= (struct dwc2_hsotg
*)data
;
3322 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
3325 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3326 * so that OPT tests pass with all PHYs.)
3328 hprt0
= dwc2_read_hprt0(hsotg
);
3329 dev_dbg(hsotg
->dev
, "Resume: HPRT0=%0x\n", hprt0
);
3330 hprt0
&= ~HPRT0_RES
;
3331 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3332 dev_dbg(hsotg
->dev
, "Clear Resume: HPRT0=%0x\n",
3333 dwc2_readl(hsotg
->regs
+ HPRT0
));
3335 dwc2_hcd_rem_wakeup(hsotg
);
3336 hsotg
->bus_suspended
= false;
3338 /* Change to L0 state */
3339 hsotg
->lx_state
= DWC2_L0
;
3342 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg
*hsotg
)
3344 struct usb_hcd
*hcd
= dwc2_hsotg_to_hcd(hsotg
);
3346 return hcd
->self
.b_hnp_enable
;
3349 /* Must NOT be called with interrupt disabled or spinlock held */
3350 static void dwc2_port_suspend(struct dwc2_hsotg
*hsotg
, u16 windex
)
3352 unsigned long flags
;
3357 dev_dbg(hsotg
->dev
, "%s()\n", __func__
);
3359 spin_lock_irqsave(&hsotg
->lock
, flags
);
3361 if (windex
== hsotg
->otg_port
&& dwc2_host_is_b_hnp_enabled(hsotg
)) {
3362 gotgctl
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
3363 gotgctl
|= GOTGCTL_HSTSETHNPEN
;
3364 dwc2_writel(gotgctl
, hsotg
->regs
+ GOTGCTL
);
3365 hsotg
->op_state
= OTG_STATE_A_SUSPEND
;
3368 hprt0
= dwc2_read_hprt0(hsotg
);
3369 hprt0
|= HPRT0_SUSP
;
3370 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3372 hsotg
->bus_suspended
= true;
3375 * If hibernation is supported, Phy clock will be suspended
3376 * after registers are backuped.
3378 if (!hsotg
->params
.hibernation
) {
3379 /* Suspend the Phy Clock */
3380 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
3381 pcgctl
|= PCGCTL_STOPPCLK
;
3382 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
3386 /* For HNP the bus must be suspended for at least 200ms */
3387 if (dwc2_host_is_b_hnp_enabled(hsotg
)) {
3388 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
3389 pcgctl
&= ~PCGCTL_STOPPCLK
;
3390 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
3392 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3396 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3400 /* Must NOT be called with interrupt disabled or spinlock held */
3401 static void dwc2_port_resume(struct dwc2_hsotg
*hsotg
)
3403 unsigned long flags
;
3407 spin_lock_irqsave(&hsotg
->lock
, flags
);
3410 * If hibernation is supported, Phy clock is already resumed
3411 * after registers restore.
3413 if (!hsotg
->params
.hibernation
) {
3414 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
3415 pcgctl
&= ~PCGCTL_STOPPCLK
;
3416 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
3417 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3419 spin_lock_irqsave(&hsotg
->lock
, flags
);
3422 hprt0
= dwc2_read_hprt0(hsotg
);
3424 hprt0
&= ~HPRT0_SUSP
;
3425 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3426 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3428 msleep(USB_RESUME_TIMEOUT
);
3430 spin_lock_irqsave(&hsotg
->lock
, flags
);
3431 hprt0
= dwc2_read_hprt0(hsotg
);
3432 hprt0
&= ~(HPRT0_RES
| HPRT0_SUSP
);
3433 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3434 hsotg
->bus_suspended
= false;
3435 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3438 /* Handles hub class-specific requests */
3439 static int dwc2_hcd_hub_control(struct dwc2_hsotg
*hsotg
, u16 typereq
,
3440 u16 wvalue
, u16 windex
, char *buf
, u16 wlength
)
3442 struct usb_hub_descriptor
*hub_desc
;
3450 case ClearHubFeature
:
3451 dev_dbg(hsotg
->dev
, "ClearHubFeature %1xh\n", wvalue
);
3454 case C_HUB_LOCAL_POWER
:
3455 case C_HUB_OVER_CURRENT
:
3456 /* Nothing required here */
3462 "ClearHubFeature request %1xh unknown\n",
3467 case ClearPortFeature
:
3468 if (wvalue
!= USB_PORT_FEAT_L1
)
3469 if (!windex
|| windex
> 1)
3472 case USB_PORT_FEAT_ENABLE
:
3474 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3475 hprt0
= dwc2_read_hprt0(hsotg
);
3477 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3480 case USB_PORT_FEAT_SUSPEND
:
3482 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3484 if (hsotg
->bus_suspended
)
3485 dwc2_port_resume(hsotg
);
3488 case USB_PORT_FEAT_POWER
:
3490 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3491 hprt0
= dwc2_read_hprt0(hsotg
);
3492 hprt0
&= ~HPRT0_PWR
;
3493 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3496 case USB_PORT_FEAT_INDICATOR
:
3498 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3499 /* Port indicator not supported */
3502 case USB_PORT_FEAT_C_CONNECTION
:
3504 * Clears driver's internal Connect Status Change flag
3507 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3508 hsotg
->flags
.b
.port_connect_status_change
= 0;
3511 case USB_PORT_FEAT_C_RESET
:
3512 /* Clears driver's internal Port Reset Change flag */
3514 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3515 hsotg
->flags
.b
.port_reset_change
= 0;
3518 case USB_PORT_FEAT_C_ENABLE
:
3520 * Clears the driver's internal Port Enable/Disable
3524 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3525 hsotg
->flags
.b
.port_enable_change
= 0;
3528 case USB_PORT_FEAT_C_SUSPEND
:
3530 * Clears the driver's internal Port Suspend Change
3531 * flag, which is set when resume signaling on the host
3535 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3536 hsotg
->flags
.b
.port_suspend_change
= 0;
3539 case USB_PORT_FEAT_C_PORT_L1
:
3541 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3542 hsotg
->flags
.b
.port_l1_change
= 0;
3545 case USB_PORT_FEAT_C_OVER_CURRENT
:
3547 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3548 hsotg
->flags
.b
.port_over_current_change
= 0;
3554 "ClearPortFeature request %1xh unknown or unsupported\n",
3559 case GetHubDescriptor
:
3560 dev_dbg(hsotg
->dev
, "GetHubDescriptor\n");
3561 hub_desc
= (struct usb_hub_descriptor
*)buf
;
3562 hub_desc
->bDescLength
= 9;
3563 hub_desc
->bDescriptorType
= USB_DT_HUB
;
3564 hub_desc
->bNbrPorts
= 1;
3565 hub_desc
->wHubCharacteristics
=
3566 cpu_to_le16(HUB_CHAR_COMMON_LPSM
|
3567 HUB_CHAR_INDV_PORT_OCPM
);
3568 hub_desc
->bPwrOn2PwrGood
= 1;
3569 hub_desc
->bHubContrCurrent
= 0;
3570 hub_desc
->u
.hs
.DeviceRemovable
[0] = 0;
3571 hub_desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
3575 dev_dbg(hsotg
->dev
, "GetHubStatus\n");
3580 dev_vdbg(hsotg
->dev
,
3581 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex
,
3583 if (!windex
|| windex
> 1)
3587 if (hsotg
->flags
.b
.port_connect_status_change
)
3588 port_status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
3589 if (hsotg
->flags
.b
.port_enable_change
)
3590 port_status
|= USB_PORT_STAT_C_ENABLE
<< 16;
3591 if (hsotg
->flags
.b
.port_suspend_change
)
3592 port_status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
3593 if (hsotg
->flags
.b
.port_l1_change
)
3594 port_status
|= USB_PORT_STAT_C_L1
<< 16;
3595 if (hsotg
->flags
.b
.port_reset_change
)
3596 port_status
|= USB_PORT_STAT_C_RESET
<< 16;
3597 if (hsotg
->flags
.b
.port_over_current_change
) {
3598 dev_warn(hsotg
->dev
, "Overcurrent change detected\n");
3599 port_status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
3602 if (!hsotg
->flags
.b
.port_connect_status
) {
3604 * The port is disconnected, which means the core is
3605 * either in device mode or it soon will be. Just
3606 * return 0's for the remainder of the port status
3607 * since the port register can't be read if the core
3608 * is in device mode.
3610 *(__le32
*)buf
= cpu_to_le32(port_status
);
3614 hprt0
= dwc2_readl(hsotg
->regs
+ HPRT0
);
3615 dev_vdbg(hsotg
->dev
, " HPRT0: 0x%08x\n", hprt0
);
3617 if (hprt0
& HPRT0_CONNSTS
)
3618 port_status
|= USB_PORT_STAT_CONNECTION
;
3619 if (hprt0
& HPRT0_ENA
)
3620 port_status
|= USB_PORT_STAT_ENABLE
;
3621 if (hprt0
& HPRT0_SUSP
)
3622 port_status
|= USB_PORT_STAT_SUSPEND
;
3623 if (hprt0
& HPRT0_OVRCURRACT
)
3624 port_status
|= USB_PORT_STAT_OVERCURRENT
;
3625 if (hprt0
& HPRT0_RST
)
3626 port_status
|= USB_PORT_STAT_RESET
;
3627 if (hprt0
& HPRT0_PWR
)
3628 port_status
|= USB_PORT_STAT_POWER
;
3630 speed
= (hprt0
& HPRT0_SPD_MASK
) >> HPRT0_SPD_SHIFT
;
3631 if (speed
== HPRT0_SPD_HIGH_SPEED
)
3632 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
3633 else if (speed
== HPRT0_SPD_LOW_SPEED
)
3634 port_status
|= USB_PORT_STAT_LOW_SPEED
;
3636 if (hprt0
& HPRT0_TSTCTL_MASK
)
3637 port_status
|= USB_PORT_STAT_TEST
;
3638 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3640 if (hsotg
->params
.dma_desc_fs_enable
) {
3642 * Enable descriptor DMA only if a full speed
3643 * device is connected.
3645 if (hsotg
->new_connection
&&
3647 (USB_PORT_STAT_CONNECTION
|
3648 USB_PORT_STAT_HIGH_SPEED
|
3649 USB_PORT_STAT_LOW_SPEED
)) ==
3650 USB_PORT_STAT_CONNECTION
)) {
3653 dev_info(hsotg
->dev
, "Enabling descriptor DMA mode\n");
3654 hsotg
->params
.dma_desc_enable
= true;
3655 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
3656 hcfg
|= HCFG_DESCDMA
;
3657 dwc2_writel(hcfg
, hsotg
->regs
+ HCFG
);
3658 hsotg
->new_connection
= false;
3662 dev_vdbg(hsotg
->dev
, "port_status=%08x\n", port_status
);
3663 *(__le32
*)buf
= cpu_to_le32(port_status
);
3667 dev_dbg(hsotg
->dev
, "SetHubFeature\n");
3668 /* No HUB features supported */
3671 case SetPortFeature
:
3672 dev_dbg(hsotg
->dev
, "SetPortFeature\n");
3673 if (wvalue
!= USB_PORT_FEAT_TEST
&& (!windex
|| windex
> 1))
3676 if (!hsotg
->flags
.b
.port_connect_status
) {
3678 * The port is disconnected, which means the core is
3679 * either in device mode or it soon will be. Just
3680 * return without doing anything since the port
3681 * register can't be written if the core is in device
3688 case USB_PORT_FEAT_SUSPEND
:
3690 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3691 if (windex
!= hsotg
->otg_port
)
3693 dwc2_port_suspend(hsotg
, windex
);
3696 case USB_PORT_FEAT_POWER
:
3698 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3699 hprt0
= dwc2_read_hprt0(hsotg
);
3701 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3704 case USB_PORT_FEAT_RESET
:
3705 hprt0
= dwc2_read_hprt0(hsotg
);
3707 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3708 pcgctl
= dwc2_readl(hsotg
->regs
+ PCGCTL
);
3709 pcgctl
&= ~(PCGCTL_ENBL_SLEEP_GATING
| PCGCTL_STOPPCLK
);
3710 dwc2_writel(pcgctl
, hsotg
->regs
+ PCGCTL
);
3711 /* ??? Original driver does this */
3712 dwc2_writel(0, hsotg
->regs
+ PCGCTL
);
3714 hprt0
= dwc2_read_hprt0(hsotg
);
3715 /* Clear suspend bit if resetting from suspend state */
3716 hprt0
&= ~HPRT0_SUSP
;
3719 * When B-Host the Port reset bit is set in the Start
3720 * HCD Callback function, so that the reset is started
3721 * within 1ms of the HNP success interrupt
3723 if (!dwc2_hcd_is_b_host(hsotg
)) {
3724 hprt0
|= HPRT0_PWR
| HPRT0_RST
;
3726 "In host mode, hprt0=%08x\n", hprt0
);
3727 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3730 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3732 hprt0
&= ~HPRT0_RST
;
3733 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3734 hsotg
->lx_state
= DWC2_L0
; /* Now back to On state */
3737 case USB_PORT_FEAT_INDICATOR
:
3739 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3743 case USB_PORT_FEAT_TEST
:
3744 hprt0
= dwc2_read_hprt0(hsotg
);
3746 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3747 hprt0
&= ~HPRT0_TSTCTL_MASK
;
3748 hprt0
|= (windex
>> 8) << HPRT0_TSTCTL_SHIFT
;
3749 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
3755 "SetPortFeature %1xh unknown or unsupported\n",
3765 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3766 typereq
, windex
, wvalue
);
3773 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg
*hsotg
, int port
)
3780 retval
= (hsotg
->flags
.b
.port_connect_status_change
||
3781 hsotg
->flags
.b
.port_reset_change
||
3782 hsotg
->flags
.b
.port_enable_change
||
3783 hsotg
->flags
.b
.port_suspend_change
||
3784 hsotg
->flags
.b
.port_over_current_change
);
3788 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3789 dev_dbg(hsotg
->dev
, " port_connect_status_change: %d\n",
3790 hsotg
->flags
.b
.port_connect_status_change
);
3791 dev_dbg(hsotg
->dev
, " port_reset_change: %d\n",
3792 hsotg
->flags
.b
.port_reset_change
);
3793 dev_dbg(hsotg
->dev
, " port_enable_change: %d\n",
3794 hsotg
->flags
.b
.port_enable_change
);
3795 dev_dbg(hsotg
->dev
, " port_suspend_change: %d\n",
3796 hsotg
->flags
.b
.port_suspend_change
);
3797 dev_dbg(hsotg
->dev
, " port_over_current_change: %d\n",
3798 hsotg
->flags
.b
.port_over_current_change
);
3804 int dwc2_hcd_get_frame_number(struct dwc2_hsotg
*hsotg
)
3806 u32 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
3808 #ifdef DWC2_DEBUG_SOF
3809 dev_vdbg(hsotg
->dev
, "DWC OTG HCD GET FRAME NUMBER %d\n",
3810 (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
);
3812 return (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
;
3815 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg
*hsotg
, int us
)
3817 u32 hprt
= dwc2_readl(hsotg
->regs
+ HPRT0
);
3818 u32 hfir
= dwc2_readl(hsotg
->regs
+ HFIR
);
3819 u32 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
3820 unsigned int us_per_frame
;
3821 unsigned int frame_number
;
3822 unsigned int remaining
;
3823 unsigned int interval
;
3824 unsigned int phy_clks
;
3826 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3827 us_per_frame
= (hprt
& HPRT0_SPD_MASK
) ? 1000 : 125;
3829 /* Extract fields */
3830 frame_number
= (hfnum
& HFNUM_FRNUM_MASK
) >> HFNUM_FRNUM_SHIFT
;
3831 remaining
= (hfnum
& HFNUM_FRREM_MASK
) >> HFNUM_FRREM_SHIFT
;
3832 interval
= (hfir
& HFIR_FRINT_MASK
) >> HFIR_FRINT_SHIFT
;
3835 * Number of phy clocks since the last tick of the frame number after
3838 phy_clks
= (interval
- remaining
) +
3839 DIV_ROUND_UP(interval
* us
, us_per_frame
);
3841 return dwc2_frame_num_inc(frame_number
, phy_clks
/ interval
);
3844 int dwc2_hcd_is_b_host(struct dwc2_hsotg
*hsotg
)
3846 return hsotg
->op_state
== OTG_STATE_B_HOST
;
3849 static struct dwc2_hcd_urb
*dwc2_hcd_urb_alloc(struct dwc2_hsotg
*hsotg
,
3853 struct dwc2_hcd_urb
*urb
;
3854 u32 size
= sizeof(*urb
) + iso_desc_count
*
3855 sizeof(struct dwc2_hcd_iso_packet_desc
);
3857 urb
= kzalloc(size
, mem_flags
);
3859 urb
->packet_count
= iso_desc_count
;
3863 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg
*hsotg
,
3864 struct dwc2_hcd_urb
*urb
, u8 dev_addr
,
3865 u8 ep_num
, u8 ep_type
, u8 ep_dir
, u16 mps
)
3868 ep_type
== USB_ENDPOINT_XFER_BULK
||
3869 ep_type
== USB_ENDPOINT_XFER_CONTROL
)
3870 dev_vdbg(hsotg
->dev
,
3871 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3872 dev_addr
, ep_num
, ep_dir
, ep_type
, mps
);
3873 urb
->pipe_info
.dev_addr
= dev_addr
;
3874 urb
->pipe_info
.ep_num
= ep_num
;
3875 urb
->pipe_info
.pipe_type
= ep_type
;
3876 urb
->pipe_info
.pipe_dir
= ep_dir
;
3877 urb
->pipe_info
.mps
= mps
;
3881 * NOTE: This function will be removed once the peripheral controller code
3882 * is integrated and the driver is stable
3884 void dwc2_hcd_dump_state(struct dwc2_hsotg
*hsotg
)
3887 struct dwc2_host_chan
*chan
;
3888 struct dwc2_hcd_urb
*urb
;
3889 struct dwc2_qtd
*qtd
;
3895 num_channels
= hsotg
->params
.host_channels
;
3896 dev_dbg(hsotg
->dev
, "\n");
3898 "************************************************************\n");
3899 dev_dbg(hsotg
->dev
, "HCD State:\n");
3900 dev_dbg(hsotg
->dev
, " Num channels: %d\n", num_channels
);
3902 for (i
= 0; i
< num_channels
; i
++) {
3903 chan
= hsotg
->hc_ptr_array
[i
];
3904 dev_dbg(hsotg
->dev
, " Channel %d:\n", i
);
3906 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3907 chan
->dev_addr
, chan
->ep_num
, chan
->ep_is_in
);
3908 dev_dbg(hsotg
->dev
, " speed: %d\n", chan
->speed
);
3909 dev_dbg(hsotg
->dev
, " ep_type: %d\n", chan
->ep_type
);
3910 dev_dbg(hsotg
->dev
, " max_packet: %d\n", chan
->max_packet
);
3911 dev_dbg(hsotg
->dev
, " data_pid_start: %d\n",
3912 chan
->data_pid_start
);
3913 dev_dbg(hsotg
->dev
, " multi_count: %d\n", chan
->multi_count
);
3914 dev_dbg(hsotg
->dev
, " xfer_started: %d\n",
3915 chan
->xfer_started
);
3916 dev_dbg(hsotg
->dev
, " xfer_buf: %p\n", chan
->xfer_buf
);
3917 dev_dbg(hsotg
->dev
, " xfer_dma: %08lx\n",
3918 (unsigned long)chan
->xfer_dma
);
3919 dev_dbg(hsotg
->dev
, " xfer_len: %d\n", chan
->xfer_len
);
3920 dev_dbg(hsotg
->dev
, " xfer_count: %d\n", chan
->xfer_count
);
3921 dev_dbg(hsotg
->dev
, " halt_on_queue: %d\n",
3922 chan
->halt_on_queue
);
3923 dev_dbg(hsotg
->dev
, " halt_pending: %d\n",
3924 chan
->halt_pending
);
3925 dev_dbg(hsotg
->dev
, " halt_status: %d\n", chan
->halt_status
);
3926 dev_dbg(hsotg
->dev
, " do_split: %d\n", chan
->do_split
);
3927 dev_dbg(hsotg
->dev
, " complete_split: %d\n",
3928 chan
->complete_split
);
3929 dev_dbg(hsotg
->dev
, " hub_addr: %d\n", chan
->hub_addr
);
3930 dev_dbg(hsotg
->dev
, " hub_port: %d\n", chan
->hub_port
);
3931 dev_dbg(hsotg
->dev
, " xact_pos: %d\n", chan
->xact_pos
);
3932 dev_dbg(hsotg
->dev
, " requests: %d\n", chan
->requests
);
3933 dev_dbg(hsotg
->dev
, " qh: %p\n", chan
->qh
);
3935 if (chan
->xfer_started
) {
3936 u32 hfnum
, hcchar
, hctsiz
, hcint
, hcintmsk
;
3938 hfnum
= dwc2_readl(hsotg
->regs
+ HFNUM
);
3939 hcchar
= dwc2_readl(hsotg
->regs
+ HCCHAR(i
));
3940 hctsiz
= dwc2_readl(hsotg
->regs
+ HCTSIZ(i
));
3941 hcint
= dwc2_readl(hsotg
->regs
+ HCINT(i
));
3942 hcintmsk
= dwc2_readl(hsotg
->regs
+ HCINTMSK(i
));
3943 dev_dbg(hsotg
->dev
, " hfnum: 0x%08x\n", hfnum
);
3944 dev_dbg(hsotg
->dev
, " hcchar: 0x%08x\n", hcchar
);
3945 dev_dbg(hsotg
->dev
, " hctsiz: 0x%08x\n", hctsiz
);
3946 dev_dbg(hsotg
->dev
, " hcint: 0x%08x\n", hcint
);
3947 dev_dbg(hsotg
->dev
, " hcintmsk: 0x%08x\n", hcintmsk
);
3950 if (!(chan
->xfer_started
&& chan
->qh
))
3953 list_for_each_entry(qtd
, &chan
->qh
->qtd_list
, qtd_list_entry
) {
3954 if (!qtd
->in_process
)
3957 dev_dbg(hsotg
->dev
, " URB Info:\n");
3958 dev_dbg(hsotg
->dev
, " qtd: %p, urb: %p\n",
3962 " Dev: %d, EP: %d %s\n",
3963 dwc2_hcd_get_dev_addr(&urb
->pipe_info
),
3964 dwc2_hcd_get_ep_num(&urb
->pipe_info
),
3965 dwc2_hcd_is_pipe_in(&urb
->pipe_info
) ?
3968 " Max packet size: %d\n",
3969 dwc2_hcd_get_mps(&urb
->pipe_info
));
3971 " transfer_buffer: %p\n",
3974 " transfer_dma: %08lx\n",
3975 (unsigned long)urb
->dma
);
3977 " transfer_buffer_length: %d\n",
3979 dev_dbg(hsotg
->dev
, " actual_length: %d\n",
3980 urb
->actual_length
);
3985 dev_dbg(hsotg
->dev
, " non_periodic_channels: %d\n",
3986 hsotg
->non_periodic_channels
);
3987 dev_dbg(hsotg
->dev
, " periodic_channels: %d\n",
3988 hsotg
->periodic_channels
);
3989 dev_dbg(hsotg
->dev
, " periodic_usecs: %d\n", hsotg
->periodic_usecs
);
3990 np_tx_status
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
3991 dev_dbg(hsotg
->dev
, " NP Tx Req Queue Space Avail: %d\n",
3992 (np_tx_status
& TXSTS_QSPCAVAIL_MASK
) >> TXSTS_QSPCAVAIL_SHIFT
);
3993 dev_dbg(hsotg
->dev
, " NP Tx FIFO Space Avail: %d\n",
3994 (np_tx_status
& TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
);
3995 p_tx_status
= dwc2_readl(hsotg
->regs
+ HPTXSTS
);
3996 dev_dbg(hsotg
->dev
, " P Tx Req Queue Space Avail: %d\n",
3997 (p_tx_status
& TXSTS_QSPCAVAIL_MASK
) >> TXSTS_QSPCAVAIL_SHIFT
);
3998 dev_dbg(hsotg
->dev
, " P Tx FIFO Space Avail: %d\n",
3999 (p_tx_status
& TXSTS_FSPCAVAIL_MASK
) >> TXSTS_FSPCAVAIL_SHIFT
);
4000 dwc2_hcd_dump_frrem(hsotg
);
4001 dwc2_dump_global_registers(hsotg
);
4002 dwc2_dump_host_registers(hsotg
);
4004 "************************************************************\n");
4005 dev_dbg(hsotg
->dev
, "\n");
4010 * NOTE: This function will be removed once the peripheral controller code
4011 * is integrated and the driver is stable
4013 void dwc2_hcd_dump_frrem(struct dwc2_hsotg
*hsotg
)
4015 #ifdef DWC2_DUMP_FRREM
4016 dev_dbg(hsotg
->dev
, "Frame remaining at SOF:\n");
4017 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4018 hsotg
->frrem_samples
, hsotg
->frrem_accum
,
4019 hsotg
->frrem_samples
> 0 ?
4020 hsotg
->frrem_accum
/ hsotg
->frrem_samples
: 0);
4021 dev_dbg(hsotg
->dev
, "\n");
4022 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 7):\n");
4023 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4024 hsotg
->hfnum_7_samples
,
4025 hsotg
->hfnum_7_frrem_accum
,
4026 hsotg
->hfnum_7_samples
> 0 ?
4027 hsotg
->hfnum_7_frrem_accum
/ hsotg
->hfnum_7_samples
: 0);
4028 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 0):\n");
4029 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4030 hsotg
->hfnum_0_samples
,
4031 hsotg
->hfnum_0_frrem_accum
,
4032 hsotg
->hfnum_0_samples
> 0 ?
4033 hsotg
->hfnum_0_frrem_accum
/ hsotg
->hfnum_0_samples
: 0);
4034 dev_dbg(hsotg
->dev
, "Frame remaining at start_transfer (uframe 1-6):\n");
4035 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4036 hsotg
->hfnum_other_samples
,
4037 hsotg
->hfnum_other_frrem_accum
,
4038 hsotg
->hfnum_other_samples
> 0 ?
4039 hsotg
->hfnum_other_frrem_accum
/ hsotg
->hfnum_other_samples
:
4041 dev_dbg(hsotg
->dev
, "\n");
4042 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 7):\n");
4043 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4044 hsotg
->hfnum_7_samples_a
, hsotg
->hfnum_7_frrem_accum_a
,
4045 hsotg
->hfnum_7_samples_a
> 0 ?
4046 hsotg
->hfnum_7_frrem_accum_a
/ hsotg
->hfnum_7_samples_a
: 0);
4047 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 0):\n");
4048 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4049 hsotg
->hfnum_0_samples_a
, hsotg
->hfnum_0_frrem_accum_a
,
4050 hsotg
->hfnum_0_samples_a
> 0 ?
4051 hsotg
->hfnum_0_frrem_accum_a
/ hsotg
->hfnum_0_samples_a
: 0);
4052 dev_dbg(hsotg
->dev
, "Frame remaining at sample point A (uframe 1-6):\n");
4053 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4054 hsotg
->hfnum_other_samples_a
, hsotg
->hfnum_other_frrem_accum_a
,
4055 hsotg
->hfnum_other_samples_a
> 0 ?
4056 hsotg
->hfnum_other_frrem_accum_a
/ hsotg
->hfnum_other_samples_a
4058 dev_dbg(hsotg
->dev
, "\n");
4059 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 7):\n");
4060 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4061 hsotg
->hfnum_7_samples_b
, hsotg
->hfnum_7_frrem_accum_b
,
4062 hsotg
->hfnum_7_samples_b
> 0 ?
4063 hsotg
->hfnum_7_frrem_accum_b
/ hsotg
->hfnum_7_samples_b
: 0);
4064 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 0):\n");
4065 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4066 hsotg
->hfnum_0_samples_b
, hsotg
->hfnum_0_frrem_accum_b
,
4067 (hsotg
->hfnum_0_samples_b
> 0) ?
4068 hsotg
->hfnum_0_frrem_accum_b
/ hsotg
->hfnum_0_samples_b
: 0);
4069 dev_dbg(hsotg
->dev
, "Frame remaining at sample point B (uframe 1-6):\n");
4070 dev_dbg(hsotg
->dev
, " samples %u, accum %llu, avg %llu\n",
4071 hsotg
->hfnum_other_samples_b
, hsotg
->hfnum_other_frrem_accum_b
,
4072 (hsotg
->hfnum_other_samples_b
> 0) ?
4073 hsotg
->hfnum_other_frrem_accum_b
/ hsotg
->hfnum_other_samples_b
4078 struct wrapper_priv_data
{
4079 struct dwc2_hsotg
*hsotg
;
4082 /* Gets the dwc2_hsotg from a usb_hcd */
4083 static struct dwc2_hsotg
*dwc2_hcd_to_hsotg(struct usb_hcd
*hcd
)
4085 struct wrapper_priv_data
*p
;
4087 p
= (struct wrapper_priv_data
*)&hcd
->hcd_priv
;
4092 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4094 * This will get the dwc2_tt structure (and ttport) associated with the given
4095 * context (which is really just a struct urb pointer).
4097 * The first time this is called for a given TT we allocate memory for our
4098 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4099 * then the refcount for the structure will go to 0 and we'll free it.
4101 * @hsotg: The HCD state structure for the DWC OTG controller.
4102 * @qh: The QH structure.
4103 * @context: The priv pointer from a struct dwc2_hcd_urb.
4104 * @mem_flags: Flags for allocating memory.
4105 * @ttport: We'll return this device's port number here. That's used to
4106 * reference into the bitmap if we're on a multi_tt hub.
4108 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4109 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4112 struct dwc2_tt
*dwc2_host_get_tt_info(struct dwc2_hsotg
*hsotg
, void *context
,
4113 gfp_t mem_flags
, int *ttport
)
4115 struct urb
*urb
= context
;
4116 struct dwc2_tt
*dwc_tt
= NULL
;
4119 *ttport
= urb
->dev
->ttport
;
4121 dwc_tt
= urb
->dev
->tt
->hcpriv
;
4126 * For single_tt we need one schedule. For multi_tt
4127 * we need one per port.
4129 bitmap_size
= DWC2_ELEMENTS_PER_LS_BITMAP
*
4130 sizeof(dwc_tt
->periodic_bitmaps
[0]);
4131 if (urb
->dev
->tt
->multi
)
4132 bitmap_size
*= urb
->dev
->tt
->hub
->maxchild
;
4134 dwc_tt
= kzalloc(sizeof(*dwc_tt
) + bitmap_size
,
4139 dwc_tt
->usb_tt
= urb
->dev
->tt
;
4140 dwc_tt
->usb_tt
->hcpriv
= dwc_tt
;
4150 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4152 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4153 * of the structure are done.
4155 * It's OK to call this with NULL.
4157 * @hsotg: The HCD state structure for the DWC OTG controller.
4158 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4160 void dwc2_host_put_tt_info(struct dwc2_hsotg
*hsotg
, struct dwc2_tt
*dwc_tt
)
4162 /* Model kfree and make put of NULL a no-op */
4166 WARN_ON(dwc_tt
->refcount
< 1);
4169 if (!dwc_tt
->refcount
) {
4170 dwc_tt
->usb_tt
->hcpriv
= NULL
;
4175 int dwc2_host_get_speed(struct dwc2_hsotg
*hsotg
, void *context
)
4177 struct urb
*urb
= context
;
4179 return urb
->dev
->speed
;
4182 static void dwc2_allocate_bus_bandwidth(struct usb_hcd
*hcd
, u16 bw
,
4185 struct usb_bus
*bus
= hcd_to_bus(hcd
);
4188 bus
->bandwidth_allocated
+= bw
/ urb
->interval
;
4189 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
4190 bus
->bandwidth_isoc_reqs
++;
4192 bus
->bandwidth_int_reqs
++;
4195 static void dwc2_free_bus_bandwidth(struct usb_hcd
*hcd
, u16 bw
,
4198 struct usb_bus
*bus
= hcd_to_bus(hcd
);
4201 bus
->bandwidth_allocated
-= bw
/ urb
->interval
;
4202 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
4203 bus
->bandwidth_isoc_reqs
--;
4205 bus
->bandwidth_int_reqs
--;
4209 * Sets the final status of an URB and returns it to the upper layer. Any
4210 * required cleanup of the URB is performed.
4212 * Must be called with interrupt disabled and spinlock held
4214 void dwc2_host_complete(struct dwc2_hsotg
*hsotg
, struct dwc2_qtd
*qtd
,
4221 dev_dbg(hsotg
->dev
, "## %s: qtd is NULL ##\n", __func__
);
4226 dev_dbg(hsotg
->dev
, "## %s: qtd->urb is NULL ##\n", __func__
);
4230 urb
= qtd
->urb
->priv
;
4232 dev_dbg(hsotg
->dev
, "## %s: urb->priv is NULL ##\n", __func__
);
4236 urb
->actual_length
= dwc2_hcd_urb_get_actual_length(qtd
->urb
);
4239 dev_vdbg(hsotg
->dev
,
4240 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4241 __func__
, urb
, usb_pipedevice(urb
->pipe
),
4242 usb_pipeendpoint(urb
->pipe
),
4243 usb_pipein(urb
->pipe
) ? "IN" : "OUT", status
,
4244 urb
->actual_length
);
4246 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
4247 urb
->error_count
= dwc2_hcd_urb_get_error_count(qtd
->urb
);
4248 for (i
= 0; i
< urb
->number_of_packets
; ++i
) {
4249 urb
->iso_frame_desc
[i
].actual_length
=
4250 dwc2_hcd_urb_get_iso_desc_actual_length(
4252 urb
->iso_frame_desc
[i
].status
=
4253 dwc2_hcd_urb_get_iso_desc_status(qtd
->urb
, i
);
4257 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
&& dbg_perio()) {
4258 for (i
= 0; i
< urb
->number_of_packets
; i
++)
4259 dev_vdbg(hsotg
->dev
, " ISO Desc %d status %d\n",
4260 i
, urb
->iso_frame_desc
[i
].status
);
4263 urb
->status
= status
;
4265 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) &&
4266 urb
->actual_length
< urb
->transfer_buffer_length
)
4267 urb
->status
= -EREMOTEIO
;
4270 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
||
4271 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
) {
4272 struct usb_host_endpoint
*ep
= urb
->ep
;
4275 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg
),
4276 dwc2_hcd_get_ep_bandwidth(hsotg
, ep
),
4280 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg
), urb
);
4285 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg
), urb
, status
);
4289 * Work queue function for starting the HCD when A-Cable is connected
4291 static void dwc2_hcd_start_func(struct work_struct
*work
)
4293 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
4296 dev_dbg(hsotg
->dev
, "%s() %p\n", __func__
, hsotg
);
4297 dwc2_host_start(hsotg
);
4301 * Reset work queue function
4303 static void dwc2_hcd_reset_func(struct work_struct
*work
)
4305 struct dwc2_hsotg
*hsotg
= container_of(work
, struct dwc2_hsotg
,
4307 unsigned long flags
;
4310 dev_dbg(hsotg
->dev
, "USB RESET function called\n");
4312 spin_lock_irqsave(&hsotg
->lock
, flags
);
4314 hprt0
= dwc2_read_hprt0(hsotg
);
4315 hprt0
&= ~HPRT0_RST
;
4316 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
4317 hsotg
->flags
.b
.port_reset_change
= 1;
4319 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4323 * =========================================================================
4324 * Linux HC Driver Functions
4325 * =========================================================================
4329 * Initializes the DWC_otg controller and its root hub and prepares it for host
4330 * mode operation. Activates the root port. Returns 0 on success and a negative
4331 * error code on failure.
4333 static int _dwc2_hcd_start(struct usb_hcd
*hcd
)
4335 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4336 struct usb_bus
*bus
= hcd_to_bus(hcd
);
4337 unsigned long flags
;
4339 dev_dbg(hsotg
->dev
, "DWC OTG HCD START\n");
4341 spin_lock_irqsave(&hsotg
->lock
, flags
);
4342 hsotg
->lx_state
= DWC2_L0
;
4343 hcd
->state
= HC_STATE_RUNNING
;
4344 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
4346 if (dwc2_is_device_mode(hsotg
)) {
4347 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4348 return 0; /* why 0 ?? */
4351 dwc2_hcd_reinit(hsotg
);
4353 /* Initialize and connect root hub if one is not already attached */
4354 if (bus
->root_hub
) {
4355 dev_dbg(hsotg
->dev
, "DWC OTG HCD Has Root Hub\n");
4356 /* Inform the HUB driver to resume */
4357 usb_hcd_resume_root_hub(hcd
);
4360 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4365 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4368 static void _dwc2_hcd_stop(struct usb_hcd
*hcd
)
4370 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4371 unsigned long flags
;
4373 /* Turn off all host-specific interrupts */
4374 dwc2_disable_host_interrupts(hsotg
);
4376 /* Wait for interrupt processing to finish */
4377 synchronize_irq(hcd
->irq
);
4379 spin_lock_irqsave(&hsotg
->lock
, flags
);
4380 /* Ensure hcd is disconnected */
4381 dwc2_hcd_disconnect(hsotg
, true);
4382 dwc2_hcd_stop(hsotg
);
4383 hsotg
->lx_state
= DWC2_L3
;
4384 hcd
->state
= HC_STATE_HALT
;
4385 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
4386 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4388 usleep_range(1000, 3000);
4391 static int _dwc2_hcd_suspend(struct usb_hcd
*hcd
)
4393 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4394 unsigned long flags
;
4398 spin_lock_irqsave(&hsotg
->lock
, flags
);
4400 if (dwc2_is_device_mode(hsotg
))
4403 if (hsotg
->lx_state
!= DWC2_L0
)
4406 if (!HCD_HW_ACCESSIBLE(hcd
))
4409 if (hsotg
->op_state
== OTG_STATE_B_PERIPHERAL
)
4412 if (!hsotg
->params
.hibernation
)
4413 goto skip_power_saving
;
4416 * Drive USB suspend and disable port Power
4417 * if usb bus is not suspended.
4419 if (!hsotg
->bus_suspended
) {
4420 hprt0
= dwc2_read_hprt0(hsotg
);
4421 hprt0
|= HPRT0_SUSP
;
4422 hprt0
&= ~HPRT0_PWR
;
4423 dwc2_writel(hprt0
, hsotg
->regs
+ HPRT0
);
4426 /* Enter hibernation */
4427 ret
= dwc2_enter_hibernation(hsotg
);
4429 if (ret
!= -ENOTSUPP
)
4431 "enter hibernation failed\n");
4432 goto skip_power_saving
;
4435 /* Ask phy to be suspended */
4436 if (!IS_ERR_OR_NULL(hsotg
->uphy
)) {
4437 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4438 usb_phy_set_suspend(hsotg
->uphy
, true);
4439 spin_lock_irqsave(&hsotg
->lock
, flags
);
4442 /* After entering hibernation, hardware is no more accessible */
4443 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
4446 hsotg
->lx_state
= DWC2_L2
;
4448 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4453 static int _dwc2_hcd_resume(struct usb_hcd
*hcd
)
4455 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4456 unsigned long flags
;
4459 spin_lock_irqsave(&hsotg
->lock
, flags
);
4461 if (dwc2_is_device_mode(hsotg
))
4464 if (hsotg
->lx_state
!= DWC2_L2
)
4467 if (!hsotg
->params
.hibernation
) {
4468 hsotg
->lx_state
= DWC2_L0
;
4473 * Set HW accessible bit before powering on the controller
4474 * since an interrupt may rise.
4476 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
4479 * Enable power if not already done.
4480 * This must not be spinlocked since duration
4481 * of this call is unknown.
4483 if (!IS_ERR_OR_NULL(hsotg
->uphy
)) {
4484 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4485 usb_phy_set_suspend(hsotg
->uphy
, false);
4486 spin_lock_irqsave(&hsotg
->lock
, flags
);
4489 /* Exit hibernation */
4490 ret
= dwc2_exit_hibernation(hsotg
, true);
4491 if (ret
&& (ret
!= -ENOTSUPP
))
4492 dev_err(hsotg
->dev
, "exit hibernation failed\n");
4494 hsotg
->lx_state
= DWC2_L0
;
4496 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4498 if (hsotg
->bus_suspended
) {
4499 spin_lock_irqsave(&hsotg
->lock
, flags
);
4500 hsotg
->flags
.b
.port_suspend_change
= 1;
4501 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4502 dwc2_port_resume(hsotg
);
4504 /* Wait for controller to correctly update D+/D- level */
4505 usleep_range(3000, 5000);
4508 * Clear Port Enable and Port Status changes.
4509 * Enable Port Power.
4511 dwc2_writel(HPRT0_PWR
| HPRT0_CONNDET
|
4512 HPRT0_ENACHG
, hsotg
->regs
+ HPRT0
);
4513 /* Wait for controller to detect Port Connect */
4514 usleep_range(5000, 7000);
4519 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4524 /* Returns the current frame number */
4525 static int _dwc2_hcd_get_frame_number(struct usb_hcd
*hcd
)
4527 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4529 return dwc2_hcd_get_frame_number(hsotg
);
4532 static void dwc2_dump_urb_info(struct usb_hcd
*hcd
, struct urb
*urb
,
4535 #ifdef VERBOSE_DEBUG
4536 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4537 char *pipetype
= NULL
;
4540 dev_vdbg(hsotg
->dev
, "%s, urb %p\n", fn_name
, urb
);
4541 dev_vdbg(hsotg
->dev
, " Device address: %d\n",
4542 usb_pipedevice(urb
->pipe
));
4543 dev_vdbg(hsotg
->dev
, " Endpoint: %d, %s\n",
4544 usb_pipeendpoint(urb
->pipe
),
4545 usb_pipein(urb
->pipe
) ? "IN" : "OUT");
4547 switch (usb_pipetype(urb
->pipe
)) {
4549 pipetype
= "CONTROL";
4554 case PIPE_INTERRUPT
:
4555 pipetype
= "INTERRUPT";
4557 case PIPE_ISOCHRONOUS
:
4558 pipetype
= "ISOCHRONOUS";
4562 dev_vdbg(hsotg
->dev
, " Endpoint type: %s %s (%s)\n", pipetype
,
4563 usb_urb_dir_in(urb
) ? "IN" : "OUT", usb_pipein(urb
->pipe
) ?
4566 switch (urb
->dev
->speed
) {
4567 case USB_SPEED_HIGH
:
4570 case USB_SPEED_FULL
:
4581 dev_vdbg(hsotg
->dev
, " Speed: %s\n", speed
);
4582 dev_vdbg(hsotg
->dev
, " Max packet size: %d\n",
4583 usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
)));
4584 dev_vdbg(hsotg
->dev
, " Data buffer length: %d\n",
4585 urb
->transfer_buffer_length
);
4586 dev_vdbg(hsotg
->dev
, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4587 urb
->transfer_buffer
, (unsigned long)urb
->transfer_dma
);
4588 dev_vdbg(hsotg
->dev
, " Setup buffer: %p, Setup DMA: %08lx\n",
4589 urb
->setup_packet
, (unsigned long)urb
->setup_dma
);
4590 dev_vdbg(hsotg
->dev
, " Interval: %d\n", urb
->interval
);
4592 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
4595 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
4596 dev_vdbg(hsotg
->dev
, " ISO Desc %d:\n", i
);
4597 dev_vdbg(hsotg
->dev
, " offset: %d, length %d\n",
4598 urb
->iso_frame_desc
[i
].offset
,
4599 urb
->iso_frame_desc
[i
].length
);
4606 * Starts processing a USB transfer request specified by a USB Request Block
4607 * (URB). mem_flags indicates the type of memory allocation to use while
4608 * processing this URB.
4610 static int _dwc2_hcd_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
,
4613 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4614 struct usb_host_endpoint
*ep
= urb
->ep
;
4615 struct dwc2_hcd_urb
*dwc2_urb
;
4618 int alloc_bandwidth
= 0;
4622 unsigned long flags
;
4624 bool qh_allocated
= false;
4625 struct dwc2_qtd
*qtd
;
4628 dev_vdbg(hsotg
->dev
, "DWC OTG HCD URB Enqueue\n");
4629 dwc2_dump_urb_info(hcd
, urb
, "urb_enqueue");
4635 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
||
4636 usb_pipetype(urb
->pipe
) == PIPE_INTERRUPT
) {
4637 spin_lock_irqsave(&hsotg
->lock
, flags
);
4638 if (!dwc2_hcd_is_bandwidth_allocated(hsotg
, ep
))
4639 alloc_bandwidth
= 1;
4640 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4643 switch (usb_pipetype(urb
->pipe
)) {
4645 ep_type
= USB_ENDPOINT_XFER_CONTROL
;
4647 case PIPE_ISOCHRONOUS
:
4648 ep_type
= USB_ENDPOINT_XFER_ISOC
;
4651 ep_type
= USB_ENDPOINT_XFER_BULK
;
4653 case PIPE_INTERRUPT
:
4654 ep_type
= USB_ENDPOINT_XFER_INT
;
4658 dwc2_urb
= dwc2_hcd_urb_alloc(hsotg
, urb
->number_of_packets
,
4663 dwc2_hcd_urb_set_pipeinfo(hsotg
, dwc2_urb
, usb_pipedevice(urb
->pipe
),
4664 usb_pipeendpoint(urb
->pipe
), ep_type
,
4665 usb_pipein(urb
->pipe
),
4666 usb_maxpacket(urb
->dev
, urb
->pipe
,
4667 !(usb_pipein(urb
->pipe
))));
4669 buf
= urb
->transfer_buffer
;
4671 if (hcd
->self
.uses_dma
) {
4672 if (!buf
&& (urb
->transfer_dma
& 3)) {
4674 "%s: unaligned transfer with no transfer_buffer",
4681 if (!(urb
->transfer_flags
& URB_NO_INTERRUPT
))
4682 tflags
|= URB_GIVEBACK_ASAP
;
4683 if (urb
->transfer_flags
& URB_ZERO_PACKET
)
4684 tflags
|= URB_SEND_ZERO_PACKET
;
4686 dwc2_urb
->priv
= urb
;
4687 dwc2_urb
->buf
= buf
;
4688 dwc2_urb
->dma
= urb
->transfer_dma
;
4689 dwc2_urb
->length
= urb
->transfer_buffer_length
;
4690 dwc2_urb
->setup_packet
= urb
->setup_packet
;
4691 dwc2_urb
->setup_dma
= urb
->setup_dma
;
4692 dwc2_urb
->flags
= tflags
;
4693 dwc2_urb
->interval
= urb
->interval
;
4694 dwc2_urb
->status
= -EINPROGRESS
;
4696 for (i
= 0; i
< urb
->number_of_packets
; ++i
)
4697 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb
, i
,
4698 urb
->iso_frame_desc
[i
].offset
,
4699 urb
->iso_frame_desc
[i
].length
);
4701 urb
->hcpriv
= dwc2_urb
;
4702 qh
= (struct dwc2_qh
*)ep
->hcpriv
;
4703 /* Create QH for the endpoint if it doesn't exist */
4705 qh
= dwc2_hcd_qh_create(hsotg
, dwc2_urb
, mem_flags
);
4711 qh_allocated
= true;
4714 qtd
= kzalloc(sizeof(*qtd
), mem_flags
);
4720 spin_lock_irqsave(&hsotg
->lock
, flags
);
4721 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
4725 retval
= dwc2_hcd_urb_enqueue(hsotg
, dwc2_urb
, qh
, qtd
);
4729 if (alloc_bandwidth
) {
4730 dwc2_allocate_bus_bandwidth(hcd
,
4731 dwc2_hcd_get_ep_bandwidth(hsotg
, ep
),
4735 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4740 dwc2_urb
->priv
= NULL
;
4741 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
4742 if (qh_allocated
&& qh
->channel
&& qh
->channel
->qh
== qh
)
4743 qh
->channel
->qh
= NULL
;
4745 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4751 struct dwc2_qtd
*qtd2
, *qtd2_tmp
;
4754 dwc2_hcd_qh_unlink(hsotg
, qh
);
4755 /* Free each QTD in the QH's QTD list */
4756 list_for_each_entry_safe(qtd2
, qtd2_tmp
, &qh
->qtd_list
,
4758 dwc2_hcd_qtd_unlink_and_free(hsotg
, qtd2
, qh
);
4759 dwc2_hcd_qh_free(hsotg
, qh
);
4768 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4770 static int _dwc2_hcd_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
,
4773 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4775 unsigned long flags
;
4777 dev_dbg(hsotg
->dev
, "DWC OTG HCD URB Dequeue\n");
4778 dwc2_dump_urb_info(hcd
, urb
, "urb_dequeue");
4780 spin_lock_irqsave(&hsotg
->lock
, flags
);
4782 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
4787 dev_dbg(hsotg
->dev
, "## urb->hcpriv is NULL ##\n");
4791 rc
= dwc2_hcd_urb_dequeue(hsotg
, urb
->hcpriv
);
4793 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
4798 /* Higher layer software sets URB status */
4799 spin_unlock(&hsotg
->lock
);
4800 usb_hcd_giveback_urb(hcd
, urb
, status
);
4801 spin_lock(&hsotg
->lock
);
4803 dev_dbg(hsotg
->dev
, "Called usb_hcd_giveback_urb()\n");
4804 dev_dbg(hsotg
->dev
, " urb->status = %d\n", urb
->status
);
4806 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4812 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4813 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4814 * must already be dequeued.
4816 static void _dwc2_hcd_endpoint_disable(struct usb_hcd
*hcd
,
4817 struct usb_host_endpoint
*ep
)
4819 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4822 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4823 ep
->desc
.bEndpointAddress
, ep
->hcpriv
);
4824 dwc2_hcd_endpoint_disable(hsotg
, ep
, 250);
4828 * Resets endpoint specific parameter values, in current version used to reset
4829 * the data toggle (as a WA). This function can be called from usb_clear_halt
4832 static void _dwc2_hcd_endpoint_reset(struct usb_hcd
*hcd
,
4833 struct usb_host_endpoint
*ep
)
4835 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4836 unsigned long flags
;
4839 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4840 ep
->desc
.bEndpointAddress
);
4842 spin_lock_irqsave(&hsotg
->lock
, flags
);
4843 dwc2_hcd_endpoint_reset(hsotg
, ep
);
4844 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4848 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4849 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4852 * This function is called by the USB core when an interrupt occurs
4854 static irqreturn_t
_dwc2_hcd_irq(struct usb_hcd
*hcd
)
4856 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4858 return dwc2_handle_hcd_intr(hsotg
);
4862 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4863 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4864 * is the status change indicator for the single root port. Returns 1 if either
4865 * change indicator is 1, otherwise returns 0.
4867 static int _dwc2_hcd_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
4869 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4871 buf
[0] = dwc2_hcd_is_status_changed(hsotg
, 1) << 1;
4875 /* Handles hub class-specific requests */
4876 static int _dwc2_hcd_hub_control(struct usb_hcd
*hcd
, u16 typereq
, u16 wvalue
,
4877 u16 windex
, char *buf
, u16 wlength
)
4879 int retval
= dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd
), typereq
,
4880 wvalue
, windex
, buf
, wlength
);
4884 /* Handles hub TT buffer clear completions */
4885 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd
*hcd
,
4886 struct usb_host_endpoint
*ep
)
4888 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4890 unsigned long flags
;
4896 spin_lock_irqsave(&hsotg
->lock
, flags
);
4897 qh
->tt_buffer_dirty
= 0;
4899 if (hsotg
->flags
.b
.port_connect_status
)
4900 dwc2_hcd_queue_transactions(hsotg
, DWC2_TRANSACTION_ALL
);
4902 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4906 * HPRT0_SPD_HIGH_SPEED: high speed
4907 * HPRT0_SPD_FULL_SPEED: full speed
4909 static void dwc2_change_bus_speed(struct usb_hcd
*hcd
, int speed
)
4911 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4913 if (hsotg
->params
.speed
== speed
)
4916 hsotg
->params
.speed
= speed
;
4917 queue_work(hsotg
->wq_otg
, &hsotg
->wf_otg
);
4920 static void dwc2_free_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4922 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4924 if (!hsotg
->params
.change_speed_quirk
)
4928 * On removal, set speed to default high-speed.
4930 if (udev
->parent
&& udev
->parent
->speed
> USB_SPEED_UNKNOWN
&&
4931 udev
->parent
->speed
< USB_SPEED_HIGH
) {
4932 dev_info(hsotg
->dev
, "Set speed to default high-speed\n");
4933 dwc2_change_bus_speed(hcd
, HPRT0_SPD_HIGH_SPEED
);
4937 static int dwc2_reset_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4939 struct dwc2_hsotg
*hsotg
= dwc2_hcd_to_hsotg(hcd
);
4941 if (!hsotg
->params
.change_speed_quirk
)
4944 if (udev
->speed
== USB_SPEED_HIGH
) {
4945 dev_info(hsotg
->dev
, "Set speed to high-speed\n");
4946 dwc2_change_bus_speed(hcd
, HPRT0_SPD_HIGH_SPEED
);
4947 } else if ((udev
->speed
== USB_SPEED_FULL
||
4948 udev
->speed
== USB_SPEED_LOW
)) {
4950 * Change speed setting to full-speed if there's
4951 * a full-speed or low-speed device plugged in.
4953 dev_info(hsotg
->dev
, "Set speed to full-speed\n");
4954 dwc2_change_bus_speed(hcd
, HPRT0_SPD_FULL_SPEED
);
4960 static struct hc_driver dwc2_hc_driver
= {
4961 .description
= "dwc2_hsotg",
4962 .product_desc
= "DWC OTG Controller",
4963 .hcd_priv_size
= sizeof(struct wrapper_priv_data
),
4965 .irq
= _dwc2_hcd_irq
,
4966 .flags
= HCD_MEMORY
| HCD_USB2
| HCD_BH
,
4968 .start
= _dwc2_hcd_start
,
4969 .stop
= _dwc2_hcd_stop
,
4970 .urb_enqueue
= _dwc2_hcd_urb_enqueue
,
4971 .urb_dequeue
= _dwc2_hcd_urb_dequeue
,
4972 .endpoint_disable
= _dwc2_hcd_endpoint_disable
,
4973 .endpoint_reset
= _dwc2_hcd_endpoint_reset
,
4974 .get_frame_number
= _dwc2_hcd_get_frame_number
,
4976 .hub_status_data
= _dwc2_hcd_hub_status_data
,
4977 .hub_control
= _dwc2_hcd_hub_control
,
4978 .clear_tt_buffer_complete
= _dwc2_hcd_clear_tt_buffer_complete
,
4980 .bus_suspend
= _dwc2_hcd_suspend
,
4981 .bus_resume
= _dwc2_hcd_resume
,
4983 .map_urb_for_dma
= dwc2_map_urb_for_dma
,
4984 .unmap_urb_for_dma
= dwc2_unmap_urb_for_dma
,
4988 * Frees secondary storage associated with the dwc2_hsotg structure contained
4989 * in the struct usb_hcd field
4991 static void dwc2_hcd_free(struct dwc2_hsotg
*hsotg
)
4997 dev_dbg(hsotg
->dev
, "DWC OTG HCD FREE\n");
4999 /* Free memory for QH/QTD lists */
5000 dwc2_qh_list_free(hsotg
, &hsotg
->non_periodic_sched_inactive
);
5001 dwc2_qh_list_free(hsotg
, &hsotg
->non_periodic_sched_active
);
5002 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_inactive
);
5003 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_ready
);
5004 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_assigned
);
5005 dwc2_qh_list_free(hsotg
, &hsotg
->periodic_sched_queued
);
5007 /* Free memory for the host channels */
5008 for (i
= 0; i
< MAX_EPS_CHANNELS
; i
++) {
5009 struct dwc2_host_chan
*chan
= hsotg
->hc_ptr_array
[i
];
5012 dev_dbg(hsotg
->dev
, "HCD Free channel #%i, chan=%p\n",
5014 hsotg
->hc_ptr_array
[i
] = NULL
;
5019 if (hsotg
->params
.host_dma
) {
5020 if (hsotg
->status_buf
) {
5021 dma_free_coherent(hsotg
->dev
, DWC2_HCD_STATUS_BUF_SIZE
,
5023 hsotg
->status_buf_dma
);
5024 hsotg
->status_buf
= NULL
;
5027 kfree(hsotg
->status_buf
);
5028 hsotg
->status_buf
= NULL
;
5031 ahbcfg
= dwc2_readl(hsotg
->regs
+ GAHBCFG
);
5033 /* Disable all interrupts */
5034 ahbcfg
&= ~GAHBCFG_GLBL_INTR_EN
;
5035 dwc2_writel(ahbcfg
, hsotg
->regs
+ GAHBCFG
);
5036 dwc2_writel(0, hsotg
->regs
+ GINTMSK
);
5038 if (hsotg
->hw_params
.snpsid
>= DWC2_CORE_REV_3_00a
) {
5039 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
5040 dctl
|= DCTL_SFTDISCON
;
5041 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
5044 if (hsotg
->wq_otg
) {
5045 if (!cancel_work_sync(&hsotg
->wf_otg
))
5046 flush_workqueue(hsotg
->wq_otg
);
5047 destroy_workqueue(hsotg
->wq_otg
);
5050 del_timer(&hsotg
->wkp_timer
);
5053 static void dwc2_hcd_release(struct dwc2_hsotg
*hsotg
)
5055 /* Turn off all host-specific interrupts */
5056 dwc2_disable_host_interrupts(hsotg
);
5058 dwc2_hcd_free(hsotg
);
5062 * Initializes the HCD. This function allocates memory for and initializes the
5063 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5064 * USB bus with the core and calls the hc_driver->start() function. It returns
5065 * a negative error on failure.
5067 int dwc2_hcd_init(struct dwc2_hsotg
*hsotg
)
5069 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
5070 struct resource
*res
;
5071 struct usb_hcd
*hcd
;
5072 struct dwc2_host_chan
*channel
;
5074 int i
, num_channels
;
5080 dev_dbg(hsotg
->dev
, "DWC OTG HCD INIT\n");
5084 hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
5085 dev_dbg(hsotg
->dev
, "hcfg=%08x\n", hcfg
);
5087 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5088 hsotg
->frame_num_array
= kzalloc(sizeof(*hsotg
->frame_num_array
) *
5089 FRAME_NUM_ARRAY_SIZE
, GFP_KERNEL
);
5090 if (!hsotg
->frame_num_array
)
5092 hsotg
->last_frame_num_array
= kzalloc(
5093 sizeof(*hsotg
->last_frame_num_array
) *
5094 FRAME_NUM_ARRAY_SIZE
, GFP_KERNEL
);
5095 if (!hsotg
->last_frame_num_array
)
5098 hsotg
->last_frame_num
= HFNUM_MAX_FRNUM
;
5100 /* Check if the bus driver or platform code has setup a dma_mask */
5101 if (hsotg
->params
.host_dma
&&
5102 !hsotg
->dev
->dma_mask
) {
5103 dev_warn(hsotg
->dev
,
5104 "dma_mask not set, disabling DMA\n");
5105 hsotg
->params
.host_dma
= false;
5106 hsotg
->params
.dma_desc_enable
= false;
5109 /* Set device flags indicating whether the HCD supports DMA */
5110 if (hsotg
->params
.host_dma
) {
5111 if (dma_set_mask(hsotg
->dev
, DMA_BIT_MASK(32)) < 0)
5112 dev_warn(hsotg
->dev
, "can't set DMA mask\n");
5113 if (dma_set_coherent_mask(hsotg
->dev
, DMA_BIT_MASK(32)) < 0)
5114 dev_warn(hsotg
->dev
, "can't set coherent DMA mask\n");
5117 if (hsotg
->params
.change_speed_quirk
) {
5118 dwc2_hc_driver
.free_dev
= dwc2_free_dev
;
5119 dwc2_hc_driver
.reset_device
= dwc2_reset_device
;
5122 hcd
= usb_create_hcd(&dwc2_hc_driver
, hsotg
->dev
, dev_name(hsotg
->dev
));
5126 if (!hsotg
->params
.host_dma
)
5127 hcd
->self
.uses_dma
= 0;
5131 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
5132 hcd
->rsrc_start
= res
->start
;
5133 hcd
->rsrc_len
= resource_size(res
);
5135 ((struct wrapper_priv_data
*)&hcd
->hcd_priv
)->hsotg
= hsotg
;
5139 * Disable the global interrupt until all the interrupt handlers are
5142 dwc2_disable_global_interrupts(hsotg
);
5144 /* Initialize the DWC_otg core, and select the Phy type */
5145 retval
= dwc2_core_init(hsotg
, true);
5149 /* Create new workqueue and init work */
5151 hsotg
->wq_otg
= alloc_ordered_workqueue("dwc2", 0);
5152 if (!hsotg
->wq_otg
) {
5153 dev_err(hsotg
->dev
, "Failed to create workqueue\n");
5156 INIT_WORK(&hsotg
->wf_otg
, dwc2_conn_id_status_change
);
5158 setup_timer(&hsotg
->wkp_timer
, dwc2_wakeup_detected
,
5159 (unsigned long)hsotg
);
5161 /* Initialize the non-periodic schedule */
5162 INIT_LIST_HEAD(&hsotg
->non_periodic_sched_inactive
);
5163 INIT_LIST_HEAD(&hsotg
->non_periodic_sched_active
);
5165 /* Initialize the periodic schedule */
5166 INIT_LIST_HEAD(&hsotg
->periodic_sched_inactive
);
5167 INIT_LIST_HEAD(&hsotg
->periodic_sched_ready
);
5168 INIT_LIST_HEAD(&hsotg
->periodic_sched_assigned
);
5169 INIT_LIST_HEAD(&hsotg
->periodic_sched_queued
);
5171 INIT_LIST_HEAD(&hsotg
->split_order
);
5174 * Create a host channel descriptor for each host channel implemented
5175 * in the controller. Initialize the channel descriptor array.
5177 INIT_LIST_HEAD(&hsotg
->free_hc_list
);
5178 num_channels
= hsotg
->params
.host_channels
;
5179 memset(&hsotg
->hc_ptr_array
[0], 0, sizeof(hsotg
->hc_ptr_array
));
5181 for (i
= 0; i
< num_channels
; i
++) {
5182 channel
= kzalloc(sizeof(*channel
), GFP_KERNEL
);
5185 channel
->hc_num
= i
;
5186 INIT_LIST_HEAD(&channel
->split_order_list_entry
);
5187 hsotg
->hc_ptr_array
[i
] = channel
;
5190 /* Initialize hsotg start work */
5191 INIT_DELAYED_WORK(&hsotg
->start_work
, dwc2_hcd_start_func
);
5193 /* Initialize port reset work */
5194 INIT_DELAYED_WORK(&hsotg
->reset_work
, dwc2_hcd_reset_func
);
5197 * Allocate space for storing data on status transactions. Normally no
5198 * data is sent, but this space acts as a bit bucket. This must be
5199 * done after usb_add_hcd since that function allocates the DMA buffer
5202 if (hsotg
->params
.host_dma
)
5203 hsotg
->status_buf
= dma_alloc_coherent(hsotg
->dev
,
5204 DWC2_HCD_STATUS_BUF_SIZE
,
5205 &hsotg
->status_buf_dma
, GFP_KERNEL
);
5207 hsotg
->status_buf
= kzalloc(DWC2_HCD_STATUS_BUF_SIZE
,
5210 if (!hsotg
->status_buf
)
5214 * Create kmem caches to handle descriptor buffers in descriptor
5216 * Alignment must be set to 512 bytes.
5218 if (hsotg
->params
.dma_desc_enable
||
5219 hsotg
->params
.dma_desc_fs_enable
) {
5220 hsotg
->desc_gen_cache
= kmem_cache_create("dwc2-gen-desc",
5221 sizeof(struct dwc2_dma_desc
) *
5222 MAX_DMA_DESC_NUM_GENERIC
, 512, SLAB_CACHE_DMA
,
5224 if (!hsotg
->desc_gen_cache
) {
5226 "unable to create dwc2 generic desc cache\n");
5229 * Disable descriptor dma mode since it will not be
5232 hsotg
->params
.dma_desc_enable
= false;
5233 hsotg
->params
.dma_desc_fs_enable
= false;
5236 hsotg
->desc_hsisoc_cache
= kmem_cache_create("dwc2-hsisoc-desc",
5237 sizeof(struct dwc2_dma_desc
) *
5238 MAX_DMA_DESC_NUM_HS_ISOC
, 512, 0, NULL
);
5239 if (!hsotg
->desc_hsisoc_cache
) {
5241 "unable to create dwc2 hs isoc desc cache\n");
5243 kmem_cache_destroy(hsotg
->desc_gen_cache
);
5246 * Disable descriptor dma mode since it will not be
5249 hsotg
->params
.dma_desc_enable
= false;
5250 hsotg
->params
.dma_desc_fs_enable
= false;
5254 hsotg
->otg_port
= 1;
5255 hsotg
->frame_list
= NULL
;
5256 hsotg
->frame_list_dma
= 0;
5257 hsotg
->periodic_qh_count
= 0;
5259 /* Initiate lx_state to L3 disconnected state */
5260 hsotg
->lx_state
= DWC2_L3
;
5262 hcd
->self
.otg_port
= hsotg
->otg_port
;
5264 /* Don't support SG list at this point */
5265 hcd
->self
.sg_tablesize
= 0;
5267 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
5268 otg_set_host(hsotg
->uphy
->otg
, &hcd
->self
);
5271 * Finish generic HCD initialization and start the HCD. This function
5272 * allocates the DMA buffer pool, registers the USB bus, requests the
5273 * IRQ line, and calls hcd_start method.
5275 retval
= usb_add_hcd(hcd
, hsotg
->irq
, IRQF_SHARED
);
5279 device_wakeup_enable(hcd
->self
.controller
);
5281 dwc2_hcd_dump_state(hsotg
);
5283 dwc2_enable_global_interrupts(hsotg
);
5288 kmem_cache_destroy(hsotg
->desc_gen_cache
);
5289 kmem_cache_destroy(hsotg
->desc_hsisoc_cache
);
5291 dwc2_hcd_release(hsotg
);
5296 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5297 kfree(hsotg
->last_frame_num_array
);
5298 kfree(hsotg
->frame_num_array
);
5301 dev_err(hsotg
->dev
, "%s() FAILED, returning %d\n", __func__
, retval
);
5307 * Frees memory and resources associated with the HCD and deregisters the bus.
5309 void dwc2_hcd_remove(struct dwc2_hsotg
*hsotg
)
5311 struct usb_hcd
*hcd
;
5313 dev_dbg(hsotg
->dev
, "DWC OTG HCD REMOVE\n");
5315 hcd
= dwc2_hsotg_to_hcd(hsotg
);
5316 dev_dbg(hsotg
->dev
, "hsotg->hcd = %p\n", hcd
);
5319 dev_dbg(hsotg
->dev
, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5324 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
5325 otg_set_host(hsotg
->uphy
->otg
, NULL
);
5327 usb_remove_hcd(hcd
);
5330 kmem_cache_destroy(hsotg
->desc_gen_cache
);
5331 kmem_cache_destroy(hsotg
->desc_hsisoc_cache
);
5333 dwc2_hcd_release(hsotg
);
5336 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5337 kfree(hsotg
->last_frame_num_array
);
5338 kfree(hsotg
->frame_num_array
);
5343 * dwc2_backup_host_registers() - Backup controller host registers.
5344 * When suspending usb bus, registers needs to be backuped
5345 * if controller power is disabled once suspended.
5347 * @hsotg: Programming view of the DWC_otg controller
5349 int dwc2_backup_host_registers(struct dwc2_hsotg
*hsotg
)
5351 struct dwc2_hregs_backup
*hr
;
5354 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
5356 /* Backup Host regs */
5357 hr
= &hsotg
->hr_backup
;
5358 hr
->hcfg
= dwc2_readl(hsotg
->regs
+ HCFG
);
5359 hr
->haintmsk
= dwc2_readl(hsotg
->regs
+ HAINTMSK
);
5360 for (i
= 0; i
< hsotg
->params
.host_channels
; ++i
)
5361 hr
->hcintmsk
[i
] = dwc2_readl(hsotg
->regs
+ HCINTMSK(i
));
5363 hr
->hprt0
= dwc2_read_hprt0(hsotg
);
5364 hr
->hfir
= dwc2_readl(hsotg
->regs
+ HFIR
);
5371 * dwc2_restore_host_registers() - Restore controller host registers.
5372 * When resuming usb bus, device registers needs to be restored
5373 * if controller power were disabled.
5375 * @hsotg: Programming view of the DWC_otg controller
5377 int dwc2_restore_host_registers(struct dwc2_hsotg
*hsotg
)
5379 struct dwc2_hregs_backup
*hr
;
5382 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
5384 /* Restore host regs */
5385 hr
= &hsotg
->hr_backup
;
5387 dev_err(hsotg
->dev
, "%s: no host registers to restore\n",
5393 dwc2_writel(hr
->hcfg
, hsotg
->regs
+ HCFG
);
5394 dwc2_writel(hr
->haintmsk
, hsotg
->regs
+ HAINTMSK
);
5396 for (i
= 0; i
< hsotg
->params
.host_channels
; ++i
)
5397 dwc2_writel(hr
->hcintmsk
[i
], hsotg
->regs
+ HCINTMSK(i
));
5399 dwc2_writel(hr
->hprt0
, hsotg
->regs
+ HPRT0
);
5400 dwc2_writel(hr
->hfir
, hsotg
->regs
+ HFIR
);
5401 hsotg
->frame_number
= 0;