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[mirror_ubuntu-bionic-kernel.git] / drivers / video / fbdev / aty / radeon_base.c
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include "radeonfb.h"
56
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/ctype.h>
63 #include <linux/mm.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/time.h>
67 #include <linux/fb.h>
68 #include <linux/ioport.h>
69 #include <linux/init.h>
70 #include <linux/pci.h>
71 #include <linux/vmalloc.h>
72 #include <linux/device.h>
73
74 #include <asm/io.h>
75 #include <linux/uaccess.h>
76
77 #ifdef CONFIG_PPC
78
79 #include "../macmodes.h"
80
81 #ifdef CONFIG_BOOTX_TEXT
82 #include <asm/btext.h>
83 #endif
84
85 #endif /* CONFIG_PPC */
86
87 #include <video/radeon.h>
88 #include <linux/radeonfb.h>
89
90 #include "../edid.h" // MOVE THAT TO include/video
91 #include "ati_ids.h"
92
93 #define MAX_MAPPED_VRAM (2048*2048*4)
94 #define MIN_MAPPED_VRAM (1024*768*1)
95
96 #define CHIP_DEF(id, family, flags) \
97 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
98
99 static const struct pci_device_id radeonfb_pci_table[] = {
100 /* Radeon Xpress 200m */
101 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
102 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
103 /* Mobility M6 */
104 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106 /* Radeon VE/7000 */
107 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
108 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
109 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
110 /* Radeon IGP320M (U1) */
111 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
112 /* Radeon IGP320 (A3) */
113 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
114 /* IGP330M/340M/350M (U2) */
115 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
116 /* IGP330/340/350 (A4) */
117 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
118 /* Mobility 7000 IGP */
119 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
120 /* 7000 IGP (A4+) */
121 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
122 /* 8500 AIW */
123 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
124 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
125 /* 8700/8800 */
126 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
127 /* 8500 */
128 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
129 /* 9100 */
130 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
131 /* Mobility M7 */
132 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
133 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134 /* 7500 */
135 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
136 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
137 /* Mobility M9 */
138 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 /* 9000/Pro */
143 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
144 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
145
146 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
147 /* Mobility 9100 IGP (U3) */
148 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
149 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 /* 9100 IGP (A5) */
151 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
152 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
153 /* Mobility 9200 (M9+) */
154 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
155 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 /* 9200 */
157 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
158 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
159 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
161 /* 9500 */
162 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
164 /* 9600TX / FireGL Z1 */
165 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
166 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
167 /* 9700/9500/Pro/FireGL X1 */
168 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
172 /* Mobility M10/M11 */
173 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
174 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 /* 9600/FireGL T2 */
180 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
181 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
186 /* 9800/Pro/FileGL X2 */
187 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
195 /* Newer stuff */
196 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
199 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
200 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
206 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
207 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
214 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
223 /* Original Radeon/7200 */
224 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
225 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
226 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
227 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
228 { 0, }
229 };
230 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
231
232
233 typedef struct {
234 u16 reg;
235 u32 val;
236 } reg_val;
237
238
239 /* these common regs are cleared before mode setting so they do not
240 * interfere with anything
241 */
242 static reg_val common_regs[] = {
243 { OVR_CLR, 0 },
244 { OVR_WID_LEFT_RIGHT, 0 },
245 { OVR_WID_TOP_BOTTOM, 0 },
246 { OV0_SCALE_CNTL, 0 },
247 { SUBPIC_CNTL, 0 },
248 { VIPH_CONTROL, 0 },
249 { I2C_CNTL_1, 0 },
250 { GEN_INT_CNTL, 0 },
251 { CAP0_TRIG_CNTL, 0 },
252 { CAP1_TRIG_CNTL, 0 },
253 };
254
255 /*
256 * globals
257 */
258
259 static char *mode_option;
260 static char *monitor_layout;
261 static bool noaccel = 0;
262 static int default_dynclk = -2;
263 static bool nomodeset = 0;
264 static bool ignore_edid = 0;
265 static bool mirror = 0;
266 static int panel_yres = 0;
267 static bool force_dfp = 0;
268 static bool force_measure_pll = 0;
269 static bool nomtrr = 0;
270 static bool force_sleep;
271 static bool ignore_devlist;
272 #ifdef CONFIG_PMAC_BACKLIGHT
273 static int backlight = 1;
274 #else
275 static int backlight = 0;
276 #endif
277
278 /* Note about this function: we have some rare cases where we must not schedule,
279 * this typically happen with our special "wake up early" hook which allows us to
280 * wake up the graphic chip (and thus get the console back) before everything else
281 * on some machines that support that mechanism. At this point, interrupts are off
282 * and scheduling is not permitted
283 */
284 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
285 {
286 if (rinfo->no_schedule || oops_in_progress)
287 mdelay(ms);
288 else
289 msleep(ms);
290 }
291
292 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
293 {
294 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
295 (void)INREG(CLOCK_CNTL_DATA);
296 (void)INREG(CRTC_GEN_CNTL);
297 }
298
299 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
300 {
301 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
302 /* we can't deal with posted writes here ... */
303 _radeon_msleep(rinfo, 5);
304 }
305 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
306 u32 save, tmp;
307 save = INREG(CLOCK_CNTL_INDEX);
308 tmp = save & ~(0x3f | PLL_WR_EN);
309 OUTREG(CLOCK_CNTL_INDEX, tmp);
310 tmp = INREG(CLOCK_CNTL_DATA);
311 OUTREG(CLOCK_CNTL_INDEX, save);
312 }
313 }
314
315 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
316 {
317 unsigned long flags;
318 unsigned int tmp;
319
320 spin_lock_irqsave(&rinfo->reg_lock, flags);
321 tmp = INREG(addr);
322 tmp &= (mask);
323 tmp |= (val);
324 OUTREG(addr, tmp);
325 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
326 }
327
328 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
329 {
330 u32 data;
331
332 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
333 radeon_pll_errata_after_index(rinfo);
334 data = INREG(CLOCK_CNTL_DATA);
335 radeon_pll_errata_after_data(rinfo);
336 return data;
337 }
338
339 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
340 {
341 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
342 radeon_pll_errata_after_index(rinfo);
343 OUTREG(CLOCK_CNTL_DATA, val);
344 radeon_pll_errata_after_data(rinfo);
345 }
346
347 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
348 u32 val, u32 mask)
349 {
350 unsigned int tmp;
351
352 tmp = __INPLL(rinfo, index);
353 tmp &= (mask);
354 tmp |= (val);
355 __OUTPLL(rinfo, index, tmp);
356 }
357
358 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
359 {
360 int i;
361
362 for (i=0; i<2000000; i++) {
363 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
364 return;
365 udelay(1);
366 }
367 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
368 }
369
370 void radeon_engine_flush(struct radeonfb_info *rinfo)
371 {
372 int i;
373
374 /* Initiate flush */
375 OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
376 ~RB2D_DC_FLUSH_ALL);
377
378 /* Ensure FIFO is empty, ie, make sure the flush commands
379 * has reached the cache
380 */
381 _radeon_fifo_wait(rinfo, 64);
382
383 /* Wait for the flush to complete */
384 for (i=0; i < 2000000; i++) {
385 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
386 return;
387 udelay(1);
388 }
389 printk(KERN_ERR "radeonfb: Flush Timeout !\n");
390 }
391
392 void _radeon_engine_idle(struct radeonfb_info *rinfo)
393 {
394 int i;
395
396 /* ensure FIFO is empty before waiting for idle */
397 _radeon_fifo_wait(rinfo, 64);
398
399 for (i=0; i<2000000; i++) {
400 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
401 radeon_engine_flush(rinfo);
402 return;
403 }
404 udelay(1);
405 }
406 printk(KERN_ERR "radeonfb: Idle Timeout !\n");
407 }
408
409
410
411 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
412 {
413 if (!rinfo->bios_seg)
414 return;
415 pci_unmap_rom(dev, rinfo->bios_seg);
416 }
417
418 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
419 {
420 void __iomem *rom;
421 u16 dptr;
422 u8 rom_type;
423 size_t rom_size;
424
425 /* If this is a primary card, there is a shadow copy of the
426 * ROM somewhere in the first meg. We will just ignore the copy
427 * and use the ROM directly.
428 */
429
430 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
431 unsigned int temp;
432 temp = INREG(MPP_TB_CONFIG);
433 temp &= 0x00ffffffu;
434 temp |= 0x04 << 24;
435 OUTREG(MPP_TB_CONFIG, temp);
436 temp = INREG(MPP_TB_CONFIG);
437
438 rom = pci_map_rom(dev, &rom_size);
439 if (!rom) {
440 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
441 pci_name(rinfo->pdev));
442 return -ENOMEM;
443 }
444
445 rinfo->bios_seg = rom;
446
447 /* Very simple test to make sure it appeared */
448 if (BIOS_IN16(0) != 0xaa55) {
449 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
450 "should be 0xaa55\n",
451 pci_name(rinfo->pdev), BIOS_IN16(0));
452 goto failed;
453 }
454 /* Look for the PCI data to check the ROM type */
455 dptr = BIOS_IN16(0x18);
456
457 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
458 * for now, until I've verified this works everywhere. The goal here is more
459 * to phase out Open Firmware images.
460 *
461 * Currently, we only look at the first PCI data, we could iteratre and deal with
462 * them all, and we should use fb_bios_start relative to start of image and not
463 * relative start of ROM, but so far, I never found a dual-image ATI card
464 *
465 * typedef struct {
466 * u32 signature; + 0x00
467 * u16 vendor; + 0x04
468 * u16 device; + 0x06
469 * u16 reserved_1; + 0x08
470 * u16 dlen; + 0x0a
471 * u8 drevision; + 0x0c
472 * u8 class_hi; + 0x0d
473 * u16 class_lo; + 0x0e
474 * u16 ilen; + 0x10
475 * u16 irevision; + 0x12
476 * u8 type; + 0x14
477 * u8 indicator; + 0x15
478 * u16 reserved_2; + 0x16
479 * } pci_data_t;
480 */
481 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
482 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
483 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
484 goto anyway;
485 }
486 rom_type = BIOS_IN8(dptr + 0x14);
487 switch(rom_type) {
488 case 0:
489 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
490 break;
491 case 1:
492 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
493 goto failed;
494 case 2:
495 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
496 goto failed;
497 default:
498 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
499 goto failed;
500 }
501 anyway:
502 /* Locate the flat panel infos, do some sanity checking !!! */
503 rinfo->fp_bios_start = BIOS_IN16(0x48);
504 return 0;
505
506 failed:
507 rinfo->bios_seg = NULL;
508 radeon_unmap_ROM(rinfo, dev);
509 return -ENXIO;
510 }
511
512 #ifdef CONFIG_X86
513 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
514 {
515 /* I simplified this code as we used to miss the signatures in
516 * a lot of case. It's now closer to XFree, we just don't check
517 * for signatures at all... Something better will have to be done
518 * if we end up having conflicts
519 */
520 u32 segstart;
521 void __iomem *rom_base = NULL;
522
523 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
524 rom_base = ioremap(segstart, 0x10000);
525 if (rom_base == NULL)
526 return -ENOMEM;
527 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
528 break;
529 iounmap(rom_base);
530 rom_base = NULL;
531 }
532 if (rom_base == NULL)
533 return -ENXIO;
534
535 /* Locate the flat panel infos, do some sanity checking !!! */
536 rinfo->bios_seg = rom_base;
537 rinfo->fp_bios_start = BIOS_IN16(0x48);
538
539 return 0;
540 }
541 #endif
542
543 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
544 /*
545 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
546 * tree. Hopefully, ATI OF driver is kind enough to fill these
547 */
548 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
549 {
550 struct device_node *dp = rinfo->of_node;
551 const u32 *val;
552
553 if (dp == NULL)
554 return -ENODEV;
555 val = of_get_property(dp, "ATY,RefCLK", NULL);
556 if (!val || !*val) {
557 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
558 return -EINVAL;
559 }
560
561 rinfo->pll.ref_clk = (*val) / 10;
562
563 val = of_get_property(dp, "ATY,SCLK", NULL);
564 if (val && *val)
565 rinfo->pll.sclk = (*val) / 10;
566
567 val = of_get_property(dp, "ATY,MCLK", NULL);
568 if (val && *val)
569 rinfo->pll.mclk = (*val) / 10;
570
571 return 0;
572 }
573 #endif /* CONFIG_PPC || CONFIG_SPARC */
574
575 /*
576 * Read PLL infos from chip registers
577 */
578 static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
579 {
580 unsigned char ppll_div_sel;
581 unsigned Ns, Nm, M;
582 unsigned sclk, mclk, tmp, ref_div;
583 int hTotal, vTotal, num, denom, m, n;
584 unsigned long long hz, vclk;
585 long xtal;
586 struct timeval start_tv, stop_tv;
587 long total_secs, total_usecs;
588 int i;
589
590 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
591 * here, so... --BenH
592 */
593
594 /* Flush PCI buffers ? */
595 tmp = INREG16(DEVICE_ID);
596
597 local_irq_disable();
598
599 for(i=0; i<1000000; i++)
600 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
601 break;
602
603 do_gettimeofday(&start_tv);
604
605 for(i=0; i<1000000; i++)
606 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
607 break;
608
609 for(i=0; i<1000000; i++)
610 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
611 break;
612
613 do_gettimeofday(&stop_tv);
614
615 local_irq_enable();
616
617 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
618 if (total_secs > 10)
619 return -1;
620 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
621 total_usecs += total_secs * 1000000;
622 if (total_usecs < 0)
623 total_usecs = -total_usecs;
624 hz = 1000000/total_usecs;
625
626 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
627 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
628 vclk = (long long)hTotal * (long long)vTotal * hz;
629
630 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
631 case 0:
632 default:
633 num = 1;
634 denom = 1;
635 break;
636 case 1:
637 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
638 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
639 num = 2*n;
640 denom = 2*m;
641 break;
642 case 2:
643 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
644 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
645 num = 2*n;
646 denom = 2*m;
647 break;
648 }
649
650 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
651 radeon_pll_errata_after_index(rinfo);
652
653 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
654 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
655
656 num *= n;
657 denom *= m;
658
659 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
660 case 1:
661 denom *= 2;
662 break;
663 case 2:
664 denom *= 4;
665 break;
666 case 3:
667 denom *= 8;
668 break;
669 case 4:
670 denom *= 3;
671 break;
672 case 6:
673 denom *= 6;
674 break;
675 case 7:
676 denom *= 12;
677 break;
678 }
679
680 vclk *= denom;
681 do_div(vclk, 1000 * num);
682 xtal = vclk;
683
684 if ((xtal > 26900) && (xtal < 27100))
685 xtal = 2700;
686 else if ((xtal > 14200) && (xtal < 14400))
687 xtal = 1432;
688 else if ((xtal > 29400) && (xtal < 29600))
689 xtal = 2950;
690 else {
691 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
692 return -1;
693 }
694
695 tmp = INPLL(M_SPLL_REF_FB_DIV);
696 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
697
698 Ns = (tmp & 0xff0000) >> 16;
699 Nm = (tmp & 0xff00) >> 8;
700 M = (tmp & 0xff);
701 sclk = round_div((2 * Ns * xtal), (2 * M));
702 mclk = round_div((2 * Nm * xtal), (2 * M));
703
704 /* we're done, hopefully these are sane values */
705 rinfo->pll.ref_clk = xtal;
706 rinfo->pll.ref_div = ref_div;
707 rinfo->pll.sclk = sclk;
708 rinfo->pll.mclk = mclk;
709
710 return 0;
711 }
712
713 /*
714 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
715 */
716 static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
717 {
718 /*
719 * In the case nothing works, these are defaults; they are mostly
720 * incomplete, however. It does provide ppll_max and _min values
721 * even for most other methods, however.
722 */
723 switch (rinfo->chipset) {
724 case PCI_DEVICE_ID_ATI_RADEON_QW:
725 case PCI_DEVICE_ID_ATI_RADEON_QX:
726 rinfo->pll.ppll_max = 35000;
727 rinfo->pll.ppll_min = 12000;
728 rinfo->pll.mclk = 23000;
729 rinfo->pll.sclk = 23000;
730 rinfo->pll.ref_clk = 2700;
731 break;
732 case PCI_DEVICE_ID_ATI_RADEON_QL:
733 case PCI_DEVICE_ID_ATI_RADEON_QN:
734 case PCI_DEVICE_ID_ATI_RADEON_QO:
735 case PCI_DEVICE_ID_ATI_RADEON_Ql:
736 case PCI_DEVICE_ID_ATI_RADEON_BB:
737 rinfo->pll.ppll_max = 35000;
738 rinfo->pll.ppll_min = 12000;
739 rinfo->pll.mclk = 27500;
740 rinfo->pll.sclk = 27500;
741 rinfo->pll.ref_clk = 2700;
742 break;
743 case PCI_DEVICE_ID_ATI_RADEON_Id:
744 case PCI_DEVICE_ID_ATI_RADEON_Ie:
745 case PCI_DEVICE_ID_ATI_RADEON_If:
746 case PCI_DEVICE_ID_ATI_RADEON_Ig:
747 rinfo->pll.ppll_max = 35000;
748 rinfo->pll.ppll_min = 12000;
749 rinfo->pll.mclk = 25000;
750 rinfo->pll.sclk = 25000;
751 rinfo->pll.ref_clk = 2700;
752 break;
753 case PCI_DEVICE_ID_ATI_RADEON_ND:
754 case PCI_DEVICE_ID_ATI_RADEON_NE:
755 case PCI_DEVICE_ID_ATI_RADEON_NF:
756 case PCI_DEVICE_ID_ATI_RADEON_NG:
757 rinfo->pll.ppll_max = 40000;
758 rinfo->pll.ppll_min = 20000;
759 rinfo->pll.mclk = 27000;
760 rinfo->pll.sclk = 27000;
761 rinfo->pll.ref_clk = 2700;
762 break;
763 case PCI_DEVICE_ID_ATI_RADEON_QD:
764 case PCI_DEVICE_ID_ATI_RADEON_QE:
765 case PCI_DEVICE_ID_ATI_RADEON_QF:
766 case PCI_DEVICE_ID_ATI_RADEON_QG:
767 default:
768 rinfo->pll.ppll_max = 35000;
769 rinfo->pll.ppll_min = 12000;
770 rinfo->pll.mclk = 16600;
771 rinfo->pll.sclk = 16600;
772 rinfo->pll.ref_clk = 2700;
773 break;
774 }
775 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
776
777
778 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
779 /*
780 * Retrieve PLL infos from Open Firmware first
781 */
782 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
783 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
784 goto found;
785 }
786 #endif /* CONFIG_PPC || CONFIG_SPARC */
787
788 /*
789 * Check out if we have an X86 which gave us some PLL informations
790 * and if yes, retrieve them
791 */
792 if (!force_measure_pll && rinfo->bios_seg) {
793 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
794
795 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
796 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
797 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
798 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
799 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
800 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
801
802 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
803 goto found;
804 }
805
806 /*
807 * We didn't get PLL parameters from either OF or BIOS, we try to
808 * probe them
809 */
810 if (radeon_probe_pll_params(rinfo) == 0) {
811 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
812 goto found;
813 }
814
815 /*
816 * Fall back to already-set defaults...
817 */
818 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
819
820 found:
821 /*
822 * Some methods fail to retrieve SCLK and MCLK values, we apply default
823 * settings in this case (200Mhz). If that really happens often, we
824 * could fetch from registers instead...
825 */
826 if (rinfo->pll.mclk == 0)
827 rinfo->pll.mclk = 20000;
828 if (rinfo->pll.sclk == 0)
829 rinfo->pll.sclk = 20000;
830
831 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
832 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
833 rinfo->pll.ref_div,
834 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
835 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
836 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
837 }
838
839 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
840 {
841 struct radeonfb_info *rinfo = info->par;
842 struct fb_var_screeninfo v;
843 int nom, den;
844 unsigned int pitch;
845
846 if (radeon_match_mode(rinfo, &v, var))
847 return -EINVAL;
848
849 switch (v.bits_per_pixel) {
850 case 0 ... 8:
851 v.bits_per_pixel = 8;
852 break;
853 case 9 ... 16:
854 v.bits_per_pixel = 16;
855 break;
856 case 17 ... 24:
857 #if 0 /* Doesn't seem to work */
858 v.bits_per_pixel = 24;
859 break;
860 #endif
861 return -EINVAL;
862 case 25 ... 32:
863 v.bits_per_pixel = 32;
864 break;
865 default:
866 return -EINVAL;
867 }
868
869 switch (var_to_depth(&v)) {
870 case 8:
871 nom = den = 1;
872 v.red.offset = v.green.offset = v.blue.offset = 0;
873 v.red.length = v.green.length = v.blue.length = 8;
874 v.transp.offset = v.transp.length = 0;
875 break;
876 case 15:
877 nom = 2;
878 den = 1;
879 v.red.offset = 10;
880 v.green.offset = 5;
881 v.blue.offset = 0;
882 v.red.length = v.green.length = v.blue.length = 5;
883 v.transp.offset = v.transp.length = 0;
884 break;
885 case 16:
886 nom = 2;
887 den = 1;
888 v.red.offset = 11;
889 v.green.offset = 5;
890 v.blue.offset = 0;
891 v.red.length = 5;
892 v.green.length = 6;
893 v.blue.length = 5;
894 v.transp.offset = v.transp.length = 0;
895 break;
896 case 24:
897 nom = 4;
898 den = 1;
899 v.red.offset = 16;
900 v.green.offset = 8;
901 v.blue.offset = 0;
902 v.red.length = v.blue.length = v.green.length = 8;
903 v.transp.offset = v.transp.length = 0;
904 break;
905 case 32:
906 nom = 4;
907 den = 1;
908 v.red.offset = 16;
909 v.green.offset = 8;
910 v.blue.offset = 0;
911 v.red.length = v.blue.length = v.green.length = 8;
912 v.transp.offset = 24;
913 v.transp.length = 8;
914 break;
915 default:
916 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
917 var->xres, var->yres, var->bits_per_pixel);
918 return -EINVAL;
919 }
920
921 if (v.yres_virtual < v.yres)
922 v.yres_virtual = v.yres;
923 if (v.xres_virtual < v.xres)
924 v.xres_virtual = v.xres;
925
926
927 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
928 * with some panels, though I don't quite like this solution
929 */
930 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
931 v.xres_virtual = v.xres_virtual & ~7ul;
932 } else {
933 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
934 & ~(0x3f)) >> 6;
935 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
936 }
937
938 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
939 return -EINVAL;
940
941 if (v.xres_virtual < v.xres)
942 v.xres = v.xres_virtual;
943
944 if (v.xoffset > v.xres_virtual - v.xres)
945 v.xoffset = v.xres_virtual - v.xres - 1;
946
947 if (v.yoffset > v.yres_virtual - v.yres)
948 v.yoffset = v.yres_virtual - v.yres - 1;
949
950 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
951 v.transp.offset = v.transp.length =
952 v.transp.msb_right = 0;
953
954 memcpy(var, &v, sizeof(v));
955
956 return 0;
957 }
958
959
960 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
961 struct fb_info *info)
962 {
963 struct radeonfb_info *rinfo = info->par;
964
965 if ((var->xoffset + info->var.xres > info->var.xres_virtual)
966 || (var->yoffset + info->var.yres > info->var.yres_virtual))
967 return -EINVAL;
968
969 if (rinfo->asleep)
970 return 0;
971
972 radeon_fifo_wait(2);
973 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
974 var->xoffset * info->var.bits_per_pixel / 8) & ~7);
975 return 0;
976 }
977
978
979 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
980 unsigned long arg)
981 {
982 struct radeonfb_info *rinfo = info->par;
983 unsigned int tmp;
984 u32 value = 0;
985 int rc;
986
987 switch (cmd) {
988 /*
989 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
990 * and do something better using 2nd CRTC instead of just hackish
991 * routing to second output
992 */
993 case FBIO_RADEON_SET_MIRROR:
994 if (!rinfo->is_mobility)
995 return -EINVAL;
996
997 rc = get_user(value, (__u32 __user *)arg);
998
999 if (rc)
1000 return rc;
1001
1002 radeon_fifo_wait(2);
1003 if (value & 0x01) {
1004 tmp = INREG(LVDS_GEN_CNTL);
1005
1006 tmp |= (LVDS_ON | LVDS_BLON);
1007 } else {
1008 tmp = INREG(LVDS_GEN_CNTL);
1009
1010 tmp &= ~(LVDS_ON | LVDS_BLON);
1011 }
1012
1013 OUTREG(LVDS_GEN_CNTL, tmp);
1014
1015 if (value & 0x02) {
1016 tmp = INREG(CRTC_EXT_CNTL);
1017 tmp |= CRTC_CRT_ON;
1018
1019 mirror = 1;
1020 } else {
1021 tmp = INREG(CRTC_EXT_CNTL);
1022 tmp &= ~CRTC_CRT_ON;
1023
1024 mirror = 0;
1025 }
1026
1027 OUTREG(CRTC_EXT_CNTL, tmp);
1028
1029 return 0;
1030 case FBIO_RADEON_GET_MIRROR:
1031 if (!rinfo->is_mobility)
1032 return -EINVAL;
1033
1034 tmp = INREG(LVDS_GEN_CNTL);
1035 if ((LVDS_ON | LVDS_BLON) & tmp)
1036 value |= 0x01;
1037
1038 tmp = INREG(CRTC_EXT_CNTL);
1039 if (CRTC_CRT_ON & tmp)
1040 value |= 0x02;
1041
1042 return put_user(value, (__u32 __user *)arg);
1043 default:
1044 return -EINVAL;
1045 }
1046
1047 return -EINVAL;
1048 }
1049
1050
1051 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
1052 {
1053 u32 val;
1054 u32 tmp_pix_clks;
1055 int unblank = 0;
1056
1057 if (rinfo->lock_blank)
1058 return 0;
1059
1060 radeon_engine_idle();
1061
1062 val = INREG(CRTC_EXT_CNTL);
1063 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1064 CRTC_VSYNC_DIS);
1065 switch (blank) {
1066 case FB_BLANK_VSYNC_SUSPEND:
1067 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1068 break;
1069 case FB_BLANK_HSYNC_SUSPEND:
1070 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1071 break;
1072 case FB_BLANK_POWERDOWN:
1073 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1074 CRTC_HSYNC_DIS);
1075 break;
1076 case FB_BLANK_NORMAL:
1077 val |= CRTC_DISPLAY_DIS;
1078 break;
1079 case FB_BLANK_UNBLANK:
1080 default:
1081 unblank = 1;
1082 }
1083 OUTREG(CRTC_EXT_CNTL, val);
1084
1085
1086 switch (rinfo->mon1_type) {
1087 case MT_DFP:
1088 if (unblank)
1089 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
1090 ~(FP_FPON | FP_TMDS_EN));
1091 else {
1092 if (mode_switch || blank == FB_BLANK_NORMAL)
1093 break;
1094 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
1095 }
1096 break;
1097 case MT_LCD:
1098 del_timer_sync(&rinfo->lvds_timer);
1099 val = INREG(LVDS_GEN_CNTL);
1100 if (unblank) {
1101 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
1102 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
1103 & (LVDS_DIGON | LVDS_BL_MOD_EN));
1104 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
1105 OUTREG(LVDS_GEN_CNTL, target_val);
1106 else if ((val ^ target_val) != 0) {
1107 OUTREG(LVDS_GEN_CNTL, target_val
1108 & ~(LVDS_ON | LVDS_BL_MOD_EN));
1109 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1110 rinfo->init_state.lvds_gen_cntl |=
1111 target_val & LVDS_STATE_MASK;
1112 if (mode_switch) {
1113 radeon_msleep(rinfo->panel_info.pwr_delay);
1114 OUTREG(LVDS_GEN_CNTL, target_val);
1115 }
1116 else {
1117 rinfo->pending_lvds_gen_cntl = target_val;
1118 mod_timer(&rinfo->lvds_timer,
1119 jiffies +
1120 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1121 }
1122 }
1123 } else {
1124 val |= LVDS_DISPLAY_DIS;
1125 OUTREG(LVDS_GEN_CNTL, val);
1126
1127 /* We don't do a full switch-off on a simple mode switch */
1128 if (mode_switch || blank == FB_BLANK_NORMAL)
1129 break;
1130
1131 /* Asic bug, when turning off LVDS_ON, we have to make sure
1132 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1133 */
1134 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1135 if (rinfo->is_mobility || rinfo->is_IGP)
1136 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1137 val &= ~(LVDS_BL_MOD_EN);
1138 OUTREG(LVDS_GEN_CNTL, val);
1139 udelay(100);
1140 val &= ~(LVDS_ON | LVDS_EN);
1141 OUTREG(LVDS_GEN_CNTL, val);
1142 val &= ~LVDS_DIGON;
1143 rinfo->pending_lvds_gen_cntl = val;
1144 mod_timer(&rinfo->lvds_timer,
1145 jiffies +
1146 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1147 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1148 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1149 if (rinfo->is_mobility || rinfo->is_IGP)
1150 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1151 }
1152 break;
1153 case MT_CRT:
1154 // todo: powerdown DAC
1155 default:
1156 break;
1157 }
1158
1159 return 0;
1160 }
1161
1162 static int radeonfb_blank (int blank, struct fb_info *info)
1163 {
1164 struct radeonfb_info *rinfo = info->par;
1165
1166 if (rinfo->asleep)
1167 return 0;
1168
1169 return radeon_screen_blank(rinfo, blank, 0);
1170 }
1171
1172 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1173 unsigned blue, unsigned transp,
1174 struct radeonfb_info *rinfo)
1175 {
1176 u32 pindex;
1177 unsigned int i;
1178
1179
1180 if (regno > 255)
1181 return -EINVAL;
1182
1183 red >>= 8;
1184 green >>= 8;
1185 blue >>= 8;
1186 rinfo->palette[regno].red = red;
1187 rinfo->palette[regno].green = green;
1188 rinfo->palette[regno].blue = blue;
1189
1190 /* default */
1191 pindex = regno;
1192
1193 if (!rinfo->asleep) {
1194 radeon_fifo_wait(9);
1195
1196 if (rinfo->bpp == 16) {
1197 pindex = regno * 8;
1198
1199 if (rinfo->depth == 16 && regno > 63)
1200 return -EINVAL;
1201 if (rinfo->depth == 15 && regno > 31)
1202 return -EINVAL;
1203
1204 /* For 565, the green component is mixed one order
1205 * below
1206 */
1207 if (rinfo->depth == 16) {
1208 OUTREG(PALETTE_INDEX, pindex>>1);
1209 OUTREG(PALETTE_DATA,
1210 (rinfo->palette[regno>>1].red << 16) |
1211 (green << 8) |
1212 (rinfo->palette[regno>>1].blue));
1213 green = rinfo->palette[regno<<1].green;
1214 }
1215 }
1216
1217 if (rinfo->depth != 16 || regno < 32) {
1218 OUTREG(PALETTE_INDEX, pindex);
1219 OUTREG(PALETTE_DATA, (red << 16) |
1220 (green << 8) | blue);
1221 }
1222 }
1223 if (regno < 16) {
1224 u32 *pal = rinfo->info->pseudo_palette;
1225 switch (rinfo->depth) {
1226 case 15:
1227 pal[regno] = (regno << 10) | (regno << 5) | regno;
1228 break;
1229 case 16:
1230 pal[regno] = (regno << 11) | (regno << 5) | regno;
1231 break;
1232 case 24:
1233 pal[regno] = (regno << 16) | (regno << 8) | regno;
1234 break;
1235 case 32:
1236 i = (regno << 8) | regno;
1237 pal[regno] = (i << 16) | i;
1238 break;
1239 }
1240 }
1241 return 0;
1242 }
1243
1244 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1245 unsigned blue, unsigned transp,
1246 struct fb_info *info)
1247 {
1248 struct radeonfb_info *rinfo = info->par;
1249 u32 dac_cntl2, vclk_cntl = 0;
1250 int rc;
1251
1252 if (!rinfo->asleep) {
1253 if (rinfo->is_mobility) {
1254 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1255 OUTPLL(VCLK_ECP_CNTL,
1256 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1257 }
1258
1259 /* Make sure we are on first palette */
1260 if (rinfo->has_CRTC2) {
1261 dac_cntl2 = INREG(DAC_CNTL2);
1262 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1263 OUTREG(DAC_CNTL2, dac_cntl2);
1264 }
1265 }
1266
1267 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1268
1269 if (!rinfo->asleep && rinfo->is_mobility)
1270 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1271
1272 return rc;
1273 }
1274
1275 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1276 {
1277 struct radeonfb_info *rinfo = info->par;
1278 u16 *red, *green, *blue, *transp;
1279 u32 dac_cntl2, vclk_cntl = 0;
1280 int i, start, rc = 0;
1281
1282 if (!rinfo->asleep) {
1283 if (rinfo->is_mobility) {
1284 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1285 OUTPLL(VCLK_ECP_CNTL,
1286 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1287 }
1288
1289 /* Make sure we are on first palette */
1290 if (rinfo->has_CRTC2) {
1291 dac_cntl2 = INREG(DAC_CNTL2);
1292 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1293 OUTREG(DAC_CNTL2, dac_cntl2);
1294 }
1295 }
1296
1297 red = cmap->red;
1298 green = cmap->green;
1299 blue = cmap->blue;
1300 transp = cmap->transp;
1301 start = cmap->start;
1302
1303 for (i = 0; i < cmap->len; i++) {
1304 u_int hred, hgreen, hblue, htransp = 0xffff;
1305
1306 hred = *red++;
1307 hgreen = *green++;
1308 hblue = *blue++;
1309 if (transp)
1310 htransp = *transp++;
1311 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1312 rinfo);
1313 if (rc)
1314 break;
1315 }
1316
1317 if (!rinfo->asleep && rinfo->is_mobility)
1318 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1319
1320 return rc;
1321 }
1322
1323 static void radeon_save_state (struct radeonfb_info *rinfo,
1324 struct radeon_regs *save)
1325 {
1326 /* CRTC regs */
1327 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1328 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1329 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1330 save->dac_cntl = INREG(DAC_CNTL);
1331 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1332 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1333 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1334 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1335 save->crtc_pitch = INREG(CRTC_PITCH);
1336 save->surface_cntl = INREG(SURFACE_CNTL);
1337
1338 /* FP regs */
1339 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1340 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1341 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1342 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1343 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1344 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1345 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1346 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1347 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1348 save->tmds_crc = INREG(TMDS_CRC);
1349 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1350 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1351
1352 /* PLL regs */
1353 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1354 radeon_pll_errata_after_index(rinfo);
1355 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1356 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1357 }
1358
1359
1360 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1361 {
1362 int i;
1363
1364 radeon_fifo_wait(20);
1365
1366 /* Workaround from XFree */
1367 if (rinfo->is_mobility) {
1368 /* A temporal workaround for the occasional blanking on certain laptop
1369 * panels. This appears to related to the PLL divider registers
1370 * (fail to lock?). It occurs even when all dividers are the same
1371 * with their old settings. In this case we really don't need to
1372 * fiddle with PLL registers. By doing this we can avoid the blanking
1373 * problem with some panels.
1374 */
1375 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1376 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1377 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1378 /* We still have to force a switch to selected PPLL div thanks to
1379 * an XFree86 driver bug which will switch it away in some cases
1380 * even when using UseFDev */
1381 OUTREGP(CLOCK_CNTL_INDEX,
1382 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1383 ~PPLL_DIV_SEL_MASK);
1384 radeon_pll_errata_after_index(rinfo);
1385 radeon_pll_errata_after_data(rinfo);
1386 return;
1387 }
1388 }
1389
1390 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1391 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1392
1393 /* Reset PPLL & enable atomic update */
1394 OUTPLLP(PPLL_CNTL,
1395 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1396 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1397
1398 /* Switch to selected PPLL divider */
1399 OUTREGP(CLOCK_CNTL_INDEX,
1400 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1401 ~PPLL_DIV_SEL_MASK);
1402 radeon_pll_errata_after_index(rinfo);
1403 radeon_pll_errata_after_data(rinfo);
1404
1405 /* Set PPLL ref. div */
1406 if (IS_R300_VARIANT(rinfo) ||
1407 rinfo->family == CHIP_FAMILY_RS300 ||
1408 rinfo->family == CHIP_FAMILY_RS400 ||
1409 rinfo->family == CHIP_FAMILY_RS480) {
1410 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1411 /* When restoring console mode, use saved PPLL_REF_DIV
1412 * setting.
1413 */
1414 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1415 } else {
1416 /* R300 uses ref_div_acc field as real ref divider */
1417 OUTPLLP(PPLL_REF_DIV,
1418 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1419 ~R300_PPLL_REF_DIV_ACC_MASK);
1420 }
1421 } else
1422 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1423
1424 /* Set PPLL divider 3 & post divider*/
1425 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1426 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1427
1428 /* Write update */
1429 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1430 ;
1431 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1432
1433 /* Wait read update complete */
1434 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1435 the cause yet, but this workaround will mask the problem for now.
1436 Other chips usually will pass at the very first test, so the
1437 workaround shouldn't have any effect on them. */
1438 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1439 ;
1440
1441 OUTPLL(HTOTAL_CNTL, 0);
1442
1443 /* Clear reset & atomic update */
1444 OUTPLLP(PPLL_CNTL, 0,
1445 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1446
1447 /* We may want some locking ... oh well */
1448 radeon_msleep(5);
1449
1450 /* Switch back VCLK source to PPLL */
1451 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1452 }
1453
1454 /*
1455 * Timer function for delayed LVDS panel power up/down
1456 */
1457 static void radeon_lvds_timer_func(unsigned long data)
1458 {
1459 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1460
1461 radeon_engine_idle();
1462
1463 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1464 }
1465
1466 /*
1467 * Apply a video mode. This will apply the whole register set, including
1468 * the PLL registers, to the card
1469 */
1470 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1471 int regs_only)
1472 {
1473 int i;
1474 int primary_mon = PRIMARY_MONITOR(rinfo);
1475
1476 if (nomodeset)
1477 return;
1478
1479 if (!regs_only)
1480 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1481
1482 radeon_fifo_wait(31);
1483 for (i=0; i<10; i++)
1484 OUTREG(common_regs[i].reg, common_regs[i].val);
1485
1486 /* Apply surface registers */
1487 for (i=0; i<8; i++) {
1488 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1489 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1490 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1491 }
1492
1493 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1494 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1495 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1496 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1497 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1498 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1499 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1500 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1501 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1502 OUTREG(CRTC_OFFSET, 0);
1503 OUTREG(CRTC_OFFSET_CNTL, 0);
1504 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1505 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1506
1507 radeon_write_pll_regs(rinfo, mode);
1508
1509 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1510 radeon_fifo_wait(10);
1511 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1512 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1513 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1514 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1515 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1516 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1517 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1518 OUTREG(TMDS_CRC, mode->tmds_crc);
1519 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1520 }
1521
1522 if (!regs_only)
1523 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1524
1525 radeon_fifo_wait(2);
1526 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1527
1528 return;
1529 }
1530
1531 /*
1532 * Calculate the PLL values for a given mode
1533 */
1534 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1535 unsigned long freq)
1536 {
1537 static const struct {
1538 int divider;
1539 int bitvalue;
1540 } *post_div,
1541 post_divs[] = {
1542 { 1, 0 },
1543 { 2, 1 },
1544 { 4, 2 },
1545 { 8, 3 },
1546 { 3, 4 },
1547 { 16, 5 },
1548 { 6, 6 },
1549 { 12, 7 },
1550 { 0, 0 },
1551 };
1552 int fb_div, pll_output_freq = 0;
1553 int uses_dvo = 0;
1554
1555 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1556 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1557 * recent than an r(v)100...
1558 */
1559 #if 1
1560 /* XXX I had reports of flicker happening with the cinema display
1561 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1562 * this case. This could just be a bandwidth calculation issue, I
1563 * haven't implemented the bandwidth code yet, but in the meantime,
1564 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1565 * I haven't seen a case were were absolutely needed an odd PLL
1566 * divider. I'll find a better fix once I have more infos on the
1567 * real cause of the problem.
1568 */
1569 while (rinfo->has_CRTC2) {
1570 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1571 u32 disp_output_cntl;
1572 int source;
1573
1574 /* FP2 path not enabled */
1575 if ((fp2_gen_cntl & FP2_ON) == 0)
1576 break;
1577 /* Not all chip revs have the same format for this register,
1578 * extract the source selection
1579 */
1580 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1581 source = (fp2_gen_cntl >> 10) & 0x3;
1582 /* sourced from transform unit, check for transform unit
1583 * own source
1584 */
1585 if (source == 3) {
1586 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1587 source = (disp_output_cntl >> 12) & 0x3;
1588 }
1589 } else
1590 source = (fp2_gen_cntl >> 13) & 0x1;
1591 /* sourced from CRTC2 -> exit */
1592 if (source == 1)
1593 break;
1594
1595 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1596 uses_dvo = 1;
1597 break;
1598 }
1599 #else
1600 uses_dvo = 1;
1601 #endif
1602 if (freq > rinfo->pll.ppll_max)
1603 freq = rinfo->pll.ppll_max;
1604 if (freq*12 < rinfo->pll.ppll_min)
1605 freq = rinfo->pll.ppll_min / 12;
1606 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1607 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1608
1609 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1610 pll_output_freq = post_div->divider * freq;
1611 /* If we output to the DVO port (external TMDS), we don't allow an
1612 * odd PLL divider as those aren't supported on this path
1613 */
1614 if (uses_dvo && (post_div->divider & 1))
1615 continue;
1616 if (pll_output_freq >= rinfo->pll.ppll_min &&
1617 pll_output_freq <= rinfo->pll.ppll_max)
1618 break;
1619 }
1620
1621 /* If we fall through the bottom, try the "default value"
1622 given by the terminal post_div->bitvalue */
1623 if ( !post_div->divider ) {
1624 post_div = &post_divs[post_div->bitvalue];
1625 pll_output_freq = post_div->divider * freq;
1626 }
1627 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1628 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1629 pll_output_freq);
1630
1631 /* If we fall through the bottom, try the "default value"
1632 given by the terminal post_div->bitvalue */
1633 if ( !post_div->divider ) {
1634 post_div = &post_divs[post_div->bitvalue];
1635 pll_output_freq = post_div->divider * freq;
1636 }
1637 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1638 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1639 pll_output_freq);
1640
1641 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1642 rinfo->pll.ref_clk);
1643 regs->ppll_ref_div = rinfo->pll.ref_div;
1644 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1645
1646 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1647 pr_debug("fb_div = 0x%x\n", fb_div);
1648 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1649 }
1650
1651 static int radeonfb_set_par(struct fb_info *info)
1652 {
1653 struct radeonfb_info *rinfo = info->par;
1654 struct fb_var_screeninfo *mode = &info->var;
1655 struct radeon_regs *newmode;
1656 int hTotal, vTotal, hSyncStart, hSyncEnd,
1657 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1658 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1659 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1660 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1661 int i, freq;
1662 int format = 0;
1663 int nopllcalc = 0;
1664 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1665 int primary_mon = PRIMARY_MONITOR(rinfo);
1666 int depth = var_to_depth(mode);
1667 int use_rmx = 0;
1668
1669 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1670 if (!newmode)
1671 return -ENOMEM;
1672
1673 /* We always want engine to be idle on a mode switch, even
1674 * if we won't actually change the mode
1675 */
1676 radeon_engine_idle();
1677
1678 hSyncStart = mode->xres + mode->right_margin;
1679 hSyncEnd = hSyncStart + mode->hsync_len;
1680 hTotal = hSyncEnd + mode->left_margin;
1681
1682 vSyncStart = mode->yres + mode->lower_margin;
1683 vSyncEnd = vSyncStart + mode->vsync_len;
1684 vTotal = vSyncEnd + mode->upper_margin;
1685 pixClock = mode->pixclock;
1686
1687 sync = mode->sync;
1688 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1689 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1690
1691 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1692 if (rinfo->panel_info.xres < mode->xres)
1693 mode->xres = rinfo->panel_info.xres;
1694 if (rinfo->panel_info.yres < mode->yres)
1695 mode->yres = rinfo->panel_info.yres;
1696
1697 hTotal = mode->xres + rinfo->panel_info.hblank;
1698 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1699 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1700
1701 vTotal = mode->yres + rinfo->panel_info.vblank;
1702 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1703 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1704
1705 h_sync_pol = !rinfo->panel_info.hAct_high;
1706 v_sync_pol = !rinfo->panel_info.vAct_high;
1707
1708 pixClock = 100000000 / rinfo->panel_info.clock;
1709
1710 if (rinfo->panel_info.use_bios_dividers) {
1711 nopllcalc = 1;
1712 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1713 (rinfo->panel_info.post_divider << 16);
1714 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1715 }
1716 }
1717 dotClock = 1000000000 / pixClock;
1718 freq = dotClock / 10; /* x100 */
1719
1720 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1721 hSyncStart, hSyncEnd, hTotal);
1722 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1723 vSyncStart, vSyncEnd, vTotal);
1724
1725 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1726 vsync_wid = vSyncEnd - vSyncStart;
1727 if (hsync_wid == 0)
1728 hsync_wid = 1;
1729 else if (hsync_wid > 0x3f) /* max */
1730 hsync_wid = 0x3f;
1731
1732 if (vsync_wid == 0)
1733 vsync_wid = 1;
1734 else if (vsync_wid > 0x1f) /* max */
1735 vsync_wid = 0x1f;
1736
1737 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1738 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1739
1740 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1741
1742 format = radeon_get_dstbpp(depth);
1743 bytpp = mode->bits_per_pixel >> 3;
1744
1745 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1746 hsync_fudge = hsync_fudge_fp[format-1];
1747 else
1748 hsync_fudge = hsync_adj_tab[format-1];
1749
1750 hsync_start = hSyncStart - 8 + hsync_fudge;
1751
1752 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1753 (format << 8);
1754
1755 /* Clear auto-center etc... */
1756 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1757 newmode->crtc_more_cntl &= 0xfffffff0;
1758
1759 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1760 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1761 if (mirror)
1762 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1763
1764 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1765 CRTC_INTERLACE_EN);
1766 } else {
1767 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1768 CRTC_CRT_ON;
1769 }
1770
1771 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1772 DAC_8BIT_EN;
1773
1774 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1775 (((mode->xres / 8) - 1) << 16));
1776
1777 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1778 (hsync_wid << 16) | (h_sync_pol << 23));
1779
1780 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1781 ((mode->yres - 1) << 16);
1782
1783 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1784 (vsync_wid << 16) | (v_sync_pol << 23));
1785
1786 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1787 /* We first calculate the engine pitch */
1788 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1789 & ~(0x3f)) >> 6;
1790
1791 /* Then, re-multiply it to get the CRTC pitch */
1792 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1793 } else
1794 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1795
1796 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1797
1798 /*
1799 * It looks like recent chips have a problem with SURFACE_CNTL,
1800 * setting SURF_TRANSLATION_DIS completely disables the
1801 * swapper as well, so we leave it unset now.
1802 */
1803 newmode->surface_cntl = 0;
1804
1805 #if defined(__BIG_ENDIAN)
1806
1807 /* Setup swapping on both apertures, though we currently
1808 * only use aperture 0, enabling swapper on aperture 1
1809 * won't harm
1810 */
1811 switch (mode->bits_per_pixel) {
1812 case 16:
1813 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1814 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1815 break;
1816 case 24:
1817 case 32:
1818 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1819 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1820 break;
1821 }
1822 #endif
1823
1824 /* Clear surface registers */
1825 for (i=0; i<8; i++) {
1826 newmode->surf_lower_bound[i] = 0;
1827 newmode->surf_upper_bound[i] = 0x1f;
1828 newmode->surf_info[i] = 0;
1829 }
1830
1831 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1832 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1833 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1834 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1835
1836 rinfo->bpp = mode->bits_per_pixel;
1837 rinfo->depth = depth;
1838
1839 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1840 pr_debug("freq = %lu\n", (unsigned long)freq);
1841
1842 /* We use PPLL_DIV_3 */
1843 newmode->clk_cntl_index = 0x300;
1844
1845 /* Calculate PPLL value if necessary */
1846 if (!nopllcalc)
1847 radeon_calc_pll_regs(rinfo, newmode, freq);
1848
1849 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1850
1851 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1852 unsigned int hRatio, vRatio;
1853
1854 if (mode->xres > rinfo->panel_info.xres)
1855 mode->xres = rinfo->panel_info.xres;
1856 if (mode->yres > rinfo->panel_info.yres)
1857 mode->yres = rinfo->panel_info.yres;
1858
1859 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1860 << HORZ_PANEL_SHIFT);
1861 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1862 << VERT_PANEL_SHIFT);
1863
1864 if (mode->xres != rinfo->panel_info.xres) {
1865 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1866 rinfo->panel_info.xres);
1867 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1868 (newmode->fp_horz_stretch &
1869 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1870 HORZ_AUTO_RATIO_INC)));
1871 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1872 HORZ_STRETCH_ENABLE);
1873 use_rmx = 1;
1874 }
1875 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1876
1877 if (mode->yres != rinfo->panel_info.yres) {
1878 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1879 rinfo->panel_info.yres);
1880 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1881 (newmode->fp_vert_stretch &
1882 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1883 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1884 VERT_STRETCH_ENABLE);
1885 use_rmx = 1;
1886 }
1887 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1888
1889 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1890 ~(FP_SEL_CRTC2 |
1891 FP_RMX_HVSYNC_CONTROL_EN |
1892 FP_DFP_SYNC_SEL |
1893 FP_CRT_SYNC_SEL |
1894 FP_CRTC_LOCK_8DOT |
1895 FP_USE_SHADOW_EN |
1896 FP_CRTC_USE_SHADOW_VEND |
1897 FP_CRT_SYNC_ALT));
1898
1899 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1900 FP_CRTC_DONT_SHADOW_HEND |
1901 FP_PANEL_FORMAT);
1902
1903 if (IS_R300_VARIANT(rinfo) ||
1904 (rinfo->family == CHIP_FAMILY_R200)) {
1905 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1906 if (use_rmx)
1907 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1908 else
1909 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1910 } else
1911 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1912
1913 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1914 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1915 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1916 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1917
1918 if (primary_mon == MT_LCD) {
1919 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1920 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1921 } else {
1922 /* DFP */
1923 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1924 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1925 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1926 if (IS_R300_VARIANT(rinfo) ||
1927 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1928 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1929 else
1930 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1931 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1932 }
1933
1934 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1935 (((mode->xres / 8) - 1) << 16));
1936 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1937 ((mode->yres - 1) << 16);
1938 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1939 (hsync_wid << 16) | (h_sync_pol << 23));
1940 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1941 (vsync_wid << 16) | (v_sync_pol << 23));
1942 }
1943
1944 /* do it! */
1945 if (!rinfo->asleep) {
1946 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1947 radeon_write_mode (rinfo, newmode, 0);
1948 /* (re)initialize the engine */
1949 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1950 radeonfb_engine_init (rinfo);
1951 }
1952 /* Update fix */
1953 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1954 info->fix.line_length = rinfo->pitch*64;
1955 else
1956 info->fix.line_length = mode->xres_virtual
1957 * ((mode->bits_per_pixel + 1) / 8);
1958 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1959 : FB_VISUAL_DIRECTCOLOR;
1960
1961 #ifdef CONFIG_BOOTX_TEXT
1962 /* Update debug text engine */
1963 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1964 rinfo->depth, info->fix.line_length);
1965 #endif
1966
1967 kfree(newmode);
1968 return 0;
1969 }
1970
1971
1972 static struct fb_ops radeonfb_ops = {
1973 .owner = THIS_MODULE,
1974 .fb_check_var = radeonfb_check_var,
1975 .fb_set_par = radeonfb_set_par,
1976 .fb_setcolreg = radeonfb_setcolreg,
1977 .fb_setcmap = radeonfb_setcmap,
1978 .fb_pan_display = radeonfb_pan_display,
1979 .fb_blank = radeonfb_blank,
1980 .fb_ioctl = radeonfb_ioctl,
1981 .fb_sync = radeonfb_sync,
1982 .fb_fillrect = radeonfb_fillrect,
1983 .fb_copyarea = radeonfb_copyarea,
1984 .fb_imageblit = radeonfb_imageblit,
1985 };
1986
1987
1988 static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1989 {
1990 struct fb_info *info = rinfo->info;
1991
1992 info->par = rinfo;
1993 info->pseudo_palette = rinfo->pseudo_palette;
1994 info->flags = FBINFO_DEFAULT
1995 | FBINFO_HWACCEL_COPYAREA
1996 | FBINFO_HWACCEL_FILLRECT
1997 | FBINFO_HWACCEL_XPAN
1998 | FBINFO_HWACCEL_YPAN;
1999 info->fbops = &radeonfb_ops;
2000 info->screen_base = rinfo->fb_base;
2001 info->screen_size = rinfo->mapped_vram;
2002 /* Fill fix common fields */
2003 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2004 info->fix.smem_start = rinfo->fb_base_phys;
2005 info->fix.smem_len = rinfo->video_ram;
2006 info->fix.type = FB_TYPE_PACKED_PIXELS;
2007 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2008 info->fix.xpanstep = 8;
2009 info->fix.ypanstep = 1;
2010 info->fix.ywrapstep = 0;
2011 info->fix.type_aux = 0;
2012 info->fix.mmio_start = rinfo->mmio_base_phys;
2013 info->fix.mmio_len = RADEON_REGSIZE;
2014 info->fix.accel = FB_ACCEL_ATI_RADEON;
2015
2016 fb_alloc_cmap(&info->cmap, 256, 0);
2017
2018 if (noaccel)
2019 info->flags |= FBINFO_HWACCEL_DISABLED;
2020
2021 return 0;
2022 }
2023
2024 /*
2025 * This reconfigure the card's internal memory map. In theory, we'd like
2026 * to setup the card's memory at the same address as it's PCI bus address,
2027 * and the AGP aperture right after that so that system RAM on 32 bits
2028 * machines at least, is directly accessible. However, doing so would
2029 * conflict with the current XFree drivers...
2030 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2031 * on the proper way to set this up and duplicate this here. In the meantime,
2032 * I put the card's memory at 0 in card space and AGP at some random high
2033 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
2034 */
2035 #ifdef CONFIG_PPC
2036 #undef SET_MC_FB_FROM_APERTURE
2037 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2038 {
2039 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
2040 u32 save_crtc_ext_cntl;
2041 u32 aper_base, aper_size;
2042 u32 agp_base;
2043
2044 /* First, we disable display to avoid interfering */
2045 if (rinfo->has_CRTC2) {
2046 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
2047 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
2048 }
2049 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2050 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2051
2052 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
2053 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
2054 mdelay(100);
2055
2056 aper_base = INREG(CNFG_APER_0_BASE);
2057 aper_size = INREG(CNFG_APER_SIZE);
2058
2059 #ifdef SET_MC_FB_FROM_APERTURE
2060 /* Set framebuffer to be at the same address as set in PCI BAR */
2061 OUTREG(MC_FB_LOCATION,
2062 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
2063 rinfo->fb_local_base = aper_base;
2064 #else
2065 OUTREG(MC_FB_LOCATION, 0x7fff0000);
2066 rinfo->fb_local_base = 0;
2067 #endif
2068 agp_base = aper_base + aper_size;
2069 if (agp_base & 0xf0000000)
2070 agp_base = (aper_base | 0x0fffffff) + 1;
2071
2072 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2073 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2074 * always the case on PPCs afaik.
2075 */
2076 #ifdef SET_MC_FB_FROM_APERTURE
2077 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2078 #else
2079 OUTREG(MC_AGP_LOCATION, 0xffffe000);
2080 #endif
2081
2082 /* Fixup the display base addresses & engine offsets while we
2083 * are at it as well
2084 */
2085 #ifdef SET_MC_FB_FROM_APERTURE
2086 OUTREG(DISPLAY_BASE_ADDR, aper_base);
2087 if (rinfo->has_CRTC2)
2088 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2089 OUTREG(OV0_BASE_ADDR, aper_base);
2090 #else
2091 OUTREG(DISPLAY_BASE_ADDR, 0);
2092 if (rinfo->has_CRTC2)
2093 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2094 OUTREG(OV0_BASE_ADDR, 0);
2095 #endif
2096 mdelay(100);
2097
2098 /* Restore display settings */
2099 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2100 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2101 if (rinfo->has_CRTC2)
2102 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2103
2104 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2105 aper_base,
2106 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2107 0xffff0000 | (agp_base >> 16));
2108 }
2109 #endif /* CONFIG_PPC */
2110
2111
2112 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2113 {
2114 u32 tmp;
2115
2116 /* framebuffer size */
2117 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2118 (rinfo->family == CHIP_FAMILY_RS200) ||
2119 (rinfo->family == CHIP_FAMILY_RS300) ||
2120 (rinfo->family == CHIP_FAMILY_RC410) ||
2121 (rinfo->family == CHIP_FAMILY_RS400) ||
2122 (rinfo->family == CHIP_FAMILY_RS480) ) {
2123 u32 tom = INREG(NB_TOM);
2124 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2125
2126 radeon_fifo_wait(6);
2127 OUTREG(MC_FB_LOCATION, tom);
2128 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2129 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2130 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2131
2132 /* This is supposed to fix the crtc2 noise problem. */
2133 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2134
2135 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2136 (rinfo->family == CHIP_FAMILY_RS200)) {
2137 /* This is to workaround the asic bug for RMX, some versions
2138 of BIOS doesn't have this register initialized correctly.
2139 */
2140 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2141 ~CRTC_H_CUTOFF_ACTIVE_EN);
2142 }
2143 } else {
2144 tmp = INREG(CNFG_MEMSIZE);
2145 }
2146
2147 /* mem size is bits [28:0], mask off the rest */
2148 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2149
2150 /*
2151 * Hack to get around some busted production M6's
2152 * reporting no ram
2153 */
2154 if (rinfo->video_ram == 0) {
2155 switch (rinfo->pdev->device) {
2156 case PCI_CHIP_RADEON_LY:
2157 case PCI_CHIP_RADEON_LZ:
2158 rinfo->video_ram = 8192 * 1024;
2159 break;
2160 default:
2161 break;
2162 }
2163 }
2164
2165
2166 /*
2167 * Now try to identify VRAM type
2168 */
2169 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2170 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2171 rinfo->vram_ddr = 1;
2172 else
2173 rinfo->vram_ddr = 0;
2174
2175 tmp = INREG(MEM_CNTL);
2176 if (IS_R300_VARIANT(rinfo)) {
2177 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2178 switch (tmp) {
2179 case 0: rinfo->vram_width = 64; break;
2180 case 1: rinfo->vram_width = 128; break;
2181 case 2: rinfo->vram_width = 256; break;
2182 default: rinfo->vram_width = 128; break;
2183 }
2184 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2185 (rinfo->family == CHIP_FAMILY_RS100) ||
2186 (rinfo->family == CHIP_FAMILY_RS200)){
2187 if (tmp & RV100_MEM_HALF_MODE)
2188 rinfo->vram_width = 32;
2189 else
2190 rinfo->vram_width = 64;
2191 } else {
2192 if (tmp & MEM_NUM_CHANNELS_MASK)
2193 rinfo->vram_width = 128;
2194 else
2195 rinfo->vram_width = 64;
2196 }
2197
2198 /* This may not be correct, as some cards can have half of channel disabled
2199 * ToDo: identify these cases
2200 */
2201
2202 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2203 pci_name(rinfo->pdev),
2204 rinfo->video_ram / 1024,
2205 rinfo->vram_ddr ? "DDR" : "SDRAM",
2206 rinfo->vram_width);
2207 }
2208
2209 /*
2210 * Sysfs
2211 */
2212
2213 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2214 {
2215 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2216 }
2217
2218
2219 static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2220 struct bin_attribute *bin_attr,
2221 char *buf, loff_t off, size_t count)
2222 {
2223 struct device *dev = container_of(kobj, struct device, kobj);
2224 struct pci_dev *pdev = to_pci_dev(dev);
2225 struct fb_info *info = pci_get_drvdata(pdev);
2226 struct radeonfb_info *rinfo = info->par;
2227
2228 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2229 }
2230
2231
2232 static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2233 struct bin_attribute *bin_attr,
2234 char *buf, loff_t off, size_t count)
2235 {
2236 struct device *dev = container_of(kobj, struct device, kobj);
2237 struct pci_dev *pdev = to_pci_dev(dev);
2238 struct fb_info *info = pci_get_drvdata(pdev);
2239 struct radeonfb_info *rinfo = info->par;
2240
2241 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2242 }
2243
2244 static const struct bin_attribute edid1_attr = {
2245 .attr = {
2246 .name = "edid1",
2247 .mode = 0444,
2248 },
2249 .size = EDID_LENGTH,
2250 .read = radeon_show_edid1,
2251 };
2252
2253 static const struct bin_attribute edid2_attr = {
2254 .attr = {
2255 .name = "edid2",
2256 .mode = 0444,
2257 },
2258 .size = EDID_LENGTH,
2259 .read = radeon_show_edid2,
2260 };
2261
2262
2263 static int radeonfb_pci_register(struct pci_dev *pdev,
2264 const struct pci_device_id *ent)
2265 {
2266 struct fb_info *info;
2267 struct radeonfb_info *rinfo;
2268 int ret;
2269 unsigned char c1, c2;
2270 int err = 0;
2271
2272 pr_debug("radeonfb_pci_register BEGIN\n");
2273
2274 /* Enable device in PCI config */
2275 ret = pci_enable_device(pdev);
2276 if (ret < 0) {
2277 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2278 pci_name(pdev));
2279 goto err_out;
2280 }
2281
2282 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2283 if (!info) {
2284 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2285 pci_name(pdev));
2286 ret = -ENOMEM;
2287 goto err_disable;
2288 }
2289 rinfo = info->par;
2290 rinfo->info = info;
2291 rinfo->pdev = pdev;
2292
2293 spin_lock_init(&rinfo->reg_lock);
2294 init_timer(&rinfo->lvds_timer);
2295 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2296 rinfo->lvds_timer.data = (unsigned long)rinfo;
2297
2298 c1 = ent->device >> 8;
2299 c2 = ent->device & 0xff;
2300 if (isprint(c1) && isprint(c2))
2301 snprintf(rinfo->name, sizeof(rinfo->name),
2302 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2303 else
2304 snprintf(rinfo->name, sizeof(rinfo->name),
2305 "ATI Radeon %x", ent->device & 0xffff);
2306
2307 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2308 rinfo->chipset = pdev->device;
2309 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2310 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2311 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2312
2313 /* Set base addrs */
2314 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2315 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2316
2317 /* request the mem regions */
2318 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2319 if (ret < 0) {
2320 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2321 pci_name(rinfo->pdev));
2322 goto err_release_fb;
2323 }
2324
2325 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2326 if (ret < 0) {
2327 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2328 pci_name(rinfo->pdev));
2329 goto err_release_pci0;
2330 }
2331
2332 /* map the regions */
2333 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2334 if (!rinfo->mmio_base) {
2335 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2336 pci_name(rinfo->pdev));
2337 ret = -EIO;
2338 goto err_release_pci2;
2339 }
2340
2341 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2342
2343 /*
2344 * Check for errata
2345 */
2346 rinfo->errata = 0;
2347 if (rinfo->family == CHIP_FAMILY_R300 &&
2348 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2349 == CFG_ATI_REV_A11)
2350 rinfo->errata |= CHIP_ERRATA_R300_CG;
2351
2352 if (rinfo->family == CHIP_FAMILY_RV200 ||
2353 rinfo->family == CHIP_FAMILY_RS200)
2354 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2355
2356 if (rinfo->family == CHIP_FAMILY_RV100 ||
2357 rinfo->family == CHIP_FAMILY_RS100 ||
2358 rinfo->family == CHIP_FAMILY_RS200)
2359 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2360
2361 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
2362 /* On PPC, we obtain the OF device-node pointer to the firmware
2363 * data for this chip
2364 */
2365 rinfo->of_node = pci_device_to_OF_node(pdev);
2366 if (rinfo->of_node == NULL)
2367 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2368 pci_name(rinfo->pdev));
2369
2370 #endif /* CONFIG_PPC || CONFIG_SPARC */
2371 #ifdef CONFIG_PPC
2372 /* On PPC, the firmware sets up a memory mapping that tends
2373 * to cause lockups when enabling the engine. We reconfigure
2374 * the card internal memory mappings properly
2375 */
2376 fixup_memory_mappings(rinfo);
2377 #endif /* CONFIG_PPC */
2378
2379 /* Get VRAM size and type */
2380 radeon_identify_vram(rinfo);
2381
2382 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2383
2384 do {
2385 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
2386 rinfo->mapped_vram);
2387 } while (rinfo->fb_base == NULL &&
2388 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2389
2390 if (rinfo->fb_base == NULL) {
2391 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2392 pci_name(rinfo->pdev));
2393 ret = -EIO;
2394 goto err_unmap_rom;
2395 }
2396
2397 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2398 rinfo->mapped_vram/1024);
2399
2400 /*
2401 * Map the BIOS ROM if any and retrieve PLL parameters from
2402 * the BIOS. We skip that on mobility chips as the real panel
2403 * values we need aren't in the ROM but in the BIOS image in
2404 * memory. This is definitely not the best meacnism though,
2405 * we really need the arch code to tell us which is the "primary"
2406 * video adapter to use the memory image (or better, the arch
2407 * should provide us a copy of the BIOS image to shield us from
2408 * archs who would store that elsewhere and/or could initialize
2409 * more than one adapter during boot).
2410 */
2411 if (!rinfo->is_mobility)
2412 radeon_map_ROM(rinfo, pdev);
2413
2414 /*
2415 * On x86, the primary display on laptop may have it's BIOS
2416 * ROM elsewhere, try to locate it at the legacy memory hole.
2417 * We probably need to make sure this is the primary display,
2418 * but that is difficult without some arch support.
2419 */
2420 #ifdef CONFIG_X86
2421 if (rinfo->bios_seg == NULL)
2422 radeon_find_mem_vbios(rinfo);
2423 #endif
2424
2425 /* If both above failed, try the BIOS ROM again for mobility
2426 * chips
2427 */
2428 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2429 radeon_map_ROM(rinfo, pdev);
2430
2431 /* Get informations about the board's PLL */
2432 radeon_get_pllinfo(rinfo);
2433
2434 #ifdef CONFIG_FB_RADEON_I2C
2435 /* Register I2C bus */
2436 radeon_create_i2c_busses(rinfo);
2437 #endif
2438
2439 /* set all the vital stuff */
2440 radeon_set_fbinfo (rinfo);
2441
2442 /* Probe screen types */
2443 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2444
2445 /* Build mode list, check out panel native model */
2446 radeon_check_modes(rinfo, mode_option);
2447
2448 /* Register some sysfs stuff (should be done better) */
2449 if (rinfo->mon1_EDID)
2450 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2451 &edid1_attr);
2452 if (rinfo->mon2_EDID)
2453 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2454 &edid2_attr);
2455 if (err)
2456 pr_warn("%s() Creating sysfs files failed, continuing\n",
2457 __func__);
2458
2459 /* save current mode regs before we switch into the new one
2460 * so we can restore this upon __exit
2461 */
2462 radeon_save_state (rinfo, &rinfo->init_state);
2463 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2464
2465 /* Setup Power Management capabilities */
2466 if (default_dynclk < -1) {
2467 /* -2 is special: means ON on mobility chips and do not
2468 * change on others
2469 */
2470 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2471 } else
2472 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2473
2474 pci_set_drvdata(pdev, info);
2475
2476 /* Register with fbdev layer */
2477 ret = register_framebuffer(info);
2478 if (ret < 0) {
2479 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2480 pci_name(rinfo->pdev));
2481 goto err_unmap_fb;
2482 }
2483
2484 if (!nomtrr)
2485 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
2486 rinfo->video_ram);
2487
2488 if (backlight)
2489 radeonfb_bl_init(rinfo);
2490
2491 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2492
2493 if (rinfo->bios_seg)
2494 radeon_unmap_ROM(rinfo, pdev);
2495 pr_debug("radeonfb_pci_register END\n");
2496
2497 return 0;
2498 err_unmap_fb:
2499 iounmap(rinfo->fb_base);
2500 err_unmap_rom:
2501 kfree(rinfo->mon1_EDID);
2502 kfree(rinfo->mon2_EDID);
2503 if (rinfo->mon1_modedb)
2504 fb_destroy_modedb(rinfo->mon1_modedb);
2505 fb_dealloc_cmap(&info->cmap);
2506 #ifdef CONFIG_FB_RADEON_I2C
2507 radeon_delete_i2c_busses(rinfo);
2508 #endif
2509 if (rinfo->bios_seg)
2510 radeon_unmap_ROM(rinfo, pdev);
2511 iounmap(rinfo->mmio_base);
2512 err_release_pci2:
2513 pci_release_region(pdev, 2);
2514 err_release_pci0:
2515 pci_release_region(pdev, 0);
2516 err_release_fb:
2517 framebuffer_release(info);
2518 err_disable:
2519 err_out:
2520 return ret;
2521 }
2522
2523
2524
2525 static void radeonfb_pci_unregister(struct pci_dev *pdev)
2526 {
2527 struct fb_info *info = pci_get_drvdata(pdev);
2528 struct radeonfb_info *rinfo = info->par;
2529
2530 if (!rinfo)
2531 return;
2532
2533 radeonfb_pm_exit(rinfo);
2534
2535 if (rinfo->mon1_EDID)
2536 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2537 if (rinfo->mon2_EDID)
2538 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2539
2540 #if 0
2541 /* restore original state
2542 *
2543 * Doesn't quite work yet, I suspect if we come from a legacy
2544 * VGA mode (or worse, text mode), we need to do some VGA black
2545 * magic here that I know nothing about. --BenH
2546 */
2547 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2548 #endif
2549
2550 del_timer_sync(&rinfo->lvds_timer);
2551 arch_phys_wc_del(rinfo->wc_cookie);
2552 unregister_framebuffer(info);
2553
2554 radeonfb_bl_exit(rinfo);
2555
2556 iounmap(rinfo->mmio_base);
2557 iounmap(rinfo->fb_base);
2558
2559 pci_release_region(pdev, 2);
2560 pci_release_region(pdev, 0);
2561
2562 kfree(rinfo->mon1_EDID);
2563 kfree(rinfo->mon2_EDID);
2564 if (rinfo->mon1_modedb)
2565 fb_destroy_modedb(rinfo->mon1_modedb);
2566 #ifdef CONFIG_FB_RADEON_I2C
2567 radeon_delete_i2c_busses(rinfo);
2568 #endif
2569 fb_dealloc_cmap(&info->cmap);
2570 framebuffer_release(info);
2571 }
2572
2573
2574 static struct pci_driver radeonfb_driver = {
2575 .name = "radeonfb",
2576 .id_table = radeonfb_pci_table,
2577 .probe = radeonfb_pci_register,
2578 .remove = radeonfb_pci_unregister,
2579 #ifdef CONFIG_PM
2580 .suspend = radeonfb_pci_suspend,
2581 .resume = radeonfb_pci_resume,
2582 #endif /* CONFIG_PM */
2583 };
2584
2585 #ifndef MODULE
2586 static int __init radeonfb_setup (char *options)
2587 {
2588 char *this_opt;
2589
2590 if (!options || !*options)
2591 return 0;
2592
2593 while ((this_opt = strsep (&options, ",")) != NULL) {
2594 if (!*this_opt)
2595 continue;
2596
2597 if (!strncmp(this_opt, "noaccel", 7)) {
2598 noaccel = 1;
2599 } else if (!strncmp(this_opt, "mirror", 6)) {
2600 mirror = 1;
2601 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2602 force_dfp = 1;
2603 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2604 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2605 } else if (!strncmp(this_opt, "backlight:", 10)) {
2606 backlight = simple_strtoul(this_opt+10, NULL, 0);
2607 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2608 nomtrr = 1;
2609 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2610 nomodeset = 1;
2611 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2612 force_measure_pll = 1;
2613 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2614 ignore_edid = 1;
2615 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2616 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2617 force_sleep = 1;
2618 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2619 ignore_devlist = 1;
2620 #endif
2621 } else
2622 mode_option = this_opt;
2623 }
2624 return 0;
2625 }
2626 #endif /* MODULE */
2627
2628 static int __init radeonfb_init (void)
2629 {
2630 #ifndef MODULE
2631 char *option = NULL;
2632
2633 if (fb_get_options("radeonfb", &option))
2634 return -ENODEV;
2635 radeonfb_setup(option);
2636 #endif
2637 return pci_register_driver (&radeonfb_driver);
2638 }
2639
2640
2641 static void __exit radeonfb_exit (void)
2642 {
2643 pci_unregister_driver (&radeonfb_driver);
2644 }
2645
2646 module_init(radeonfb_init);
2647 module_exit(radeonfb_exit);
2648
2649 MODULE_AUTHOR("Ani Joshi");
2650 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2651 MODULE_LICENSE("GPL");
2652 module_param(noaccel, bool, 0);
2653 module_param(default_dynclk, int, 0);
2654 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2655 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2656 module_param(nomodeset, bool, 0);
2657 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2658 module_param(mirror, bool, 0);
2659 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2660 module_param(force_dfp, bool, 0);
2661 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2662 module_param(ignore_edid, bool, 0);
2663 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2664 module_param(monitor_layout, charp, 0);
2665 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2666 module_param(force_measure_pll, bool, 0);
2667 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2668 module_param(nomtrr, bool, 0);
2669 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2670 module_param(panel_yres, int, 0);
2671 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2672 module_param(mode_option, charp, 0);
2673 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2674 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2675 module_param(force_sleep, bool, 0);
2676 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2677 module_param(ignore_devlist, bool, 0);
2678 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2679 #endif
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