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net/mlx5: Fix mlx5_ifc_query_lag_out_bits
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 };
64
65 enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 };
71
72 enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 };
76
77 enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
150 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
241 MLX5_CMD_OP_MAX
242 };
243
244 struct mlx5_ifc_flow_table_fields_supported_bits {
245 u8 outer_dmac[0x1];
246 u8 outer_smac[0x1];
247 u8 outer_ether_type[0x1];
248 u8 outer_ip_version[0x1];
249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
252 u8 outer_ipv4_ttl[0x1];
253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
256 u8 reserved_at_b[0x1];
257 u8 outer_sip[0x1];
258 u8 outer_dip[0x1];
259 u8 outer_frag[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
271 u8 reserved_at_1a[0x5];
272 u8 source_eswitch_port[0x1];
273
274 u8 inner_dmac[0x1];
275 u8 inner_smac[0x1];
276 u8 inner_ether_type[0x1];
277 u8 inner_ip_version[0x1];
278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
281 u8 reserved_at_27[0x1];
282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
285 u8 reserved_at_2b[0x1];
286 u8 inner_sip[0x1];
287 u8 inner_dip[0x1];
288 u8 inner_frag[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
297 u8 reserved_at_37[0x9];
298 u8 reserved_at_40[0x1a];
299 u8 bth_dst_qp[0x1];
300
301 u8 reserved_at_5b[0x25];
302 };
303
304 struct mlx5_ifc_flow_table_prop_layout_bits {
305 u8 ft_support[0x1];
306 u8 reserved_at_1[0x1];
307 u8 flow_counter[0x1];
308 u8 flow_modify_en[0x1];
309 u8 modify_root[0x1];
310 u8 identified_miss_table_mode[0x1];
311 u8 flow_table_modify[0x1];
312 u8 encap[0x1];
313 u8 decap[0x1];
314 u8 reserved_at_9[0x17];
315
316 u8 reserved_at_20[0x2];
317 u8 log_max_ft_size[0x6];
318 u8 log_max_modify_header_context[0x8];
319 u8 max_modify_header_actions[0x8];
320 u8 max_ft_level[0x8];
321
322 u8 reserved_at_40[0x20];
323
324 u8 reserved_at_60[0x18];
325 u8 log_max_ft_num[0x8];
326
327 u8 reserved_at_80[0x18];
328 u8 log_max_destination[0x8];
329
330 u8 log_max_flow_counter[0x8];
331 u8 reserved_at_a8[0x10];
332 u8 log_max_flow[0x8];
333
334 u8 reserved_at_c0[0x40];
335
336 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
337
338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
339 };
340
341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
342 u8 send[0x1];
343 u8 receive[0x1];
344 u8 write[0x1];
345 u8 read[0x1];
346 u8 atomic[0x1];
347 u8 srq_receive[0x1];
348 u8 reserved_at_6[0x1a];
349 };
350
351 struct mlx5_ifc_ipv4_layout_bits {
352 u8 reserved_at_0[0x60];
353
354 u8 ipv4[0x20];
355 };
356
357 struct mlx5_ifc_ipv6_layout_bits {
358 u8 ipv6[16][0x8];
359 };
360
361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
362 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
363 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
364 u8 reserved_at_0[0x80];
365 };
366
367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
368 u8 smac_47_16[0x20];
369
370 u8 smac_15_0[0x10];
371 u8 ethertype[0x10];
372
373 u8 dmac_47_16[0x20];
374
375 u8 dmac_15_0[0x10];
376 u8 first_prio[0x3];
377 u8 first_cfi[0x1];
378 u8 first_vid[0xc];
379
380 u8 ip_protocol[0x8];
381 u8 ip_dscp[0x6];
382 u8 ip_ecn[0x2];
383 u8 cvlan_tag[0x1];
384 u8 svlan_tag[0x1];
385 u8 frag[0x1];
386 u8 ip_version[0x4];
387 u8 tcp_flags[0x9];
388
389 u8 tcp_sport[0x10];
390 u8 tcp_dport[0x10];
391
392 u8 reserved_at_c0[0x18];
393 u8 ttl_hoplimit[0x8];
394
395 u8 udp_sport[0x10];
396 u8 udp_dport[0x10];
397
398 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
399
400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
401 };
402
403 struct mlx5_ifc_fte_match_set_misc_bits {
404 u8 reserved_at_0[0x8];
405 u8 source_sqn[0x18];
406
407 u8 reserved_at_20[0x10];
408 u8 source_port[0x10];
409
410 u8 outer_second_prio[0x3];
411 u8 outer_second_cfi[0x1];
412 u8 outer_second_vid[0xc];
413 u8 inner_second_prio[0x3];
414 u8 inner_second_cfi[0x1];
415 u8 inner_second_vid[0xc];
416
417 u8 outer_second_cvlan_tag[0x1];
418 u8 inner_second_cvlan_tag[0x1];
419 u8 outer_second_svlan_tag[0x1];
420 u8 inner_second_svlan_tag[0x1];
421 u8 reserved_at_64[0xc];
422 u8 gre_protocol[0x10];
423
424 u8 gre_key_h[0x18];
425 u8 gre_key_l[0x8];
426
427 u8 vxlan_vni[0x18];
428 u8 reserved_at_b8[0x8];
429
430 u8 reserved_at_c0[0x20];
431
432 u8 reserved_at_e0[0xc];
433 u8 outer_ipv6_flow_label[0x14];
434
435 u8 reserved_at_100[0xc];
436 u8 inner_ipv6_flow_label[0x14];
437
438 u8 reserved_at_120[0x28];
439 u8 bth_dst_qp[0x18];
440 u8 reserved_at_160[0xa0];
441 };
442
443 struct mlx5_ifc_cmd_pas_bits {
444 u8 pa_h[0x20];
445
446 u8 pa_l[0x14];
447 u8 reserved_at_34[0xc];
448 };
449
450 struct mlx5_ifc_uint64_bits {
451 u8 hi[0x20];
452
453 u8 lo[0x20];
454 };
455
456 enum {
457 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
458 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
459 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
460 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
461 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
462 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
463 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
464 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
465 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
466 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
467 };
468
469 struct mlx5_ifc_ads_bits {
470 u8 fl[0x1];
471 u8 free_ar[0x1];
472 u8 reserved_at_2[0xe];
473 u8 pkey_index[0x10];
474
475 u8 reserved_at_20[0x8];
476 u8 grh[0x1];
477 u8 mlid[0x7];
478 u8 rlid[0x10];
479
480 u8 ack_timeout[0x5];
481 u8 reserved_at_45[0x3];
482 u8 src_addr_index[0x8];
483 u8 reserved_at_50[0x4];
484 u8 stat_rate[0x4];
485 u8 hop_limit[0x8];
486
487 u8 reserved_at_60[0x4];
488 u8 tclass[0x8];
489 u8 flow_label[0x14];
490
491 u8 rgid_rip[16][0x8];
492
493 u8 reserved_at_100[0x4];
494 u8 f_dscp[0x1];
495 u8 f_ecn[0x1];
496 u8 reserved_at_106[0x1];
497 u8 f_eth_prio[0x1];
498 u8 ecn[0x2];
499 u8 dscp[0x6];
500 u8 udp_sport[0x10];
501
502 u8 dei_cfi[0x1];
503 u8 eth_prio[0x3];
504 u8 sl[0x4];
505 u8 port[0x8];
506 u8 rmac_47_32[0x10];
507
508 u8 rmac_31_0[0x20];
509 };
510
511 struct mlx5_ifc_flow_table_nic_cap_bits {
512 u8 nic_rx_multi_path_tirs[0x1];
513 u8 nic_rx_multi_path_tirs_fts[0x1];
514 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
515 u8 reserved_at_3[0x1fd];
516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
518
519 u8 reserved_at_400[0x200];
520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
522
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
524
525 u8 reserved_at_a00[0x200];
526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
528
529 u8 reserved_at_e00[0x7200];
530 };
531
532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
533 u8 reserved_at_0[0x200];
534
535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
536
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
538
539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
540
541 u8 reserved_at_800[0x7800];
542 };
543
544 struct mlx5_ifc_e_switch_cap_bits {
545 u8 vport_svlan_strip[0x1];
546 u8 vport_cvlan_strip[0x1];
547 u8 vport_svlan_insert[0x1];
548 u8 vport_cvlan_insert_if_not_exist[0x1];
549 u8 vport_cvlan_insert_overwrite[0x1];
550 u8 reserved_at_5[0x19];
551 u8 nic_vport_node_guid_modify[0x1];
552 u8 nic_vport_port_guid_modify[0x1];
553
554 u8 vxlan_encap_decap[0x1];
555 u8 nvgre_encap_decap[0x1];
556 u8 reserved_at_22[0x9];
557 u8 log_max_encap_headers[0x5];
558 u8 reserved_2b[0x6];
559 u8 max_encap_header_size[0xa];
560
561 u8 reserved_40[0x7c0];
562
563 };
564
565 struct mlx5_ifc_qos_cap_bits {
566 u8 packet_pacing[0x1];
567 u8 esw_scheduling[0x1];
568 u8 esw_bw_share[0x1];
569 u8 esw_rate_limit[0x1];
570 u8 reserved_at_4[0x1c];
571
572 u8 reserved_at_20[0x20];
573
574 u8 packet_pacing_max_rate[0x20];
575
576 u8 packet_pacing_min_rate[0x20];
577
578 u8 reserved_at_80[0x10];
579 u8 packet_pacing_rate_table_size[0x10];
580
581 u8 esw_element_type[0x10];
582 u8 esw_tsar_type[0x10];
583
584 u8 reserved_at_c0[0x10];
585 u8 max_qos_para_vport[0x10];
586
587 u8 max_tsar_bw_share[0x20];
588
589 u8 reserved_at_100[0x700];
590 };
591
592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
593 u8 csum_cap[0x1];
594 u8 vlan_cap[0x1];
595 u8 lro_cap[0x1];
596 u8 lro_psh_flag[0x1];
597 u8 lro_time_stamp[0x1];
598 u8 reserved_at_5[0x2];
599 u8 wqe_vlan_insert[0x1];
600 u8 self_lb_en_modifiable[0x1];
601 u8 reserved_at_9[0x2];
602 u8 max_lso_cap[0x5];
603 u8 multi_pkt_send_wqe[0x2];
604 u8 wqe_inline_mode[0x2];
605 u8 rss_ind_tbl_cap[0x4];
606 u8 reg_umr_sq[0x1];
607 u8 scatter_fcs[0x1];
608 u8 enhanced_multi_pkt_send_wqe[0x1];
609 u8 tunnel_lso_const_out_ip_id[0x1];
610 u8 reserved_at_1c[0x2];
611 u8 tunnel_stateless_gre[0x1];
612 u8 tunnel_stateless_vxlan[0x1];
613
614 u8 swp[0x1];
615 u8 swp_csum[0x1];
616 u8 swp_lso[0x1];
617 u8 cqe_checksum_full[0x1];
618 u8 reserved_at_24[0x1a];
619 u8 max_geneve_opt_len[0x1];
620 u8 tunnel_stateless_geneve_rx[0x1];
621
622 u8 reserved_at_40[0x10];
623 u8 lro_min_mss_size[0x10];
624
625 u8 reserved_at_60[0x120];
626
627 u8 lro_timer_supported_periods[4][0x20];
628
629 u8 reserved_at_200[0x600];
630 };
631
632 struct mlx5_ifc_roce_cap_bits {
633 u8 roce_apm[0x1];
634 u8 reserved_at_1[0x1f];
635
636 u8 reserved_at_20[0x60];
637
638 u8 reserved_at_80[0xc];
639 u8 l3_type[0x4];
640 u8 reserved_at_90[0x8];
641 u8 roce_version[0x8];
642
643 u8 reserved_at_a0[0x10];
644 u8 r_roce_dest_udp_port[0x10];
645
646 u8 r_roce_max_src_udp_port[0x10];
647 u8 r_roce_min_src_udp_port[0x10];
648
649 u8 reserved_at_e0[0x10];
650 u8 roce_address_table_size[0x10];
651
652 u8 reserved_at_100[0x700];
653 };
654
655 enum {
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
665 };
666
667 enum {
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
676 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
677 };
678
679 struct mlx5_ifc_atomic_caps_bits {
680 u8 reserved_at_0[0x40];
681
682 u8 atomic_req_8B_endianness_mode[0x2];
683 u8 reserved_at_42[0x4];
684 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
685
686 u8 reserved_at_47[0x19];
687
688 u8 reserved_at_60[0x20];
689
690 u8 reserved_at_80[0x10];
691 u8 atomic_operations[0x10];
692
693 u8 reserved_at_a0[0x10];
694 u8 atomic_size_qp[0x10];
695
696 u8 reserved_at_c0[0x10];
697 u8 atomic_size_dc[0x10];
698
699 u8 reserved_at_e0[0x720];
700 };
701
702 struct mlx5_ifc_odp_cap_bits {
703 u8 reserved_at_0[0x40];
704
705 u8 sig[0x1];
706 u8 reserved_at_41[0x1f];
707
708 u8 reserved_at_60[0x20];
709
710 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
711
712 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
713
714 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
715
716 u8 reserved_at_e0[0x720];
717 };
718
719 struct mlx5_ifc_calc_op {
720 u8 reserved_at_0[0x10];
721 u8 reserved_at_10[0x9];
722 u8 op_swap_endianness[0x1];
723 u8 op_min[0x1];
724 u8 op_xor[0x1];
725 u8 op_or[0x1];
726 u8 op_and[0x1];
727 u8 op_max[0x1];
728 u8 op_add[0x1];
729 };
730
731 struct mlx5_ifc_vector_calc_cap_bits {
732 u8 calc_matrix[0x1];
733 u8 reserved_at_1[0x1f];
734 u8 reserved_at_20[0x8];
735 u8 max_vec_count[0x8];
736 u8 reserved_at_30[0xd];
737 u8 max_chunk_size[0x3];
738 struct mlx5_ifc_calc_op calc0;
739 struct mlx5_ifc_calc_op calc1;
740 struct mlx5_ifc_calc_op calc2;
741 struct mlx5_ifc_calc_op calc3;
742
743 u8 reserved_at_e0[0x720];
744 };
745
746 enum {
747 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
748 MLX5_WQ_TYPE_CYCLIC = 0x1,
749 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
750 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
751 };
752
753 enum {
754 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
755 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
756 };
757
758 enum {
759 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
760 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
761 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
762 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
763 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
764 };
765
766 enum {
767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
768 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
769 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
770 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
771 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
772 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
773 };
774
775 enum {
776 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
777 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
778 };
779
780 enum {
781 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
782 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
783 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
784 };
785
786 enum {
787 MLX5_CAP_PORT_TYPE_IB = 0x0,
788 MLX5_CAP_PORT_TYPE_ETH = 0x1,
789 };
790
791 enum {
792 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
793 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
794 MLX5_CAP_UMR_FENCE_NONE = 0x2,
795 };
796
797 struct mlx5_ifc_cmd_hca_cap_bits {
798 u8 reserved_at_0[0x80];
799
800 u8 log_max_srq_sz[0x8];
801 u8 log_max_qp_sz[0x8];
802 u8 reserved_at_90[0xb];
803 u8 log_max_qp[0x5];
804
805 u8 reserved_at_a0[0xb];
806 u8 log_max_srq[0x5];
807 u8 reserved_at_b0[0x10];
808
809 u8 reserved_at_c0[0x8];
810 u8 log_max_cq_sz[0x8];
811 u8 reserved_at_d0[0xb];
812 u8 log_max_cq[0x5];
813
814 u8 log_max_eq_sz[0x8];
815 u8 reserved_at_e8[0x2];
816 u8 log_max_mkey[0x6];
817 u8 reserved_at_f0[0xc];
818 u8 log_max_eq[0x4];
819
820 u8 max_indirection[0x8];
821 u8 fixed_buffer_size[0x1];
822 u8 log_max_mrw_sz[0x7];
823 u8 force_teardown[0x1];
824 u8 reserved_at_111[0x1];
825 u8 log_max_bsf_list_size[0x6];
826 u8 umr_extended_translation_offset[0x1];
827 u8 null_mkey[0x1];
828 u8 log_max_klm_list_size[0x6];
829
830 u8 reserved_at_120[0xa];
831 u8 log_max_ra_req_dc[0x6];
832 u8 reserved_at_130[0xa];
833 u8 log_max_ra_res_dc[0x6];
834
835 u8 reserved_at_140[0xa];
836 u8 log_max_ra_req_qp[0x6];
837 u8 reserved_at_150[0xa];
838 u8 log_max_ra_res_qp[0x6];
839
840 u8 end_pad[0x1];
841 u8 cc_query_allowed[0x1];
842 u8 cc_modify_allowed[0x1];
843 u8 start_pad[0x1];
844 u8 cache_line_128byte[0x1];
845 u8 reserved_at_165[0xa];
846 u8 qcam_reg[0x1];
847 u8 gid_table_size[0x10];
848
849 u8 out_of_seq_cnt[0x1];
850 u8 vport_counters[0x1];
851 u8 retransmission_q_counters[0x1];
852 u8 reserved_at_183[0x1];
853 u8 modify_rq_counter_set_id[0x1];
854 u8 rq_delay_drop[0x1];
855 u8 max_qp_cnt[0xa];
856 u8 pkey_table_size[0x10];
857
858 u8 vport_group_manager[0x1];
859 u8 vhca_group_manager[0x1];
860 u8 ib_virt[0x1];
861 u8 eth_virt[0x1];
862 u8 reserved_at_1a4[0x1];
863 u8 ets[0x1];
864 u8 nic_flow_table[0x1];
865 u8 eswitch_manager[0x1];
866 u8 early_vf_enable[0x1];
867 u8 mcam_reg[0x1];
868 u8 pcam_reg[0x1];
869 u8 local_ca_ack_delay[0x5];
870 u8 port_module_event[0x1];
871 u8 enhanced_error_q_counters[0x1];
872 u8 ports_check[0x1];
873 u8 reserved_at_1b3[0x1];
874 u8 disable_link_up[0x1];
875 u8 beacon_led[0x1];
876 u8 port_type[0x2];
877 u8 num_ports[0x8];
878
879 u8 reserved_at_1c0[0x1];
880 u8 pps[0x1];
881 u8 pps_modify[0x1];
882 u8 log_max_msg[0x5];
883 u8 reserved_at_1c8[0x4];
884 u8 max_tc[0x4];
885 u8 reserved_at_1d0[0x1];
886 u8 dcbx[0x1];
887 u8 general_notification_event[0x1];
888 u8 reserved_at_1d3[0x2];
889 u8 fpga[0x1];
890 u8 rol_s[0x1];
891 u8 rol_g[0x1];
892 u8 reserved_at_1d8[0x1];
893 u8 wol_s[0x1];
894 u8 wol_g[0x1];
895 u8 wol_a[0x1];
896 u8 wol_b[0x1];
897 u8 wol_m[0x1];
898 u8 wol_u[0x1];
899 u8 wol_p[0x1];
900
901 u8 stat_rate_support[0x10];
902 u8 reserved_at_1f0[0xc];
903 u8 cqe_version[0x4];
904
905 u8 compact_address_vector[0x1];
906 u8 striding_rq[0x1];
907 u8 reserved_at_202[0x1];
908 u8 ipoib_enhanced_offloads[0x1];
909 u8 ipoib_basic_offloads[0x1];
910 u8 reserved_at_205[0x5];
911 u8 umr_fence[0x2];
912 u8 reserved_at_20c[0x3];
913 u8 drain_sigerr[0x1];
914 u8 cmdif_checksum[0x2];
915 u8 sigerr_cqe[0x1];
916 u8 reserved_at_213[0x1];
917 u8 wq_signature[0x1];
918 u8 sctr_data_cqe[0x1];
919 u8 reserved_at_216[0x1];
920 u8 sho[0x1];
921 u8 tph[0x1];
922 u8 rf[0x1];
923 u8 dct[0x1];
924 u8 qos[0x1];
925 u8 eth_net_offloads[0x1];
926 u8 roce[0x1];
927 u8 atomic[0x1];
928 u8 reserved_at_21f[0x1];
929
930 u8 cq_oi[0x1];
931 u8 cq_resize[0x1];
932 u8 cq_moderation[0x1];
933 u8 reserved_at_223[0x3];
934 u8 cq_eq_remap[0x1];
935 u8 pg[0x1];
936 u8 block_lb_mc[0x1];
937 u8 reserved_at_229[0x1];
938 u8 scqe_break_moderation[0x1];
939 u8 cq_period_start_from_cqe[0x1];
940 u8 cd[0x1];
941 u8 reserved_at_22d[0x1];
942 u8 apm[0x1];
943 u8 vector_calc[0x1];
944 u8 umr_ptr_rlky[0x1];
945 u8 imaicl[0x1];
946 u8 reserved_at_232[0x4];
947 u8 qkv[0x1];
948 u8 pkv[0x1];
949 u8 set_deth_sqpn[0x1];
950 u8 reserved_at_239[0x3];
951 u8 xrc[0x1];
952 u8 ud[0x1];
953 u8 uc[0x1];
954 u8 rc[0x1];
955
956 u8 uar_4k[0x1];
957 u8 reserved_at_241[0x9];
958 u8 uar_sz[0x6];
959 u8 reserved_at_250[0x8];
960 u8 log_pg_sz[0x8];
961
962 u8 bf[0x1];
963 u8 driver_version[0x1];
964 u8 pad_tx_eth_packet[0x1];
965 u8 reserved_at_263[0x8];
966 u8 log_bf_reg_size[0x5];
967
968 u8 reserved_at_270[0xb];
969 u8 lag_master[0x1];
970 u8 num_lag_ports[0x4];
971
972 u8 reserved_at_280[0x10];
973 u8 max_wqe_sz_sq[0x10];
974
975 u8 reserved_at_2a0[0x10];
976 u8 max_wqe_sz_rq[0x10];
977
978 u8 max_flow_counter_31_16[0x10];
979 u8 max_wqe_sz_sq_dc[0x10];
980
981 u8 reserved_at_2e0[0x7];
982 u8 max_qp_mcg[0x19];
983
984 u8 reserved_at_300[0x18];
985 u8 log_max_mcg[0x8];
986
987 u8 reserved_at_320[0x3];
988 u8 log_max_transport_domain[0x5];
989 u8 reserved_at_328[0x3];
990 u8 log_max_pd[0x5];
991 u8 reserved_at_330[0xb];
992 u8 log_max_xrcd[0x5];
993
994 u8 reserved_at_340[0x8];
995 u8 log_max_flow_counter_bulk[0x8];
996 u8 max_flow_counter_15_0[0x10];
997
998
999 u8 reserved_at_360[0x3];
1000 u8 log_max_rq[0x5];
1001 u8 reserved_at_368[0x3];
1002 u8 log_max_sq[0x5];
1003 u8 reserved_at_370[0x3];
1004 u8 log_max_tir[0x5];
1005 u8 reserved_at_378[0x3];
1006 u8 log_max_tis[0x5];
1007
1008 u8 basic_cyclic_rcv_wqe[0x1];
1009 u8 reserved_at_381[0x2];
1010 u8 log_max_rmp[0x5];
1011 u8 reserved_at_388[0x3];
1012 u8 log_max_rqt[0x5];
1013 u8 reserved_at_390[0x3];
1014 u8 log_max_rqt_size[0x5];
1015 u8 reserved_at_398[0x3];
1016 u8 log_max_tis_per_sq[0x5];
1017
1018 u8 reserved_at_3a0[0x3];
1019 u8 log_max_stride_sz_rq[0x5];
1020 u8 reserved_at_3a8[0x3];
1021 u8 log_min_stride_sz_rq[0x5];
1022 u8 reserved_at_3b0[0x3];
1023 u8 log_max_stride_sz_sq[0x5];
1024 u8 reserved_at_3b8[0x3];
1025 u8 log_min_stride_sz_sq[0x5];
1026
1027 u8 reserved_at_3c0[0x1b];
1028 u8 log_max_wq_sz[0x5];
1029
1030 u8 nic_vport_change_event[0x1];
1031 u8 disable_local_lb_uc[0x1];
1032 u8 disable_local_lb_mc[0x1];
1033 u8 reserved_at_3e3[0x8];
1034 u8 log_max_vlan_list[0x5];
1035 u8 reserved_at_3f0[0x3];
1036 u8 log_max_current_mc_list[0x5];
1037 u8 reserved_at_3f8[0x3];
1038 u8 log_max_current_uc_list[0x5];
1039
1040 u8 reserved_at_400[0x80];
1041
1042 u8 reserved_at_480[0x3];
1043 u8 log_max_l2_table[0x5];
1044 u8 reserved_at_488[0x8];
1045 u8 log_uar_page_sz[0x10];
1046
1047 u8 reserved_at_4a0[0x20];
1048 u8 device_frequency_mhz[0x20];
1049 u8 device_frequency_khz[0x20];
1050
1051 u8 reserved_at_500[0x20];
1052 u8 num_of_uars_per_page[0x20];
1053 u8 reserved_at_540[0x40];
1054
1055 u8 reserved_at_580[0x3d];
1056 u8 cqe_128_always[0x1];
1057 u8 cqe_compression_128[0x1];
1058 u8 cqe_compression[0x1];
1059
1060 u8 cqe_compression_timeout[0x10];
1061 u8 cqe_compression_max_num[0x10];
1062
1063 u8 reserved_at_5e0[0x10];
1064 u8 tag_matching[0x1];
1065 u8 rndv_offload_rc[0x1];
1066 u8 rndv_offload_dc[0x1];
1067 u8 log_tag_matching_list_sz[0x5];
1068 u8 reserved_at_5f8[0x3];
1069 u8 log_max_xrq[0x5];
1070
1071 u8 reserved_at_600[0x200];
1072 };
1073
1074 enum mlx5_flow_destination_type {
1075 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1076 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1077 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1078
1079 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1080 };
1081
1082 struct mlx5_ifc_dest_format_struct_bits {
1083 u8 destination_type[0x8];
1084 u8 destination_id[0x18];
1085
1086 u8 reserved_at_20[0x20];
1087 };
1088
1089 struct mlx5_ifc_flow_counter_list_bits {
1090 u8 flow_counter_id[0x20];
1091
1092 u8 reserved_at_20[0x20];
1093 };
1094
1095 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1096 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1097 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1098 u8 reserved_at_0[0x40];
1099 };
1100
1101 struct mlx5_ifc_fte_match_param_bits {
1102 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1103
1104 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1105
1106 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1107
1108 u8 reserved_at_600[0xa00];
1109 };
1110
1111 enum {
1112 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1115 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1116 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1117 };
1118
1119 struct mlx5_ifc_rx_hash_field_select_bits {
1120 u8 l3_prot_type[0x1];
1121 u8 l4_prot_type[0x1];
1122 u8 selected_fields[0x1e];
1123 };
1124
1125 enum {
1126 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1127 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1128 };
1129
1130 enum {
1131 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1132 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1133 };
1134
1135 struct mlx5_ifc_wq_bits {
1136 u8 wq_type[0x4];
1137 u8 wq_signature[0x1];
1138 u8 end_padding_mode[0x2];
1139 u8 cd_slave[0x1];
1140 u8 reserved_at_8[0x18];
1141
1142 u8 hds_skip_first_sge[0x1];
1143 u8 log2_hds_buf_size[0x3];
1144 u8 reserved_at_24[0x7];
1145 u8 page_offset[0x5];
1146 u8 lwm[0x10];
1147
1148 u8 reserved_at_40[0x8];
1149 u8 pd[0x18];
1150
1151 u8 reserved_at_60[0x8];
1152 u8 uar_page[0x18];
1153
1154 u8 dbr_addr[0x40];
1155
1156 u8 hw_counter[0x20];
1157
1158 u8 sw_counter[0x20];
1159
1160 u8 reserved_at_100[0xc];
1161 u8 log_wq_stride[0x4];
1162 u8 reserved_at_110[0x3];
1163 u8 log_wq_pg_sz[0x5];
1164 u8 reserved_at_118[0x3];
1165 u8 log_wq_sz[0x5];
1166
1167 u8 reserved_at_120[0x15];
1168 u8 log_wqe_num_of_strides[0x3];
1169 u8 two_byte_shift_en[0x1];
1170 u8 reserved_at_139[0x4];
1171 u8 log_wqe_stride_size[0x3];
1172
1173 u8 reserved_at_140[0x4c0];
1174
1175 struct mlx5_ifc_cmd_pas_bits pas[0];
1176 };
1177
1178 struct mlx5_ifc_rq_num_bits {
1179 u8 reserved_at_0[0x8];
1180 u8 rq_num[0x18];
1181 };
1182
1183 struct mlx5_ifc_mac_address_layout_bits {
1184 u8 reserved_at_0[0x10];
1185 u8 mac_addr_47_32[0x10];
1186
1187 u8 mac_addr_31_0[0x20];
1188 };
1189
1190 struct mlx5_ifc_vlan_layout_bits {
1191 u8 reserved_at_0[0x14];
1192 u8 vlan[0x0c];
1193
1194 u8 reserved_at_20[0x20];
1195 };
1196
1197 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1198 u8 reserved_at_0[0xa0];
1199
1200 u8 min_time_between_cnps[0x20];
1201
1202 u8 reserved_at_c0[0x12];
1203 u8 cnp_dscp[0x6];
1204 u8 reserved_at_d8[0x4];
1205 u8 cnp_prio_mode[0x1];
1206 u8 cnp_802p_prio[0x3];
1207
1208 u8 reserved_at_e0[0x720];
1209 };
1210
1211 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1212 u8 reserved_at_0[0x60];
1213
1214 u8 reserved_at_60[0x4];
1215 u8 clamp_tgt_rate[0x1];
1216 u8 reserved_at_65[0x3];
1217 u8 clamp_tgt_rate_after_time_inc[0x1];
1218 u8 reserved_at_69[0x17];
1219
1220 u8 reserved_at_80[0x20];
1221
1222 u8 rpg_time_reset[0x20];
1223
1224 u8 rpg_byte_reset[0x20];
1225
1226 u8 rpg_threshold[0x20];
1227
1228 u8 rpg_max_rate[0x20];
1229
1230 u8 rpg_ai_rate[0x20];
1231
1232 u8 rpg_hai_rate[0x20];
1233
1234 u8 rpg_gd[0x20];
1235
1236 u8 rpg_min_dec_fac[0x20];
1237
1238 u8 rpg_min_rate[0x20];
1239
1240 u8 reserved_at_1c0[0xe0];
1241
1242 u8 rate_to_set_on_first_cnp[0x20];
1243
1244 u8 dce_tcp_g[0x20];
1245
1246 u8 dce_tcp_rtt[0x20];
1247
1248 u8 rate_reduce_monitor_period[0x20];
1249
1250 u8 reserved_at_320[0x20];
1251
1252 u8 initial_alpha_value[0x20];
1253
1254 u8 reserved_at_360[0x4a0];
1255 };
1256
1257 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1258 u8 reserved_at_0[0x80];
1259
1260 u8 rppp_max_rps[0x20];
1261
1262 u8 rpg_time_reset[0x20];
1263
1264 u8 rpg_byte_reset[0x20];
1265
1266 u8 rpg_threshold[0x20];
1267
1268 u8 rpg_max_rate[0x20];
1269
1270 u8 rpg_ai_rate[0x20];
1271
1272 u8 rpg_hai_rate[0x20];
1273
1274 u8 rpg_gd[0x20];
1275
1276 u8 rpg_min_dec_fac[0x20];
1277
1278 u8 rpg_min_rate[0x20];
1279
1280 u8 reserved_at_1c0[0x640];
1281 };
1282
1283 enum {
1284 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1285 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1286 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1287 };
1288
1289 struct mlx5_ifc_resize_field_select_bits {
1290 u8 resize_field_select[0x20];
1291 };
1292
1293 enum {
1294 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1295 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1296 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1297 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1298 };
1299
1300 struct mlx5_ifc_modify_field_select_bits {
1301 u8 modify_field_select[0x20];
1302 };
1303
1304 struct mlx5_ifc_field_select_r_roce_np_bits {
1305 u8 field_select_r_roce_np[0x20];
1306 };
1307
1308 struct mlx5_ifc_field_select_r_roce_rp_bits {
1309 u8 field_select_r_roce_rp[0x20];
1310 };
1311
1312 enum {
1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1323 };
1324
1325 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1326 u8 field_select_8021qaurp[0x20];
1327 };
1328
1329 struct mlx5_ifc_phys_layer_cntrs_bits {
1330 u8 time_since_last_clear_high[0x20];
1331
1332 u8 time_since_last_clear_low[0x20];
1333
1334 u8 symbol_errors_high[0x20];
1335
1336 u8 symbol_errors_low[0x20];
1337
1338 u8 sync_headers_errors_high[0x20];
1339
1340 u8 sync_headers_errors_low[0x20];
1341
1342 u8 edpl_bip_errors_lane0_high[0x20];
1343
1344 u8 edpl_bip_errors_lane0_low[0x20];
1345
1346 u8 edpl_bip_errors_lane1_high[0x20];
1347
1348 u8 edpl_bip_errors_lane1_low[0x20];
1349
1350 u8 edpl_bip_errors_lane2_high[0x20];
1351
1352 u8 edpl_bip_errors_lane2_low[0x20];
1353
1354 u8 edpl_bip_errors_lane3_high[0x20];
1355
1356 u8 edpl_bip_errors_lane3_low[0x20];
1357
1358 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1359
1360 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1361
1362 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1363
1364 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1365
1366 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1367
1368 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1369
1370 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1371
1372 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1373
1374 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1375
1376 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1377
1378 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1379
1380 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1381
1382 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1383
1384 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1385
1386 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1387
1388 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1389
1390 u8 rs_fec_corrected_blocks_high[0x20];
1391
1392 u8 rs_fec_corrected_blocks_low[0x20];
1393
1394 u8 rs_fec_uncorrectable_blocks_high[0x20];
1395
1396 u8 rs_fec_uncorrectable_blocks_low[0x20];
1397
1398 u8 rs_fec_no_errors_blocks_high[0x20];
1399
1400 u8 rs_fec_no_errors_blocks_low[0x20];
1401
1402 u8 rs_fec_single_error_blocks_high[0x20];
1403
1404 u8 rs_fec_single_error_blocks_low[0x20];
1405
1406 u8 rs_fec_corrected_symbols_total_high[0x20];
1407
1408 u8 rs_fec_corrected_symbols_total_low[0x20];
1409
1410 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1411
1412 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1413
1414 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1415
1416 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1417
1418 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1419
1420 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1421
1422 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1423
1424 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1425
1426 u8 link_down_events[0x20];
1427
1428 u8 successful_recovery_events[0x20];
1429
1430 u8 reserved_at_640[0x180];
1431 };
1432
1433 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1434 u8 time_since_last_clear_high[0x20];
1435
1436 u8 time_since_last_clear_low[0x20];
1437
1438 u8 phy_received_bits_high[0x20];
1439
1440 u8 phy_received_bits_low[0x20];
1441
1442 u8 phy_symbol_errors_high[0x20];
1443
1444 u8 phy_symbol_errors_low[0x20];
1445
1446 u8 phy_corrected_bits_high[0x20];
1447
1448 u8 phy_corrected_bits_low[0x20];
1449
1450 u8 phy_corrected_bits_lane0_high[0x20];
1451
1452 u8 phy_corrected_bits_lane0_low[0x20];
1453
1454 u8 phy_corrected_bits_lane1_high[0x20];
1455
1456 u8 phy_corrected_bits_lane1_low[0x20];
1457
1458 u8 phy_corrected_bits_lane2_high[0x20];
1459
1460 u8 phy_corrected_bits_lane2_low[0x20];
1461
1462 u8 phy_corrected_bits_lane3_high[0x20];
1463
1464 u8 phy_corrected_bits_lane3_low[0x20];
1465
1466 u8 reserved_at_200[0x5c0];
1467 };
1468
1469 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1470 u8 symbol_error_counter[0x10];
1471
1472 u8 link_error_recovery_counter[0x8];
1473
1474 u8 link_downed_counter[0x8];
1475
1476 u8 port_rcv_errors[0x10];
1477
1478 u8 port_rcv_remote_physical_errors[0x10];
1479
1480 u8 port_rcv_switch_relay_errors[0x10];
1481
1482 u8 port_xmit_discards[0x10];
1483
1484 u8 port_xmit_constraint_errors[0x8];
1485
1486 u8 port_rcv_constraint_errors[0x8];
1487
1488 u8 reserved_at_70[0x8];
1489
1490 u8 link_overrun_errors[0x8];
1491
1492 u8 reserved_at_80[0x10];
1493
1494 u8 vl_15_dropped[0x10];
1495
1496 u8 reserved_at_a0[0x80];
1497
1498 u8 port_xmit_wait[0x20];
1499 };
1500
1501 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1502 u8 transmit_queue_high[0x20];
1503
1504 u8 transmit_queue_low[0x20];
1505
1506 u8 reserved_at_40[0x780];
1507 };
1508
1509 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1510 u8 rx_octets_high[0x20];
1511
1512 u8 rx_octets_low[0x20];
1513
1514 u8 reserved_at_40[0xc0];
1515
1516 u8 rx_frames_high[0x20];
1517
1518 u8 rx_frames_low[0x20];
1519
1520 u8 tx_octets_high[0x20];
1521
1522 u8 tx_octets_low[0x20];
1523
1524 u8 reserved_at_180[0xc0];
1525
1526 u8 tx_frames_high[0x20];
1527
1528 u8 tx_frames_low[0x20];
1529
1530 u8 rx_pause_high[0x20];
1531
1532 u8 rx_pause_low[0x20];
1533
1534 u8 rx_pause_duration_high[0x20];
1535
1536 u8 rx_pause_duration_low[0x20];
1537
1538 u8 tx_pause_high[0x20];
1539
1540 u8 tx_pause_low[0x20];
1541
1542 u8 tx_pause_duration_high[0x20];
1543
1544 u8 tx_pause_duration_low[0x20];
1545
1546 u8 rx_pause_transition_high[0x20];
1547
1548 u8 rx_pause_transition_low[0x20];
1549
1550 u8 reserved_at_3c0[0x400];
1551 };
1552
1553 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1554 u8 port_transmit_wait_high[0x20];
1555
1556 u8 port_transmit_wait_low[0x20];
1557
1558 u8 reserved_at_40[0x100];
1559
1560 u8 rx_buffer_almost_full_high[0x20];
1561
1562 u8 rx_buffer_almost_full_low[0x20];
1563
1564 u8 rx_buffer_full_high[0x20];
1565
1566 u8 rx_buffer_full_low[0x20];
1567
1568 u8 reserved_at_1c0[0x600];
1569 };
1570
1571 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1572 u8 dot3stats_alignment_errors_high[0x20];
1573
1574 u8 dot3stats_alignment_errors_low[0x20];
1575
1576 u8 dot3stats_fcs_errors_high[0x20];
1577
1578 u8 dot3stats_fcs_errors_low[0x20];
1579
1580 u8 dot3stats_single_collision_frames_high[0x20];
1581
1582 u8 dot3stats_single_collision_frames_low[0x20];
1583
1584 u8 dot3stats_multiple_collision_frames_high[0x20];
1585
1586 u8 dot3stats_multiple_collision_frames_low[0x20];
1587
1588 u8 dot3stats_sqe_test_errors_high[0x20];
1589
1590 u8 dot3stats_sqe_test_errors_low[0x20];
1591
1592 u8 dot3stats_deferred_transmissions_high[0x20];
1593
1594 u8 dot3stats_deferred_transmissions_low[0x20];
1595
1596 u8 dot3stats_late_collisions_high[0x20];
1597
1598 u8 dot3stats_late_collisions_low[0x20];
1599
1600 u8 dot3stats_excessive_collisions_high[0x20];
1601
1602 u8 dot3stats_excessive_collisions_low[0x20];
1603
1604 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1605
1606 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1607
1608 u8 dot3stats_carrier_sense_errors_high[0x20];
1609
1610 u8 dot3stats_carrier_sense_errors_low[0x20];
1611
1612 u8 dot3stats_frame_too_longs_high[0x20];
1613
1614 u8 dot3stats_frame_too_longs_low[0x20];
1615
1616 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1617
1618 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1619
1620 u8 dot3stats_symbol_errors_high[0x20];
1621
1622 u8 dot3stats_symbol_errors_low[0x20];
1623
1624 u8 dot3control_in_unknown_opcodes_high[0x20];
1625
1626 u8 dot3control_in_unknown_opcodes_low[0x20];
1627
1628 u8 dot3in_pause_frames_high[0x20];
1629
1630 u8 dot3in_pause_frames_low[0x20];
1631
1632 u8 dot3out_pause_frames_high[0x20];
1633
1634 u8 dot3out_pause_frames_low[0x20];
1635
1636 u8 reserved_at_400[0x3c0];
1637 };
1638
1639 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1640 u8 ether_stats_drop_events_high[0x20];
1641
1642 u8 ether_stats_drop_events_low[0x20];
1643
1644 u8 ether_stats_octets_high[0x20];
1645
1646 u8 ether_stats_octets_low[0x20];
1647
1648 u8 ether_stats_pkts_high[0x20];
1649
1650 u8 ether_stats_pkts_low[0x20];
1651
1652 u8 ether_stats_broadcast_pkts_high[0x20];
1653
1654 u8 ether_stats_broadcast_pkts_low[0x20];
1655
1656 u8 ether_stats_multicast_pkts_high[0x20];
1657
1658 u8 ether_stats_multicast_pkts_low[0x20];
1659
1660 u8 ether_stats_crc_align_errors_high[0x20];
1661
1662 u8 ether_stats_crc_align_errors_low[0x20];
1663
1664 u8 ether_stats_undersize_pkts_high[0x20];
1665
1666 u8 ether_stats_undersize_pkts_low[0x20];
1667
1668 u8 ether_stats_oversize_pkts_high[0x20];
1669
1670 u8 ether_stats_oversize_pkts_low[0x20];
1671
1672 u8 ether_stats_fragments_high[0x20];
1673
1674 u8 ether_stats_fragments_low[0x20];
1675
1676 u8 ether_stats_jabbers_high[0x20];
1677
1678 u8 ether_stats_jabbers_low[0x20];
1679
1680 u8 ether_stats_collisions_high[0x20];
1681
1682 u8 ether_stats_collisions_low[0x20];
1683
1684 u8 ether_stats_pkts64octets_high[0x20];
1685
1686 u8 ether_stats_pkts64octets_low[0x20];
1687
1688 u8 ether_stats_pkts65to127octets_high[0x20];
1689
1690 u8 ether_stats_pkts65to127octets_low[0x20];
1691
1692 u8 ether_stats_pkts128to255octets_high[0x20];
1693
1694 u8 ether_stats_pkts128to255octets_low[0x20];
1695
1696 u8 ether_stats_pkts256to511octets_high[0x20];
1697
1698 u8 ether_stats_pkts256to511octets_low[0x20];
1699
1700 u8 ether_stats_pkts512to1023octets_high[0x20];
1701
1702 u8 ether_stats_pkts512to1023octets_low[0x20];
1703
1704 u8 ether_stats_pkts1024to1518octets_high[0x20];
1705
1706 u8 ether_stats_pkts1024to1518octets_low[0x20];
1707
1708 u8 ether_stats_pkts1519to2047octets_high[0x20];
1709
1710 u8 ether_stats_pkts1519to2047octets_low[0x20];
1711
1712 u8 ether_stats_pkts2048to4095octets_high[0x20];
1713
1714 u8 ether_stats_pkts2048to4095octets_low[0x20];
1715
1716 u8 ether_stats_pkts4096to8191octets_high[0x20];
1717
1718 u8 ether_stats_pkts4096to8191octets_low[0x20];
1719
1720 u8 ether_stats_pkts8192to10239octets_high[0x20];
1721
1722 u8 ether_stats_pkts8192to10239octets_low[0x20];
1723
1724 u8 reserved_at_540[0x280];
1725 };
1726
1727 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1728 u8 if_in_octets_high[0x20];
1729
1730 u8 if_in_octets_low[0x20];
1731
1732 u8 if_in_ucast_pkts_high[0x20];
1733
1734 u8 if_in_ucast_pkts_low[0x20];
1735
1736 u8 if_in_discards_high[0x20];
1737
1738 u8 if_in_discards_low[0x20];
1739
1740 u8 if_in_errors_high[0x20];
1741
1742 u8 if_in_errors_low[0x20];
1743
1744 u8 if_in_unknown_protos_high[0x20];
1745
1746 u8 if_in_unknown_protos_low[0x20];
1747
1748 u8 if_out_octets_high[0x20];
1749
1750 u8 if_out_octets_low[0x20];
1751
1752 u8 if_out_ucast_pkts_high[0x20];
1753
1754 u8 if_out_ucast_pkts_low[0x20];
1755
1756 u8 if_out_discards_high[0x20];
1757
1758 u8 if_out_discards_low[0x20];
1759
1760 u8 if_out_errors_high[0x20];
1761
1762 u8 if_out_errors_low[0x20];
1763
1764 u8 if_in_multicast_pkts_high[0x20];
1765
1766 u8 if_in_multicast_pkts_low[0x20];
1767
1768 u8 if_in_broadcast_pkts_high[0x20];
1769
1770 u8 if_in_broadcast_pkts_low[0x20];
1771
1772 u8 if_out_multicast_pkts_high[0x20];
1773
1774 u8 if_out_multicast_pkts_low[0x20];
1775
1776 u8 if_out_broadcast_pkts_high[0x20];
1777
1778 u8 if_out_broadcast_pkts_low[0x20];
1779
1780 u8 reserved_at_340[0x480];
1781 };
1782
1783 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1784 u8 a_frames_transmitted_ok_high[0x20];
1785
1786 u8 a_frames_transmitted_ok_low[0x20];
1787
1788 u8 a_frames_received_ok_high[0x20];
1789
1790 u8 a_frames_received_ok_low[0x20];
1791
1792 u8 a_frame_check_sequence_errors_high[0x20];
1793
1794 u8 a_frame_check_sequence_errors_low[0x20];
1795
1796 u8 a_alignment_errors_high[0x20];
1797
1798 u8 a_alignment_errors_low[0x20];
1799
1800 u8 a_octets_transmitted_ok_high[0x20];
1801
1802 u8 a_octets_transmitted_ok_low[0x20];
1803
1804 u8 a_octets_received_ok_high[0x20];
1805
1806 u8 a_octets_received_ok_low[0x20];
1807
1808 u8 a_multicast_frames_xmitted_ok_high[0x20];
1809
1810 u8 a_multicast_frames_xmitted_ok_low[0x20];
1811
1812 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1813
1814 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1815
1816 u8 a_multicast_frames_received_ok_high[0x20];
1817
1818 u8 a_multicast_frames_received_ok_low[0x20];
1819
1820 u8 a_broadcast_frames_received_ok_high[0x20];
1821
1822 u8 a_broadcast_frames_received_ok_low[0x20];
1823
1824 u8 a_in_range_length_errors_high[0x20];
1825
1826 u8 a_in_range_length_errors_low[0x20];
1827
1828 u8 a_out_of_range_length_field_high[0x20];
1829
1830 u8 a_out_of_range_length_field_low[0x20];
1831
1832 u8 a_frame_too_long_errors_high[0x20];
1833
1834 u8 a_frame_too_long_errors_low[0x20];
1835
1836 u8 a_symbol_error_during_carrier_high[0x20];
1837
1838 u8 a_symbol_error_during_carrier_low[0x20];
1839
1840 u8 a_mac_control_frames_transmitted_high[0x20];
1841
1842 u8 a_mac_control_frames_transmitted_low[0x20];
1843
1844 u8 a_mac_control_frames_received_high[0x20];
1845
1846 u8 a_mac_control_frames_received_low[0x20];
1847
1848 u8 a_unsupported_opcodes_received_high[0x20];
1849
1850 u8 a_unsupported_opcodes_received_low[0x20];
1851
1852 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1853
1854 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1855
1856 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1857
1858 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1859
1860 u8 reserved_at_4c0[0x300];
1861 };
1862
1863 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1864 u8 life_time_counter_high[0x20];
1865
1866 u8 life_time_counter_low[0x20];
1867
1868 u8 rx_errors[0x20];
1869
1870 u8 tx_errors[0x20];
1871
1872 u8 l0_to_recovery_eieos[0x20];
1873
1874 u8 l0_to_recovery_ts[0x20];
1875
1876 u8 l0_to_recovery_framing[0x20];
1877
1878 u8 l0_to_recovery_retrain[0x20];
1879
1880 u8 crc_error_dllp[0x20];
1881
1882 u8 crc_error_tlp[0x20];
1883
1884 u8 tx_overflow_buffer_pkt_high[0x20];
1885
1886 u8 tx_overflow_buffer_pkt_low[0x20];
1887
1888 u8 outbound_stalled_reads[0x20];
1889
1890 u8 outbound_stalled_writes[0x20];
1891
1892 u8 outbound_stalled_reads_events[0x20];
1893
1894 u8 outbound_stalled_writes_events[0x20];
1895
1896 u8 reserved_at_200[0x5c0];
1897 };
1898
1899 struct mlx5_ifc_cmd_inter_comp_event_bits {
1900 u8 command_completion_vector[0x20];
1901
1902 u8 reserved_at_20[0xc0];
1903 };
1904
1905 struct mlx5_ifc_stall_vl_event_bits {
1906 u8 reserved_at_0[0x18];
1907 u8 port_num[0x1];
1908 u8 reserved_at_19[0x3];
1909 u8 vl[0x4];
1910
1911 u8 reserved_at_20[0xa0];
1912 };
1913
1914 struct mlx5_ifc_db_bf_congestion_event_bits {
1915 u8 event_subtype[0x8];
1916 u8 reserved_at_8[0x8];
1917 u8 congestion_level[0x8];
1918 u8 reserved_at_18[0x8];
1919
1920 u8 reserved_at_20[0xa0];
1921 };
1922
1923 struct mlx5_ifc_gpio_event_bits {
1924 u8 reserved_at_0[0x60];
1925
1926 u8 gpio_event_hi[0x20];
1927
1928 u8 gpio_event_lo[0x20];
1929
1930 u8 reserved_at_a0[0x40];
1931 };
1932
1933 struct mlx5_ifc_port_state_change_event_bits {
1934 u8 reserved_at_0[0x40];
1935
1936 u8 port_num[0x4];
1937 u8 reserved_at_44[0x1c];
1938
1939 u8 reserved_at_60[0x80];
1940 };
1941
1942 struct mlx5_ifc_dropped_packet_logged_bits {
1943 u8 reserved_at_0[0xe0];
1944 };
1945
1946 enum {
1947 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1948 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1949 };
1950
1951 struct mlx5_ifc_cq_error_bits {
1952 u8 reserved_at_0[0x8];
1953 u8 cqn[0x18];
1954
1955 u8 reserved_at_20[0x20];
1956
1957 u8 reserved_at_40[0x18];
1958 u8 syndrome[0x8];
1959
1960 u8 reserved_at_60[0x80];
1961 };
1962
1963 struct mlx5_ifc_rdma_page_fault_event_bits {
1964 u8 bytes_committed[0x20];
1965
1966 u8 r_key[0x20];
1967
1968 u8 reserved_at_40[0x10];
1969 u8 packet_len[0x10];
1970
1971 u8 rdma_op_len[0x20];
1972
1973 u8 rdma_va[0x40];
1974
1975 u8 reserved_at_c0[0x5];
1976 u8 rdma[0x1];
1977 u8 write[0x1];
1978 u8 requestor[0x1];
1979 u8 qp_number[0x18];
1980 };
1981
1982 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1983 u8 bytes_committed[0x20];
1984
1985 u8 reserved_at_20[0x10];
1986 u8 wqe_index[0x10];
1987
1988 u8 reserved_at_40[0x10];
1989 u8 len[0x10];
1990
1991 u8 reserved_at_60[0x60];
1992
1993 u8 reserved_at_c0[0x5];
1994 u8 rdma[0x1];
1995 u8 write_read[0x1];
1996 u8 requestor[0x1];
1997 u8 qpn[0x18];
1998 };
1999
2000 struct mlx5_ifc_qp_events_bits {
2001 u8 reserved_at_0[0xa0];
2002
2003 u8 type[0x8];
2004 u8 reserved_at_a8[0x18];
2005
2006 u8 reserved_at_c0[0x8];
2007 u8 qpn_rqn_sqn[0x18];
2008 };
2009
2010 struct mlx5_ifc_dct_events_bits {
2011 u8 reserved_at_0[0xc0];
2012
2013 u8 reserved_at_c0[0x8];
2014 u8 dct_number[0x18];
2015 };
2016
2017 struct mlx5_ifc_comp_event_bits {
2018 u8 reserved_at_0[0xc0];
2019
2020 u8 reserved_at_c0[0x8];
2021 u8 cq_number[0x18];
2022 };
2023
2024 enum {
2025 MLX5_QPC_STATE_RST = 0x0,
2026 MLX5_QPC_STATE_INIT = 0x1,
2027 MLX5_QPC_STATE_RTR = 0x2,
2028 MLX5_QPC_STATE_RTS = 0x3,
2029 MLX5_QPC_STATE_SQER = 0x4,
2030 MLX5_QPC_STATE_ERR = 0x6,
2031 MLX5_QPC_STATE_SQD = 0x7,
2032 MLX5_QPC_STATE_SUSPENDED = 0x9,
2033 };
2034
2035 enum {
2036 MLX5_QPC_ST_RC = 0x0,
2037 MLX5_QPC_ST_UC = 0x1,
2038 MLX5_QPC_ST_UD = 0x2,
2039 MLX5_QPC_ST_XRC = 0x3,
2040 MLX5_QPC_ST_DCI = 0x5,
2041 MLX5_QPC_ST_QP0 = 0x7,
2042 MLX5_QPC_ST_QP1 = 0x8,
2043 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2044 MLX5_QPC_ST_REG_UMR = 0xc,
2045 };
2046
2047 enum {
2048 MLX5_QPC_PM_STATE_ARMED = 0x0,
2049 MLX5_QPC_PM_STATE_REARM = 0x1,
2050 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2051 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2052 };
2053
2054 enum {
2055 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2056 };
2057
2058 enum {
2059 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2060 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2061 };
2062
2063 enum {
2064 MLX5_QPC_MTU_256_BYTES = 0x1,
2065 MLX5_QPC_MTU_512_BYTES = 0x2,
2066 MLX5_QPC_MTU_1K_BYTES = 0x3,
2067 MLX5_QPC_MTU_2K_BYTES = 0x4,
2068 MLX5_QPC_MTU_4K_BYTES = 0x5,
2069 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2070 };
2071
2072 enum {
2073 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2074 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2075 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2076 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2077 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2078 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2079 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2080 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2081 };
2082
2083 enum {
2084 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2085 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2086 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2087 };
2088
2089 enum {
2090 MLX5_QPC_CS_RES_DISABLE = 0x0,
2091 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2092 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2093 };
2094
2095 struct mlx5_ifc_qpc_bits {
2096 u8 state[0x4];
2097 u8 lag_tx_port_affinity[0x4];
2098 u8 st[0x8];
2099 u8 reserved_at_10[0x3];
2100 u8 pm_state[0x2];
2101 u8 reserved_at_15[0x3];
2102 u8 offload_type[0x4];
2103 u8 end_padding_mode[0x2];
2104 u8 reserved_at_1e[0x2];
2105
2106 u8 wq_signature[0x1];
2107 u8 block_lb_mc[0x1];
2108 u8 atomic_like_write_en[0x1];
2109 u8 latency_sensitive[0x1];
2110 u8 reserved_at_24[0x1];
2111 u8 drain_sigerr[0x1];
2112 u8 reserved_at_26[0x2];
2113 u8 pd[0x18];
2114
2115 u8 mtu[0x3];
2116 u8 log_msg_max[0x5];
2117 u8 reserved_at_48[0x1];
2118 u8 log_rq_size[0x4];
2119 u8 log_rq_stride[0x3];
2120 u8 no_sq[0x1];
2121 u8 log_sq_size[0x4];
2122 u8 reserved_at_55[0x6];
2123 u8 rlky[0x1];
2124 u8 ulp_stateless_offload_mode[0x4];
2125
2126 u8 counter_set_id[0x8];
2127 u8 uar_page[0x18];
2128
2129 u8 reserved_at_80[0x8];
2130 u8 user_index[0x18];
2131
2132 u8 reserved_at_a0[0x3];
2133 u8 log_page_size[0x5];
2134 u8 remote_qpn[0x18];
2135
2136 struct mlx5_ifc_ads_bits primary_address_path;
2137
2138 struct mlx5_ifc_ads_bits secondary_address_path;
2139
2140 u8 log_ack_req_freq[0x4];
2141 u8 reserved_at_384[0x4];
2142 u8 log_sra_max[0x3];
2143 u8 reserved_at_38b[0x2];
2144 u8 retry_count[0x3];
2145 u8 rnr_retry[0x3];
2146 u8 reserved_at_393[0x1];
2147 u8 fre[0x1];
2148 u8 cur_rnr_retry[0x3];
2149 u8 cur_retry_count[0x3];
2150 u8 reserved_at_39b[0x5];
2151
2152 u8 reserved_at_3a0[0x20];
2153
2154 u8 reserved_at_3c0[0x8];
2155 u8 next_send_psn[0x18];
2156
2157 u8 reserved_at_3e0[0x8];
2158 u8 cqn_snd[0x18];
2159
2160 u8 reserved_at_400[0x8];
2161 u8 deth_sqpn[0x18];
2162
2163 u8 reserved_at_420[0x20];
2164
2165 u8 reserved_at_440[0x8];
2166 u8 last_acked_psn[0x18];
2167
2168 u8 reserved_at_460[0x8];
2169 u8 ssn[0x18];
2170
2171 u8 reserved_at_480[0x8];
2172 u8 log_rra_max[0x3];
2173 u8 reserved_at_48b[0x1];
2174 u8 atomic_mode[0x4];
2175 u8 rre[0x1];
2176 u8 rwe[0x1];
2177 u8 rae[0x1];
2178 u8 reserved_at_493[0x1];
2179 u8 page_offset[0x6];
2180 u8 reserved_at_49a[0x3];
2181 u8 cd_slave_receive[0x1];
2182 u8 cd_slave_send[0x1];
2183 u8 cd_master[0x1];
2184
2185 u8 reserved_at_4a0[0x3];
2186 u8 min_rnr_nak[0x5];
2187 u8 next_rcv_psn[0x18];
2188
2189 u8 reserved_at_4c0[0x8];
2190 u8 xrcd[0x18];
2191
2192 u8 reserved_at_4e0[0x8];
2193 u8 cqn_rcv[0x18];
2194
2195 u8 dbr_addr[0x40];
2196
2197 u8 q_key[0x20];
2198
2199 u8 reserved_at_560[0x5];
2200 u8 rq_type[0x3];
2201 u8 srqn_rmpn_xrqn[0x18];
2202
2203 u8 reserved_at_580[0x8];
2204 u8 rmsn[0x18];
2205
2206 u8 hw_sq_wqebb_counter[0x10];
2207 u8 sw_sq_wqebb_counter[0x10];
2208
2209 u8 hw_rq_counter[0x20];
2210
2211 u8 sw_rq_counter[0x20];
2212
2213 u8 reserved_at_600[0x20];
2214
2215 u8 reserved_at_620[0xf];
2216 u8 cgs[0x1];
2217 u8 cs_req[0x8];
2218 u8 cs_res[0x8];
2219
2220 u8 dc_access_key[0x40];
2221
2222 u8 reserved_at_680[0xc0];
2223 };
2224
2225 struct mlx5_ifc_roce_addr_layout_bits {
2226 u8 source_l3_address[16][0x8];
2227
2228 u8 reserved_at_80[0x3];
2229 u8 vlan_valid[0x1];
2230 u8 vlan_id[0xc];
2231 u8 source_mac_47_32[0x10];
2232
2233 u8 source_mac_31_0[0x20];
2234
2235 u8 reserved_at_c0[0x14];
2236 u8 roce_l3_type[0x4];
2237 u8 roce_version[0x8];
2238
2239 u8 reserved_at_e0[0x20];
2240 };
2241
2242 union mlx5_ifc_hca_cap_union_bits {
2243 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2244 struct mlx5_ifc_odp_cap_bits odp_cap;
2245 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2246 struct mlx5_ifc_roce_cap_bits roce_cap;
2247 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2248 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2249 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2250 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2251 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2252 struct mlx5_ifc_qos_cap_bits qos_cap;
2253 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2254 u8 reserved_at_0[0x8000];
2255 };
2256
2257 enum {
2258 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2259 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2260 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2261 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2262 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2263 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2264 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2265 };
2266
2267 struct mlx5_ifc_flow_context_bits {
2268 u8 reserved_at_0[0x20];
2269
2270 u8 group_id[0x20];
2271
2272 u8 reserved_at_40[0x8];
2273 u8 flow_tag[0x18];
2274
2275 u8 reserved_at_60[0x10];
2276 u8 action[0x10];
2277
2278 u8 reserved_at_80[0x8];
2279 u8 destination_list_size[0x18];
2280
2281 u8 reserved_at_a0[0x8];
2282 u8 flow_counter_list_size[0x18];
2283
2284 u8 encap_id[0x20];
2285
2286 u8 modify_header_id[0x20];
2287
2288 u8 reserved_at_100[0x100];
2289
2290 struct mlx5_ifc_fte_match_param_bits match_value;
2291
2292 u8 reserved_at_1200[0x600];
2293
2294 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2295 };
2296
2297 enum {
2298 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2299 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2300 };
2301
2302 struct mlx5_ifc_xrc_srqc_bits {
2303 u8 state[0x4];
2304 u8 log_xrc_srq_size[0x4];
2305 u8 reserved_at_8[0x18];
2306
2307 u8 wq_signature[0x1];
2308 u8 cont_srq[0x1];
2309 u8 reserved_at_22[0x1];
2310 u8 rlky[0x1];
2311 u8 basic_cyclic_rcv_wqe[0x1];
2312 u8 log_rq_stride[0x3];
2313 u8 xrcd[0x18];
2314
2315 u8 page_offset[0x6];
2316 u8 reserved_at_46[0x2];
2317 u8 cqn[0x18];
2318
2319 u8 reserved_at_60[0x20];
2320
2321 u8 user_index_equal_xrc_srqn[0x1];
2322 u8 reserved_at_81[0x1];
2323 u8 log_page_size[0x6];
2324 u8 user_index[0x18];
2325
2326 u8 reserved_at_a0[0x20];
2327
2328 u8 reserved_at_c0[0x8];
2329 u8 pd[0x18];
2330
2331 u8 lwm[0x10];
2332 u8 wqe_cnt[0x10];
2333
2334 u8 reserved_at_100[0x40];
2335
2336 u8 db_record_addr_h[0x20];
2337
2338 u8 db_record_addr_l[0x1e];
2339 u8 reserved_at_17e[0x2];
2340
2341 u8 reserved_at_180[0x80];
2342 };
2343
2344 struct mlx5_ifc_traffic_counter_bits {
2345 u8 packets[0x40];
2346
2347 u8 octets[0x40];
2348 };
2349
2350 struct mlx5_ifc_tisc_bits {
2351 u8 strict_lag_tx_port_affinity[0x1];
2352 u8 reserved_at_1[0x3];
2353 u8 lag_tx_port_affinity[0x04];
2354
2355 u8 reserved_at_8[0x4];
2356 u8 prio[0x4];
2357 u8 reserved_at_10[0x10];
2358
2359 u8 reserved_at_20[0x100];
2360
2361 u8 reserved_at_120[0x8];
2362 u8 transport_domain[0x18];
2363
2364 u8 reserved_at_140[0x8];
2365 u8 underlay_qpn[0x18];
2366 u8 reserved_at_160[0x3a0];
2367 };
2368
2369 enum {
2370 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2371 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2372 };
2373
2374 enum {
2375 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2376 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2377 };
2378
2379 enum {
2380 MLX5_RX_HASH_FN_NONE = 0x0,
2381 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2382 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2383 };
2384
2385 enum {
2386 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2387 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2388 };
2389
2390 struct mlx5_ifc_tirc_bits {
2391 u8 reserved_at_0[0x20];
2392
2393 u8 disp_type[0x4];
2394 u8 reserved_at_24[0x1c];
2395
2396 u8 reserved_at_40[0x40];
2397
2398 u8 reserved_at_80[0x4];
2399 u8 lro_timeout_period_usecs[0x10];
2400 u8 lro_enable_mask[0x4];
2401 u8 lro_max_ip_payload_size[0x8];
2402
2403 u8 reserved_at_a0[0x40];
2404
2405 u8 reserved_at_e0[0x8];
2406 u8 inline_rqn[0x18];
2407
2408 u8 rx_hash_symmetric[0x1];
2409 u8 reserved_at_101[0x1];
2410 u8 tunneled_offload_en[0x1];
2411 u8 reserved_at_103[0x5];
2412 u8 indirect_table[0x18];
2413
2414 u8 rx_hash_fn[0x4];
2415 u8 reserved_at_124[0x2];
2416 u8 self_lb_block[0x2];
2417 u8 transport_domain[0x18];
2418
2419 u8 rx_hash_toeplitz_key[10][0x20];
2420
2421 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2422
2423 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2424
2425 u8 reserved_at_2c0[0x4c0];
2426 };
2427
2428 enum {
2429 MLX5_SRQC_STATE_GOOD = 0x0,
2430 MLX5_SRQC_STATE_ERROR = 0x1,
2431 };
2432
2433 struct mlx5_ifc_srqc_bits {
2434 u8 state[0x4];
2435 u8 log_srq_size[0x4];
2436 u8 reserved_at_8[0x18];
2437
2438 u8 wq_signature[0x1];
2439 u8 cont_srq[0x1];
2440 u8 reserved_at_22[0x1];
2441 u8 rlky[0x1];
2442 u8 reserved_at_24[0x1];
2443 u8 log_rq_stride[0x3];
2444 u8 xrcd[0x18];
2445
2446 u8 page_offset[0x6];
2447 u8 reserved_at_46[0x2];
2448 u8 cqn[0x18];
2449
2450 u8 reserved_at_60[0x20];
2451
2452 u8 reserved_at_80[0x2];
2453 u8 log_page_size[0x6];
2454 u8 reserved_at_88[0x18];
2455
2456 u8 reserved_at_a0[0x20];
2457
2458 u8 reserved_at_c0[0x8];
2459 u8 pd[0x18];
2460
2461 u8 lwm[0x10];
2462 u8 wqe_cnt[0x10];
2463
2464 u8 reserved_at_100[0x40];
2465
2466 u8 dbr_addr[0x40];
2467
2468 u8 reserved_at_180[0x80];
2469 };
2470
2471 enum {
2472 MLX5_SQC_STATE_RST = 0x0,
2473 MLX5_SQC_STATE_RDY = 0x1,
2474 MLX5_SQC_STATE_ERR = 0x3,
2475 };
2476
2477 struct mlx5_ifc_sqc_bits {
2478 u8 rlky[0x1];
2479 u8 cd_master[0x1];
2480 u8 fre[0x1];
2481 u8 flush_in_error_en[0x1];
2482 u8 allow_multi_pkt_send_wqe[0x1];
2483 u8 min_wqe_inline_mode[0x3];
2484 u8 state[0x4];
2485 u8 reg_umr[0x1];
2486 u8 allow_swp[0x1];
2487 u8 reserved_at_e[0x12];
2488
2489 u8 reserved_at_20[0x8];
2490 u8 user_index[0x18];
2491
2492 u8 reserved_at_40[0x8];
2493 u8 cqn[0x18];
2494
2495 u8 reserved_at_60[0x90];
2496
2497 u8 packet_pacing_rate_limit_index[0x10];
2498 u8 tis_lst_sz[0x10];
2499 u8 reserved_at_110[0x10];
2500
2501 u8 reserved_at_120[0x40];
2502
2503 u8 reserved_at_160[0x8];
2504 u8 tis_num_0[0x18];
2505
2506 struct mlx5_ifc_wq_bits wq;
2507 };
2508
2509 enum {
2510 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2511 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2512 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2513 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2514 };
2515
2516 struct mlx5_ifc_scheduling_context_bits {
2517 u8 element_type[0x8];
2518 u8 reserved_at_8[0x18];
2519
2520 u8 element_attributes[0x20];
2521
2522 u8 parent_element_id[0x20];
2523
2524 u8 reserved_at_60[0x40];
2525
2526 u8 bw_share[0x20];
2527
2528 u8 max_average_bw[0x20];
2529
2530 u8 reserved_at_e0[0x120];
2531 };
2532
2533 struct mlx5_ifc_rqtc_bits {
2534 u8 reserved_at_0[0xa0];
2535
2536 u8 reserved_at_a0[0x10];
2537 u8 rqt_max_size[0x10];
2538
2539 u8 reserved_at_c0[0x10];
2540 u8 rqt_actual_size[0x10];
2541
2542 u8 reserved_at_e0[0x6a0];
2543
2544 struct mlx5_ifc_rq_num_bits rq_num[0];
2545 };
2546
2547 enum {
2548 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2549 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2550 };
2551
2552 enum {
2553 MLX5_RQC_STATE_RST = 0x0,
2554 MLX5_RQC_STATE_RDY = 0x1,
2555 MLX5_RQC_STATE_ERR = 0x3,
2556 };
2557
2558 struct mlx5_ifc_rqc_bits {
2559 u8 rlky[0x1];
2560 u8 delay_drop_en[0x1];
2561 u8 scatter_fcs[0x1];
2562 u8 vsd[0x1];
2563 u8 mem_rq_type[0x4];
2564 u8 state[0x4];
2565 u8 reserved_at_c[0x1];
2566 u8 flush_in_error_en[0x1];
2567 u8 reserved_at_e[0x12];
2568
2569 u8 reserved_at_20[0x8];
2570 u8 user_index[0x18];
2571
2572 u8 reserved_at_40[0x8];
2573 u8 cqn[0x18];
2574
2575 u8 counter_set_id[0x8];
2576 u8 reserved_at_68[0x18];
2577
2578 u8 reserved_at_80[0x8];
2579 u8 rmpn[0x18];
2580
2581 u8 reserved_at_a0[0xe0];
2582
2583 struct mlx5_ifc_wq_bits wq;
2584 };
2585
2586 enum {
2587 MLX5_RMPC_STATE_RDY = 0x1,
2588 MLX5_RMPC_STATE_ERR = 0x3,
2589 };
2590
2591 struct mlx5_ifc_rmpc_bits {
2592 u8 reserved_at_0[0x8];
2593 u8 state[0x4];
2594 u8 reserved_at_c[0x14];
2595
2596 u8 basic_cyclic_rcv_wqe[0x1];
2597 u8 reserved_at_21[0x1f];
2598
2599 u8 reserved_at_40[0x140];
2600
2601 struct mlx5_ifc_wq_bits wq;
2602 };
2603
2604 struct mlx5_ifc_nic_vport_context_bits {
2605 u8 reserved_at_0[0x5];
2606 u8 min_wqe_inline_mode[0x3];
2607 u8 reserved_at_8[0x15];
2608 u8 disable_mc_local_lb[0x1];
2609 u8 disable_uc_local_lb[0x1];
2610 u8 roce_en[0x1];
2611
2612 u8 arm_change_event[0x1];
2613 u8 reserved_at_21[0x1a];
2614 u8 event_on_mtu[0x1];
2615 u8 event_on_promisc_change[0x1];
2616 u8 event_on_vlan_change[0x1];
2617 u8 event_on_mc_address_change[0x1];
2618 u8 event_on_uc_address_change[0x1];
2619
2620 u8 reserved_at_40[0xf0];
2621
2622 u8 mtu[0x10];
2623
2624 u8 system_image_guid[0x40];
2625 u8 port_guid[0x40];
2626 u8 node_guid[0x40];
2627
2628 u8 reserved_at_200[0x140];
2629 u8 qkey_violation_counter[0x10];
2630 u8 reserved_at_350[0x430];
2631
2632 u8 promisc_uc[0x1];
2633 u8 promisc_mc[0x1];
2634 u8 promisc_all[0x1];
2635 u8 reserved_at_783[0x2];
2636 u8 allowed_list_type[0x3];
2637 u8 reserved_at_788[0xc];
2638 u8 allowed_list_size[0xc];
2639
2640 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2641
2642 u8 reserved_at_7e0[0x20];
2643
2644 u8 current_uc_mac_address[0][0x40];
2645 };
2646
2647 enum {
2648 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2649 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2650 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2651 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2652 };
2653
2654 struct mlx5_ifc_mkc_bits {
2655 u8 reserved_at_0[0x1];
2656 u8 free[0x1];
2657 u8 reserved_at_2[0xd];
2658 u8 small_fence_on_rdma_read_response[0x1];
2659 u8 umr_en[0x1];
2660 u8 a[0x1];
2661 u8 rw[0x1];
2662 u8 rr[0x1];
2663 u8 lw[0x1];
2664 u8 lr[0x1];
2665 u8 access_mode[0x2];
2666 u8 reserved_at_18[0x8];
2667
2668 u8 qpn[0x18];
2669 u8 mkey_7_0[0x8];
2670
2671 u8 reserved_at_40[0x20];
2672
2673 u8 length64[0x1];
2674 u8 bsf_en[0x1];
2675 u8 sync_umr[0x1];
2676 u8 reserved_at_63[0x2];
2677 u8 expected_sigerr_count[0x1];
2678 u8 reserved_at_66[0x1];
2679 u8 en_rinval[0x1];
2680 u8 pd[0x18];
2681
2682 u8 start_addr[0x40];
2683
2684 u8 len[0x40];
2685
2686 u8 bsf_octword_size[0x20];
2687
2688 u8 reserved_at_120[0x80];
2689
2690 u8 translations_octword_size[0x20];
2691
2692 u8 reserved_at_1c0[0x1b];
2693 u8 log_page_size[0x5];
2694
2695 u8 reserved_at_1e0[0x20];
2696 };
2697
2698 struct mlx5_ifc_pkey_bits {
2699 u8 reserved_at_0[0x10];
2700 u8 pkey[0x10];
2701 };
2702
2703 struct mlx5_ifc_array128_auto_bits {
2704 u8 array128_auto[16][0x8];
2705 };
2706
2707 struct mlx5_ifc_hca_vport_context_bits {
2708 u8 field_select[0x20];
2709
2710 u8 reserved_at_20[0xe0];
2711
2712 u8 sm_virt_aware[0x1];
2713 u8 has_smi[0x1];
2714 u8 has_raw[0x1];
2715 u8 grh_required[0x1];
2716 u8 reserved_at_104[0xc];
2717 u8 port_physical_state[0x4];
2718 u8 vport_state_policy[0x4];
2719 u8 port_state[0x4];
2720 u8 vport_state[0x4];
2721
2722 u8 reserved_at_120[0x20];
2723
2724 u8 system_image_guid[0x40];
2725
2726 u8 port_guid[0x40];
2727
2728 u8 node_guid[0x40];
2729
2730 u8 cap_mask1[0x20];
2731
2732 u8 cap_mask1_field_select[0x20];
2733
2734 u8 cap_mask2[0x20];
2735
2736 u8 cap_mask2_field_select[0x20];
2737
2738 u8 reserved_at_280[0x80];
2739
2740 u8 lid[0x10];
2741 u8 reserved_at_310[0x4];
2742 u8 init_type_reply[0x4];
2743 u8 lmc[0x3];
2744 u8 subnet_timeout[0x5];
2745
2746 u8 sm_lid[0x10];
2747 u8 sm_sl[0x4];
2748 u8 reserved_at_334[0xc];
2749
2750 u8 qkey_violation_counter[0x10];
2751 u8 pkey_violation_counter[0x10];
2752
2753 u8 reserved_at_360[0xca0];
2754 };
2755
2756 struct mlx5_ifc_esw_vport_context_bits {
2757 u8 reserved_at_0[0x3];
2758 u8 vport_svlan_strip[0x1];
2759 u8 vport_cvlan_strip[0x1];
2760 u8 vport_svlan_insert[0x1];
2761 u8 vport_cvlan_insert[0x2];
2762 u8 reserved_at_8[0x18];
2763
2764 u8 reserved_at_20[0x20];
2765
2766 u8 svlan_cfi[0x1];
2767 u8 svlan_pcp[0x3];
2768 u8 svlan_id[0xc];
2769 u8 cvlan_cfi[0x1];
2770 u8 cvlan_pcp[0x3];
2771 u8 cvlan_id[0xc];
2772
2773 u8 reserved_at_60[0x7a0];
2774 };
2775
2776 enum {
2777 MLX5_EQC_STATUS_OK = 0x0,
2778 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2779 };
2780
2781 enum {
2782 MLX5_EQC_ST_ARMED = 0x9,
2783 MLX5_EQC_ST_FIRED = 0xa,
2784 };
2785
2786 struct mlx5_ifc_eqc_bits {
2787 u8 status[0x4];
2788 u8 reserved_at_4[0x9];
2789 u8 ec[0x1];
2790 u8 oi[0x1];
2791 u8 reserved_at_f[0x5];
2792 u8 st[0x4];
2793 u8 reserved_at_18[0x8];
2794
2795 u8 reserved_at_20[0x20];
2796
2797 u8 reserved_at_40[0x14];
2798 u8 page_offset[0x6];
2799 u8 reserved_at_5a[0x6];
2800
2801 u8 reserved_at_60[0x3];
2802 u8 log_eq_size[0x5];
2803 u8 uar_page[0x18];
2804
2805 u8 reserved_at_80[0x20];
2806
2807 u8 reserved_at_a0[0x18];
2808 u8 intr[0x8];
2809
2810 u8 reserved_at_c0[0x3];
2811 u8 log_page_size[0x5];
2812 u8 reserved_at_c8[0x18];
2813
2814 u8 reserved_at_e0[0x60];
2815
2816 u8 reserved_at_140[0x8];
2817 u8 consumer_counter[0x18];
2818
2819 u8 reserved_at_160[0x8];
2820 u8 producer_counter[0x18];
2821
2822 u8 reserved_at_180[0x80];
2823 };
2824
2825 enum {
2826 MLX5_DCTC_STATE_ACTIVE = 0x0,
2827 MLX5_DCTC_STATE_DRAINING = 0x1,
2828 MLX5_DCTC_STATE_DRAINED = 0x2,
2829 };
2830
2831 enum {
2832 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2833 MLX5_DCTC_CS_RES_NA = 0x1,
2834 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2835 };
2836
2837 enum {
2838 MLX5_DCTC_MTU_256_BYTES = 0x1,
2839 MLX5_DCTC_MTU_512_BYTES = 0x2,
2840 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2841 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2842 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2843 };
2844
2845 struct mlx5_ifc_dctc_bits {
2846 u8 reserved_at_0[0x4];
2847 u8 state[0x4];
2848 u8 reserved_at_8[0x18];
2849
2850 u8 reserved_at_20[0x8];
2851 u8 user_index[0x18];
2852
2853 u8 reserved_at_40[0x8];
2854 u8 cqn[0x18];
2855
2856 u8 counter_set_id[0x8];
2857 u8 atomic_mode[0x4];
2858 u8 rre[0x1];
2859 u8 rwe[0x1];
2860 u8 rae[0x1];
2861 u8 atomic_like_write_en[0x1];
2862 u8 latency_sensitive[0x1];
2863 u8 rlky[0x1];
2864 u8 free_ar[0x1];
2865 u8 reserved_at_73[0xd];
2866
2867 u8 reserved_at_80[0x8];
2868 u8 cs_res[0x8];
2869 u8 reserved_at_90[0x3];
2870 u8 min_rnr_nak[0x5];
2871 u8 reserved_at_98[0x8];
2872
2873 u8 reserved_at_a0[0x8];
2874 u8 srqn_xrqn[0x18];
2875
2876 u8 reserved_at_c0[0x8];
2877 u8 pd[0x18];
2878
2879 u8 tclass[0x8];
2880 u8 reserved_at_e8[0x4];
2881 u8 flow_label[0x14];
2882
2883 u8 dc_access_key[0x40];
2884
2885 u8 reserved_at_140[0x5];
2886 u8 mtu[0x3];
2887 u8 port[0x8];
2888 u8 pkey_index[0x10];
2889
2890 u8 reserved_at_160[0x8];
2891 u8 my_addr_index[0x8];
2892 u8 reserved_at_170[0x8];
2893 u8 hop_limit[0x8];
2894
2895 u8 dc_access_key_violation_count[0x20];
2896
2897 u8 reserved_at_1a0[0x14];
2898 u8 dei_cfi[0x1];
2899 u8 eth_prio[0x3];
2900 u8 ecn[0x2];
2901 u8 dscp[0x6];
2902
2903 u8 reserved_at_1c0[0x40];
2904 };
2905
2906 enum {
2907 MLX5_CQC_STATUS_OK = 0x0,
2908 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2909 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2910 };
2911
2912 enum {
2913 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2914 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2915 };
2916
2917 enum {
2918 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2919 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2920 MLX5_CQC_ST_FIRED = 0xa,
2921 };
2922
2923 enum {
2924 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2925 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2926 MLX5_CQ_PERIOD_NUM_MODES
2927 };
2928
2929 struct mlx5_ifc_cqc_bits {
2930 u8 status[0x4];
2931 u8 reserved_at_4[0x4];
2932 u8 cqe_sz[0x3];
2933 u8 cc[0x1];
2934 u8 reserved_at_c[0x1];
2935 u8 scqe_break_moderation_en[0x1];
2936 u8 oi[0x1];
2937 u8 cq_period_mode[0x2];
2938 u8 cqe_comp_en[0x1];
2939 u8 mini_cqe_res_format[0x2];
2940 u8 st[0x4];
2941 u8 reserved_at_18[0x8];
2942
2943 u8 reserved_at_20[0x20];
2944
2945 u8 reserved_at_40[0x14];
2946 u8 page_offset[0x6];
2947 u8 reserved_at_5a[0x6];
2948
2949 u8 reserved_at_60[0x3];
2950 u8 log_cq_size[0x5];
2951 u8 uar_page[0x18];
2952
2953 u8 reserved_at_80[0x4];
2954 u8 cq_period[0xc];
2955 u8 cq_max_count[0x10];
2956
2957 u8 reserved_at_a0[0x18];
2958 u8 c_eqn[0x8];
2959
2960 u8 reserved_at_c0[0x3];
2961 u8 log_page_size[0x5];
2962 u8 reserved_at_c8[0x18];
2963
2964 u8 reserved_at_e0[0x20];
2965
2966 u8 reserved_at_100[0x8];
2967 u8 last_notified_index[0x18];
2968
2969 u8 reserved_at_120[0x8];
2970 u8 last_solicit_index[0x18];
2971
2972 u8 reserved_at_140[0x8];
2973 u8 consumer_counter[0x18];
2974
2975 u8 reserved_at_160[0x8];
2976 u8 producer_counter[0x18];
2977
2978 u8 reserved_at_180[0x40];
2979
2980 u8 dbr_addr[0x40];
2981 };
2982
2983 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2984 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2985 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2986 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2987 u8 reserved_at_0[0x800];
2988 };
2989
2990 struct mlx5_ifc_query_adapter_param_block_bits {
2991 u8 reserved_at_0[0xc0];
2992
2993 u8 reserved_at_c0[0x8];
2994 u8 ieee_vendor_id[0x18];
2995
2996 u8 reserved_at_e0[0x10];
2997 u8 vsd_vendor_id[0x10];
2998
2999 u8 vsd[208][0x8];
3000
3001 u8 vsd_contd_psid[16][0x8];
3002 };
3003
3004 enum {
3005 MLX5_XRQC_STATE_GOOD = 0x0,
3006 MLX5_XRQC_STATE_ERROR = 0x1,
3007 };
3008
3009 enum {
3010 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3011 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3012 };
3013
3014 enum {
3015 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3016 };
3017
3018 struct mlx5_ifc_tag_matching_topology_context_bits {
3019 u8 log_matching_list_sz[0x4];
3020 u8 reserved_at_4[0xc];
3021 u8 append_next_index[0x10];
3022
3023 u8 sw_phase_cnt[0x10];
3024 u8 hw_phase_cnt[0x10];
3025
3026 u8 reserved_at_40[0x40];
3027 };
3028
3029 struct mlx5_ifc_xrqc_bits {
3030 u8 state[0x4];
3031 u8 rlkey[0x1];
3032 u8 reserved_at_5[0xf];
3033 u8 topology[0x4];
3034 u8 reserved_at_18[0x4];
3035 u8 offload[0x4];
3036
3037 u8 reserved_at_20[0x8];
3038 u8 user_index[0x18];
3039
3040 u8 reserved_at_40[0x8];
3041 u8 cqn[0x18];
3042
3043 u8 reserved_at_60[0xa0];
3044
3045 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3046
3047 u8 reserved_at_180[0x280];
3048
3049 struct mlx5_ifc_wq_bits wq;
3050 };
3051
3052 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3053 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3054 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3055 u8 reserved_at_0[0x20];
3056 };
3057
3058 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3059 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3060 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3061 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3062 u8 reserved_at_0[0x20];
3063 };
3064
3065 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3066 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3067 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3068 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3069 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3070 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3071 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3072 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3073 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3074 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3075 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3076 u8 reserved_at_0[0x7c0];
3077 };
3078
3079 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3080 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3081 u8 reserved_at_0[0x7c0];
3082 };
3083
3084 union mlx5_ifc_event_auto_bits {
3085 struct mlx5_ifc_comp_event_bits comp_event;
3086 struct mlx5_ifc_dct_events_bits dct_events;
3087 struct mlx5_ifc_qp_events_bits qp_events;
3088 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3089 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3090 struct mlx5_ifc_cq_error_bits cq_error;
3091 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3092 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3093 struct mlx5_ifc_gpio_event_bits gpio_event;
3094 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3095 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3096 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3097 u8 reserved_at_0[0xe0];
3098 };
3099
3100 struct mlx5_ifc_health_buffer_bits {
3101 u8 reserved_at_0[0x100];
3102
3103 u8 assert_existptr[0x20];
3104
3105 u8 assert_callra[0x20];
3106
3107 u8 reserved_at_140[0x40];
3108
3109 u8 fw_version[0x20];
3110
3111 u8 hw_id[0x20];
3112
3113 u8 reserved_at_1c0[0x20];
3114
3115 u8 irisc_index[0x8];
3116 u8 synd[0x8];
3117 u8 ext_synd[0x10];
3118 };
3119
3120 struct mlx5_ifc_register_loopback_control_bits {
3121 u8 no_lb[0x1];
3122 u8 reserved_at_1[0x7];
3123 u8 port[0x8];
3124 u8 reserved_at_10[0x10];
3125
3126 u8 reserved_at_20[0x60];
3127 };
3128
3129 struct mlx5_ifc_vport_tc_element_bits {
3130 u8 traffic_class[0x4];
3131 u8 reserved_at_4[0xc];
3132 u8 vport_number[0x10];
3133 };
3134
3135 struct mlx5_ifc_vport_element_bits {
3136 u8 reserved_at_0[0x10];
3137 u8 vport_number[0x10];
3138 };
3139
3140 enum {
3141 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3142 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3143 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3144 };
3145
3146 struct mlx5_ifc_tsar_element_bits {
3147 u8 reserved_at_0[0x8];
3148 u8 tsar_type[0x8];
3149 u8 reserved_at_10[0x10];
3150 };
3151
3152 enum {
3153 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3154 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3155 };
3156
3157 struct mlx5_ifc_teardown_hca_out_bits {
3158 u8 status[0x8];
3159 u8 reserved_at_8[0x18];
3160
3161 u8 syndrome[0x20];
3162
3163 u8 reserved_at_40[0x3f];
3164
3165 u8 force_state[0x1];
3166 };
3167
3168 enum {
3169 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3170 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3171 };
3172
3173 struct mlx5_ifc_teardown_hca_in_bits {
3174 u8 opcode[0x10];
3175 u8 reserved_at_10[0x10];
3176
3177 u8 reserved_at_20[0x10];
3178 u8 op_mod[0x10];
3179
3180 u8 reserved_at_40[0x10];
3181 u8 profile[0x10];
3182
3183 u8 reserved_at_60[0x20];
3184 };
3185
3186 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3187 u8 status[0x8];
3188 u8 reserved_at_8[0x18];
3189
3190 u8 syndrome[0x20];
3191
3192 u8 reserved_at_40[0x40];
3193 };
3194
3195 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3196 u8 opcode[0x10];
3197 u8 reserved_at_10[0x10];
3198
3199 u8 reserved_at_20[0x10];
3200 u8 op_mod[0x10];
3201
3202 u8 reserved_at_40[0x8];
3203 u8 qpn[0x18];
3204
3205 u8 reserved_at_60[0x20];
3206
3207 u8 opt_param_mask[0x20];
3208
3209 u8 reserved_at_a0[0x20];
3210
3211 struct mlx5_ifc_qpc_bits qpc;
3212
3213 u8 reserved_at_800[0x80];
3214 };
3215
3216 struct mlx5_ifc_sqd2rts_qp_out_bits {
3217 u8 status[0x8];
3218 u8 reserved_at_8[0x18];
3219
3220 u8 syndrome[0x20];
3221
3222 u8 reserved_at_40[0x40];
3223 };
3224
3225 struct mlx5_ifc_sqd2rts_qp_in_bits {
3226 u8 opcode[0x10];
3227 u8 reserved_at_10[0x10];
3228
3229 u8 reserved_at_20[0x10];
3230 u8 op_mod[0x10];
3231
3232 u8 reserved_at_40[0x8];
3233 u8 qpn[0x18];
3234
3235 u8 reserved_at_60[0x20];
3236
3237 u8 opt_param_mask[0x20];
3238
3239 u8 reserved_at_a0[0x20];
3240
3241 struct mlx5_ifc_qpc_bits qpc;
3242
3243 u8 reserved_at_800[0x80];
3244 };
3245
3246 struct mlx5_ifc_set_roce_address_out_bits {
3247 u8 status[0x8];
3248 u8 reserved_at_8[0x18];
3249
3250 u8 syndrome[0x20];
3251
3252 u8 reserved_at_40[0x40];
3253 };
3254
3255 struct mlx5_ifc_set_roce_address_in_bits {
3256 u8 opcode[0x10];
3257 u8 reserved_at_10[0x10];
3258
3259 u8 reserved_at_20[0x10];
3260 u8 op_mod[0x10];
3261
3262 u8 roce_address_index[0x10];
3263 u8 reserved_at_50[0x10];
3264
3265 u8 reserved_at_60[0x20];
3266
3267 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3268 };
3269
3270 struct mlx5_ifc_set_mad_demux_out_bits {
3271 u8 status[0x8];
3272 u8 reserved_at_8[0x18];
3273
3274 u8 syndrome[0x20];
3275
3276 u8 reserved_at_40[0x40];
3277 };
3278
3279 enum {
3280 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3281 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3282 };
3283
3284 struct mlx5_ifc_set_mad_demux_in_bits {
3285 u8 opcode[0x10];
3286 u8 reserved_at_10[0x10];
3287
3288 u8 reserved_at_20[0x10];
3289 u8 op_mod[0x10];
3290
3291 u8 reserved_at_40[0x20];
3292
3293 u8 reserved_at_60[0x6];
3294 u8 demux_mode[0x2];
3295 u8 reserved_at_68[0x18];
3296 };
3297
3298 struct mlx5_ifc_set_l2_table_entry_out_bits {
3299 u8 status[0x8];
3300 u8 reserved_at_8[0x18];
3301
3302 u8 syndrome[0x20];
3303
3304 u8 reserved_at_40[0x40];
3305 };
3306
3307 struct mlx5_ifc_set_l2_table_entry_in_bits {
3308 u8 opcode[0x10];
3309 u8 reserved_at_10[0x10];
3310
3311 u8 reserved_at_20[0x10];
3312 u8 op_mod[0x10];
3313
3314 u8 reserved_at_40[0x60];
3315
3316 u8 reserved_at_a0[0x8];
3317 u8 table_index[0x18];
3318
3319 u8 reserved_at_c0[0x20];
3320
3321 u8 reserved_at_e0[0x13];
3322 u8 vlan_valid[0x1];
3323 u8 vlan[0xc];
3324
3325 struct mlx5_ifc_mac_address_layout_bits mac_address;
3326
3327 u8 reserved_at_140[0xc0];
3328 };
3329
3330 struct mlx5_ifc_set_issi_out_bits {
3331 u8 status[0x8];
3332 u8 reserved_at_8[0x18];
3333
3334 u8 syndrome[0x20];
3335
3336 u8 reserved_at_40[0x40];
3337 };
3338
3339 struct mlx5_ifc_set_issi_in_bits {
3340 u8 opcode[0x10];
3341 u8 reserved_at_10[0x10];
3342
3343 u8 reserved_at_20[0x10];
3344 u8 op_mod[0x10];
3345
3346 u8 reserved_at_40[0x10];
3347 u8 current_issi[0x10];
3348
3349 u8 reserved_at_60[0x20];
3350 };
3351
3352 struct mlx5_ifc_set_hca_cap_out_bits {
3353 u8 status[0x8];
3354 u8 reserved_at_8[0x18];
3355
3356 u8 syndrome[0x20];
3357
3358 u8 reserved_at_40[0x40];
3359 };
3360
3361 struct mlx5_ifc_set_hca_cap_in_bits {
3362 u8 opcode[0x10];
3363 u8 reserved_at_10[0x10];
3364
3365 u8 reserved_at_20[0x10];
3366 u8 op_mod[0x10];
3367
3368 u8 reserved_at_40[0x40];
3369
3370 union mlx5_ifc_hca_cap_union_bits capability;
3371 };
3372
3373 enum {
3374 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3375 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3376 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3377 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3378 };
3379
3380 struct mlx5_ifc_set_fte_out_bits {
3381 u8 status[0x8];
3382 u8 reserved_at_8[0x18];
3383
3384 u8 syndrome[0x20];
3385
3386 u8 reserved_at_40[0x40];
3387 };
3388
3389 struct mlx5_ifc_set_fte_in_bits {
3390 u8 opcode[0x10];
3391 u8 reserved_at_10[0x10];
3392
3393 u8 reserved_at_20[0x10];
3394 u8 op_mod[0x10];
3395
3396 u8 other_vport[0x1];
3397 u8 reserved_at_41[0xf];
3398 u8 vport_number[0x10];
3399
3400 u8 reserved_at_60[0x20];
3401
3402 u8 table_type[0x8];
3403 u8 reserved_at_88[0x18];
3404
3405 u8 reserved_at_a0[0x8];
3406 u8 table_id[0x18];
3407
3408 u8 reserved_at_c0[0x18];
3409 u8 modify_enable_mask[0x8];
3410
3411 u8 reserved_at_e0[0x20];
3412
3413 u8 flow_index[0x20];
3414
3415 u8 reserved_at_120[0xe0];
3416
3417 struct mlx5_ifc_flow_context_bits flow_context;
3418 };
3419
3420 struct mlx5_ifc_rts2rts_qp_out_bits {
3421 u8 status[0x8];
3422 u8 reserved_at_8[0x18];
3423
3424 u8 syndrome[0x20];
3425
3426 u8 reserved_at_40[0x40];
3427 };
3428
3429 struct mlx5_ifc_rts2rts_qp_in_bits {
3430 u8 opcode[0x10];
3431 u8 reserved_at_10[0x10];
3432
3433 u8 reserved_at_20[0x10];
3434 u8 op_mod[0x10];
3435
3436 u8 reserved_at_40[0x8];
3437 u8 qpn[0x18];
3438
3439 u8 reserved_at_60[0x20];
3440
3441 u8 opt_param_mask[0x20];
3442
3443 u8 reserved_at_a0[0x20];
3444
3445 struct mlx5_ifc_qpc_bits qpc;
3446
3447 u8 reserved_at_800[0x80];
3448 };
3449
3450 struct mlx5_ifc_rtr2rts_qp_out_bits {
3451 u8 status[0x8];
3452 u8 reserved_at_8[0x18];
3453
3454 u8 syndrome[0x20];
3455
3456 u8 reserved_at_40[0x40];
3457 };
3458
3459 struct mlx5_ifc_rtr2rts_qp_in_bits {
3460 u8 opcode[0x10];
3461 u8 reserved_at_10[0x10];
3462
3463 u8 reserved_at_20[0x10];
3464 u8 op_mod[0x10];
3465
3466 u8 reserved_at_40[0x8];
3467 u8 qpn[0x18];
3468
3469 u8 reserved_at_60[0x20];
3470
3471 u8 opt_param_mask[0x20];
3472
3473 u8 reserved_at_a0[0x20];
3474
3475 struct mlx5_ifc_qpc_bits qpc;
3476
3477 u8 reserved_at_800[0x80];
3478 };
3479
3480 struct mlx5_ifc_rst2init_qp_out_bits {
3481 u8 status[0x8];
3482 u8 reserved_at_8[0x18];
3483
3484 u8 syndrome[0x20];
3485
3486 u8 reserved_at_40[0x40];
3487 };
3488
3489 struct mlx5_ifc_rst2init_qp_in_bits {
3490 u8 opcode[0x10];
3491 u8 reserved_at_10[0x10];
3492
3493 u8 reserved_at_20[0x10];
3494 u8 op_mod[0x10];
3495
3496 u8 reserved_at_40[0x8];
3497 u8 qpn[0x18];
3498
3499 u8 reserved_at_60[0x20];
3500
3501 u8 opt_param_mask[0x20];
3502
3503 u8 reserved_at_a0[0x20];
3504
3505 struct mlx5_ifc_qpc_bits qpc;
3506
3507 u8 reserved_at_800[0x80];
3508 };
3509
3510 struct mlx5_ifc_query_xrq_out_bits {
3511 u8 status[0x8];
3512 u8 reserved_at_8[0x18];
3513
3514 u8 syndrome[0x20];
3515
3516 u8 reserved_at_40[0x40];
3517
3518 struct mlx5_ifc_xrqc_bits xrq_context;
3519 };
3520
3521 struct mlx5_ifc_query_xrq_in_bits {
3522 u8 opcode[0x10];
3523 u8 reserved_at_10[0x10];
3524
3525 u8 reserved_at_20[0x10];
3526 u8 op_mod[0x10];
3527
3528 u8 reserved_at_40[0x8];
3529 u8 xrqn[0x18];
3530
3531 u8 reserved_at_60[0x20];
3532 };
3533
3534 struct mlx5_ifc_query_xrc_srq_out_bits {
3535 u8 status[0x8];
3536 u8 reserved_at_8[0x18];
3537
3538 u8 syndrome[0x20];
3539
3540 u8 reserved_at_40[0x40];
3541
3542 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3543
3544 u8 reserved_at_280[0x600];
3545
3546 u8 pas[0][0x40];
3547 };
3548
3549 struct mlx5_ifc_query_xrc_srq_in_bits {
3550 u8 opcode[0x10];
3551 u8 reserved_at_10[0x10];
3552
3553 u8 reserved_at_20[0x10];
3554 u8 op_mod[0x10];
3555
3556 u8 reserved_at_40[0x8];
3557 u8 xrc_srqn[0x18];
3558
3559 u8 reserved_at_60[0x20];
3560 };
3561
3562 enum {
3563 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3564 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3565 };
3566
3567 struct mlx5_ifc_query_vport_state_out_bits {
3568 u8 status[0x8];
3569 u8 reserved_at_8[0x18];
3570
3571 u8 syndrome[0x20];
3572
3573 u8 reserved_at_40[0x20];
3574
3575 u8 reserved_at_60[0x18];
3576 u8 admin_state[0x4];
3577 u8 state[0x4];
3578 };
3579
3580 enum {
3581 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3582 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3583 };
3584
3585 struct mlx5_ifc_query_vport_state_in_bits {
3586 u8 opcode[0x10];
3587 u8 reserved_at_10[0x10];
3588
3589 u8 reserved_at_20[0x10];
3590 u8 op_mod[0x10];
3591
3592 u8 other_vport[0x1];
3593 u8 reserved_at_41[0xf];
3594 u8 vport_number[0x10];
3595
3596 u8 reserved_at_60[0x20];
3597 };
3598
3599 struct mlx5_ifc_query_vport_counter_out_bits {
3600 u8 status[0x8];
3601 u8 reserved_at_8[0x18];
3602
3603 u8 syndrome[0x20];
3604
3605 u8 reserved_at_40[0x40];
3606
3607 struct mlx5_ifc_traffic_counter_bits received_errors;
3608
3609 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3610
3611 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3612
3613 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3614
3615 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3616
3617 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3618
3619 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3620
3621 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3622
3623 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3624
3625 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3626
3627 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3628
3629 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3630
3631 u8 reserved_at_680[0xa00];
3632 };
3633
3634 enum {
3635 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3636 };
3637
3638 struct mlx5_ifc_query_vport_counter_in_bits {
3639 u8 opcode[0x10];
3640 u8 reserved_at_10[0x10];
3641
3642 u8 reserved_at_20[0x10];
3643 u8 op_mod[0x10];
3644
3645 u8 other_vport[0x1];
3646 u8 reserved_at_41[0xb];
3647 u8 port_num[0x4];
3648 u8 vport_number[0x10];
3649
3650 u8 reserved_at_60[0x60];
3651
3652 u8 clear[0x1];
3653 u8 reserved_at_c1[0x1f];
3654
3655 u8 reserved_at_e0[0x20];
3656 };
3657
3658 struct mlx5_ifc_query_tis_out_bits {
3659 u8 status[0x8];
3660 u8 reserved_at_8[0x18];
3661
3662 u8 syndrome[0x20];
3663
3664 u8 reserved_at_40[0x40];
3665
3666 struct mlx5_ifc_tisc_bits tis_context;
3667 };
3668
3669 struct mlx5_ifc_query_tis_in_bits {
3670 u8 opcode[0x10];
3671 u8 reserved_at_10[0x10];
3672
3673 u8 reserved_at_20[0x10];
3674 u8 op_mod[0x10];
3675
3676 u8 reserved_at_40[0x8];
3677 u8 tisn[0x18];
3678
3679 u8 reserved_at_60[0x20];
3680 };
3681
3682 struct mlx5_ifc_query_tir_out_bits {
3683 u8 status[0x8];
3684 u8 reserved_at_8[0x18];
3685
3686 u8 syndrome[0x20];
3687
3688 u8 reserved_at_40[0xc0];
3689
3690 struct mlx5_ifc_tirc_bits tir_context;
3691 };
3692
3693 struct mlx5_ifc_query_tir_in_bits {
3694 u8 opcode[0x10];
3695 u8 reserved_at_10[0x10];
3696
3697 u8 reserved_at_20[0x10];
3698 u8 op_mod[0x10];
3699
3700 u8 reserved_at_40[0x8];
3701 u8 tirn[0x18];
3702
3703 u8 reserved_at_60[0x20];
3704 };
3705
3706 struct mlx5_ifc_query_srq_out_bits {
3707 u8 status[0x8];
3708 u8 reserved_at_8[0x18];
3709
3710 u8 syndrome[0x20];
3711
3712 u8 reserved_at_40[0x40];
3713
3714 struct mlx5_ifc_srqc_bits srq_context_entry;
3715
3716 u8 reserved_at_280[0x600];
3717
3718 u8 pas[0][0x40];
3719 };
3720
3721 struct mlx5_ifc_query_srq_in_bits {
3722 u8 opcode[0x10];
3723 u8 reserved_at_10[0x10];
3724
3725 u8 reserved_at_20[0x10];
3726 u8 op_mod[0x10];
3727
3728 u8 reserved_at_40[0x8];
3729 u8 srqn[0x18];
3730
3731 u8 reserved_at_60[0x20];
3732 };
3733
3734 struct mlx5_ifc_query_sq_out_bits {
3735 u8 status[0x8];
3736 u8 reserved_at_8[0x18];
3737
3738 u8 syndrome[0x20];
3739
3740 u8 reserved_at_40[0xc0];
3741
3742 struct mlx5_ifc_sqc_bits sq_context;
3743 };
3744
3745 struct mlx5_ifc_query_sq_in_bits {
3746 u8 opcode[0x10];
3747 u8 reserved_at_10[0x10];
3748
3749 u8 reserved_at_20[0x10];
3750 u8 op_mod[0x10];
3751
3752 u8 reserved_at_40[0x8];
3753 u8 sqn[0x18];
3754
3755 u8 reserved_at_60[0x20];
3756 };
3757
3758 struct mlx5_ifc_query_special_contexts_out_bits {
3759 u8 status[0x8];
3760 u8 reserved_at_8[0x18];
3761
3762 u8 syndrome[0x20];
3763
3764 u8 dump_fill_mkey[0x20];
3765
3766 u8 resd_lkey[0x20];
3767
3768 u8 null_mkey[0x20];
3769
3770 u8 reserved_at_a0[0x60];
3771 };
3772
3773 struct mlx5_ifc_query_special_contexts_in_bits {
3774 u8 opcode[0x10];
3775 u8 reserved_at_10[0x10];
3776
3777 u8 reserved_at_20[0x10];
3778 u8 op_mod[0x10];
3779
3780 u8 reserved_at_40[0x40];
3781 };
3782
3783 struct mlx5_ifc_query_scheduling_element_out_bits {
3784 u8 opcode[0x10];
3785 u8 reserved_at_10[0x10];
3786
3787 u8 reserved_at_20[0x10];
3788 u8 op_mod[0x10];
3789
3790 u8 reserved_at_40[0xc0];
3791
3792 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3793
3794 u8 reserved_at_300[0x100];
3795 };
3796
3797 enum {
3798 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3799 };
3800
3801 struct mlx5_ifc_query_scheduling_element_in_bits {
3802 u8 opcode[0x10];
3803 u8 reserved_at_10[0x10];
3804
3805 u8 reserved_at_20[0x10];
3806 u8 op_mod[0x10];
3807
3808 u8 scheduling_hierarchy[0x8];
3809 u8 reserved_at_48[0x18];
3810
3811 u8 scheduling_element_id[0x20];
3812
3813 u8 reserved_at_80[0x180];
3814 };
3815
3816 struct mlx5_ifc_query_rqt_out_bits {
3817 u8 status[0x8];
3818 u8 reserved_at_8[0x18];
3819
3820 u8 syndrome[0x20];
3821
3822 u8 reserved_at_40[0xc0];
3823
3824 struct mlx5_ifc_rqtc_bits rqt_context;
3825 };
3826
3827 struct mlx5_ifc_query_rqt_in_bits {
3828 u8 opcode[0x10];
3829 u8 reserved_at_10[0x10];
3830
3831 u8 reserved_at_20[0x10];
3832 u8 op_mod[0x10];
3833
3834 u8 reserved_at_40[0x8];
3835 u8 rqtn[0x18];
3836
3837 u8 reserved_at_60[0x20];
3838 };
3839
3840 struct mlx5_ifc_query_rq_out_bits {
3841 u8 status[0x8];
3842 u8 reserved_at_8[0x18];
3843
3844 u8 syndrome[0x20];
3845
3846 u8 reserved_at_40[0xc0];
3847
3848 struct mlx5_ifc_rqc_bits rq_context;
3849 };
3850
3851 struct mlx5_ifc_query_rq_in_bits {
3852 u8 opcode[0x10];
3853 u8 reserved_at_10[0x10];
3854
3855 u8 reserved_at_20[0x10];
3856 u8 op_mod[0x10];
3857
3858 u8 reserved_at_40[0x8];
3859 u8 rqn[0x18];
3860
3861 u8 reserved_at_60[0x20];
3862 };
3863
3864 struct mlx5_ifc_query_roce_address_out_bits {
3865 u8 status[0x8];
3866 u8 reserved_at_8[0x18];
3867
3868 u8 syndrome[0x20];
3869
3870 u8 reserved_at_40[0x40];
3871
3872 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3873 };
3874
3875 struct mlx5_ifc_query_roce_address_in_bits {
3876 u8 opcode[0x10];
3877 u8 reserved_at_10[0x10];
3878
3879 u8 reserved_at_20[0x10];
3880 u8 op_mod[0x10];
3881
3882 u8 roce_address_index[0x10];
3883 u8 reserved_at_50[0x10];
3884
3885 u8 reserved_at_60[0x20];
3886 };
3887
3888 struct mlx5_ifc_query_rmp_out_bits {
3889 u8 status[0x8];
3890 u8 reserved_at_8[0x18];
3891
3892 u8 syndrome[0x20];
3893
3894 u8 reserved_at_40[0xc0];
3895
3896 struct mlx5_ifc_rmpc_bits rmp_context;
3897 };
3898
3899 struct mlx5_ifc_query_rmp_in_bits {
3900 u8 opcode[0x10];
3901 u8 reserved_at_10[0x10];
3902
3903 u8 reserved_at_20[0x10];
3904 u8 op_mod[0x10];
3905
3906 u8 reserved_at_40[0x8];
3907 u8 rmpn[0x18];
3908
3909 u8 reserved_at_60[0x20];
3910 };
3911
3912 struct mlx5_ifc_query_qp_out_bits {
3913 u8 status[0x8];
3914 u8 reserved_at_8[0x18];
3915
3916 u8 syndrome[0x20];
3917
3918 u8 reserved_at_40[0x40];
3919
3920 u8 opt_param_mask[0x20];
3921
3922 u8 reserved_at_a0[0x20];
3923
3924 struct mlx5_ifc_qpc_bits qpc;
3925
3926 u8 reserved_at_800[0x80];
3927
3928 u8 pas[0][0x40];
3929 };
3930
3931 struct mlx5_ifc_query_qp_in_bits {
3932 u8 opcode[0x10];
3933 u8 reserved_at_10[0x10];
3934
3935 u8 reserved_at_20[0x10];
3936 u8 op_mod[0x10];
3937
3938 u8 reserved_at_40[0x8];
3939 u8 qpn[0x18];
3940
3941 u8 reserved_at_60[0x20];
3942 };
3943
3944 struct mlx5_ifc_query_q_counter_out_bits {
3945 u8 status[0x8];
3946 u8 reserved_at_8[0x18];
3947
3948 u8 syndrome[0x20];
3949
3950 u8 reserved_at_40[0x40];
3951
3952 u8 rx_write_requests[0x20];
3953
3954 u8 reserved_at_a0[0x20];
3955
3956 u8 rx_read_requests[0x20];
3957
3958 u8 reserved_at_e0[0x20];
3959
3960 u8 rx_atomic_requests[0x20];
3961
3962 u8 reserved_at_120[0x20];
3963
3964 u8 rx_dct_connect[0x20];
3965
3966 u8 reserved_at_160[0x20];
3967
3968 u8 out_of_buffer[0x20];
3969
3970 u8 reserved_at_1a0[0x20];
3971
3972 u8 out_of_sequence[0x20];
3973
3974 u8 reserved_at_1e0[0x20];
3975
3976 u8 duplicate_request[0x20];
3977
3978 u8 reserved_at_220[0x20];
3979
3980 u8 rnr_nak_retry_err[0x20];
3981
3982 u8 reserved_at_260[0x20];
3983
3984 u8 packet_seq_err[0x20];
3985
3986 u8 reserved_at_2a0[0x20];
3987
3988 u8 implied_nak_seq_err[0x20];
3989
3990 u8 reserved_at_2e0[0x20];
3991
3992 u8 local_ack_timeout_err[0x20];
3993
3994 u8 reserved_at_320[0xa0];
3995
3996 u8 resp_local_length_error[0x20];
3997
3998 u8 req_local_length_error[0x20];
3999
4000 u8 resp_local_qp_error[0x20];
4001
4002 u8 local_operation_error[0x20];
4003
4004 u8 resp_local_protection[0x20];
4005
4006 u8 req_local_protection[0x20];
4007
4008 u8 resp_cqe_error[0x20];
4009
4010 u8 req_cqe_error[0x20];
4011
4012 u8 req_mw_binding[0x20];
4013
4014 u8 req_bad_response[0x20];
4015
4016 u8 req_remote_invalid_request[0x20];
4017
4018 u8 resp_remote_invalid_request[0x20];
4019
4020 u8 req_remote_access_errors[0x20];
4021
4022 u8 resp_remote_access_errors[0x20];
4023
4024 u8 req_remote_operation_errors[0x20];
4025
4026 u8 req_transport_retries_exceeded[0x20];
4027
4028 u8 cq_overflow[0x20];
4029
4030 u8 resp_cqe_flush_error[0x20];
4031
4032 u8 req_cqe_flush_error[0x20];
4033
4034 u8 reserved_at_620[0x1e0];
4035 };
4036
4037 struct mlx5_ifc_query_q_counter_in_bits {
4038 u8 opcode[0x10];
4039 u8 reserved_at_10[0x10];
4040
4041 u8 reserved_at_20[0x10];
4042 u8 op_mod[0x10];
4043
4044 u8 reserved_at_40[0x80];
4045
4046 u8 clear[0x1];
4047 u8 reserved_at_c1[0x1f];
4048
4049 u8 reserved_at_e0[0x18];
4050 u8 counter_set_id[0x8];
4051 };
4052
4053 struct mlx5_ifc_query_pages_out_bits {
4054 u8 status[0x8];
4055 u8 reserved_at_8[0x18];
4056
4057 u8 syndrome[0x20];
4058
4059 u8 reserved_at_40[0x10];
4060 u8 function_id[0x10];
4061
4062 u8 num_pages[0x20];
4063 };
4064
4065 enum {
4066 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4067 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4068 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4069 };
4070
4071 struct mlx5_ifc_query_pages_in_bits {
4072 u8 opcode[0x10];
4073 u8 reserved_at_10[0x10];
4074
4075 u8 reserved_at_20[0x10];
4076 u8 op_mod[0x10];
4077
4078 u8 reserved_at_40[0x10];
4079 u8 function_id[0x10];
4080
4081 u8 reserved_at_60[0x20];
4082 };
4083
4084 struct mlx5_ifc_query_nic_vport_context_out_bits {
4085 u8 status[0x8];
4086 u8 reserved_at_8[0x18];
4087
4088 u8 syndrome[0x20];
4089
4090 u8 reserved_at_40[0x40];
4091
4092 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4093 };
4094
4095 struct mlx5_ifc_query_nic_vport_context_in_bits {
4096 u8 opcode[0x10];
4097 u8 reserved_at_10[0x10];
4098
4099 u8 reserved_at_20[0x10];
4100 u8 op_mod[0x10];
4101
4102 u8 other_vport[0x1];
4103 u8 reserved_at_41[0xf];
4104 u8 vport_number[0x10];
4105
4106 u8 reserved_at_60[0x5];
4107 u8 allowed_list_type[0x3];
4108 u8 reserved_at_68[0x18];
4109 };
4110
4111 struct mlx5_ifc_query_mkey_out_bits {
4112 u8 status[0x8];
4113 u8 reserved_at_8[0x18];
4114
4115 u8 syndrome[0x20];
4116
4117 u8 reserved_at_40[0x40];
4118
4119 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4120
4121 u8 reserved_at_280[0x600];
4122
4123 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4124
4125 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4126 };
4127
4128 struct mlx5_ifc_query_mkey_in_bits {
4129 u8 opcode[0x10];
4130 u8 reserved_at_10[0x10];
4131
4132 u8 reserved_at_20[0x10];
4133 u8 op_mod[0x10];
4134
4135 u8 reserved_at_40[0x8];
4136 u8 mkey_index[0x18];
4137
4138 u8 pg_access[0x1];
4139 u8 reserved_at_61[0x1f];
4140 };
4141
4142 struct mlx5_ifc_query_mad_demux_out_bits {
4143 u8 status[0x8];
4144 u8 reserved_at_8[0x18];
4145
4146 u8 syndrome[0x20];
4147
4148 u8 reserved_at_40[0x40];
4149
4150 u8 mad_dumux_parameters_block[0x20];
4151 };
4152
4153 struct mlx5_ifc_query_mad_demux_in_bits {
4154 u8 opcode[0x10];
4155 u8 reserved_at_10[0x10];
4156
4157 u8 reserved_at_20[0x10];
4158 u8 op_mod[0x10];
4159
4160 u8 reserved_at_40[0x40];
4161 };
4162
4163 struct mlx5_ifc_query_l2_table_entry_out_bits {
4164 u8 status[0x8];
4165 u8 reserved_at_8[0x18];
4166
4167 u8 syndrome[0x20];
4168
4169 u8 reserved_at_40[0xa0];
4170
4171 u8 reserved_at_e0[0x13];
4172 u8 vlan_valid[0x1];
4173 u8 vlan[0xc];
4174
4175 struct mlx5_ifc_mac_address_layout_bits mac_address;
4176
4177 u8 reserved_at_140[0xc0];
4178 };
4179
4180 struct mlx5_ifc_query_l2_table_entry_in_bits {
4181 u8 opcode[0x10];
4182 u8 reserved_at_10[0x10];
4183
4184 u8 reserved_at_20[0x10];
4185 u8 op_mod[0x10];
4186
4187 u8 reserved_at_40[0x60];
4188
4189 u8 reserved_at_a0[0x8];
4190 u8 table_index[0x18];
4191
4192 u8 reserved_at_c0[0x140];
4193 };
4194
4195 struct mlx5_ifc_query_issi_out_bits {
4196 u8 status[0x8];
4197 u8 reserved_at_8[0x18];
4198
4199 u8 syndrome[0x20];
4200
4201 u8 reserved_at_40[0x10];
4202 u8 current_issi[0x10];
4203
4204 u8 reserved_at_60[0xa0];
4205
4206 u8 reserved_at_100[76][0x8];
4207 u8 supported_issi_dw0[0x20];
4208 };
4209
4210 struct mlx5_ifc_query_issi_in_bits {
4211 u8 opcode[0x10];
4212 u8 reserved_at_10[0x10];
4213
4214 u8 reserved_at_20[0x10];
4215 u8 op_mod[0x10];
4216
4217 u8 reserved_at_40[0x40];
4218 };
4219
4220 struct mlx5_ifc_set_driver_version_out_bits {
4221 u8 status[0x8];
4222 u8 reserved_0[0x18];
4223
4224 u8 syndrome[0x20];
4225 u8 reserved_1[0x40];
4226 };
4227
4228 struct mlx5_ifc_set_driver_version_in_bits {
4229 u8 opcode[0x10];
4230 u8 reserved_0[0x10];
4231
4232 u8 reserved_1[0x10];
4233 u8 op_mod[0x10];
4234
4235 u8 reserved_2[0x40];
4236 u8 driver_version[64][0x8];
4237 };
4238
4239 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4240 u8 status[0x8];
4241 u8 reserved_at_8[0x18];
4242
4243 u8 syndrome[0x20];
4244
4245 u8 reserved_at_40[0x40];
4246
4247 struct mlx5_ifc_pkey_bits pkey[0];
4248 };
4249
4250 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4251 u8 opcode[0x10];
4252 u8 reserved_at_10[0x10];
4253
4254 u8 reserved_at_20[0x10];
4255 u8 op_mod[0x10];
4256
4257 u8 other_vport[0x1];
4258 u8 reserved_at_41[0xb];
4259 u8 port_num[0x4];
4260 u8 vport_number[0x10];
4261
4262 u8 reserved_at_60[0x10];
4263 u8 pkey_index[0x10];
4264 };
4265
4266 enum {
4267 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4268 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4269 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4270 };
4271
4272 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4273 u8 status[0x8];
4274 u8 reserved_at_8[0x18];
4275
4276 u8 syndrome[0x20];
4277
4278 u8 reserved_at_40[0x20];
4279
4280 u8 gids_num[0x10];
4281 u8 reserved_at_70[0x10];
4282
4283 struct mlx5_ifc_array128_auto_bits gid[0];
4284 };
4285
4286 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4287 u8 opcode[0x10];
4288 u8 reserved_at_10[0x10];
4289
4290 u8 reserved_at_20[0x10];
4291 u8 op_mod[0x10];
4292
4293 u8 other_vport[0x1];
4294 u8 reserved_at_41[0xb];
4295 u8 port_num[0x4];
4296 u8 vport_number[0x10];
4297
4298 u8 reserved_at_60[0x10];
4299 u8 gid_index[0x10];
4300 };
4301
4302 struct mlx5_ifc_query_hca_vport_context_out_bits {
4303 u8 status[0x8];
4304 u8 reserved_at_8[0x18];
4305
4306 u8 syndrome[0x20];
4307
4308 u8 reserved_at_40[0x40];
4309
4310 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4311 };
4312
4313 struct mlx5_ifc_query_hca_vport_context_in_bits {
4314 u8 opcode[0x10];
4315 u8 reserved_at_10[0x10];
4316
4317 u8 reserved_at_20[0x10];
4318 u8 op_mod[0x10];
4319
4320 u8 other_vport[0x1];
4321 u8 reserved_at_41[0xb];
4322 u8 port_num[0x4];
4323 u8 vport_number[0x10];
4324
4325 u8 reserved_at_60[0x20];
4326 };
4327
4328 struct mlx5_ifc_query_hca_cap_out_bits {
4329 u8 status[0x8];
4330 u8 reserved_at_8[0x18];
4331
4332 u8 syndrome[0x20];
4333
4334 u8 reserved_at_40[0x40];
4335
4336 union mlx5_ifc_hca_cap_union_bits capability;
4337 };
4338
4339 struct mlx5_ifc_query_hca_cap_in_bits {
4340 u8 opcode[0x10];
4341 u8 reserved_at_10[0x10];
4342
4343 u8 reserved_at_20[0x10];
4344 u8 op_mod[0x10];
4345
4346 u8 reserved_at_40[0x40];
4347 };
4348
4349 struct mlx5_ifc_query_flow_table_out_bits {
4350 u8 status[0x8];
4351 u8 reserved_at_8[0x18];
4352
4353 u8 syndrome[0x20];
4354
4355 u8 reserved_at_40[0x80];
4356
4357 u8 reserved_at_c0[0x8];
4358 u8 level[0x8];
4359 u8 reserved_at_d0[0x8];
4360 u8 log_size[0x8];
4361
4362 u8 reserved_at_e0[0x120];
4363 };
4364
4365 struct mlx5_ifc_query_flow_table_in_bits {
4366 u8 opcode[0x10];
4367 u8 reserved_at_10[0x10];
4368
4369 u8 reserved_at_20[0x10];
4370 u8 op_mod[0x10];
4371
4372 u8 reserved_at_40[0x40];
4373
4374 u8 table_type[0x8];
4375 u8 reserved_at_88[0x18];
4376
4377 u8 reserved_at_a0[0x8];
4378 u8 table_id[0x18];
4379
4380 u8 reserved_at_c0[0x140];
4381 };
4382
4383 struct mlx5_ifc_query_fte_out_bits {
4384 u8 status[0x8];
4385 u8 reserved_at_8[0x18];
4386
4387 u8 syndrome[0x20];
4388
4389 u8 reserved_at_40[0x1c0];
4390
4391 struct mlx5_ifc_flow_context_bits flow_context;
4392 };
4393
4394 struct mlx5_ifc_query_fte_in_bits {
4395 u8 opcode[0x10];
4396 u8 reserved_at_10[0x10];
4397
4398 u8 reserved_at_20[0x10];
4399 u8 op_mod[0x10];
4400
4401 u8 reserved_at_40[0x40];
4402
4403 u8 table_type[0x8];
4404 u8 reserved_at_88[0x18];
4405
4406 u8 reserved_at_a0[0x8];
4407 u8 table_id[0x18];
4408
4409 u8 reserved_at_c0[0x40];
4410
4411 u8 flow_index[0x20];
4412
4413 u8 reserved_at_120[0xe0];
4414 };
4415
4416 enum {
4417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4418 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4419 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4420 };
4421
4422 struct mlx5_ifc_query_flow_group_out_bits {
4423 u8 status[0x8];
4424 u8 reserved_at_8[0x18];
4425
4426 u8 syndrome[0x20];
4427
4428 u8 reserved_at_40[0xa0];
4429
4430 u8 start_flow_index[0x20];
4431
4432 u8 reserved_at_100[0x20];
4433
4434 u8 end_flow_index[0x20];
4435
4436 u8 reserved_at_140[0xa0];
4437
4438 u8 reserved_at_1e0[0x18];
4439 u8 match_criteria_enable[0x8];
4440
4441 struct mlx5_ifc_fte_match_param_bits match_criteria;
4442
4443 u8 reserved_at_1200[0xe00];
4444 };
4445
4446 struct mlx5_ifc_query_flow_group_in_bits {
4447 u8 opcode[0x10];
4448 u8 reserved_at_10[0x10];
4449
4450 u8 reserved_at_20[0x10];
4451 u8 op_mod[0x10];
4452
4453 u8 reserved_at_40[0x40];
4454
4455 u8 table_type[0x8];
4456 u8 reserved_at_88[0x18];
4457
4458 u8 reserved_at_a0[0x8];
4459 u8 table_id[0x18];
4460
4461 u8 group_id[0x20];
4462
4463 u8 reserved_at_e0[0x120];
4464 };
4465
4466 struct mlx5_ifc_query_flow_counter_out_bits {
4467 u8 status[0x8];
4468 u8 reserved_at_8[0x18];
4469
4470 u8 syndrome[0x20];
4471
4472 u8 reserved_at_40[0x40];
4473
4474 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4475 };
4476
4477 struct mlx5_ifc_query_flow_counter_in_bits {
4478 u8 opcode[0x10];
4479 u8 reserved_at_10[0x10];
4480
4481 u8 reserved_at_20[0x10];
4482 u8 op_mod[0x10];
4483
4484 u8 reserved_at_40[0x80];
4485
4486 u8 clear[0x1];
4487 u8 reserved_at_c1[0xf];
4488 u8 num_of_counters[0x10];
4489
4490 u8 flow_counter_id[0x20];
4491 };
4492
4493 struct mlx5_ifc_query_esw_vport_context_out_bits {
4494 u8 status[0x8];
4495 u8 reserved_at_8[0x18];
4496
4497 u8 syndrome[0x20];
4498
4499 u8 reserved_at_40[0x40];
4500
4501 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4502 };
4503
4504 struct mlx5_ifc_query_esw_vport_context_in_bits {
4505 u8 opcode[0x10];
4506 u8 reserved_at_10[0x10];
4507
4508 u8 reserved_at_20[0x10];
4509 u8 op_mod[0x10];
4510
4511 u8 other_vport[0x1];
4512 u8 reserved_at_41[0xf];
4513 u8 vport_number[0x10];
4514
4515 u8 reserved_at_60[0x20];
4516 };
4517
4518 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4519 u8 status[0x8];
4520 u8 reserved_at_8[0x18];
4521
4522 u8 syndrome[0x20];
4523
4524 u8 reserved_at_40[0x40];
4525 };
4526
4527 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4528 u8 reserved_at_0[0x1c];
4529 u8 vport_cvlan_insert[0x1];
4530 u8 vport_svlan_insert[0x1];
4531 u8 vport_cvlan_strip[0x1];
4532 u8 vport_svlan_strip[0x1];
4533 };
4534
4535 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4536 u8 opcode[0x10];
4537 u8 reserved_at_10[0x10];
4538
4539 u8 reserved_at_20[0x10];
4540 u8 op_mod[0x10];
4541
4542 u8 other_vport[0x1];
4543 u8 reserved_at_41[0xf];
4544 u8 vport_number[0x10];
4545
4546 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4547
4548 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4549 };
4550
4551 struct mlx5_ifc_query_eq_out_bits {
4552 u8 status[0x8];
4553 u8 reserved_at_8[0x18];
4554
4555 u8 syndrome[0x20];
4556
4557 u8 reserved_at_40[0x40];
4558
4559 struct mlx5_ifc_eqc_bits eq_context_entry;
4560
4561 u8 reserved_at_280[0x40];
4562
4563 u8 event_bitmask[0x40];
4564
4565 u8 reserved_at_300[0x580];
4566
4567 u8 pas[0][0x40];
4568 };
4569
4570 struct mlx5_ifc_query_eq_in_bits {
4571 u8 opcode[0x10];
4572 u8 reserved_at_10[0x10];
4573
4574 u8 reserved_at_20[0x10];
4575 u8 op_mod[0x10];
4576
4577 u8 reserved_at_40[0x18];
4578 u8 eq_number[0x8];
4579
4580 u8 reserved_at_60[0x20];
4581 };
4582
4583 struct mlx5_ifc_encap_header_in_bits {
4584 u8 reserved_at_0[0x5];
4585 u8 header_type[0x3];
4586 u8 reserved_at_8[0xe];
4587 u8 encap_header_size[0xa];
4588
4589 u8 reserved_at_20[0x10];
4590 u8 encap_header[2][0x8];
4591
4592 u8 more_encap_header[0][0x8];
4593 };
4594
4595 struct mlx5_ifc_query_encap_header_out_bits {
4596 u8 status[0x8];
4597 u8 reserved_at_8[0x18];
4598
4599 u8 syndrome[0x20];
4600
4601 u8 reserved_at_40[0xa0];
4602
4603 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4604 };
4605
4606 struct mlx5_ifc_query_encap_header_in_bits {
4607 u8 opcode[0x10];
4608 u8 reserved_at_10[0x10];
4609
4610 u8 reserved_at_20[0x10];
4611 u8 op_mod[0x10];
4612
4613 u8 encap_id[0x20];
4614
4615 u8 reserved_at_60[0xa0];
4616 };
4617
4618 struct mlx5_ifc_alloc_encap_header_out_bits {
4619 u8 status[0x8];
4620 u8 reserved_at_8[0x18];
4621
4622 u8 syndrome[0x20];
4623
4624 u8 encap_id[0x20];
4625
4626 u8 reserved_at_60[0x20];
4627 };
4628
4629 struct mlx5_ifc_alloc_encap_header_in_bits {
4630 u8 opcode[0x10];
4631 u8 reserved_at_10[0x10];
4632
4633 u8 reserved_at_20[0x10];
4634 u8 op_mod[0x10];
4635
4636 u8 reserved_at_40[0xa0];
4637
4638 struct mlx5_ifc_encap_header_in_bits encap_header;
4639 };
4640
4641 struct mlx5_ifc_dealloc_encap_header_out_bits {
4642 u8 status[0x8];
4643 u8 reserved_at_8[0x18];
4644
4645 u8 syndrome[0x20];
4646
4647 u8 reserved_at_40[0x40];
4648 };
4649
4650 struct mlx5_ifc_dealloc_encap_header_in_bits {
4651 u8 opcode[0x10];
4652 u8 reserved_at_10[0x10];
4653
4654 u8 reserved_20[0x10];
4655 u8 op_mod[0x10];
4656
4657 u8 encap_id[0x20];
4658
4659 u8 reserved_60[0x20];
4660 };
4661
4662 struct mlx5_ifc_set_action_in_bits {
4663 u8 action_type[0x4];
4664 u8 field[0xc];
4665 u8 reserved_at_10[0x3];
4666 u8 offset[0x5];
4667 u8 reserved_at_18[0x3];
4668 u8 length[0x5];
4669
4670 u8 data[0x20];
4671 };
4672
4673 struct mlx5_ifc_add_action_in_bits {
4674 u8 action_type[0x4];
4675 u8 field[0xc];
4676 u8 reserved_at_10[0x10];
4677
4678 u8 data[0x20];
4679 };
4680
4681 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4682 struct mlx5_ifc_set_action_in_bits set_action_in;
4683 struct mlx5_ifc_add_action_in_bits add_action_in;
4684 u8 reserved_at_0[0x40];
4685 };
4686
4687 enum {
4688 MLX5_ACTION_TYPE_SET = 0x1,
4689 MLX5_ACTION_TYPE_ADD = 0x2,
4690 };
4691
4692 enum {
4693 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4694 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4695 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4696 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4697 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4698 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4699 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4700 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4701 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4702 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4703 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4704 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4705 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4706 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4707 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4708 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4709 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4710 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4711 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4712 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4713 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4714 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4715 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4716 };
4717
4718 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4719 u8 status[0x8];
4720 u8 reserved_at_8[0x18];
4721
4722 u8 syndrome[0x20];
4723
4724 u8 modify_header_id[0x20];
4725
4726 u8 reserved_at_60[0x20];
4727 };
4728
4729 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4730 u8 opcode[0x10];
4731 u8 reserved_at_10[0x10];
4732
4733 u8 reserved_at_20[0x10];
4734 u8 op_mod[0x10];
4735
4736 u8 reserved_at_40[0x20];
4737
4738 u8 table_type[0x8];
4739 u8 reserved_at_68[0x10];
4740 u8 num_of_actions[0x8];
4741
4742 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4743 };
4744
4745 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4746 u8 status[0x8];
4747 u8 reserved_at_8[0x18];
4748
4749 u8 syndrome[0x20];
4750
4751 u8 reserved_at_40[0x40];
4752 };
4753
4754 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4755 u8 opcode[0x10];
4756 u8 reserved_at_10[0x10];
4757
4758 u8 reserved_at_20[0x10];
4759 u8 op_mod[0x10];
4760
4761 u8 modify_header_id[0x20];
4762
4763 u8 reserved_at_60[0x20];
4764 };
4765
4766 struct mlx5_ifc_query_dct_out_bits {
4767 u8 status[0x8];
4768 u8 reserved_at_8[0x18];
4769
4770 u8 syndrome[0x20];
4771
4772 u8 reserved_at_40[0x40];
4773
4774 struct mlx5_ifc_dctc_bits dct_context_entry;
4775
4776 u8 reserved_at_280[0x180];
4777 };
4778
4779 struct mlx5_ifc_query_dct_in_bits {
4780 u8 opcode[0x10];
4781 u8 reserved_at_10[0x10];
4782
4783 u8 reserved_at_20[0x10];
4784 u8 op_mod[0x10];
4785
4786 u8 reserved_at_40[0x8];
4787 u8 dctn[0x18];
4788
4789 u8 reserved_at_60[0x20];
4790 };
4791
4792 struct mlx5_ifc_query_cq_out_bits {
4793 u8 status[0x8];
4794 u8 reserved_at_8[0x18];
4795
4796 u8 syndrome[0x20];
4797
4798 u8 reserved_at_40[0x40];
4799
4800 struct mlx5_ifc_cqc_bits cq_context;
4801
4802 u8 reserved_at_280[0x600];
4803
4804 u8 pas[0][0x40];
4805 };
4806
4807 struct mlx5_ifc_query_cq_in_bits {
4808 u8 opcode[0x10];
4809 u8 reserved_at_10[0x10];
4810
4811 u8 reserved_at_20[0x10];
4812 u8 op_mod[0x10];
4813
4814 u8 reserved_at_40[0x8];
4815 u8 cqn[0x18];
4816
4817 u8 reserved_at_60[0x20];
4818 };
4819
4820 struct mlx5_ifc_query_cong_status_out_bits {
4821 u8 status[0x8];
4822 u8 reserved_at_8[0x18];
4823
4824 u8 syndrome[0x20];
4825
4826 u8 reserved_at_40[0x20];
4827
4828 u8 enable[0x1];
4829 u8 tag_enable[0x1];
4830 u8 reserved_at_62[0x1e];
4831 };
4832
4833 struct mlx5_ifc_query_cong_status_in_bits {
4834 u8 opcode[0x10];
4835 u8 reserved_at_10[0x10];
4836
4837 u8 reserved_at_20[0x10];
4838 u8 op_mod[0x10];
4839
4840 u8 reserved_at_40[0x18];
4841 u8 priority[0x4];
4842 u8 cong_protocol[0x4];
4843
4844 u8 reserved_at_60[0x20];
4845 };
4846
4847 struct mlx5_ifc_query_cong_statistics_out_bits {
4848 u8 status[0x8];
4849 u8 reserved_at_8[0x18];
4850
4851 u8 syndrome[0x20];
4852
4853 u8 reserved_at_40[0x40];
4854
4855 u8 rp_cur_flows[0x20];
4856
4857 u8 sum_flows[0x20];
4858
4859 u8 rp_cnp_ignored_high[0x20];
4860
4861 u8 rp_cnp_ignored_low[0x20];
4862
4863 u8 rp_cnp_handled_high[0x20];
4864
4865 u8 rp_cnp_handled_low[0x20];
4866
4867 u8 reserved_at_140[0x100];
4868
4869 u8 time_stamp_high[0x20];
4870
4871 u8 time_stamp_low[0x20];
4872
4873 u8 accumulators_period[0x20];
4874
4875 u8 np_ecn_marked_roce_packets_high[0x20];
4876
4877 u8 np_ecn_marked_roce_packets_low[0x20];
4878
4879 u8 np_cnp_sent_high[0x20];
4880
4881 u8 np_cnp_sent_low[0x20];
4882
4883 u8 reserved_at_320[0x560];
4884 };
4885
4886 struct mlx5_ifc_query_cong_statistics_in_bits {
4887 u8 opcode[0x10];
4888 u8 reserved_at_10[0x10];
4889
4890 u8 reserved_at_20[0x10];
4891 u8 op_mod[0x10];
4892
4893 u8 clear[0x1];
4894 u8 reserved_at_41[0x1f];
4895
4896 u8 reserved_at_60[0x20];
4897 };
4898
4899 struct mlx5_ifc_query_cong_params_out_bits {
4900 u8 status[0x8];
4901 u8 reserved_at_8[0x18];
4902
4903 u8 syndrome[0x20];
4904
4905 u8 reserved_at_40[0x40];
4906
4907 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4908 };
4909
4910 struct mlx5_ifc_query_cong_params_in_bits {
4911 u8 opcode[0x10];
4912 u8 reserved_at_10[0x10];
4913
4914 u8 reserved_at_20[0x10];
4915 u8 op_mod[0x10];
4916
4917 u8 reserved_at_40[0x1c];
4918 u8 cong_protocol[0x4];
4919
4920 u8 reserved_at_60[0x20];
4921 };
4922
4923 struct mlx5_ifc_query_adapter_out_bits {
4924 u8 status[0x8];
4925 u8 reserved_at_8[0x18];
4926
4927 u8 syndrome[0x20];
4928
4929 u8 reserved_at_40[0x40];
4930
4931 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4932 };
4933
4934 struct mlx5_ifc_query_adapter_in_bits {
4935 u8 opcode[0x10];
4936 u8 reserved_at_10[0x10];
4937
4938 u8 reserved_at_20[0x10];
4939 u8 op_mod[0x10];
4940
4941 u8 reserved_at_40[0x40];
4942 };
4943
4944 struct mlx5_ifc_qp_2rst_out_bits {
4945 u8 status[0x8];
4946 u8 reserved_at_8[0x18];
4947
4948 u8 syndrome[0x20];
4949
4950 u8 reserved_at_40[0x40];
4951 };
4952
4953 struct mlx5_ifc_qp_2rst_in_bits {
4954 u8 opcode[0x10];
4955 u8 reserved_at_10[0x10];
4956
4957 u8 reserved_at_20[0x10];
4958 u8 op_mod[0x10];
4959
4960 u8 reserved_at_40[0x8];
4961 u8 qpn[0x18];
4962
4963 u8 reserved_at_60[0x20];
4964 };
4965
4966 struct mlx5_ifc_qp_2err_out_bits {
4967 u8 status[0x8];
4968 u8 reserved_at_8[0x18];
4969
4970 u8 syndrome[0x20];
4971
4972 u8 reserved_at_40[0x40];
4973 };
4974
4975 struct mlx5_ifc_qp_2err_in_bits {
4976 u8 opcode[0x10];
4977 u8 reserved_at_10[0x10];
4978
4979 u8 reserved_at_20[0x10];
4980 u8 op_mod[0x10];
4981
4982 u8 reserved_at_40[0x8];
4983 u8 qpn[0x18];
4984
4985 u8 reserved_at_60[0x20];
4986 };
4987
4988 struct mlx5_ifc_page_fault_resume_out_bits {
4989 u8 status[0x8];
4990 u8 reserved_at_8[0x18];
4991
4992 u8 syndrome[0x20];
4993
4994 u8 reserved_at_40[0x40];
4995 };
4996
4997 struct mlx5_ifc_page_fault_resume_in_bits {
4998 u8 opcode[0x10];
4999 u8 reserved_at_10[0x10];
5000
5001 u8 reserved_at_20[0x10];
5002 u8 op_mod[0x10];
5003
5004 u8 error[0x1];
5005 u8 reserved_at_41[0x4];
5006 u8 page_fault_type[0x3];
5007 u8 wq_number[0x18];
5008
5009 u8 reserved_at_60[0x8];
5010 u8 token[0x18];
5011 };
5012
5013 struct mlx5_ifc_nop_out_bits {
5014 u8 status[0x8];
5015 u8 reserved_at_8[0x18];
5016
5017 u8 syndrome[0x20];
5018
5019 u8 reserved_at_40[0x40];
5020 };
5021
5022 struct mlx5_ifc_nop_in_bits {
5023 u8 opcode[0x10];
5024 u8 reserved_at_10[0x10];
5025
5026 u8 reserved_at_20[0x10];
5027 u8 op_mod[0x10];
5028
5029 u8 reserved_at_40[0x40];
5030 };
5031
5032 struct mlx5_ifc_modify_vport_state_out_bits {
5033 u8 status[0x8];
5034 u8 reserved_at_8[0x18];
5035
5036 u8 syndrome[0x20];
5037
5038 u8 reserved_at_40[0x40];
5039 };
5040
5041 struct mlx5_ifc_modify_vport_state_in_bits {
5042 u8 opcode[0x10];
5043 u8 reserved_at_10[0x10];
5044
5045 u8 reserved_at_20[0x10];
5046 u8 op_mod[0x10];
5047
5048 u8 other_vport[0x1];
5049 u8 reserved_at_41[0xf];
5050 u8 vport_number[0x10];
5051
5052 u8 reserved_at_60[0x18];
5053 u8 admin_state[0x4];
5054 u8 reserved_at_7c[0x4];
5055 };
5056
5057 struct mlx5_ifc_modify_tis_out_bits {
5058 u8 status[0x8];
5059 u8 reserved_at_8[0x18];
5060
5061 u8 syndrome[0x20];
5062
5063 u8 reserved_at_40[0x40];
5064 };
5065
5066 struct mlx5_ifc_modify_tis_bitmask_bits {
5067 u8 reserved_at_0[0x20];
5068
5069 u8 reserved_at_20[0x1d];
5070 u8 lag_tx_port_affinity[0x1];
5071 u8 strict_lag_tx_port_affinity[0x1];
5072 u8 prio[0x1];
5073 };
5074
5075 struct mlx5_ifc_modify_tis_in_bits {
5076 u8 opcode[0x10];
5077 u8 reserved_at_10[0x10];
5078
5079 u8 reserved_at_20[0x10];
5080 u8 op_mod[0x10];
5081
5082 u8 reserved_at_40[0x8];
5083 u8 tisn[0x18];
5084
5085 u8 reserved_at_60[0x20];
5086
5087 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5088
5089 u8 reserved_at_c0[0x40];
5090
5091 struct mlx5_ifc_tisc_bits ctx;
5092 };
5093
5094 struct mlx5_ifc_modify_tir_bitmask_bits {
5095 u8 reserved_at_0[0x20];
5096
5097 u8 reserved_at_20[0x1b];
5098 u8 self_lb_en[0x1];
5099 u8 reserved_at_3c[0x1];
5100 u8 hash[0x1];
5101 u8 reserved_at_3e[0x1];
5102 u8 lro[0x1];
5103 };
5104
5105 struct mlx5_ifc_modify_tir_out_bits {
5106 u8 status[0x8];
5107 u8 reserved_at_8[0x18];
5108
5109 u8 syndrome[0x20];
5110
5111 u8 reserved_at_40[0x40];
5112 };
5113
5114 struct mlx5_ifc_modify_tir_in_bits {
5115 u8 opcode[0x10];
5116 u8 reserved_at_10[0x10];
5117
5118 u8 reserved_at_20[0x10];
5119 u8 op_mod[0x10];
5120
5121 u8 reserved_at_40[0x8];
5122 u8 tirn[0x18];
5123
5124 u8 reserved_at_60[0x20];
5125
5126 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5127
5128 u8 reserved_at_c0[0x40];
5129
5130 struct mlx5_ifc_tirc_bits ctx;
5131 };
5132
5133 struct mlx5_ifc_modify_sq_out_bits {
5134 u8 status[0x8];
5135 u8 reserved_at_8[0x18];
5136
5137 u8 syndrome[0x20];
5138
5139 u8 reserved_at_40[0x40];
5140 };
5141
5142 struct mlx5_ifc_modify_sq_in_bits {
5143 u8 opcode[0x10];
5144 u8 reserved_at_10[0x10];
5145
5146 u8 reserved_at_20[0x10];
5147 u8 op_mod[0x10];
5148
5149 u8 sq_state[0x4];
5150 u8 reserved_at_44[0x4];
5151 u8 sqn[0x18];
5152
5153 u8 reserved_at_60[0x20];
5154
5155 u8 modify_bitmask[0x40];
5156
5157 u8 reserved_at_c0[0x40];
5158
5159 struct mlx5_ifc_sqc_bits ctx;
5160 };
5161
5162 struct mlx5_ifc_modify_scheduling_element_out_bits {
5163 u8 status[0x8];
5164 u8 reserved_at_8[0x18];
5165
5166 u8 syndrome[0x20];
5167
5168 u8 reserved_at_40[0x1c0];
5169 };
5170
5171 enum {
5172 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5173 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5174 };
5175
5176 struct mlx5_ifc_modify_scheduling_element_in_bits {
5177 u8 opcode[0x10];
5178 u8 reserved_at_10[0x10];
5179
5180 u8 reserved_at_20[0x10];
5181 u8 op_mod[0x10];
5182
5183 u8 scheduling_hierarchy[0x8];
5184 u8 reserved_at_48[0x18];
5185
5186 u8 scheduling_element_id[0x20];
5187
5188 u8 reserved_at_80[0x20];
5189
5190 u8 modify_bitmask[0x20];
5191
5192 u8 reserved_at_c0[0x40];
5193
5194 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5195
5196 u8 reserved_at_300[0x100];
5197 };
5198
5199 struct mlx5_ifc_modify_rqt_out_bits {
5200 u8 status[0x8];
5201 u8 reserved_at_8[0x18];
5202
5203 u8 syndrome[0x20];
5204
5205 u8 reserved_at_40[0x40];
5206 };
5207
5208 struct mlx5_ifc_rqt_bitmask_bits {
5209 u8 reserved_at_0[0x20];
5210
5211 u8 reserved_at_20[0x1f];
5212 u8 rqn_list[0x1];
5213 };
5214
5215 struct mlx5_ifc_modify_rqt_in_bits {
5216 u8 opcode[0x10];
5217 u8 reserved_at_10[0x10];
5218
5219 u8 reserved_at_20[0x10];
5220 u8 op_mod[0x10];
5221
5222 u8 reserved_at_40[0x8];
5223 u8 rqtn[0x18];
5224
5225 u8 reserved_at_60[0x20];
5226
5227 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5228
5229 u8 reserved_at_c0[0x40];
5230
5231 struct mlx5_ifc_rqtc_bits ctx;
5232 };
5233
5234 struct mlx5_ifc_modify_rq_out_bits {
5235 u8 status[0x8];
5236 u8 reserved_at_8[0x18];
5237
5238 u8 syndrome[0x20];
5239
5240 u8 reserved_at_40[0x40];
5241 };
5242
5243 enum {
5244 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5245 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5246 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5247 };
5248
5249 struct mlx5_ifc_modify_rq_in_bits {
5250 u8 opcode[0x10];
5251 u8 reserved_at_10[0x10];
5252
5253 u8 reserved_at_20[0x10];
5254 u8 op_mod[0x10];
5255
5256 u8 rq_state[0x4];
5257 u8 reserved_at_44[0x4];
5258 u8 rqn[0x18];
5259
5260 u8 reserved_at_60[0x20];
5261
5262 u8 modify_bitmask[0x40];
5263
5264 u8 reserved_at_c0[0x40];
5265
5266 struct mlx5_ifc_rqc_bits ctx;
5267 };
5268
5269 struct mlx5_ifc_modify_rmp_out_bits {
5270 u8 status[0x8];
5271 u8 reserved_at_8[0x18];
5272
5273 u8 syndrome[0x20];
5274
5275 u8 reserved_at_40[0x40];
5276 };
5277
5278 struct mlx5_ifc_rmp_bitmask_bits {
5279 u8 reserved_at_0[0x20];
5280
5281 u8 reserved_at_20[0x1f];
5282 u8 lwm[0x1];
5283 };
5284
5285 struct mlx5_ifc_modify_rmp_in_bits {
5286 u8 opcode[0x10];
5287 u8 reserved_at_10[0x10];
5288
5289 u8 reserved_at_20[0x10];
5290 u8 op_mod[0x10];
5291
5292 u8 rmp_state[0x4];
5293 u8 reserved_at_44[0x4];
5294 u8 rmpn[0x18];
5295
5296 u8 reserved_at_60[0x20];
5297
5298 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5299
5300 u8 reserved_at_c0[0x40];
5301
5302 struct mlx5_ifc_rmpc_bits ctx;
5303 };
5304
5305 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5306 u8 status[0x8];
5307 u8 reserved_at_8[0x18];
5308
5309 u8 syndrome[0x20];
5310
5311 u8 reserved_at_40[0x40];
5312 };
5313
5314 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5315 u8 reserved_at_0[0x14];
5316 u8 disable_uc_local_lb[0x1];
5317 u8 disable_mc_local_lb[0x1];
5318 u8 node_guid[0x1];
5319 u8 port_guid[0x1];
5320 u8 min_inline[0x1];
5321 u8 mtu[0x1];
5322 u8 change_event[0x1];
5323 u8 promisc[0x1];
5324 u8 permanent_address[0x1];
5325 u8 addresses_list[0x1];
5326 u8 roce_en[0x1];
5327 u8 reserved_at_1f[0x1];
5328 };
5329
5330 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5331 u8 opcode[0x10];
5332 u8 reserved_at_10[0x10];
5333
5334 u8 reserved_at_20[0x10];
5335 u8 op_mod[0x10];
5336
5337 u8 other_vport[0x1];
5338 u8 reserved_at_41[0xf];
5339 u8 vport_number[0x10];
5340
5341 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5342
5343 u8 reserved_at_80[0x780];
5344
5345 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5346 };
5347
5348 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5349 u8 status[0x8];
5350 u8 reserved_at_8[0x18];
5351
5352 u8 syndrome[0x20];
5353
5354 u8 reserved_at_40[0x40];
5355 };
5356
5357 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5358 u8 opcode[0x10];
5359 u8 reserved_at_10[0x10];
5360
5361 u8 reserved_at_20[0x10];
5362 u8 op_mod[0x10];
5363
5364 u8 other_vport[0x1];
5365 u8 reserved_at_41[0xb];
5366 u8 port_num[0x4];
5367 u8 vport_number[0x10];
5368
5369 u8 reserved_at_60[0x20];
5370
5371 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5372 };
5373
5374 struct mlx5_ifc_modify_cq_out_bits {
5375 u8 status[0x8];
5376 u8 reserved_at_8[0x18];
5377
5378 u8 syndrome[0x20];
5379
5380 u8 reserved_at_40[0x40];
5381 };
5382
5383 enum {
5384 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5385 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5386 };
5387
5388 struct mlx5_ifc_modify_cq_in_bits {
5389 u8 opcode[0x10];
5390 u8 reserved_at_10[0x10];
5391
5392 u8 reserved_at_20[0x10];
5393 u8 op_mod[0x10];
5394
5395 u8 reserved_at_40[0x8];
5396 u8 cqn[0x18];
5397
5398 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5399
5400 struct mlx5_ifc_cqc_bits cq_context;
5401
5402 u8 reserved_at_280[0x60];
5403
5404 u8 cq_umem_valid[0x1];
5405 u8 reserved_at_2e1[0x1f];
5406
5407 u8 reserved_at_300[0x580];
5408
5409 u8 pas[0][0x40];
5410 };
5411
5412 struct mlx5_ifc_modify_cong_status_out_bits {
5413 u8 status[0x8];
5414 u8 reserved_at_8[0x18];
5415
5416 u8 syndrome[0x20];
5417
5418 u8 reserved_at_40[0x40];
5419 };
5420
5421 struct mlx5_ifc_modify_cong_status_in_bits {
5422 u8 opcode[0x10];
5423 u8 reserved_at_10[0x10];
5424
5425 u8 reserved_at_20[0x10];
5426 u8 op_mod[0x10];
5427
5428 u8 reserved_at_40[0x18];
5429 u8 priority[0x4];
5430 u8 cong_protocol[0x4];
5431
5432 u8 enable[0x1];
5433 u8 tag_enable[0x1];
5434 u8 reserved_at_62[0x1e];
5435 };
5436
5437 struct mlx5_ifc_modify_cong_params_out_bits {
5438 u8 status[0x8];
5439 u8 reserved_at_8[0x18];
5440
5441 u8 syndrome[0x20];
5442
5443 u8 reserved_at_40[0x40];
5444 };
5445
5446 struct mlx5_ifc_modify_cong_params_in_bits {
5447 u8 opcode[0x10];
5448 u8 reserved_at_10[0x10];
5449
5450 u8 reserved_at_20[0x10];
5451 u8 op_mod[0x10];
5452
5453 u8 reserved_at_40[0x1c];
5454 u8 cong_protocol[0x4];
5455
5456 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5457
5458 u8 reserved_at_80[0x80];
5459
5460 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5461 };
5462
5463 struct mlx5_ifc_manage_pages_out_bits {
5464 u8 status[0x8];
5465 u8 reserved_at_8[0x18];
5466
5467 u8 syndrome[0x20];
5468
5469 u8 output_num_entries[0x20];
5470
5471 u8 reserved_at_60[0x20];
5472
5473 u8 pas[0][0x40];
5474 };
5475
5476 enum {
5477 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5478 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5479 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5480 };
5481
5482 struct mlx5_ifc_manage_pages_in_bits {
5483 u8 opcode[0x10];
5484 u8 reserved_at_10[0x10];
5485
5486 u8 reserved_at_20[0x10];
5487 u8 op_mod[0x10];
5488
5489 u8 reserved_at_40[0x10];
5490 u8 function_id[0x10];
5491
5492 u8 input_num_entries[0x20];
5493
5494 u8 pas[0][0x40];
5495 };
5496
5497 struct mlx5_ifc_mad_ifc_out_bits {
5498 u8 status[0x8];
5499 u8 reserved_at_8[0x18];
5500
5501 u8 syndrome[0x20];
5502
5503 u8 reserved_at_40[0x40];
5504
5505 u8 response_mad_packet[256][0x8];
5506 };
5507
5508 struct mlx5_ifc_mad_ifc_in_bits {
5509 u8 opcode[0x10];
5510 u8 reserved_at_10[0x10];
5511
5512 u8 reserved_at_20[0x10];
5513 u8 op_mod[0x10];
5514
5515 u8 remote_lid[0x10];
5516 u8 reserved_at_50[0x8];
5517 u8 port[0x8];
5518
5519 u8 reserved_at_60[0x20];
5520
5521 u8 mad[256][0x8];
5522 };
5523
5524 struct mlx5_ifc_init_hca_out_bits {
5525 u8 status[0x8];
5526 u8 reserved_at_8[0x18];
5527
5528 u8 syndrome[0x20];
5529
5530 u8 reserved_at_40[0x40];
5531 };
5532
5533 struct mlx5_ifc_init_hca_in_bits {
5534 u8 opcode[0x10];
5535 u8 reserved_at_10[0x10];
5536
5537 u8 reserved_at_20[0x10];
5538 u8 op_mod[0x10];
5539
5540 u8 reserved_at_40[0x40];
5541 };
5542
5543 struct mlx5_ifc_init2rtr_qp_out_bits {
5544 u8 status[0x8];
5545 u8 reserved_at_8[0x18];
5546
5547 u8 syndrome[0x20];
5548
5549 u8 reserved_at_40[0x40];
5550 };
5551
5552 struct mlx5_ifc_init2rtr_qp_in_bits {
5553 u8 opcode[0x10];
5554 u8 reserved_at_10[0x10];
5555
5556 u8 reserved_at_20[0x10];
5557 u8 op_mod[0x10];
5558
5559 u8 reserved_at_40[0x8];
5560 u8 qpn[0x18];
5561
5562 u8 reserved_at_60[0x20];
5563
5564 u8 opt_param_mask[0x20];
5565
5566 u8 reserved_at_a0[0x20];
5567
5568 struct mlx5_ifc_qpc_bits qpc;
5569
5570 u8 reserved_at_800[0x80];
5571 };
5572
5573 struct mlx5_ifc_init2init_qp_out_bits {
5574 u8 status[0x8];
5575 u8 reserved_at_8[0x18];
5576
5577 u8 syndrome[0x20];
5578
5579 u8 reserved_at_40[0x40];
5580 };
5581
5582 struct mlx5_ifc_init2init_qp_in_bits {
5583 u8 opcode[0x10];
5584 u8 reserved_at_10[0x10];
5585
5586 u8 reserved_at_20[0x10];
5587 u8 op_mod[0x10];
5588
5589 u8 reserved_at_40[0x8];
5590 u8 qpn[0x18];
5591
5592 u8 reserved_at_60[0x20];
5593
5594 u8 opt_param_mask[0x20];
5595
5596 u8 reserved_at_a0[0x20];
5597
5598 struct mlx5_ifc_qpc_bits qpc;
5599
5600 u8 reserved_at_800[0x80];
5601 };
5602
5603 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5604 u8 status[0x8];
5605 u8 reserved_at_8[0x18];
5606
5607 u8 syndrome[0x20];
5608
5609 u8 reserved_at_40[0x40];
5610
5611 u8 packet_headers_log[128][0x8];
5612
5613 u8 packet_syndrome[64][0x8];
5614 };
5615
5616 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5617 u8 opcode[0x10];
5618 u8 reserved_at_10[0x10];
5619
5620 u8 reserved_at_20[0x10];
5621 u8 op_mod[0x10];
5622
5623 u8 reserved_at_40[0x40];
5624 };
5625
5626 struct mlx5_ifc_gen_eqe_in_bits {
5627 u8 opcode[0x10];
5628 u8 reserved_at_10[0x10];
5629
5630 u8 reserved_at_20[0x10];
5631 u8 op_mod[0x10];
5632
5633 u8 reserved_at_40[0x18];
5634 u8 eq_number[0x8];
5635
5636 u8 reserved_at_60[0x20];
5637
5638 u8 eqe[64][0x8];
5639 };
5640
5641 struct mlx5_ifc_gen_eq_out_bits {
5642 u8 status[0x8];
5643 u8 reserved_at_8[0x18];
5644
5645 u8 syndrome[0x20];
5646
5647 u8 reserved_at_40[0x40];
5648 };
5649
5650 struct mlx5_ifc_enable_hca_out_bits {
5651 u8 status[0x8];
5652 u8 reserved_at_8[0x18];
5653
5654 u8 syndrome[0x20];
5655
5656 u8 reserved_at_40[0x20];
5657 };
5658
5659 struct mlx5_ifc_enable_hca_in_bits {
5660 u8 opcode[0x10];
5661 u8 reserved_at_10[0x10];
5662
5663 u8 reserved_at_20[0x10];
5664 u8 op_mod[0x10];
5665
5666 u8 reserved_at_40[0x10];
5667 u8 function_id[0x10];
5668
5669 u8 reserved_at_60[0x20];
5670 };
5671
5672 struct mlx5_ifc_drain_dct_out_bits {
5673 u8 status[0x8];
5674 u8 reserved_at_8[0x18];
5675
5676 u8 syndrome[0x20];
5677
5678 u8 reserved_at_40[0x40];
5679 };
5680
5681 struct mlx5_ifc_drain_dct_in_bits {
5682 u8 opcode[0x10];
5683 u8 reserved_at_10[0x10];
5684
5685 u8 reserved_at_20[0x10];
5686 u8 op_mod[0x10];
5687
5688 u8 reserved_at_40[0x8];
5689 u8 dctn[0x18];
5690
5691 u8 reserved_at_60[0x20];
5692 };
5693
5694 struct mlx5_ifc_disable_hca_out_bits {
5695 u8 status[0x8];
5696 u8 reserved_at_8[0x18];
5697
5698 u8 syndrome[0x20];
5699
5700 u8 reserved_at_40[0x20];
5701 };
5702
5703 struct mlx5_ifc_disable_hca_in_bits {
5704 u8 opcode[0x10];
5705 u8 reserved_at_10[0x10];
5706
5707 u8 reserved_at_20[0x10];
5708 u8 op_mod[0x10];
5709
5710 u8 reserved_at_40[0x10];
5711 u8 function_id[0x10];
5712
5713 u8 reserved_at_60[0x20];
5714 };
5715
5716 struct mlx5_ifc_detach_from_mcg_out_bits {
5717 u8 status[0x8];
5718 u8 reserved_at_8[0x18];
5719
5720 u8 syndrome[0x20];
5721
5722 u8 reserved_at_40[0x40];
5723 };
5724
5725 struct mlx5_ifc_detach_from_mcg_in_bits {
5726 u8 opcode[0x10];
5727 u8 reserved_at_10[0x10];
5728
5729 u8 reserved_at_20[0x10];
5730 u8 op_mod[0x10];
5731
5732 u8 reserved_at_40[0x8];
5733 u8 qpn[0x18];
5734
5735 u8 reserved_at_60[0x20];
5736
5737 u8 multicast_gid[16][0x8];
5738 };
5739
5740 struct mlx5_ifc_destroy_xrq_out_bits {
5741 u8 status[0x8];
5742 u8 reserved_at_8[0x18];
5743
5744 u8 syndrome[0x20];
5745
5746 u8 reserved_at_40[0x40];
5747 };
5748
5749 struct mlx5_ifc_destroy_xrq_in_bits {
5750 u8 opcode[0x10];
5751 u8 reserved_at_10[0x10];
5752
5753 u8 reserved_at_20[0x10];
5754 u8 op_mod[0x10];
5755
5756 u8 reserved_at_40[0x8];
5757 u8 xrqn[0x18];
5758
5759 u8 reserved_at_60[0x20];
5760 };
5761
5762 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5763 u8 status[0x8];
5764 u8 reserved_at_8[0x18];
5765
5766 u8 syndrome[0x20];
5767
5768 u8 reserved_at_40[0x40];
5769 };
5770
5771 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5772 u8 opcode[0x10];
5773 u8 reserved_at_10[0x10];
5774
5775 u8 reserved_at_20[0x10];
5776 u8 op_mod[0x10];
5777
5778 u8 reserved_at_40[0x8];
5779 u8 xrc_srqn[0x18];
5780
5781 u8 reserved_at_60[0x20];
5782 };
5783
5784 struct mlx5_ifc_destroy_tis_out_bits {
5785 u8 status[0x8];
5786 u8 reserved_at_8[0x18];
5787
5788 u8 syndrome[0x20];
5789
5790 u8 reserved_at_40[0x40];
5791 };
5792
5793 struct mlx5_ifc_destroy_tis_in_bits {
5794 u8 opcode[0x10];
5795 u8 reserved_at_10[0x10];
5796
5797 u8 reserved_at_20[0x10];
5798 u8 op_mod[0x10];
5799
5800 u8 reserved_at_40[0x8];
5801 u8 tisn[0x18];
5802
5803 u8 reserved_at_60[0x20];
5804 };
5805
5806 struct mlx5_ifc_destroy_tir_out_bits {
5807 u8 status[0x8];
5808 u8 reserved_at_8[0x18];
5809
5810 u8 syndrome[0x20];
5811
5812 u8 reserved_at_40[0x40];
5813 };
5814
5815 struct mlx5_ifc_destroy_tir_in_bits {
5816 u8 opcode[0x10];
5817 u8 reserved_at_10[0x10];
5818
5819 u8 reserved_at_20[0x10];
5820 u8 op_mod[0x10];
5821
5822 u8 reserved_at_40[0x8];
5823 u8 tirn[0x18];
5824
5825 u8 reserved_at_60[0x20];
5826 };
5827
5828 struct mlx5_ifc_destroy_srq_out_bits {
5829 u8 status[0x8];
5830 u8 reserved_at_8[0x18];
5831
5832 u8 syndrome[0x20];
5833
5834 u8 reserved_at_40[0x40];
5835 };
5836
5837 struct mlx5_ifc_destroy_srq_in_bits {
5838 u8 opcode[0x10];
5839 u8 reserved_at_10[0x10];
5840
5841 u8 reserved_at_20[0x10];
5842 u8 op_mod[0x10];
5843
5844 u8 reserved_at_40[0x8];
5845 u8 srqn[0x18];
5846
5847 u8 reserved_at_60[0x20];
5848 };
5849
5850 struct mlx5_ifc_destroy_sq_out_bits {
5851 u8 status[0x8];
5852 u8 reserved_at_8[0x18];
5853
5854 u8 syndrome[0x20];
5855
5856 u8 reserved_at_40[0x40];
5857 };
5858
5859 struct mlx5_ifc_destroy_sq_in_bits {
5860 u8 opcode[0x10];
5861 u8 reserved_at_10[0x10];
5862
5863 u8 reserved_at_20[0x10];
5864 u8 op_mod[0x10];
5865
5866 u8 reserved_at_40[0x8];
5867 u8 sqn[0x18];
5868
5869 u8 reserved_at_60[0x20];
5870 };
5871
5872 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5873 u8 status[0x8];
5874 u8 reserved_at_8[0x18];
5875
5876 u8 syndrome[0x20];
5877
5878 u8 reserved_at_40[0x1c0];
5879 };
5880
5881 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5882 u8 opcode[0x10];
5883 u8 reserved_at_10[0x10];
5884
5885 u8 reserved_at_20[0x10];
5886 u8 op_mod[0x10];
5887
5888 u8 scheduling_hierarchy[0x8];
5889 u8 reserved_at_48[0x18];
5890
5891 u8 scheduling_element_id[0x20];
5892
5893 u8 reserved_at_80[0x180];
5894 };
5895
5896 struct mlx5_ifc_destroy_rqt_out_bits {
5897 u8 status[0x8];
5898 u8 reserved_at_8[0x18];
5899
5900 u8 syndrome[0x20];
5901
5902 u8 reserved_at_40[0x40];
5903 };
5904
5905 struct mlx5_ifc_destroy_rqt_in_bits {
5906 u8 opcode[0x10];
5907 u8 reserved_at_10[0x10];
5908
5909 u8 reserved_at_20[0x10];
5910 u8 op_mod[0x10];
5911
5912 u8 reserved_at_40[0x8];
5913 u8 rqtn[0x18];
5914
5915 u8 reserved_at_60[0x20];
5916 };
5917
5918 struct mlx5_ifc_destroy_rq_out_bits {
5919 u8 status[0x8];
5920 u8 reserved_at_8[0x18];
5921
5922 u8 syndrome[0x20];
5923
5924 u8 reserved_at_40[0x40];
5925 };
5926
5927 struct mlx5_ifc_destroy_rq_in_bits {
5928 u8 opcode[0x10];
5929 u8 reserved_at_10[0x10];
5930
5931 u8 reserved_at_20[0x10];
5932 u8 op_mod[0x10];
5933
5934 u8 reserved_at_40[0x8];
5935 u8 rqn[0x18];
5936
5937 u8 reserved_at_60[0x20];
5938 };
5939
5940 struct mlx5_ifc_set_delay_drop_params_in_bits {
5941 u8 opcode[0x10];
5942 u8 reserved_at_10[0x10];
5943
5944 u8 reserved_at_20[0x10];
5945 u8 op_mod[0x10];
5946
5947 u8 reserved_at_40[0x20];
5948
5949 u8 reserved_at_60[0x10];
5950 u8 delay_drop_timeout[0x10];
5951 };
5952
5953 struct mlx5_ifc_set_delay_drop_params_out_bits {
5954 u8 status[0x8];
5955 u8 reserved_at_8[0x18];
5956
5957 u8 syndrome[0x20];
5958
5959 u8 reserved_at_40[0x40];
5960 };
5961
5962 struct mlx5_ifc_destroy_rmp_out_bits {
5963 u8 status[0x8];
5964 u8 reserved_at_8[0x18];
5965
5966 u8 syndrome[0x20];
5967
5968 u8 reserved_at_40[0x40];
5969 };
5970
5971 struct mlx5_ifc_destroy_rmp_in_bits {
5972 u8 opcode[0x10];
5973 u8 reserved_at_10[0x10];
5974
5975 u8 reserved_at_20[0x10];
5976 u8 op_mod[0x10];
5977
5978 u8 reserved_at_40[0x8];
5979 u8 rmpn[0x18];
5980
5981 u8 reserved_at_60[0x20];
5982 };
5983
5984 struct mlx5_ifc_destroy_qp_out_bits {
5985 u8 status[0x8];
5986 u8 reserved_at_8[0x18];
5987
5988 u8 syndrome[0x20];
5989
5990 u8 reserved_at_40[0x40];
5991 };
5992
5993 struct mlx5_ifc_destroy_qp_in_bits {
5994 u8 opcode[0x10];
5995 u8 reserved_at_10[0x10];
5996
5997 u8 reserved_at_20[0x10];
5998 u8 op_mod[0x10];
5999
6000 u8 reserved_at_40[0x8];
6001 u8 qpn[0x18];
6002
6003 u8 reserved_at_60[0x20];
6004 };
6005
6006 struct mlx5_ifc_destroy_psv_out_bits {
6007 u8 status[0x8];
6008 u8 reserved_at_8[0x18];
6009
6010 u8 syndrome[0x20];
6011
6012 u8 reserved_at_40[0x40];
6013 };
6014
6015 struct mlx5_ifc_destroy_psv_in_bits {
6016 u8 opcode[0x10];
6017 u8 reserved_at_10[0x10];
6018
6019 u8 reserved_at_20[0x10];
6020 u8 op_mod[0x10];
6021
6022 u8 reserved_at_40[0x8];
6023 u8 psvn[0x18];
6024
6025 u8 reserved_at_60[0x20];
6026 };
6027
6028 struct mlx5_ifc_destroy_mkey_out_bits {
6029 u8 status[0x8];
6030 u8 reserved_at_8[0x18];
6031
6032 u8 syndrome[0x20];
6033
6034 u8 reserved_at_40[0x40];
6035 };
6036
6037 struct mlx5_ifc_destroy_mkey_in_bits {
6038 u8 opcode[0x10];
6039 u8 reserved_at_10[0x10];
6040
6041 u8 reserved_at_20[0x10];
6042 u8 op_mod[0x10];
6043
6044 u8 reserved_at_40[0x8];
6045 u8 mkey_index[0x18];
6046
6047 u8 reserved_at_60[0x20];
6048 };
6049
6050 struct mlx5_ifc_destroy_flow_table_out_bits {
6051 u8 status[0x8];
6052 u8 reserved_at_8[0x18];
6053
6054 u8 syndrome[0x20];
6055
6056 u8 reserved_at_40[0x40];
6057 };
6058
6059 struct mlx5_ifc_destroy_flow_table_in_bits {
6060 u8 opcode[0x10];
6061 u8 reserved_at_10[0x10];
6062
6063 u8 reserved_at_20[0x10];
6064 u8 op_mod[0x10];
6065
6066 u8 other_vport[0x1];
6067 u8 reserved_at_41[0xf];
6068 u8 vport_number[0x10];
6069
6070 u8 reserved_at_60[0x20];
6071
6072 u8 table_type[0x8];
6073 u8 reserved_at_88[0x18];
6074
6075 u8 reserved_at_a0[0x8];
6076 u8 table_id[0x18];
6077
6078 u8 reserved_at_c0[0x140];
6079 };
6080
6081 struct mlx5_ifc_destroy_flow_group_out_bits {
6082 u8 status[0x8];
6083 u8 reserved_at_8[0x18];
6084
6085 u8 syndrome[0x20];
6086
6087 u8 reserved_at_40[0x40];
6088 };
6089
6090 struct mlx5_ifc_destroy_flow_group_in_bits {
6091 u8 opcode[0x10];
6092 u8 reserved_at_10[0x10];
6093
6094 u8 reserved_at_20[0x10];
6095 u8 op_mod[0x10];
6096
6097 u8 other_vport[0x1];
6098 u8 reserved_at_41[0xf];
6099 u8 vport_number[0x10];
6100
6101 u8 reserved_at_60[0x20];
6102
6103 u8 table_type[0x8];
6104 u8 reserved_at_88[0x18];
6105
6106 u8 reserved_at_a0[0x8];
6107 u8 table_id[0x18];
6108
6109 u8 group_id[0x20];
6110
6111 u8 reserved_at_e0[0x120];
6112 };
6113
6114 struct mlx5_ifc_destroy_eq_out_bits {
6115 u8 status[0x8];
6116 u8 reserved_at_8[0x18];
6117
6118 u8 syndrome[0x20];
6119
6120 u8 reserved_at_40[0x40];
6121 };
6122
6123 struct mlx5_ifc_destroy_eq_in_bits {
6124 u8 opcode[0x10];
6125 u8 reserved_at_10[0x10];
6126
6127 u8 reserved_at_20[0x10];
6128 u8 op_mod[0x10];
6129
6130 u8 reserved_at_40[0x18];
6131 u8 eq_number[0x8];
6132
6133 u8 reserved_at_60[0x20];
6134 };
6135
6136 struct mlx5_ifc_destroy_dct_out_bits {
6137 u8 status[0x8];
6138 u8 reserved_at_8[0x18];
6139
6140 u8 syndrome[0x20];
6141
6142 u8 reserved_at_40[0x40];
6143 };
6144
6145 struct mlx5_ifc_destroy_dct_in_bits {
6146 u8 opcode[0x10];
6147 u8 reserved_at_10[0x10];
6148
6149 u8 reserved_at_20[0x10];
6150 u8 op_mod[0x10];
6151
6152 u8 reserved_at_40[0x8];
6153 u8 dctn[0x18];
6154
6155 u8 reserved_at_60[0x20];
6156 };
6157
6158 struct mlx5_ifc_destroy_cq_out_bits {
6159 u8 status[0x8];
6160 u8 reserved_at_8[0x18];
6161
6162 u8 syndrome[0x20];
6163
6164 u8 reserved_at_40[0x40];
6165 };
6166
6167 struct mlx5_ifc_destroy_cq_in_bits {
6168 u8 opcode[0x10];
6169 u8 reserved_at_10[0x10];
6170
6171 u8 reserved_at_20[0x10];
6172 u8 op_mod[0x10];
6173
6174 u8 reserved_at_40[0x8];
6175 u8 cqn[0x18];
6176
6177 u8 reserved_at_60[0x20];
6178 };
6179
6180 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6181 u8 status[0x8];
6182 u8 reserved_at_8[0x18];
6183
6184 u8 syndrome[0x20];
6185
6186 u8 reserved_at_40[0x40];
6187 };
6188
6189 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6190 u8 opcode[0x10];
6191 u8 reserved_at_10[0x10];
6192
6193 u8 reserved_at_20[0x10];
6194 u8 op_mod[0x10];
6195
6196 u8 reserved_at_40[0x20];
6197
6198 u8 reserved_at_60[0x10];
6199 u8 vxlan_udp_port[0x10];
6200 };
6201
6202 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6203 u8 status[0x8];
6204 u8 reserved_at_8[0x18];
6205
6206 u8 syndrome[0x20];
6207
6208 u8 reserved_at_40[0x40];
6209 };
6210
6211 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6212 u8 opcode[0x10];
6213 u8 reserved_at_10[0x10];
6214
6215 u8 reserved_at_20[0x10];
6216 u8 op_mod[0x10];
6217
6218 u8 reserved_at_40[0x60];
6219
6220 u8 reserved_at_a0[0x8];
6221 u8 table_index[0x18];
6222
6223 u8 reserved_at_c0[0x140];
6224 };
6225
6226 struct mlx5_ifc_delete_fte_out_bits {
6227 u8 status[0x8];
6228 u8 reserved_at_8[0x18];
6229
6230 u8 syndrome[0x20];
6231
6232 u8 reserved_at_40[0x40];
6233 };
6234
6235 struct mlx5_ifc_delete_fte_in_bits {
6236 u8 opcode[0x10];
6237 u8 reserved_at_10[0x10];
6238
6239 u8 reserved_at_20[0x10];
6240 u8 op_mod[0x10];
6241
6242 u8 other_vport[0x1];
6243 u8 reserved_at_41[0xf];
6244 u8 vport_number[0x10];
6245
6246 u8 reserved_at_60[0x20];
6247
6248 u8 table_type[0x8];
6249 u8 reserved_at_88[0x18];
6250
6251 u8 reserved_at_a0[0x8];
6252 u8 table_id[0x18];
6253
6254 u8 reserved_at_c0[0x40];
6255
6256 u8 flow_index[0x20];
6257
6258 u8 reserved_at_120[0xe0];
6259 };
6260
6261 struct mlx5_ifc_dealloc_xrcd_out_bits {
6262 u8 status[0x8];
6263 u8 reserved_at_8[0x18];
6264
6265 u8 syndrome[0x20];
6266
6267 u8 reserved_at_40[0x40];
6268 };
6269
6270 struct mlx5_ifc_dealloc_xrcd_in_bits {
6271 u8 opcode[0x10];
6272 u8 reserved_at_10[0x10];
6273
6274 u8 reserved_at_20[0x10];
6275 u8 op_mod[0x10];
6276
6277 u8 reserved_at_40[0x8];
6278 u8 xrcd[0x18];
6279
6280 u8 reserved_at_60[0x20];
6281 };
6282
6283 struct mlx5_ifc_dealloc_uar_out_bits {
6284 u8 status[0x8];
6285 u8 reserved_at_8[0x18];
6286
6287 u8 syndrome[0x20];
6288
6289 u8 reserved_at_40[0x40];
6290 };
6291
6292 struct mlx5_ifc_dealloc_uar_in_bits {
6293 u8 opcode[0x10];
6294 u8 reserved_at_10[0x10];
6295
6296 u8 reserved_at_20[0x10];
6297 u8 op_mod[0x10];
6298
6299 u8 reserved_at_40[0x8];
6300 u8 uar[0x18];
6301
6302 u8 reserved_at_60[0x20];
6303 };
6304
6305 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6306 u8 status[0x8];
6307 u8 reserved_at_8[0x18];
6308
6309 u8 syndrome[0x20];
6310
6311 u8 reserved_at_40[0x40];
6312 };
6313
6314 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6315 u8 opcode[0x10];
6316 u8 reserved_at_10[0x10];
6317
6318 u8 reserved_at_20[0x10];
6319 u8 op_mod[0x10];
6320
6321 u8 reserved_at_40[0x8];
6322 u8 transport_domain[0x18];
6323
6324 u8 reserved_at_60[0x20];
6325 };
6326
6327 struct mlx5_ifc_dealloc_q_counter_out_bits {
6328 u8 status[0x8];
6329 u8 reserved_at_8[0x18];
6330
6331 u8 syndrome[0x20];
6332
6333 u8 reserved_at_40[0x40];
6334 };
6335
6336 struct mlx5_ifc_dealloc_q_counter_in_bits {
6337 u8 opcode[0x10];
6338 u8 reserved_at_10[0x10];
6339
6340 u8 reserved_at_20[0x10];
6341 u8 op_mod[0x10];
6342
6343 u8 reserved_at_40[0x18];
6344 u8 counter_set_id[0x8];
6345
6346 u8 reserved_at_60[0x20];
6347 };
6348
6349 struct mlx5_ifc_dealloc_pd_out_bits {
6350 u8 status[0x8];
6351 u8 reserved_at_8[0x18];
6352
6353 u8 syndrome[0x20];
6354
6355 u8 reserved_at_40[0x40];
6356 };
6357
6358 struct mlx5_ifc_dealloc_pd_in_bits {
6359 u8 opcode[0x10];
6360 u8 reserved_at_10[0x10];
6361
6362 u8 reserved_at_20[0x10];
6363 u8 op_mod[0x10];
6364
6365 u8 reserved_at_40[0x8];
6366 u8 pd[0x18];
6367
6368 u8 reserved_at_60[0x20];
6369 };
6370
6371 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6372 u8 status[0x8];
6373 u8 reserved_at_8[0x18];
6374
6375 u8 syndrome[0x20];
6376
6377 u8 reserved_at_40[0x40];
6378 };
6379
6380 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6381 u8 opcode[0x10];
6382 u8 reserved_at_10[0x10];
6383
6384 u8 reserved_at_20[0x10];
6385 u8 op_mod[0x10];
6386
6387 u8 flow_counter_id[0x20];
6388
6389 u8 reserved_at_60[0x20];
6390 };
6391
6392 struct mlx5_ifc_create_xrq_out_bits {
6393 u8 status[0x8];
6394 u8 reserved_at_8[0x18];
6395
6396 u8 syndrome[0x20];
6397
6398 u8 reserved_at_40[0x8];
6399 u8 xrqn[0x18];
6400
6401 u8 reserved_at_60[0x20];
6402 };
6403
6404 struct mlx5_ifc_create_xrq_in_bits {
6405 u8 opcode[0x10];
6406 u8 reserved_at_10[0x10];
6407
6408 u8 reserved_at_20[0x10];
6409 u8 op_mod[0x10];
6410
6411 u8 reserved_at_40[0x40];
6412
6413 struct mlx5_ifc_xrqc_bits xrq_context;
6414 };
6415
6416 struct mlx5_ifc_create_xrc_srq_out_bits {
6417 u8 status[0x8];
6418 u8 reserved_at_8[0x18];
6419
6420 u8 syndrome[0x20];
6421
6422 u8 reserved_at_40[0x8];
6423 u8 xrc_srqn[0x18];
6424
6425 u8 reserved_at_60[0x20];
6426 };
6427
6428 struct mlx5_ifc_create_xrc_srq_in_bits {
6429 u8 opcode[0x10];
6430 u8 reserved_at_10[0x10];
6431
6432 u8 reserved_at_20[0x10];
6433 u8 op_mod[0x10];
6434
6435 u8 reserved_at_40[0x40];
6436
6437 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6438
6439 u8 reserved_at_280[0x600];
6440
6441 u8 pas[0][0x40];
6442 };
6443
6444 struct mlx5_ifc_create_tis_out_bits {
6445 u8 status[0x8];
6446 u8 reserved_at_8[0x18];
6447
6448 u8 syndrome[0x20];
6449
6450 u8 reserved_at_40[0x8];
6451 u8 tisn[0x18];
6452
6453 u8 reserved_at_60[0x20];
6454 };
6455
6456 struct mlx5_ifc_create_tis_in_bits {
6457 u8 opcode[0x10];
6458 u8 reserved_at_10[0x10];
6459
6460 u8 reserved_at_20[0x10];
6461 u8 op_mod[0x10];
6462
6463 u8 reserved_at_40[0xc0];
6464
6465 struct mlx5_ifc_tisc_bits ctx;
6466 };
6467
6468 struct mlx5_ifc_create_tir_out_bits {
6469 u8 status[0x8];
6470 u8 reserved_at_8[0x18];
6471
6472 u8 syndrome[0x20];
6473
6474 u8 reserved_at_40[0x8];
6475 u8 tirn[0x18];
6476
6477 u8 reserved_at_60[0x20];
6478 };
6479
6480 struct mlx5_ifc_create_tir_in_bits {
6481 u8 opcode[0x10];
6482 u8 reserved_at_10[0x10];
6483
6484 u8 reserved_at_20[0x10];
6485 u8 op_mod[0x10];
6486
6487 u8 reserved_at_40[0xc0];
6488
6489 struct mlx5_ifc_tirc_bits ctx;
6490 };
6491
6492 struct mlx5_ifc_create_srq_out_bits {
6493 u8 status[0x8];
6494 u8 reserved_at_8[0x18];
6495
6496 u8 syndrome[0x20];
6497
6498 u8 reserved_at_40[0x8];
6499 u8 srqn[0x18];
6500
6501 u8 reserved_at_60[0x20];
6502 };
6503
6504 struct mlx5_ifc_create_srq_in_bits {
6505 u8 opcode[0x10];
6506 u8 reserved_at_10[0x10];
6507
6508 u8 reserved_at_20[0x10];
6509 u8 op_mod[0x10];
6510
6511 u8 reserved_at_40[0x40];
6512
6513 struct mlx5_ifc_srqc_bits srq_context_entry;
6514
6515 u8 reserved_at_280[0x600];
6516
6517 u8 pas[0][0x40];
6518 };
6519
6520 struct mlx5_ifc_create_sq_out_bits {
6521 u8 status[0x8];
6522 u8 reserved_at_8[0x18];
6523
6524 u8 syndrome[0x20];
6525
6526 u8 reserved_at_40[0x8];
6527 u8 sqn[0x18];
6528
6529 u8 reserved_at_60[0x20];
6530 };
6531
6532 struct mlx5_ifc_create_sq_in_bits {
6533 u8 opcode[0x10];
6534 u8 reserved_at_10[0x10];
6535
6536 u8 reserved_at_20[0x10];
6537 u8 op_mod[0x10];
6538
6539 u8 reserved_at_40[0xc0];
6540
6541 struct mlx5_ifc_sqc_bits ctx;
6542 };
6543
6544 struct mlx5_ifc_create_scheduling_element_out_bits {
6545 u8 status[0x8];
6546 u8 reserved_at_8[0x18];
6547
6548 u8 syndrome[0x20];
6549
6550 u8 reserved_at_40[0x40];
6551
6552 u8 scheduling_element_id[0x20];
6553
6554 u8 reserved_at_a0[0x160];
6555 };
6556
6557 struct mlx5_ifc_create_scheduling_element_in_bits {
6558 u8 opcode[0x10];
6559 u8 reserved_at_10[0x10];
6560
6561 u8 reserved_at_20[0x10];
6562 u8 op_mod[0x10];
6563
6564 u8 scheduling_hierarchy[0x8];
6565 u8 reserved_at_48[0x18];
6566
6567 u8 reserved_at_60[0xa0];
6568
6569 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6570
6571 u8 reserved_at_300[0x100];
6572 };
6573
6574 struct mlx5_ifc_create_rqt_out_bits {
6575 u8 status[0x8];
6576 u8 reserved_at_8[0x18];
6577
6578 u8 syndrome[0x20];
6579
6580 u8 reserved_at_40[0x8];
6581 u8 rqtn[0x18];
6582
6583 u8 reserved_at_60[0x20];
6584 };
6585
6586 struct mlx5_ifc_create_rqt_in_bits {
6587 u8 opcode[0x10];
6588 u8 reserved_at_10[0x10];
6589
6590 u8 reserved_at_20[0x10];
6591 u8 op_mod[0x10];
6592
6593 u8 reserved_at_40[0xc0];
6594
6595 struct mlx5_ifc_rqtc_bits rqt_context;
6596 };
6597
6598 struct mlx5_ifc_create_rq_out_bits {
6599 u8 status[0x8];
6600 u8 reserved_at_8[0x18];
6601
6602 u8 syndrome[0x20];
6603
6604 u8 reserved_at_40[0x8];
6605 u8 rqn[0x18];
6606
6607 u8 reserved_at_60[0x20];
6608 };
6609
6610 struct mlx5_ifc_create_rq_in_bits {
6611 u8 opcode[0x10];
6612 u8 reserved_at_10[0x10];
6613
6614 u8 reserved_at_20[0x10];
6615 u8 op_mod[0x10];
6616
6617 u8 reserved_at_40[0xc0];
6618
6619 struct mlx5_ifc_rqc_bits ctx;
6620 };
6621
6622 struct mlx5_ifc_create_rmp_out_bits {
6623 u8 status[0x8];
6624 u8 reserved_at_8[0x18];
6625
6626 u8 syndrome[0x20];
6627
6628 u8 reserved_at_40[0x8];
6629 u8 rmpn[0x18];
6630
6631 u8 reserved_at_60[0x20];
6632 };
6633
6634 struct mlx5_ifc_create_rmp_in_bits {
6635 u8 opcode[0x10];
6636 u8 reserved_at_10[0x10];
6637
6638 u8 reserved_at_20[0x10];
6639 u8 op_mod[0x10];
6640
6641 u8 reserved_at_40[0xc0];
6642
6643 struct mlx5_ifc_rmpc_bits ctx;
6644 };
6645
6646 struct mlx5_ifc_create_qp_out_bits {
6647 u8 status[0x8];
6648 u8 reserved_at_8[0x18];
6649
6650 u8 syndrome[0x20];
6651
6652 u8 reserved_at_40[0x8];
6653 u8 qpn[0x18];
6654
6655 u8 reserved_at_60[0x20];
6656 };
6657
6658 struct mlx5_ifc_create_qp_in_bits {
6659 u8 opcode[0x10];
6660 u8 reserved_at_10[0x10];
6661
6662 u8 reserved_at_20[0x10];
6663 u8 op_mod[0x10];
6664
6665 u8 reserved_at_40[0x40];
6666
6667 u8 opt_param_mask[0x20];
6668
6669 u8 reserved_at_a0[0x20];
6670
6671 struct mlx5_ifc_qpc_bits qpc;
6672
6673 u8 reserved_at_800[0x80];
6674
6675 u8 pas[0][0x40];
6676 };
6677
6678 struct mlx5_ifc_create_psv_out_bits {
6679 u8 status[0x8];
6680 u8 reserved_at_8[0x18];
6681
6682 u8 syndrome[0x20];
6683
6684 u8 reserved_at_40[0x40];
6685
6686 u8 reserved_at_80[0x8];
6687 u8 psv0_index[0x18];
6688
6689 u8 reserved_at_a0[0x8];
6690 u8 psv1_index[0x18];
6691
6692 u8 reserved_at_c0[0x8];
6693 u8 psv2_index[0x18];
6694
6695 u8 reserved_at_e0[0x8];
6696 u8 psv3_index[0x18];
6697 };
6698
6699 struct mlx5_ifc_create_psv_in_bits {
6700 u8 opcode[0x10];
6701 u8 reserved_at_10[0x10];
6702
6703 u8 reserved_at_20[0x10];
6704 u8 op_mod[0x10];
6705
6706 u8 num_psv[0x4];
6707 u8 reserved_at_44[0x4];
6708 u8 pd[0x18];
6709
6710 u8 reserved_at_60[0x20];
6711 };
6712
6713 struct mlx5_ifc_create_mkey_out_bits {
6714 u8 status[0x8];
6715 u8 reserved_at_8[0x18];
6716
6717 u8 syndrome[0x20];
6718
6719 u8 reserved_at_40[0x8];
6720 u8 mkey_index[0x18];
6721
6722 u8 reserved_at_60[0x20];
6723 };
6724
6725 struct mlx5_ifc_create_mkey_in_bits {
6726 u8 opcode[0x10];
6727 u8 reserved_at_10[0x10];
6728
6729 u8 reserved_at_20[0x10];
6730 u8 op_mod[0x10];
6731
6732 u8 reserved_at_40[0x20];
6733
6734 u8 pg_access[0x1];
6735 u8 reserved_at_61[0x1f];
6736
6737 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6738
6739 u8 reserved_at_280[0x80];
6740
6741 u8 translations_octword_actual_size[0x20];
6742
6743 u8 reserved_at_320[0x560];
6744
6745 u8 klm_pas_mtt[0][0x20];
6746 };
6747
6748 struct mlx5_ifc_create_flow_table_out_bits {
6749 u8 status[0x8];
6750 u8 reserved_at_8[0x18];
6751
6752 u8 syndrome[0x20];
6753
6754 u8 reserved_at_40[0x8];
6755 u8 table_id[0x18];
6756
6757 u8 reserved_at_60[0x20];
6758 };
6759
6760 struct mlx5_ifc_flow_table_context_bits {
6761 u8 encap_en[0x1];
6762 u8 decap_en[0x1];
6763 u8 reserved_at_2[0x2];
6764 u8 table_miss_action[0x4];
6765 u8 level[0x8];
6766 u8 reserved_at_10[0x8];
6767 u8 log_size[0x8];
6768
6769 u8 reserved_at_20[0x8];
6770 u8 table_miss_id[0x18];
6771
6772 u8 reserved_at_40[0x8];
6773 u8 lag_master_next_table_id[0x18];
6774
6775 u8 reserved_at_60[0xe0];
6776 };
6777
6778 struct mlx5_ifc_create_flow_table_in_bits {
6779 u8 opcode[0x10];
6780 u8 reserved_at_10[0x10];
6781
6782 u8 reserved_at_20[0x10];
6783 u8 op_mod[0x10];
6784
6785 u8 other_vport[0x1];
6786 u8 reserved_at_41[0xf];
6787 u8 vport_number[0x10];
6788
6789 u8 reserved_at_60[0x20];
6790
6791 u8 table_type[0x8];
6792 u8 reserved_at_88[0x18];
6793
6794 u8 reserved_at_a0[0x20];
6795
6796 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6797 };
6798
6799 struct mlx5_ifc_create_flow_group_out_bits {
6800 u8 status[0x8];
6801 u8 reserved_at_8[0x18];
6802
6803 u8 syndrome[0x20];
6804
6805 u8 reserved_at_40[0x8];
6806 u8 group_id[0x18];
6807
6808 u8 reserved_at_60[0x20];
6809 };
6810
6811 enum {
6812 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6813 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6814 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6815 };
6816
6817 struct mlx5_ifc_create_flow_group_in_bits {
6818 u8 opcode[0x10];
6819 u8 reserved_at_10[0x10];
6820
6821 u8 reserved_at_20[0x10];
6822 u8 op_mod[0x10];
6823
6824 u8 other_vport[0x1];
6825 u8 reserved_at_41[0xf];
6826 u8 vport_number[0x10];
6827
6828 u8 reserved_at_60[0x20];
6829
6830 u8 table_type[0x8];
6831 u8 reserved_at_88[0x18];
6832
6833 u8 reserved_at_a0[0x8];
6834 u8 table_id[0x18];
6835
6836 u8 reserved_at_c0[0x20];
6837
6838 u8 start_flow_index[0x20];
6839
6840 u8 reserved_at_100[0x20];
6841
6842 u8 end_flow_index[0x20];
6843
6844 u8 reserved_at_140[0xa0];
6845
6846 u8 reserved_at_1e0[0x18];
6847 u8 match_criteria_enable[0x8];
6848
6849 struct mlx5_ifc_fte_match_param_bits match_criteria;
6850
6851 u8 reserved_at_1200[0xe00];
6852 };
6853
6854 struct mlx5_ifc_create_eq_out_bits {
6855 u8 status[0x8];
6856 u8 reserved_at_8[0x18];
6857
6858 u8 syndrome[0x20];
6859
6860 u8 reserved_at_40[0x18];
6861 u8 eq_number[0x8];
6862
6863 u8 reserved_at_60[0x20];
6864 };
6865
6866 struct mlx5_ifc_create_eq_in_bits {
6867 u8 opcode[0x10];
6868 u8 reserved_at_10[0x10];
6869
6870 u8 reserved_at_20[0x10];
6871 u8 op_mod[0x10];
6872
6873 u8 reserved_at_40[0x40];
6874
6875 struct mlx5_ifc_eqc_bits eq_context_entry;
6876
6877 u8 reserved_at_280[0x40];
6878
6879 u8 event_bitmask[0x40];
6880
6881 u8 reserved_at_300[0x580];
6882
6883 u8 pas[0][0x40];
6884 };
6885
6886 struct mlx5_ifc_create_dct_out_bits {
6887 u8 status[0x8];
6888 u8 reserved_at_8[0x18];
6889
6890 u8 syndrome[0x20];
6891
6892 u8 reserved_at_40[0x8];
6893 u8 dctn[0x18];
6894
6895 u8 reserved_at_60[0x20];
6896 };
6897
6898 struct mlx5_ifc_create_dct_in_bits {
6899 u8 opcode[0x10];
6900 u8 reserved_at_10[0x10];
6901
6902 u8 reserved_at_20[0x10];
6903 u8 op_mod[0x10];
6904
6905 u8 reserved_at_40[0x40];
6906
6907 struct mlx5_ifc_dctc_bits dct_context_entry;
6908
6909 u8 reserved_at_280[0x180];
6910 };
6911
6912 struct mlx5_ifc_create_cq_out_bits {
6913 u8 status[0x8];
6914 u8 reserved_at_8[0x18];
6915
6916 u8 syndrome[0x20];
6917
6918 u8 reserved_at_40[0x8];
6919 u8 cqn[0x18];
6920
6921 u8 reserved_at_60[0x20];
6922 };
6923
6924 struct mlx5_ifc_create_cq_in_bits {
6925 u8 opcode[0x10];
6926 u8 reserved_at_10[0x10];
6927
6928 u8 reserved_at_20[0x10];
6929 u8 op_mod[0x10];
6930
6931 u8 reserved_at_40[0x40];
6932
6933 struct mlx5_ifc_cqc_bits cq_context;
6934
6935 u8 reserved_at_280[0x600];
6936
6937 u8 pas[0][0x40];
6938 };
6939
6940 struct mlx5_ifc_config_int_moderation_out_bits {
6941 u8 status[0x8];
6942 u8 reserved_at_8[0x18];
6943
6944 u8 syndrome[0x20];
6945
6946 u8 reserved_at_40[0x4];
6947 u8 min_delay[0xc];
6948 u8 int_vector[0x10];
6949
6950 u8 reserved_at_60[0x20];
6951 };
6952
6953 enum {
6954 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6955 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6956 };
6957
6958 struct mlx5_ifc_config_int_moderation_in_bits {
6959 u8 opcode[0x10];
6960 u8 reserved_at_10[0x10];
6961
6962 u8 reserved_at_20[0x10];
6963 u8 op_mod[0x10];
6964
6965 u8 reserved_at_40[0x4];
6966 u8 min_delay[0xc];
6967 u8 int_vector[0x10];
6968
6969 u8 reserved_at_60[0x20];
6970 };
6971
6972 struct mlx5_ifc_attach_to_mcg_out_bits {
6973 u8 status[0x8];
6974 u8 reserved_at_8[0x18];
6975
6976 u8 syndrome[0x20];
6977
6978 u8 reserved_at_40[0x40];
6979 };
6980
6981 struct mlx5_ifc_attach_to_mcg_in_bits {
6982 u8 opcode[0x10];
6983 u8 reserved_at_10[0x10];
6984
6985 u8 reserved_at_20[0x10];
6986 u8 op_mod[0x10];
6987
6988 u8 reserved_at_40[0x8];
6989 u8 qpn[0x18];
6990
6991 u8 reserved_at_60[0x20];
6992
6993 u8 multicast_gid[16][0x8];
6994 };
6995
6996 struct mlx5_ifc_arm_xrq_out_bits {
6997 u8 status[0x8];
6998 u8 reserved_at_8[0x18];
6999
7000 u8 syndrome[0x20];
7001
7002 u8 reserved_at_40[0x40];
7003 };
7004
7005 struct mlx5_ifc_arm_xrq_in_bits {
7006 u8 opcode[0x10];
7007 u8 reserved_at_10[0x10];
7008
7009 u8 reserved_at_20[0x10];
7010 u8 op_mod[0x10];
7011
7012 u8 reserved_at_40[0x8];
7013 u8 xrqn[0x18];
7014
7015 u8 reserved_at_60[0x10];
7016 u8 lwm[0x10];
7017 };
7018
7019 struct mlx5_ifc_arm_xrc_srq_out_bits {
7020 u8 status[0x8];
7021 u8 reserved_at_8[0x18];
7022
7023 u8 syndrome[0x20];
7024
7025 u8 reserved_at_40[0x40];
7026 };
7027
7028 enum {
7029 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7030 };
7031
7032 struct mlx5_ifc_arm_xrc_srq_in_bits {
7033 u8 opcode[0x10];
7034 u8 reserved_at_10[0x10];
7035
7036 u8 reserved_at_20[0x10];
7037 u8 op_mod[0x10];
7038
7039 u8 reserved_at_40[0x8];
7040 u8 xrc_srqn[0x18];
7041
7042 u8 reserved_at_60[0x10];
7043 u8 lwm[0x10];
7044 };
7045
7046 struct mlx5_ifc_arm_rq_out_bits {
7047 u8 status[0x8];
7048 u8 reserved_at_8[0x18];
7049
7050 u8 syndrome[0x20];
7051
7052 u8 reserved_at_40[0x40];
7053 };
7054
7055 enum {
7056 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7057 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7058 };
7059
7060 struct mlx5_ifc_arm_rq_in_bits {
7061 u8 opcode[0x10];
7062 u8 reserved_at_10[0x10];
7063
7064 u8 reserved_at_20[0x10];
7065 u8 op_mod[0x10];
7066
7067 u8 reserved_at_40[0x8];
7068 u8 srq_number[0x18];
7069
7070 u8 reserved_at_60[0x10];
7071 u8 lwm[0x10];
7072 };
7073
7074 struct mlx5_ifc_arm_dct_out_bits {
7075 u8 status[0x8];
7076 u8 reserved_at_8[0x18];
7077
7078 u8 syndrome[0x20];
7079
7080 u8 reserved_at_40[0x40];
7081 };
7082
7083 struct mlx5_ifc_arm_dct_in_bits {
7084 u8 opcode[0x10];
7085 u8 reserved_at_10[0x10];
7086
7087 u8 reserved_at_20[0x10];
7088 u8 op_mod[0x10];
7089
7090 u8 reserved_at_40[0x8];
7091 u8 dct_number[0x18];
7092
7093 u8 reserved_at_60[0x20];
7094 };
7095
7096 struct mlx5_ifc_alloc_xrcd_out_bits {
7097 u8 status[0x8];
7098 u8 reserved_at_8[0x18];
7099
7100 u8 syndrome[0x20];
7101
7102 u8 reserved_at_40[0x8];
7103 u8 xrcd[0x18];
7104
7105 u8 reserved_at_60[0x20];
7106 };
7107
7108 struct mlx5_ifc_alloc_xrcd_in_bits {
7109 u8 opcode[0x10];
7110 u8 reserved_at_10[0x10];
7111
7112 u8 reserved_at_20[0x10];
7113 u8 op_mod[0x10];
7114
7115 u8 reserved_at_40[0x40];
7116 };
7117
7118 struct mlx5_ifc_alloc_uar_out_bits {
7119 u8 status[0x8];
7120 u8 reserved_at_8[0x18];
7121
7122 u8 syndrome[0x20];
7123
7124 u8 reserved_at_40[0x8];
7125 u8 uar[0x18];
7126
7127 u8 reserved_at_60[0x20];
7128 };
7129
7130 struct mlx5_ifc_alloc_uar_in_bits {
7131 u8 opcode[0x10];
7132 u8 reserved_at_10[0x10];
7133
7134 u8 reserved_at_20[0x10];
7135 u8 op_mod[0x10];
7136
7137 u8 reserved_at_40[0x40];
7138 };
7139
7140 struct mlx5_ifc_alloc_transport_domain_out_bits {
7141 u8 status[0x8];
7142 u8 reserved_at_8[0x18];
7143
7144 u8 syndrome[0x20];
7145
7146 u8 reserved_at_40[0x8];
7147 u8 transport_domain[0x18];
7148
7149 u8 reserved_at_60[0x20];
7150 };
7151
7152 struct mlx5_ifc_alloc_transport_domain_in_bits {
7153 u8 opcode[0x10];
7154 u8 reserved_at_10[0x10];
7155
7156 u8 reserved_at_20[0x10];
7157 u8 op_mod[0x10];
7158
7159 u8 reserved_at_40[0x40];
7160 };
7161
7162 struct mlx5_ifc_alloc_q_counter_out_bits {
7163 u8 status[0x8];
7164 u8 reserved_at_8[0x18];
7165
7166 u8 syndrome[0x20];
7167
7168 u8 reserved_at_40[0x18];
7169 u8 counter_set_id[0x8];
7170
7171 u8 reserved_at_60[0x20];
7172 };
7173
7174 struct mlx5_ifc_alloc_q_counter_in_bits {
7175 u8 opcode[0x10];
7176 u8 reserved_at_10[0x10];
7177
7178 u8 reserved_at_20[0x10];
7179 u8 op_mod[0x10];
7180
7181 u8 reserved_at_40[0x40];
7182 };
7183
7184 struct mlx5_ifc_alloc_pd_out_bits {
7185 u8 status[0x8];
7186 u8 reserved_at_8[0x18];
7187
7188 u8 syndrome[0x20];
7189
7190 u8 reserved_at_40[0x8];
7191 u8 pd[0x18];
7192
7193 u8 reserved_at_60[0x20];
7194 };
7195
7196 struct mlx5_ifc_alloc_pd_in_bits {
7197 u8 opcode[0x10];
7198 u8 reserved_at_10[0x10];
7199
7200 u8 reserved_at_20[0x10];
7201 u8 op_mod[0x10];
7202
7203 u8 reserved_at_40[0x40];
7204 };
7205
7206 struct mlx5_ifc_alloc_flow_counter_out_bits {
7207 u8 status[0x8];
7208 u8 reserved_at_8[0x18];
7209
7210 u8 syndrome[0x20];
7211
7212 u8 flow_counter_id[0x20];
7213
7214 u8 reserved_at_60[0x20];
7215 };
7216
7217 struct mlx5_ifc_alloc_flow_counter_in_bits {
7218 u8 opcode[0x10];
7219 u8 reserved_at_10[0x10];
7220
7221 u8 reserved_at_20[0x10];
7222 u8 op_mod[0x10];
7223
7224 u8 reserved_at_40[0x40];
7225 };
7226
7227 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7228 u8 status[0x8];
7229 u8 reserved_at_8[0x18];
7230
7231 u8 syndrome[0x20];
7232
7233 u8 reserved_at_40[0x40];
7234 };
7235
7236 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7237 u8 opcode[0x10];
7238 u8 reserved_at_10[0x10];
7239
7240 u8 reserved_at_20[0x10];
7241 u8 op_mod[0x10];
7242
7243 u8 reserved_at_40[0x20];
7244
7245 u8 reserved_at_60[0x10];
7246 u8 vxlan_udp_port[0x10];
7247 };
7248
7249 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7250 u8 status[0x8];
7251 u8 reserved_at_8[0x18];
7252
7253 u8 syndrome[0x20];
7254
7255 u8 reserved_at_40[0x40];
7256 };
7257
7258 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7259 u8 opcode[0x10];
7260 u8 reserved_at_10[0x10];
7261
7262 u8 reserved_at_20[0x10];
7263 u8 op_mod[0x10];
7264
7265 u8 reserved_at_40[0x10];
7266 u8 rate_limit_index[0x10];
7267
7268 u8 reserved_at_60[0x20];
7269
7270 u8 rate_limit[0x20];
7271
7272 u8 reserved_at_a0[0x160];
7273 };
7274
7275 struct mlx5_ifc_access_register_out_bits {
7276 u8 status[0x8];
7277 u8 reserved_at_8[0x18];
7278
7279 u8 syndrome[0x20];
7280
7281 u8 reserved_at_40[0x40];
7282
7283 u8 register_data[0][0x20];
7284 };
7285
7286 enum {
7287 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7288 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7289 };
7290
7291 struct mlx5_ifc_access_register_in_bits {
7292 u8 opcode[0x10];
7293 u8 reserved_at_10[0x10];
7294
7295 u8 reserved_at_20[0x10];
7296 u8 op_mod[0x10];
7297
7298 u8 reserved_at_40[0x10];
7299 u8 register_id[0x10];
7300
7301 u8 argument[0x20];
7302
7303 u8 register_data[0][0x20];
7304 };
7305
7306 struct mlx5_ifc_sltp_reg_bits {
7307 u8 status[0x4];
7308 u8 version[0x4];
7309 u8 local_port[0x8];
7310 u8 pnat[0x2];
7311 u8 reserved_at_12[0x2];
7312 u8 lane[0x4];
7313 u8 reserved_at_18[0x8];
7314
7315 u8 reserved_at_20[0x20];
7316
7317 u8 reserved_at_40[0x7];
7318 u8 polarity[0x1];
7319 u8 ob_tap0[0x8];
7320 u8 ob_tap1[0x8];
7321 u8 ob_tap2[0x8];
7322
7323 u8 reserved_at_60[0xc];
7324 u8 ob_preemp_mode[0x4];
7325 u8 ob_reg[0x8];
7326 u8 ob_bias[0x8];
7327
7328 u8 reserved_at_80[0x20];
7329 };
7330
7331 struct mlx5_ifc_slrg_reg_bits {
7332 u8 status[0x4];
7333 u8 version[0x4];
7334 u8 local_port[0x8];
7335 u8 pnat[0x2];
7336 u8 reserved_at_12[0x2];
7337 u8 lane[0x4];
7338 u8 reserved_at_18[0x8];
7339
7340 u8 time_to_link_up[0x10];
7341 u8 reserved_at_30[0xc];
7342 u8 grade_lane_speed[0x4];
7343
7344 u8 grade_version[0x8];
7345 u8 grade[0x18];
7346
7347 u8 reserved_at_60[0x4];
7348 u8 height_grade_type[0x4];
7349 u8 height_grade[0x18];
7350
7351 u8 height_dz[0x10];
7352 u8 height_dv[0x10];
7353
7354 u8 reserved_at_a0[0x10];
7355 u8 height_sigma[0x10];
7356
7357 u8 reserved_at_c0[0x20];
7358
7359 u8 reserved_at_e0[0x4];
7360 u8 phase_grade_type[0x4];
7361 u8 phase_grade[0x18];
7362
7363 u8 reserved_at_100[0x8];
7364 u8 phase_eo_pos[0x8];
7365 u8 reserved_at_110[0x8];
7366 u8 phase_eo_neg[0x8];
7367
7368 u8 ffe_set_tested[0x10];
7369 u8 test_errors_per_lane[0x10];
7370 };
7371
7372 struct mlx5_ifc_pvlc_reg_bits {
7373 u8 reserved_at_0[0x8];
7374 u8 local_port[0x8];
7375 u8 reserved_at_10[0x10];
7376
7377 u8 reserved_at_20[0x1c];
7378 u8 vl_hw_cap[0x4];
7379
7380 u8 reserved_at_40[0x1c];
7381 u8 vl_admin[0x4];
7382
7383 u8 reserved_at_60[0x1c];
7384 u8 vl_operational[0x4];
7385 };
7386
7387 struct mlx5_ifc_pude_reg_bits {
7388 u8 swid[0x8];
7389 u8 local_port[0x8];
7390 u8 reserved_at_10[0x4];
7391 u8 admin_status[0x4];
7392 u8 reserved_at_18[0x4];
7393 u8 oper_status[0x4];
7394
7395 u8 reserved_at_20[0x60];
7396 };
7397
7398 struct mlx5_ifc_ptys_reg_bits {
7399 u8 reserved_at_0[0x1];
7400 u8 an_disable_admin[0x1];
7401 u8 an_disable_cap[0x1];
7402 u8 reserved_at_3[0x5];
7403 u8 local_port[0x8];
7404 u8 reserved_at_10[0xd];
7405 u8 proto_mask[0x3];
7406
7407 u8 an_status[0x4];
7408 u8 reserved_at_24[0x3c];
7409
7410 u8 eth_proto_capability[0x20];
7411
7412 u8 ib_link_width_capability[0x10];
7413 u8 ib_proto_capability[0x10];
7414
7415 u8 reserved_at_a0[0x20];
7416
7417 u8 eth_proto_admin[0x20];
7418
7419 u8 ib_link_width_admin[0x10];
7420 u8 ib_proto_admin[0x10];
7421
7422 u8 reserved_at_100[0x20];
7423
7424 u8 eth_proto_oper[0x20];
7425
7426 u8 ib_link_width_oper[0x10];
7427 u8 ib_proto_oper[0x10];
7428
7429 u8 reserved_at_160[0x1c];
7430 u8 connector_type[0x4];
7431
7432 u8 eth_proto_lp_advertise[0x20];
7433
7434 u8 reserved_at_1a0[0x60];
7435 };
7436
7437 struct mlx5_ifc_mlcr_reg_bits {
7438 u8 reserved_at_0[0x8];
7439 u8 local_port[0x8];
7440 u8 reserved_at_10[0x20];
7441
7442 u8 beacon_duration[0x10];
7443 u8 reserved_at_40[0x10];
7444
7445 u8 beacon_remain[0x10];
7446 };
7447
7448 struct mlx5_ifc_ptas_reg_bits {
7449 u8 reserved_at_0[0x20];
7450
7451 u8 algorithm_options[0x10];
7452 u8 reserved_at_30[0x4];
7453 u8 repetitions_mode[0x4];
7454 u8 num_of_repetitions[0x8];
7455
7456 u8 grade_version[0x8];
7457 u8 height_grade_type[0x4];
7458 u8 phase_grade_type[0x4];
7459 u8 height_grade_weight[0x8];
7460 u8 phase_grade_weight[0x8];
7461
7462 u8 gisim_measure_bits[0x10];
7463 u8 adaptive_tap_measure_bits[0x10];
7464
7465 u8 ber_bath_high_error_threshold[0x10];
7466 u8 ber_bath_mid_error_threshold[0x10];
7467
7468 u8 ber_bath_low_error_threshold[0x10];
7469 u8 one_ratio_high_threshold[0x10];
7470
7471 u8 one_ratio_high_mid_threshold[0x10];
7472 u8 one_ratio_low_mid_threshold[0x10];
7473
7474 u8 one_ratio_low_threshold[0x10];
7475 u8 ndeo_error_threshold[0x10];
7476
7477 u8 mixer_offset_step_size[0x10];
7478 u8 reserved_at_110[0x8];
7479 u8 mix90_phase_for_voltage_bath[0x8];
7480
7481 u8 mixer_offset_start[0x10];
7482 u8 mixer_offset_end[0x10];
7483
7484 u8 reserved_at_140[0x15];
7485 u8 ber_test_time[0xb];
7486 };
7487
7488 struct mlx5_ifc_pspa_reg_bits {
7489 u8 swid[0x8];
7490 u8 local_port[0x8];
7491 u8 sub_port[0x8];
7492 u8 reserved_at_18[0x8];
7493
7494 u8 reserved_at_20[0x20];
7495 };
7496
7497 struct mlx5_ifc_pqdr_reg_bits {
7498 u8 reserved_at_0[0x8];
7499 u8 local_port[0x8];
7500 u8 reserved_at_10[0x5];
7501 u8 prio[0x3];
7502 u8 reserved_at_18[0x6];
7503 u8 mode[0x2];
7504
7505 u8 reserved_at_20[0x20];
7506
7507 u8 reserved_at_40[0x10];
7508 u8 min_threshold[0x10];
7509
7510 u8 reserved_at_60[0x10];
7511 u8 max_threshold[0x10];
7512
7513 u8 reserved_at_80[0x10];
7514 u8 mark_probability_denominator[0x10];
7515
7516 u8 reserved_at_a0[0x60];
7517 };
7518
7519 struct mlx5_ifc_ppsc_reg_bits {
7520 u8 reserved_at_0[0x8];
7521 u8 local_port[0x8];
7522 u8 reserved_at_10[0x10];
7523
7524 u8 reserved_at_20[0x60];
7525
7526 u8 reserved_at_80[0x1c];
7527 u8 wrps_admin[0x4];
7528
7529 u8 reserved_at_a0[0x1c];
7530 u8 wrps_status[0x4];
7531
7532 u8 reserved_at_c0[0x8];
7533 u8 up_threshold[0x8];
7534 u8 reserved_at_d0[0x8];
7535 u8 down_threshold[0x8];
7536
7537 u8 reserved_at_e0[0x20];
7538
7539 u8 reserved_at_100[0x1c];
7540 u8 srps_admin[0x4];
7541
7542 u8 reserved_at_120[0x1c];
7543 u8 srps_status[0x4];
7544
7545 u8 reserved_at_140[0x40];
7546 };
7547
7548 struct mlx5_ifc_pplr_reg_bits {
7549 u8 reserved_at_0[0x8];
7550 u8 local_port[0x8];
7551 u8 reserved_at_10[0x10];
7552
7553 u8 reserved_at_20[0x8];
7554 u8 lb_cap[0x8];
7555 u8 reserved_at_30[0x8];
7556 u8 lb_en[0x8];
7557 };
7558
7559 struct mlx5_ifc_pplm_reg_bits {
7560 u8 reserved_at_0[0x8];
7561 u8 local_port[0x8];
7562 u8 reserved_at_10[0x10];
7563
7564 u8 reserved_at_20[0x20];
7565
7566 u8 port_profile_mode[0x8];
7567 u8 static_port_profile[0x8];
7568 u8 active_port_profile[0x8];
7569 u8 reserved_at_58[0x8];
7570
7571 u8 retransmission_active[0x8];
7572 u8 fec_mode_active[0x18];
7573
7574 u8 reserved_at_80[0x20];
7575 };
7576
7577 struct mlx5_ifc_ppcnt_reg_bits {
7578 u8 swid[0x8];
7579 u8 local_port[0x8];
7580 u8 pnat[0x2];
7581 u8 reserved_at_12[0x8];
7582 u8 grp[0x6];
7583
7584 u8 clr[0x1];
7585 u8 reserved_at_21[0x1c];
7586 u8 prio_tc[0x3];
7587
7588 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7589 };
7590
7591 struct mlx5_ifc_mpcnt_reg_bits {
7592 u8 reserved_at_0[0x8];
7593 u8 pcie_index[0x8];
7594 u8 reserved_at_10[0xa];
7595 u8 grp[0x6];
7596
7597 u8 clr[0x1];
7598 u8 reserved_at_21[0x1f];
7599
7600 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7601 };
7602
7603 struct mlx5_ifc_ppad_reg_bits {
7604 u8 reserved_at_0[0x3];
7605 u8 single_mac[0x1];
7606 u8 reserved_at_4[0x4];
7607 u8 local_port[0x8];
7608 u8 mac_47_32[0x10];
7609
7610 u8 mac_31_0[0x20];
7611
7612 u8 reserved_at_40[0x40];
7613 };
7614
7615 struct mlx5_ifc_pmtu_reg_bits {
7616 u8 reserved_at_0[0x8];
7617 u8 local_port[0x8];
7618 u8 reserved_at_10[0x10];
7619
7620 u8 max_mtu[0x10];
7621 u8 reserved_at_30[0x10];
7622
7623 u8 admin_mtu[0x10];
7624 u8 reserved_at_50[0x10];
7625
7626 u8 oper_mtu[0x10];
7627 u8 reserved_at_70[0x10];
7628 };
7629
7630 struct mlx5_ifc_pmpr_reg_bits {
7631 u8 reserved_at_0[0x8];
7632 u8 module[0x8];
7633 u8 reserved_at_10[0x10];
7634
7635 u8 reserved_at_20[0x18];
7636 u8 attenuation_5g[0x8];
7637
7638 u8 reserved_at_40[0x18];
7639 u8 attenuation_7g[0x8];
7640
7641 u8 reserved_at_60[0x18];
7642 u8 attenuation_12g[0x8];
7643 };
7644
7645 struct mlx5_ifc_pmpe_reg_bits {
7646 u8 reserved_at_0[0x8];
7647 u8 module[0x8];
7648 u8 reserved_at_10[0xc];
7649 u8 module_status[0x4];
7650
7651 u8 reserved_at_20[0x60];
7652 };
7653
7654 struct mlx5_ifc_pmpc_reg_bits {
7655 u8 module_state_updated[32][0x8];
7656 };
7657
7658 struct mlx5_ifc_pmlpn_reg_bits {
7659 u8 reserved_at_0[0x4];
7660 u8 mlpn_status[0x4];
7661 u8 local_port[0x8];
7662 u8 reserved_at_10[0x10];
7663
7664 u8 e[0x1];
7665 u8 reserved_at_21[0x1f];
7666 };
7667
7668 struct mlx5_ifc_pmlp_reg_bits {
7669 u8 rxtx[0x1];
7670 u8 reserved_at_1[0x7];
7671 u8 local_port[0x8];
7672 u8 reserved_at_10[0x8];
7673 u8 width[0x8];
7674
7675 u8 lane0_module_mapping[0x20];
7676
7677 u8 lane1_module_mapping[0x20];
7678
7679 u8 lane2_module_mapping[0x20];
7680
7681 u8 lane3_module_mapping[0x20];
7682
7683 u8 reserved_at_a0[0x160];
7684 };
7685
7686 struct mlx5_ifc_pmaos_reg_bits {
7687 u8 reserved_at_0[0x8];
7688 u8 module[0x8];
7689 u8 reserved_at_10[0x4];
7690 u8 admin_status[0x4];
7691 u8 reserved_at_18[0x4];
7692 u8 oper_status[0x4];
7693
7694 u8 ase[0x1];
7695 u8 ee[0x1];
7696 u8 reserved_at_22[0x1c];
7697 u8 e[0x2];
7698
7699 u8 reserved_at_40[0x40];
7700 };
7701
7702 struct mlx5_ifc_plpc_reg_bits {
7703 u8 reserved_at_0[0x4];
7704 u8 profile_id[0xc];
7705 u8 reserved_at_10[0x4];
7706 u8 proto_mask[0x4];
7707 u8 reserved_at_18[0x8];
7708
7709 u8 reserved_at_20[0x10];
7710 u8 lane_speed[0x10];
7711
7712 u8 reserved_at_40[0x17];
7713 u8 lpbf[0x1];
7714 u8 fec_mode_policy[0x8];
7715
7716 u8 retransmission_capability[0x8];
7717 u8 fec_mode_capability[0x18];
7718
7719 u8 retransmission_support_admin[0x8];
7720 u8 fec_mode_support_admin[0x18];
7721
7722 u8 retransmission_request_admin[0x8];
7723 u8 fec_mode_request_admin[0x18];
7724
7725 u8 reserved_at_c0[0x80];
7726 };
7727
7728 struct mlx5_ifc_plib_reg_bits {
7729 u8 reserved_at_0[0x8];
7730 u8 local_port[0x8];
7731 u8 reserved_at_10[0x8];
7732 u8 ib_port[0x8];
7733
7734 u8 reserved_at_20[0x60];
7735 };
7736
7737 struct mlx5_ifc_plbf_reg_bits {
7738 u8 reserved_at_0[0x8];
7739 u8 local_port[0x8];
7740 u8 reserved_at_10[0xd];
7741 u8 lbf_mode[0x3];
7742
7743 u8 reserved_at_20[0x20];
7744 };
7745
7746 struct mlx5_ifc_pipg_reg_bits {
7747 u8 reserved_at_0[0x8];
7748 u8 local_port[0x8];
7749 u8 reserved_at_10[0x10];
7750
7751 u8 dic[0x1];
7752 u8 reserved_at_21[0x19];
7753 u8 ipg[0x4];
7754 u8 reserved_at_3e[0x2];
7755 };
7756
7757 struct mlx5_ifc_pifr_reg_bits {
7758 u8 reserved_at_0[0x8];
7759 u8 local_port[0x8];
7760 u8 reserved_at_10[0x10];
7761
7762 u8 reserved_at_20[0xe0];
7763
7764 u8 port_filter[8][0x20];
7765
7766 u8 port_filter_update_en[8][0x20];
7767 };
7768
7769 struct mlx5_ifc_pfcc_reg_bits {
7770 u8 reserved_at_0[0x8];
7771 u8 local_port[0x8];
7772 u8 reserved_at_10[0x10];
7773
7774 u8 ppan[0x4];
7775 u8 reserved_at_24[0x4];
7776 u8 prio_mask_tx[0x8];
7777 u8 reserved_at_30[0x8];
7778 u8 prio_mask_rx[0x8];
7779
7780 u8 pptx[0x1];
7781 u8 aptx[0x1];
7782 u8 reserved_at_42[0x6];
7783 u8 pfctx[0x8];
7784 u8 reserved_at_50[0x10];
7785
7786 u8 pprx[0x1];
7787 u8 aprx[0x1];
7788 u8 reserved_at_62[0x6];
7789 u8 pfcrx[0x8];
7790 u8 reserved_at_70[0x10];
7791
7792 u8 reserved_at_80[0x80];
7793 };
7794
7795 struct mlx5_ifc_pelc_reg_bits {
7796 u8 op[0x4];
7797 u8 reserved_at_4[0x4];
7798 u8 local_port[0x8];
7799 u8 reserved_at_10[0x10];
7800
7801 u8 op_admin[0x8];
7802 u8 op_capability[0x8];
7803 u8 op_request[0x8];
7804 u8 op_active[0x8];
7805
7806 u8 admin[0x40];
7807
7808 u8 capability[0x40];
7809
7810 u8 request[0x40];
7811
7812 u8 active[0x40];
7813
7814 u8 reserved_at_140[0x80];
7815 };
7816
7817 struct mlx5_ifc_peir_reg_bits {
7818 u8 reserved_at_0[0x8];
7819 u8 local_port[0x8];
7820 u8 reserved_at_10[0x10];
7821
7822 u8 reserved_at_20[0xc];
7823 u8 error_count[0x4];
7824 u8 reserved_at_30[0x10];
7825
7826 u8 reserved_at_40[0xc];
7827 u8 lane[0x4];
7828 u8 reserved_at_50[0x8];
7829 u8 error_type[0x8];
7830 };
7831
7832 struct mlx5_ifc_pcam_enhanced_features_bits {
7833 u8 reserved_at_0[0x7b];
7834
7835 u8 rx_buffer_fullness_counters[0x1];
7836 u8 ptys_connector_type[0x1];
7837 u8 reserved_at_7d[0x1];
7838 u8 ppcnt_discard_group[0x1];
7839 u8 ppcnt_statistical_group[0x1];
7840 };
7841
7842 struct mlx5_ifc_pcam_reg_bits {
7843 u8 reserved_at_0[0x8];
7844 u8 feature_group[0x8];
7845 u8 reserved_at_10[0x8];
7846 u8 access_reg_group[0x8];
7847
7848 u8 reserved_at_20[0x20];
7849
7850 union {
7851 u8 reserved_at_0[0x80];
7852 } port_access_reg_cap_mask;
7853
7854 u8 reserved_at_c0[0x80];
7855
7856 union {
7857 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7858 u8 reserved_at_0[0x80];
7859 } feature_cap_mask;
7860
7861 u8 reserved_at_1c0[0xc0];
7862 };
7863
7864 struct mlx5_ifc_mcam_enhanced_features_bits {
7865 u8 reserved_at_0[0x7b];
7866 u8 pcie_outbound_stalled[0x1];
7867 u8 tx_overflow_buffer_pkt[0x1];
7868 u8 mtpps_enh_out_per_adj[0x1];
7869 u8 mtpps_fs[0x1];
7870 u8 pcie_performance_group[0x1];
7871 };
7872
7873 struct mlx5_ifc_mcam_access_reg_bits {
7874 u8 reserved_at_0[0x1c];
7875 u8 mcda[0x1];
7876 u8 mcc[0x1];
7877 u8 mcqi[0x1];
7878 u8 reserved_at_1f[0x1];
7879
7880 u8 regs_95_to_64[0x20];
7881 u8 regs_63_to_32[0x20];
7882 u8 regs_31_to_0[0x20];
7883 };
7884
7885 struct mlx5_ifc_mcam_reg_bits {
7886 u8 reserved_at_0[0x8];
7887 u8 feature_group[0x8];
7888 u8 reserved_at_10[0x8];
7889 u8 access_reg_group[0x8];
7890
7891 u8 reserved_at_20[0x20];
7892
7893 union {
7894 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7895 u8 reserved_at_0[0x80];
7896 } mng_access_reg_cap_mask;
7897
7898 u8 reserved_at_c0[0x80];
7899
7900 union {
7901 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7902 u8 reserved_at_0[0x80];
7903 } mng_feature_cap_mask;
7904
7905 u8 reserved_at_1c0[0x80];
7906 };
7907
7908 struct mlx5_ifc_qcam_access_reg_cap_mask {
7909 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7910 u8 qpdpm[0x1];
7911 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7912 u8 qdpm[0x1];
7913 u8 qpts[0x1];
7914 u8 qcap[0x1];
7915 u8 qcam_access_reg_cap_mask_0[0x1];
7916 };
7917
7918 struct mlx5_ifc_qcam_qos_feature_cap_mask {
7919 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
7920 u8 qpts_trust_both[0x1];
7921 };
7922
7923 struct mlx5_ifc_qcam_reg_bits {
7924 u8 reserved_at_0[0x8];
7925 u8 feature_group[0x8];
7926 u8 reserved_at_10[0x8];
7927 u8 access_reg_group[0x8];
7928 u8 reserved_at_20[0x20];
7929
7930 union {
7931 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7932 u8 reserved_at_0[0x80];
7933 } qos_access_reg_cap_mask;
7934
7935 u8 reserved_at_c0[0x80];
7936
7937 union {
7938 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7939 u8 reserved_at_0[0x80];
7940 } qos_feature_cap_mask;
7941
7942 u8 reserved_at_1c0[0x80];
7943 };
7944
7945 struct mlx5_ifc_pcap_reg_bits {
7946 u8 reserved_at_0[0x8];
7947 u8 local_port[0x8];
7948 u8 reserved_at_10[0x10];
7949
7950 u8 port_capability_mask[4][0x20];
7951 };
7952
7953 struct mlx5_ifc_paos_reg_bits {
7954 u8 swid[0x8];
7955 u8 local_port[0x8];
7956 u8 reserved_at_10[0x4];
7957 u8 admin_status[0x4];
7958 u8 reserved_at_18[0x4];
7959 u8 oper_status[0x4];
7960
7961 u8 ase[0x1];
7962 u8 ee[0x1];
7963 u8 reserved_at_22[0x1c];
7964 u8 e[0x2];
7965
7966 u8 reserved_at_40[0x40];
7967 };
7968
7969 struct mlx5_ifc_pamp_reg_bits {
7970 u8 reserved_at_0[0x8];
7971 u8 opamp_group[0x8];
7972 u8 reserved_at_10[0xc];
7973 u8 opamp_group_type[0x4];
7974
7975 u8 start_index[0x10];
7976 u8 reserved_at_30[0x4];
7977 u8 num_of_indices[0xc];
7978
7979 u8 index_data[18][0x10];
7980 };
7981
7982 struct mlx5_ifc_pcmr_reg_bits {
7983 u8 reserved_at_0[0x8];
7984 u8 local_port[0x8];
7985 u8 reserved_at_10[0x2e];
7986 u8 fcs_cap[0x1];
7987 u8 reserved_at_3f[0x1f];
7988 u8 fcs_chk[0x1];
7989 u8 reserved_at_5f[0x1];
7990 };
7991
7992 struct mlx5_ifc_lane_2_module_mapping_bits {
7993 u8 reserved_at_0[0x6];
7994 u8 rx_lane[0x2];
7995 u8 reserved_at_8[0x6];
7996 u8 tx_lane[0x2];
7997 u8 reserved_at_10[0x8];
7998 u8 module[0x8];
7999 };
8000
8001 struct mlx5_ifc_bufferx_reg_bits {
8002 u8 reserved_at_0[0x6];
8003 u8 lossy[0x1];
8004 u8 epsb[0x1];
8005 u8 reserved_at_8[0xc];
8006 u8 size[0xc];
8007
8008 u8 xoff_threshold[0x10];
8009 u8 xon_threshold[0x10];
8010 };
8011
8012 struct mlx5_ifc_set_node_in_bits {
8013 u8 node_description[64][0x8];
8014 };
8015
8016 struct mlx5_ifc_register_power_settings_bits {
8017 u8 reserved_at_0[0x18];
8018 u8 power_settings_level[0x8];
8019
8020 u8 reserved_at_20[0x60];
8021 };
8022
8023 struct mlx5_ifc_register_host_endianness_bits {
8024 u8 he[0x1];
8025 u8 reserved_at_1[0x1f];
8026
8027 u8 reserved_at_20[0x60];
8028 };
8029
8030 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8031 u8 reserved_at_0[0x20];
8032
8033 u8 mkey[0x20];
8034
8035 u8 addressh_63_32[0x20];
8036
8037 u8 addressl_31_0[0x20];
8038 };
8039
8040 struct mlx5_ifc_ud_adrs_vector_bits {
8041 u8 dc_key[0x40];
8042
8043 u8 ext[0x1];
8044 u8 reserved_at_41[0x7];
8045 u8 destination_qp_dct[0x18];
8046
8047 u8 static_rate[0x4];
8048 u8 sl_eth_prio[0x4];
8049 u8 fl[0x1];
8050 u8 mlid[0x7];
8051 u8 rlid_udp_sport[0x10];
8052
8053 u8 reserved_at_80[0x20];
8054
8055 u8 rmac_47_16[0x20];
8056
8057 u8 rmac_15_0[0x10];
8058 u8 tclass[0x8];
8059 u8 hop_limit[0x8];
8060
8061 u8 reserved_at_e0[0x1];
8062 u8 grh[0x1];
8063 u8 reserved_at_e2[0x2];
8064 u8 src_addr_index[0x8];
8065 u8 flow_label[0x14];
8066
8067 u8 rgid_rip[16][0x8];
8068 };
8069
8070 struct mlx5_ifc_pages_req_event_bits {
8071 u8 reserved_at_0[0x10];
8072 u8 function_id[0x10];
8073
8074 u8 num_pages[0x20];
8075
8076 u8 reserved_at_40[0xa0];
8077 };
8078
8079 struct mlx5_ifc_eqe_bits {
8080 u8 reserved_at_0[0x8];
8081 u8 event_type[0x8];
8082 u8 reserved_at_10[0x8];
8083 u8 event_sub_type[0x8];
8084
8085 u8 reserved_at_20[0xe0];
8086
8087 union mlx5_ifc_event_auto_bits event_data;
8088
8089 u8 reserved_at_1e0[0x10];
8090 u8 signature[0x8];
8091 u8 reserved_at_1f8[0x7];
8092 u8 owner[0x1];
8093 };
8094
8095 enum {
8096 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8097 };
8098
8099 struct mlx5_ifc_cmd_queue_entry_bits {
8100 u8 type[0x8];
8101 u8 reserved_at_8[0x18];
8102
8103 u8 input_length[0x20];
8104
8105 u8 input_mailbox_pointer_63_32[0x20];
8106
8107 u8 input_mailbox_pointer_31_9[0x17];
8108 u8 reserved_at_77[0x9];
8109
8110 u8 command_input_inline_data[16][0x8];
8111
8112 u8 command_output_inline_data[16][0x8];
8113
8114 u8 output_mailbox_pointer_63_32[0x20];
8115
8116 u8 output_mailbox_pointer_31_9[0x17];
8117 u8 reserved_at_1b7[0x9];
8118
8119 u8 output_length[0x20];
8120
8121 u8 token[0x8];
8122 u8 signature[0x8];
8123 u8 reserved_at_1f0[0x8];
8124 u8 status[0x7];
8125 u8 ownership[0x1];
8126 };
8127
8128 struct mlx5_ifc_cmd_out_bits {
8129 u8 status[0x8];
8130 u8 reserved_at_8[0x18];
8131
8132 u8 syndrome[0x20];
8133
8134 u8 command_output[0x20];
8135 };
8136
8137 struct mlx5_ifc_cmd_in_bits {
8138 u8 opcode[0x10];
8139 u8 reserved_at_10[0x10];
8140
8141 u8 reserved_at_20[0x10];
8142 u8 op_mod[0x10];
8143
8144 u8 command[0][0x20];
8145 };
8146
8147 struct mlx5_ifc_cmd_if_box_bits {
8148 u8 mailbox_data[512][0x8];
8149
8150 u8 reserved_at_1000[0x180];
8151
8152 u8 next_pointer_63_32[0x20];
8153
8154 u8 next_pointer_31_10[0x16];
8155 u8 reserved_at_11b6[0xa];
8156
8157 u8 block_number[0x20];
8158
8159 u8 reserved_at_11e0[0x8];
8160 u8 token[0x8];
8161 u8 ctrl_signature[0x8];
8162 u8 signature[0x8];
8163 };
8164
8165 struct mlx5_ifc_mtt_bits {
8166 u8 ptag_63_32[0x20];
8167
8168 u8 ptag_31_8[0x18];
8169 u8 reserved_at_38[0x6];
8170 u8 wr_en[0x1];
8171 u8 rd_en[0x1];
8172 };
8173
8174 struct mlx5_ifc_query_wol_rol_out_bits {
8175 u8 status[0x8];
8176 u8 reserved_at_8[0x18];
8177
8178 u8 syndrome[0x20];
8179
8180 u8 reserved_at_40[0x10];
8181 u8 rol_mode[0x8];
8182 u8 wol_mode[0x8];
8183
8184 u8 reserved_at_60[0x20];
8185 };
8186
8187 struct mlx5_ifc_query_wol_rol_in_bits {
8188 u8 opcode[0x10];
8189 u8 reserved_at_10[0x10];
8190
8191 u8 reserved_at_20[0x10];
8192 u8 op_mod[0x10];
8193
8194 u8 reserved_at_40[0x40];
8195 };
8196
8197 struct mlx5_ifc_set_wol_rol_out_bits {
8198 u8 status[0x8];
8199 u8 reserved_at_8[0x18];
8200
8201 u8 syndrome[0x20];
8202
8203 u8 reserved_at_40[0x40];
8204 };
8205
8206 struct mlx5_ifc_set_wol_rol_in_bits {
8207 u8 opcode[0x10];
8208 u8 reserved_at_10[0x10];
8209
8210 u8 reserved_at_20[0x10];
8211 u8 op_mod[0x10];
8212
8213 u8 rol_mode_valid[0x1];
8214 u8 wol_mode_valid[0x1];
8215 u8 reserved_at_42[0xe];
8216 u8 rol_mode[0x8];
8217 u8 wol_mode[0x8];
8218
8219 u8 reserved_at_60[0x20];
8220 };
8221
8222 enum {
8223 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8224 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8225 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8226 };
8227
8228 enum {
8229 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8230 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8231 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8232 };
8233
8234 enum {
8235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8238 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8239 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8240 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8241 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8242 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8243 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8244 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8245 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8246 };
8247
8248 struct mlx5_ifc_initial_seg_bits {
8249 u8 fw_rev_minor[0x10];
8250 u8 fw_rev_major[0x10];
8251
8252 u8 cmd_interface_rev[0x10];
8253 u8 fw_rev_subminor[0x10];
8254
8255 u8 reserved_at_40[0x40];
8256
8257 u8 cmdq_phy_addr_63_32[0x20];
8258
8259 u8 cmdq_phy_addr_31_12[0x14];
8260 u8 reserved_at_b4[0x2];
8261 u8 nic_interface[0x2];
8262 u8 log_cmdq_size[0x4];
8263 u8 log_cmdq_stride[0x4];
8264
8265 u8 command_doorbell_vector[0x20];
8266
8267 u8 reserved_at_e0[0xf00];
8268
8269 u8 initializing[0x1];
8270 u8 reserved_at_fe1[0x4];
8271 u8 nic_interface_supported[0x3];
8272 u8 reserved_at_fe8[0x18];
8273
8274 struct mlx5_ifc_health_buffer_bits health_buffer;
8275
8276 u8 no_dram_nic_offset[0x20];
8277
8278 u8 reserved_at_1220[0x6e40];
8279
8280 u8 reserved_at_8060[0x1f];
8281 u8 clear_int[0x1];
8282
8283 u8 health_syndrome[0x8];
8284 u8 health_counter[0x18];
8285
8286 u8 reserved_at_80a0[0x17fc0];
8287 };
8288
8289 struct mlx5_ifc_mtpps_reg_bits {
8290 u8 reserved_at_0[0xc];
8291 u8 cap_number_of_pps_pins[0x4];
8292 u8 reserved_at_10[0x4];
8293 u8 cap_max_num_of_pps_in_pins[0x4];
8294 u8 reserved_at_18[0x4];
8295 u8 cap_max_num_of_pps_out_pins[0x4];
8296
8297 u8 reserved_at_20[0x24];
8298 u8 cap_pin_3_mode[0x4];
8299 u8 reserved_at_48[0x4];
8300 u8 cap_pin_2_mode[0x4];
8301 u8 reserved_at_50[0x4];
8302 u8 cap_pin_1_mode[0x4];
8303 u8 reserved_at_58[0x4];
8304 u8 cap_pin_0_mode[0x4];
8305
8306 u8 reserved_at_60[0x4];
8307 u8 cap_pin_7_mode[0x4];
8308 u8 reserved_at_68[0x4];
8309 u8 cap_pin_6_mode[0x4];
8310 u8 reserved_at_70[0x4];
8311 u8 cap_pin_5_mode[0x4];
8312 u8 reserved_at_78[0x4];
8313 u8 cap_pin_4_mode[0x4];
8314
8315 u8 field_select[0x20];
8316 u8 reserved_at_a0[0x60];
8317
8318 u8 enable[0x1];
8319 u8 reserved_at_101[0xb];
8320 u8 pattern[0x4];
8321 u8 reserved_at_110[0x4];
8322 u8 pin_mode[0x4];
8323 u8 pin[0x8];
8324
8325 u8 reserved_at_120[0x20];
8326
8327 u8 time_stamp[0x40];
8328
8329 u8 out_pulse_duration[0x10];
8330 u8 out_periodic_adjustment[0x10];
8331 u8 enhanced_out_periodic_adjustment[0x20];
8332
8333 u8 reserved_at_1c0[0x20];
8334 };
8335
8336 struct mlx5_ifc_mtppse_reg_bits {
8337 u8 reserved_at_0[0x18];
8338 u8 pin[0x8];
8339 u8 event_arm[0x1];
8340 u8 reserved_at_21[0x1b];
8341 u8 event_generation_mode[0x4];
8342 u8 reserved_at_40[0x40];
8343 };
8344
8345 struct mlx5_ifc_mcqi_cap_bits {
8346 u8 supported_info_bitmask[0x20];
8347
8348 u8 component_size[0x20];
8349
8350 u8 max_component_size[0x20];
8351
8352 u8 log_mcda_word_size[0x4];
8353 u8 reserved_at_64[0xc];
8354 u8 mcda_max_write_size[0x10];
8355
8356 u8 rd_en[0x1];
8357 u8 reserved_at_81[0x1];
8358 u8 match_chip_id[0x1];
8359 u8 match_psid[0x1];
8360 u8 check_user_timestamp[0x1];
8361 u8 match_base_guid_mac[0x1];
8362 u8 reserved_at_86[0x1a];
8363 };
8364
8365 struct mlx5_ifc_mcqi_reg_bits {
8366 u8 read_pending_component[0x1];
8367 u8 reserved_at_1[0xf];
8368 u8 component_index[0x10];
8369
8370 u8 reserved_at_20[0x20];
8371
8372 u8 reserved_at_40[0x1b];
8373 u8 info_type[0x5];
8374
8375 u8 info_size[0x20];
8376
8377 u8 offset[0x20];
8378
8379 u8 reserved_at_a0[0x10];
8380 u8 data_size[0x10];
8381
8382 u8 data[0][0x20];
8383 };
8384
8385 struct mlx5_ifc_mcc_reg_bits {
8386 u8 reserved_at_0[0x4];
8387 u8 time_elapsed_since_last_cmd[0xc];
8388 u8 reserved_at_10[0x8];
8389 u8 instruction[0x8];
8390
8391 u8 reserved_at_20[0x10];
8392 u8 component_index[0x10];
8393
8394 u8 reserved_at_40[0x8];
8395 u8 update_handle[0x18];
8396
8397 u8 handle_owner_type[0x4];
8398 u8 handle_owner_host_id[0x4];
8399 u8 reserved_at_68[0x1];
8400 u8 control_progress[0x7];
8401 u8 error_code[0x8];
8402 u8 reserved_at_78[0x4];
8403 u8 control_state[0x4];
8404
8405 u8 component_size[0x20];
8406
8407 u8 reserved_at_a0[0x60];
8408 };
8409
8410 struct mlx5_ifc_mcda_reg_bits {
8411 u8 reserved_at_0[0x8];
8412 u8 update_handle[0x18];
8413
8414 u8 offset[0x20];
8415
8416 u8 reserved_at_40[0x10];
8417 u8 size[0x10];
8418
8419 u8 reserved_at_60[0x20];
8420
8421 u8 data[0][0x20];
8422 };
8423
8424 union mlx5_ifc_ports_control_registers_document_bits {
8425 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8426 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8427 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8428 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8429 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8430 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8431 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8432 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8433 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8434 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8435 struct mlx5_ifc_paos_reg_bits paos_reg;
8436 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8437 struct mlx5_ifc_peir_reg_bits peir_reg;
8438 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8439 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8440 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8441 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8442 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8443 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8444 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8445 struct mlx5_ifc_plib_reg_bits plib_reg;
8446 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8447 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8448 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8449 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8450 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8451 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8452 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8453 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8454 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8455 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8456 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8457 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8458 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8459 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8460 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8461 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8462 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8463 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8464 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8465 struct mlx5_ifc_pude_reg_bits pude_reg;
8466 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8467 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8468 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8469 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8470 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8471 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8472 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8473 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8474 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8475 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8476 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8477 u8 reserved_at_0[0x60e0];
8478 };
8479
8480 union mlx5_ifc_debug_enhancements_document_bits {
8481 struct mlx5_ifc_health_buffer_bits health_buffer;
8482 u8 reserved_at_0[0x200];
8483 };
8484
8485 union mlx5_ifc_uplink_pci_interface_document_bits {
8486 struct mlx5_ifc_initial_seg_bits initial_seg;
8487 u8 reserved_at_0[0x20060];
8488 };
8489
8490 struct mlx5_ifc_set_flow_table_root_out_bits {
8491 u8 status[0x8];
8492 u8 reserved_at_8[0x18];
8493
8494 u8 syndrome[0x20];
8495
8496 u8 reserved_at_40[0x40];
8497 };
8498
8499 struct mlx5_ifc_set_flow_table_root_in_bits {
8500 u8 opcode[0x10];
8501 u8 reserved_at_10[0x10];
8502
8503 u8 reserved_at_20[0x10];
8504 u8 op_mod[0x10];
8505
8506 u8 other_vport[0x1];
8507 u8 reserved_at_41[0xf];
8508 u8 vport_number[0x10];
8509
8510 u8 reserved_at_60[0x20];
8511
8512 u8 table_type[0x8];
8513 u8 reserved_at_88[0x18];
8514
8515 u8 reserved_at_a0[0x8];
8516 u8 table_id[0x18];
8517
8518 u8 reserved_at_c0[0x8];
8519 u8 underlay_qpn[0x18];
8520 u8 reserved_at_e0[0x120];
8521 };
8522
8523 enum {
8524 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8525 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8526 };
8527
8528 struct mlx5_ifc_modify_flow_table_out_bits {
8529 u8 status[0x8];
8530 u8 reserved_at_8[0x18];
8531
8532 u8 syndrome[0x20];
8533
8534 u8 reserved_at_40[0x40];
8535 };
8536
8537 struct mlx5_ifc_modify_flow_table_in_bits {
8538 u8 opcode[0x10];
8539 u8 reserved_at_10[0x10];
8540
8541 u8 reserved_at_20[0x10];
8542 u8 op_mod[0x10];
8543
8544 u8 other_vport[0x1];
8545 u8 reserved_at_41[0xf];
8546 u8 vport_number[0x10];
8547
8548 u8 reserved_at_60[0x10];
8549 u8 modify_field_select[0x10];
8550
8551 u8 table_type[0x8];
8552 u8 reserved_at_88[0x18];
8553
8554 u8 reserved_at_a0[0x8];
8555 u8 table_id[0x18];
8556
8557 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8558 };
8559
8560 struct mlx5_ifc_ets_tcn_config_reg_bits {
8561 u8 g[0x1];
8562 u8 b[0x1];
8563 u8 r[0x1];
8564 u8 reserved_at_3[0x9];
8565 u8 group[0x4];
8566 u8 reserved_at_10[0x9];
8567 u8 bw_allocation[0x7];
8568
8569 u8 reserved_at_20[0xc];
8570 u8 max_bw_units[0x4];
8571 u8 reserved_at_30[0x8];
8572 u8 max_bw_value[0x8];
8573 };
8574
8575 struct mlx5_ifc_ets_global_config_reg_bits {
8576 u8 reserved_at_0[0x2];
8577 u8 r[0x1];
8578 u8 reserved_at_3[0x1d];
8579
8580 u8 reserved_at_20[0xc];
8581 u8 max_bw_units[0x4];
8582 u8 reserved_at_30[0x8];
8583 u8 max_bw_value[0x8];
8584 };
8585
8586 struct mlx5_ifc_qetc_reg_bits {
8587 u8 reserved_at_0[0x8];
8588 u8 port_number[0x8];
8589 u8 reserved_at_10[0x30];
8590
8591 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8592 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8593 };
8594
8595 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8596 u8 e[0x1];
8597 u8 reserved_at_01[0x0b];
8598 u8 prio[0x04];
8599 };
8600
8601 struct mlx5_ifc_qpdpm_reg_bits {
8602 u8 reserved_at_0[0x8];
8603 u8 local_port[0x8];
8604 u8 reserved_at_10[0x10];
8605 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8606 };
8607
8608 struct mlx5_ifc_qpts_reg_bits {
8609 u8 reserved_at_0[0x8];
8610 u8 local_port[0x8];
8611 u8 reserved_at_10[0x2d];
8612 u8 trust_state[0x3];
8613 };
8614
8615 struct mlx5_ifc_qtct_reg_bits {
8616 u8 reserved_at_0[0x8];
8617 u8 port_number[0x8];
8618 u8 reserved_at_10[0xd];
8619 u8 prio[0x3];
8620
8621 u8 reserved_at_20[0x1d];
8622 u8 tclass[0x3];
8623 };
8624
8625 struct mlx5_ifc_mcia_reg_bits {
8626 u8 l[0x1];
8627 u8 reserved_at_1[0x7];
8628 u8 module[0x8];
8629 u8 reserved_at_10[0x8];
8630 u8 status[0x8];
8631
8632 u8 i2c_device_address[0x8];
8633 u8 page_number[0x8];
8634 u8 device_address[0x10];
8635
8636 u8 reserved_at_40[0x10];
8637 u8 size[0x10];
8638
8639 u8 reserved_at_60[0x20];
8640
8641 u8 dword_0[0x20];
8642 u8 dword_1[0x20];
8643 u8 dword_2[0x20];
8644 u8 dword_3[0x20];
8645 u8 dword_4[0x20];
8646 u8 dword_5[0x20];
8647 u8 dword_6[0x20];
8648 u8 dword_7[0x20];
8649 u8 dword_8[0x20];
8650 u8 dword_9[0x20];
8651 u8 dword_10[0x20];
8652 u8 dword_11[0x20];
8653 };
8654
8655 struct mlx5_ifc_dcbx_param_bits {
8656 u8 dcbx_cee_cap[0x1];
8657 u8 dcbx_ieee_cap[0x1];
8658 u8 dcbx_standby_cap[0x1];
8659 u8 reserved_at_0[0x5];
8660 u8 port_number[0x8];
8661 u8 reserved_at_10[0xa];
8662 u8 max_application_table_size[6];
8663 u8 reserved_at_20[0x15];
8664 u8 version_oper[0x3];
8665 u8 reserved_at_38[5];
8666 u8 version_admin[0x3];
8667 u8 willing_admin[0x1];
8668 u8 reserved_at_41[0x3];
8669 u8 pfc_cap_oper[0x4];
8670 u8 reserved_at_48[0x4];
8671 u8 pfc_cap_admin[0x4];
8672 u8 reserved_at_50[0x4];
8673 u8 num_of_tc_oper[0x4];
8674 u8 reserved_at_58[0x4];
8675 u8 num_of_tc_admin[0x4];
8676 u8 remote_willing[0x1];
8677 u8 reserved_at_61[3];
8678 u8 remote_pfc_cap[4];
8679 u8 reserved_at_68[0x14];
8680 u8 remote_num_of_tc[0x4];
8681 u8 reserved_at_80[0x18];
8682 u8 error[0x8];
8683 u8 reserved_at_a0[0x160];
8684 };
8685
8686 struct mlx5_ifc_lagc_bits {
8687 u8 reserved_at_0[0x1d];
8688 u8 lag_state[0x3];
8689
8690 u8 reserved_at_20[0x14];
8691 u8 tx_remap_affinity_2[0x4];
8692 u8 reserved_at_38[0x4];
8693 u8 tx_remap_affinity_1[0x4];
8694 };
8695
8696 struct mlx5_ifc_create_lag_out_bits {
8697 u8 status[0x8];
8698 u8 reserved_at_8[0x18];
8699
8700 u8 syndrome[0x20];
8701
8702 u8 reserved_at_40[0x40];
8703 };
8704
8705 struct mlx5_ifc_create_lag_in_bits {
8706 u8 opcode[0x10];
8707 u8 reserved_at_10[0x10];
8708
8709 u8 reserved_at_20[0x10];
8710 u8 op_mod[0x10];
8711
8712 struct mlx5_ifc_lagc_bits ctx;
8713 };
8714
8715 struct mlx5_ifc_modify_lag_out_bits {
8716 u8 status[0x8];
8717 u8 reserved_at_8[0x18];
8718
8719 u8 syndrome[0x20];
8720
8721 u8 reserved_at_40[0x40];
8722 };
8723
8724 struct mlx5_ifc_modify_lag_in_bits {
8725 u8 opcode[0x10];
8726 u8 reserved_at_10[0x10];
8727
8728 u8 reserved_at_20[0x10];
8729 u8 op_mod[0x10];
8730
8731 u8 reserved_at_40[0x20];
8732 u8 field_select[0x20];
8733
8734 struct mlx5_ifc_lagc_bits ctx;
8735 };
8736
8737 struct mlx5_ifc_query_lag_out_bits {
8738 u8 status[0x8];
8739 u8 reserved_at_8[0x18];
8740
8741 u8 syndrome[0x20];
8742
8743 struct mlx5_ifc_lagc_bits ctx;
8744 };
8745
8746 struct mlx5_ifc_query_lag_in_bits {
8747 u8 opcode[0x10];
8748 u8 reserved_at_10[0x10];
8749
8750 u8 reserved_at_20[0x10];
8751 u8 op_mod[0x10];
8752
8753 u8 reserved_at_40[0x40];
8754 };
8755
8756 struct mlx5_ifc_destroy_lag_out_bits {
8757 u8 status[0x8];
8758 u8 reserved_at_8[0x18];
8759
8760 u8 syndrome[0x20];
8761
8762 u8 reserved_at_40[0x40];
8763 };
8764
8765 struct mlx5_ifc_destroy_lag_in_bits {
8766 u8 opcode[0x10];
8767 u8 reserved_at_10[0x10];
8768
8769 u8 reserved_at_20[0x10];
8770 u8 op_mod[0x10];
8771
8772 u8 reserved_at_40[0x40];
8773 };
8774
8775 struct mlx5_ifc_create_vport_lag_out_bits {
8776 u8 status[0x8];
8777 u8 reserved_at_8[0x18];
8778
8779 u8 syndrome[0x20];
8780
8781 u8 reserved_at_40[0x40];
8782 };
8783
8784 struct mlx5_ifc_create_vport_lag_in_bits {
8785 u8 opcode[0x10];
8786 u8 reserved_at_10[0x10];
8787
8788 u8 reserved_at_20[0x10];
8789 u8 op_mod[0x10];
8790
8791 u8 reserved_at_40[0x40];
8792 };
8793
8794 struct mlx5_ifc_destroy_vport_lag_out_bits {
8795 u8 status[0x8];
8796 u8 reserved_at_8[0x18];
8797
8798 u8 syndrome[0x20];
8799
8800 u8 reserved_at_40[0x40];
8801 };
8802
8803 struct mlx5_ifc_destroy_vport_lag_in_bits {
8804 u8 opcode[0x10];
8805 u8 reserved_at_10[0x10];
8806
8807 u8 reserved_at_20[0x10];
8808 u8 op_mod[0x10];
8809
8810 u8 reserved_at_40[0x40];
8811 };
8812
8813 #endif /* MLX5_IFC_H */
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