2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 #if defined(__cplusplus)
36 /* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
41 * DOC: uevents generated by i915 on it's device node
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * the GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT "ERROR"
63 #define I915_RESET_UEVENT "RESET"
66 * MOCS indexes used for GPU surfaces, defining the cacheability of the
67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
69 enum i915_mocs_table_index
{
71 * Not cached anywhere, coherency between CPU and GPU accesses is
76 * Cacheability and coherency controlled by the kernel automatically
77 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
78 * usage of the surface (used for display scanout or not).
82 * Cached in all GPU caches available on the platform.
83 * Coherency between CPU and GPU accesses to the surface is not
84 * guaranteed without extra synchronization.
90 * Different engines serve different roles, and there may be more than one
91 * engine serving each role. enum drm_i915_gem_engine_class provides a
92 * classification of the role of the engine, which may be used when requesting
93 * operations to be performed on a certain subset of engines, or for providing
94 * information about that group.
96 enum drm_i915_gem_engine_class
{
97 I915_ENGINE_CLASS_RENDER
= 0,
98 I915_ENGINE_CLASS_COPY
= 1,
99 I915_ENGINE_CLASS_VIDEO
= 2,
100 I915_ENGINE_CLASS_VIDEO_ENHANCE
= 3,
102 I915_ENGINE_CLASS_INVALID
= -1
105 /* Each region is a minimum of 16k, and there are at most 255 of them.
107 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
108 * of chars for next/prev indices */
109 #define I915_LOG_MIN_TEX_REGION_SIZE 14
111 typedef struct _drm_i915_init
{
113 I915_INIT_DMA
= 0x01,
114 I915_CLEANUP_DMA
= 0x02,
115 I915_RESUME_DMA
= 0x03
117 unsigned int mmio_offset
;
118 int sarea_priv_offset
;
119 unsigned int ring_start
;
120 unsigned int ring_end
;
121 unsigned int ring_size
;
122 unsigned int front_offset
;
123 unsigned int back_offset
;
124 unsigned int depth_offset
;
128 unsigned int pitch_bits
;
129 unsigned int back_pitch
;
130 unsigned int depth_pitch
;
132 unsigned int chipset
;
135 typedef struct _drm_i915_sarea
{
136 struct drm_tex_region texList
[I915_NR_TEX_REGIONS
+ 1];
137 int last_upload
; /* last time texture was uploaded */
138 int last_enqueue
; /* last time a buffer was enqueued */
139 int last_dispatch
; /* age of the most recently dispatched buffer */
140 int ctxOwner
; /* last context to upload state */
142 int pf_enabled
; /* is pageflipping allowed? */
144 int pf_current_page
; /* which buffer is being displayed? */
145 int perf_boxes
; /* performance boxes to be displayed */
146 int width
, height
; /* screen size in pixels */
148 drm_handle_t front_handle
;
152 drm_handle_t back_handle
;
156 drm_handle_t depth_handle
;
160 drm_handle_t tex_handle
;
163 int log_tex_granularity
;
165 int rotation
; /* 0, 90, 180 or 270 */
169 int virtualX
, virtualY
;
171 unsigned int front_tiled
;
172 unsigned int back_tiled
;
173 unsigned int depth_tiled
;
174 unsigned int rotated_tiled
;
175 unsigned int rotated2_tiled
;
186 /* fill out some space for old userspace triple buffer */
187 drm_handle_t unused_handle
;
188 __u32 unused1
, unused2
, unused3
;
190 /* buffer object handles for static buffers. May change
191 * over the lifetime of the client.
193 __u32 front_bo_handle
;
194 __u32 back_bo_handle
;
195 __u32 unused_bo_handle
;
196 __u32 depth_bo_handle
;
200 /* due to userspace building against these headers we need some compat here */
201 #define planeA_x pipeA_x
202 #define planeA_y pipeA_y
203 #define planeA_w pipeA_w
204 #define planeA_h pipeA_h
205 #define planeB_x pipeB_x
206 #define planeB_y pipeB_y
207 #define planeB_w pipeB_w
208 #define planeB_h pipeB_h
210 /* Flags for perf_boxes
212 #define I915_BOX_RING_EMPTY 0x1
213 #define I915_BOX_FLIP 0x2
214 #define I915_BOX_WAIT 0x4
215 #define I915_BOX_TEXTURE_LOAD 0x8
216 #define I915_BOX_LOST_CONTEXT 0x10
219 * i915 specific ioctls.
221 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
222 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
223 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
225 #define DRM_I915_INIT 0x00
226 #define DRM_I915_FLUSH 0x01
227 #define DRM_I915_FLIP 0x02
228 #define DRM_I915_BATCHBUFFER 0x03
229 #define DRM_I915_IRQ_EMIT 0x04
230 #define DRM_I915_IRQ_WAIT 0x05
231 #define DRM_I915_GETPARAM 0x06
232 #define DRM_I915_SETPARAM 0x07
233 #define DRM_I915_ALLOC 0x08
234 #define DRM_I915_FREE 0x09
235 #define DRM_I915_INIT_HEAP 0x0a
236 #define DRM_I915_CMDBUFFER 0x0b
237 #define DRM_I915_DESTROY_HEAP 0x0c
238 #define DRM_I915_SET_VBLANK_PIPE 0x0d
239 #define DRM_I915_GET_VBLANK_PIPE 0x0e
240 #define DRM_I915_VBLANK_SWAP 0x0f
241 #define DRM_I915_HWS_ADDR 0x11
242 #define DRM_I915_GEM_INIT 0x13
243 #define DRM_I915_GEM_EXECBUFFER 0x14
244 #define DRM_I915_GEM_PIN 0x15
245 #define DRM_I915_GEM_UNPIN 0x16
246 #define DRM_I915_GEM_BUSY 0x17
247 #define DRM_I915_GEM_THROTTLE 0x18
248 #define DRM_I915_GEM_ENTERVT 0x19
249 #define DRM_I915_GEM_LEAVEVT 0x1a
250 #define DRM_I915_GEM_CREATE 0x1b
251 #define DRM_I915_GEM_PREAD 0x1c
252 #define DRM_I915_GEM_PWRITE 0x1d
253 #define DRM_I915_GEM_MMAP 0x1e
254 #define DRM_I915_GEM_SET_DOMAIN 0x1f
255 #define DRM_I915_GEM_SW_FINISH 0x20
256 #define DRM_I915_GEM_SET_TILING 0x21
257 #define DRM_I915_GEM_GET_TILING 0x22
258 #define DRM_I915_GEM_GET_APERTURE 0x23
259 #define DRM_I915_GEM_MMAP_GTT 0x24
260 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
261 #define DRM_I915_GEM_MADVISE 0x26
262 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
263 #define DRM_I915_OVERLAY_ATTRS 0x28
264 #define DRM_I915_GEM_EXECBUFFER2 0x29
265 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
266 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
267 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
268 #define DRM_I915_GEM_WAIT 0x2c
269 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
270 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
271 #define DRM_I915_GEM_SET_CACHING 0x2f
272 #define DRM_I915_GEM_GET_CACHING 0x30
273 #define DRM_I915_REG_READ 0x31
274 #define DRM_I915_GET_RESET_STATS 0x32
275 #define DRM_I915_GEM_USERPTR 0x33
276 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
277 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
278 #define DRM_I915_PERF_OPEN 0x36
279 #define DRM_I915_PERF_ADD_CONFIG 0x37
280 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
282 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
283 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
284 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
285 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
286 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
287 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
288 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
289 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
290 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
291 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
292 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
293 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
294 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
295 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
296 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
297 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
298 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
299 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
300 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
301 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
302 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
303 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
304 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
305 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
306 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
307 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
308 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
309 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
310 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
311 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
312 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
313 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
314 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
315 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
316 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
317 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
318 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
319 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
320 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
321 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
322 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
323 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
324 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
325 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
326 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
327 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
328 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
329 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
330 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
331 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
332 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
333 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
334 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
335 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
336 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
337 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
339 /* Allow drivers to submit batchbuffers directly to hardware, relying
340 * on the security mechanisms provided by hardware.
342 typedef struct drm_i915_batchbuffer
{
343 int start
; /* agp offset */
344 int used
; /* nr bytes in use */
345 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
346 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
347 int num_cliprects
; /* mulitpass with multiple cliprects? */
348 struct drm_clip_rect __user
*cliprects
; /* pointer to userspace cliprects */
349 } drm_i915_batchbuffer_t
;
351 /* As above, but pass a pointer to userspace buffer which can be
352 * validated by the kernel prior to sending to hardware.
354 typedef struct _drm_i915_cmdbuffer
{
355 char __user
*buf
; /* pointer to userspace command buffer */
356 int sz
; /* nr bytes in buf */
357 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
358 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
359 int num_cliprects
; /* mulitpass with multiple cliprects? */
360 struct drm_clip_rect __user
*cliprects
; /* pointer to userspace cliprects */
361 } drm_i915_cmdbuffer_t
;
363 /* Userspace can request & wait on irq's:
365 typedef struct drm_i915_irq_emit
{
367 } drm_i915_irq_emit_t
;
369 typedef struct drm_i915_irq_wait
{
371 } drm_i915_irq_wait_t
;
373 /* Ioctl to query kernel params:
375 #define I915_PARAM_IRQ_ACTIVE 1
376 #define I915_PARAM_ALLOW_BATCHBUFFER 2
377 #define I915_PARAM_LAST_DISPATCH 3
378 #define I915_PARAM_CHIPSET_ID 4
379 #define I915_PARAM_HAS_GEM 5
380 #define I915_PARAM_NUM_FENCES_AVAIL 6
381 #define I915_PARAM_HAS_OVERLAY 7
382 #define I915_PARAM_HAS_PAGEFLIPPING 8
383 #define I915_PARAM_HAS_EXECBUF2 9
384 #define I915_PARAM_HAS_BSD 10
385 #define I915_PARAM_HAS_BLT 11
386 #define I915_PARAM_HAS_RELAXED_FENCING 12
387 #define I915_PARAM_HAS_COHERENT_RINGS 13
388 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
389 #define I915_PARAM_HAS_RELAXED_DELTA 15
390 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
391 #define I915_PARAM_HAS_LLC 17
392 #define I915_PARAM_HAS_ALIASING_PPGTT 18
393 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
394 #define I915_PARAM_HAS_SEMAPHORES 20
395 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
396 #define I915_PARAM_HAS_VEBOX 22
397 #define I915_PARAM_HAS_SECURE_BATCHES 23
398 #define I915_PARAM_HAS_PINNED_BATCHES 24
399 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
400 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
401 #define I915_PARAM_HAS_WT 27
402 #define I915_PARAM_CMD_PARSER_VERSION 28
403 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
404 #define I915_PARAM_MMAP_VERSION 30
405 #define I915_PARAM_HAS_BSD2 31
406 #define I915_PARAM_REVISION 32
407 #define I915_PARAM_SUBSLICE_TOTAL 33
408 #define I915_PARAM_EU_TOTAL 34
409 #define I915_PARAM_HAS_GPU_RESET 35
410 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
411 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
412 #define I915_PARAM_HAS_POOLED_EU 38
413 #define I915_PARAM_MIN_EU_IN_POOL 39
414 #define I915_PARAM_MMAP_GTT_VERSION 40
417 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
418 * priorities and the driver will attempt to execute batches in priority order.
419 * The param returns a capability bitmask, nonzero implies that the scheduler
420 * is enabled, with different features present according to the mask.
422 * The initial priority for each batch is supplied by the context and is
423 * controlled via I915_CONTEXT_PARAM_PRIORITY.
425 #define I915_PARAM_HAS_SCHEDULER 41
426 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
427 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
428 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
430 #define I915_PARAM_HUC_STATUS 42
432 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
433 * synchronisation with implicit fencing on individual objects.
434 * See EXEC_OBJECT_ASYNC.
436 #define I915_PARAM_HAS_EXEC_ASYNC 43
438 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
439 * both being able to pass in a sync_file fd to wait upon before executing,
440 * and being able to return a new sync_file fd that is signaled when the
441 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
443 #define I915_PARAM_HAS_EXEC_FENCE 44
445 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
446 * user specified bufffers for post-mortem debugging of GPU hangs. See
447 * EXEC_OBJECT_CAPTURE.
449 #define I915_PARAM_HAS_EXEC_CAPTURE 45
451 #define I915_PARAM_SLICE_MASK 46
453 /* Assuming it's uniform for each slice, this queries the mask of subslices
454 * per-slice for this system.
456 #define I915_PARAM_SUBSLICE_MASK 47
459 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
460 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
462 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
464 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
465 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
467 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
469 typedef struct drm_i915_getparam
{
472 * WARNING: Using pointers instead of fixed-size u64 means we need to write
473 * compat32 code. Don't repeat this mistake.
476 } drm_i915_getparam_t
;
478 /* Ioctl to set kernel params:
480 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
481 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
482 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
483 #define I915_SETPARAM_NUM_USED_FENCES 4
485 typedef struct drm_i915_setparam
{
488 } drm_i915_setparam_t
;
490 /* A memory manager for regions of shared memory:
492 #define I915_MEM_REGION_AGP 1
494 typedef struct drm_i915_mem_alloc
{
498 int __user
*region_offset
; /* offset from start of fb or agp */
499 } drm_i915_mem_alloc_t
;
501 typedef struct drm_i915_mem_free
{
504 } drm_i915_mem_free_t
;
506 typedef struct drm_i915_mem_init_heap
{
510 } drm_i915_mem_init_heap_t
;
512 /* Allow memory manager to be torn down and re-initialized (eg on
515 typedef struct drm_i915_mem_destroy_heap
{
517 } drm_i915_mem_destroy_heap_t
;
519 /* Allow X server to configure which pipes to monitor for vblank signals
521 #define DRM_I915_VBLANK_PIPE_A 1
522 #define DRM_I915_VBLANK_PIPE_B 2
524 typedef struct drm_i915_vblank_pipe
{
526 } drm_i915_vblank_pipe_t
;
528 /* Schedule buffer swap at given vertical blank:
530 typedef struct drm_i915_vblank_swap
{
531 drm_drawable_t drawable
;
532 enum drm_vblank_seq_type seqtype
;
533 unsigned int sequence
;
534 } drm_i915_vblank_swap_t
;
536 typedef struct drm_i915_hws_addr
{
538 } drm_i915_hws_addr_t
;
540 struct drm_i915_gem_init
{
542 * Beginning offset in the GTT to be managed by the DRM memory
547 * Ending offset in the GTT to be managed by the DRM memory
553 struct drm_i915_gem_create
{
555 * Requested size for the object.
557 * The (page-aligned) allocated size for the object will be returned.
561 * Returned handle for the object.
563 * Object handles are nonzero.
569 struct drm_i915_gem_pread
{
570 /** Handle for the object being read. */
573 /** Offset into the object to read from */
575 /** Length of data to read */
578 * Pointer to write the data into.
580 * This is a fixed-size type for 32/64 compatibility.
585 struct drm_i915_gem_pwrite
{
586 /** Handle for the object being written to. */
589 /** Offset into the object to write to */
591 /** Length of data to write */
594 * Pointer to read the data from.
596 * This is a fixed-size type for 32/64 compatibility.
601 struct drm_i915_gem_mmap
{
602 /** Handle for the object being mapped. */
605 /** Offset in the object to map. */
608 * Length of data to map.
610 * The value will be page-aligned.
614 * Returned pointer the data was mapped at.
616 * This is a fixed-size type for 32/64 compatibility.
621 * Flags for extended behaviour.
623 * Added in version 2.
626 #define I915_MMAP_WC 0x1
629 struct drm_i915_gem_mmap_gtt
{
630 /** Handle for the object being mapped. */
634 * Fake offset to use for subsequent mmap call
636 * This is a fixed-size type for 32/64 compatibility.
641 struct drm_i915_gem_set_domain
{
642 /** Handle for the object */
645 /** New read domains */
648 /** New write domain */
652 struct drm_i915_gem_sw_finish
{
653 /** Handle for the object */
657 struct drm_i915_gem_relocation_entry
{
659 * Handle of the buffer being pointed to by this relocation entry.
661 * It's appealing to make this be an index into the mm_validate_entry
662 * list to refer to the buffer, but this allows the driver to create
663 * a relocation list for state buffers and not re-write it per
664 * exec using the buffer.
669 * Value to be added to the offset of the target buffer to make up
670 * the relocation entry.
674 /** Offset in the buffer the relocation entry will be written into */
678 * Offset value of the target buffer that the relocation entry was last
681 * If the buffer has the same offset as last time, we can skip syncing
682 * and writing the relocation. This value is written back out by
683 * the execbuffer ioctl when the relocation is written.
685 __u64 presumed_offset
;
688 * Target memory domains read by this operation.
693 * Target memory domains written by this operation.
695 * Note that only one domain may be written by the whole
696 * execbuffer operation, so that where there are conflicts,
697 * the application will get -EINVAL back.
703 * Intel memory domains
705 * Most of these just align with the various caches in
706 * the system and are used to flush and invalidate as
707 * objects end up cached in different domains.
710 #define I915_GEM_DOMAIN_CPU 0x00000001
711 /** Render cache, used by 2D and 3D drawing */
712 #define I915_GEM_DOMAIN_RENDER 0x00000002
713 /** Sampler cache, used by texture engine */
714 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
715 /** Command queue, used to load batch buffers */
716 #define I915_GEM_DOMAIN_COMMAND 0x00000008
717 /** Instruction cache, used by shader programs */
718 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
719 /** Vertex address cache */
720 #define I915_GEM_DOMAIN_VERTEX 0x00000020
721 /** GTT domain - aperture and scanout */
722 #define I915_GEM_DOMAIN_GTT 0x00000040
723 /** WC domain - uncached access */
724 #define I915_GEM_DOMAIN_WC 0x00000080
727 struct drm_i915_gem_exec_object
{
729 * User's handle for a buffer to be bound into the GTT for this
734 /** Number of relocations to be performed on this buffer */
735 __u32 relocation_count
;
737 * Pointer to array of struct drm_i915_gem_relocation_entry containing
738 * the relocations to be performed in this buffer.
742 /** Required alignment in graphics aperture */
746 * Returned value of the updated offset of the object, for future
747 * presumed_offset writes.
752 struct drm_i915_gem_execbuffer
{
754 * List of buffers to be validated with their relocations to be
755 * performend on them.
757 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
759 * These buffers must be listed in an order such that all relocations
760 * a buffer is performing refer to buffers that have already appeared
761 * in the validate list.
766 /** Offset in the batchbuffer to start execution from. */
767 __u32 batch_start_offset
;
768 /** Bytes used in batchbuffer from batch_start_offset */
773 /** This is a struct drm_clip_rect *cliprects */
777 struct drm_i915_gem_exec_object2
{
779 * User's handle for a buffer to be bound into the GTT for this
784 /** Number of relocations to be performed on this buffer */
785 __u32 relocation_count
;
787 * Pointer to array of struct drm_i915_gem_relocation_entry containing
788 * the relocations to be performed in this buffer.
792 /** Required alignment in graphics aperture */
796 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
797 * the user with the GTT offset at which this object will be pinned.
798 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
799 * presumed_offset of the object.
800 * During execbuffer2 the kernel populates it with the value of the
801 * current GTT offset of the object, for future presumed_offset writes.
805 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
806 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
807 #define EXEC_OBJECT_WRITE (1<<2)
808 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
809 #define EXEC_OBJECT_PINNED (1<<4)
810 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
811 /* The kernel implicitly tracks GPU activity on all GEM objects, and
812 * synchronises operations with outstanding rendering. This includes
813 * rendering on other devices if exported via dma-buf. However, sometimes
814 * this tracking is too coarse and the user knows better. For example,
815 * if the object is split into non-overlapping ranges shared between different
816 * clients or engines (i.e. suballocating objects), the implicit tracking
817 * by kernel assumes that each operation affects the whole object rather
818 * than an individual range, causing needless synchronisation between clients.
819 * The kernel will also forgo any CPU cache flushes prior to rendering from
820 * the object as the client is expected to be also handling such domain
823 * The kernel maintains the implicit tracking in order to manage resources
824 * used by the GPU - this flag only disables the synchronisation prior to
825 * rendering with this object in this execbuf.
827 * Opting out of implicit synhronisation requires the user to do its own
828 * explicit tracking to avoid rendering corruption. See, for example,
829 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
831 #define EXEC_OBJECT_ASYNC (1<<6)
832 /* Request that the contents of this execobject be copied into the error
833 * state upon a GPU hang involving this batch for post-mortem debugging.
834 * These buffers are recorded in no particular order as "user" in
835 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
836 * if the kernel supports this flag.
838 #define EXEC_OBJECT_CAPTURE (1<<7)
839 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
840 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
850 struct drm_i915_gem_exec_fence
{
852 * User's handle for a drm_syncobj to wait on or signal.
856 #define I915_EXEC_FENCE_WAIT (1<<0)
857 #define I915_EXEC_FENCE_SIGNAL (1<<1)
858 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
862 struct drm_i915_gem_execbuffer2
{
864 * List of gem_exec_object2 structs
869 /** Offset in the batchbuffer to start execution from. */
870 __u32 batch_start_offset
;
871 /** Bytes used in batchbuffer from batch_start_offset */
877 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
878 * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
879 * struct drm_i915_gem_exec_fence *fences.
882 #define I915_EXEC_RING_MASK (0x3f)
883 #define I915_EXEC_DEFAULT (0<<0)
884 #define I915_EXEC_RENDER (1<<0)
885 #define I915_EXEC_BSD (2<<0)
886 #define I915_EXEC_BLT (3<<0)
887 #define I915_EXEC_VEBOX (4<<0)
889 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
890 * Gen6+ only supports relative addressing to dynamic state (default) and
891 * absolute addressing.
893 * These flags are ignored for the BSD and BLT rings.
895 #define I915_EXEC_CONSTANTS_MASK (3<<6)
896 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
897 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
898 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
900 __u64 rsvd1
; /* now used for context info */
904 /** Resets the SO write offset registers for transform feedback on gen7. */
905 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
907 /** Request a privileged ("secure") batch buffer. Note only available for
908 * DRM_ROOT_ONLY | DRM_MASTER processes.
910 #define I915_EXEC_SECURE (1<<9)
912 /** Inform the kernel that the batch is and will always be pinned. This
913 * negates the requirement for a workaround to be performed to avoid
914 * an incoherent CS (such as can be found on 830/845). If this flag is
915 * not passed, the kernel will endeavour to make sure the batch is
916 * coherent with the CS before execution. If this flag is passed,
917 * userspace assumes the responsibility for ensuring the same.
919 #define I915_EXEC_IS_PINNED (1<<10)
921 /** Provide a hint to the kernel that the command stream and auxiliary
922 * state buffers already holds the correct presumed addresses and so the
923 * relocation process may be skipped if no buffers need to be moved in
924 * preparation for the execbuffer.
926 #define I915_EXEC_NO_RELOC (1<<11)
928 /** Use the reloc.handle as an index into the exec object array rather
929 * than as the per-file handle.
931 #define I915_EXEC_HANDLE_LUT (1<<12)
933 /** Used for switching BSD rings on the platforms with two BSD rings */
934 #define I915_EXEC_BSD_SHIFT (13)
935 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
936 /* default ping-pong mode */
937 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
938 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
939 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
941 /** Tell the kernel that the batchbuffer is processed by
942 * the resource streamer.
944 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
946 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
947 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
950 * Returns -EINVAL if the sync_file fd cannot be found.
952 #define I915_EXEC_FENCE_IN (1<<16)
954 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
955 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
956 * to the caller, and it should be close() after use. (The fd is a regular
957 * file descriptor and will be cleaned up on process termination. It holds
958 * a reference to the request, but nothing else.)
960 * The sync_file fd can be combined with other sync_file and passed either
961 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
962 * will only occur after this request completes), or to other devices.
964 * Using I915_EXEC_FENCE_OUT requires use of
965 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
966 * back to userspace. Failure to do so will cause the out-fence to always
967 * be reported as zero, and the real fence fd to be leaked.
969 #define I915_EXEC_FENCE_OUT (1<<17)
972 * Traditionally the execbuf ioctl has only considered the final element in
973 * the execobject[] to be the executable batch. Often though, the client
974 * will known the batch object prior to construction and being able to place
975 * it into the execobject[] array first can simplify the relocation tracking.
976 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
977 * execobject[] as the * batch instead (the default is to use the last
980 #define I915_EXEC_BATCH_FIRST (1<<18)
982 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
983 * define an array of i915_gem_exec_fence structures which specify a set of
984 * dma fences to wait upon or signal.
986 #define I915_EXEC_FENCE_ARRAY (1<<19)
988 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
990 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
991 #define i915_execbuffer2_set_context_id(eb2, context) \
992 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
993 #define i915_execbuffer2_get_context_id(eb2) \
994 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
996 struct drm_i915_gem_pin
{
997 /** Handle of the buffer to be pinned. */
1001 /** alignment required within the aperture */
1004 /** Returned GTT offset of the buffer. */
1008 struct drm_i915_gem_unpin
{
1009 /** Handle of the buffer to be unpinned. */
1014 struct drm_i915_gem_busy
{
1015 /** Handle of the buffer to check for busy */
1018 /** Return busy status
1020 * A return of 0 implies that the object is idle (after
1021 * having flushed any pending activity), and a non-zero return that
1022 * the object is still in-flight on the GPU. (The GPU has not yet
1023 * signaled completion for all pending requests that reference the
1024 * object.) An object is guaranteed to become idle eventually (so
1025 * long as no new GPU commands are executed upon it). Due to the
1026 * asynchronous nature of the hardware, an object reported
1027 * as busy may become idle before the ioctl is completed.
1029 * Furthermore, if the object is busy, which engine is busy is only
1030 * provided as a guide. There are race conditions which prevent the
1031 * report of which engines are busy from being always accurate.
1032 * However, the converse is not true. If the object is idle, the
1033 * result of the ioctl, that all engines are idle, is accurate.
1035 * The returned dword is split into two fields to indicate both
1036 * the engines on which the object is being read, and the
1037 * engine on which it is currently being written (if any).
1039 * The low word (bits 0:15) indicate if the object is being written
1040 * to by any engine (there can only be one, as the GEM implicit
1041 * synchronisation rules force writes to be serialised). Only the
1042 * engine for the last write is reported.
1044 * The high word (bits 16:31) are a bitmask of which engines are
1045 * currently reading from the object. Multiple engines may be
1046 * reading from the object simultaneously.
1048 * The value of each engine is the same as specified in the
1049 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
1050 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
1051 * the I915_EXEC_RENDER engine for execution, and so it is never
1052 * reported as active itself. Some hardware may have parallel
1053 * execution engines, e.g. multiple media engines, which are
1054 * mapped to the same identifier in the EXECBUFFER2 ioctl and
1055 * so are not separately reported for busyness.
1058 * Only the boolean result of this query is reliable; that is whether
1059 * the object is idle or busy. The report of which engines are busy
1060 * should be only used as a heuristic.
1068 * GPU access is not coherent with cpu caches. Default for machines without an
1071 #define I915_CACHING_NONE 0
1073 * I915_CACHING_CACHED
1075 * GPU access is coherent with cpu caches and furthermore the data is cached in
1076 * last-level caches shared between cpu cores and the gpu GT. Default on
1077 * machines with HAS_LLC.
1079 #define I915_CACHING_CACHED 1
1081 * I915_CACHING_DISPLAY
1083 * Special GPU caching mode which is coherent with the scanout engines.
1084 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1085 * cache mode (like write-through or gfdt flushing) is available. The kernel
1086 * automatically sets this mode when using a buffer as a scanout target.
1087 * Userspace can manually set this mode to avoid a costly stall and clflush in
1088 * the hotpath of drawing the first frame.
1090 #define I915_CACHING_DISPLAY 2
1092 struct drm_i915_gem_caching
{
1094 * Handle of the buffer to set/get the caching level of. */
1098 * Cacheing level to apply or return value
1100 * bits0-15 are for generic caching control (i.e. the above defined
1101 * values). bits16-31 are reserved for platform-specific variations
1102 * (e.g. l3$ caching on gen7). */
1106 #define I915_TILING_NONE 0
1107 #define I915_TILING_X 1
1108 #define I915_TILING_Y 2
1109 #define I915_TILING_LAST I915_TILING_Y
1111 #define I915_BIT_6_SWIZZLE_NONE 0
1112 #define I915_BIT_6_SWIZZLE_9 1
1113 #define I915_BIT_6_SWIZZLE_9_10 2
1114 #define I915_BIT_6_SWIZZLE_9_11 3
1115 #define I915_BIT_6_SWIZZLE_9_10_11 4
1116 /* Not seen by userland */
1117 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
1118 /* Seen by userland. */
1119 #define I915_BIT_6_SWIZZLE_9_17 6
1120 #define I915_BIT_6_SWIZZLE_9_10_17 7
1122 struct drm_i915_gem_set_tiling
{
1123 /** Handle of the buffer to have its tiling state updated */
1127 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1130 * This value is to be set on request, and will be updated by the
1131 * kernel on successful return with the actual chosen tiling layout.
1133 * The tiling mode may be demoted to I915_TILING_NONE when the system
1134 * has bit 6 swizzling that can't be managed correctly by GEM.
1136 * Buffer contents become undefined when changing tiling_mode.
1141 * Stride in bytes for the object when in I915_TILING_X or
1147 * Returned address bit 6 swizzling required for CPU access through
1153 struct drm_i915_gem_get_tiling
{
1154 /** Handle of the buffer to get tiling state for. */
1158 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1164 * Returned address bit 6 swizzling required for CPU access through
1170 * Returned address bit 6 swizzling required for CPU access through
1171 * mmap mapping whilst bound.
1173 __u32 phys_swizzle_mode
;
1176 struct drm_i915_gem_get_aperture
{
1177 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1181 * Available space in the aperture used by i915_gem_execbuffer, in
1184 __u64 aper_available_size
;
1187 struct drm_i915_get_pipe_from_crtc_id
{
1188 /** ID of CRTC being requested **/
1191 /** pipe of requested CRTC **/
1195 #define I915_MADV_WILLNEED 0
1196 #define I915_MADV_DONTNEED 1
1197 #define __I915_MADV_PURGED 2 /* internal state */
1199 struct drm_i915_gem_madvise
{
1200 /** Handle of the buffer to change the backing store advice */
1203 /* Advice: either the buffer will be needed again in the near future,
1204 * or wont be and could be discarded under memory pressure.
1208 /** Whether the backing store still exists. */
1213 #define I915_OVERLAY_TYPE_MASK 0xff
1214 #define I915_OVERLAY_YUV_PLANAR 0x01
1215 #define I915_OVERLAY_YUV_PACKED 0x02
1216 #define I915_OVERLAY_RGB 0x03
1218 #define I915_OVERLAY_DEPTH_MASK 0xff00
1219 #define I915_OVERLAY_RGB24 0x1000
1220 #define I915_OVERLAY_RGB16 0x2000
1221 #define I915_OVERLAY_RGB15 0x3000
1222 #define I915_OVERLAY_YUV422 0x0100
1223 #define I915_OVERLAY_YUV411 0x0200
1224 #define I915_OVERLAY_YUV420 0x0300
1225 #define I915_OVERLAY_YUV410 0x0400
1227 #define I915_OVERLAY_SWAP_MASK 0xff0000
1228 #define I915_OVERLAY_NO_SWAP 0x000000
1229 #define I915_OVERLAY_UV_SWAP 0x010000
1230 #define I915_OVERLAY_Y_SWAP 0x020000
1231 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1233 #define I915_OVERLAY_FLAGS_MASK 0xff000000
1234 #define I915_OVERLAY_ENABLE 0x01000000
1236 struct drm_intel_overlay_put_image
{
1237 /* various flags and src format description */
1239 /* source picture description */
1241 /* stride values and offsets are in bytes, buffer relative */
1242 __u16 stride_Y
; /* stride for packed formats */
1244 __u32 offset_Y
; /* offset for packet formats */
1250 /* to compensate the scaling factors for partially covered surfaces */
1251 __u16 src_scan_width
;
1252 __u16 src_scan_height
;
1253 /* output crtc description */
1262 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1263 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1264 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1265 struct drm_intel_overlay_attrs
{
1280 * Intel sprite handling
1282 * Color keying works with a min/mask/max tuple. Both source and destination
1283 * color keying is allowed.
1286 * Sprite pixels within the min & max values, masked against the color channels
1287 * specified in the mask field, will be transparent. All other pixels will
1288 * be displayed on top of the primary plane. For RGB surfaces, only the min
1289 * and mask fields will be used; ranged compares are not allowed.
1291 * Destination keying:
1292 * Primary plane pixels that match the min value, masked against the color
1293 * channels specified in the mask field, will be replaced by corresponding
1294 * pixels from the sprite plane.
1296 * Note that source & destination keying are exclusive; only one can be
1297 * active on a given plane.
1300 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
1301 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1302 #define I915_SET_COLORKEY_SOURCE (1<<2)
1303 struct drm_intel_sprite_colorkey
{
1311 struct drm_i915_gem_wait
{
1312 /** Handle of BO we shall wait on */
1315 /** Number of nanoseconds to wait, Returns time remaining. */
1319 struct drm_i915_gem_context_create
{
1320 /* output: id of new context*/
1325 struct drm_i915_gem_context_destroy
{
1330 struct drm_i915_reg_read
{
1333 * For 64bit wide registers where the upper 32bits don't immediately
1334 * follow the lower 32bits, the offset of the lower 32bits must
1338 #define I915_REG_READ_8B_WA (1ul << 0)
1340 __u64 val
; /* Return value */
1344 * Render engine timestamp - 0x2358 + 64bit - gen7+
1345 * - Note this register returns an invalid value if using the default
1346 * single instruction 8byte read, in order to workaround that pass
1347 * flag I915_REG_READ_8B_WA in offset field.
1351 struct drm_i915_reset_stats
{
1355 /* All resets since boot/module reload, for all contexts */
1358 /* Number of batches lost when active in GPU, for this context */
1361 /* Number of batches lost pending for execution, for this context */
1362 __u32 batch_pending
;
1367 struct drm_i915_gem_userptr
{
1371 #define I915_USERPTR_READ_ONLY 0x1
1372 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1374 * Returned handle for the object.
1376 * Object handles are nonzero.
1381 struct drm_i915_gem_context_param
{
1385 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1386 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1387 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1388 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1389 #define I915_CONTEXT_PARAM_BANNABLE 0x5
1390 #define I915_CONTEXT_PARAM_PRIORITY 0x6
1391 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1392 #define I915_CONTEXT_DEFAULT_PRIORITY 0
1393 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1397 enum drm_i915_oa_format
{
1398 I915_OA_FORMAT_A13
= 1, /* HSW only */
1399 I915_OA_FORMAT_A29
, /* HSW only */
1400 I915_OA_FORMAT_A13_B8_C8
, /* HSW only */
1401 I915_OA_FORMAT_B4_C8
, /* HSW only */
1402 I915_OA_FORMAT_A45_B8_C8
, /* HSW only */
1403 I915_OA_FORMAT_B4_C8_A16
, /* HSW only */
1404 I915_OA_FORMAT_C4_B8
, /* HSW+ */
1408 I915_OA_FORMAT_A12_B8_C8
,
1409 I915_OA_FORMAT_A32u40_A4u32_B8_C8
,
1411 I915_OA_FORMAT_MAX
/* non-ABI */
1414 enum drm_i915_perf_property_id
{
1416 * Open the stream for a specific context handle (as used with
1417 * execbuffer2). A stream opened for a specific context this way
1418 * won't typically require root privileges.
1420 DRM_I915_PERF_PROP_CTX_HANDLE
= 1,
1423 * A value of 1 requests the inclusion of raw OA unit reports as
1424 * part of stream samples.
1426 DRM_I915_PERF_PROP_SAMPLE_OA
,
1429 * The value specifies which set of OA unit metrics should be
1430 * be configured, defining the contents of any OA unit reports.
1432 DRM_I915_PERF_PROP_OA_METRICS_SET
,
1435 * The value specifies the size and layout of OA unit reports.
1437 DRM_I915_PERF_PROP_OA_FORMAT
,
1440 * Specifying this property implicitly requests periodic OA unit
1441 * sampling and (at least on Haswell) the sampling frequency is derived
1442 * from this exponent as follows:
1444 * 80ns * 2^(period_exponent + 1)
1446 DRM_I915_PERF_PROP_OA_EXPONENT
,
1448 DRM_I915_PERF_PROP_MAX
/* non-ABI */
1451 struct drm_i915_perf_open_param
{
1453 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1454 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1455 #define I915_PERF_FLAG_DISABLED (1<<2)
1457 /** The number of u64 (id, value) pairs */
1458 __u32 num_properties
;
1461 * Pointer to array of u64 (id, value) pairs configuring the stream
1464 __u64 properties_ptr
;
1468 * Enable data capture for a stream that was either opened in a disabled state
1469 * via I915_PERF_FLAG_DISABLED or was later disabled via
1470 * I915_PERF_IOCTL_DISABLE.
1472 * It is intended to be cheaper to disable and enable a stream than it may be
1473 * to close and re-open a stream with the same configuration.
1475 * It's undefined whether any pending data for the stream will be lost.
1477 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1480 * Disable data capture for a stream.
1482 * It is an error to try and read a stream that is disabled.
1484 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1487 * Common to all i915 perf records
1489 struct drm_i915_perf_record_header
{
1495 enum drm_i915_perf_record_type
{
1498 * Samples are the work horse record type whose contents are extensible
1499 * and defined when opening an i915 perf stream based on the given
1502 * Boolean properties following the naming convention
1503 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1506 * The order of these sample properties given by userspace has no
1507 * affect on the ordering of data within a sample. The order is
1511 * struct drm_i915_perf_record_header header;
1513 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1516 DRM_I915_PERF_RECORD_SAMPLE
= 1,
1519 * Indicates that one or more OA reports were not written by the
1520 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1521 * command collides with periodic sampling - which would be more likely
1522 * at higher sampling frequencies.
1524 DRM_I915_PERF_RECORD_OA_REPORT_LOST
= 2,
1527 * An error occurred that resulted in all pending OA reports being lost.
1529 DRM_I915_PERF_RECORD_OA_BUFFER_LOST
= 3,
1531 DRM_I915_PERF_RECORD_MAX
/* non-ABI */
1535 * Structure to upload perf dynamic configuration into the kernel.
1537 struct drm_i915_perf_oa_config
{
1538 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
1542 __u32 n_boolean_regs
;
1546 * These fields are pointers to tuples of u32 values (register
1547 * address, value). For example the expected length of the buffer
1548 * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
1551 __u64 boolean_regs_ptr
;
1552 __u64 flex_regs_ptr
;
1555 #if defined(__cplusplus)
1559 #endif /* _UAPI_I915_DRM_H_ */