ZTE ZX296702 I2S controller
Required properties:
- - compatible : Must be "zte,zx296702-i2s"
+ - compatible : Must be one of:
+ "zte,zx296718-i2s", "zte,zx296702-i2s"
+ "zte,zx296702-i2s"
- reg : Must contain I2S core's registers location and length
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
- - clock-names: "tx" for the clock to the I2S interface.
+ - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
- dmas: Pairs of phandle and specifier for the DMA channel that is used by
the core. The core expects two dma channels for transmit.
- dma-names : Must be "tx" and "rx"
* dma/dma.txt
Example:
- i2s0: i2s0@0b005000 {
+ i2s0: i2s@b005000 {
#sound-dai-cells = <0>;
- compatible = "zte,zx296702-i2s";
+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x0b005000 0x1000>;
- clocks = <&lsp0clk ZX296702_I2S0_DIV>;
- clock-names = "tx";
+ clocks = <&audiocrm AUDIO_I2S0_WCLK>, <&audiocrm AUDIO_I2S0_PCLK>;
+ clock-names = "wclk", "pclk";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma 5>, <&dma 6>;
dma-names = "tx", "rx";
static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
static const struct snd_kcontrol_new wm8753_snd_controls[] = {
+SOC_SINGLE("Hi-Fi DAC Left/Right channel Swap", WM8753_HIFI, 5, 1, 0),
SOC_DOUBLE_R_TLV("PCM Volume", WM8753_LDAC, WM8753_RDAC, 0, 255, 0, dac_tlv),
SOC_DOUBLE_R_TLV("ADC Capture Volume", WM8753_LADC, WM8753_RADC, 0, 255, 0,
{
u16 ioctl, hifi;
- hifi = snd_soc_read(codec, WM8753_HIFI) & 0x011f;
+ hifi = snd_soc_read(codec, WM8753_HIFI) & 0x013f;
ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x00ae;
/* set master/slave audio interface */
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
void __iomem *reg_base;
int master;
resource_size_t mapbase;
struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(socdai);
struct snd_dmaengine_dai_dma_data *dma_data;
unsigned int lane, ch_num, len, ret = 0;
- unsigned long val, format;
+ unsigned long val;
unsigned long chn_cfg;
dma_data = snd_soc_dai_get_dma_data(socdai, substream);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
- format = 0;
len = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
- format = 1;
len = 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
- format = 2;
len = 32;
break;
default:
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ ret = clk_set_rate(i2s->dai_wclk,
+ params_rate(params) * ch_num * CLK_RAT);
+
return ret;
}
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
- return clk_prepare_enable(zx_i2s->dai_clk);
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
+
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(&pdev->dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(&pdev->dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(&pdev->dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_err(&pdev->dev, "Fail to get pclk\n");
+ return PTR_ERR(zx_i2s->dai_pclk);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);