clk: ingenic: jz4740: Fix gating of UDC clock

BugLink: https://bugs.launchpad.net/bugs/1863019
[ Upstream commit b7e29924a1a628aec60d18651b493fa1601bf944 ]

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9cae ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 32fcc75f6f77e362279775dd9b20444660347911..689b43d8b5bba3b19f3229b291d1d795d7030c7f 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
                .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
                .mux = { CGU_REG_CPCCR, 29, 1 },
                .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-               .gate = { CGU_REG_SCR, 6 },
+               .gate = { CGU_REG_SCR, 6, true },
        },
 
        /* Gate-only clocks */