dmaengine: dw-dmac: implement dma protection control setting

BugLink: https://bugs.launchpad.net/bugs/1857158
[ Upstream commit 7b0c03ecc42fb223baf015877fee9d517c2c8af1 ]

This patch adds a new device-tree property that allows to
specify the dma protection control bits for the all of the
DMA controller's channel uniformly.

Setting the "correct" bits can have a huge impact on the
PPC460EX and APM82181 that use this DMA engine in combination
with a DesignWare' SATA-II core (sata_dwc_460ex driver).

In the OpenWrt Forum, the user takimata reported that:
|It seems your patch unleashed the full power of the SATA port.
|Where I was previously hitting a really hard limit at around
|82 MB/s for reading and 27 MB/s for writing, I am now getting this:
|
|root@OpenWrt:/mnt# time dd if=/dev/zero of=tempfile bs=1M count=1024
|1024+0 records in
|1024+0 records out
|real    0m 13.65s
|user    0m 0.01s
|sys     0m 11.89s
|
|root@OpenWrt:/mnt# time dd if=tempfile of=/dev/null bs=1M count=1024
|1024+0 records in
|1024+0 records out
|real    0m 8.41s
|user    0m 0.01s
|sys     0m 4.70s
|
|This means: 121 MB/s reading and 75 MB/s writing!
|
|The drive is a WD Green WD10EARX taken from an older MBL Single.
|I repeated the test a few times with even larger files to rule out
|any caching, I'm still seeing the same great performance. OpenWrt is
|now completely on par with the original MBL firmware's performance.

Another user And.short reported:
|I can report that your fix worked! Boots up fine with two
|drives even with more partitions, and no more reboot on
|concurrent disk access!

A closer look into the sata_dwc_460ex code revealed that
the driver did initally set the correct protection control
bits. However, this feature was lost when the sata_dwc_460ex
driver was converted to the generic DMA driver framework.

BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/55
BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/50
Fixes: 8b3444852a2b ("sata_dwc_460ex: move to generic DMA driver")
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 0f389e008ce64ac0c55f71ce44549d464c0e4c1e..055d83b6cb68af4bbf6798abf09c7ff749607224 100644 (file)
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
 
 static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
 {
+       struct dw_dma *dw = to_dw_dma(dwc->chan.device);
        u32 cfghi = DWC_CFGH_FIFO_MODE;
        u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
        bool hs_polarity = dwc->dws.hs_polarity;
 
        cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
        cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
+       cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
 
        /* Set polarity of handshake interface */
        cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;

diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index bc31fe8020619d6e2bbff5ec1e49786bb3193d7b..46a519e07195c73846a7672f04fc19417b948301 100644 (file)
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *pdev)
                        pdata->multi_block[tmp] = 1;
        }
 
+       if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
+               if (tmp > CHAN_PROTCTL_MASK)
+                       return NULL;
+               pdata->protctl = tmp;
+       }
+
        return pdata;
 }
 #else

diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 09e7dfdbb7907df6217b65fb6b2ff3a96520e2ec..646c9c960c071a40b9dad231c5298f44106aa2f4 100644 (file)
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -200,6 +200,10 @@ enum dw_dma_msize {
 #define DWC_CFGH_FCMODE                (1 << 0)
 #define DWC_CFGH_FIFO_MODE     (1 << 1)
 #define DWC_CFGH_PROTCTL(x)    ((x) << 2)
+#define DWC_CFGH_PROTCTL_DATA  (0 << 2)        /* data access - always set */
+#define DWC_CFGH_PROTCTL_PRIV  (1 << 2)        /* privileged -> AHB HPROT[1] */
+#define DWC_CFGH_PROTCTL_BUFFER        (2 << 2)        /* bufferable -> AHB HPROT[2] */
+#define DWC_CFGH_PROTCTL_CACHE (4 << 2)        /* cacheable  -> AHB HPROT[3] */
 #define DWC_CFGH_DS_UPD_EN     (1 << 5)
 #define DWC_CFGH_SS_UPD_EN     (1 << 6)
 #define DWC_CFGH_SRC_PER(x)    ((x) << 7)

diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 896cb71a382cbf4aa8eff220638310895f0ee965..1a1d58ebffbf1f43179b87d7eafc0071b7af38a3 100644 (file)
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -49,6 +49,7 @@ struct dw_dma_slave {
  * @data_width: Maximum data width supported by hardware per AHB master
  *             (in bytes, power of 2)
  * @multi_block: Multi block transfers supported by hardware per channel.
+ * @protctl: Protection control signals setting per channel.
  */
 struct dw_dma_platform_data {
        unsigned int    nr_channels;
@@ -65,6 +66,11 @@ struct dw_dma_platform_data {
        unsigned char   nr_masters;
        unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
        unsigned char   multi_block[DW_DMA_MAX_NR_CHANNELS];
+#define CHAN_PROTCTL_PRIVILEGED                BIT(0)
+#define CHAN_PROTCTL_BUFFERABLE                BIT(1)
+#define CHAN_PROTCTL_CACHEABLE         BIT(2)
+#define CHAN_PROTCTL_MASK              GENMASK(2, 0)
+       unsigned char   protctl;
 };
 
 #endif /* _PLATFORM_DATA_DMA_DW_H */