spi: tegra114: terminate dma and reset on transfer timeout

BugLink: https://bugs.launchpad.net/bugs/1863019
[ Upstream commit 32bd1a9551cae34e6889afa235c7afdfede9aeac ]

Fixes: terminate DMA and perform controller reset on transfer timeout
to clear the FIFO's and errors.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 17c2c78318f71fadf278811cf8c3ef62aff8fd2f..b1b726673f8504531a2fa3a7a6fb7bf05db08f71 100644 (file)
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -869,7 +869,16 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
                if (WARN_ON(ret == 0)) {
                        dev_err(tspi->dev,
                                "spi transfer timeout, err %d\n", ret);
+                       if (tspi->is_curr_dma_xfer &&
+                           (tspi->cur_direction & DATA_DIR_TX))
+                               dmaengine_terminate_all(tspi->tx_dma_chan);
+                       if (tspi->is_curr_dma_xfer &&
+                           (tspi->cur_direction & DATA_DIR_RX))
+                               dmaengine_terminate_all(tspi->rx_dma_chan);
                        ret = -EIO;
+                       reset_control_assert(tspi->rst);
+                       udelay(2);
+                       reset_control_deassert(tspi->rst);
                        goto complete_xfer;
                }