Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull  more x86 pti fixes from Thomas Gleixner:
 "Another small stash of fixes for fallout from the PTI work:

   - Fix the modules vs. KASAN breakage which was caused by making
     MODULES_END depend of the fixmap size. That was done when the cpu
     entry area moved into the fixmap, but now that we have a separate
     map space for that this is causing more issues than it solves.

   - Use the proper cache flush methods for the debugstore buffers as
     they are mapped/unmapped during runtime and not statically mapped
     at boot time like the rest of the cpu entry area.

   - Make the map layout of the cpu_entry_area consistent for 4 and 5
     level paging and fix the KASLR vaddr_end wreckage.

   - Use PER_CPU_EXPORT for per cpu variable and while at it unbreak
     nvidia gfx drivers by dropping the GPL export. The subject line of
     the commit tells it the other way around, but I noticed that too
     late.

   - Fix the ASM alternative macros so they can be used in the middle of
     an inline asm block.

   - Rename the BUG_CPU_INSECURE flag to BUG_CPU_MELTDOWN so the attack
     vector is properly identified. The Spectre mitigations will come
     with their own bug bits later"

* 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/pti: Rename BUG_CPU_INSECURE to BUG_CPU_MELTDOWN
  x86/alternatives: Add missing '\n' at end of ALTERNATIVE inline asm
  x86/tlb: Drop the _GPL from the cpu_tlbstate export
  x86/events/intel/ds: Use the proper cache flush method for mapping ds buffers
  x86/kaslr: Fix the vaddr_end mess
  x86/mm: Map cpu_entry_area at the same place on 4/5 level
  x86/mm: Set MODULES_END to 0xffffffffff000000

diff --combined arch/x86/kernel/cpu/common.c
index 7d9e3b06209b8f36bf1ddd690308df76485c7950,2d3bd2215e5b47b87e6383dd1386e871e71bbcde..39d7ea865207d102d2f03fc9ca779b2bdbb03c61
--- 1/arch/x86/kernel/cpu/common.c
--- 2/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@@ -329,30 -329,6 +329,30 @@@ static __always_inline void setup_smap(
        }
  }
  
 +static __always_inline void setup_umip(struct cpuinfo_x86 *c)
 +{
 +      /* Check the boot processor, plus build option for UMIP. */
 +      if (!cpu_feature_enabled(X86_FEATURE_UMIP))
 +              goto out;
 +
 +      /* Check the current processor's cpuid bits. */
 +      if (!cpu_has(c, X86_FEATURE_UMIP))
 +              goto out;
 +
 +      cr4_set_bits(X86_CR4_UMIP);
 +
 +      pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n");
 +
 +      return;
 +
 +out:
 +      /*
 +       * Make sure UMIP is disabled in case it was enabled in a
 +       * previous boot (e.g., via kexec).
 +       */
 +      cr4_clear_bits(X86_CR4_UMIP);
 +}
 +
  /*
   * Protection Keys are not available in 32-bit mode.
   */
@@@ -882,8 -858,8 +882,8 @@@ static void identify_cpu_without_cpuid(
   * cache alignment.
   * The others are not touched to avoid unwanted side effects.
   *
 - * WARNING: this function is only called on the BP.  Don't add code here
 - * that is supposed to run on all CPUs.
 + * WARNING: this function is only called on the boot CPU.  Don't add code
 + * here that is supposed to run on all CPUs.
   */
  static void __init early_identify_cpu(struct cpuinfo_x86 *c)
  {
@@@ -924,7 -900,7 +924,7 @@@
        setup_force_cpu_cap(X86_FEATURE_ALWAYS);
  
        if (c->x86_vendor != X86_VENDOR_AMD)
-               setup_force_cpu_bug(X86_BUG_CPU_INSECURE);
+               setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
  
        fpu__init_system(c);
  
@@@ -1170,10 -1146,9 +1170,10 @@@ static void identify_cpu(struct cpuinfo
        /* Disable the PN if appropriate */
        squash_the_stupid_serial_number(c);
  
 -      /* Set up SMEP/SMAP */
 +      /* Set up SMEP/SMAP/UMIP */
        setup_smep(c);
        setup_smap(c);
 +      setup_umip(c);
  
        /*
         * The vendor-specific functions might have changed features.

diff --combined arch/x86/mm/init.c
index 8ca324d072828e19700ba094dbeae433b767c964,6b462a472a7bfbc19f0b5a3b0e83a22ab1f72179..82f5252c723a4a544593067981d90191c7b22c1d
--- 1/arch/x86/mm/init.c
--- 2/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@@ -93,7 -93,8 +93,7 @@@ __ref void *alloc_low_pages(unsigned in
                unsigned int order;
  
                order = get_order((unsigned long)num << PAGE_SHIFT);
 -              return (void *)__get_free_pages(GFP_ATOMIC | __GFP_NOTRACK |
 -                                              __GFP_ZERO, order);
 +              return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
        }
  
        if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
@@@ -170,11 -171,12 +170,11 @@@ static void enable_global_pages(void
  static void __init probe_page_size_mask(void)
  {
        /*
 -       * For CONFIG_KMEMCHECK or pagealloc debugging, identity mapping will
 -       * use small pages.
 +       * For pagealloc debugging, identity mapping will use small pages.
         * This will simplify cpa(), which otherwise needs to support splitting
         * large pages into small in interrupt context, etc.
         */
 -      if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled() && !IS_ENABLED(CONFIG_KMEMCHECK))
 +      if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
                page_size_mask |= 1 << PG_LEVEL_2M;
        else
                direct_gbpages = 0;
@@@ -868,7 -870,7 +868,7 @@@ __visible DEFINE_PER_CPU_SHARED_ALIGNED
        .next_asid = 1,
        .cr4 = ~0UL,    /* fail hard if we screw up cr4 shadow initialization */
  };
- EXPORT_SYMBOL_GPL(cpu_tlbstate);
+ EXPORT_PER_CPU_SYMBOL(cpu_tlbstate);
  
  void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
  {