xtensa: increase ranges in ___invalidate_{i,d}cache_all

BugLink: https://bugs.launchpad.net/bugs/1835972
commit fec3259c9f747c039f90e99570540114c8d81a14 upstream.

Cache invalidation macros use cache line size to iterate over
invalidated cache lines, assuming that all cache ways are invalidated by
single instruction, but xtensa ISA recommends to not assume that for
future compatibility:
  In some implementations all ways at index Addry-1..z are invalidated
  regardless of the specified way, but for future compatibility this
  behavior should not be assumed.

Iterate over all cache ways in ___invalidate_icache_all and
___invalidate_dcache_all.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
index 2c73b45712261688e07c5984a8681f57335abcca..34545ecfdd6b7332df7fb486930f1f35c5532640 100644 (file)
--- a/arch/xtensa/include/asm/cacheasm.h
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -123,7 +123,7 @@
        .macro  ___invalidate_dcache_all ar at
 
 #if XCHAL_DCACHE_SIZE
-       __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
+       __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
                         XCHAL_DCACHE_LINEWIDTH 1020
 #endif
 
@@ -133,7 +133,7 @@
        .macro  ___invalidate_icache_all ar at
 
 #if XCHAL_ICACHE_SIZE
-       __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
+       __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
                         XCHAL_ICACHE_LINEWIDTH 1020
 #endif