drm/i915: Unify the appearance of gen3/4 irq_postistall hooks

Do the irq_mask/enable_mask setup in the same way on gen3/4, and also
reorder the steps to make the code more uniform.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-9-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6431f4ebb726f7dd5b7af1eb528e9604df795a5d..b51aeed59e7179eda2a8b9556ea7f43ba5afebad 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3769,8 +3769,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
 
        GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
 
-       i915_enable_asle_pipestat(dev_priv);
-
        /* Interrupt setup is already guaranteed to be single-threaded, this is
         * just to make the assert_spin_locked check happy. */
        spin_lock_irq(&dev_priv->irq_lock);
@@ -3778,6 +3776,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
        spin_unlock_irq(&dev_priv->irq_lock);
 
+       i915_enable_asle_pipestat(dev_priv);
+
        return 0;
 }
 
@@ -3935,18 +3935,26 @@ static int i965_irq_postinstall(struct drm_device *dev)
        I915_WRITE(EMR, error_mask);
 
        /* Unmask the interrupts that we always want on. */
-       dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
-                              I915_DISPLAY_PORT_INTERRUPT |
-                              I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-                              I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-                              I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
+       dev_priv->irq_mask =
+               ~(I915_ASLE_INTERRUPT |
+                 I915_DISPLAY_PORT_INTERRUPT |
+                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 
-       enable_mask = ~dev_priv->irq_mask;
-       enable_mask |= I915_USER_INTERRUPT;
+       enable_mask =
+               I915_ASLE_INTERRUPT |
+               I915_DISPLAY_PORT_INTERRUPT |
+               I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+               I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+               I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
+               I915_USER_INTERRUPT;
 
        if (IS_G4X(dev_priv))
                enable_mask |= I915_BSD_USER_INTERRUPT;
 
+       GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+
        /* Interrupt setup is already guaranteed to be single-threaded, this is
         * just to make the assert_spin_locked check happy. */
        spin_lock_irq(&dev_priv->irq_lock);
@@ -3955,8 +3963,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
        spin_unlock_irq(&dev_priv->irq_lock);
 
-       GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
-
        i915_enable_asle_pipestat(dev_priv);
 
        return 0;