clk: samsung: exynos3250: Fix PLL rates

BugLink: http://bugs.launchpad.net/bugs/1783418
[ Upstream commit a8321e7887410a2b2e80ab89d1ef7b30562658ea ]

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. If that is not the case, rate of the PLL's child clock
might be set not as expected. For instance, if in the PLL rates table we have
a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
will return 393216003. If we now attempt to set rate of a PLL's child divider
clock to 393216000/2 its rate will be 131072001, rather than 196608000.
That is, the divider will be set to 3 instead of 2, because 393216003/2 is
greater than 196608000.

To fix this issue declared rates are changed to exactly match rates generated
by the PLL, as calculated from the P, M, S, K coefficients.

In this patch an erroneous P value for 74176002 output frequency is also
corrected.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 1b81e283f60589c900c5bfc6370a125d8c8c845d..ed36728424a21f31d3ff3317c96a5ba16270484d 100644 (file)
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -698,7 +698,7 @@ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst =
        PLL_36XX_RATE(144000000,  96, 2, 3,     0),
        PLL_36XX_RATE( 96000000, 128, 2, 4,     0),
        PLL_36XX_RATE( 84000000, 112, 2, 4,     0),
-       PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
+       PLL_36XX_RATE( 80000003, 106, 2, 4, 43691),
        PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),
        PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
        PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
@@ -734,7 +734,7 @@ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst =
        PLL_36XX_RATE(148352005,  98, 2, 3, 59070),
        PLL_36XX_RATE(108000000, 144, 2, 4,     0),
        PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
-       PLL_36XX_RATE( 74176002,  98, 3, 4, 59070),
+       PLL_36XX_RATE( 74176002,  98, 2, 4, 59070),
        PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
        PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
        { /* sentinel */ }