Chris Wilson [Mon, 11 Sep 2017 08:41:26 +0000 (09:41 +0100)]
drm/i915/fence: Avoid del_timer_sync() from inside a timer
A fence may be signaled from any context, including from inside a timer.
One example is timer_i915_sw_fence_wake() which is used to provide a
safety-net when waiting on an external fence. If the external fence is
not signaled within a timely fashion, we signal our fence on its behalf,
and so we then may process subsequent fences in the chain from within
that timer context.
Given that dma_i915_sw_fence_wake() may be from inside a timer, we cannot
then use del_timer_sync() as that requires the timer lock for itself. To
circumvent this, while trying to keep the signal propagation as low
latency as possible, move the completion into a worker and use a bit of
atomic switheroo to serialise the timer-callback and the dma-callback.
Chris Wilson [Mon, 18 Sep 2017 16:46:52 +0000 (17:46 +0100)]
drm/i915/selftests: Only touch archdata.iommu when it exists
archdata.iommu only exists when CONFIG_IOMMU_API is enabled (and only
applies to intel-iommu in our case) so conditionally compile it out when
it doesn't exist.
drm/i915/cnp: Don't touch other PCH clock gating bits.
Don't touch other bits. My bad.
I haven't seen any case where those other bits appeard to be
set before we touch it, but it is safe to avoid touching
other bits we weren't told to touch.
Some platforms do not support PSR and DRRS simultaneously.
Visual artifacts and flickering were reported on BDW HP Spectre
x360 Convertible. Deferring to PSR when both PSR and DRRS are
supported by the panel.
V2: Minor code-style changes suggested by Rodrigo
V3: Add a WARN_ON during PSR init suggested by Dhinakaran
Correct debug message,title suggested by Jani
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101111 Cc: Nicholas Stommel <nicholas.stommel@gmail.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914181641.24393-1-radhakrishna.sripada@intel.com
Chris Wilson [Thu, 14 Sep 2017 16:22:40 +0000 (17:22 +0100)]
drm/i915/selftests: Disable iommu for the mock device
On some machines, the iommu cannot allocate a domain for the mock device
causing the dma_map_sg() to fail, and the selftest to fail with -ENOMEM.
For the mock selftests, we are using a fake device and do not care about
iommu; so convince intel_iommu to treat us as a dummy device with an
identity mapping (and no iommu domain).
Zhi Wang [Mon, 18 Sep 2017 13:36:34 +0000 (21:36 +0800)]
drm/i915: Return the correct score in i915_ppat_get()
The cache attribute of the required entry has to be the same with the
existing value. After this requirement is met, the futher comparison
should be performed. After this fix, the refined test case can pass.
v2:
- Refine the tittle and comments. (Rodrigo)
Fixes: 4395890a4855 ("drm/i915: Introduce private PAT management") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505741794-10593-1-git-send-email-zhi.a.wang@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Michał Winiarski [Mon, 18 Sep 2017 09:25:35 +0000 (11:25 +0200)]
drm/i915/guc: Cleanup adding GuC work items
We can just operate on the wq_tail directly (in the process descriptor).
This allows us to remove the duplicated tail from the client. While I'm
here let's also remove the constants kept in the client and document our
locking requirements. This causes a small change in one of GuC debugfs
files. We're no longer reporting constant values (which I don't think
is a problem), but we're also no longer reporting the tail (does anyone
care?).
v2: Update tail after wqi contents. (Chris)
v3: Really update tail after wqi contents.
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170918092536.12287-1-michal.winiarski@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Michał Winiarski [Thu, 14 Sep 2017 10:51:23 +0000 (12:51 +0200)]
drm/i915/guc: Simplify GuC doorbell logic
All we're really doing is incrementing a simple counter in a
doorbell_info struct. We can do without extra variables and a separate
counter kept in guc_client. Since it's gone, we're also removing its
debugfs.
The only functional change here, is that we're no longer treating 0 as a
special value. GuC doesn't seem to care, why should we?
v2: Restore desc->tail update.
v3: Drop the retry loop, assert that doorbell cookie doesn't change
behind our back.
v4: WARN rather than BUG, use xchg. (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914105125.3031-1-michal.winiarski@intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to stop pretending
that we're doing "lite-restore" in GuC submission (we would create a
workitem each time we hit this condition). This allows us to completely
remove the reservation, replacing it with a compile time check.
v2: Also coalesce when replaying on reset (Daniele)
v3: Consistent wq_resv - per-request (Daniele)
v4: Squash removing wq_resv
v5: Reflect i915_guc_submit argument changes in doc
v6: Rebase on top of execlists reset/restart fix (Chris,Michał)
References: https://bugs.freedesktop.org/show_bug.cgi?id=101873 Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170914083216.10192-2-michal.winiarski@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Michał Winiarski [Thu, 14 Sep 2017 08:32:12 +0000 (10:32 +0200)]
drm/i915/guc: Remove obsolete comments and remove unused variable
Originally removed in: c1adab970348 ("drm/i915/guc: Remove failed doorbell stat from debugfs") f1448a62a103 ("drm/i915/guc: Remove last submission result from debugfs")
Were accidentally restored in: 925344ccc91d ("BackMerge tag 'v4.12-rc5' into drm-next")
We can also remove unused variable and replace it with a WARN.
Chris Wilson [Sat, 16 Sep 2017 20:44:14 +0000 (21:44 +0100)]
drm/i915/execlists: Unwind incomplete requests on resets
Given the mechanism to unwind and replay requests (designed to support
preemption), we have an alternative to the current method of
resubmitting the ELSP upon reset. Resubmitting ELSP turns out to be more
complicated than expected, due to having to handle lost context-switch
interrupts and so guessing what ELSP we need to resubmit later. Instead,
by unwinding the requests and clearing the ELSP tracking entirely, we
can then just dequeue the first pair of ready requests after resetting,
using the normal submission procedure.
Currently, the unwound requests have maximum priority and so are
guaranteed to be resubmitted upon resume. If we are lucky, we may be
able to coalesce a new request on top!
Suggested-by: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170916204414.32762-4-chris@chris-wilson.co.uk Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Chris Wilson [Sat, 16 Sep 2017 20:44:13 +0000 (21:44 +0100)]
drm/i915/execlists: Split insert_request()
In the next patch we will want to reinsert a request not at the end of
the priority queue, but at the front. Here we split insert_request()
into two, the first function retrieves the priority list (for reuse for
unsubmit later) and a wrapper function to insert at the end of that list
and to schedule the tasklet if we were first.
Chris Wilson [Sat, 16 Sep 2017 20:44:11 +0000 (21:44 +0100)]
drm/i915/execlists: Kick start request processing after a reset
During a reset, we may skip over completed requests and lost
context-switch interrupts. Following the reset, we may then may end up
with no active requests in the ELSP (and so do not resubmit to restart
the engine), but have a queue of requests ready for execution. This is
unlikely, it requires the last request to complete after the hang is
detected, but not impossible. The outcome of this is that the engine
stalls, possibly leading to full ring and indefinite wait under
struct_mutex, eventually leading to a full driver hang.
Alternatively, we can solve this by unsubmitting the incomplete requests
and just kickstarting the tasklet. Michał has patches for that, which I
initially disliked due to the extra complexity, but the complexity of
this "simple" restart is growing...
Chris Wilson [Fri, 15 Sep 2017 17:31:00 +0000 (18:31 +0100)]
drm/i915: Cancel all ready but queued requests when wedging
When wedging the hw, we want to mark all in-flight requests as -EIO.
This is made slightly more complex by execlists who store the ready but
not yet submitted-to-hw requests on a private queue (an rbtree
priolist). Call into execlists to cancel not only the ELSP tracking for
the submitted requests, but also the queue of unsubmitted requests.
v2: Move the majority of engine_set_wedged to the backends (both legacy
ringbuffer and execlists handling their own lists).
Reported-by: Michał Winiarski <michal.winiarski@intel.com>
Testcase: igt/gem_eio/in-flight-contexts Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170915173100.26470-1-chris@chris-wilson.co.uk Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Ville Syrjälä [Fri, 18 Aug 2017 18:37:05 +0000 (21:37 +0300)]
drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x
Now that we're not using MSI anymore on gen4 we can start
using GMBUS and AUX interrupts again. These were disabled on
account of them causing the hardware to somehow generate
legacy interrupts even when MSI was enabled.
See commit c12aba5aa0e6 ("drm/i915: stop using GMBUS IRQs on Gen4
chips") and commit 4e6b788c3f23 ("drm/i915: Disable dp aux irq on
g4x") for more details.
Ville Syrjälä [Fri, 18 Aug 2017 18:37:03 +0000 (21:37 +0300)]
drm/i915: Clean up the HWSTAM mess
Currently we're unmasking some random looking bits in HWSTAM
on gen3/4/5. The two bits we apparently unmask are 0 and 12,
and also bits 16-31 on gen4/5.
What those bits do depends on the gen as follows:
bit 0: Breakpoint (gen2), ASLE (gen3), reserved (gen4), render user interrupt (gen5)
bit 12: Sync flush statusa (gen2-4), reserved (gen5)
bit 16-31: The ones that can unmasked seem to be mostly some
display stuff on gen4. Bit 18 is the PIPE_CONTROL notify,
which might be the only intresting one. On gen5 all the
bits are reserved.
So I don't know whether we actually depend on that status page write
somehow. Extra seqno coherency by accident perhaps? Except we don't
even unmask the user interrupt bit in HWSTAM except on gen5, and
sync flush isn't something we use normally, so seems unlikely. So
let's just assume we don't need any of this and mask everything in
HWSTAM.
From gen6 onwards there's a separate HWSTAM for each engine, and so
we deal with them during the engine setup.
Ville Syrjälä [Fri, 18 Aug 2017 18:37:01 +0000 (21:37 +0300)]
drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode
The execlist code already masks everything in the ring HWSTAM, but
the ringbuffer code doesn't. Let's go ahead and do that. Pre-gen6
platforms setup HWSTAM during irq setup already since there's just
the one register, and it also contains bits for non-ring interrupts.
Michal Wajdeczko [Thu, 14 Sep 2017 15:08:03 +0000 (15:08 +0000)]
drm/i915: Extend private i915_param_named macro with description
We're always specifying description of each module param in
separate macro. Let's combine description into our main macro.
Started with Coccinelle, followed by minor cleanup.
@fix1 depends on match1@
declarer name i915_param_named;
declarer name i915_param_named_unsafe;
identifier match1.n;
constant match1.c;
@@
(
i915_param_named(n, ...
+ , c
);
|
i915_param_named_unsafe(n, ...
+ , c
);
)
Suggested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914150805.28376-4-michal.wajdeczko@intel.com
Michal Wajdeczko [Thu, 14 Sep 2017 15:08:02 +0000 (15:08 +0000)]
drm/i915: Introduce custom variant of module_param_named macro
As we now use same name for public module param and its local
representation we can simplify param definition macro.
Changes done with Coccinelle:
@@
declarer name module_param_named;
declarer name module_param_named_unsafe;
declarer name i915_param_named;
declarer name i915_param_named_unsafe;
identifier n;
@@
Michal Wajdeczko [Thu, 14 Sep 2017 15:08:01 +0000 (15:08 +0000)]
drm/i915: Rename lvds_use_ssc modparam to panel_use_ssc
This modparam affects not only LVDS but also eDP panels. Additionally
with this rename we will keep modparam and i915_params field name in sync.
This patch will unblock us with further improvements around params defs.
Suggested-by: Ville Syrjala <ville.syrjala@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914150805.28376-2-michal.wajdeczko@intel.com
Chris Wilson [Thu, 14 Sep 2017 16:42:13 +0000 (17:42 +0100)]
drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos()
Commit 1bf6ad622b9b ("drm/vblank: drop the mode argument from
drm_calc_vbltimestamp_from_scanoutpos") removed the use of in_vbl, but
did not remove the local variable. Do so now.
Fixes: 1bf6ad622b9b ("drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914164213.18461-1-chris@chris-wilson.co.uk Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
drm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACTION_SHIFT
No functional changes. Only change the macro from
"DPLL_CFGCR0_DC0_FRAC_SHIFT to DPLL_CFGCR0_DCO_FRACTION_SHIFT
to be consistent with DPLL_CFGCR0_DCO_FRACTION_MASK
and DPLL_CFGCR0_DCO_FRACTION
Ville Syrjälä [Fri, 18 Aug 2017 18:37:02 +0000 (21:37 +0300)]
drm/i915: Gen3 HWSTAM is actually 32 bits
Bspec claims that HWSTAM is only 16 bits on gen3, but the other
interrupts registers are 32 bits and there are 18 valid interrupt
bits. Hence a 16 bit HWSTAM wouldn't be able to contain all the
bits, so it seems the spec is incorrect about the size of the
register. And indeed I can clear bits 16 and 17 just fine with
a 32 bit write. So let's adjust the code to treat the register
as 32 bits.
Ville Syrjälä [Fri, 18 Aug 2017 18:37:00 +0000 (21:37 +0300)]
drm/i915: Rewrite GMCH irq handlers to avoid loops
Eliminate the loops from the gen2-3 irq handlers. Since we don't use
MSI anymore on these platforms, and thus the CPU interrupt will be level
triggered, we shouldn't need to play any tricks with IER to induce edges
from IIR. IIR itself still detects only edges from PIPESTAT & co. on
gen4 but since IIR is double buffered and we only clear one bit per irq
handler invocation we can use the normal "clear PIPESTAT & co. -> clear
IIR" approach to ack the interrupts. On gen2 everything is level
triggered, and gen3 presumably follows either the gen2 or gen4 approach
since nothing else would really make sense.
v2: Drop the IER tricks since we no longer use MSI
Ville Syrjälä [Fri, 18 Aug 2017 18:36:59 +0000 (21:36 +0300)]
drm/i915: Extract PIPESTAT irq handling into separate functions
Extract the gen2-4 PIPESTAT irq handling into separate functions just
like we already do on VLV/CHV.
We can share valleyview_pipestat_irq_ack() on all gmch platforms to
actually read and clear the PIPESTAT status bits, so let's rename
it to i9xx_pipestat_irq_ack().
Ville Syrjälä [Fri, 18 Aug 2017 18:36:58 +0000 (21:36 +0300)]
drm/i915: Remove NULL dev_priv checks from irq_uninstall
There should be no way to land in irq_uninstall without a
valid dev_priv. Let's kill off the remaining checks, which are
probably some kind of UMS leftovers. Not all the irq_uninstall
hooks even had them anymore.
Ville Syrjälä [Fri, 18 Aug 2017 18:36:52 +0000 (21:36 +0300)]
drm/i915: s/GEN5/GEN3/
The GEN5_IRQ_RESET/INIT macros are perfectly suitable even for
gen3/4 hardware as those have 32 bit interrupt registers. Let's
rename the macros to reflect that fact.
Gen2 on the other hand has 16 bit interrupt registers so these
macros aren't really appropriate there.
Ville Syrjälä [Fri, 18 Aug 2017 18:36:51 +0000 (21:36 +0300)]
drm/i915: Clear pipestat consistently
We have a lot of different ways of clearing the PIPESTAT registers.
Let's unify it all into one function. There's no magic in PIPESTAT
that would require any of the double clearing and whatnot that
some of the code tries to do. All we can really do is clear the status
bits and disable the enable bits. There is no way to mask anything
so as soon as another event happens the status bit will become set
again, and trying to clear them twice or something can't protect
against that.
Ville Syrjälä [Fri, 18 Aug 2017 18:36:50 +0000 (21:36 +0300)]
drm/i915: Don't enable/unmask flip interrupts
commit fd3a40242e87 ("drm/i915: Rip out legacy page_flip completion/irq
handling") removed the code to hande the flip done/pending interrupts,
but it failed to actually disable/mask those interrupts. Let's do that
now.
Zhi Wang [Thu, 14 Sep 2017 12:39:41 +0000 (20:39 +0800)]
drm/i915: Remove the "INDEX" suffix from PPAT marcos
Remove the "INDEX" suffix from PPAT marcos as they are bits actually, not
indexes.
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505392783-4084-2-git-send-email-zhi.a.wang@intel.com
Zhi Wang [Thu, 14 Sep 2017 12:39:40 +0000 (20:39 +0800)]
drm/i915: Introduce private PAT management
The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_put.
intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate a new
entry if there is any available PPAT indexs, or return a partially
matched PPAT entry if there is no available PPAT indexes.
intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count will
be decreased. If the reference count turns into zero, the PPAT index is
freed again.
Besides, another two callbacks are introduced to support the private PAT
management framework. One is ppat->update_hw(), which writes the PPAT
configurations in ppat->entries into HW. Another one is ppat->match, which
will return a score to show how two PPAT values match with each other.
v17:
- Refine the comparision of score of BDW. (Joonas)
v16:
- Fix a bug in PPAT match function of BDW. (Joonas)
v15:
- Refine some code flow. (Joonas)
v12:
- Fix a problem "not returning the entry of best score". (Zhenyu)
v7:
- Keep all the register writes unchanged in this patch. (Joonas)
v6:
- Address all comments from Chris:
http://www.spinics.net/lists/intel-gfx/msg136850.html
- Address all comments from Joonas:
http://www.spinics.net/lists/intel-gfx/msg136845.html
v5:
- Add check and warnnings for those platforms which don't have PPAT.
v3:
- Introduce dirty bitmap for PPAT registers. (Chris)
- Change the name of the pointer "dev_priv" to "i915". (Chris)
- intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)
v2:
- API re-design. (Chris)
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v7 Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
[Joonas: Use BIT() in the enum in bdw_private_pat_match] Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505392783-4084-1-git-send-email-zhi.a.wang@intel.com
Ville Syrjälä [Thu, 24 Aug 2017 19:10:51 +0000 (22:10 +0300)]
drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for CCS
Use the LLC/eLLC hotspot avoidance mode for CCS on LLC machines. This is
reported to give better performance.
Testing has indicated that we don't need to enforce any massive 2 or 4
MiB alignment for all compressed resources even though there are still
plenty of stale comments in the spec suggesting that we do.
We do need to make sure every hardware unit that deals with the
compressed data uses the same hash mode.
Split INTEL_GEN_MASK out of IS_GEN macro, and make it usable
within static declarations (unlike compound statements).
v2:
- s/combound/compound/ (Tvrtko)
- Fix whitespace (yes, we need automatic checkpatch.pl)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170913115255.13851-1-joonas.lahtinen@linux.intel.com
drm/i915: Refresh VLV/CHV PSR comments on HW PSR_state machine.
DK had pointed out a comment there was hard to understand, so I
tried to read back again and I couldn't understand that as well.
So let me re-phrase that in a way that anyone can understand
later, even myself.
Also fixed the comment block style.
v2: Accept DK's suggestion on PSR_state 2 and PSR_state 3 named
as spec.
Chris Wilson [Wed, 13 Sep 2017 08:56:05 +0000 (09:56 +0100)]
drm/i915/execlists: Read the context-status HEAD from the HWSP
The engine also provides a mirror of the CSB write pointer in the HWSP,
but not of our read pointer. To take advantage of this we need to
remember where we read up to on the last interrupt and continue off from
there. This poses a problem following a reset, as we don't know where
the hw will start writing from, and due to the use of power contexts we
cannot perform that query during the reset itself. So we continue the
current modus operandi of delaying the first read of the context-status
read/write pointers until after the first interrupt. With this we should
now have eliminated all uncached mmio reads in handling the
context-status interrupt, though we still have the uncached mmio writes
for submitting new work, and many uncached mmio reads in the global
interrupt handler itself. Still a step in the right direction towards
reducing our resubmit latency, although it appears lost in the noise!
v2: Cannonlake moved the CSB write index
v3: Include the sw/hwsp state in debugfs/i915_engine_info
v4: Also revert to using CSB mmio for GVT-g
v5: Prevent the compiler reloading tail (Mika)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Acked-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170913085605.18299-6-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Chris Wilson [Wed, 13 Sep 2017 13:35:34 +0000 (14:35 +0100)]
drm/i915/execlists: Read the context-status buffer from the HWSP
The engine provides a mirror of the CSB in the HWSP. If we use the
cacheable reads from the HWSP, we can shave off a few mmio reads per
context-switch interrupt (which are quite frequent!). Just removing a
couple of mmio is not enough to actually reduce any latency, but a small
reduction in overall cpu usage.
Much appreciation for Ben dropping the bombshell that the CSB was in the
HWSP and for Michel in digging out the details.
v2: Don't be lazy, add the defines for the indices.
v3: Include the HWSP in debugfs/i915_engine_info
v4: Check for GVT-g, it currently depends on intercepting CSB mmio
v5: Fixup GVT-g mmio path
v6: Disable HWSP if VT-d is active as the iommu adds unpredictable
memory latency. (Mika)
v7: Also markup the CSB read with READ_ONCE() as it may still be an mmio
read and we want to stop the compiler from issuing a later (v.slow) reload.
Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Acked-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170913133534.26927-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Chris Wilson [Wed, 13 Sep 2017 08:56:03 +0000 (09:56 +0100)]
drm/i915: Allow HW status page to be bound high
At the time of commit 1f767e02d69f ("drm/i915: HWS must be in the
mappable region for g33"), drm_mm insertion would often default to
placing a new object high in the zone forcing us to specify that certain
HWSP must be bound within the low mappable region. Since then, drm_mm
has gained more finesse over its placement and exposes that to the
caller, commit 4e64e5539d15 ("drm: Improve drm_mm search (and fix
topdown allocation) with rbtrees"). As such where possible we want the
HWSP to be outside of the mappable aperture and so need to specify that
can be pinned high.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170913085605.18299-4-chris@chris-wilson.co.uk
On gen8+ we're currently using the PPHWSP of the kernel ctx as the
global HWSP. However, when the kernel ctx gets submitted (e.g. from
__intel_autoenable_gt_powersave) the HW will use that page as both
HWSP and PPHWSP. This causes a conflict in the register arena of the
HWSP, i.e. dword indices below 0x30. We don't current utilize this arena,
but in the following patches we will take advantage of the cached
register state for handling execlist's context status interrupt.
To avoid the conflict, instead of re-using the PPHWSP of the kernel
ctx we can allocate a separate page for the HWSP like what happens for
pre-execlists platform.
v2: Add a use-case for the register arena of the HWSP.
Michel Thierry [Wed, 13 Sep 2017 08:56:01 +0000 (09:56 +0100)]
drm/i915/guc: Don't make assumptions while getting the lrca offset
Using the HWSP ggtt_offset to get the lrca offset is only correct if the
HWSP happens to be before it (when we reuse the PPHWSP of the kernel
context as the engine HWSP). Instead of making this assumption, get the
lrca offset from the kernel_context engine state.
And while looking at this part of the GuC interaction, it was also
noticed that the firmware expects the size of only the engine context
(context minus the execlist part, i.e. don't include the first 80
dwords), so pass the right size.
v2: Use the new macros to prevent abusive overuse of the old ones (Chris).
Michel Thierry [Wed, 13 Sep 2017 08:56:00 +0000 (09:56 +0100)]
drm/i915/lrc: Clarify the format of the context image
Not only the context image consist of two parts (the PPHWSP, and the
logical context state), but we also allocate a header at the start of
for sharing data with GuC. Thus every lrc looks like this:
So far, we have oversimplified whenever we use each of these parts of the
context, just because the GuC header happens to be in page 0, and the
(PP)HWSP is in page 1. But this had led to using the same define for more
than one meaning (as a page index in the lrc and as 1 page).
This patch adds defines for the GuC shared page, the PPHWSP page and the
start of the logical state. It also updated the places where the old
define was being used. Since we are not changing the size (or format) of
the context, there are no functional changes.
Chris Wilson [Wed, 13 Sep 2017 10:51:54 +0000 (11:51 +0100)]
drm/i915/selftests: Use mul_u32_u32() for 32b x 32b -> 64b result
As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
for performing a 32b x 32b multiply returning a 64b result (i.e. where
we idiomatically use u64 result = (u64)x * (u32)x).
Chris Wilson [Wed, 13 Sep 2017 10:51:53 +0000 (11:51 +0100)]
drm/i915: Use mul_u32_u32() for 32b x 32b -> 64b result
As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
for performing a 32b x 32b multiply returning a 64b result (i.e. where
we idiomatically use u64 result = (u64)x * (u32)x). This catches a
couple of instances in the display code using (u64)x * (u32)y.
Chris Wilson [Tue, 12 Sep 2017 21:49:05 +0000 (22:49 +0100)]
drm/i915: Move the context descriptor to an inline helper
The context descriptor is stored inside the per-engine context state, as
we only need to compute it once and access it frequently. However,
currently only intel_lrc.c has easy access, but i915_guc_submission.c
would like to frequently read it as well, and more so only ever needs
the lower 32bits. Make it an inline as the compiler should be able to
retrieve the value in less instructions than it takes to do the function
call:
add/remove: 0/1 grow/shrink: 1/0 up/down: 8/-45 (-37)
function old new delta
i915_guc_submit 621 629 +8
intel_lr_context_descriptor 45 - -45
Min brightness value from vbt was missing for CNP platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.
Uma Shankar [Tue, 5 Sep 2017 09:44:31 +0000 (15:14 +0530)]
Revert "drm/i915/bxt: Disable device ready before shutdown command"
This reverts commit bbdf0b2ff32a ("drm/i915/bxt: Disable device ready
before shutdown command").
Disable device ready before shutdown command was added previously to
avoid a split screen issue seen on dual link DSI panels. As of now, dual
link is not supported and will need some rework in the upstream
code. For single link DSI panels, the change is not required. This will
cause failure in sending SHUTDOWN packet during disable. Hence reverting
the change. Will handle the change as part of dual link enabling in
upstream.
Chris Wilson [Tue, 12 Sep 2017 15:07:52 +0000 (16:07 +0100)]
drm/i915: Cleanup error paths through eb_lookup_vma()
Following the simplification to a single lookup loop in commit 170fa29b14fa ("drm/i915: Simplify eb_lookup_vmas()") and commit d1b48c1e7184 ("drm/i915: Replace execbuf vma ht with an idr"), we can go
one step further and reorder the error paths so that the state of the
local variable obj is always known to the compiler and doesn't need the
uninitialized_var markup to squelch a compiler warning.
drm/i915/spt+: Don't reset invalid AUX channel interrupt bits in SDEIMR
The SDE interrupt bits 25, 26 and 27 are either reserved or meant for
DDI E hotplug in SPT+. These bits are meant for AUX channels only in LPT
and CPT, so add the appropriate checks.
Zhi Wang [Tue, 12 Sep 2017 07:42:24 +0000 (15:42 +0800)]
drm/i915: Factor out setup_private_pat()
Factor out setup_private_pat() for introducing the following patches.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505202148-22959-1-git-send-email-zhi.a.wang@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Min brightness value from vbt was missing for BXT platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.
Marta Lofstedt [Fri, 8 Sep 2017 13:28:29 +0000 (16:28 +0300)]
drm/i915: Increase poll time for BDW FCLK_DONE
During IGT testing it has been shown that the specification
defined polling time of 1 us for FCLK_DONE, is sometimes not
enough. The issue is still reproducible while disabling
C-states through the PM QoS framework and also while disabling
preemtion. From this the most plausible explanation is that the
issue is due to a firmware flaw.
As a workaround, it is better to wait a little bit longer for
the FCLK_DONE to come around, than to leave with an DRM_ERROR
and having FCLK_DONE at a randome time after.
While spinning a list of igt tests prone to reproduce the issue
the FCLK_DONE poll failed at approximately 2% of the invocations
of the bdw_set_cdclk function. The longest poll time during this
testing was measured to ~7us. So, the suggested new poll time of
100us is on the safe side.
v2: Added more documentation about investigations done.
Let's move the activation calls together after enable is done.
No real functional change should be expected here. Just an attempt
to get it clear when we are really activating PSR after enabling it.
v2: Add braces on if/else because commit message there is too long
as suggested by Jani.
v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
crtc_state to PSR enable/disable")
drm/i915/psr: Move hsw_enable_source after enabling sink.
No functional change is expected here since at this point
PSR is not allowed to go to any active state. In other
words, not really enabled.
However let's do in a separated patch so it gets clear
on what is change and specially it can helps on bisect
case if we figure something has caused changes in behaviour.
But this needs to be done before we make the vfunc to
enable source to be in parity with VLV implementation.
This sequence is part of enable source anyways, but they
only need to be executed once and not on every activation,
So let's re-create hsw_enable_source.
v2: Avoid changing order here to avoid changing behaviour
as suggested by Jani.
v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb
crtc_state to PSR enable/disable")
On HSW+ the real activate of PSR is decided by the source
after certain amount of configured idle frames.
However for the driver perspective where we track psr.active
variable this function here is the actual activate one. So
let's rename it before moving to vfunc with that.
Chris Wilson [Fri, 8 Sep 2017 18:16:22 +0000 (19:16 +0100)]
drm/i915: Only initialize partially filled pagetables
If we know that we will completely fill a pagetable (i.e. we are
inserting a complete set of 512 pages), we can skip prefilling that PT
with scratch entries. If we have to abort the insertion prior to writing
the real entries, we will teardown the pagetable and remove it from the
page directory (so that we will restart the allocation next time).
We could do similar tricks for the PD and PDP, but the likelihood of a
single insertion covering the entire 512 entries diminishes, as do the
cycle savings. The saving are even greater (relatively) when we are
preallocating page tables for huge pages, as then we never need to fill
the page table.
Changbin Du [Wed, 23 Aug 2017 06:08:10 +0000 (14:08 +0800)]
drm/i915/gvt: Add support for PCIe extended configuration space
IGD is PCIe device and has extended configuration space. Checking
the binary dump, we can see we have Caps located out of PCI compatible
Configuration Space range.
Currently, we only emulate the PCI compatible Configuration Space.
This is okay if we attach vGPU to PCI bus. But when we attach to
a PCI Express bus (when Qemu emulates a Intel Q35 chipset which has
PCIe slot), it will not work. Extended Configuration Space is required
for a PCIe device.
This patch extended the virtual configuration space from 256 bytes
to 4KB bytes. So we are to be a *real* PCIe device. And for the
Extended CapList we keep same to physical GPU.
Cc: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Changbin Du [Fri, 18 Aug 2017 09:49:58 +0000 (17:49 +0800)]
drm/i915/gvt: Fix incorrect PCI BARs reporting
Looking at our virtual PCI device, we can see surprising Region 4 and Region 5.
00:10.0 VGA compatible controller: Intel Corporation Sky Lake Integrated Graphics (rev 06) (prog-if 00 [VGA controller])
....
Region 0: Memory at 140000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at 180000000 (64-bit, prefetchable) [size=1G]
Region 4: Memory at <ignored> (32-bit, non-prefetchable)
Region 5: Memory at <ignored> (32-bit, non-prefetchable)
Expansion ROM at febd6000 [disabled] [size=2K]
The fact is that we only implemented BAR0 and BAR2. Surprising Region 4 and
Region 5 are shown because we report their size as 0xffffffff. They should
report size 0 instead.
BTW, the physical GPU has a PIO BAR. GVTg hasn't implemented PIO access, so
we ignored this BAR for vGPU device.
fred gao [Fri, 18 Aug 2017 07:41:10 +0000 (15:41 +0800)]
drm/i915/gvt: Refine error handling in dispatch_workload
When an error occurs in dispatch_workload, this patch is to do the
proper cleanup and rollback to the original states before the workload
is abandoned.
v2:
- split the mixed several error paths for better review. (Zhenyu)
v3:
- original PTR_ERR(cs) is good and code cleanup. (Zhenyu)
v4:
- reuse the existing i915_add_request for error handling. (Zhenyu)
v5:
- remove the duplicate error handling release_shadow_wa_ctx and
move the engine->context_unpin upper. (Zhenyu)
v6:
- keep the old label "out". (Zhenyu)
Signed-off-by: fred gao <fred.gao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
fred gao [Fri, 18 Aug 2017 07:41:07 +0000 (15:41 +0800)]
drm/i915/gvt: Add error handling for intel_gvt_scan_and_shadow_workload
When an error occurs after shadow_indirect_ctx, this patch is to do the
proper cleanup and rollback to the original states for shadowed indirect
context before the workload is abandoned.
v2:
- split the mixed several error paths for better review. (Zhenyu)
v3:
- no return check for clean up functions. (Changbin)
v4:
- expose and reuse the existing release_shadow_wa_ctx. (Zhenyu)
v5:
- move the release function to scheduler.c file. (Zhenyu)
v6:
- move error handling code of intel_gvt_scan_and_shadow_workload
to here. (Zhenyu)
Signed-off-by: fred gao <fred.gao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
fred gao [Fri, 18 Aug 2017 07:41:06 +0000 (15:41 +0800)]
drm/i915/gvt: Separate cmd scan from request allocation
Currently i915 request structure and shadow ring buffer are allocated
before command scan, so it will have to restore to previous states once
any error happens afterwards in the long dispatch_workload path.
This patch is to introduce a reserved ring buffer created at the beginning
of vGPU initialization. Workload will be coped to this reserved buffer and
be scanned first, the i915 request and shadow ring buffer are only
allocated after the result of scan is successful.
To balance the memory usage and buffer alloc time, the coming bigger ring
buffer will be reallocated and kept until more bigger buffer is coming.
v2:
- use kmalloc for the smaller ring buffer, realloc if required. (Zhenyu)
v3:
- remove the dynamically allocated ring buffer. (Zhenyu)
Changbin Du [Tue, 15 Aug 2017 05:14:04 +0000 (13:14 +0800)]
drm/i915/gvt: Add emulation for BAR2 (aperture) with normal file RW approach
For vfio-pci, if the region support MMAP then it should support both
mmap and normal file access. The user-space is free to choose which is
being used. For qemu, we just need add 'x-no-mmap=on' for vfio-pci
option.
Currently GVTg only support MMAP for BAR2. So GVTg will not work when
user turn on x-no-mmap option.
This patch added file style access for BAR2, aka the GPU aperture. We
map the entire aperture partition of active vGPU to kernel space when
guest driver try to enable PCI Memory Space. Then we redirect the file
RW operation from kvmgt to this mapped area.
Changbin Du [Tue, 15 Aug 2017 05:20:51 +0000 (13:20 +0800)]
drm/i915/kvmgt: Sanitize PCI bar emulation
For PCI, 64bit bar consumes two BAR registers, but this doesn't mean
both of two BAR are valid. Actually the second BAR is regarded as
reserved in this case. So we shouldn't emulate the second BAR.
Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Oscar Mateo [Thu, 7 Sep 2017 15:40:09 +0000 (08:40 -0700)]
drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write
FF_SLICE_CS_CHICKEN2 does not belong to the context image.
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-6-git-send-email-oscar.mateo@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Oscar Mateo [Thu, 7 Sep 2017 15:40:08 +0000 (08:40 -0700)]
drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write
GAMT_CHKN_BIT_REG does not live in the context image.
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-5-git-send-email-oscar.mateo@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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