net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode

BugLink: https://bugs.launchpad.net/bugs/1959879
[ Upstream commit 0959bc4bd4206433ed101a1332a23e93ad16ec77 ]

Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fixed.
Also, some control bits should be modified with a specific sequence.

Fixes: b38dd98ff8d0 ("net: stmmac: Add Toshiba Visconti SoCs glue driver")
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index 1c599a005aab64bd282008a1ade8c273af8968d5..4578c64953eac351bbb0136aa6c1863cf56b9e83 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -96,31 +96,41 @@ static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed)
        val |= ETHER_CLK_SEL_TX_O_E_N_IN;
        writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
 
+       /* Set Clock-Mux, Start clock, Set TX_O direction */
        switch (dwmac->phy_intf_sel) {
        case ETHER_CONFIG_INTF_RGMII:
                val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+               val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+               val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
                break;
        case ETHER_CONFIG_INTF_RMII:
                val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
-                       ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN |
+                       ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
                        ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+               val |= ETHER_CLK_SEL_RMII_CLK_RST;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+               val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
                break;
        case ETHER_CONFIG_INTF_MII:
        default:
                val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
-                       ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
-                       ETHER_CLK_SEL_RMII_CLK_EN;
+                       ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+               val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+               writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
                break;
        }
 
-       /* Start clock */
-       writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-       val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
-       writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
-       val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
-       writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
        spin_unlock_irqrestore(&dwmac->lock, flags);
 }