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Commit | Line | Data |
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8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
21266be9 | 6 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
8c2c3df3 | 7 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 8 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 9 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 10 | select ARCH_HAS_SG_CHAIN |
1f85008e | 11 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 12 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 13 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 14 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 15 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 16 | select ARCH_WANT_FRAME_POINTERS |
25c92a37 | 17 | select ARM_AMBA |
1aee5d7a | 18 | select ARM_ARCH_TIMER |
c4188edc | 19 | select ARM_GIC |
875cbf3e | 20 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 21 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 22 | select ARM_GIC_V3 |
19812729 | 23 | select ARM_GIC_V3_ITS if PCI_MSI |
bff60792 | 24 | select ARM_PSCI_FW |
adace895 | 25 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 26 | select CLONE_BACKWARDS |
7ca2ef33 | 27 | select COMMON_CLK |
166936ba | 28 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 29 | select DCACHE_WORD_ACCESS |
ef37566c | 30 | select EDAC_SUPPORT |
2f34f173 | 31 | select FRAME_POINTER |
d4932f9e | 32 | select GENERIC_ALLOCATOR |
8c2c3df3 | 33 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 34 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 35 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 36 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 37 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
38 | select GENERIC_IRQ_PROBE |
39 | select GENERIC_IRQ_SHOW | |
6544e67b | 40 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 41 | select GENERIC_PCI_IOMAP |
65cd4f6c | 42 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 43 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
44 | select GENERIC_STRNCPY_FROM_USER |
45 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 46 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 47 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 48 | select HARDIRQS_SW_RESEND |
5284e1b4 | 49 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 50 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 51 | select HAVE_ARCH_BITREVERSE |
9732cafd | 52 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 53 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 54 | select HAVE_ARCH_KGDB |
a1ae65b2 | 55 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 56 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 57 | select HAVE_BPF_JIT |
af64d2aa | 58 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 59 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 60 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 61 | select HAVE_CMPXCHG_LOCAL |
9b2a60c4 | 62 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 63 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 CM |
64 | select HAVE_DMA_API_DEBUG |
65 | select HAVE_DMA_ATTRS | |
6ac2104d | 66 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 67 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 68 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 69 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
70 | select HAVE_FUNCTION_TRACER |
71 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 72 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 73 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 74 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 75 | select HAVE_MEMBLOCK |
55834a77 | 76 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 77 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
78 | select HAVE_PERF_REGS |
79 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 80 | select HAVE_RCU_TABLE_FREE |
055b1212 | 81 | select HAVE_SYSCALL_TRACEPOINTS |
876945db | 82 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 83 | select IRQ_DOMAIN |
e8557d1f | 84 | select IRQ_FORCED_THREADING |
fea2acaa | 85 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
86 | select NO_BOOTMEM |
87 | select OF | |
88 | select OF_EARLY_FLATTREE | |
9bf14b7c | 89 | select OF_RESERVED_MEM |
8c2c3df3 | 90 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
91 | select POWER_RESET |
92 | select POWER_SUPPLY | |
8c2c3df3 CM |
93 | select RTC_LIB |
94 | select SPARSE_IRQ | |
7ac57a89 | 95 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 96 | select HAVE_CONTEXT_TRACKING |
14457459 | 97 | select HAVE_ARM_SMCCC |
8c2c3df3 CM |
98 | help |
99 | ARM 64-bit (AArch64) Linux support. | |
100 | ||
101 | config 64BIT | |
102 | def_bool y | |
103 | ||
104 | config ARCH_PHYS_ADDR_T_64BIT | |
105 | def_bool y | |
106 | ||
107 | config MMU | |
108 | def_bool y | |
109 | ||
ce816fa8 | 110 | config NO_IOPORT_MAP |
d1e6dc91 | 111 | def_bool y if !PCI |
8c2c3df3 CM |
112 | |
113 | config STACKTRACE_SUPPORT | |
114 | def_bool y | |
115 | ||
bf0c4e04 JVS |
116 | config ILLEGAL_POINTER_VALUE |
117 | hex | |
118 | default 0xdead000000000000 | |
119 | ||
8c2c3df3 CM |
120 | config LOCKDEP_SUPPORT |
121 | def_bool y | |
122 | ||
123 | config TRACE_IRQFLAGS_SUPPORT | |
124 | def_bool y | |
125 | ||
c209f799 | 126 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
127 | def_bool y |
128 | ||
9fb7410f DM |
129 | config GENERIC_BUG |
130 | def_bool y | |
131 | depends on BUG | |
132 | ||
133 | config GENERIC_BUG_RELATIVE_POINTERS | |
134 | def_bool y | |
135 | depends on GENERIC_BUG | |
136 | ||
8c2c3df3 CM |
137 | config GENERIC_HWEIGHT |
138 | def_bool y | |
139 | ||
140 | config GENERIC_CSUM | |
141 | def_bool y | |
142 | ||
143 | config GENERIC_CALIBRATE_DELAY | |
144 | def_bool y | |
145 | ||
19e7640d | 146 | config ZONE_DMA |
8c2c3df3 CM |
147 | def_bool y |
148 | ||
29e56940 SC |
149 | config HAVE_GENERIC_RCU_GUP |
150 | def_bool y | |
151 | ||
8c2c3df3 CM |
152 | config ARCH_DMA_ADDR_T_64BIT |
153 | def_bool y | |
154 | ||
155 | config NEED_DMA_MAP_STATE | |
156 | def_bool y | |
157 | ||
158 | config NEED_SG_DMA_LENGTH | |
159 | def_bool y | |
160 | ||
4b3dc967 WD |
161 | config SMP |
162 | def_bool y | |
163 | ||
8c2c3df3 CM |
164 | config SWIOTLB |
165 | def_bool y | |
166 | ||
167 | config IOMMU_HELPER | |
168 | def_bool SWIOTLB | |
169 | ||
4cfb3613 AB |
170 | config KERNEL_MODE_NEON |
171 | def_bool y | |
172 | ||
92cc15fc RH |
173 | config FIX_EARLYCON_MEM |
174 | def_bool y | |
175 | ||
9f25e6ad KS |
176 | config PGTABLE_LEVELS |
177 | int | |
21539939 | 178 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
179 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
180 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
181 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
182 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
183 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 184 | |
8c2c3df3 CM |
185 | source "init/Kconfig" |
186 | ||
187 | source "kernel/Kconfig.freezer" | |
188 | ||
6a377491 | 189 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
190 | |
191 | menu "Bus support" | |
192 | ||
d1e6dc91 LD |
193 | config PCI |
194 | bool "PCI support" | |
195 | help | |
196 | This feature enables support for PCI bus system. If you say Y | |
197 | here, the kernel will include drivers and infrastructure code | |
198 | to support PCI bus devices. | |
199 | ||
200 | config PCI_DOMAINS | |
201 | def_bool PCI | |
202 | ||
203 | config PCI_DOMAINS_GENERIC | |
204 | def_bool PCI | |
205 | ||
206 | config PCI_SYSCALL | |
207 | def_bool PCI | |
208 | ||
209 | source "drivers/pci/Kconfig" | |
210 | source "drivers/pci/pcie/Kconfig" | |
211 | source "drivers/pci/hotplug/Kconfig" | |
212 | ||
8c2c3df3 CM |
213 | endmenu |
214 | ||
215 | menu "Kernel Features" | |
216 | ||
c0a01b84 AP |
217 | menu "ARM errata workarounds via the alternatives framework" |
218 | ||
219 | config ARM64_ERRATUM_826319 | |
220 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
221 | default y | |
222 | help | |
223 | This option adds an alternative code sequence to work around ARM | |
224 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
225 | AXI master interface and an L2 cache. | |
226 | ||
227 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
228 | and is unable to accept a certain write via this interface, it will | |
229 | not progress on read data presented on the read data channel and the | |
230 | system can deadlock. | |
231 | ||
232 | The workaround promotes data cache clean instructions to | |
233 | data cache clean-and-invalidate. | |
234 | Please note that this does not necessarily enable the workaround, | |
235 | as it depends on the alternative framework, which will only patch | |
236 | the kernel if an affected CPU is detected. | |
237 | ||
238 | If unsure, say Y. | |
239 | ||
240 | config ARM64_ERRATUM_827319 | |
241 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
242 | default y | |
243 | help | |
244 | This option adds an alternative code sequence to work around ARM | |
245 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
246 | master interface and an L2 cache. | |
247 | ||
248 | Under certain conditions this erratum can cause a clean line eviction | |
249 | to occur at the same time as another transaction to the same address | |
250 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
251 | interconnect reorders the two transactions. | |
252 | ||
253 | The workaround promotes data cache clean instructions to | |
254 | data cache clean-and-invalidate. | |
255 | Please note that this does not necessarily enable the workaround, | |
256 | as it depends on the alternative framework, which will only patch | |
257 | the kernel if an affected CPU is detected. | |
258 | ||
259 | If unsure, say Y. | |
260 | ||
261 | config ARM64_ERRATUM_824069 | |
262 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
263 | default y | |
264 | help | |
265 | This option adds an alternative code sequence to work around ARM | |
266 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
267 | to a coherent interconnect. | |
268 | ||
269 | If a Cortex-A53 processor is executing a store or prefetch for | |
270 | write instruction at the same time as a processor in another | |
271 | cluster is executing a cache maintenance operation to the same | |
272 | address, then this erratum might cause a clean cache line to be | |
273 | incorrectly marked as dirty. | |
274 | ||
275 | The workaround promotes data cache clean instructions to | |
276 | data cache clean-and-invalidate. | |
277 | Please note that this option does not necessarily enable the | |
278 | workaround, as it depends on the alternative framework, which will | |
279 | only patch the kernel if an affected CPU is detected. | |
280 | ||
281 | If unsure, say Y. | |
282 | ||
283 | config ARM64_ERRATUM_819472 | |
284 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
285 | default y | |
286 | help | |
287 | This option adds an alternative code sequence to work around ARM | |
288 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
289 | present when it is connected to a coherent interconnect. | |
290 | ||
291 | If the processor is executing a load and store exclusive sequence at | |
292 | the same time as a processor in another cluster is executing a cache | |
293 | maintenance operation to the same address, then this erratum might | |
294 | cause data corruption. | |
295 | ||
296 | The workaround promotes data cache clean instructions to | |
297 | data cache clean-and-invalidate. | |
298 | Please note that this does not necessarily enable the workaround, | |
299 | as it depends on the alternative framework, which will only patch | |
300 | the kernel if an affected CPU is detected. | |
301 | ||
302 | If unsure, say Y. | |
303 | ||
304 | config ARM64_ERRATUM_832075 | |
305 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
306 | default y | |
307 | help | |
308 | This option adds an alternative code sequence to work around ARM | |
309 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
310 | ||
311 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
312 | instructions to Write-Back memory are mixed with Device loads. | |
313 | ||
314 | The workaround is to promote device loads to use Load-Acquire | |
315 | semantics. | |
316 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
317 | as it depends on the alternative framework, which will only patch |
318 | the kernel if an affected CPU is detected. | |
319 | ||
320 | If unsure, say Y. | |
321 | ||
322 | config ARM64_ERRATUM_834220 | |
323 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
324 | depends on KVM | |
325 | default y | |
326 | help | |
327 | This option adds an alternative code sequence to work around ARM | |
328 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
329 | ||
330 | Affected Cortex-A57 parts might report a Stage 2 translation | |
331 | fault as the result of a Stage 1 fault for load crossing a | |
332 | page boundary when there is a permission or device memory | |
333 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
334 | ||
335 | The workaround is to verify that the Stage 1 translation | |
336 | doesn't generate a fault before handling the Stage 2 fault. | |
337 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
338 | as it depends on the alternative framework, which will only patch |
339 | the kernel if an affected CPU is detected. | |
340 | ||
341 | If unsure, say Y. | |
342 | ||
905e8c5d WD |
343 | config ARM64_ERRATUM_845719 |
344 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
345 | depends on COMPAT | |
346 | default y | |
347 | help | |
348 | This option adds an alternative code sequence to work around ARM | |
349 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
350 | ||
351 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
352 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
353 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
354 | might return incorrect data. | |
355 | ||
356 | The workaround is to write the contextidr_el1 register on exception | |
357 | return to a 32-bit task. | |
358 | Please note that this does not necessarily enable the workaround, | |
359 | as it depends on the alternative framework, which will only patch | |
360 | the kernel if an affected CPU is detected. | |
361 | ||
362 | If unsure, say Y. | |
363 | ||
df057cc7 WD |
364 | config ARM64_ERRATUM_843419 |
365 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
366 | depends on MODULES | |
367 | default y | |
368 | help | |
369 | This option builds kernel modules using the large memory model in | |
370 | order to avoid the use of the ADRP instruction, which can cause | |
371 | a subsequent memory access to use an incorrect address on Cortex-A53 | |
372 | parts up to r0p4. | |
373 | ||
374 | Note that the kernel itself must be linked with a version of ld | |
375 | which fixes potentially affected ADRP instructions through the | |
376 | use of veneers. | |
377 | ||
378 | If unsure, say Y. | |
379 | ||
94100970 RR |
380 | config CAVIUM_ERRATUM_22375 |
381 | bool "Cavium erratum 22375, 24313" | |
382 | default y | |
383 | help | |
384 | Enable workaround for erratum 22375, 24313. | |
385 | ||
386 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
387 | with small impact affecting only ITS table allocation. | |
388 | ||
389 | erratum 22375: only alloc 8MB table size | |
390 | erratum 24313: ignore memory access type | |
391 | ||
392 | The fixes are in ITS initialization and basically ignore memory access | |
393 | type and table size provided by the TYPER and BASER registers. | |
394 | ||
395 | If unsure, say Y. | |
396 | ||
6d4e11c5 RR |
397 | config CAVIUM_ERRATUM_23154 |
398 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
399 | default y | |
400 | help | |
401 | The gicv3 of ThunderX requires a modified version for | |
402 | reading the IAR status to ensure data synchronization | |
403 | (access to icc_iar1_el1 is not sync'ed before and after). | |
404 | ||
405 | If unsure, say Y. | |
406 | ||
c0a01b84 AP |
407 | endmenu |
408 | ||
409 | ||
e41ceed0 JL |
410 | choice |
411 | prompt "Page size" | |
412 | default ARM64_4K_PAGES | |
413 | help | |
414 | Page size (translation granule) configuration. | |
415 | ||
416 | config ARM64_4K_PAGES | |
417 | bool "4KB" | |
418 | help | |
419 | This feature enables 4KB pages support. | |
420 | ||
44eaacf1 SP |
421 | config ARM64_16K_PAGES |
422 | bool "16KB" | |
423 | help | |
424 | The system will use 16KB pages support. AArch32 emulation | |
425 | requires applications compiled with 16K (or a multiple of 16K) | |
426 | aligned segments. | |
427 | ||
8c2c3df3 | 428 | config ARM64_64K_PAGES |
e41ceed0 | 429 | bool "64KB" |
8c2c3df3 CM |
430 | help |
431 | This feature enables 64KB pages support (4KB by default) | |
432 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
433 | look-up. AArch32 emulation requires applications compiled |
434 | with 64K aligned segments. | |
8c2c3df3 | 435 | |
e41ceed0 JL |
436 | endchoice |
437 | ||
438 | choice | |
439 | prompt "Virtual address space size" | |
440 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 441 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
442 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
443 | help | |
444 | Allows choosing one of multiple possible virtual address | |
445 | space sizes. The level of translation table is determined by | |
446 | a combination of page size and virtual address space size. | |
447 | ||
21539939 | 448 | config ARM64_VA_BITS_36 |
56a3f30e | 449 | bool "36-bit" if EXPERT |
21539939 SP |
450 | depends on ARM64_16K_PAGES |
451 | ||
e41ceed0 JL |
452 | config ARM64_VA_BITS_39 |
453 | bool "39-bit" | |
454 | depends on ARM64_4K_PAGES | |
455 | ||
456 | config ARM64_VA_BITS_42 | |
457 | bool "42-bit" | |
458 | depends on ARM64_64K_PAGES | |
459 | ||
44eaacf1 SP |
460 | config ARM64_VA_BITS_47 |
461 | bool "47-bit" | |
462 | depends on ARM64_16K_PAGES | |
463 | ||
c79b954b JL |
464 | config ARM64_VA_BITS_48 |
465 | bool "48-bit" | |
c79b954b | 466 | |
e41ceed0 JL |
467 | endchoice |
468 | ||
469 | config ARM64_VA_BITS | |
470 | int | |
21539939 | 471 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
472 | default 39 if ARM64_VA_BITS_39 |
473 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 474 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 475 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 476 | |
a872013d WD |
477 | config CPU_BIG_ENDIAN |
478 | bool "Build big-endian kernel" | |
479 | help | |
480 | Say Y if you plan on running a kernel in big-endian mode. | |
481 | ||
f6e763b9 MB |
482 | config SCHED_MC |
483 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
484 | help |
485 | Multi-core scheduler support improves the CPU scheduler's decision | |
486 | making when dealing with multi-core CPU chips at a cost of slightly | |
487 | increased overhead in some places. If unsure say N here. | |
488 | ||
489 | config SCHED_SMT | |
490 | bool "SMT scheduler support" | |
f6e763b9 MB |
491 | help |
492 | Improves the CPU scheduler's decision making when dealing with | |
493 | MultiThreading at a cost of slightly increased overhead in some | |
494 | places. If unsure say N here. | |
495 | ||
8c2c3df3 | 496 | config NR_CPUS |
62aa9655 GK |
497 | int "Maximum number of CPUs (2-4096)" |
498 | range 2 4096 | |
15942853 | 499 | # These have to remain sorted largest to smallest |
e3672649 | 500 | default "64" |
8c2c3df3 | 501 | |
9327e2c6 MR |
502 | config HOTPLUG_CPU |
503 | bool "Support for hot-pluggable CPUs" | |
217d453d | 504 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
505 | help |
506 | Say Y here to experiment with turning CPUs off and on. CPUs | |
507 | can be controlled through /sys/devices/system/cpu. | |
508 | ||
8c2c3df3 | 509 | source kernel/Kconfig.preempt |
f90df5e2 | 510 | source kernel/Kconfig.hz |
8c2c3df3 CM |
511 | |
512 | config ARCH_HAS_HOLES_MEMORYMODEL | |
513 | def_bool y if SPARSEMEM | |
514 | ||
515 | config ARCH_SPARSEMEM_ENABLE | |
516 | def_bool y | |
517 | select SPARSEMEM_VMEMMAP_ENABLE | |
518 | ||
519 | config ARCH_SPARSEMEM_DEFAULT | |
520 | def_bool ARCH_SPARSEMEM_ENABLE | |
521 | ||
522 | config ARCH_SELECT_MEMORY_MODEL | |
523 | def_bool ARCH_SPARSEMEM_ENABLE | |
524 | ||
525 | config HAVE_ARCH_PFN_VALID | |
526 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
527 | ||
528 | config HW_PERF_EVENTS | |
6475b2d8 MR |
529 | def_bool y |
530 | depends on ARM_PMU | |
8c2c3df3 | 531 | |
084bd298 SC |
532 | config SYS_SUPPORTS_HUGETLBFS |
533 | def_bool y | |
534 | ||
084bd298 | 535 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 536 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 537 | |
af074848 SC |
538 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
539 | def_bool y | |
540 | ||
a41dc0e8 CM |
541 | config ARCH_HAS_CACHE_LINE_SIZE |
542 | def_bool y | |
543 | ||
8c2c3df3 CM |
544 | source "mm/Kconfig" |
545 | ||
a1ae65b2 AT |
546 | config SECCOMP |
547 | bool "Enable seccomp to safely compute untrusted bytecode" | |
548 | ---help--- | |
549 | This kernel feature is useful for number crunching applications | |
550 | that may need to compute untrusted bytecode during their | |
551 | execution. By using pipes or other transports made available to | |
552 | the process as file descriptors supporting the read/write | |
553 | syscalls, it's possible to isolate those applications in | |
554 | their own address space using seccomp. Once seccomp is | |
555 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
556 | and the task is only allowed to execute a few safe syscalls | |
557 | defined by each seccomp mode. | |
558 | ||
dfd57bc3 SS |
559 | config PARAVIRT |
560 | bool "Enable paravirtualization code" | |
561 | help | |
562 | This changes the kernel so it can modify itself when it is run | |
563 | under a hypervisor, potentially improving performance significantly | |
564 | over full virtualization. | |
565 | ||
566 | config PARAVIRT_TIME_ACCOUNTING | |
567 | bool "Paravirtual steal time accounting" | |
568 | select PARAVIRT | |
569 | default n | |
570 | help | |
571 | Select this option to enable fine granularity task steal time | |
572 | accounting. Time spent executing other tasks in parallel with | |
573 | the current vCPU is discounted from the vCPU power. To account for | |
574 | that, there can be a small performance impact. | |
575 | ||
576 | If in doubt, say N here. | |
577 | ||
aa42aa13 SS |
578 | config XEN_DOM0 |
579 | def_bool y | |
580 | depends on XEN | |
581 | ||
582 | config XEN | |
c2ba1f7d | 583 | bool "Xen guest support on ARM64" |
aa42aa13 | 584 | depends on ARM64 && OF |
83862ccf | 585 | select SWIOTLB_XEN |
dfd57bc3 | 586 | select PARAVIRT |
aa42aa13 SS |
587 | help |
588 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
589 | ||
d03bb145 SC |
590 | config FORCE_MAX_ZONEORDER |
591 | int | |
592 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 593 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 594 | default "11" |
44eaacf1 SP |
595 | help |
596 | The kernel memory allocator divides physically contiguous memory | |
597 | blocks into "zones", where each zone is a power of two number of | |
598 | pages. This option selects the largest power of two that the kernel | |
599 | keeps in the memory allocator. If you need to allocate very large | |
600 | blocks of physically contiguous memory, then you may need to | |
601 | increase this value. | |
602 | ||
603 | This config option is actually maximum order plus one. For example, | |
604 | a value of 11 means that the largest free memory block is 2^10 pages. | |
605 | ||
606 | We make sure that we can allocate upto a HugePage size for each configuration. | |
607 | Hence we have : | |
608 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
609 | ||
610 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
611 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 612 | |
1b907f46 WD |
613 | menuconfig ARMV8_DEPRECATED |
614 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
615 | depends on COMPAT | |
616 | help | |
617 | Legacy software support may require certain instructions | |
618 | that have been deprecated or obsoleted in the architecture. | |
619 | ||
620 | Enable this config to enable selective emulation of these | |
621 | features. | |
622 | ||
623 | If unsure, say Y | |
624 | ||
625 | if ARMV8_DEPRECATED | |
626 | ||
627 | config SWP_EMULATION | |
628 | bool "Emulate SWP/SWPB instructions" | |
629 | help | |
630 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
631 | they are always undefined. Say Y here to enable software | |
632 | emulation of these instructions for userspace using LDXR/STXR. | |
633 | ||
634 | In some older versions of glibc [<=2.8] SWP is used during futex | |
635 | trylock() operations with the assumption that the code will not | |
636 | be preempted. This invalid assumption may be more likely to fail | |
637 | with SWP emulation enabled, leading to deadlock of the user | |
638 | application. | |
639 | ||
640 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
641 | on an external transaction monitoring block called a global | |
642 | monitor to maintain update atomicity. If your system does not | |
643 | implement a global monitor, this option can cause programs that | |
644 | perform SWP operations to uncached memory to deadlock. | |
645 | ||
646 | If unsure, say Y | |
647 | ||
648 | config CP15_BARRIER_EMULATION | |
649 | bool "Emulate CP15 Barrier instructions" | |
650 | help | |
651 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
652 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
653 | strongly recommended to use the ISB, DSB, and DMB | |
654 | instructions instead. | |
655 | ||
656 | Say Y here to enable software emulation of these | |
657 | instructions for AArch32 userspace code. When this option is | |
658 | enabled, CP15 barrier usage is traced which can help | |
659 | identify software that needs updating. | |
660 | ||
661 | If unsure, say Y | |
662 | ||
2d888f48 SP |
663 | config SETEND_EMULATION |
664 | bool "Emulate SETEND instruction" | |
665 | help | |
666 | The SETEND instruction alters the data-endianness of the | |
667 | AArch32 EL0, and is deprecated in ARMv8. | |
668 | ||
669 | Say Y here to enable software emulation of the instruction | |
670 | for AArch32 userspace code. | |
671 | ||
672 | Note: All the cpus on the system must have mixed endian support at EL0 | |
673 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
674 | endian - is hotplugged in after this feature has been enabled, there could | |
675 | be unexpected results in the applications. | |
676 | ||
677 | If unsure, say Y | |
1b907f46 WD |
678 | endif |
679 | ||
0e4a0709 WD |
680 | menu "ARMv8.1 architectural features" |
681 | ||
682 | config ARM64_HW_AFDBM | |
683 | bool "Support for hardware updates of the Access and Dirty page flags" | |
684 | default y | |
685 | help | |
686 | The ARMv8.1 architecture extensions introduce support for | |
687 | hardware updates of the access and dirty information in page | |
688 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
689 | capable processors, accesses to pages with PTE_AF cleared will | |
690 | set this bit instead of raising an access flag fault. | |
691 | Similarly, writes to read-only pages with the DBM bit set will | |
692 | clear the read-only bit (AP[2]) instead of raising a | |
693 | permission fault. | |
694 | ||
695 | Kernels built with this configuration option enabled continue | |
696 | to work on pre-ARMv8.1 hardware and the performance impact is | |
697 | minimal. If unsure, say Y. | |
698 | ||
699 | config ARM64_PAN | |
700 | bool "Enable support for Privileged Access Never (PAN)" | |
701 | default y | |
702 | help | |
703 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
704 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
705 | memory directly. | |
706 | ||
707 | Choosing this option will cause any unprotected (not using | |
708 | copy_to_user et al) memory access to fail with a permission fault. | |
709 | ||
710 | The feature is detected at runtime, and will remain as a 'nop' | |
711 | instruction if the cpu does not implement the feature. | |
712 | ||
713 | config ARM64_LSE_ATOMICS | |
714 | bool "Atomic instructions" | |
715 | help | |
716 | As part of the Large System Extensions, ARMv8.1 introduces new | |
717 | atomic instructions that are designed specifically to scale in | |
718 | very large systems. | |
719 | ||
720 | Say Y here to make use of these instructions for the in-kernel | |
721 | atomic routines. This incurs a small overhead on CPUs that do | |
722 | not support these instructions and requires the kernel to be | |
723 | built with binutils >= 2.25. | |
724 | ||
725 | endmenu | |
726 | ||
8c2c3df3 CM |
727 | endmenu |
728 | ||
729 | menu "Boot options" | |
730 | ||
731 | config CMDLINE | |
732 | string "Default kernel command string" | |
733 | default "" | |
734 | help | |
735 | Provide a set of default command-line options at build time by | |
736 | entering them here. As a minimum, you should specify the the | |
737 | root device (e.g. root=/dev/nfs). | |
738 | ||
739 | config CMDLINE_FORCE | |
740 | bool "Always use the default kernel command string" | |
741 | help | |
742 | Always use the default kernel command string, even if the boot | |
743 | loader passes other arguments to the kernel. | |
744 | This is useful if you cannot or don't want to change the | |
745 | command-line options your boot loader passes to the kernel. | |
746 | ||
f4f75ad5 AB |
747 | config EFI_STUB |
748 | bool | |
749 | ||
f84d0275 MS |
750 | config EFI |
751 | bool "UEFI runtime support" | |
752 | depends on OF && !CPU_BIG_ENDIAN | |
753 | select LIBFDT | |
754 | select UCS2_STRING | |
755 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 756 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
757 | select EFI_STUB |
758 | select EFI_ARMSTUB | |
f84d0275 MS |
759 | default y |
760 | help | |
761 | This option provides support for runtime services provided | |
762 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
763 | clock, and platform reset). A UEFI stub is also provided to |
764 | allow the kernel to be booted as an EFI application. This | |
765 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 766 | |
d1ae8c00 YL |
767 | config DMI |
768 | bool "Enable support for SMBIOS (DMI) tables" | |
769 | depends on EFI | |
770 | default y | |
771 | help | |
772 | This enables SMBIOS/DMI feature for systems. | |
773 | ||
774 | This option is only useful on systems that have UEFI firmware. | |
775 | However, even with this option, the resultant kernel should | |
776 | continue to boot on existing non-UEFI platforms. | |
777 | ||
8c2c3df3 CM |
778 | endmenu |
779 | ||
780 | menu "Userspace binary formats" | |
781 | ||
782 | source "fs/Kconfig.binfmt" | |
783 | ||
784 | config COMPAT | |
785 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 786 | depends on ARM64_4K_PAGES || EXPERT |
8c2c3df3 | 787 | select COMPAT_BINFMT_ELF |
af1839eb | 788 | select HAVE_UID16 |
84b9e9b4 | 789 | select OLD_SIGSUSPEND3 |
51682036 | 790 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
791 | help |
792 | This option enables support for a 32-bit EL0 running under a 64-bit | |
793 | kernel at EL1. AArch32-specific components such as system calls, | |
794 | the user helper functions, VFP support and the ptrace interface are | |
795 | handled appropriately by the kernel. | |
796 | ||
44eaacf1 SP |
797 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
798 | that you will only be able to execute AArch32 binaries that were compiled | |
799 | with page size aligned segments. | |
a8fcd8b1 | 800 | |
8c2c3df3 CM |
801 | If you want to execute 32-bit userspace applications, say Y. |
802 | ||
803 | config SYSVIPC_COMPAT | |
804 | def_bool y | |
805 | depends on COMPAT && SYSVIPC | |
806 | ||
807 | endmenu | |
808 | ||
166936ba LP |
809 | menu "Power management options" |
810 | ||
811 | source "kernel/power/Kconfig" | |
812 | ||
813 | config ARCH_SUSPEND_POSSIBLE | |
814 | def_bool y | |
815 | ||
166936ba LP |
816 | endmenu |
817 | ||
1307220d LP |
818 | menu "CPU Power Management" |
819 | ||
820 | source "drivers/cpuidle/Kconfig" | |
821 | ||
52e7e816 RH |
822 | source "drivers/cpufreq/Kconfig" |
823 | ||
824 | endmenu | |
825 | ||
8c2c3df3 CM |
826 | source "net/Kconfig" |
827 | ||
828 | source "drivers/Kconfig" | |
829 | ||
f84d0275 MS |
830 | source "drivers/firmware/Kconfig" |
831 | ||
b6a02173 GG |
832 | source "drivers/acpi/Kconfig" |
833 | ||
8c2c3df3 CM |
834 | source "fs/Kconfig" |
835 | ||
c3eb5b14 MZ |
836 | source "arch/arm64/kvm/Kconfig" |
837 | ||
8c2c3df3 CM |
838 | source "arch/arm64/Kconfig.debug" |
839 | ||
840 | source "security/Kconfig" | |
841 | ||
842 | source "crypto/Kconfig" | |
2c98833a AB |
843 | if CRYPTO |
844 | source "arch/arm64/crypto/Kconfig" | |
845 | endif | |
8c2c3df3 CM |
846 | |
847 | source "lib/Kconfig" |