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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
8aa34ab8 | 18 | |
0ebc4cda BH |
19 | /* |
20 | * We layout physical memory as follows: | |
21 | * 0x0000 - 0x00ff : Secondary processor spin code | |
c1fb6816 MN |
22 | * 0x0100 - 0x17ff : pSeries Interrupt prologs |
23 | * 0x1800 - 0x4000 : interrupt support common interrupt prologs | |
24 | * 0x4000 - 0x5fff : pSeries interrupts with IR=1,DR=1 | |
25 | * 0x6000 - 0x6fff : more interrupt support including for IR=1,DR=1 | |
0ebc4cda | 26 | * 0x7000 - 0x7fff : FWNMI data area |
c1fb6816 MN |
27 | * 0x8000 - 0x8fff : Initial (CPU0) segment table |
28 | * 0x9000 - : Early init and support code | |
0ebc4cda | 29 | */ |
742415d6 MN |
30 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
31 | #define SYSCALL_PSERIES_1 \ | |
32 | BEGIN_FTR_SECTION \ | |
33 | cmpdi r0,0x1ebe ; \ | |
34 | beq- 1f ; \ | |
35 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
36 | mr r9,r13 ; \ | |
37 | GET_PACA(r13) ; \ | |
38 | mfspr r11,SPRN_SRR0 ; \ | |
39 | 0: | |
40 | ||
41 | #define SYSCALL_PSERIES_2_RFID \ | |
42 | mfspr r12,SPRN_SRR1 ; \ | |
43 | ld r10,PACAKBASE(r13) ; \ | |
44 | LOAD_HANDLER(r10, system_call_entry) ; \ | |
45 | mtspr SPRN_SRR0,r10 ; \ | |
46 | ld r10,PACAKMSR(r13) ; \ | |
47 | mtspr SPRN_SRR1,r10 ; \ | |
48 | rfid ; \ | |
49 | b . ; /* prevent speculative execution */ | |
50 | ||
51 | #define SYSCALL_PSERIES_3 \ | |
52 | /* Fast LE/BE switch system call */ \ | |
53 | 1: mfspr r12,SPRN_SRR1 ; \ | |
54 | xori r12,r12,MSR_LE ; \ | |
55 | mtspr SPRN_SRR1,r12 ; \ | |
56 | rfid ; /* return to userspace */ \ | |
57 | b . ; \ | |
58 | 2: mfspr r12,SPRN_SRR1 ; \ | |
59 | andi. r12,r12,MSR_PR ; \ | |
60 | bne 0b ; \ | |
61 | mtspr SPRN_SRR0,r3 ; \ | |
62 | mtspr SPRN_SRR1,r4 ; \ | |
63 | mtspr SPRN_SDR1,r5 ; \ | |
64 | rfid ; \ | |
65 | b . ; /* prevent speculative execution */ | |
66 | ||
4700dfaf MN |
67 | #if defined(CONFIG_RELOCATABLE) |
68 | /* | |
69 | * We can't branch directly; in the direct case we use LR | |
70 | * and system_call_entry restores LR. (We thus need to move | |
71 | * LR to r10 in the RFID case too.) | |
72 | */ | |
73 | #define SYSCALL_PSERIES_2_DIRECT \ | |
74 | mflr r10 ; \ | |
75 | ld r12,PACAKBASE(r13) ; \ | |
76 | LOAD_HANDLER(r12, system_call_entry_direct) ; \ | |
77 | mtlr r12 ; \ | |
78 | mfspr r12,SPRN_SRR1 ; \ | |
79 | /* Re-use of r13... No spare regs to do this */ \ | |
80 | li r13,MSR_RI ; \ | |
81 | mtmsrd r13,1 ; \ | |
82 | GET_PACA(r13) ; /* get r13 back */ \ | |
83 | blr ; | |
84 | #else | |
85 | /* We can branch directly */ | |
86 | #define SYSCALL_PSERIES_2_DIRECT \ | |
87 | mfspr r12,SPRN_SRR1 ; \ | |
88 | li r10,MSR_RI ; \ | |
89 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
90 | b system_call_entry_direct ; | |
91 | #endif | |
0ebc4cda | 92 | |
0ebc4cda BH |
93 | /* |
94 | * This is the start of the interrupt handlers for pSeries | |
95 | * This code runs with relocation off. | |
96 | * Code from here to __end_interrupts gets copied down to real | |
97 | * address 0x100 when we are running a relocatable kernel. | |
98 | * Therefore any relative branches in this section must only | |
99 | * branch to labels in this section. | |
100 | */ | |
101 | . = 0x100 | |
102 | .globl __start_interrupts | |
103 | __start_interrupts: | |
104 | ||
948cf67c BH |
105 | .globl system_reset_pSeries; |
106 | system_reset_pSeries: | |
44e9309f | 107 | HMT_MEDIUM_PPR_DISCARD |
948cf67c BH |
108 | SET_SCRATCH0(r13) |
109 | #ifdef CONFIG_PPC_P7_NAP | |
110 | BEGIN_FTR_SECTION | |
111 | /* Running native on arch 2.06 or later, check if we are | |
112 | * waking up from nap. We only handle no state loss and | |
113 | * supervisor state loss. We do -not- handle hypervisor | |
114 | * state loss at this time. | |
115 | */ | |
116 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
117 | rlwinm. r13,r13,47-31,30,31 |
118 | beq 9f | |
119 | ||
120 | /* waking up from powersave (nap) state */ | |
121 | cmpwi cr1,r13,2 | |
948cf67c BH |
122 | /* Total loss of HV state is fatal, we could try to use the |
123 | * PIR to locate a PACA, then use an emergency stack etc... | |
124 | * but for now, let's just stay stuck here | |
125 | */ | |
371fefd6 PM |
126 | bgt cr1,. |
127 | GET_PACA(r13) | |
128 | ||
129 | #ifdef CONFIG_KVM_BOOK3S_64_HV | |
f0888f70 PM |
130 | li r0,KVM_HWTHREAD_IN_KERNEL |
131 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
132 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
133 | sync | |
134 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
135 | cmpwi r0,0 | |
136 | beq 1f | |
371fefd6 PM |
137 | b kvm_start_guest |
138 | 1: | |
139 | #endif | |
140 | ||
141 | beq cr1,2f | |
142 | b .power7_wakeup_noloss | |
143 | 2: b .power7_wakeup_loss | |
144 | 9: | |
969391c5 | 145 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 146 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
147 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
148 | NOTEST, 0x100) | |
0ebc4cda BH |
149 | |
150 | . = 0x200 | |
b01c8b54 PM |
151 | machine_check_pSeries_1: |
152 | /* This is moved out of line as it can be patched by FW, but | |
153 | * some code path might still want to branch into the original | |
154 | * vector | |
155 | */ | |
1707dd16 PM |
156 | HMT_MEDIUM_PPR_DISCARD |
157 | SET_SCRATCH0(r13) /* save r13 */ | |
158 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
159 | b machine_check_pSeries_0 | |
0ebc4cda BH |
160 | |
161 | . = 0x300 | |
162 | .globl data_access_pSeries | |
163 | data_access_pSeries: | |
44e9309f | 164 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 165 | SET_SCRATCH0(r13) |
0ebc4cda | 166 | BEGIN_FTR_SECTION |
b01c8b54 PM |
167 | b data_access_check_stab |
168 | data_access_not_stab: | |
169 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB) | |
b01c8b54 | 170 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD, |
697d3899 | 171 | KVMTEST, 0x300) |
0ebc4cda BH |
172 | |
173 | . = 0x380 | |
174 | .globl data_access_slb_pSeries | |
175 | data_access_slb_pSeries: | |
44e9309f | 176 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 177 | SET_SCRATCH0(r13) |
1707dd16 | 178 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
697d3899 | 179 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST, 0x380) |
0ebc4cda BH |
180 | std r3,PACA_EXSLB+EX_R3(r13) |
181 | mfspr r3,SPRN_DAR | |
0ebc4cda BH |
182 | #ifdef __DISABLED__ |
183 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
184 | cmpdi r3,0 | |
185 | bge slb_miss_user_pseries | |
186 | #endif /* __DISABLED__ */ | |
b01c8b54 | 187 | mfspr r12,SPRN_SRR1 |
0ebc4cda BH |
188 | #ifndef CONFIG_RELOCATABLE |
189 | b .slb_miss_realmode | |
190 | #else | |
191 | /* | |
192 | * We can't just use a direct branch to .slb_miss_realmode | |
193 | * because the distance from here to there depends on where | |
194 | * the kernel ends up being put. | |
195 | */ | |
196 | mfctr r11 | |
197 | ld r10,PACAKBASE(r13) | |
198 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
199 | mtctr r10 | |
200 | bctr | |
201 | #endif | |
202 | ||
b3e6b5df | 203 | STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access) |
0ebc4cda BH |
204 | |
205 | . = 0x480 | |
206 | .globl instruction_access_slb_pSeries | |
207 | instruction_access_slb_pSeries: | |
44e9309f | 208 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 209 | SET_SCRATCH0(r13) |
1707dd16 | 210 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
de56a948 | 211 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
212 | std r3,PACA_EXSLB+EX_R3(r13) |
213 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
0ebc4cda BH |
214 | #ifdef __DISABLED__ |
215 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
216 | cmpdi r3,0 | |
217 | bge slb_miss_user_pseries | |
218 | #endif /* __DISABLED__ */ | |
b01c8b54 | 219 | mfspr r12,SPRN_SRR1 |
0ebc4cda BH |
220 | #ifndef CONFIG_RELOCATABLE |
221 | b .slb_miss_realmode | |
222 | #else | |
223 | mfctr r11 | |
224 | ld r10,PACAKBASE(r13) | |
225 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
226 | mtctr r10 | |
227 | bctr | |
228 | #endif | |
229 | ||
b3e6b5df BH |
230 | /* We open code these as we can't have a ". = x" (even with |
231 | * x = "." within a feature section | |
232 | */ | |
a5d4f3ad | 233 | . = 0x500; |
b3e6b5df BH |
234 | .globl hardware_interrupt_pSeries; |
235 | .globl hardware_interrupt_hv; | |
a5d4f3ad | 236 | hardware_interrupt_pSeries: |
b3e6b5df | 237 | hardware_interrupt_hv: |
a5d4f3ad | 238 | BEGIN_FTR_SECTION |
b01c8b54 PM |
239 | _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, |
240 | EXC_HV, SOFTEN_TEST_HV) | |
241 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) | |
de56a948 PM |
242 | FTR_SECTION_ELSE |
243 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, | |
9e368f29 | 244 | EXC_STD, SOFTEN_TEST_HV_201) |
de56a948 | 245 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 246 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
a5d4f3ad | 247 | |
b3e6b5df | 248 | STD_EXCEPTION_PSERIES(0x600, 0x600, alignment) |
de56a948 | 249 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600) |
b01c8b54 | 250 | |
b3e6b5df | 251 | STD_EXCEPTION_PSERIES(0x700, 0x700, program_check) |
de56a948 | 252 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x700) |
b01c8b54 | 253 | |
b3e6b5df | 254 | STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable) |
de56a948 | 255 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800) |
a5d4f3ad | 256 | |
b3e6b5df | 257 | MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer) |
dabe859e | 258 | STD_EXCEPTION_HV(0x980, 0x982, hdecrementer) |
a5d4f3ad | 259 | |
1dbdafec | 260 | MASKABLE_EXCEPTION_PSERIES(0xa00, 0xa00, doorbell_super) |
de56a948 | 261 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xa00) |
b01c8b54 | 262 | |
b3e6b5df | 263 | STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b) |
de56a948 | 264 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xb00) |
0ebc4cda BH |
265 | |
266 | . = 0xc00 | |
267 | .globl system_call_pSeries | |
268 | system_call_pSeries: | |
269 | HMT_MEDIUM | |
b01c8b54 PM |
270 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
271 | SET_SCRATCH0(r13) | |
272 | GET_PACA(r13) | |
273 | std r9,PACA_EXGEN+EX_R9(r13) | |
274 | std r10,PACA_EXGEN+EX_R10(r13) | |
275 | mfcr r9 | |
276 | KVMTEST(0xc00) | |
277 | GET_SCRATCH0(r13) | |
278 | #endif | |
742415d6 MN |
279 | SYSCALL_PSERIES_1 |
280 | SYSCALL_PSERIES_2_RFID | |
281 | SYSCALL_PSERIES_3 | |
b01c8b54 PM |
282 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
283 | ||
b3e6b5df | 284 | STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step) |
de56a948 | 285 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00) |
b3e6b5df BH |
286 | |
287 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
288 | * out of line to handle them | |
289 | */ | |
290 | . = 0xe00 | |
e6a74c6e | 291 | hv_exception_trampoline: |
1707dd16 PM |
292 | SET_SCRATCH0(r13) |
293 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 294 | b h_data_storage_hv |
1707dd16 | 295 | |
b3e6b5df | 296 | . = 0xe20 |
1707dd16 PM |
297 | SET_SCRATCH0(r13) |
298 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 299 | b h_instr_storage_hv |
1707dd16 | 300 | |
b3e6b5df | 301 | . = 0xe40 |
1707dd16 PM |
302 | SET_SCRATCH0(r13) |
303 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 304 | b emulation_assist_hv |
1707dd16 | 305 | |
b3e6b5df | 306 | . = 0xe60 |
1707dd16 PM |
307 | SET_SCRATCH0(r13) |
308 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
b3e6b5df | 309 | b hmi_exception_hv |
1707dd16 | 310 | |
655bb3f4 | 311 | . = 0xe80 |
1707dd16 PM |
312 | SET_SCRATCH0(r13) |
313 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
655bb3f4 | 314 | b h_doorbell_hv |
0ebc4cda BH |
315 | |
316 | /* We need to deal with the Altivec unavailable exception | |
317 | * here which is at 0xf20, thus in the middle of the | |
318 | * prolog code of the PerformanceMonitor one. A little | |
319 | * trickery is thus necessary | |
320 | */ | |
c86e2ead | 321 | performance_monitor_pSeries_1: |
0ebc4cda | 322 | . = 0xf00 |
1707dd16 PM |
323 | SET_SCRATCH0(r13) |
324 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
325 | b performance_monitor_pSeries |
326 | ||
c86e2ead | 327 | altivec_unavailable_pSeries_1: |
0ebc4cda | 328 | . = 0xf20 |
1707dd16 PM |
329 | SET_SCRATCH0(r13) |
330 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
331 | b altivec_unavailable_pSeries |
332 | ||
c86e2ead | 333 | vsx_unavailable_pSeries_1: |
0ebc4cda | 334 | . = 0xf40 |
1707dd16 PM |
335 | SET_SCRATCH0(r13) |
336 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
0ebc4cda BH |
337 | b vsx_unavailable_pSeries |
338 | ||
339 | #ifdef CONFIG_CBE_RAS | |
b3e6b5df | 340 | STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error) |
5ccf55dd | 341 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1202) |
0ebc4cda | 342 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 343 | |
b3e6b5df | 344 | STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint) |
de56a948 | 345 | KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300) |
b01c8b54 | 346 | |
b92a66a6 | 347 | . = 0x1500 |
51cf2b30 | 348 | .global denorm_exception_hv |
b92a66a6 | 349 | denorm_exception_hv: |
44e9309f | 350 | HMT_MEDIUM_PPR_DISCARD |
b92a66a6 | 351 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 352 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
b92a66a6 MN |
353 | std r11,PACA_EXGEN+EX_R11(r13) |
354 | std r12,PACA_EXGEN+EX_R12(r13) | |
355 | mfspr r9,SPRN_SPRG_HSCRATCH0 | |
356 | std r9,PACA_EXGEN+EX_R13(r13) | |
357 | mfcr r9 | |
358 | ||
359 | #ifdef CONFIG_PPC_DENORMALISATION | |
360 | mfspr r10,SPRN_HSRR1 | |
361 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
362 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ | |
363 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
364 | bne+ denorm_assist | |
365 | #endif | |
366 | ||
367 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
368 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500) | |
369 | ||
0ebc4cda | 370 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 371 | STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance) |
5ccf55dd | 372 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1602) |
0ebc4cda | 373 | #endif /* CONFIG_CBE_RAS */ |
b01c8b54 | 374 | |
b3e6b5df | 375 | STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist) |
de56a948 | 376 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x1700) |
b01c8b54 | 377 | |
0ebc4cda | 378 | #ifdef CONFIG_CBE_RAS |
b3e6b5df | 379 | STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal) |
5ccf55dd | 380 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802) |
faab4dd2 MN |
381 | #else |
382 | . = 0x1800 | |
0ebc4cda BH |
383 | #endif /* CONFIG_CBE_RAS */ |
384 | ||
0ebc4cda | 385 | |
b3e6b5df BH |
386 | /*** Out of line interrupts support ***/ |
387 | ||
faab4dd2 | 388 | .align 7 |
b01c8b54 PM |
389 | /* moved from 0x200 */ |
390 | machine_check_pSeries: | |
391 | .globl machine_check_fwnmi | |
392 | machine_check_fwnmi: | |
44e9309f | 393 | HMT_MEDIUM_PPR_DISCARD |
b01c8b54 | 394 | SET_SCRATCH0(r13) /* save r13 */ |
1707dd16 PM |
395 | EXCEPTION_PROLOG_0(PACA_EXMC) |
396 | machine_check_pSeries_0: | |
397 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST, 0x200) | |
398 | EXCEPTION_PROLOG_PSERIES_1(machine_check_common, EXC_STD) | |
b01c8b54 PM |
399 | KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200) |
400 | ||
b01c8b54 PM |
401 | /* moved from 0x300 */ |
402 | data_access_check_stab: | |
403 | GET_PACA(r13) | |
404 | std r9,PACA_EXSLB+EX_R9(r13) | |
405 | std r10,PACA_EXSLB+EX_R10(r13) | |
406 | mfspr r10,SPRN_DAR | |
407 | mfspr r9,SPRN_DSISR | |
408 | srdi r10,r10,60 | |
409 | rlwimi r10,r9,16,0x20 | |
de56a948 | 410 | #ifdef CONFIG_KVM_BOOK3S_PR |
3c42bf8a | 411 | lbz r9,HSTATE_IN_GUEST(r13) |
b01c8b54 PM |
412 | rlwimi r10,r9,8,0x300 |
413 | #endif | |
414 | mfcr r9 | |
415 | cmpwi r10,0x2c | |
416 | beq do_stab_bolted_pSeries | |
417 | mtcrf 0x80,r9 | |
418 | ld r9,PACA_EXSLB+EX_R9(r13) | |
419 | ld r10,PACA_EXSLB+EX_R10(r13) | |
420 | b data_access_not_stab | |
421 | do_stab_bolted_pSeries: | |
422 | std r11,PACA_EXSLB+EX_R11(r13) | |
423 | std r12,PACA_EXSLB+EX_R12(r13) | |
424 | GET_SCRATCH0(r10) | |
425 | std r10,PACA_EXSLB+EX_R13(r13) | |
426 | EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD) | |
b01c8b54 | 427 | |
697d3899 PM |
428 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300) |
429 | KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380) | |
de56a948 PM |
430 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x400) |
431 | KVM_HANDLER_PR(PACA_EXSLB, EXC_STD, 0x480) | |
432 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900) | |
b01c8b54 PM |
433 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982) |
434 | ||
b92a66a6 MN |
435 | #ifdef CONFIG_PPC_DENORMALISATION |
436 | denorm_assist: | |
437 | BEGIN_FTR_SECTION | |
438 | /* | |
439 | * To denormalise we need to move a copy of the register to itself. | |
440 | * For POWER6 do that here for all FP regs. | |
441 | */ | |
442 | mfmsr r10 | |
443 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
444 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
445 | mtmsrd r10 | |
446 | sync | |
447 | fmr 0,0 | |
448 | fmr 1,1 | |
449 | fmr 2,2 | |
450 | fmr 3,3 | |
451 | fmr 4,4 | |
452 | fmr 5,5 | |
453 | fmr 6,6 | |
454 | fmr 7,7 | |
455 | fmr 8,8 | |
456 | fmr 9,9 | |
457 | fmr 10,10 | |
458 | fmr 11,11 | |
459 | fmr 12,12 | |
460 | fmr 13,13 | |
461 | fmr 14,14 | |
462 | fmr 15,15 | |
463 | fmr 16,16 | |
464 | fmr 17,17 | |
465 | fmr 18,18 | |
466 | fmr 19,19 | |
467 | fmr 20,20 | |
468 | fmr 21,21 | |
469 | fmr 22,22 | |
470 | fmr 23,23 | |
471 | fmr 24,24 | |
472 | fmr 25,25 | |
473 | fmr 26,26 | |
474 | fmr 27,27 | |
475 | fmr 28,28 | |
476 | fmr 29,29 | |
477 | fmr 30,30 | |
478 | fmr 31,31 | |
479 | FTR_SECTION_ELSE | |
480 | /* | |
481 | * To denormalise we need to move a copy of the register to itself. | |
482 | * For POWER7 do that here for the first 32 VSX registers only. | |
483 | */ | |
484 | mfmsr r10 | |
485 | oris r10,r10,MSR_VSX@h | |
486 | mtmsrd r10 | |
487 | sync | |
488 | XVCPSGNDP(0,0,0) | |
489 | XVCPSGNDP(1,1,1) | |
490 | XVCPSGNDP(2,2,2) | |
491 | XVCPSGNDP(3,3,3) | |
492 | XVCPSGNDP(4,4,4) | |
493 | XVCPSGNDP(5,5,5) | |
494 | XVCPSGNDP(6,6,6) | |
495 | XVCPSGNDP(7,7,7) | |
496 | XVCPSGNDP(8,8,8) | |
497 | XVCPSGNDP(9,9,9) | |
498 | XVCPSGNDP(10,10,10) | |
499 | XVCPSGNDP(11,11,11) | |
500 | XVCPSGNDP(12,12,12) | |
501 | XVCPSGNDP(13,13,13) | |
502 | XVCPSGNDP(14,14,14) | |
503 | XVCPSGNDP(15,15,15) | |
504 | XVCPSGNDP(16,16,16) | |
505 | XVCPSGNDP(17,17,17) | |
506 | XVCPSGNDP(18,18,18) | |
507 | XVCPSGNDP(19,19,19) | |
508 | XVCPSGNDP(20,20,20) | |
509 | XVCPSGNDP(21,21,21) | |
510 | XVCPSGNDP(22,22,22) | |
511 | XVCPSGNDP(23,23,23) | |
512 | XVCPSGNDP(24,24,24) | |
513 | XVCPSGNDP(25,25,25) | |
514 | XVCPSGNDP(26,26,26) | |
515 | XVCPSGNDP(27,27,27) | |
516 | XVCPSGNDP(28,28,28) | |
517 | XVCPSGNDP(29,29,29) | |
518 | XVCPSGNDP(30,30,30) | |
519 | XVCPSGNDP(31,31,31) | |
520 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) | |
521 | mtspr SPRN_HSRR0,r11 | |
522 | mtcrf 0x80,r9 | |
523 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 524 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
b92a66a6 MN |
525 | ld r10,PACA_EXGEN+EX_R10(r13) |
526 | ld r11,PACA_EXGEN+EX_R11(r13) | |
527 | ld r12,PACA_EXGEN+EX_R12(r13) | |
528 | ld r13,PACA_EXGEN+EX_R13(r13) | |
529 | HRFID | |
530 | b . | |
531 | #endif | |
532 | ||
b01c8b54 | 533 | .align 7 |
b3e6b5df | 534 | /* moved from 0xe00 */ |
1707dd16 | 535 | STD_EXCEPTION_HV_OOL(0xe02, h_data_storage) |
b01c8b54 | 536 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0xe02) |
1707dd16 | 537 | STD_EXCEPTION_HV_OOL(0xe22, h_instr_storage) |
b01c8b54 | 538 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe22) |
1707dd16 | 539 | STD_EXCEPTION_HV_OOL(0xe42, emulation_assist) |
b01c8b54 | 540 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe42) |
1707dd16 | 541 | STD_EXCEPTION_HV_OOL(0xe62, hmi_exception) /* need to flush cache ? */ |
b01c8b54 | 542 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe62) |
1707dd16 | 543 | MASKABLE_EXCEPTION_HV_OOL(0xe82, h_doorbell) |
655bb3f4 | 544 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe82) |
0ebc4cda BH |
545 | |
546 | /* moved from 0xf00 */ | |
1707dd16 | 547 | STD_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor) |
de56a948 | 548 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf00) |
1707dd16 | 549 | STD_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable) |
de56a948 | 550 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf20) |
1707dd16 | 551 | STD_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable) |
de56a948 | 552 | KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40) |
0ebc4cda BH |
553 | |
554 | /* | |
fe9e1d54 IM |
555 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
556 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
557 | * - If it was a doorbell we return immediately since doorbells are edge | |
558 | * triggered and won't automatically refire. | |
559 | * - else we hard disable and return. | |
560 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 561 | */ |
7230c564 BH |
562 | #define MASKED_INTERRUPT(_H) \ |
563 | masked_##_H##interrupt: \ | |
564 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
565 | lbz r11,PACAIRQHAPPENED(r13); \ | |
566 | or r11,r11,r10; \ | |
567 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
568 | cmpwi r10,PACA_IRQ_DEC; \ |
569 | bne 1f; \ | |
7230c564 BH |
570 | lis r10,0x7fff; \ |
571 | ori r10,r10,0xffff; \ | |
572 | mtspr SPRN_DEC,r10; \ | |
573 | b 2f; \ | |
fe9e1d54 IM |
574 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
575 | beq 2f; \ | |
576 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
577 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
578 | rotldi r10,r10,16; \ | |
579 | mtspr SPRN_##_H##SRR1,r10; \ | |
580 | 2: mtcrf 0x80,r9; \ | |
581 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
582 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
583 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
584 | GET_SCRATCH0(r13); \ | |
585 | ##_H##rfid; \ | |
0ebc4cda | 586 | b . |
7230c564 BH |
587 | |
588 | MASKED_INTERRUPT() | |
589 | MASKED_INTERRUPT(H) | |
0ebc4cda | 590 | |
7230c564 BH |
591 | /* |
592 | * Called from arch_local_irq_enable when an interrupt needs | |
fe9e1d54 IM |
593 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
594 | * which kind of interrupt. MSR:EE is already off. We generate a | |
7230c564 BH |
595 | * stackframe like if a real interrupt had happened. |
596 | * | |
597 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
598 | * in the generated frame has EE set to 1 or the exception | |
599 | * handler will not properly re-enable them. | |
600 | */ | |
601 | _GLOBAL(__replay_interrupt) | |
602 | /* We are going to jump to the exception common code which | |
603 | * will retrieve various register values from the PACA which | |
604 | * we don't give a damn about, so we don't bother storing them. | |
605 | */ | |
606 | mfmsr r12 | |
607 | mflr r11 | |
608 | mfcr r9 | |
609 | ori r12,r12,MSR_EE | |
fe9e1d54 IM |
610 | cmpwi r3,0x900 |
611 | beq decrementer_common | |
612 | cmpwi r3,0x500 | |
613 | beq hardware_interrupt_common | |
614 | BEGIN_FTR_SECTION | |
615 | cmpwi r3,0xe80 | |
616 | beq h_doorbell_common | |
617 | FTR_SECTION_ELSE | |
618 | cmpwi r3,0xa00 | |
619 | beq doorbell_super_common | |
620 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
621 | blr | |
a5d4f3ad | 622 | |
0ebc4cda BH |
623 | #ifdef CONFIG_PPC_PSERIES |
624 | /* | |
625 | * Vectors for the FWNMI option. Share common code. | |
626 | */ | |
627 | .globl system_reset_fwnmi | |
628 | .align 7 | |
629 | system_reset_fwnmi: | |
44e9309f | 630 | HMT_MEDIUM_PPR_DISCARD |
673b189a | 631 | SET_SCRATCH0(r13) /* save r13 */ |
b01c8b54 PM |
632 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
633 | NOTEST, 0x100) | |
0ebc4cda BH |
634 | |
635 | #endif /* CONFIG_PPC_PSERIES */ | |
636 | ||
637 | #ifdef __DISABLED__ | |
638 | /* | |
639 | * This is used for when the SLB miss handler has to go virtual, | |
640 | * which doesn't happen for now anymore but will once we re-implement | |
641 | * dynamic VSIDs for shared page tables | |
642 | */ | |
643 | slb_miss_user_pseries: | |
644 | std r10,PACA_EXGEN+EX_R10(r13) | |
645 | std r11,PACA_EXGEN+EX_R11(r13) | |
646 | std r12,PACA_EXGEN+EX_R12(r13) | |
673b189a | 647 | GET_SCRATCH0(r10) |
0ebc4cda BH |
648 | ld r11,PACA_EXSLB+EX_R9(r13) |
649 | ld r12,PACA_EXSLB+EX_R3(r13) | |
650 | std r10,PACA_EXGEN+EX_R13(r13) | |
651 | std r11,PACA_EXGEN+EX_R9(r13) | |
652 | std r12,PACA_EXGEN+EX_R3(r13) | |
653 | clrrdi r12,r13,32 | |
654 | mfmsr r10 | |
655 | mfspr r11,SRR0 /* save SRR0 */ | |
656 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
657 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
658 | mtspr SRR0,r12 | |
659 | mfspr r12,SRR1 /* and SRR1 */ | |
660 | mtspr SRR1,r10 | |
661 | rfid | |
662 | b . /* prevent spec. execution */ | |
663 | #endif /* __DISABLED__ */ | |
664 | ||
0ebc4cda BH |
665 | /* |
666 | * Code from here down to __end_handlers is invoked from the | |
667 | * exception prologs above. Because the prologs assemble the | |
668 | * addresses of these handlers using the LOAD_HANDLER macro, | |
61e2390e MN |
669 | * which uses an ori instruction, these handlers must be in |
670 | * the first 64k of the kernel image. | |
0ebc4cda BH |
671 | */ |
672 | ||
673 | /*** Common interrupt handlers ***/ | |
674 | ||
675 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
676 | ||
677 | /* | |
678 | * Machine check is different because we use a different | |
679 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
680 | */ | |
681 | .align 7 | |
682 | .globl machine_check_common | |
683 | machine_check_common: | |
684 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
685 | FINISH_NAP | |
686 | DISABLE_INTS | |
687 | bl .save_nvgprs | |
688 | addi r3,r1,STACK_FRAME_OVERHEAD | |
689 | bl .machine_check_exception | |
690 | b .ret_from_except | |
691 | ||
7450f6f0 BH |
692 | STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ) |
693 | STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt) | |
dabe859e | 694 | STD_EXCEPTION_COMMON(0x980, hdecrementer, .hdec_interrupt) |
1dbdafec IM |
695 | #ifdef CONFIG_PPC_DOORBELL |
696 | STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, .doorbell_exception) | |
697 | #else | |
698 | STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, .unknown_exception) | |
699 | #endif | |
0ebc4cda BH |
700 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) |
701 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
702 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
278a6cdc MN |
703 | STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) |
704 | STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) | |
655bb3f4 IM |
705 | #ifdef CONFIG_PPC_DOORBELL |
706 | STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception) | |
707 | #else | |
708 | STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .unknown_exception) | |
709 | #endif | |
7450f6f0 | 710 | STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception) |
0ebc4cda | 711 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) |
b92a66a6 | 712 | STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception) |
0ebc4cda BH |
713 | #ifdef CONFIG_ALTIVEC |
714 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
715 | #else | |
716 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
717 | #endif | |
718 | #ifdef CONFIG_CBE_RAS | |
719 | STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception) | |
720 | STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception) | |
721 | STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) | |
722 | #endif /* CONFIG_CBE_RAS */ | |
723 | ||
c1fb6816 MN |
724 | /* |
725 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
726 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
727 | * it. Addresses are the same as the original interrupt addresses, but | |
728 | * offset by 0xc000000000004000. | |
729 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
730 | * KVM: None of these traps are from the guest ; anything that escalated | |
731 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
732 | */ | |
733 | ||
734 | /* | |
735 | * This uses the standard macro, since the original 0x300 vector | |
736 | * only has extra guff for STAB-based processors -- which never | |
737 | * come here. | |
738 | */ | |
739 | STD_RELON_EXCEPTION_PSERIES(0x4300, 0x300, data_access) | |
740 | . = 0x4380 | |
741 | .globl data_access_slb_relon_pSeries | |
742 | data_access_slb_relon_pSeries: | |
c1fb6816 | 743 | SET_SCRATCH0(r13) |
1707dd16 | 744 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
745 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
746 | std r3,PACA_EXSLB+EX_R3(r13) | |
747 | mfspr r3,SPRN_DAR | |
748 | mfspr r12,SPRN_SRR1 | |
749 | #ifndef CONFIG_RELOCATABLE | |
750 | b .slb_miss_realmode | |
751 | #else | |
752 | /* | |
753 | * We can't just use a direct branch to .slb_miss_realmode | |
754 | * because the distance from here to there depends on where | |
755 | * the kernel ends up being put. | |
756 | */ | |
757 | mfctr r11 | |
758 | ld r10,PACAKBASE(r13) | |
759 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
760 | mtctr r10 | |
761 | bctr | |
762 | #endif | |
763 | ||
764 | STD_RELON_EXCEPTION_PSERIES(0x4400, 0x400, instruction_access) | |
765 | . = 0x4480 | |
766 | .globl instruction_access_slb_relon_pSeries | |
767 | instruction_access_slb_relon_pSeries: | |
c1fb6816 | 768 | SET_SCRATCH0(r13) |
1707dd16 | 769 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
770 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
771 | std r3,PACA_EXSLB+EX_R3(r13) | |
772 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
773 | mfspr r12,SPRN_SRR1 | |
774 | #ifndef CONFIG_RELOCATABLE | |
775 | b .slb_miss_realmode | |
776 | #else | |
777 | mfctr r11 | |
778 | ld r10,PACAKBASE(r13) | |
779 | LOAD_HANDLER(r10, .slb_miss_realmode) | |
780 | mtctr r10 | |
781 | bctr | |
782 | #endif | |
783 | ||
784 | . = 0x4500 | |
785 | .globl hardware_interrupt_relon_pSeries; | |
786 | .globl hardware_interrupt_relon_hv; | |
787 | hardware_interrupt_relon_pSeries: | |
788 | hardware_interrupt_relon_hv: | |
789 | BEGIN_FTR_SECTION | |
790 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV) | |
791 | FTR_SECTION_ELSE | |
792 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR) | |
793 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206) | |
794 | STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment) | |
795 | STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check) | |
796 | STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable) | |
797 | MASKABLE_RELON_EXCEPTION_PSERIES(0x4900, 0x900, decrementer) | |
798 | STD_RELON_EXCEPTION_HV(0x4980, 0x982, hdecrementer) | |
1dbdafec | 799 | MASKABLE_RELON_EXCEPTION_PSERIES(0x4a00, 0xa00, doorbell_super) |
c1fb6816 MN |
800 | STD_RELON_EXCEPTION_PSERIES(0x4b00, 0xb00, trap_0b) |
801 | ||
802 | . = 0x4c00 | |
803 | .globl system_call_relon_pSeries | |
804 | system_call_relon_pSeries: | |
805 | HMT_MEDIUM | |
806 | SYSCALL_PSERIES_1 | |
807 | SYSCALL_PSERIES_2_DIRECT | |
808 | SYSCALL_PSERIES_3 | |
809 | ||
810 | STD_RELON_EXCEPTION_PSERIES(0x4d00, 0xd00, single_step) | |
811 | ||
812 | . = 0x4e00 | |
1707dd16 PM |
813 | SET_SCRATCH0(r13) |
814 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
815 | b h_data_storage_relon_hv |
816 | ||
817 | . = 0x4e20 | |
1707dd16 PM |
818 | SET_SCRATCH0(r13) |
819 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
820 | b h_instr_storage_relon_hv |
821 | ||
822 | . = 0x4e40 | |
1707dd16 PM |
823 | SET_SCRATCH0(r13) |
824 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
825 | b emulation_assist_relon_hv |
826 | ||
c1fb6816 | 827 | . = 0x4e60 |
1707dd16 PM |
828 | SET_SCRATCH0(r13) |
829 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
830 | b hmi_exception_relon_hv |
831 | ||
655bb3f4 | 832 | . = 0x4e80 |
1707dd16 PM |
833 | SET_SCRATCH0(r13) |
834 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
655bb3f4 | 835 | b h_doorbell_relon_hv |
c1fb6816 MN |
836 | |
837 | performance_monitor_relon_pSeries_1: | |
838 | . = 0x4f00 | |
1707dd16 PM |
839 | SET_SCRATCH0(r13) |
840 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
841 | b performance_monitor_relon_pSeries |
842 | ||
843 | altivec_unavailable_relon_pSeries_1: | |
844 | . = 0x4f20 | |
1707dd16 PM |
845 | SET_SCRATCH0(r13) |
846 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
847 | b altivec_unavailable_relon_pSeries |
848 | ||
849 | vsx_unavailable_relon_pSeries_1: | |
850 | . = 0x4f40 | |
1707dd16 PM |
851 | SET_SCRATCH0(r13) |
852 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
c1fb6816 MN |
853 | b vsx_unavailable_relon_pSeries |
854 | ||
c1fb6816 MN |
855 | STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint) |
856 | #ifdef CONFIG_PPC_DENORMALISATION | |
857 | . = 0x5500 | |
858 | b denorm_exception_hv | |
859 | #endif | |
c1fb6816 MN |
860 | #ifdef CONFIG_HVC_SCOM |
861 | STD_RELON_EXCEPTION_HV(0x5600, 0x1600, maintence_interrupt) | |
862 | KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1600) | |
863 | #endif /* CONFIG_HVC_SCOM */ | |
c1fb6816 | 864 | STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist) |
c1fb6816 MN |
865 | |
866 | /* Other future vectors */ | |
867 | .align 7 | |
868 | .globl __end_interrupts | |
869 | __end_interrupts: | |
870 | ||
0ebc4cda | 871 | .align 7 |
c1fb6816 MN |
872 | system_call_entry_direct: |
873 | #if defined(CONFIG_RELOCATABLE) | |
874 | /* The first level prologue may have used LR to get here, saving | |
875 | * orig in r10. To save hacking/ifdeffing common code, restore here. | |
876 | */ | |
877 | mtlr r10 | |
878 | #endif | |
0ebc4cda BH |
879 | system_call_entry: |
880 | b system_call_common | |
881 | ||
fe1952fc BH |
882 | ppc64_runlatch_on_trampoline: |
883 | b .__ppc64_runlatch_on | |
884 | ||
0ebc4cda BH |
885 | /* |
886 | * Here we have detected that the kernel stack pointer is bad. | |
887 | * R9 contains the saved CR, r13 points to the paca, | |
888 | * r10 contains the (bad) kernel stack pointer, | |
889 | * r11 and r12 contain the saved SRR0 and SRR1. | |
890 | * We switch to using an emergency stack, save the registers there, | |
891 | * and call kernel_bad_stack(), which panics. | |
892 | */ | |
893 | bad_stack: | |
894 | ld r1,PACAEMERGSP(r13) | |
895 | subi r1,r1,64+INT_FRAME_SIZE | |
896 | std r9,_CCR(r1) | |
897 | std r10,GPR1(r1) | |
898 | std r11,_NIP(r1) | |
899 | std r12,_MSR(r1) | |
900 | mfspr r11,SPRN_DAR | |
901 | mfspr r12,SPRN_DSISR | |
902 | std r11,_DAR(r1) | |
903 | std r12,_DSISR(r1) | |
904 | mflr r10 | |
905 | mfctr r11 | |
906 | mfxer r12 | |
907 | std r10,_LINK(r1) | |
908 | std r11,_CTR(r1) | |
909 | std r12,_XER(r1) | |
910 | SAVE_GPR(0,r1) | |
911 | SAVE_GPR(2,r1) | |
1977b502 PM |
912 | ld r10,EX_R3(r3) |
913 | std r10,GPR3(r1) | |
914 | SAVE_GPR(4,r1) | |
915 | SAVE_4GPRS(5,r1) | |
916 | ld r9,EX_R9(r3) | |
917 | ld r10,EX_R10(r3) | |
918 | SAVE_2GPRS(9,r1) | |
919 | ld r9,EX_R11(r3) | |
920 | ld r10,EX_R12(r3) | |
921 | ld r11,EX_R13(r3) | |
922 | std r9,GPR11(r1) | |
923 | std r10,GPR12(r1) | |
924 | std r11,GPR13(r1) | |
48404f2e PM |
925 | BEGIN_FTR_SECTION |
926 | ld r10,EX_CFAR(r3) | |
927 | std r10,ORIG_GPR3(r1) | |
928 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1977b502 | 929 | SAVE_8GPRS(14,r1) |
0ebc4cda BH |
930 | SAVE_10GPRS(22,r1) |
931 | lhz r12,PACA_TRAP_SAVE(r13) | |
932 | std r12,_TRAP(r1) | |
933 | addi r11,r1,INT_FRAME_SIZE | |
934 | std r11,0(r1) | |
935 | li r12,0 | |
936 | std r12,0(r11) | |
937 | ld r2,PACATOC(r13) | |
1977b502 PM |
938 | ld r11,exception_marker@toc(r2) |
939 | std r12,RESULT(r1) | |
940 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
0ebc4cda BH |
941 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
942 | bl .kernel_bad_stack | |
943 | b 1b | |
944 | ||
945 | /* | |
946 | * Here r13 points to the paca, r9 contains the saved CR, | |
947 | * SRR0 and SRR1 are saved in r11 and r12, | |
948 | * r9 - r13 are saved in paca->exgen. | |
949 | */ | |
950 | .align 7 | |
951 | .globl data_access_common | |
952 | data_access_common: | |
953 | mfspr r10,SPRN_DAR | |
954 | std r10,PACA_EXGEN+EX_DAR(r13) | |
955 | mfspr r10,SPRN_DSISR | |
956 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
957 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
a546498f BH |
958 | DISABLE_INTS |
959 | ld r12,_MSR(r1) | |
0ebc4cda BH |
960 | ld r3,PACA_EXGEN+EX_DAR(r13) |
961 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
962 | li r5,0x300 | |
278a6cdc | 963 | b .do_hash_page /* Try to handle as hpte fault */ |
0ebc4cda | 964 | |
b3e6b5df | 965 | .align 7 |
278a6cdc | 966 | .globl h_data_storage_common |
b3e6b5df | 967 | h_data_storage_common: |
278a6cdc MN |
968 | mfspr r10,SPRN_HDAR |
969 | std r10,PACA_EXGEN+EX_DAR(r13) | |
970 | mfspr r10,SPRN_HDSISR | |
971 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
972 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
973 | bl .save_nvgprs | |
a546498f | 974 | DISABLE_INTS |
278a6cdc MN |
975 | addi r3,r1,STACK_FRAME_OVERHEAD |
976 | bl .unknown_exception | |
977 | b .ret_from_except | |
b3e6b5df | 978 | |
0ebc4cda BH |
979 | .align 7 |
980 | .globl instruction_access_common | |
981 | instruction_access_common: | |
982 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
a546498f BH |
983 | DISABLE_INTS |
984 | ld r12,_MSR(r1) | |
0ebc4cda BH |
985 | ld r3,_NIP(r1) |
986 | andis. r4,r12,0x5820 | |
987 | li r5,0x400 | |
988 | b .do_hash_page /* Try to handle as hpte fault */ | |
989 | ||
278a6cdc | 990 | STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception) |
b3e6b5df | 991 | |
0ebc4cda BH |
992 | /* |
993 | * Here is the common SLB miss user that is used when going to virtual | |
994 | * mode for SLB misses, that is currently not used | |
995 | */ | |
996 | #ifdef __DISABLED__ | |
997 | .align 7 | |
998 | .globl slb_miss_user_common | |
999 | slb_miss_user_common: | |
1000 | mflr r10 | |
1001 | std r3,PACA_EXGEN+EX_DAR(r13) | |
1002 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
1003 | std r10,PACA_EXGEN+EX_LR(r13) | |
1004 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
1005 | bl .slb_allocate_user | |
1006 | ||
1007 | ld r10,PACA_EXGEN+EX_LR(r13) | |
1008 | ld r3,PACA_EXGEN+EX_R3(r13) | |
1009 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
1010 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
1011 | mtlr r10 | |
1012 | beq- slb_miss_fault | |
1013 | ||
1014 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1015 | beq- unrecov_user_slb | |
1016 | mfmsr r10 | |
1017 | ||
1018 | .machine push | |
1019 | .machine "power4" | |
1020 | mtcrf 0x80,r9 | |
1021 | .machine pop | |
1022 | ||
1023 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
1024 | mtmsrd r10,1 | |
1025 | ||
1026 | mtspr SRR0,r11 | |
1027 | mtspr SRR1,r12 | |
1028 | ||
1029 | ld r9,PACA_EXGEN+EX_R9(r13) | |
1030 | ld r10,PACA_EXGEN+EX_R10(r13) | |
1031 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1032 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1033 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1034 | rfid | |
1035 | b . | |
1036 | ||
1037 | slb_miss_fault: | |
1038 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
1039 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
1040 | li r5,0 | |
1041 | std r4,_DAR(r1) | |
1042 | std r5,_DSISR(r1) | |
1043 | b handle_page_fault | |
1044 | ||
1045 | unrecov_user_slb: | |
1046 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
1047 | DISABLE_INTS | |
1048 | bl .save_nvgprs | |
1049 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1050 | bl .unrecoverable_exception | |
1051 | b 1b | |
1052 | ||
1053 | #endif /* __DISABLED__ */ | |
1054 | ||
1055 | ||
1056 | /* | |
1057 | * r13 points to the PACA, r9 contains the saved CR, | |
1058 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
1059 | * r3 has the faulting address | |
1060 | * r9 - r13 are saved in paca->exslb. | |
1061 | * r3 is saved in paca->slb_r3 | |
1062 | * We assume we aren't going to take any exceptions during this procedure. | |
1063 | */ | |
1064 | _GLOBAL(slb_miss_realmode) | |
1065 | mflr r10 | |
1066 | #ifdef CONFIG_RELOCATABLE | |
1067 | mtctr r11 | |
1068 | #endif | |
1069 | ||
1070 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1071 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
1072 | ||
1073 | bl .slb_allocate_realmode | |
1074 | ||
1075 | /* All done -- return from exception. */ | |
1076 | ||
1077 | ld r10,PACA_EXSLB+EX_LR(r13) | |
1078 | ld r3,PACA_EXSLB+EX_R3(r13) | |
1079 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
0ebc4cda BH |
1080 | |
1081 | mtlr r10 | |
1082 | ||
1083 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1084 | beq- 2f | |
1085 | ||
1086 | .machine push | |
1087 | .machine "power4" | |
1088 | mtcrf 0x80,r9 | |
1089 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
1090 | .machine pop | |
1091 | ||
44e9309f | 1092 | RESTORE_PPR_PACA(PACA_EXSLB, r9) |
0ebc4cda BH |
1093 | ld r9,PACA_EXSLB+EX_R9(r13) |
1094 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1095 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1096 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1097 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1098 | rfid | |
1099 | b . /* prevent speculative execution */ | |
1100 | ||
4f8cf36f | 1101 | 2: mfspr r11,SPRN_SRR0 |
0ebc4cda BH |
1102 | ld r10,PACAKBASE(r13) |
1103 | LOAD_HANDLER(r10,unrecov_slb) | |
1104 | mtspr SPRN_SRR0,r10 | |
1105 | ld r10,PACAKMSR(r13) | |
1106 | mtspr SPRN_SRR1,r10 | |
1107 | rfid | |
1108 | b . | |
1109 | ||
1110 | unrecov_slb: | |
1111 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1112 | DISABLE_INTS | |
1113 | bl .save_nvgprs | |
1114 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1115 | bl .unrecoverable_exception | |
1116 | b 1b | |
1117 | ||
0ebc4cda BH |
1118 | |
1119 | #ifdef CONFIG_PPC_970_NAP | |
1120 | power4_fixup_nap: | |
1121 | andc r9,r9,r10 | |
1122 | std r9,TI_LOCAL_FLAGS(r11) | |
1123 | ld r10,_LINK(r1) /* make idle task do the */ | |
1124 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1125 | blr | |
1126 | #endif | |
1127 | ||
1128 | .align 7 | |
1129 | .globl alignment_common | |
1130 | alignment_common: | |
1131 | mfspr r10,SPRN_DAR | |
1132 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1133 | mfspr r10,SPRN_DSISR | |
1134 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1135 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1136 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1137 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1138 | std r3,_DAR(r1) | |
1139 | std r4,_DSISR(r1) | |
1140 | bl .save_nvgprs | |
a3512b2d | 1141 | DISABLE_INTS |
0ebc4cda | 1142 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1143 | bl .alignment_exception |
1144 | b .ret_from_except | |
1145 | ||
1146 | .align 7 | |
1147 | .globl program_check_common | |
1148 | program_check_common: | |
1149 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
1150 | bl .save_nvgprs | |
54321242 | 1151 | DISABLE_INTS |
922b9f86 | 1152 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1153 | bl .program_check_exception |
1154 | b .ret_from_except | |
1155 | ||
1156 | .align 7 | |
1157 | .globl fp_unavailable_common | |
1158 | fp_unavailable_common: | |
1159 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
1160 | bne 1f /* if from user, just load it up */ | |
1161 | bl .save_nvgprs | |
9f2f79e3 | 1162 | DISABLE_INTS |
0ebc4cda | 1163 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1164 | bl .kernel_fp_unavailable_exception |
1165 | BUG_OPCODE | |
1166 | 1: bl .load_up_fpu | |
1167 | b fast_exception_return | |
1168 | ||
1169 | .align 7 | |
1170 | .globl altivec_unavailable_common | |
1171 | altivec_unavailable_common: | |
1172 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1173 | #ifdef CONFIG_ALTIVEC | |
1174 | BEGIN_FTR_SECTION | |
1175 | beq 1f | |
1176 | bl .load_up_altivec | |
1177 | b fast_exception_return | |
1178 | 1: | |
1179 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1180 | #endif | |
1181 | bl .save_nvgprs | |
9f2f79e3 | 1182 | DISABLE_INTS |
0ebc4cda | 1183 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1184 | bl .altivec_unavailable_exception |
1185 | b .ret_from_except | |
1186 | ||
1187 | .align 7 | |
1188 | .globl vsx_unavailable_common | |
1189 | vsx_unavailable_common: | |
1190 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1191 | #ifdef CONFIG_VSX | |
1192 | BEGIN_FTR_SECTION | |
7230c564 BH |
1193 | beq 1f |
1194 | b .load_up_vsx | |
0ebc4cda BH |
1195 | 1: |
1196 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1197 | #endif | |
1198 | bl .save_nvgprs | |
9f2f79e3 | 1199 | DISABLE_INTS |
0ebc4cda | 1200 | addi r3,r1,STACK_FRAME_OVERHEAD |
0ebc4cda BH |
1201 | bl .vsx_unavailable_exception |
1202 | b .ret_from_except | |
1203 | ||
1204 | .align 7 | |
1205 | .globl __end_handlers | |
1206 | __end_handlers: | |
1207 | ||
61383407 | 1208 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
1707dd16 | 1209 | STD_RELON_EXCEPTION_HV_OOL(0xe00, h_data_storage) |
61383407 | 1210 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe00) |
1707dd16 | 1211 | STD_RELON_EXCEPTION_HV_OOL(0xe20, h_instr_storage) |
61383407 | 1212 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe20) |
1707dd16 | 1213 | STD_RELON_EXCEPTION_HV_OOL(0xe40, emulation_assist) |
61383407 | 1214 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe40) |
1707dd16 | 1215 | STD_RELON_EXCEPTION_HV_OOL(0xe60, hmi_exception) |
61383407 | 1216 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe60) |
1707dd16 | 1217 | MASKABLE_RELON_EXCEPTION_HV_OOL(0xe80, h_doorbell) |
61383407 BH |
1218 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe80) |
1219 | ||
1707dd16 PM |
1220 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor) |
1221 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable) | |
1222 | STD_RELON_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable) | |
61383407 BH |
1223 | |
1224 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
1225 | /* | |
1226 | * Data area reserved for FWNMI option. | |
1227 | * This address (0x7000) is fixed by the RPA. | |
1228 | */ | |
1229 | .= 0x7000 | |
1230 | .globl fwnmi_data_area | |
1231 | fwnmi_data_area: | |
1232 | ||
1233 | /* pseries and powernv need to keep the whole page from | |
1234 | * 0x7000 to 0x8000 free for use by the firmware | |
1235 | */ | |
1236 | . = 0x8000 | |
1237 | #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */ | |
1238 | ||
1239 | /* Space for CPU0's segment table */ | |
1240 | .balign 4096 | |
1241 | .globl initial_stab | |
1242 | initial_stab: | |
1243 | .space 4096 | |
1244 | ||
1245 | #ifdef CONFIG_PPC_POWERNV | |
1246 | _GLOBAL(opal_mc_secondary_handler) | |
1247 | HMT_MEDIUM_PPR_DISCARD | |
1248 | SET_SCRATCH0(r13) | |
1249 | GET_PACA(r13) | |
1250 | clrldi r3,r3,2 | |
1251 | tovirt(r3,r3) | |
1252 | std r3,PACA_OPAL_MC_EVT(r13) | |
1253 | ld r13,OPAL_MC_SRR0(r3) | |
1254 | mtspr SPRN_SRR0,r13 | |
1255 | ld r13,OPAL_MC_SRR1(r3) | |
1256 | mtspr SPRN_SRR1,r13 | |
1257 | ld r3,OPAL_MC_GPR3(r3) | |
1258 | GET_SCRATCH0(r13) | |
1259 | b machine_check_pSeries | |
1260 | #endif /* CONFIG_PPC_POWERNV */ | |
1261 | ||
1262 | ||
0ebc4cda BH |
1263 | /* |
1264 | * Hash table stuff | |
1265 | */ | |
1266 | .align 7 | |
1267 | _STATIC(do_hash_page) | |
1268 | std r3,_DAR(r1) | |
1269 | std r4,_DSISR(r1) | |
1270 | ||
9c7cc234 | 1271 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1272 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1273 | andis. r0,r4,DSISR_DABRMATCH@h |
1274 | bne- handle_dabr_fault | |
1275 | ||
0ebc4cda BH |
1276 | BEGIN_FTR_SECTION |
1277 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
1278 | bne- do_ste_alloc /* If so handle it */ | |
44ae3ab3 | 1279 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB) |
0ebc4cda | 1280 | |
9778b696 | 1281 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1282 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1283 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1284 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1285 | /* |
1286 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
1287 | * accessing a userspace segment (even from the kernel). We assume | |
1288 | * kernel addresses always have the high bit set. | |
1289 | */ | |
1290 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
1291 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
1292 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
1293 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
1294 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
1295 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
1296 | ||
1297 | /* | |
1298 | * r3 contains the faulting address | |
1299 | * r4 contains the required access permissions | |
1300 | * r5 contains the trap number | |
1301 | * | |
7230c564 | 1302 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda BH |
1303 | */ |
1304 | bl .hash_page /* build HPTE if possible */ | |
1305 | cmpdi r3,0 /* see if hash_page succeeded */ | |
1306 | ||
7230c564 | 1307 | /* Success */ |
0ebc4cda | 1308 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1309 | |
7230c564 BH |
1310 | /* Error */ |
1311 | blt- 13f | |
9c7cc234 | 1312 | |
0ebc4cda BH |
1313 | /* Here we have a page fault that hash_page can't handle. */ |
1314 | handle_page_fault: | |
0ebc4cda BH |
1315 | 11: ld r4,_DAR(r1) |
1316 | ld r5,_DSISR(r1) | |
1317 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1318 | bl .do_page_fault | |
1319 | cmpdi r3,0 | |
a546498f | 1320 | beq+ 12f |
0ebc4cda BH |
1321 | bl .save_nvgprs |
1322 | mr r5,r3 | |
1323 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1324 | lwz r4,_DAR(r1) | |
1325 | bl .bad_page_fault | |
1326 | b .ret_from_except | |
1327 | ||
a546498f BH |
1328 | /* We have a data breakpoint exception - handle it */ |
1329 | handle_dabr_fault: | |
1330 | bl .save_nvgprs | |
1331 | ld r4,_DAR(r1) | |
1332 | ld r5,_DSISR(r1) | |
1333 | addi r3,r1,STACK_FRAME_OVERHEAD | |
9422de3e | 1334 | bl .do_break |
a546498f BH |
1335 | 12: b .ret_from_except_lite |
1336 | ||
0ebc4cda BH |
1337 | |
1338 | /* We have a page fault that hash_page could handle but HV refused | |
1339 | * the PTE insertion | |
1340 | */ | |
a546498f | 1341 | 13: bl .save_nvgprs |
0ebc4cda BH |
1342 | mr r5,r3 |
1343 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1344 | ld r4,_DAR(r1) | |
1345 | bl .low_hash_fault | |
1346 | b .ret_from_except | |
1347 | ||
9c1e1052 PM |
1348 | /* |
1349 | * We come here as a result of a DSI at a point where we don't want | |
1350 | * to call hash_page, such as when we are accessing memory (possibly | |
1351 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1352 | * were soft-disabled. We want to invoke the exception handler for | |
1353 | * the access, or panic if there isn't a handler. | |
1354 | */ | |
1355 | 77: bl .save_nvgprs | |
1356 | mr r4,r3 | |
1357 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1358 | li r5,SIGSEGV | |
1359 | bl .bad_page_fault | |
1360 | b .ret_from_except | |
1361 | ||
0ebc4cda BH |
1362 | /* here we have a segment miss */ |
1363 | do_ste_alloc: | |
1364 | bl .ste_allocate /* try to insert stab entry */ | |
1365 | cmpdi r3,0 | |
1366 | bne- handle_page_fault | |
1367 | b fast_exception_return | |
1368 | ||
1369 | /* | |
1370 | * r13 points to the PACA, r9 contains the saved CR, | |
1371 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1372 | * r9 - r13 are saved in paca->exslb. | |
1373 | * We assume we aren't going to take any exceptions during this procedure. | |
1374 | * We assume (DAR >> 60) == 0xc. | |
1375 | */ | |
1376 | .align 7 | |
1377 | _GLOBAL(do_stab_bolted) | |
1378 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1379 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
1380 | ||
1381 | /* Hash to the primary group */ | |
1382 | ld r10,PACASTABVIRT(r13) | |
1383 | mfspr r11,SPRN_DAR | |
1384 | srdi r11,r11,28 | |
1385 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
1386 | ||
1387 | /* Calculate VSID */ | |
048ee099 AK |
1388 | /* This is a kernel address, so protovsid = ESID | 1 << 37 */ |
1389 | li r9,0x1 | |
1390 | rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0 | |
0ebc4cda BH |
1391 | ASM_VSID_SCRAMBLE(r11, r9, 256M) |
1392 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
1393 | ||
1394 | /* Search the primary group for a free entry */ | |
1395 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1396 | andi. r11,r11,0x80 | |
1397 | beq 2f | |
1398 | addi r10,r10,16 | |
1399 | andi. r11,r10,0x70 | |
1400 | bne 1b | |
1401 | ||
1402 | /* Stick for only searching the primary group for now. */ | |
1403 | /* At least for now, we use a very simple random castout scheme */ | |
1404 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1405 | mftb r11 | |
1406 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1407 | ori r11,r11,0x10 | |
1408 | ||
1409 | /* r10 currently points to an ste one past the group of interest */ | |
1410 | /* make it point to the randomly selected entry */ | |
1411 | subi r10,r10,128 | |
1412 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1413 | ||
1414 | isync /* mark the entry invalid */ | |
1415 | ld r11,0(r10) | |
1416 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1417 | rotldi r11,r11,8 | |
1418 | std r11,0(r10) | |
1419 | sync | |
1420 | ||
1421 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1422 | slbie r11 | |
1423 | ||
1424 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1425 | eieio | |
1426 | ||
1427 | mfspr r11,SPRN_DAR /* Get the new esid */ | |
1428 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | |
1429 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1430 | std r11,0(r10) /* Put new entry back into the stab */ | |
1431 | ||
1432 | sync | |
1433 | ||
1434 | /* All done -- return from exception. */ | |
1435 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1436 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1437 | ||
1438 | andi. r10,r12,MSR_RI | |
1439 | beq- unrecov_slb | |
1440 | ||
1441 | mtcrf 0x80,r9 /* restore CR */ | |
1442 | ||
1443 | mfmsr r10 | |
1444 | clrrdi r10,r10,2 | |
1445 | mtmsrd r10,1 | |
1446 | ||
1447 | mtspr SPRN_SRR0,r11 | |
1448 | mtspr SPRN_SRR1,r12 | |
1449 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1450 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1451 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1452 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1453 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1454 | rfid | |
1455 | b . /* prevent speculative execution */ |