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UBUNTU: Ubuntu-4.10.0-37.41
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / sysfs.c
CommitLineData
8a25a2fd 1#include <linux/device.h>
1da177e4
LT		 2#include <linux/cpu.h>
3#include <linux/smp.h>
4#include <linux/percpu.h>
5#include <linux/init.h>
6#include <linux/sched.h>
4b16f8e2 7#include <linux/export.h>
1da177e4
LT		 8#include <linux/nodemask.h>
9#include <linux/cpumask.h>
10#include <linux/notifier.h>
11
12#include <asm/current.h>
13#include <asm/processor.h>
14#include <asm/cputable.h>
15#include <asm/hvcall.h>
16#include <asm/prom.h>
1da177e4 17#include <asm/machdep.h>
2249ca9d 18#include <asm/smp.h>
a6dbf93a 19#include <asm/pmc.h>
d1211af3 20#include <asm/firmware.h>
1da177e4 21
93197a36
NL		 22#include "cacheinfo.h"
23
b950bdd0
BH		 24#ifdef CONFIG_PPC64
25#include <asm/paca.h>
26#include <asm/lppaca.h>
27#endif
28
1da177e4
LT		 29static DEFINE_PER_CPU(struct cpu, cpu_devices);
30
b950bdd0
BH		 31/*
32 * SMT snooze delay stuff, 64-bit only for now
33 */
34
35#ifdef CONFIG_PPC64
1da177e4 36
0ddd3e7d 37/* Time in microseconds we delay before sleeping in the idle loop */
34852ed5 38static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
1da177e4 39
8a25a2fd
KS		 40static ssize_t store_smt_snooze_delay(struct device *dev,
41 struct device_attribute *attr,
4a0b2b4d 42 const char *buf,
1da177e4
LT		 43 size_t count)
44{
8a25a2fd 45 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 46 ssize_t ret;
b878dc00 47 long snooze;
1da177e4 48
b878dc00 49 ret = sscanf(buf, "%ld", &snooze);
1da177e4
LT		 50 if (ret != 1)
51 return -EINVAL;
52
8a25a2fd 53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
1da177e4
LT		 54 return count;
55}
56
8a25a2fd
KS		 57static ssize_t show_smt_snooze_delay(struct device *dev,
58 struct device_attribute *attr,
4a0b2b4d 59 char *buf)
1da177e4 60{
8a25a2fd 61 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 62
8a25a2fd 63 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
1da177e4
LT		 64}
65
8a25a2fd 66static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
1da177e4
LT		 67 store_smt_snooze_delay);
68
1da177e4
LT		 69static int __init setup_smt_snooze_delay(char *str)
70{
71 unsigned int cpu;
b878dc00 72 long snooze;
1da177e4
LT		 73
74 if (!cpu_has_feature(CPU_FTR_SMT))
75 return 1;
76
b878dc00
AB		 77 snooze = simple_strtol(str, NULL, 10);
78 for_each_possible_cpu(cpu)
79 per_cpu(smt_snooze_delay, cpu) = snooze;
1da177e4
LT		 80
81 return 1;
82}
83__setup("smt-snooze-delay=", setup_smt_snooze_delay);
84
b950bdd0 85#endif /* CONFIG_PPC64 */
180a3362 86
a7189483
WD		 87#ifdef CONFIG_PPC_FSL_BOOK3E
88#define MAX_BIT 63
89
90static u64 pw20_wt;
91static u64 altivec_idle_wt;
92
93static unsigned int get_idle_ticks_bit(u64 ns)
94{
95 u64 cycle;
96
97 if (ns >= 10000)
98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
99 else
100 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
101
102 if (!cycle)
103 return 0;
104
105 return ilog2(cycle);
106}
107
108static void do_show_pwrmgtcr0(void *val)
109{
110 u32 *value = val;
111
112 *value = mfspr(SPRN_PWRMGTCR0);
113}
114
115static ssize_t show_pw20_state(struct device *dev,
116 struct device_attribute *attr, char *buf)
117{
118 u32 value;
119 unsigned int cpu = dev->id;
120
121 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
122
123 value &= PWRMGTCR0_PW20_WAIT;
124
125 return sprintf(buf, "%u\n", value ? 1 : 0);
126}
127
128static void do_store_pw20_state(void *val)
129{
130 u32 *value = val;
131 u32 pw20_state;
132
133 pw20_state = mfspr(SPRN_PWRMGTCR0);
134
135 if (*value)
136 pw20_state |= PWRMGTCR0_PW20_WAIT;
137 else
138 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
139
140 mtspr(SPRN_PWRMGTCR0, pw20_state);
141}
142
143static ssize_t store_pw20_state(struct device *dev,
144 struct device_attribute *attr,
145 const char *buf, size_t count)
146{
147 u32 value;
148 unsigned int cpu = dev->id;
149
150 if (kstrtou32(buf, 0, &value))
151 return -EINVAL;
152
153 if (value > 1)
154 return -EINVAL;
155
156 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
157
158 return count;
159}
160
161static ssize_t show_pw20_wait_time(struct device *dev,
162 struct device_attribute *attr, char *buf)
163{
164 u32 value;
165 u64 tb_cycle = 1;
166 u64 time;
167
168 unsigned int cpu = dev->id;
169
170 if (!pw20_wt) {
171 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
172 value = (value & PWRMGTCR0_PW20_ENT) >>
173 PWRMGTCR0_PW20_ENT_SHIFT;
174
175 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
176 /* convert ms to ns */
177 if (tb_ticks_per_usec > 1000) {
178 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
179 } else {
180 u32 rem_us;
181
182 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
183 &rem_us);
184 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
185 }
186 } else {
187 time = pw20_wt;
188 }
189
190 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
191}
192
193static void set_pw20_wait_entry_bit(void *val)
194{
195 u32 *value = val;
196 u32 pw20_idle;
197
198 pw20_idle = mfspr(SPRN_PWRMGTCR0);
199
200 /* Set Automatic PW20 Core Idle Count */
201 /* clear count */
202 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
203
204 /* set count */
205 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
206
207 mtspr(SPRN_PWRMGTCR0, pw20_idle);
208}
209
210static ssize_t store_pw20_wait_time(struct device *dev,
211 struct device_attribute *attr,
212 const char *buf, size_t count)
213{
214 u32 entry_bit;
215 u64 value;
216
217 unsigned int cpu = dev->id;
218
219 if (kstrtou64(buf, 0, &value))
220 return -EINVAL;
221
222 if (!value)
223 return -EINVAL;
224
225 entry_bit = get_idle_ticks_bit(value);
226 if (entry_bit > MAX_BIT)
227 return -EINVAL;
228
229 pw20_wt = value;
230
231 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
232 &entry_bit, 1);
233
234 return count;
235}
236
237static ssize_t show_altivec_idle(struct device *dev,
238 struct device_attribute *attr, char *buf)
239{
240 u32 value;
241 unsigned int cpu = dev->id;
242
243 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
244
245 value &= PWRMGTCR0_AV_IDLE_PD_EN;
246
247 return sprintf(buf, "%u\n", value ? 1 : 0);
248}
249
250static void do_store_altivec_idle(void *val)
251{
252 u32 *value = val;
253 u32 altivec_idle;
254
255 altivec_idle = mfspr(SPRN_PWRMGTCR0);
256
257 if (*value)
258 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
259 else
260 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
261
262 mtspr(SPRN_PWRMGTCR0, altivec_idle);
263}
264
265static ssize_t store_altivec_idle(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf, size_t count)
268{
269 u32 value;
270 unsigned int cpu = dev->id;
271
272 if (kstrtou32(buf, 0, &value))
273 return -EINVAL;
274
275 if (value > 1)
276 return -EINVAL;
277
278 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
279
280 return count;
281}
282
283static ssize_t show_altivec_idle_wait_time(struct device *dev,
284 struct device_attribute *attr, char *buf)
285{
286 u32 value;
287 u64 tb_cycle = 1;
288 u64 time;
289
290 unsigned int cpu = dev->id;
291
292 if (!altivec_idle_wt) {
293 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
294 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
295 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
296
297 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
298 /* convert ms to ns */
299 if (tb_ticks_per_usec > 1000) {
300 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
301 } else {
302 u32 rem_us;
303
304 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
305 &rem_us);
306 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
307 }
308 } else {
309 time = altivec_idle_wt;
310 }
311
312 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
313}
314
315static void set_altivec_idle_wait_entry_bit(void *val)
316{
317 u32 *value = val;
318 u32 altivec_idle;
319
320 altivec_idle = mfspr(SPRN_PWRMGTCR0);
321
322 /* Set Automatic AltiVec Idle Count */
323 /* clear count */
324 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
325
326 /* set count */
327 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
328
329 mtspr(SPRN_PWRMGTCR0, altivec_idle);
330}
331
332static ssize_t store_altivec_idle_wait_time(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335{
336 u32 entry_bit;
337 u64 value;
338
339 unsigned int cpu = dev->id;
340
341 if (kstrtou64(buf, 0, &value))
342 return -EINVAL;
343
344 if (!value)
345 return -EINVAL;
346
347 entry_bit = get_idle_ticks_bit(value);
348 if (entry_bit > MAX_BIT)
349 return -EINVAL;
350
351 altivec_idle_wt = value;
352
353 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
354 &entry_bit, 1);
355
356 return count;
357}
358
359/*
360 * Enable/Disable interface:
361 * 0, disable. 1, enable.
362 */
363static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
364static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
365
366/*
367 * Set wait time interface:(Nanosecond)
368 * Example: Base on TBfreq is 41MHZ.
369 * 1~48(ns): TB[63]
370 * 49~97(ns): TB[62]
371 * 98~195(ns): TB[61]
372 * 196~390(ns): TB[60]
373 * 391~780(ns): TB[59]
374 * 781~1560(ns): TB[58]
375 * ...
376 */
377static DEVICE_ATTR(pw20_wait_time, 0600,
378 show_pw20_wait_time,
379 store_pw20_wait_time);
380static DEVICE_ATTR(altivec_idle_wait_time, 0600,
381 show_altivec_idle_wait_time,
382 store_altivec_idle_wait_time);
383#endif
384
1da177e4
LT		 385/*
386 * Enabling PMCs will slow partition context switch times so we only do
387 * it the first time we write to the PMCs.
388 */
389
390static DEFINE_PER_CPU(char, pmcs_enabled);
391
b950bdd0 392void ppc_enable_pmcs(void)
1da177e4 393{
a6dbf93a
PM		 394 ppc_set_pmu_inuse(1);
395
1da177e4 396 /* Only need to enable them once */
69111bac 397 if (__this_cpu_read(pmcs_enabled))
1da177e4
LT		 398 return;
399
69111bac 400 __this_cpu_write(pmcs_enabled, 1);
1da177e4 401
180a3362
ME		 402 if (ppc_md.enable_pmcs)
403 ppc_md.enable_pmcs();
1da177e4 404}
b950bdd0 405EXPORT_SYMBOL(ppc_enable_pmcs);
1da177e4 406
39a360ef 407#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
9a371934 408static void read_##NAME(void *val) \
1da177e4 409{ \
ec78c8ac 410 *(unsigned long *)val = mfspr(ADDRESS); \
1da177e4 411} \
ec78c8ac 412static void write_##NAME(void *val) \
1da177e4 413{ \
fd7e4296 414 EXTRA; \
9a371934 415 mtspr(ADDRESS, *(unsigned long *)val); \
39a360ef
S		 416}
417
418#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
8a25a2fd
KS		 419static ssize_t show_##NAME(struct device *dev, \
420 struct device_attribute *attr, \
4a0b2b4d 421 char *buf) \
1da177e4 422{ \
8a25a2fd 423 struct cpu *cpu = container_of(dev, struct cpu, dev); \
9a371934 424 unsigned long val; \
8a25a2fd 425 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
1da177e4
LT		 426 return sprintf(buf, "%lx\n", val); \
427} \
3ff6eecc 428static ssize_t __used \
8a25a2fd 429 store_##NAME(struct device *dev, struct device_attribute *attr, \
4a0b2b4d 430 const char *buf, size_t count) \
1da177e4 431{ \
8a25a2fd 432 struct cpu *cpu = container_of(dev, struct cpu, dev); \
1da177e4
LT		 433 unsigned long val; \
434 int ret = sscanf(buf, "%lx", &val); \
435 if (ret != 1) \
436 return -EINVAL; \
8a25a2fd 437 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
1da177e4
LT		 438 return count; \
439}
440
39a360ef
S		 441#define SYSFS_PMCSETUP(NAME, ADDRESS) \
442 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
443 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
444#define SYSFS_SPRSETUP(NAME, ADDRESS) \
445 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
446 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
447
448#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
449 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
6529c13d
OJ		 450
451/* Let's define all possible registers, we'll only hook up the ones
452 * that are implemented on the current processor
453 */
454
33a7f122 455#if defined(CONFIG_PPC64)
b950bdd0
BH		 456#define HAS_PPC_PMC_CLASSIC 1
457#define HAS_PPC_PMC_IBM 1
458#define HAS_PPC_PMC_PA6T 1
33a7f122 459#elif defined(CONFIG_6xx)
b950bdd0
BH		 460#define HAS_PPC_PMC_CLASSIC 1
461#define HAS_PPC_PMC_IBM 1
462#define HAS_PPC_PMC_G4 1
463#endif
464
465
466#ifdef HAS_PPC_PMC_CLASSIC
1da177e4
LT		 467SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
468SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
1da177e4
LT		 469SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
470SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
471SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
472SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
473SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
474SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
b950bdd0
BH		 475
476#ifdef HAS_PPC_PMC_G4
477SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
478#endif
479
480#ifdef CONFIG_PPC64
1da177e4
LT		 481SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
482SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
b950bdd0
BH		 483
484SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
fd7e4296
MS		 485SYSFS_SPRSETUP(purr, SPRN_PURR);
486SYSFS_SPRSETUP(spurr, SPRN_SPURR);
fd7e4296 487SYSFS_SPRSETUP(pir, SPRN_PIR);
1da177e4 488
d1211af3
MS		 489/*
490 Lets only enable read for phyp resources and
491 enable write when needed with a separate function.
492 Lets be conservative and default to pseries.
493*/
8a25a2fd 494static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
d5dae721 495static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
d1211af3 496static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
7affca35 497static DEVICE_ATTR(pir, 0400, show_pir, NULL);
efcac658 498
d3cb06e0
AK		 499/*
500 * This is the system wide DSCR register default value. Any
501 * change to this default value through the sysfs interface
502 * will update all per cpu DSCR default values across the
503 * system stored in their respective PACA structures.
504 */
1739ea9e
S		 505static unsigned long dscr_default;
506
d3cb06e0
AK		 507/**
508 * read_dscr() - Fetch the cpu specific DSCR default
509 * @val: Returned cpu specific DSCR default value
510 *
511 * This function returns the per cpu DSCR default value
512 * for any cpu which is contained in it's PACA structure.
513 */
1739ea9e
S		 514static void read_dscr(void *val)
515{
516 *(unsigned long *)val = get_paca()->dscr_default;
517}
518
d3cb06e0
AK		 519
520/**
521 * write_dscr() - Update the cpu specific DSCR default
522 * @val: New cpu specific DSCR default value to update
523 *
524 * This function updates the per cpu DSCR default value
525 * for any cpu which is contained in it's PACA structure.
526 */
1739ea9e
S		 527static void write_dscr(void *val)
528{
529 get_paca()->dscr_default = *(unsigned long *)val;
530 if (!current->thread.dscr_inherit) {
531 current->thread.dscr = *(unsigned long *)val;
532 mtspr(SPRN_DSCR, *(unsigned long *)val);
533 }
534}
535
536SYSFS_SPRSETUP_SHOW_STORE(dscr);
537static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
efcac658 538
d1211af3
MS		 539static void add_write_permission_dev_attr(struct device_attribute *attr)
540{
541 attr->attr.mode |= 0200;
542}
543
d3cb06e0
AK		 544/**
545 * show_dscr_default() - Fetch the system wide DSCR default
546 * @dev: Device structure
547 * @attr: Device attribute structure
548 * @buf: Interface buffer
549 *
550 * This function returns the system wide DSCR default value.
551 */
8a25a2fd
KS		 552static ssize_t show_dscr_default(struct device *dev,
553 struct device_attribute *attr, char *buf)
efcac658
AK		 554{
555 return sprintf(buf, "%lx\n", dscr_default);
556}
557
d3cb06e0
AK		 558/**
559 * store_dscr_default() - Update the system wide DSCR default
560 * @dev: Device structure
561 * @attr: Device attribute structure
562 * @buf: Interface buffer
563 * @count: Size of the update
564 *
565 * This function updates the system wide DSCR default value.
566 */
8a25a2fd
KS		 567static ssize_t __used store_dscr_default(struct device *dev,
568 struct device_attribute *attr, const char *buf,
efcac658
AK		 569 size_t count)
570{
571 unsigned long val;
572 int ret = 0;
573
574 ret = sscanf(buf, "%lx", &val);
575 if (ret != 1)
576 return -EINVAL;
577 dscr_default = val;
578
1739ea9e 579 on_each_cpu(write_dscr, &val, 1);
1b6ca2a6 580
efcac658
AK		 581 return count;
582}
583
8a25a2fd 584static DEVICE_ATTR(dscr_default, 0600,
efcac658
AK		 585 show_dscr_default, store_dscr_default);
586
587static void sysfs_create_dscr_default(void)
588{
589 int err = 0;
590 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 591 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
efcac658 592}
b950bdd0
BH		 593#endif /* CONFIG_PPC64 */
594
595#ifdef HAS_PPC_PMC_PA6T
25fc530e
OJ		 596SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
597SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
598SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
599SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
600SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
601SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
2e1957fd 602#ifdef CONFIG_DEBUG_KERNEL
fd7e4296
MS		 603SYSFS_SPRSETUP(hid0, SPRN_HID0);
604SYSFS_SPRSETUP(hid1, SPRN_HID1);
605SYSFS_SPRSETUP(hid4, SPRN_HID4);
606SYSFS_SPRSETUP(hid5, SPRN_HID5);
607SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
608SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
609SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
610SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
611SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
612SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
613SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
614SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
615SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
616SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
617SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
618SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
619SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
620SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
621SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
622SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
623SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
624SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
625SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
626SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
627SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
628SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
629SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
630SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
2e1957fd 631#endif /* CONFIG_DEBUG_KERNEL */
b950bdd0 632#endif /* HAS_PPC_PMC_PA6T */
6529c13d 633
b950bdd0 634#ifdef HAS_PPC_PMC_IBM
8a25a2fd
KS		 635static struct device_attribute ibm_common_attrs[] = {
636 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
637 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
6529c13d 638};
b950bdd0
BH		 639#endif /* HAS_PPC_PMC_G4 */
640
641#ifdef HAS_PPC_PMC_G4
8a25a2fd
KS		 642static struct device_attribute g4_common_attrs[] = {
643 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
644 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
645 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
b950bdd0
BH		 646};
647#endif /* HAS_PPC_PMC_G4 */
6529c13d 648
8a25a2fd
KS		 649static struct device_attribute classic_pmc_attrs[] = {
650 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
651 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
652 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
653 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
654 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
655 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
b950bdd0 656#ifdef CONFIG_PPC64
8a25a2fd
KS		 657 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
658 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
b950bdd0 659#endif
6529c13d
OJ		 660};
661
b950bdd0 662#ifdef HAS_PPC_PMC_PA6T
8a25a2fd
KS		 663static struct device_attribute pa6t_attrs[] = {
664 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
665 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
666 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
667 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
668 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
669 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
670 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
671 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
2e1957fd 672#ifdef CONFIG_DEBUG_KERNEL
8a25a2fd
KS		 673 __ATTR(hid0, 0600, show_hid0, store_hid0),
674 __ATTR(hid1, 0600, show_hid1, store_hid1),
675 __ATTR(hid4, 0600, show_hid4, store_hid4),
676 __ATTR(hid5, 0600, show_hid5, store_hid5),
677 __ATTR(ima0, 0600, show_ima0, store_ima0),
678 __ATTR(ima1, 0600, show_ima1, store_ima1),
679 __ATTR(ima2, 0600, show_ima2, store_ima2),
680 __ATTR(ima3, 0600, show_ima3, store_ima3),
681 __ATTR(ima4, 0600, show_ima4, store_ima4),
682 __ATTR(ima5, 0600, show_ima5, store_ima5),
683 __ATTR(ima6, 0600, show_ima6, store_ima6),
684 __ATTR(ima7, 0600, show_ima7, store_ima7),
685 __ATTR(ima8, 0600, show_ima8, store_ima8),
686 __ATTR(ima9, 0600, show_ima9, store_ima9),
687 __ATTR(imaat, 0600, show_imaat, store_imaat),
688 __ATTR(btcr, 0600, show_btcr, store_btcr),
689 __ATTR(pccr, 0600, show_pccr, store_pccr),
690 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
691 __ATTR(der, 0600, show_der, store_der),
692 __ATTR(mer, 0600, show_mer, store_mer),
693 __ATTR(ber, 0600, show_ber, store_ber),
694 __ATTR(ier, 0600, show_ier, store_ier),
695 __ATTR(sier, 0600, show_sier, store_sier),
696 __ATTR(siar, 0600, show_siar, store_siar),
697 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
698 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
699 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
700 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
2e1957fd 701#endif /* CONFIG_DEBUG_KERNEL */
6529c13d 702};
b950bdd0
BH		 703#endif /* HAS_PPC_PMC_PA6T */
704#endif /* HAS_PPC_PMC_CLASSIC */
6529c13d 705
977ab257 706static int register_cpu_online(unsigned int cpu)
1da177e4
LT		 707{
708 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS		 709 struct device *s = &c->dev;
710 struct device_attribute *attrs, *pmc_attrs;
6529c13d 711 int i, nattrs;
1da177e4 712
b950bdd0 713#ifdef CONFIG_PPC64
f5339277 714 if (cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 715 device_create_file(s, &dev_attr_smt_snooze_delay);
b950bdd0 716#endif
1da177e4
LT		 717
718 /* PMC stuff */
6529c13d 719 switch (cur_cpu_spec->pmc_type) {
b950bdd0 720#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ		 721 case PPC_PMC_IBM:
722 attrs = ibm_common_attrs;
8a25a2fd 723 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0 724 pmc_attrs = classic_pmc_attrs;
6529c13d 725 break;
b950bdd0
BH		 726#endif /* HAS_PPC_PMC_IBM */
727#ifdef HAS_PPC_PMC_G4
728 case PPC_PMC_G4:
729 attrs = g4_common_attrs;
8a25a2fd 730 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH		 731 pmc_attrs = classic_pmc_attrs;
732 break;
733#endif /* HAS_PPC_PMC_G4 */
734#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ		 735 case PPC_PMC_PA6T:
736 /* PA Semi starts counting at PMC0 */
737 attrs = pa6t_attrs;
8a25a2fd 738 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ		 739 pmc_attrs = NULL;
740 break;
b950bdd0 741#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ		 742 default:
743 attrs = NULL;
744 nattrs = 0;
745 pmc_attrs = NULL;
746 }
747
748 for (i = 0; i < nattrs; i++)
8a25a2fd 749 device_create_file(s, &attrs[i]);
1da177e4 750
6529c13d
OJ		 751 if (pmc_attrs)
752 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 753 device_create_file(s, &pmc_attrs[i]);
1da177e4 754
b950bdd0 755#ifdef CONFIG_PPC64
1da177e4 756 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 757 device_create_file(s, &dev_attr_mmcra);
1da177e4 758
d1211af3
MS		 759 if (cpu_has_feature(CPU_FTR_PURR)) {
760 if (!firmware_has_feature(FW_FEATURE_LPAR))
761 add_write_permission_dev_attr(&dev_attr_purr);
8a25a2fd 762 device_create_file(s, &dev_attr_purr);
d1211af3 763 }
4c198557 764
f050982a 765 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 766 device_create_file(s, &dev_attr_spurr);
f050982a 767
4c198557 768 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 769 device_create_file(s, &dev_attr_dscr);
595fe914
AM		 770
771 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
7affca35 772 device_create_file(s, &dev_attr_pir);
b950bdd0 773#endif /* CONFIG_PPC64 */
124c27d3 774
a7189483
WD		 775#ifdef CONFIG_PPC_FSL_BOOK3E
776 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
777 device_create_file(s, &dev_attr_pw20_state);
778 device_create_file(s, &dev_attr_pw20_wait_time);
779
780 device_create_file(s, &dev_attr_altivec_idle);
781 device_create_file(s, &dev_attr_altivec_idle_wait_time);
782 }
783#endif
93197a36 784 cacheinfo_cpu_online(cpu);
977ab257 785 return 0;
1da177e4
LT		 786}
787
977ab257 788static int unregister_cpu_online(unsigned int cpu)
1da177e4 789{
977ab257 790#ifdef CONFIG_HOTPLUG_CPU
1da177e4 791 struct cpu *c = &per_cpu(cpu_devices, cpu);
8a25a2fd
KS		 792 struct device *s = &c->dev;
793 struct device_attribute *attrs, *pmc_attrs;
6529c13d 794 int i, nattrs;
1da177e4 795
72486f1f 796 BUG_ON(!c->hotpluggable);
1da177e4 797
a1e0eb10 798#ifdef CONFIG_PPC64
f5339277 799 if (cpu_has_feature(CPU_FTR_SMT))
8a25a2fd 800 device_remove_file(s, &dev_attr_smt_snooze_delay);
a1e0eb10 801#endif
1da177e4
LT		 802
803 /* PMC stuff */
6529c13d 804 switch (cur_cpu_spec->pmc_type) {
b950bdd0 805#ifdef HAS_PPC_PMC_IBM
6529c13d
OJ		 806 case PPC_PMC_IBM:
807 attrs = ibm_common_attrs;
8a25a2fd 808 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
b950bdd0
BH		 809 pmc_attrs = classic_pmc_attrs;
810 break;
811#endif /* HAS_PPC_PMC_IBM */
812#ifdef HAS_PPC_PMC_G4
813 case PPC_PMC_G4:
814 attrs = g4_common_attrs;
8a25a2fd 815 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
b950bdd0 816 pmc_attrs = classic_pmc_attrs;
6529c13d 817 break;
b950bdd0
BH		 818#endif /* HAS_PPC_PMC_G4 */
819#ifdef HAS_PPC_PMC_PA6T
6529c13d
OJ		 820 case PPC_PMC_PA6T:
821 /* PA Semi starts counting at PMC0 */
822 attrs = pa6t_attrs;
8a25a2fd 823 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
6529c13d
OJ		 824 pmc_attrs = NULL;
825 break;
b950bdd0 826#endif /* HAS_PPC_PMC_PA6T */
6529c13d
OJ		 827 default:
828 attrs = NULL;
829 nattrs = 0;
830 pmc_attrs = NULL;
831 }
1da177e4 832
6529c13d 833 for (i = 0; i < nattrs; i++)
8a25a2fd 834 device_remove_file(s, &attrs[i]);
6529c13d
OJ		 835
836 if (pmc_attrs)
837 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
8a25a2fd 838 device_remove_file(s, &pmc_attrs[i]);
1da177e4 839
b950bdd0 840#ifdef CONFIG_PPC64
1da177e4 841 if (cpu_has_feature(CPU_FTR_MMCRA))
8a25a2fd 842 device_remove_file(s, &dev_attr_mmcra);
1da177e4 843
afd05423 844 if (cpu_has_feature(CPU_FTR_PURR))
8a25a2fd 845 device_remove_file(s, &dev_attr_purr);
4c198557 846
f050982a 847 if (cpu_has_feature(CPU_FTR_SPURR))
8a25a2fd 848 device_remove_file(s, &dev_attr_spurr);
f050982a 849
4c198557 850 if (cpu_has_feature(CPU_FTR_DSCR))
8a25a2fd 851 device_remove_file(s, &dev_attr_dscr);
595fe914
AM		 852
853 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
7affca35 854 device_remove_file(s, &dev_attr_pir);
b950bdd0 855#endif /* CONFIG_PPC64 */
124c27d3 856
a7189483
WD		 857#ifdef CONFIG_PPC_FSL_BOOK3E
858 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
859 device_remove_file(s, &dev_attr_pw20_state);
860 device_remove_file(s, &dev_attr_pw20_wait_time);
861
862 device_remove_file(s, &dev_attr_altivec_idle);
863 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
864 }
865#endif
93197a36 866 cacheinfo_cpu_offline(cpu);
977ab257
SAS		 867#endif /* CONFIG_HOTPLUG_CPU */
868 return 0;
1da177e4 869}
12633e80
NF		 870
871#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
872ssize_t arch_cpu_probe(const char *buf, size_t count)
873{
874 if (ppc_md.cpu_probe)
875 return ppc_md.cpu_probe(buf, count);
876
877 return -EINVAL;
878}
879
880ssize_t arch_cpu_release(const char *buf, size_t count)
881{
882 if (ppc_md.cpu_release)
883 return ppc_md.cpu_release(buf, count);
884
885 return -EINVAL;
886}
887#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
888
0344c6c5
CK		 889static DEFINE_MUTEX(cpu_mutex);
890
8a25a2fd 891int cpu_add_dev_attr(struct device_attribute *attr)
0344c6c5
CK		 892{
893 int cpu;
894
895 mutex_lock(&cpu_mutex);
896
897 for_each_possible_cpu(cpu) {
8a25a2fd 898 device_create_file(get_cpu_device(cpu), attr);
0344c6c5
CK		 899 }
900
901 mutex_unlock(&cpu_mutex);
902 return 0;
903}
8a25a2fd 904EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
0344c6c5 905
8a25a2fd 906int cpu_add_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK		 907{
908 int cpu;
8a25a2fd 909 struct device *dev;
6bcc4c01 910 int ret;
0344c6c5
CK		 911
912 mutex_lock(&cpu_mutex);
913
914 for_each_possible_cpu(cpu) {
8a25a2fd
KS		 915 dev = get_cpu_device(cpu);
916 ret = sysfs_create_group(&dev->kobj, attrs);
6bcc4c01 917 WARN_ON(ret != 0);
0344c6c5
CK		 918 }
919
920 mutex_unlock(&cpu_mutex);
921 return 0;
922}
8a25a2fd 923EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
0344c6c5
CK		 924
925
8a25a2fd 926void cpu_remove_dev_attr(struct device_attribute *attr)
0344c6c5
CK		 927{
928 int cpu;
929
930 mutex_lock(&cpu_mutex);
931
932 for_each_possible_cpu(cpu) {
8a25a2fd 933 device_remove_file(get_cpu_device(cpu), attr);
0344c6c5
CK		 934 }
935
936 mutex_unlock(&cpu_mutex);
937}
8a25a2fd 938EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
0344c6c5 939
8a25a2fd 940void cpu_remove_dev_attr_group(struct attribute_group *attrs)
0344c6c5
CK		 941{
942 int cpu;
8a25a2fd 943 struct device *dev;
0344c6c5
CK		 944
945 mutex_lock(&cpu_mutex);
946
947 for_each_possible_cpu(cpu) {
8a25a2fd
KS		 948 dev = get_cpu_device(cpu);
949 sysfs_remove_group(&dev->kobj, attrs);
0344c6c5
CK		 950 }
951
952 mutex_unlock(&cpu_mutex);
953}
8a25a2fd 954EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
0344c6c5
CK		 955
956
1da177e4
LT		 957/* NUMA stuff */
958
959#ifdef CONFIG_NUMA
1da177e4
LT		 960static void register_nodes(void)
961{
962 int i;
963
0fc44159
YG		 964 for (i = 0; i < MAX_NUMNODES; i++)
965 register_one_node(i);
1da177e4 966}
953039c8 967
8a25a2fd 968int sysfs_add_device_to_node(struct device *dev, int nid)
953039c8 969{
8732794b 970 struct node *node = node_devices[nid];
10fbcf4c 971 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
953039c8
JK		 972 kobject_name(&dev->kobj));
973}
12654f77 974EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
953039c8 975
8a25a2fd 976void sysfs_remove_device_from_node(struct device *dev, int nid)
953039c8 977{
8732794b 978 struct node *node = node_devices[nid];
10fbcf4c 979 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
953039c8 980}
12654f77 981EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
953039c8 982
1da177e4
LT		 983#else
984static void register_nodes(void)
985{
986 return;
987}
953039c8 988
1da177e4
LT		 989#endif
990
991/* Only valid if CPU is present. */
8a25a2fd
KS		 992static ssize_t show_physical_id(struct device *dev,
993 struct device_attribute *attr, char *buf)
1da177e4 994{
8a25a2fd 995 struct cpu *cpu = container_of(dev, struct cpu, dev);
1da177e4 996
8a25a2fd 997 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1da177e4 998}
8a25a2fd 999static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1da177e4
LT		 1000
1001static int __init topology_init(void)
1002{
977ab257 1003 int cpu, r;
1da177e4
LT		 1004
1005 register_nodes();
d1a55113 1006
0e551954 1007 for_each_possible_cpu(cpu) {
1da177e4
LT		 1008 struct cpu *c = &per_cpu(cpu_devices, cpu);
1009
1da177e4
LT		 1010 /*
1011 * For now, we just see if the system supports making
1012 * the RTAS calls for CPU hotplug. But, there may be a
1013 * more comprehensive way to do this for an individual
1014 * CPU. For instance, the boot cpu might never be valid
1015 * for hotplugging.
1016 */
72486f1f
SS		 1017 if (ppc_md.cpu_die)
1018 c->hotpluggable = 1;
1da177e4 1019
72486f1f 1020 if (cpu_online(cpu) || c->hotpluggable) {
76b67ed9 1021 register_cpu(c, cpu);
1da177e4 1022
8a25a2fd 1023 device_create_file(&c->dev, &dev_attr_physical_id);
1da177e4 1024 }
1da177e4 1025 }
977ab257
SAS		 1026 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1027 register_cpu_online, unregister_cpu_online);
1028 WARN_ON(r < 0);
efcac658
AK		 1029#ifdef CONFIG_PPC64
1030 sysfs_create_dscr_default();
1031#endif /* CONFIG_PPC64 */
1da177e4
LT		 1032
1033 return 0;
1034}
e9e77ce8 1035subsys_initcall(topology_init);
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