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net: ena: fix theoretical Rx hang on low memory systems
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / amazon / ena / ena_netdev.c
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1738cd3e
NB		 1/*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#ifdef CONFIG_RFS_ACCEL
36#include <linux/cpu_rmap.h>
37#endif /* CONFIG_RFS_ACCEL */
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/numa.h>
44#include <linux/pci.h>
45#include <linux/utsname.h>
46#include <linux/version.h>
47#include <linux/vmalloc.h>
48#include <net/ip.h>
49
50#include "ena_netdev.h"
51#include "ena_pci_id_tbl.h"
52
53static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
54
55MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
56MODULE_DESCRIPTION(DEVICE_NAME);
57MODULE_LICENSE("GPL");
58MODULE_VERSION(DRV_MODULE_VERSION);
59
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (5 * HZ)
62
63#define ENA_NAPI_BUDGET 64
64
65#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
67static int debug = -1;
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71static struct ena_aenq_handlers aenq_handlers;
72
73static struct workqueue_struct *ena_wq;
74
75MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
76
77static int ena_rss_init_default(struct ena_adapter *adapter);
78
79static void ena_tx_timeout(struct net_device *dev)
80{
81 struct ena_adapter *adapter = netdev_priv(dev);
82
d5796182
NB		 83 /* Change the state of the device to trigger reset
84 * Check that we are not in the middle or a trigger already
85 */
86
87 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
88 return;
89
1738cd3e
NB		 90 u64_stats_update_begin(&adapter->syncp);
91 adapter->dev_stats.tx_timeout++;
92 u64_stats_update_end(&adapter->syncp);
93
94 netif_err(adapter, tx_err, dev, "Transmit time out\n");
1738cd3e
NB		 95}
96
97static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
98{
99 int i;
100
101 for (i = 0; i < adapter->num_queues; i++)
102 adapter->rx_ring[i].mtu = mtu;
103}
104
105static int ena_change_mtu(struct net_device *dev, int new_mtu)
106{
107 struct ena_adapter *adapter = netdev_priv(dev);
108 int ret;
109
1738cd3e
NB		 110 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
111 if (!ret) {
112 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
113 update_rx_ring_mtu(adapter, new_mtu);
114 dev->mtu = new_mtu;
115 } else {
116 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
117 new_mtu);
118 }
119
120 return ret;
121}
122
123static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
124{
125#ifdef CONFIG_RFS_ACCEL
126 u32 i;
127 int rc;
128
129 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
130 if (!adapter->netdev->rx_cpu_rmap)
131 return -ENOMEM;
132 for (i = 0; i < adapter->num_queues; i++) {
133 int irq_idx = ENA_IO_IRQ_IDX(i);
134
135 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
e328a031 136 pci_irq_vector(adapter->pdev, irq_idx));
1738cd3e
NB		 137 if (rc) {
138 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
139 adapter->netdev->rx_cpu_rmap = NULL;
140 return rc;
141 }
142 }
143#endif /* CONFIG_RFS_ACCEL */
144 return 0;
145}
146
147static void ena_init_io_rings_common(struct ena_adapter *adapter,
148 struct ena_ring *ring, u16 qid)
149{
150 ring->qid = qid;
151 ring->pdev = adapter->pdev;
152 ring->dev = &adapter->pdev->dev;
153 ring->netdev = adapter->netdev;
154 ring->napi = &adapter->ena_napi[qid].napi;
155 ring->adapter = adapter;
156 ring->ena_dev = adapter->ena_dev;
157 ring->per_napi_packets = 0;
158 ring->per_napi_bytes = 0;
159 ring->cpu = 0;
160 u64_stats_init(&ring->syncp);
161}
162
163static void ena_init_io_rings(struct ena_adapter *adapter)
164{
165 struct ena_com_dev *ena_dev;
166 struct ena_ring *txr, *rxr;
167 int i;
168
169 ena_dev = adapter->ena_dev;
170
171 for (i = 0; i < adapter->num_queues; i++) {
172 txr = &adapter->tx_ring[i];
173 rxr = &adapter->rx_ring[i];
174
175 /* TX/RX common ring state */
176 ena_init_io_rings_common(adapter, txr, i);
177 ena_init_io_rings_common(adapter, rxr, i);
178
179 /* TX specific ring state */
180 txr->ring_size = adapter->tx_ring_size;
181 txr->tx_max_header_size = ena_dev->tx_max_header_size;
182 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
183 txr->sgl_size = adapter->max_tx_sgl_size;
184 txr->smoothed_interval =
185 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
186
187 /* RX specific ring state */
188 rxr->ring_size = adapter->rx_ring_size;
189 rxr->rx_copybreak = adapter->rx_copybreak;
190 rxr->sgl_size = adapter->max_rx_sgl_size;
191 rxr->smoothed_interval =
192 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
d09b6090 193 rxr->empty_rx_queue = 0;
1738cd3e
NB		 194 }
195}
196
197/* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
198 * @adapter: network interface device structure
199 * @qid: queue index
200 *
201 * Return 0 on success, negative on failure
202 */
203static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
204{
205 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
206 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
207 int size, i, node;
208
209 if (tx_ring->tx_buffer_info) {
210 netif_err(adapter, ifup,
211 adapter->netdev, "tx_buffer_info info is not NULL");
212 return -EEXIST;
213 }
214
215 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
216 node = cpu_to_node(ena_irq->cpu);
217
218 tx_ring->tx_buffer_info = vzalloc_node(size, node);
219 if (!tx_ring->tx_buffer_info) {
220 tx_ring->tx_buffer_info = vzalloc(size);
221 if (!tx_ring->tx_buffer_info)
222 return -ENOMEM;
223 }
224
225 size = sizeof(u16) * tx_ring->ring_size;
226 tx_ring->free_tx_ids = vzalloc_node(size, node);
227 if (!tx_ring->free_tx_ids) {
228 tx_ring->free_tx_ids = vzalloc(size);
229 if (!tx_ring->free_tx_ids) {
230 vfree(tx_ring->tx_buffer_info);
231 return -ENOMEM;
232 }
233 }
234
235 /* Req id ring for TX out of order completions */
236 for (i = 0; i < tx_ring->ring_size; i++)
237 tx_ring->free_tx_ids[i] = i;
238
239 /* Reset tx statistics */
240 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
241
242 tx_ring->next_to_use = 0;
243 tx_ring->next_to_clean = 0;
244 tx_ring->cpu = ena_irq->cpu;
245 return 0;
246}
247
248/* ena_free_tx_resources - Free I/O Tx Resources per Queue
249 * @adapter: network interface device structure
250 * @qid: queue index
251 *
252 * Free all transmit software resources
253 */
254static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
255{
256 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
257
258 vfree(tx_ring->tx_buffer_info);
259 tx_ring->tx_buffer_info = NULL;
260
261 vfree(tx_ring->free_tx_ids);
262 tx_ring->free_tx_ids = NULL;
263}
264
265/* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
266 * @adapter: private structure
267 *
268 * Return 0 on success, negative on failure
269 */
270static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
271{
272 int i, rc = 0;
273
274 for (i = 0; i < adapter->num_queues; i++) {
275 rc = ena_setup_tx_resources(adapter, i);
276 if (rc)
277 goto err_setup_tx;
278 }
279
280 return 0;
281
282err_setup_tx:
283
284 netif_err(adapter, ifup, adapter->netdev,
285 "Tx queue %d: allocation failed\n", i);
286
287 /* rewind the index freeing the rings as we go */
288 while (i--)
289 ena_free_tx_resources(adapter, i);
290 return rc;
291}
292
293/* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
294 * @adapter: board private structure
295 *
296 * Free all transmit software resources
297 */
298static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
299{
300 int i;
301
302 for (i = 0; i < adapter->num_queues; i++)
303 ena_free_tx_resources(adapter, i);
304}
305
306/* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
307 * @adapter: network interface device structure
308 * @qid: queue index
309 *
310 * Returns 0 on success, negative on failure
311 */
312static int ena_setup_rx_resources(struct ena_adapter *adapter,
313 u32 qid)
314{
315 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
316 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
317 int size, node;
318
319 if (rx_ring->rx_buffer_info) {
320 netif_err(adapter, ifup, adapter->netdev,
321 "rx_buffer_info is not NULL");
322 return -EEXIST;
323 }
324
325 /* alloc extra element so in rx path
326 * we can always prefetch rx_info + 1
327 */
328 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
329 node = cpu_to_node(ena_irq->cpu);
330
331 rx_ring->rx_buffer_info = vzalloc_node(size, node);
332 if (!rx_ring->rx_buffer_info) {
333 rx_ring->rx_buffer_info = vzalloc(size);
334 if (!rx_ring->rx_buffer_info)
335 return -ENOMEM;
336 }
337
338 /* Reset rx statistics */
339 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
340
341 rx_ring->next_to_clean = 0;
342 rx_ring->next_to_use = 0;
343 rx_ring->cpu = ena_irq->cpu;
344
345 return 0;
346}
347
348/* ena_free_rx_resources - Free I/O Rx Resources
349 * @adapter: network interface device structure
350 * @qid: queue index
351 *
352 * Free all receive software resources
353 */
354static void ena_free_rx_resources(struct ena_adapter *adapter,
355 u32 qid)
356{
357 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
358
359 vfree(rx_ring->rx_buffer_info);
360 rx_ring->rx_buffer_info = NULL;
361}
362
363/* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
364 * @adapter: board private structure
365 *
366 * Return 0 on success, negative on failure
367 */
368static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
369{
370 int i, rc = 0;
371
372 for (i = 0; i < adapter->num_queues; i++) {
373 rc = ena_setup_rx_resources(adapter, i);
374 if (rc)
375 goto err_setup_rx;
376 }
377
378 return 0;
379
380err_setup_rx:
381
382 netif_err(adapter, ifup, adapter->netdev,
383 "Rx queue %d: allocation failed\n", i);
384
385 /* rewind the index freeing the rings as we go */
386 while (i--)
387 ena_free_rx_resources(adapter, i);
388 return rc;
389}
390
391/* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
392 * @adapter: board private structure
393 *
394 * Free all receive software resources
395 */
396static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
397{
398 int i;
399
400 for (i = 0; i < adapter->num_queues; i++)
401 ena_free_rx_resources(adapter, i);
402}
403
404static inline int ena_alloc_rx_page(struct ena_ring *rx_ring,
405 struct ena_rx_buffer *rx_info, gfp_t gfp)
406{
407 struct ena_com_buf *ena_buf;
408 struct page *page;
409 dma_addr_t dma;
410
411 /* if previous allocated page is not used */
412 if (unlikely(rx_info->page))
413 return 0;
414
415 page = alloc_page(gfp);
416 if (unlikely(!page)) {
417 u64_stats_update_begin(&rx_ring->syncp);
418 rx_ring->rx_stats.page_alloc_fail++;
419 u64_stats_update_end(&rx_ring->syncp);
420 return -ENOMEM;
421 }
422
423 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE,
424 DMA_FROM_DEVICE);
425 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
426 u64_stats_update_begin(&rx_ring->syncp);
427 rx_ring->rx_stats.dma_mapping_err++;
428 u64_stats_update_end(&rx_ring->syncp);
429
430 __free_page(page);
431 return -EIO;
432 }
433 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
434 "alloc page %p, rx_info %p\n", page, rx_info);
435
436 rx_info->page = page;
437 rx_info->page_offset = 0;
438 ena_buf = &rx_info->ena_buf;
439 ena_buf->paddr = dma;
440 ena_buf->len = PAGE_SIZE;
441
442 return 0;
443}
444
445static void ena_free_rx_page(struct ena_ring *rx_ring,
446 struct ena_rx_buffer *rx_info)
447{
448 struct page *page = rx_info->page;
449 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
450
451 if (unlikely(!page)) {
452 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
453 "Trying to free unallocated buffer\n");
454 return;
455 }
456
457 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE,
458 DMA_FROM_DEVICE);
459
460 __free_page(page);
461 rx_info->page = NULL;
462}
463
464static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
465{
466 u16 next_to_use;
467 u32 i;
468 int rc;
469
470 next_to_use = rx_ring->next_to_use;
471
472 for (i = 0; i < num; i++) {
473 struct ena_rx_buffer *rx_info =
474 &rx_ring->rx_buffer_info[next_to_use];
475
476 rc = ena_alloc_rx_page(rx_ring, rx_info,
477 __GFP_COLD | GFP_ATOMIC | __GFP_COMP);
478 if (unlikely(rc < 0)) {
479 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
480 "failed to alloc buffer for rx queue %d\n",
481 rx_ring->qid);
482 break;
483 }
484 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
485 &rx_info->ena_buf,
486 next_to_use);
487 if (unlikely(rc)) {
488 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
489 "failed to add buffer for rx queue %d\n",
490 rx_ring->qid);
491 break;
492 }
493 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
494 rx_ring->ring_size);
495 }
496
497 if (unlikely(i < num)) {
498 u64_stats_update_begin(&rx_ring->syncp);
499 rx_ring->rx_stats.refil_partial++;
500 u64_stats_update_end(&rx_ring->syncp);
501 netdev_warn(rx_ring->netdev,
502 "refilled rx qid %d with only %d buffers (from %d)\n",
503 rx_ring->qid, i, num);
504 }
505
506 if (likely(i)) {
507 /* Add memory barrier to make sure the desc were written before
508 * issue a doorbell
509 */
510 wmb();
511 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
512 }
513
514 rx_ring->next_to_use = next_to_use;
515
516 return i;
517}
518
519static void ena_free_rx_bufs(struct ena_adapter *adapter,
520 u32 qid)
521{
522 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
523 u32 i;
524
525 for (i = 0; i < rx_ring->ring_size; i++) {
526 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
527
528 if (rx_info->page)
529 ena_free_rx_page(rx_ring, rx_info);
530 }
531}
532
533/* ena_refill_all_rx_bufs - allocate all queues Rx buffers
534 * @adapter: board private structure
535 *
536 */
537static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
538{
539 struct ena_ring *rx_ring;
540 int i, rc, bufs_num;
541
542 for (i = 0; i < adapter->num_queues; i++) {
543 rx_ring = &adapter->rx_ring[i];
544 bufs_num = rx_ring->ring_size - 1;
545 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
546
547 if (unlikely(rc != bufs_num))
548 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
549 "refilling Queue %d failed. allocated %d buffers from: %d\n",
550 i, rc, bufs_num);
551 }
552}
553
554static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
555{
556 int i;
557
558 for (i = 0; i < adapter->num_queues; i++)
559 ena_free_rx_bufs(adapter, i);
560}
561
562/* ena_free_tx_bufs - Free Tx Buffers per Queue
563 * @tx_ring: TX ring for which buffers be freed
564 */
565static void ena_free_tx_bufs(struct ena_ring *tx_ring)
566{
11a2f0ed 567 bool print_once = true;
1738cd3e
NB		 568 u32 i;
569
570 for (i = 0; i < tx_ring->ring_size; i++) {
571 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
572 struct ena_com_buf *ena_buf;
573 int nr_frags;
574 int j;
575
576 if (!tx_info->skb)
577 continue;
578
11a2f0ed
NB		 579 if (print_once) {
580 netdev_notice(tx_ring->netdev,
581 "free uncompleted tx skb qid %d idx 0x%x\n",
582 tx_ring->qid, i);
583 print_once = false;
584 } else {
585 netdev_dbg(tx_ring->netdev,
586 "free uncompleted tx skb qid %d idx 0x%x\n",
587 tx_ring->qid, i);
588 }
1738cd3e
NB		 589
590 ena_buf = tx_info->bufs;
591 dma_unmap_single(tx_ring->dev,
592 ena_buf->paddr,
593 ena_buf->len,
594 DMA_TO_DEVICE);
595
596 /* unmap remaining mapped pages */
597 nr_frags = tx_info->num_of_bufs - 1;
598 for (j = 0; j < nr_frags; j++) {
599 ena_buf++;
600 dma_unmap_page(tx_ring->dev,
601 ena_buf->paddr,
602 ena_buf->len,
603 DMA_TO_DEVICE);
604 }
605
606 dev_kfree_skb_any(tx_info->skb);
607 }
608 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
609 tx_ring->qid));
610}
611
612static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
613{
614 struct ena_ring *tx_ring;
615 int i;
616
617 for (i = 0; i < adapter->num_queues; i++) {
618 tx_ring = &adapter->tx_ring[i];
619 ena_free_tx_bufs(tx_ring);
620 }
621}
622
623static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
624{
625 u16 ena_qid;
626 int i;
627
628 for (i = 0; i < adapter->num_queues; i++) {
629 ena_qid = ENA_IO_TXQ_IDX(i);
630 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
631 }
632}
633
634static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
635{
636 u16 ena_qid;
637 int i;
638
639 for (i = 0; i < adapter->num_queues; i++) {
640 ena_qid = ENA_IO_RXQ_IDX(i);
641 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
642 }
643}
644
645static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
646{
647 ena_destroy_all_tx_queues(adapter);
648 ena_destroy_all_rx_queues(adapter);
649}
650
651static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
652{
653 struct ena_tx_buffer *tx_info = NULL;
654
655 if (likely(req_id < tx_ring->ring_size)) {
656 tx_info = &tx_ring->tx_buffer_info[req_id];
657 if (likely(tx_info->skb))
658 return 0;
659 }
660
661 if (tx_info)
662 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
663 "tx_info doesn't have valid skb\n");
664 else
665 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
666 "Invalid req_id: %hu\n", req_id);
667
668 u64_stats_update_begin(&tx_ring->syncp);
669 tx_ring->tx_stats.bad_req_id++;
670 u64_stats_update_end(&tx_ring->syncp);
671
672 /* Trigger device reset */
673 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
674 return -EFAULT;
675}
676
677static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
678{
679 struct netdev_queue *txq;
680 bool above_thresh;
681 u32 tx_bytes = 0;
682 u32 total_done = 0;
683 u16 next_to_clean;
684 u16 req_id;
685 int tx_pkts = 0;
686 int rc;
687
688 next_to_clean = tx_ring->next_to_clean;
689 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
690
691 while (tx_pkts < budget) {
692 struct ena_tx_buffer *tx_info;
693 struct sk_buff *skb;
694 struct ena_com_buf *ena_buf;
695 int i, nr_frags;
696
697 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
698 &req_id);
699 if (rc)
700 break;
701
702 rc = validate_tx_req_id(tx_ring, req_id);
703 if (rc)
704 break;
705
706 tx_info = &tx_ring->tx_buffer_info[req_id];
707 skb = tx_info->skb;
708
709 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
710 prefetch(&skb->end);
711
712 tx_info->skb = NULL;
713 tx_info->last_jiffies = 0;
714
715 if (likely(tx_info->num_of_bufs != 0)) {
716 ena_buf = tx_info->bufs;
717
718 dma_unmap_single(tx_ring->dev,
719 dma_unmap_addr(ena_buf, paddr),
720 dma_unmap_len(ena_buf, len),
721 DMA_TO_DEVICE);
722
723 /* unmap remaining mapped pages */
724 nr_frags = tx_info->num_of_bufs - 1;
725 for (i = 0; i < nr_frags; i++) {
726 ena_buf++;
727 dma_unmap_page(tx_ring->dev,
728 dma_unmap_addr(ena_buf, paddr),
729 dma_unmap_len(ena_buf, len),
730 DMA_TO_DEVICE);
731 }
732 }
733
734 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
735 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
736 skb);
737
738 tx_bytes += skb->len;
739 dev_kfree_skb(skb);
740 tx_pkts++;
741 total_done += tx_info->tx_descs;
742
743 tx_ring->free_tx_ids[next_to_clean] = req_id;
744 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
745 tx_ring->ring_size);
746 }
747
748 tx_ring->next_to_clean = next_to_clean;
749 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
750 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
751
752 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
753
754 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
755 "tx_poll: q %d done. total pkts: %d\n",
756 tx_ring->qid, tx_pkts);
757
758 /* need to make the rings circular update visible to
759 * ena_start_xmit() before checking for netif_queue_stopped().
760 */
761 smp_mb();
762
763 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
764 ENA_TX_WAKEUP_THRESH;
765 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
766 __netif_tx_lock(txq, smp_processor_id());
767 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
768 ENA_TX_WAKEUP_THRESH;
769 if (netif_tx_queue_stopped(txq) && above_thresh) {
770 netif_tx_wake_queue(txq);
771 u64_stats_update_begin(&tx_ring->syncp);
772 tx_ring->tx_stats.queue_wakeup++;
773 u64_stats_update_end(&tx_ring->syncp);
774 }
775 __netif_tx_unlock(txq);
776 }
777
778 tx_ring->per_napi_bytes += tx_bytes;
779 tx_ring->per_napi_packets += tx_pkts;
780
781 return tx_pkts;
782}
783
784static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
785 struct ena_com_rx_buf_info *ena_bufs,
786 u32 descs,
787 u16 *next_to_clean)
788{
789 struct sk_buff *skb;
790 struct ena_rx_buffer *rx_info =
791 &rx_ring->rx_buffer_info[*next_to_clean];
792 u32 len;
793 u32 buf = 0;
794 void *va;
795
796 len = ena_bufs[0].len;
797 if (unlikely(!rx_info->page)) {
798 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
799 "Page is NULL\n");
800 return NULL;
801 }
802
803 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
804 "rx_info %p page %p\n",
805 rx_info, rx_info->page);
806
807 /* save virt address of first buffer */
808 va = page_address(rx_info->page) + rx_info->page_offset;
809 prefetch(va + NET_IP_ALIGN);
810
811 if (len <= rx_ring->rx_copybreak) {
812 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
813 rx_ring->rx_copybreak);
814 if (unlikely(!skb)) {
815 u64_stats_update_begin(&rx_ring->syncp);
816 rx_ring->rx_stats.skb_alloc_fail++;
817 u64_stats_update_end(&rx_ring->syncp);
818 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
819 "Failed to allocate skb\n");
820 return NULL;
821 }
822
823 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
824 "rx allocated small packet. len %d. data_len %d\n",
825 skb->len, skb->data_len);
826
827 /* sync this buffer for CPU use */
828 dma_sync_single_for_cpu(rx_ring->dev,
829 dma_unmap_addr(&rx_info->ena_buf, paddr),
830 len,
831 DMA_FROM_DEVICE);
832 skb_copy_to_linear_data(skb, va, len);
833 dma_sync_single_for_device(rx_ring->dev,
834 dma_unmap_addr(&rx_info->ena_buf, paddr),
835 len,
836 DMA_FROM_DEVICE);
837
838 skb_put(skb, len);
839 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
840 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
841 rx_ring->ring_size);
842 return skb;
843 }
844
845 skb = napi_get_frags(rx_ring->napi);
846 if (unlikely(!skb)) {
847 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
848 "Failed allocating skb\n");
849 u64_stats_update_begin(&rx_ring->syncp);
850 rx_ring->rx_stats.skb_alloc_fail++;
851 u64_stats_update_end(&rx_ring->syncp);
852 return NULL;
853 }
854
855 do {
856 dma_unmap_page(rx_ring->dev,
857 dma_unmap_addr(&rx_info->ena_buf, paddr),
858 PAGE_SIZE, DMA_FROM_DEVICE);
859
860 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
861 rx_info->page_offset, len, PAGE_SIZE);
862
863 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
864 "rx skb updated. len %d. data_len %d\n",
865 skb->len, skb->data_len);
866
867 rx_info->page = NULL;
868 *next_to_clean =
869 ENA_RX_RING_IDX_NEXT(*next_to_clean,
870 rx_ring->ring_size);
871 if (likely(--descs == 0))
872 break;
873 rx_info = &rx_ring->rx_buffer_info[*next_to_clean];
874 len = ena_bufs[++buf].len;
875 } while (1);
876
877 return skb;
878}
879
880/* ena_rx_checksum - indicate in skb if hw indicated a good cksum
881 * @adapter: structure containing adapter specific data
882 * @ena_rx_ctx: received packet context/metadata
883 * @skb: skb currently being received and modified
884 */
885static inline void ena_rx_checksum(struct ena_ring *rx_ring,
886 struct ena_com_rx_ctx *ena_rx_ctx,
887 struct sk_buff *skb)
888{
889 /* Rx csum disabled */
890 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
891 skb->ip_summed = CHECKSUM_NONE;
892 return;
893 }
894
895 /* For fragmented packets the checksum isn't valid */
896 if (ena_rx_ctx->frag) {
897 skb->ip_summed = CHECKSUM_NONE;
898 return;
899 }
900
901 /* if IP and error */
902 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
903 (ena_rx_ctx->l3_csum_err))) {
904 /* ipv4 checksum error */
905 skb->ip_summed = CHECKSUM_NONE;
906 u64_stats_update_begin(&rx_ring->syncp);
907 rx_ring->rx_stats.bad_csum++;
908 u64_stats_update_end(&rx_ring->syncp);
909 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
910 "RX IPv4 header checksum error\n");
911 return;
912 }
913
914 /* if TCP/UDP */
915 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
916 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
917 if (unlikely(ena_rx_ctx->l4_csum_err)) {
918 /* TCP/UDP checksum error */
919 u64_stats_update_begin(&rx_ring->syncp);
920 rx_ring->rx_stats.bad_csum++;
921 u64_stats_update_end(&rx_ring->syncp);
922 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
923 "RX L4 checksum error\n");
924 skb->ip_summed = CHECKSUM_NONE;
925 return;
926 }
927
928 skb->ip_summed = CHECKSUM_UNNECESSARY;
929 }
930}
931
932static void ena_set_rx_hash(struct ena_ring *rx_ring,
933 struct ena_com_rx_ctx *ena_rx_ctx,
934 struct sk_buff *skb)
935{
936 enum pkt_hash_types hash_type;
937
938 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
939 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
940 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
941
942 hash_type = PKT_HASH_TYPE_L4;
943 else
944 hash_type = PKT_HASH_TYPE_NONE;
945
946 /* Override hash type if the packet is fragmented */
947 if (ena_rx_ctx->frag)
948 hash_type = PKT_HASH_TYPE_NONE;
949
950 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
951 }
952}
953
954/* ena_clean_rx_irq - Cleanup RX irq
955 * @rx_ring: RX ring to clean
956 * @napi: napi handler
957 * @budget: how many packets driver is allowed to clean
958 *
959 * Returns the number of cleaned buffers.
960 */
961static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
962 u32 budget)
963{
964 u16 next_to_clean = rx_ring->next_to_clean;
965 u32 res_budget, work_done;
966
967 struct ena_com_rx_ctx ena_rx_ctx;
968 struct ena_adapter *adapter;
969 struct sk_buff *skb;
970 int refill_required;
971 int refill_threshold;
972 int rc = 0;
973 int total_len = 0;
974 int rx_copybreak_pkt = 0;
975
976 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
977 "%s qid %d\n", __func__, rx_ring->qid);
978 res_budget = budget;
979
980 do {
981 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
982 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
983 ena_rx_ctx.descs = 0;
984 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
985 rx_ring->ena_com_io_sq,
986 &ena_rx_ctx);
987 if (unlikely(rc))
988 goto error;
989
990 if (unlikely(ena_rx_ctx.descs == 0))
991 break;
992
993 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
994 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
995 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
996 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
997
998 /* allocate skb and fill it */
999 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
1000 &next_to_clean);
1001
1002 /* exit if we failed to retrieve a buffer */
1003 if (unlikely(!skb)) {
1004 next_to_clean = ENA_RX_RING_IDX_ADD(next_to_clean,
1005 ena_rx_ctx.descs,
1006 rx_ring->ring_size);
1007 break;
1008 }
1009
1010 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1011
1012 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1013
1014 skb_record_rx_queue(skb, rx_ring->qid);
1015
1016 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1017 total_len += rx_ring->ena_bufs[0].len;
1018 rx_copybreak_pkt++;
1019 napi_gro_receive(napi, skb);
1020 } else {
1021 total_len += skb->len;
1022 napi_gro_frags(napi);
1023 }
1024
1025 res_budget--;
1026 } while (likely(res_budget));
1027
1028 work_done = budget - res_budget;
1029 rx_ring->per_napi_bytes += total_len;
1030 rx_ring->per_napi_packets += work_done;
1031 u64_stats_update_begin(&rx_ring->syncp);
1032 rx_ring->rx_stats.bytes += total_len;
1033 rx_ring->rx_stats.cnt += work_done;
1034 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1035 u64_stats_update_end(&rx_ring->syncp);
1036
1037 rx_ring->next_to_clean = next_to_clean;
1038
1039 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
1040 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
1041
1042 /* Optimization, try to batch new rx buffers */
1043 if (refill_required > refill_threshold) {
1044 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1045 ena_refill_rx_bufs(rx_ring, refill_required);
1046 }
1047
1048 return work_done;
1049
1050error:
1051 adapter = netdev_priv(rx_ring->netdev);
1052
1053 u64_stats_update_begin(&rx_ring->syncp);
1054 rx_ring->rx_stats.bad_desc_num++;
1055 u64_stats_update_end(&rx_ring->syncp);
1056
1057 /* Too many desc from the device. Trigger reset */
1058 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1059
1060 return 0;
1061}
1062
1063inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring,
1064 struct ena_ring *tx_ring)
1065{
1066 /* We apply adaptive moderation on Rx path only.
1067 * Tx uses static interrupt moderation.
1068 */
1069 ena_com_calculate_interrupt_delay(rx_ring->ena_dev,
1070 rx_ring->per_napi_packets,
1071 rx_ring->per_napi_bytes,
1072 &rx_ring->smoothed_interval,
1073 &rx_ring->moder_tbl_idx);
1074
1075 /* Reset per napi packets/bytes */
1076 tx_ring->per_napi_packets = 0;
1077 tx_ring->per_napi_bytes = 0;
1078 rx_ring->per_napi_packets = 0;
1079 rx_ring->per_napi_bytes = 0;
1080}
1081
77f27aaa
NB		 1082static inline void ena_unmask_interrupt(struct ena_ring *tx_ring,
1083 struct ena_ring *rx_ring)
1084{
1085 struct ena_eth_io_intr_reg intr_reg;
1086
1087 /* Update intr register: rx intr delay,
1088 * tx intr delay and interrupt unmask
1089 */
1090 ena_com_update_intr_reg(&intr_reg,
1091 rx_ring->smoothed_interval,
1092 tx_ring->smoothed_interval,
1093 true);
1094
1095 /* It is a shared MSI-X.
1096 * Tx and Rx CQ have pointer to it.
1097 * So we use one of them to reach the intr reg
1098 */
1099 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1100}
1101
1738cd3e
NB		 1102static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1103 struct ena_ring *rx_ring)
1104{
1105 int cpu = get_cpu();
1106 int numa_node;
1107
1108 /* Check only one ring since the 2 rings are running on the same cpu */
1109 if (likely(tx_ring->cpu == cpu))
1110 goto out;
1111
1112 numa_node = cpu_to_node(cpu);
1113 put_cpu();
1114
1115 if (numa_node != NUMA_NO_NODE) {
1116 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1117 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1118 }
1119
1120 tx_ring->cpu = cpu;
1121 rx_ring->cpu = cpu;
1122
1123 return;
1124out:
1125 put_cpu();
1126}
1127
1128static int ena_io_poll(struct napi_struct *napi, int budget)
1129{
1130 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1131 struct ena_ring *tx_ring, *rx_ring;
1738cd3e
NB		 1132
1133 u32 tx_work_done;
1134 u32 rx_work_done;
1135 int tx_budget;
1136 int napi_comp_call = 0;
1137 int ret;
1138
1139 tx_ring = ena_napi->tx_ring;
1140 rx_ring = ena_napi->rx_ring;
1141
1142 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1143
d5796182
NB		 1144 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1145 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1738cd3e
NB		 1146 napi_complete_done(napi, 0);
1147 return 0;
1148 }
1149
1150 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1151 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1152
e9b1d2a8
NB		 1153 /* If the device is about to reset or down, avoid unmask
1154 * the interrupt and return 0 so NAPI won't reschedule
1155 */
1156 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1157 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1158 napi_complete_done(napi, 0);
1159 ret = 0;
1738cd3e 1160
e9b1d2a8 1161 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1738cd3e 1162 napi_comp_call = 1;
1738cd3e 1163
e9b1d2a8
NB		 1164 /* Update numa and unmask the interrupt only when schedule
1165 * from the interrupt context (vs from sk_busy_loop)
1738cd3e 1166 */
e9b1d2a8
NB		 1167 if (napi_complete_done(napi, rx_work_done)) {
1168 /* Tx and Rx share the same interrupt vector */
1169 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1170 ena_adjust_intr_moderation(rx_ring, tx_ring);
1171
77f27aaa 1172 ena_unmask_interrupt(tx_ring, rx_ring);
e9b1d2a8 1173 }
1738cd3e 1174
1738cd3e
NB		 1175 ena_update_ring_numa_node(tx_ring, rx_ring);
1176
1177 ret = rx_work_done;
1178 } else {
1179 ret = budget;
1180 }
1181
1182 u64_stats_update_begin(&tx_ring->syncp);
1183 tx_ring->tx_stats.napi_comp += napi_comp_call;
1184 tx_ring->tx_stats.tx_poll++;
1185 u64_stats_update_end(&tx_ring->syncp);
1186
1187 return ret;
1188}
1189
1190static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1191{
1192 struct ena_adapter *adapter = (struct ena_adapter *)data;
1193
1194 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1195
1196 /* Don't call the aenq handler before probe is done */
1197 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1198 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1199
1200 return IRQ_HANDLED;
1201}
1202
1203/* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1204 * @irq: interrupt number
1205 * @data: pointer to a network interface private napi device structure
1206 */
1207static irqreturn_t ena_intr_msix_io(int irq, void *data)
1208{
1209 struct ena_napi *ena_napi = data;
1210
1211 napi_schedule(&ena_napi->napi);
1212
1213 return IRQ_HANDLED;
1214}
1215
1216static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1217{
e328a031 1218 int msix_vecs, rc;
1738cd3e
NB		 1219
1220 /* Reserved the max msix vectors we might need */
1221 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1222
1223 netif_dbg(adapter, probe, adapter->netdev,
1224 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1225
e328a031
CH		 1226 rc = pci_alloc_irq_vectors(adapter->pdev, msix_vecs, msix_vecs,
1227 PCI_IRQ_MSIX);
1228 if (rc < 0) {
1738cd3e
NB		 1229 netif_err(adapter, probe, adapter->netdev,
1230 "Failed to enable MSI-X, vectors %d rc %d\n",
1231 msix_vecs, rc);
1232 return -ENOSPC;
1233 }
1234
1235 netif_dbg(adapter, probe, adapter->netdev, "enable MSI-X, vectors %d\n",
1236 msix_vecs);
1237
1238 if (msix_vecs >= 1) {
1239 if (ena_init_rx_cpu_rmap(adapter))
1240 netif_warn(adapter, probe, adapter->netdev,
1241 "Failed to map IRQs to CPUs\n");
1242 }
1243
1244 adapter->msix_vecs = msix_vecs;
1738cd3e
NB		 1245
1246 return 0;
1247}
1248
1249static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1250{
1251 u32 cpu;
1252
1253 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1254 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1255 pci_name(adapter->pdev));
1256 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1257 ena_intr_msix_mgmnt;
1258 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1259 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
e328a031 1260 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1738cd3e
NB		 1261 cpu = cpumask_first(cpu_online_mask);
1262 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1263 cpumask_set_cpu(cpu,
1264 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1265}
1266
1267static void ena_setup_io_intr(struct ena_adapter *adapter)
1268{
1269 struct net_device *netdev;
1270 int irq_idx, i, cpu;
1271
1272 netdev = adapter->netdev;
1273
1274 for (i = 0; i < adapter->num_queues; i++) {
1275 irq_idx = ENA_IO_IRQ_IDX(i);
1276 cpu = i % num_online_cpus();
1277
1278 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1279 "%s-Tx-Rx-%d", netdev->name, i);
1280 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1281 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1282 adapter->irq_tbl[irq_idx].vector =
e328a031 1283 pci_irq_vector(adapter->pdev, irq_idx);
1738cd3e
NB		 1284 adapter->irq_tbl[irq_idx].cpu = cpu;
1285
1286 cpumask_set_cpu(cpu,
1287 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1288 }
1289}
1290
1291static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1292{
1293 unsigned long flags = 0;
1294 struct ena_irq *irq;
1295 int rc;
1296
1297 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1298 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1299 irq->data);
1300 if (rc) {
1301 netif_err(adapter, probe, adapter->netdev,
1302 "failed to request admin irq\n");
1303 return rc;
1304 }
1305
1306 netif_dbg(adapter, probe, adapter->netdev,
1307 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1308 irq->affinity_hint_mask.bits[0], irq->vector);
1309
1310 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1311
1312 return rc;
1313}
1314
1315static int ena_request_io_irq(struct ena_adapter *adapter)
1316{
1317 unsigned long flags = 0;
1318 struct ena_irq *irq;
1319 int rc = 0, i, k;
1320
1738cd3e
NB		 1321 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1322 irq = &adapter->irq_tbl[i];
1323 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1324 irq->data);
1325 if (rc) {
1326 netif_err(adapter, ifup, adapter->netdev,
1327 "Failed to request I/O IRQ. index %d rc %d\n",
1328 i, rc);
1329 goto err;
1330 }
1331
1332 netif_dbg(adapter, ifup, adapter->netdev,
1333 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1334 i, irq->affinity_hint_mask.bits[0], irq->vector);
1335
1336 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1337 }
1338
1339 return rc;
1340
1341err:
1342 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1343 irq = &adapter->irq_tbl[k];
1344 free_irq(irq->vector, irq->data);
1345 }
1346
1347 return rc;
1348}
1349
1350static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1351{
1352 struct ena_irq *irq;
1353
1354 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1355 synchronize_irq(irq->vector);
1356 irq_set_affinity_hint(irq->vector, NULL);
1357 free_irq(irq->vector, irq->data);
1358}
1359
1360static void ena_free_io_irq(struct ena_adapter *adapter)
1361{
1362 struct ena_irq *irq;
1363 int i;
1364
1365#ifdef CONFIG_RFS_ACCEL
1366 if (adapter->msix_vecs >= 1) {
1367 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1368 adapter->netdev->rx_cpu_rmap = NULL;
1369 }
1370#endif /* CONFIG_RFS_ACCEL */
1371
1372 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1373 irq = &adapter->irq_tbl[i];
1374 irq_set_affinity_hint(irq->vector, NULL);
1375 free_irq(irq->vector, irq->data);
1376 }
1377}
1378
1738cd3e
NB		 1379static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1380{
1381 int i;
1382
1383 if (!netif_running(adapter->netdev))
1384 return;
1385
1386 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1387 synchronize_irq(adapter->irq_tbl[i].vector);
1388}
1389
1390static void ena_del_napi(struct ena_adapter *adapter)
1391{
1392 int i;
1393
1394 for (i = 0; i < adapter->num_queues; i++)
1395 netif_napi_del(&adapter->ena_napi[i].napi);
1396}
1397
1398static void ena_init_napi(struct ena_adapter *adapter)
1399{
1400 struct ena_napi *napi;
1401 int i;
1402
1403 for (i = 0; i < adapter->num_queues; i++) {
1404 napi = &adapter->ena_napi[i];
1405
1406 netif_napi_add(adapter->netdev,
1407 &adapter->ena_napi[i].napi,
1408 ena_io_poll,
1409 ENA_NAPI_BUDGET);
1410 napi->rx_ring = &adapter->rx_ring[i];
1411 napi->tx_ring = &adapter->tx_ring[i];
1412 napi->qid = i;
1413 }
1414}
1415
1416static void ena_napi_disable_all(struct ena_adapter *adapter)
1417{
1418 int i;
1419
1420 for (i = 0; i < adapter->num_queues; i++)
1421 napi_disable(&adapter->ena_napi[i].napi);
1422}
1423
1424static void ena_napi_enable_all(struct ena_adapter *adapter)
1425{
1426 int i;
1427
1428 for (i = 0; i < adapter->num_queues; i++)
1429 napi_enable(&adapter->ena_napi[i].napi);
1430}
1431
1432static void ena_restore_ethtool_params(struct ena_adapter *adapter)
1433{
1434 adapter->tx_usecs = 0;
1435 adapter->rx_usecs = 0;
1436 adapter->tx_frames = 1;
1437 adapter->rx_frames = 1;
1438}
1439
1440/* Configure the Rx forwarding */
1441static int ena_rss_configure(struct ena_adapter *adapter)
1442{
1443 struct ena_com_dev *ena_dev = adapter->ena_dev;
1444 int rc;
1445
1446 /* In case the RSS table wasn't initialized by probe */
1447 if (!ena_dev->rss.tbl_log_size) {
1448 rc = ena_rss_init_default(adapter);
1449 if (rc && (rc != -EPERM)) {
1450 netif_err(adapter, ifup, adapter->netdev,
1451 "Failed to init RSS rc: %d\n", rc);
1452 return rc;
1453 }
1454 }
1455
1456 /* Set indirect table */
1457 rc = ena_com_indirect_table_set(ena_dev);
1458 if (unlikely(rc && rc != -EPERM))
1459 return rc;
1460
1461 /* Configure hash function (if supported) */
1462 rc = ena_com_set_hash_function(ena_dev);
1463 if (unlikely(rc && (rc != -EPERM)))
1464 return rc;
1465
1466 /* Configure hash inputs (if supported) */
1467 rc = ena_com_set_hash_ctrl(ena_dev);
1468 if (unlikely(rc && (rc != -EPERM)))
1469 return rc;
1470
1471 return 0;
1472}
1473
1474static int ena_up_complete(struct ena_adapter *adapter)
1475{
1476 int rc, i;
1477
1478 rc = ena_rss_configure(adapter);
1479 if (rc)
1480 return rc;
1481
1482 ena_init_napi(adapter);
1483
1484 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1485
1486 ena_refill_all_rx_bufs(adapter);
1487
1488 /* enable transmits */
1489 netif_tx_start_all_queues(adapter->netdev);
1490
1491 ena_restore_ethtool_params(adapter);
1492
1493 ena_napi_enable_all(adapter);
1494
77f27aaa
NB		 1495 /* Enable completion queues interrupt */
1496 for (i = 0; i < adapter->num_queues; i++)
1497 ena_unmask_interrupt(&adapter->tx_ring[i],
1498 &adapter->rx_ring[i]);
1499
1738cd3e
NB		 1500 /* schedule napi in case we had pending packets
1501 * from the last time we disable napi
1502 */
1503 for (i = 0; i < adapter->num_queues; i++)
1504 napi_schedule(&adapter->ena_napi[i].napi);
1505
1506 return 0;
1507}
1508
1509static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1510{
1511 struct ena_com_create_io_ctx ctx = { 0 };
1512 struct ena_com_dev *ena_dev;
1513 struct ena_ring *tx_ring;
1514 u32 msix_vector;
1515 u16 ena_qid;
1516 int rc;
1517
1518 ena_dev = adapter->ena_dev;
1519
1520 tx_ring = &adapter->tx_ring[qid];
1521 msix_vector = ENA_IO_IRQ_IDX(qid);
1522 ena_qid = ENA_IO_TXQ_IDX(qid);
1523
1524 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1525 ctx.qid = ena_qid;
1526 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1527 ctx.msix_vector = msix_vector;
1528 ctx.queue_size = adapter->tx_ring_size;
1529 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1530
1531 rc = ena_com_create_io_queue(ena_dev, &ctx);
1532 if (rc) {
1533 netif_err(adapter, ifup, adapter->netdev,
1534 "Failed to create I/O TX queue num %d rc: %d\n",
1535 qid, rc);
1536 return rc;
1537 }
1538
1539 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1540 &tx_ring->ena_com_io_sq,
1541 &tx_ring->ena_com_io_cq);
1542 if (rc) {
1543 netif_err(adapter, ifup, adapter->netdev,
1544 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1545 qid, rc);
1546 ena_com_destroy_io_queue(ena_dev, ena_qid);
50b95fe7 1547 return rc;
1738cd3e
NB		 1548 }
1549
1550 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1551 return rc;
1552}
1553
1554static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1555{
1556 struct ena_com_dev *ena_dev = adapter->ena_dev;
1557 int rc, i;
1558
1559 for (i = 0; i < adapter->num_queues; i++) {
1560 rc = ena_create_io_tx_queue(adapter, i);
1561 if (rc)
1562 goto create_err;
1563 }
1564
1565 return 0;
1566
1567create_err:
1568 while (i--)
1569 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1570
1571 return rc;
1572}
1573
1574static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1575{
1576 struct ena_com_dev *ena_dev;
1577 struct ena_com_create_io_ctx ctx = { 0 };
1578 struct ena_ring *rx_ring;
1579 u32 msix_vector;
1580 u16 ena_qid;
1581 int rc;
1582
1583 ena_dev = adapter->ena_dev;
1584
1585 rx_ring = &adapter->rx_ring[qid];
1586 msix_vector = ENA_IO_IRQ_IDX(qid);
1587 ena_qid = ENA_IO_RXQ_IDX(qid);
1588
1589 ctx.qid = ena_qid;
1590 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1591 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1592 ctx.msix_vector = msix_vector;
1593 ctx.queue_size = adapter->rx_ring_size;
1594 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1595
1596 rc = ena_com_create_io_queue(ena_dev, &ctx);
1597 if (rc) {
1598 netif_err(adapter, ifup, adapter->netdev,
1599 "Failed to create I/O RX queue num %d rc: %d\n",
1600 qid, rc);
1601 return rc;
1602 }
1603
1604 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1605 &rx_ring->ena_com_io_sq,
1606 &rx_ring->ena_com_io_cq);
1607 if (rc) {
1608 netif_err(adapter, ifup, adapter->netdev,
1609 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1610 qid, rc);
1611 ena_com_destroy_io_queue(ena_dev, ena_qid);
50b95fe7 1612 return rc;
1738cd3e
NB		 1613 }
1614
1615 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1616
1617 return rc;
1618}
1619
1620static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1621{
1622 struct ena_com_dev *ena_dev = adapter->ena_dev;
1623 int rc, i;
1624
1625 for (i = 0; i < adapter->num_queues; i++) {
1626 rc = ena_create_io_rx_queue(adapter, i);
1627 if (rc)
1628 goto create_err;
1629 }
1630
1631 return 0;
1632
1633create_err:
1634 while (i--)
1635 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1636
1637 return rc;
1638}
1639
1640static int ena_up(struct ena_adapter *adapter)
1641{
1642 int rc;
1643
1644 netdev_dbg(adapter->netdev, "%s\n", __func__);
1645
1646 ena_setup_io_intr(adapter);
1647
1648 rc = ena_request_io_irq(adapter);
1649 if (rc)
1650 goto err_req_irq;
1651
1652 /* allocate transmit descriptors */
1653 rc = ena_setup_all_tx_resources(adapter);
1654 if (rc)
1655 goto err_setup_tx;
1656
1657 /* allocate receive descriptors */
1658 rc = ena_setup_all_rx_resources(adapter);
1659 if (rc)
1660 goto err_setup_rx;
1661
1662 /* Create TX queues */
1663 rc = ena_create_all_io_tx_queues(adapter);
1664 if (rc)
1665 goto err_create_tx_queues;
1666
1667 /* Create RX queues */
1668 rc = ena_create_all_io_rx_queues(adapter);
1669 if (rc)
1670 goto err_create_rx_queues;
1671
1672 rc = ena_up_complete(adapter);
1673 if (rc)
1674 goto err_up;
1675
1676 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1677 netif_carrier_on(adapter->netdev);
1678
1679 u64_stats_update_begin(&adapter->syncp);
1680 adapter->dev_stats.interface_up++;
1681 u64_stats_update_end(&adapter->syncp);
1682
1683 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1684
1685 return rc;
1686
1687err_up:
1688 ena_destroy_all_rx_queues(adapter);
1689err_create_rx_queues:
1690 ena_destroy_all_tx_queues(adapter);
1691err_create_tx_queues:
1692 ena_free_all_io_rx_resources(adapter);
1693err_setup_rx:
1694 ena_free_all_io_tx_resources(adapter);
1695err_setup_tx:
1696 ena_free_io_irq(adapter);
1697err_req_irq:
1698
1699 return rc;
1700}
1701
1702static void ena_down(struct ena_adapter *adapter)
1703{
1704 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1705
1706 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1707
1708 u64_stats_update_begin(&adapter->syncp);
1709 adapter->dev_stats.interface_down++;
1710 u64_stats_update_end(&adapter->syncp);
1711
1738cd3e
NB		 1712 netif_carrier_off(adapter->netdev);
1713 netif_tx_disable(adapter->netdev);
1714
d5796182
NB		 1715 /* After this point the napi handler won't enable the tx queue */
1716 ena_napi_disable_all(adapter);
1717
1738cd3e 1718 /* After destroy the queue there won't be any new interrupts */
d5796182
NB		 1719
1720 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1721 int rc;
1722
1723 rc = ena_com_dev_reset(adapter->ena_dev);
1724 if (rc)
1725 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1726 }
1727
1738cd3e
NB		 1728 ena_destroy_all_io_queues(adapter);
1729
1730 ena_disable_io_intr_sync(adapter);
1731 ena_free_io_irq(adapter);
1732 ena_del_napi(adapter);
1733
1734 ena_free_all_tx_bufs(adapter);
1735 ena_free_all_rx_bufs(adapter);
1736 ena_free_all_io_tx_resources(adapter);
1737 ena_free_all_io_rx_resources(adapter);
1738}
1739
1740/* ena_open - Called when a network interface is made active
1741 * @netdev: network interface device structure
1742 *
1743 * Returns 0 on success, negative value on failure
1744 *
1745 * The open entry point is called when a network interface is made
1746 * active by the system (IFF_UP). At this point all resources needed
1747 * for transmit and receive operations are allocated, the interrupt
1748 * handler is registered with the OS, the watchdog timer is started,
1749 * and the stack is notified that the interface is ready.
1750 */
1751static int ena_open(struct net_device *netdev)
1752{
1753 struct ena_adapter *adapter = netdev_priv(netdev);
1754 int rc;
1755
1756 /* Notify the stack of the actual queue counts. */
1757 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1758 if (rc) {
1759 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1760 return rc;
1761 }
1762
1763 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1764 if (rc) {
1765 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1766 return rc;
1767 }
1768
1769 rc = ena_up(adapter);
1770 if (rc)
1771 return rc;
1772
1773 return rc;
1774}
1775
1776/* ena_close - Disables a network interface
1777 * @netdev: network interface device structure
1778 *
1779 * Returns 0, this is not allowed to fail
1780 *
1781 * The close entry point is called when an interface is de-activated
1782 * by the OS. The hardware is still under the drivers control, but
1783 * needs to be disabled. A global MAC reset is issued to stop the
1784 * hardware, and all transmit and receive resources are freed.
1785 */
1786static int ena_close(struct net_device *netdev)
1787{
1788 struct ena_adapter *adapter = netdev_priv(netdev);
1789
1790 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
1791
1792 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
1793 ena_down(adapter);
1794
1795 return 0;
1796}
1797
1798static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
1799{
1800 u32 mss = skb_shinfo(skb)->gso_size;
1801 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
1802 u8 l4_protocol = 0;
1803
1804 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
1805 ena_tx_ctx->l4_csum_enable = 1;
1806 if (mss) {
1807 ena_tx_ctx->tso_enable = 1;
1808 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
1809 ena_tx_ctx->l4_csum_partial = 0;
1810 } else {
1811 ena_tx_ctx->tso_enable = 0;
1812 ena_meta->l4_hdr_len = 0;
1813 ena_tx_ctx->l4_csum_partial = 1;
1814 }
1815
1816 switch (ip_hdr(skb)->version) {
1817 case IPVERSION:
1818 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
1819 if (ip_hdr(skb)->frag_off & htons(IP_DF))
1820 ena_tx_ctx->df = 1;
1821 if (mss)
1822 ena_tx_ctx->l3_csum_enable = 1;
1823 l4_protocol = ip_hdr(skb)->protocol;
1824 break;
1825 case 6:
1826 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
1827 l4_protocol = ipv6_hdr(skb)->nexthdr;
1828 break;
1829 default:
1830 break;
1831 }
1832
1833 if (l4_protocol == IPPROTO_TCP)
1834 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
1835 else
1836 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
1837
1838 ena_meta->mss = mss;
1839 ena_meta->l3_hdr_len = skb_network_header_len(skb);
1840 ena_meta->l3_hdr_offset = skb_network_offset(skb);
1841 ena_tx_ctx->meta_valid = 1;
1842
1843 } else {
1844 ena_tx_ctx->meta_valid = 0;
1845 }
1846}
1847
1848static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
1849 struct sk_buff *skb)
1850{
1851 int num_frags, header_len, rc;
1852
1853 num_frags = skb_shinfo(skb)->nr_frags;
1854 header_len = skb_headlen(skb);
1855
1856 if (num_frags < tx_ring->sgl_size)
1857 return 0;
1858
1859 if ((num_frags == tx_ring->sgl_size) &&
1860 (header_len < tx_ring->tx_max_header_size))
1861 return 0;
1862
1863 u64_stats_update_begin(&tx_ring->syncp);
1864 tx_ring->tx_stats.linearize++;
1865 u64_stats_update_end(&tx_ring->syncp);
1866
1867 rc = skb_linearize(skb);
1868 if (unlikely(rc)) {
1869 u64_stats_update_begin(&tx_ring->syncp);
1870 tx_ring->tx_stats.linearize_failed++;
1871 u64_stats_update_end(&tx_ring->syncp);
1872 }
1873
1874 return rc;
1875}
1876
1877/* Called with netif_tx_lock. */
1878static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
1879{
1880 struct ena_adapter *adapter = netdev_priv(dev);
1881 struct ena_tx_buffer *tx_info;
1882 struct ena_com_tx_ctx ena_tx_ctx;
1883 struct ena_ring *tx_ring;
1884 struct netdev_queue *txq;
1885 struct ena_com_buf *ena_buf;
1886 void *push_hdr;
1887 u32 len, last_frag;
1888 u16 next_to_use;
1889 u16 req_id;
1890 u16 push_len;
1891 u16 header_len;
1892 dma_addr_t dma;
1893 int qid, rc, nb_hw_desc;
1894 int i = -1;
1895
1896 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
1897 /* Determine which tx ring we will be placed on */
1898 qid = skb_get_queue_mapping(skb);
1899 tx_ring = &adapter->tx_ring[qid];
1900 txq = netdev_get_tx_queue(dev, qid);
1901
1902 rc = ena_check_and_linearize_skb(tx_ring, skb);
1903 if (unlikely(rc))
1904 goto error_drop_packet;
1905
1906 skb_tx_timestamp(skb);
1907 len = skb_headlen(skb);
1908
1909 next_to_use = tx_ring->next_to_use;
1910 req_id = tx_ring->free_tx_ids[next_to_use];
1911 tx_info = &tx_ring->tx_buffer_info[req_id];
1912 tx_info->num_of_bufs = 0;
1913
1914 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
1915 ena_buf = tx_info->bufs;
1916 tx_info->skb = skb;
1917
1918 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1919 /* prepared the push buffer */
1920 push_len = min_t(u32, len, tx_ring->tx_max_header_size);
1921 header_len = push_len;
1922 push_hdr = skb->data;
1923 } else {
1924 push_len = 0;
1925 header_len = min_t(u32, len, tx_ring->tx_max_header_size);
1926 push_hdr = NULL;
1927 }
1928
1929 netif_dbg(adapter, tx_queued, dev,
1930 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
1931 push_hdr, push_len);
1932
1933 if (len > push_len) {
1934 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
1935 len - push_len, DMA_TO_DEVICE);
1936 if (dma_mapping_error(tx_ring->dev, dma))
1937 goto error_report_dma_error;
1938
1939 ena_buf->paddr = dma;
1940 ena_buf->len = len - push_len;
1941
1942 ena_buf++;
1943 tx_info->num_of_bufs++;
1944 }
1945
1946 last_frag = skb_shinfo(skb)->nr_frags;
1947
1948 for (i = 0; i < last_frag; i++) {
1949 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1950
1951 len = skb_frag_size(frag);
1952 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
1953 DMA_TO_DEVICE);
1954 if (dma_mapping_error(tx_ring->dev, dma))
1955 goto error_report_dma_error;
1956
1957 ena_buf->paddr = dma;
1958 ena_buf->len = len;
1959 ena_buf++;
1960 }
1961
1962 tx_info->num_of_bufs += last_frag;
1963
1964 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1965 ena_tx_ctx.ena_bufs = tx_info->bufs;
1966 ena_tx_ctx.push_header = push_hdr;
1967 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1968 ena_tx_ctx.req_id = req_id;
1969 ena_tx_ctx.header_len = header_len;
1970
1971 /* set flags and meta data */
1972 ena_tx_csum(&ena_tx_ctx, skb);
1973
1974 /* prepare the packet's descriptors to dma engine */
1975 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
1976 &nb_hw_desc);
1977
1978 if (unlikely(rc)) {
1979 netif_err(adapter, tx_queued, dev,
1980 "failed to prepare tx bufs\n");
1981 u64_stats_update_begin(&tx_ring->syncp);
1982 tx_ring->tx_stats.queue_stop++;
1983 tx_ring->tx_stats.prepare_ctx_err++;
1984 u64_stats_update_end(&tx_ring->syncp);
1985 netif_tx_stop_queue(txq);
1986 goto error_unmap_dma;
1987 }
1988
1989 netdev_tx_sent_queue(txq, skb->len);
1990
1991 u64_stats_update_begin(&tx_ring->syncp);
1992 tx_ring->tx_stats.cnt++;
1993 tx_ring->tx_stats.bytes += skb->len;
1994 u64_stats_update_end(&tx_ring->syncp);
1995
1996 tx_info->tx_descs = nb_hw_desc;
1997 tx_info->last_jiffies = jiffies;
1998
1999 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2000 tx_ring->ring_size);
2001
2002 /* This WMB is aimed to:
2003 * 1 - perform smp barrier before reading next_to_completion
2004 * 2 - make sure the desc were written before trigger DB
2005 */
2006 wmb();
2007
2008 /* stop the queue when no more space available, the packet can have up
2009 * to sgl_size + 2. one for the meta descriptor and one for header
2010 * (if the header is larger than tx_max_header_size).
2011 */
2012 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
2013 (tx_ring->sgl_size + 2))) {
2014 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2015 __func__, qid);
2016
2017 netif_tx_stop_queue(txq);
2018 u64_stats_update_begin(&tx_ring->syncp);
2019 tx_ring->tx_stats.queue_stop++;
2020 u64_stats_update_end(&tx_ring->syncp);
2021
2022 /* There is a rare condition where this function decide to
2023 * stop the queue but meanwhile clean_tx_irq updates
2024 * next_to_completion and terminates.
2025 * The queue will remain stopped forever.
2026 * To solve this issue this function perform rmb, check
2027 * the wakeup condition and wake up the queue if needed.
2028 */
2029 smp_rmb();
2030
2031 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
2032 > ENA_TX_WAKEUP_THRESH) {
2033 netif_tx_wake_queue(txq);
2034 u64_stats_update_begin(&tx_ring->syncp);
2035 tx_ring->tx_stats.queue_wakeup++;
2036 u64_stats_update_end(&tx_ring->syncp);
2037 }
2038 }
2039
2040 if (netif_xmit_stopped(txq) || !skb->xmit_more) {
2041 /* trigger the dma engine */
2042 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2043 u64_stats_update_begin(&tx_ring->syncp);
2044 tx_ring->tx_stats.doorbells++;
2045 u64_stats_update_end(&tx_ring->syncp);
2046 }
2047
2048 return NETDEV_TX_OK;
2049
2050error_report_dma_error:
2051 u64_stats_update_begin(&tx_ring->syncp);
2052 tx_ring->tx_stats.dma_mapping_err++;
2053 u64_stats_update_end(&tx_ring->syncp);
2054 netdev_warn(adapter->netdev, "failed to map skb\n");
2055
2056 tx_info->skb = NULL;
2057
2058error_unmap_dma:
2059 if (i >= 0) {
2060 /* save value of frag that failed */
2061 last_frag = i;
2062
2063 /* start back at beginning and unmap skb */
2064 tx_info->skb = NULL;
2065 ena_buf = tx_info->bufs;
2066 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2067 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2068
2069 /* unmap remaining mapped pages */
2070 for (i = 0; i < last_frag; i++) {
2071 ena_buf++;
2072 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2073 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2074 }
2075 }
2076
2077error_drop_packet:
2078
2079 dev_kfree_skb(skb);
2080 return NETDEV_TX_OK;
2081}
2082
2083#ifdef CONFIG_NET_POLL_CONTROLLER
2084static void ena_netpoll(struct net_device *netdev)
2085{
2086 struct ena_adapter *adapter = netdev_priv(netdev);
2087 int i;
2088
d5796182
NB		 2089 /* Dont schedule NAPI if the driver is in the middle of reset
2090 * or netdev is down.
2091 */
2092
2093 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) ||
2094 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2095 return;
2096
1738cd3e
NB		 2097 for (i = 0; i < adapter->num_queues; i++)
2098 napi_schedule(&adapter->ena_napi[i].napi);
2099}
2100#endif /* CONFIG_NET_POLL_CONTROLLER */
2101
2102static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2103 void *accel_priv, select_queue_fallback_t fallback)
2104{
2105 u16 qid;
2106 /* we suspect that this is good for in--kernel network services that
2107 * want to loop incoming skb rx to tx in normal user generated traffic,
2108 * most probably we will not get to this
2109 */
2110 if (skb_rx_queue_recorded(skb))
2111 qid = skb_get_rx_queue(skb);
2112 else
2113 qid = fallback(dev, skb);
2114
2115 return qid;
2116}
2117
2118static void ena_config_host_info(struct ena_com_dev *ena_dev)
2119{
2120 struct ena_admin_host_info *host_info;
2121 int rc;
2122
2123 /* Allocate only the host info */
2124 rc = ena_com_allocate_host_info(ena_dev);
2125 if (rc) {
2126 pr_err("Cannot allocate host info\n");
2127 return;
2128 }
2129
2130 host_info = ena_dev->host_attr.host_info;
2131
2132 host_info->os_type = ENA_ADMIN_OS_LINUX;
2133 host_info->kernel_ver = LINUX_VERSION_CODE;
2134 strncpy(host_info->kernel_ver_str, utsname()->version,
2135 sizeof(host_info->kernel_ver_str) - 1);
2136 host_info->os_dist = 0;
2137 strncpy(host_info->os_dist_str, utsname()->release,
2138 sizeof(host_info->os_dist_str) - 1);
2139 host_info->driver_version =
2140 (DRV_MODULE_VER_MAJOR) |
2141 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2142 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
2143
2144 rc = ena_com_set_host_attributes(ena_dev);
2145 if (rc) {
2146 if (rc == -EPERM)
2147 pr_warn("Cannot set host attributes\n");
2148 else
2149 pr_err("Cannot set host attributes\n");
2150
2151 goto err;
2152 }
2153
2154 return;
2155
2156err:
2157 ena_com_delete_host_info(ena_dev);
2158}
2159
2160static void ena_config_debug_area(struct ena_adapter *adapter)
2161{
2162 u32 debug_area_size;
2163 int rc, ss_count;
2164
2165 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2166 if (ss_count <= 0) {
2167 netif_err(adapter, drv, adapter->netdev,
2168 "SS count is negative\n");
2169 return;
2170 }
2171
2172 /* allocate 32 bytes for each string and 64bit for the value */
2173 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2174
2175 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2176 if (rc) {
2177 pr_err("Cannot allocate debug area\n");
2178 return;
2179 }
2180
2181 rc = ena_com_set_host_attributes(adapter->ena_dev);
2182 if (rc) {
2183 if (rc == -EPERM)
2184 netif_warn(adapter, drv, adapter->netdev,
2185 "Cannot set host attributes\n");
2186 else
2187 netif_err(adapter, drv, adapter->netdev,
2188 "Cannot set host attributes\n");
2189 goto err;
2190 }
2191
2192 return;
2193err:
2194 ena_com_delete_debug_area(adapter->ena_dev);
2195}
2196
2197static struct rtnl_link_stats64 *ena_get_stats64(struct net_device *netdev,
2198 struct rtnl_link_stats64 *stats)
2199{
2200 struct ena_adapter *adapter = netdev_priv(netdev);
e487b3b0
NB		 2201 struct ena_ring *rx_ring, *tx_ring;
2202 unsigned int start;
2203 u64 rx_drops;
2204 int i;
1738cd3e
NB		 2205
2206 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2207 return NULL;
2208
e487b3b0
NB		 2209 for (i = 0; i < adapter->num_queues; i++) {
2210 u64 bytes, packets;
2211
2212 tx_ring = &adapter->tx_ring[i];
1738cd3e 2213
e487b3b0
NB		 2214 do {
2215 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2216 packets = tx_ring->tx_stats.cnt;
2217 bytes = tx_ring->tx_stats.bytes;
2218 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
1738cd3e 2219
e487b3b0
NB		 2220 stats->tx_packets += packets;
2221 stats->tx_bytes += bytes;
2222
2223 rx_ring = &adapter->rx_ring[i];
2224
2225 do {
2226 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2227 packets = rx_ring->rx_stats.cnt;
2228 bytes = rx_ring->rx_stats.bytes;
2229 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2230
2231 stats->rx_packets += packets;
2232 stats->rx_bytes += bytes;
2233 }
2234
2235 do {
2236 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2237 rx_drops = adapter->dev_stats.rx_drops;
2238 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
1738cd3e 2239
e487b3b0 2240 stats->rx_dropped = rx_drops;
1738cd3e
NB		 2241
2242 stats->multicast = 0;
2243 stats->collisions = 0;
2244
2245 stats->rx_length_errors = 0;
2246 stats->rx_crc_errors = 0;
2247 stats->rx_frame_errors = 0;
2248 stats->rx_fifo_errors = 0;
2249 stats->rx_missed_errors = 0;
2250 stats->tx_window_errors = 0;
2251
2252 stats->rx_errors = 0;
2253 stats->tx_errors = 0;
2254
2255 return stats;
2256}
2257
2258static const struct net_device_ops ena_netdev_ops = {
2259 .ndo_open = ena_open,
2260 .ndo_stop = ena_close,
2261 .ndo_start_xmit = ena_start_xmit,
2262 .ndo_select_queue = ena_select_queue,
2263 .ndo_get_stats64 = ena_get_stats64,
2264 .ndo_tx_timeout = ena_tx_timeout,
2265 .ndo_change_mtu = ena_change_mtu,
2266 .ndo_set_mac_address = NULL,
2267 .ndo_validate_addr = eth_validate_addr,
2268#ifdef CONFIG_NET_POLL_CONTROLLER
2269 .ndo_poll_controller = ena_netpoll,
2270#endif /* CONFIG_NET_POLL_CONTROLLER */
2271};
2272
2273static void ena_device_io_suspend(struct work_struct *work)
2274{
2275 struct ena_adapter *adapter =
2276 container_of(work, struct ena_adapter, suspend_io_task);
2277 struct net_device *netdev = adapter->netdev;
2278
2279 /* ena_napi_disable_all disables only the IO handling.
2280 * We are still subject to AENQ keep alive watchdog.
2281 */
2282 u64_stats_update_begin(&adapter->syncp);
2283 adapter->dev_stats.io_suspend++;
2284 u64_stats_update_begin(&adapter->syncp);
2285 ena_napi_disable_all(adapter);
2286 netif_tx_lock(netdev);
2287 netif_device_detach(netdev);
2288 netif_tx_unlock(netdev);
2289}
2290
2291static void ena_device_io_resume(struct work_struct *work)
2292{
2293 struct ena_adapter *adapter =
2294 container_of(work, struct ena_adapter, resume_io_task);
2295 struct net_device *netdev = adapter->netdev;
2296
2297 u64_stats_update_begin(&adapter->syncp);
2298 adapter->dev_stats.io_resume++;
2299 u64_stats_update_end(&adapter->syncp);
2300
2301 netif_device_attach(netdev);
2302 ena_napi_enable_all(adapter);
2303}
2304
2305static int ena_device_validate_params(struct ena_adapter *adapter,
2306 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2307{
2308 struct net_device *netdev = adapter->netdev;
2309 int rc;
2310
2311 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2312 adapter->mac_addr);
2313 if (!rc) {
2314 netif_err(adapter, drv, netdev,
2315 "Error, mac address are different\n");
2316 return -EINVAL;
2317 }
2318
2319 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) ||
2320 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) {
2321 netif_err(adapter, drv, netdev,
2322 "Error, device doesn't support enough queues\n");
2323 return -EINVAL;
2324 }
2325
2326 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2327 netif_err(adapter, drv, netdev,
2328 "Error, device max mtu is smaller than netdev MTU\n");
2329 return -EINVAL;
2330 }
2331
2332 return 0;
2333}
2334
2335static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2336 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2337 bool *wd_state)
2338{
2339 struct device *dev = &pdev->dev;
2340 bool readless_supported;
2341 u32 aenq_groups;
2342 int dma_width;
2343 int rc;
2344
2345 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2346 if (rc) {
2347 dev_err(dev, "failed to init mmio read less\n");
2348 return rc;
2349 }
2350
2351 /* The PCIe configuration space revision id indicate if mmio reg
2352 * read is disabled
2353 */
2354 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2355 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2356
2357 rc = ena_com_dev_reset(ena_dev);
2358 if (rc) {
2359 dev_err(dev, "Can not reset device\n");
2360 goto err_mmio_read_less;
2361 }
2362
2363 rc = ena_com_validate_version(ena_dev);
2364 if (rc) {
2365 dev_err(dev, "device version is too low\n");
2366 goto err_mmio_read_less;
2367 }
2368
2369 dma_width = ena_com_get_dma_width(ena_dev);
2370 if (dma_width < 0) {
2371 dev_err(dev, "Invalid dma width value %d", dma_width);
6e22066f 2372 rc = dma_width;
1738cd3e
NB		 2373 goto err_mmio_read_less;
2374 }
2375
2376 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2377 if (rc) {
2378 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2379 goto err_mmio_read_less;
2380 }
2381
2382 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2383 if (rc) {
2384 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2385 rc);
2386 goto err_mmio_read_less;
2387 }
2388
2389 /* ENA admin level init */
2390 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
2391 if (rc) {
2392 dev_err(dev,
2393 "Can not initialize ena admin queue with device\n");
2394 goto err_mmio_read_less;
2395 }
2396
2397 /* To enable the msix interrupts the driver needs to know the number
2398 * of queues. So the driver uses polling mode to retrieve this
2399 * information
2400 */
2401 ena_com_set_admin_polling_mode(ena_dev, true);
2402
bb2eb26a
NB		 2403 ena_config_host_info(ena_dev);
2404
1738cd3e
NB		 2405 /* Get Device Attributes*/
2406 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2407 if (rc) {
2408 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2409 goto err_admin_init;
2410 }
2411
2412 /* Try to turn all the available aenq groups */
2413 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2414 BIT(ENA_ADMIN_FATAL_ERROR) |
2415 BIT(ENA_ADMIN_WARNING) |
2416 BIT(ENA_ADMIN_NOTIFICATION) |
2417 BIT(ENA_ADMIN_KEEP_ALIVE);
2418
2419 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2420
2421 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2422 if (rc) {
2423 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2424 goto err_admin_init;
2425 }
2426
2427 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2428
1738cd3e
NB		 2429 return 0;
2430
2431err_admin_init:
bb2eb26a 2432 ena_com_delete_host_info(ena_dev);
1738cd3e
NB		 2433 ena_com_admin_destroy(ena_dev);
2434err_mmio_read_less:
2435 ena_com_mmio_reg_read_request_destroy(ena_dev);
2436
2437 return rc;
2438}
2439
2440static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2441 int io_vectors)
2442{
2443 struct ena_com_dev *ena_dev = adapter->ena_dev;
2444 struct device *dev = &adapter->pdev->dev;
2445 int rc;
2446
2447 rc = ena_enable_msix(adapter, io_vectors);
2448 if (rc) {
2449 dev_err(dev, "Can not reserve msix vectors\n");
2450 return rc;
2451 }
2452
2453 ena_setup_mgmnt_intr(adapter);
2454
2455 rc = ena_request_mgmnt_irq(adapter);
2456 if (rc) {
2457 dev_err(dev, "Can not setup management interrupts\n");
2458 goto err_disable_msix;
2459 }
2460
2461 ena_com_set_admin_polling_mode(ena_dev, false);
2462
2463 ena_com_admin_aenq_enable(ena_dev);
2464
2465 return 0;
2466
2467err_disable_msix:
e328a031 2468 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 2469 return rc;
2470}
2471
2472static void ena_fw_reset_device(struct work_struct *work)
2473{
2474 struct ena_com_dev_get_features_ctx get_feat_ctx;
2475 struct ena_adapter *adapter =
2476 container_of(work, struct ena_adapter, reset_task);
2477 struct net_device *netdev = adapter->netdev;
2478 struct ena_com_dev *ena_dev = adapter->ena_dev;
2479 struct pci_dev *pdev = adapter->pdev;
2480 bool dev_up, wd_state;
2481 int rc;
2482
d5796182
NB		 2483 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2484 dev_err(&pdev->dev,
2485 "device reset schedule while reset bit is off\n");
2486 return;
2487 }
2488
2489 netif_carrier_off(netdev);
2490
1738cd3e
NB		 2491 del_timer_sync(&adapter->timer_service);
2492
2493 rtnl_lock();
2494
2495 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2496 ena_com_set_admin_running_state(ena_dev, false);
2497
2498 /* After calling ena_close the tx queues and the napi
2499 * are disabled so no one can interfere or touch the
2500 * data structures
2501 */
2502 ena_close(netdev);
2503
1738cd3e
NB		 2504 ena_free_mgmnt_irq(adapter);
2505
e328a031 2506 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 2507
2508 ena_com_abort_admin_commands(ena_dev);
2509
2510 ena_com_wait_for_abort_completion(ena_dev);
2511
2512 ena_com_admin_destroy(ena_dev);
2513
2514 ena_com_mmio_reg_read_request_destroy(ena_dev);
2515
d5796182
NB		 2516 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2517
1738cd3e
NB		 2518 /* Finish with the destroy part. Start the init part */
2519
2520 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2521 if (rc) {
2522 dev_err(&pdev->dev, "Can not initialize device\n");
2523 goto err;
2524 }
2525 adapter->wd_state = wd_state;
2526
2527 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2528 if (rc) {
2529 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2530 goto err_device_destroy;
2531 }
2532
2533 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2534 adapter->num_queues);
2535 if (rc) {
2536 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2537 goto err_device_destroy;
2538 }
2539 /* If the interface was up before the reset bring it up */
2540 if (dev_up) {
2541 rc = ena_up(adapter);
2542 if (rc) {
2543 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2544 goto err_disable_msix;
2545 }
2546 }
2547
2548 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2549
2550 rtnl_unlock();
2551
2552 dev_err(&pdev->dev, "Device reset completed successfully\n");
2553
2554 return;
2555err_disable_msix:
2556 ena_free_mgmnt_irq(adapter);
e328a031 2557 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 2558err_device_destroy:
2559 ena_com_admin_destroy(ena_dev);
2560err:
2561 rtnl_unlock();
2562
dee93ee4
NB		 2563 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2564
1738cd3e
NB		 2565 dev_err(&pdev->dev,
2566 "Reset attempt failed. Can not reset the device\n");
2567}
2568
2569static void check_for_missing_tx_completions(struct ena_adapter *adapter)
2570{
2571 struct ena_tx_buffer *tx_buf;
2572 unsigned long last_jiffies;
2573 struct ena_ring *tx_ring;
2574 int i, j, budget;
2575 u32 missed_tx;
2576
2577 /* Make sure the driver doesn't turn the device in other process */
2578 smp_rmb();
2579
2580 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2581 return;
2582
d5796182
NB		 2583 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2584 return;
2585
1738cd3e
NB		 2586 budget = ENA_MONITORED_TX_QUEUES;
2587
2588 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2589 tx_ring = &adapter->tx_ring[i];
2590
2591 for (j = 0; j < tx_ring->ring_size; j++) {
2592 tx_buf = &tx_ring->tx_buffer_info[j];
2593 last_jiffies = tx_buf->last_jiffies;
2594 if (unlikely(last_jiffies && time_is_before_jiffies(last_jiffies + TX_TIMEOUT))) {
2595 netif_notice(adapter, tx_err, adapter->netdev,
2596 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2597 tx_ring->qid, j);
2598
2599 u64_stats_update_begin(&tx_ring->syncp);
2600 missed_tx = tx_ring->tx_stats.missing_tx_comp++;
2601 u64_stats_update_end(&tx_ring->syncp);
2602
2603 /* Clear last jiffies so the lost buffer won't
2604 * be counted twice.
2605 */
2606 tx_buf->last_jiffies = 0;
2607
2608 if (unlikely(missed_tx > MAX_NUM_OF_TIMEOUTED_PACKETS)) {
2609 netif_err(adapter, tx_err, adapter->netdev,
2610 "The number of lost tx completion is above the threshold (%d > %d). Reset the device\n",
2611 missed_tx, MAX_NUM_OF_TIMEOUTED_PACKETS);
2612 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2613 }
2614 }
2615 }
2616
2617 budget--;
2618 if (!budget)
2619 break;
2620 }
2621
2622 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2623}
2624
d09b6090
NB		 2625/* trigger napi schedule after 2 consecutive detections */
2626#define EMPTY_RX_REFILL 2
2627/* For the rare case where the device runs out of Rx descriptors and the
2628 * napi handler failed to refill new Rx descriptors (due to a lack of memory
2629 * for example).
2630 * This case will lead to a deadlock:
2631 * The device won't send interrupts since all the new Rx packets will be dropped
2632 * The napi handler won't allocate new Rx descriptors so the device will be
2633 * able to send new packets.
2634 *
2635 * This scenario can happen when the kernel's vm.min_free_kbytes is too small.
2636 * It is recommended to have at least 512MB, with a minimum of 128MB for
2637 * constrained environment).
2638 *
2639 * When such a situation is detected - Reschedule napi
2640 */
2641static void check_for_empty_rx_ring(struct ena_adapter *adapter)
2642{
2643 struct ena_ring *rx_ring;
2644 int i, refill_required;
2645
2646 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2647 return;
2648
2649 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2650 return;
2651
2652 for (i = 0; i < adapter->num_queues; i++) {
2653 rx_ring = &adapter->rx_ring[i];
2654
2655 refill_required =
2656 ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
2657 if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
2658 rx_ring->empty_rx_queue++;
2659
2660 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
2661 u64_stats_update_begin(&rx_ring->syncp);
2662 rx_ring->rx_stats.empty_rx_ring++;
2663 u64_stats_update_end(&rx_ring->syncp);
2664
2665 netif_err(adapter, drv, adapter->netdev,
2666 "trigger refill for ring %d\n", i);
2667
2668 napi_schedule(rx_ring->napi);
2669 rx_ring->empty_rx_queue = 0;
2670 }
2671 } else {
2672 rx_ring->empty_rx_queue = 0;
2673 }
2674 }
2675}
2676
1738cd3e
NB		 2677/* Check for keep alive expiration */
2678static void check_for_missing_keep_alive(struct ena_adapter *adapter)
2679{
2680 unsigned long keep_alive_expired;
2681
2682 if (!adapter->wd_state)
2683 return;
2684
2685 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies
2686 + ENA_DEVICE_KALIVE_TIMEOUT);
2687 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
2688 netif_err(adapter, drv, adapter->netdev,
2689 "Keep alive watchdog timeout.\n");
2690 u64_stats_update_begin(&adapter->syncp);
2691 adapter->dev_stats.wd_expired++;
2692 u64_stats_update_end(&adapter->syncp);
2693 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2694 }
2695}
2696
2697static void check_for_admin_com_state(struct ena_adapter *adapter)
2698{
2699 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
2700 netif_err(adapter, drv, adapter->netdev,
2701 "ENA admin queue is not in running state!\n");
2702 u64_stats_update_begin(&adapter->syncp);
2703 adapter->dev_stats.admin_q_pause++;
2704 u64_stats_update_end(&adapter->syncp);
2705 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2706 }
2707}
2708
2709static void ena_update_host_info(struct ena_admin_host_info *host_info,
2710 struct net_device *netdev)
2711{
2712 host_info->supported_network_features[0] =
2713 netdev->features & GENMASK_ULL(31, 0);
2714 host_info->supported_network_features[1] =
2715 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
2716}
2717
2718static void ena_timer_service(unsigned long data)
2719{
2720 struct ena_adapter *adapter = (struct ena_adapter *)data;
2721 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
2722 struct ena_admin_host_info *host_info =
2723 adapter->ena_dev->host_attr.host_info;
2724
2725 check_for_missing_keep_alive(adapter);
2726
2727 check_for_admin_com_state(adapter);
2728
2729 check_for_missing_tx_completions(adapter);
2730
d09b6090
NB		 2731 check_for_empty_rx_ring(adapter);
2732
1738cd3e
NB		 2733 if (debug_area)
2734 ena_dump_stats_to_buf(adapter, debug_area);
2735
2736 if (host_info)
2737 ena_update_host_info(host_info, adapter->netdev);
2738
d5796182 2739 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
1738cd3e
NB		 2740 netif_err(adapter, drv, adapter->netdev,
2741 "Trigger reset is on\n");
2742 ena_dump_stats_to_dmesg(adapter);
2743 queue_work(ena_wq, &adapter->reset_task);
2744 return;
2745 }
2746
2747 /* Reset the timer */
2748 mod_timer(&adapter->timer_service, jiffies + HZ);
2749}
2750
2751static int ena_calc_io_queue_num(struct pci_dev *pdev,
2752 struct ena_com_dev *ena_dev,
2753 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2754{
2755 int io_sq_num, io_queue_num;
2756
2757 /* In case of LLQ use the llq number in the get feature cmd */
2758 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2759 io_sq_num = get_feat_ctx->max_queues.max_llq_num;
2760
2761 if (io_sq_num == 0) {
2762 dev_err(&pdev->dev,
2763 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
2764
2765 ena_dev->tx_mem_queue_type =
2766 ENA_ADMIN_PLACEMENT_POLICY_HOST;
2767 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2768 }
2769 } else {
2770 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2771 }
2772
c9b0b2cf 2773 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
1738cd3e
NB		 2774 io_queue_num = min_t(int, io_queue_num, io_sq_num);
2775 io_queue_num = min_t(int, io_queue_num,
2776 get_feat_ctx->max_queues.max_cq_num);
2777 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
2778 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
2779 if (unlikely(!io_queue_num)) {
2780 dev_err(&pdev->dev, "The device doesn't have io queues\n");
2781 return -EFAULT;
2782 }
2783
2784 return io_queue_num;
2785}
2786
184b49c8
RR		 2787static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
2788 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1738cd3e
NB		 2789{
2790 bool has_mem_bar;
2791
2792 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
2793
2794 /* Enable push mode if device supports LLQ */
2795 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
2796 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2797 else
2798 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1738cd3e
NB		 2799}
2800
2801static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
2802 struct net_device *netdev)
2803{
2804 netdev_features_t dev_features = 0;
2805
2806 /* Set offload features */
2807 if (feat->offload.tx &
2808 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2809 dev_features |= NETIF_F_IP_CSUM;
2810
2811 if (feat->offload.tx &
2812 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2813 dev_features |= NETIF_F_IPV6_CSUM;
2814
2815 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2816 dev_features |= NETIF_F_TSO;
2817
2818 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
2819 dev_features |= NETIF_F_TSO6;
2820
2821 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
2822 dev_features |= NETIF_F_TSO_ECN;
2823
2824 if (feat->offload.rx_supported &
2825 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2826 dev_features |= NETIF_F_RXCSUM;
2827
2828 if (feat->offload.rx_supported &
2829 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2830 dev_features |= NETIF_F_RXCSUM;
2831
2832 netdev->features =
2833 dev_features |
2834 NETIF_F_SG |
1738cd3e
NB		 2835 NETIF_F_RXHASH |
2836 NETIF_F_HIGHDMA;
2837
2838 netdev->hw_features |= netdev->features;
2839 netdev->vlan_features |= netdev->features;
2840}
2841
2842static void ena_set_conf_feat_params(struct ena_adapter *adapter,
2843 struct ena_com_dev_get_features_ctx *feat)
2844{
2845 struct net_device *netdev = adapter->netdev;
2846
2847 /* Copy mac address */
2848 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
2849 eth_hw_addr_random(netdev);
2850 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
2851 } else {
2852 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
2853 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
2854 }
2855
2856 /* Set offload features */
2857 ena_set_dev_offloads(feat, netdev);
2858
2859 adapter->max_mtu = feat->dev_attr.max_mtu;
d894be57
JW		 2860 netdev->max_mtu = adapter->max_mtu;
2861 netdev->min_mtu = ENA_MIN_MTU;
1738cd3e
NB		 2862}
2863
2864static int ena_rss_init_default(struct ena_adapter *adapter)
2865{
2866 struct ena_com_dev *ena_dev = adapter->ena_dev;
2867 struct device *dev = &adapter->pdev->dev;
2868 int rc, i;
2869 u32 val;
2870
2871 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2872 if (unlikely(rc)) {
2873 dev_err(dev, "Cannot init indirect table\n");
2874 goto err_rss_init;
2875 }
2876
2877 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
2878 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
2879 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
2880 ENA_IO_RXQ_IDX(val));
2881 if (unlikely(rc && (rc != -EPERM))) {
2882 dev_err(dev, "Cannot fill indirect table\n");
2883 goto err_fill_indir;
2884 }
2885 }
2886
2887 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
2888 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
2889 if (unlikely(rc && (rc != -EPERM))) {
2890 dev_err(dev, "Cannot fill hash function\n");
2891 goto err_fill_indir;
2892 }
2893
2894 rc = ena_com_set_default_hash_ctrl(ena_dev);
2895 if (unlikely(rc && (rc != -EPERM))) {
2896 dev_err(dev, "Cannot fill hash control\n");
2897 goto err_fill_indir;
2898 }
2899
2900 return 0;
2901
2902err_fill_indir:
2903 ena_com_rss_destroy(ena_dev);
2904err_rss_init:
2905
2906 return rc;
2907}
2908
2909static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
2910{
2911 int release_bars;
2912
b0f66a00
NB		 2913 if (ena_dev->mem_bar)
2914 devm_iounmap(&pdev->dev, ena_dev->mem_bar);
2915
2916 devm_iounmap(&pdev->dev, ena_dev->reg_bar);
2917
1738cd3e
NB		 2918 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
2919 pci_release_selected_regions(pdev, release_bars);
2920}
2921
2922static int ena_calc_queue_size(struct pci_dev *pdev,
2923 struct ena_com_dev *ena_dev,
2924 u16 *max_tx_sgl_size,
2925 u16 *max_rx_sgl_size,
2926 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2927{
2928 u32 queue_size = ENA_DEFAULT_RING_SIZE;
2929
2930 queue_size = min_t(u32, queue_size,
2931 get_feat_ctx->max_queues.max_cq_depth);
2932 queue_size = min_t(u32, queue_size,
2933 get_feat_ctx->max_queues.max_sq_depth);
2934
2935 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
2936 queue_size = min_t(u32, queue_size,
2937 get_feat_ctx->max_queues.max_llq_depth);
2938
2939 queue_size = rounddown_pow_of_two(queue_size);
2940
2941 if (unlikely(!queue_size)) {
2942 dev_err(&pdev->dev, "Invalid queue size\n");
2943 return -EFAULT;
2944 }
2945
2946 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
2947 get_feat_ctx->max_queues.max_packet_tx_descs);
2948 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
2949 get_feat_ctx->max_queues.max_packet_rx_descs);
2950
2951 return queue_size;
2952}
2953
2954/* ena_probe - Device Initialization Routine
2955 * @pdev: PCI device information struct
2956 * @ent: entry in ena_pci_tbl
2957 *
2958 * Returns 0 on success, negative on failure
2959 *
2960 * ena_probe initializes an adapter identified by a pci_dev structure.
2961 * The OS initialization, configuring of the adapter private structure,
2962 * and a hardware reset occur.
2963 */
2964static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2965{
2966 struct ena_com_dev_get_features_ctx get_feat_ctx;
2967 static int version_printed;
2968 struct net_device *netdev;
2969 struct ena_adapter *adapter;
2970 struct ena_com_dev *ena_dev = NULL;
2971 static int adapters_found;
2972 int io_queue_num, bars, rc;
2973 int queue_size;
2974 u16 tx_sgl_size = 0;
2975 u16 rx_sgl_size = 0;
2976 bool wd_state;
2977
2978 dev_dbg(&pdev->dev, "%s\n", __func__);
2979
2980 if (version_printed++ == 0)
2981 dev_info(&pdev->dev, "%s", version);
2982
2983 rc = pci_enable_device_mem(pdev);
2984 if (rc) {
2985 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
2986 return rc;
2987 }
2988
2989 pci_set_master(pdev);
2990
2991 ena_dev = vzalloc(sizeof(*ena_dev));
2992 if (!ena_dev) {
2993 rc = -ENOMEM;
2994 goto err_disable_device;
2995 }
2996
2997 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
2998 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
2999 if (rc) {
3000 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
3001 rc);
3002 goto err_free_ena_dev;
3003 }
3004
b0f66a00
NB		 3005 ena_dev->reg_bar = devm_ioremap(&pdev->dev,
3006 pci_resource_start(pdev, ENA_REG_BAR),
3007 pci_resource_len(pdev, ENA_REG_BAR));
1738cd3e
NB		 3008 if (!ena_dev->reg_bar) {
3009 dev_err(&pdev->dev, "failed to remap regs bar\n");
3010 rc = -EFAULT;
3011 goto err_free_region;
3012 }
3013
3014 ena_dev->dmadev = &pdev->dev;
3015
3016 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
3017 if (rc) {
3018 dev_err(&pdev->dev, "ena device init failed\n");
3019 if (rc == -ETIME)
3020 rc = -EPROBE_DEFER;
3021 goto err_free_region;
3022 }
3023
184b49c8 3024 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
1738cd3e
NB		 3025
3026 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
b0f66a00
NB		 3027 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
3028 pci_resource_start(pdev, ENA_MEM_BAR),
3029 pci_resource_len(pdev, ENA_MEM_BAR));
1738cd3e
NB		 3030 if (!ena_dev->mem_bar) {
3031 rc = -EFAULT;
3032 goto err_device_destroy;
3033 }
3034 }
3035
3036 /* initial Tx interrupt delay, Assumes 1 usec granularity.
3037 * Updated during device initialization with the real granularity
3038 */
3039 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
3040 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
3041 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size,
3042 &rx_sgl_size, &get_feat_ctx);
3043 if ((queue_size <= 0) || (io_queue_num <= 0)) {
3044 rc = -EFAULT;
3045 goto err_device_destroy;
3046 }
3047
3048 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
3049 io_queue_num, queue_size);
3050
3051 /* dev zeroed in init_etherdev */
3052 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
3053 if (!netdev) {
3054 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3055 rc = -ENOMEM;
3056 goto err_device_destroy;
3057 }
3058
3059 SET_NETDEV_DEV(netdev, &pdev->dev);
3060
3061 adapter = netdev_priv(netdev);
3062 pci_set_drvdata(pdev, adapter);
3063
3064 adapter->ena_dev = ena_dev;
3065 adapter->netdev = netdev;
3066 adapter->pdev = pdev;
3067
3068 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3069
3070 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3071
3072 adapter->tx_ring_size = queue_size;
3073 adapter->rx_ring_size = queue_size;
3074
3075 adapter->max_tx_sgl_size = tx_sgl_size;
3076 adapter->max_rx_sgl_size = rx_sgl_size;
3077
3078 adapter->num_queues = io_queue_num;
3079 adapter->last_monitored_tx_qid = 0;
3080
3081 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3082 adapter->wd_state = wd_state;
3083
3084 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3085
3086 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3087 if (rc) {
3088 dev_err(&pdev->dev,
3089 "Failed to query interrupt moderation feature\n");
3090 goto err_netdev_destroy;
3091 }
3092 ena_init_io_rings(adapter);
3093
3094 netdev->netdev_ops = &ena_netdev_ops;
3095 netdev->watchdog_timeo = TX_TIMEOUT;
3096 ena_set_ethtool_ops(netdev);
3097
3098 netdev->priv_flags |= IFF_UNICAST_FLT;
3099
3100 u64_stats_init(&adapter->syncp);
3101
3102 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3103 if (rc) {
3104 dev_err(&pdev->dev,
3105 "Failed to enable and set the admin interrupts\n");
3106 goto err_worker_destroy;
3107 }
3108 rc = ena_rss_init_default(adapter);
3109 if (rc && (rc != -EPERM)) {
3110 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3111 goto err_free_msix;
3112 }
3113
3114 ena_config_debug_area(adapter);
3115
3116 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3117
3118 netif_carrier_off(netdev);
3119
3120 rc = register_netdev(netdev);
3121 if (rc) {
3122 dev_err(&pdev->dev, "Cannot register net device\n");
3123 goto err_rss;
3124 }
3125
3126 INIT_WORK(&adapter->suspend_io_task, ena_device_io_suspend);
3127 INIT_WORK(&adapter->resume_io_task, ena_device_io_resume);
3128 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3129
3130 adapter->last_keep_alive_jiffies = jiffies;
3131
f850b4a7
WY		 3132 setup_timer(&adapter->timer_service, ena_timer_service,
3133 (unsigned long)adapter);
3134 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
1738cd3e
NB		 3135
3136 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
3137 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3138 netdev->dev_addr, io_queue_num);
3139
3140 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3141
3142 adapters_found++;
3143
3144 return 0;
3145
3146err_rss:
3147 ena_com_delete_debug_area(ena_dev);
3148 ena_com_rss_destroy(ena_dev);
3149err_free_msix:
3150 ena_com_dev_reset(ena_dev);
3151 ena_free_mgmnt_irq(adapter);
e328a031 3152 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 3153err_worker_destroy:
3154 ena_com_destroy_interrupt_moderation(ena_dev);
3155 del_timer(&adapter->timer_service);
3156 cancel_work_sync(&adapter->suspend_io_task);
3157 cancel_work_sync(&adapter->resume_io_task);
3158err_netdev_destroy:
3159 free_netdev(netdev);
3160err_device_destroy:
3161 ena_com_delete_host_info(ena_dev);
3162 ena_com_admin_destroy(ena_dev);
3163err_free_region:
3164 ena_release_bars(ena_dev, pdev);
3165err_free_ena_dev:
1738cd3e
NB		 3166 vfree(ena_dev);
3167err_disable_device:
3168 pci_disable_device(pdev);
3169 return rc;
3170}
3171
3172/*****************************************************************************/
3173static int ena_sriov_configure(struct pci_dev *dev, int numvfs)
3174{
3175 int rc;
3176
3177 if (numvfs > 0) {
3178 rc = pci_enable_sriov(dev, numvfs);
3179 if (rc != 0) {
3180 dev_err(&dev->dev,
3181 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n",
3182 numvfs, rc);
3183 return rc;
3184 }
3185
3186 return numvfs;
3187 }
3188
3189 if (numvfs == 0) {
3190 pci_disable_sriov(dev);
3191 return 0;
3192 }
3193
3194 return -EINVAL;
3195}
3196
3197/*****************************************************************************/
3198/*****************************************************************************/
3199
3200/* ena_remove - Device Removal Routine
3201 * @pdev: PCI device information struct
3202 *
3203 * ena_remove is called by the PCI subsystem to alert the driver
3204 * that it should release a PCI device.
3205 */
3206static void ena_remove(struct pci_dev *pdev)
3207{
3208 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3209 struct ena_com_dev *ena_dev;
3210 struct net_device *netdev;
3211
1738cd3e
NB		 3212 ena_dev = adapter->ena_dev;
3213 netdev = adapter->netdev;
3214
3215#ifdef CONFIG_RFS_ACCEL
3216 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3217 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3218 netdev->rx_cpu_rmap = NULL;
3219 }
3220#endif /* CONFIG_RFS_ACCEL */
3221
3222 unregister_netdev(netdev);
3223 del_timer_sync(&adapter->timer_service);
3224
3225 cancel_work_sync(&adapter->reset_task);
3226
3227 cancel_work_sync(&adapter->suspend_io_task);
3228
3229 cancel_work_sync(&adapter->resume_io_task);
3230
dee93ee4
NB		 3231 /* Reset the device only if the device is running. */
3232 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
3233 ena_com_dev_reset(ena_dev);
1738cd3e
NB		 3234
3235 ena_free_mgmnt_irq(adapter);
3236
e328a031 3237 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 3238
3239 free_netdev(netdev);
3240
3241 ena_com_mmio_reg_read_request_destroy(ena_dev);
3242
3243 ena_com_abort_admin_commands(ena_dev);
3244
3245 ena_com_wait_for_abort_completion(ena_dev);
3246
3247 ena_com_admin_destroy(ena_dev);
3248
3249 ena_com_rss_destroy(ena_dev);
3250
3251 ena_com_delete_debug_area(ena_dev);
3252
3253 ena_com_delete_host_info(ena_dev);
3254
3255 ena_release_bars(ena_dev, pdev);
3256
1738cd3e
NB		 3257 pci_disable_device(pdev);
3258
3259 ena_com_destroy_interrupt_moderation(ena_dev);
3260
3261 vfree(ena_dev);
3262}
3263
3264static struct pci_driver ena_pci_driver = {
3265 .name = DRV_MODULE_NAME,
3266 .id_table = ena_pci_tbl,
3267 .probe = ena_probe,
3268 .remove = ena_remove,
3269 .sriov_configure = ena_sriov_configure,
3270};
3271
3272static int __init ena_init(void)
3273{
3274 pr_info("%s", version);
3275
3276 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3277 if (!ena_wq) {
3278 pr_err("Failed to create workqueue\n");
3279 return -ENOMEM;
3280 }
3281
3282 return pci_register_driver(&ena_pci_driver);
3283}
3284
3285static void __exit ena_cleanup(void)
3286{
3287 pci_unregister_driver(&ena_pci_driver);
3288
3289 if (ena_wq) {
3290 destroy_workqueue(ena_wq);
3291 ena_wq = NULL;
3292 }
3293}
3294
3295/******************************************************************************
3296 ******************************** AENQ Handlers *******************************
3297 *****************************************************************************/
3298/* ena_update_on_link_change:
3299 * Notify the network interface about the change in link status
3300 */
3301static void ena_update_on_link_change(void *adapter_data,
3302 struct ena_admin_aenq_entry *aenq_e)
3303{
3304 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3305 struct ena_admin_aenq_link_change_desc *aenq_desc =
3306 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3307 int status = aenq_desc->flags &
3308 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3309
3310 if (status) {
3311 netdev_dbg(adapter->netdev, "%s\n", __func__);
3312 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3313 netif_carrier_on(adapter->netdev);
3314 } else {
3315 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3316 netif_carrier_off(adapter->netdev);
3317 }
3318}
3319
3320static void ena_keep_alive_wd(void *adapter_data,
3321 struct ena_admin_aenq_entry *aenq_e)
3322{
3323 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3324
3325 adapter->last_keep_alive_jiffies = jiffies;
3326}
3327
3328static void ena_notification(void *adapter_data,
3329 struct ena_admin_aenq_entry *aenq_e)
3330{
3331 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3332
3333 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3334 "Invalid group(%x) expected %x\n",
3335 aenq_e->aenq_common_desc.group,
3336 ENA_ADMIN_NOTIFICATION);
3337
3338 switch (aenq_e->aenq_common_desc.syndrom) {
3339 case ENA_ADMIN_SUSPEND:
3340 /* Suspend just the IO queues.
3341 * We deliberately don't suspend admin so the timer and
3342 * the keep_alive events should remain.
3343 */
3344 queue_work(ena_wq, &adapter->suspend_io_task);
3345 break;
3346 case ENA_ADMIN_RESUME:
3347 queue_work(ena_wq, &adapter->resume_io_task);
3348 break;
3349 default:
3350 netif_err(adapter, drv, adapter->netdev,
3351 "Invalid aenq notification link state %d\n",
3352 aenq_e->aenq_common_desc.syndrom);
3353 }
3354}
3355
3356/* This handler will called for unknown event group or unimplemented handlers*/
3357static void unimplemented_aenq_handler(void *data,
3358 struct ena_admin_aenq_entry *aenq_e)
3359{
3360 struct ena_adapter *adapter = (struct ena_adapter *)data;
3361
3362 netif_err(adapter, drv, adapter->netdev,
3363 "Unknown event was received or event with unimplemented handler\n");
3364}
3365
3366static struct ena_aenq_handlers aenq_handlers = {
3367 .handlers = {
3368 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3369 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3370 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3371 },
3372 .unimplemented_handler = unimplemented_aenq_handler
3373};
3374
3375module_init(ena_init);
3376module_exit(ena_cleanup);
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