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UBUNTU: SAUCE: igb: add support for using Broadcom 54616 as PHY
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
806ffb1d 53#include <linux/etherdevice.h>
421e02f0 54#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 55#include <linux/dca.h>
56#endif
441fc6fd 57#include <linux/i2c.h>
9d5c8243
AK		 58#include "igb.h"
59
67b1b903 60#define MAJ 5
0742337c 61#define MIN 4
6fb46902 62#define BUILD 0
0d1fe82d 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 64__stringify(BUILD) "-k"
9d5c8243
AK		 65char igb_driver_name[] = "igb";
66char igb_driver_version[] = DRV_VERSION;
67static const char igb_driver_string[] =
68 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 69static const char igb_copyright[] =
74cfb2e1 70 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 71
9d5c8243
AK		 72static const struct e1000_info *igb_info_tbl[] = {
73 [board_82575] = &e1000_82575_info,
74};
75
cd1631ce 76static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
d66696f3 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII), board_82575 },
9d5c8243
AK		 113 /* required last entry */
114 {0, }
115};
116
117MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
118
9d5c8243
AK		 119static int igb_setup_all_tx_resources(struct igb_adapter *);
120static int igb_setup_all_rx_resources(struct igb_adapter *);
121static void igb_free_all_tx_resources(struct igb_adapter *);
122static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 123static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 124static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 125static void igb_remove(struct pci_dev *pdev);
9d5c8243 126static int igb_sw_init(struct igb_adapter *);
46eafa59
SA		 127int igb_open(struct net_device *);
128int igb_close(struct net_device *);
53c7d064 129static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 130static void igb_configure_tx(struct igb_adapter *);
131static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 132static void igb_clean_all_tx_rings(struct igb_adapter *);
133static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 134static void igb_clean_tx_ring(struct igb_ring *);
135static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 136static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 137static void igb_update_phy_info(unsigned long);
138static void igb_watchdog(unsigned long);
139static void igb_watchdog_task(struct work_struct *);
cd392f5c 140static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 141static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 142 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 143static int igb_change_mtu(struct net_device *, int);
144static int igb_set_mac(struct net_device *, void *);
bf456abb 145static void igb_set_uta(struct igb_adapter *adapter, bool set);
9d5c8243
AK		 146static irqreturn_t igb_intr(int irq, void *);
147static irqreturn_t igb_intr_msi(int irq, void *);
148static irqreturn_t igb_msix_other(int irq, void *);
047e0030 149static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 150#ifdef CONFIG_IGB_DCA
047e0030 151static void igb_update_dca(struct igb_q_vector *);
fe4506b6 152static void igb_setup_dca(struct igb_adapter *);
421e02f0 153#endif /* CONFIG_IGB_DCA */
661086df 154static int igb_poll(struct napi_struct *, int);
7f0ba845 155static bool igb_clean_tx_irq(struct igb_q_vector *, int);
32b3e08f 156static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 157static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
158static void igb_tx_timeout(struct net_device *);
159static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 160static void igb_vlan_mode(struct net_device *netdev,
161 netdev_features_t features);
80d5c368
PM		 162static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
163static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 164static void igb_restore_vlan(struct igb_adapter *);
26ad9178 165static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 166static void igb_ping_all_vfs(struct igb_adapter *);
167static void igb_msg_task(struct igb_adapter *);
4ae196df 168static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 169static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 170static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 171static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
172static int igb_ndo_set_vf_vlan(struct net_device *netdev,
79aab093 173 int vf, u16 vlan, u8 qos, __be16 vlan_proto);
ed616689 174static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 175static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
176 bool setting);
8151d294
WM		 177static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
178 struct ifla_vf_info *ivi);
17dc566c 179static void igb_check_vf_rate_limit(struct igb_adapter *);
0e71def2
GH		 180static void igb_nfc_filter_exit(struct igb_adapter *adapter);
181static void igb_nfc_filter_restore(struct igb_adapter *adapter);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 185static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 186static int igb_disable_sriov(struct pci_dev *dev);
187static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 188#endif
9d5c8243 189
9d5c8243 190#ifdef CONFIG_PM
d9dd966d 191#ifdef CONFIG_PM_SLEEP
749ab2cd 192static int igb_suspend(struct device *);
d9dd966d 193#endif
749ab2cd 194static int igb_resume(struct device *);
749ab2cd
YZ		 195static int igb_runtime_suspend(struct device *dev);
196static int igb_runtime_resume(struct device *dev);
197static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 198static const struct dev_pm_ops igb_pm_ops = {
199 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
200 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
201 igb_runtime_idle)
202};
9d5c8243
AK		 203#endif
204static void igb_shutdown(struct pci_dev *);
fa44f2f1 205static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
208static struct notifier_block dca_notifier = {
209 .notifier_call = igb_notify_dca,
210 .next = NULL,
211 .priority = 0
212};
213#endif
9d5c8243
AK		 214#ifdef CONFIG_NET_POLL_CONTROLLER
215/* for netdump / net console */
216static void igb_netpoll(struct net_device *);
217#endif
37680117 218#ifdef CONFIG_PCI_IOV
6dd6d2b7 219static unsigned int max_vfs;
2a3abf6d 220module_param(max_vfs, uint, 0);
c75c4edf 221MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 387 pr_info("Device Name state trans_start last_rx\n");
876d2d6f 388 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
4d0e9657 389 netdev->state, dev_trans_start(netdev), netdev->last_rx);
c97ec42a
TI		 390 }
391
392 /* Print Registers */
393 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 394 pr_info(" Register Name Value\n");
c97ec42a
TI		 395 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
396 reginfo->name; reginfo++) {
397 igb_regdump(hw, reginfo);
398 }
399
400 /* Print TX Ring Summary */
401 if (!netdev || !netif_running(netdev))
402 goto exit;
403
404 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 405 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 406 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 407 struct igb_tx_buffer *buffer_info;
c97ec42a 408 tx_ring = adapter->tx_ring[n];
06034649 409 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 410 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
411 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 412 (u64)dma_unmap_addr(buffer_info, dma),
413 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 414 buffer_info->next_to_watch,
415 (u64)buffer_info->time_stamp);
c97ec42a
TI		 416 }
417
418 /* Print TX Rings */
419 if (!netif_msg_tx_done(adapter))
420 goto rx_ring_summary;
421
422 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
423
424 /* Transmit Descriptor Formats
425 *
426 * Advanced Transmit Descriptor
427 * +--------------------------------------------------------------+
428 * 0 | Buffer Address [63:0] |
429 * +--------------------------------------------------------------+
430 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
431 * +--------------------------------------------------------------+
432 * 63 46 45 40 39 38 36 35 32 31 24 15 0
433 */
434
435 for (n = 0; n < adapter->num_tx_queues; n++) {
436 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 437 pr_info("------------------------------------\n");
438 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
439 pr_info("------------------------------------\n");
c75c4edf 440 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 441
442 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 443 const char *next_desc;
06034649 444 struct igb_tx_buffer *buffer_info;
60136906 445 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 446 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 447 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 448 if (i == tx_ring->next_to_use &&
449 i == tx_ring->next_to_clean)
450 next_desc = " NTC/U";
451 else if (i == tx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == tx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
c75c4edf
CW		 458 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
459 i, le64_to_cpu(u0->a),
c97ec42a 460 le64_to_cpu(u0->b),
c9f14bf3
AD		 461 (u64)dma_unmap_addr(buffer_info, dma),
462 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 463 buffer_info->next_to_watch,
464 (u64)buffer_info->time_stamp,
876d2d6f 465 buffer_info->skb, next_desc);
c97ec42a 466
b669588a 467 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS,
b669588a 470 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 471 dma_unmap_len(buffer_info, len),
472 true);
c97ec42a
TI		 473 }
474 }
475
476 /* Print RX Rings Summary */
477rx_ring_summary:
478 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 479 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 480 for (n = 0; n < adapter->num_rx_queues; n++) {
481 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 482 pr_info(" %5d %5X %5X\n",
483 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 484 }
485
486 /* Print RX Rings */
487 if (!netif_msg_rx_status(adapter))
488 goto exit;
489
490 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
491
492 /* Advanced Receive Descriptor (Read) Format
493 * 63 1 0
494 * +-----------------------------------------------------+
495 * 0 | Packet Buffer Address [63:1] |A0/NSE|
496 * +----------------------------------------------+------+
497 * 8 | Header Buffer Address [63:1] | DD |
498 * +-----------------------------------------------------+
499 *
500 *
501 * Advanced Receive Descriptor (Write-Back) Format
502 *
503 * 63 48 47 32 31 30 21 20 17 16 4 3 0
504 * +------------------------------------------------------+
505 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
506 * | Checksum Ident | | | | Type | Type |
507 * +------------------------------------------------------+
508 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
509 * +------------------------------------------------------+
510 * 63 48 47 32 31 20 19 0
511 */
512
513 for (n = 0; n < adapter->num_rx_queues; n++) {
514 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 515 pr_info("------------------------------------\n");
516 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
517 pr_info("------------------------------------\n");
c75c4edf
CW		 518 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
519 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 520
521 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 522 const char *next_desc;
06034649
AD		 523 struct igb_rx_buffer *buffer_info;
524 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 525 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 526 u0 = (struct my_u0 *)rx_desc;
527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 528
529 if (i == rx_ring->next_to_use)
530 next_desc = " NTU";
531 else if (i == rx_ring->next_to_clean)
532 next_desc = " NTC";
533 else
534 next_desc = "";
535
c97ec42a
TI		 536 if (staterr & E1000_RXD_STAT_DD) {
537 /* Descriptor Done */
1a1c225b
AD		 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
539 "RWB", i,
c97ec42a
TI		 540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
1a1c225b 542 next_desc);
c97ec42a 543 } else {
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
545 "R ", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
548 (u64)buffer_info->dma,
1a1c225b 549 next_desc);
c97ec42a 550
b669588a 551 if (netif_msg_pktdata(adapter) &&
1a1c225b 552 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 553 print_hex_dump(KERN_INFO, "",
554 DUMP_PREFIX_ADDRESS,
555 16, 1,
b669588a
ET		 556 page_address(buffer_info->page) +
557 buffer_info->page_offset,
de78d1f9 558 IGB_RX_BUFSZ, true);
c97ec42a
TI		 559 }
560 }
c97ec42a
TI		 561 }
562 }
563
564exit:
565 return;
566}
567
b980ac18
JK		 568/**
569 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 570 * @hw: pointer to hardware structure
571 * @i2cctl: Current value of I2CCTL register
572 *
573 * Returns the I2C data bit value
b980ac18 574 **/
441fc6fd
CW		 575static int igb_get_i2c_data(void *data)
576{
577 struct igb_adapter *adapter = (struct igb_adapter *)data;
578 struct e1000_hw *hw = &adapter->hw;
579 s32 i2cctl = rd32(E1000_I2CPARAMS);
580
da1f1dfe 581 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 582}
583
b980ac18
JK		 584/**
585 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 586 * @data: pointer to hardware structure
587 * @state: I2C data value (0 or 1) to set
588 *
589 * Sets the I2C data bit
b980ac18 590 **/
441fc6fd
CW		 591static void igb_set_i2c_data(void *data, int state)
592{
593 struct igb_adapter *adapter = (struct igb_adapter *)data;
594 struct e1000_hw *hw = &adapter->hw;
595 s32 i2cctl = rd32(E1000_I2CPARAMS);
596
597 if (state)
598 i2cctl |= E1000_I2C_DATA_OUT;
599 else
600 i2cctl &= ~E1000_I2C_DATA_OUT;
601
602 i2cctl &= ~E1000_I2C_DATA_OE_N;
603 i2cctl |= E1000_I2C_CLK_OE_N;
604 wr32(E1000_I2CPARAMS, i2cctl);
605 wrfl();
606
607}
608
b980ac18
JK		 609/**
610 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 611 * @data: pointer to hardware structure
612 * @state: state to set clock
613 *
614 * Sets the I2C clock line to state
b980ac18 615 **/
441fc6fd
CW		 616static void igb_set_i2c_clk(void *data, int state)
617{
618 struct igb_adapter *adapter = (struct igb_adapter *)data;
619 struct e1000_hw *hw = &adapter->hw;
620 s32 i2cctl = rd32(E1000_I2CPARAMS);
621
622 if (state) {
623 i2cctl |= E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 } else {
626 i2cctl &= ~E1000_I2C_CLK_OUT;
627 i2cctl &= ~E1000_I2C_CLK_OE_N;
628 }
629 wr32(E1000_I2CPARAMS, i2cctl);
630 wrfl();
631}
632
b980ac18
JK		 633/**
634 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 635 * @data: pointer to hardware structure
636 *
637 * Gets the I2C clock state
b980ac18 638 **/
441fc6fd
CW		 639static int igb_get_i2c_clk(void *data)
640{
641 struct igb_adapter *adapter = (struct igb_adapter *)data;
642 struct e1000_hw *hw = &adapter->hw;
643 s32 i2cctl = rd32(E1000_I2CPARAMS);
644
da1f1dfe 645 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 646}
647
648static const struct i2c_algo_bit_data igb_i2c_algo = {
649 .setsda = igb_set_i2c_data,
650 .setscl = igb_set_i2c_clk,
651 .getsda = igb_get_i2c_data,
652 .getscl = igb_get_i2c_clk,
653 .udelay = 5,
654 .timeout = 20,
655};
656
9d5c8243 657/**
b980ac18
JK		 658 * igb_get_hw_dev - return device
659 * @hw: pointer to hardware structure
660 *
661 * used by hardware layer to print debugging information
9d5c8243 662 **/
c041076a 663struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 664{
665 struct igb_adapter *adapter = hw->back;
c041076a 666 return adapter->netdev;
9d5c8243 667}
38c845c7 668
9d5c8243 669/**
b980ac18 670 * igb_init_module - Driver Registration Routine
9d5c8243 671 *
b980ac18
JK		 672 * igb_init_module is the first routine called when the driver is
673 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 674 **/
675static int __init igb_init_module(void)
676{
677 int ret;
9005df38 678
876d2d6f 679 pr_info("%s - version %s\n",
9d5c8243 680 igb_driver_string, igb_driver_version);
876d2d6f 681 pr_info("%s\n", igb_copyright);
9d5c8243 682
421e02f0 683#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 684 dca_register_notify(&dca_notifier);
685#endif
bbd98fe4 686 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 687 return ret;
688}
689
690module_init(igb_init_module);
691
692/**
b980ac18 693 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 694 *
b980ac18
JK		 695 * igb_exit_module is called just before the driver is removed
696 * from memory.
9d5c8243
AK		 697 **/
698static void __exit igb_exit_module(void)
699{
421e02f0 700#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 701 dca_unregister_notify(&dca_notifier);
702#endif
9d5c8243
AK		 703 pci_unregister_driver(&igb_driver);
704}
705
706module_exit(igb_exit_module);
707
26bc19ec
AD		 708#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
709/**
b980ac18
JK		 710 * igb_cache_ring_register - Descriptor ring to register mapping
711 * @adapter: board private structure to initialize
26bc19ec 712 *
b980ac18
JK		 713 * Once we know the feature-set enabled for the device, we'll cache
714 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 715 **/
716static void igb_cache_ring_register(struct igb_adapter *adapter)
717{
ee1b9f06 718 int i = 0, j = 0;
047e0030 719 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 720
721 switch (adapter->hw.mac.type) {
722 case e1000_82576:
723 /* The queues are allocated for virtualization such that VF 0
724 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
725 * In order to avoid collision we start at the first free queue
726 * and continue consuming queues in the same sequence
727 */
ee1b9f06 728 if (adapter->vfs_allocated_count) {
a99955fc 729 for (; i < adapter->rss_queues; i++)
3025a446 730 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 731 Q_IDX_82576(i);
ee1b9f06 732 }
b26141d4 733 /* Fall through */
26bc19ec 734 case e1000_82575:
55cac248 735 case e1000_82580:
d2ba2ed8 736 case e1000_i350:
ceb5f13b 737 case e1000_i354:
f96a8a0b
CW		 738 case e1000_i210:
739 case e1000_i211:
b26141d4 740 /* Fall through */
26bc19ec 741 default:
ee1b9f06 742 for (; i < adapter->num_rx_queues; i++)
3025a446 743 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 744 for (; j < adapter->num_tx_queues; j++)
3025a446 745 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 746 break;
747 }
748}
749
22a8b291
FT		 750u32 igb_rd32(struct e1000_hw *hw, u32 reg)
751{
752 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
753 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
754 u32 value = 0;
755
756 if (E1000_REMOVED(hw_addr))
757 return ~value;
758
759 value = readl(&hw_addr[reg]);
760
761 /* reads should not return all F's */
762 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
763 struct net_device *netdev = igb->netdev;
764 hw->hw_addr = NULL;
765 netif_device_detach(netdev);
766 netdev_err(netdev, "PCIe link lost, device now detached\n");
767 }
768
769 return value;
770}
771
4be000c8
AD		 772/**
773 * igb_write_ivar - configure ivar for given MSI-X vector
774 * @hw: pointer to the HW structure
775 * @msix_vector: vector number we are allocating to a given ring
776 * @index: row index of IVAR register to write within IVAR table
777 * @offset: column offset of in IVAR, should be multiple of 8
778 *
779 * This function is intended to handle the writing of the IVAR register
780 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
781 * each containing an cause allocation for an Rx and Tx ring, and a
782 * variable number of rows depending on the number of queues supported.
783 **/
784static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
785 int index, int offset)
786{
787 u32 ivar = array_rd32(E1000_IVAR0, index);
788
789 /* clear any bits that are currently set */
790 ivar &= ~((u32)0xFF << offset);
791
792 /* write vector and valid bit */
793 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
794
795 array_wr32(E1000_IVAR0, index, ivar);
796}
797
9d5c8243 798#define IGB_N0_QUEUE -1
047e0030 799static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 800{
047e0030 801 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 802 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 803 int rx_queue = IGB_N0_QUEUE;
804 int tx_queue = IGB_N0_QUEUE;
4be000c8 805 u32 msixbm = 0;
047e0030 806
0ba82994
AD		 807 if (q_vector->rx.ring)
808 rx_queue = q_vector->rx.ring->reg_idx;
809 if (q_vector->tx.ring)
810 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 811
812 switch (hw->mac.type) {
813 case e1000_82575:
9d5c8243 814 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 815 * bitmask for the EICR/EIMS/EIMC registers. To assign one
816 * or more queues to a vector, we write the appropriate bits
817 * into the MSIXBM register for that vector.
818 */
047e0030 819 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 820 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 821 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 822 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 823 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 824 msixbm |= E1000_EIMS_OTHER;
9d5c8243 825 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 826 q_vector->eims_value = msixbm;
2d064c06
AD		 827 break;
828 case e1000_82576:
b980ac18 829 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 830 * with 8 rows. The ordering is column-major so we use the
831 * lower 3 bits as the row index, and the 4th bit as the
832 * column offset.
833 */
834 if (rx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 rx_queue & 0x7,
837 (rx_queue & 0x8) << 1);
838 if (tx_queue > IGB_N0_QUEUE)
839 igb_write_ivar(hw, msix_vector,
840 tx_queue & 0x7,
841 ((tx_queue & 0x8) << 1) + 8);
a51d8c21 842 q_vector->eims_value = BIT(msix_vector);
2d064c06 843 break;
55cac248 844 case e1000_82580:
d2ba2ed8 845 case e1000_i350:
ceb5f13b 846 case e1000_i354:
f96a8a0b
CW		 847 case e1000_i210:
848 case e1000_i211:
b980ac18 849 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 850 * however instead of ordering column-major we have things
851 * ordered row-major. So we traverse the table by using
852 * bit 0 as the column offset, and the remaining bits as the
853 * row index.
854 */
855 if (rx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 rx_queue >> 1,
858 (rx_queue & 0x1) << 4);
859 if (tx_queue > IGB_N0_QUEUE)
860 igb_write_ivar(hw, msix_vector,
861 tx_queue >> 1,
862 ((tx_queue & 0x1) << 4) + 8);
a51d8c21 863 q_vector->eims_value = BIT(msix_vector);
55cac248 864 break;
2d064c06
AD		 865 default:
866 BUG();
867 break;
868 }
26b39276
AD		 869
870 /* add q_vector eims value to global eims_enable_mask */
871 adapter->eims_enable_mask |= q_vector->eims_value;
872
873 /* configure q_vector to set itr on first interrupt */
874 q_vector->set_itr = 1;
9d5c8243
AK		 875}
876
877/**
b980ac18
JK		 878 * igb_configure_msix - Configure MSI-X hardware
879 * @adapter: board private structure to initialize
9d5c8243 880 *
b980ac18
JK		 881 * igb_configure_msix sets up the hardware to properly
882 * generate MSI-X interrupts.
9d5c8243
AK		 883 **/
884static void igb_configure_msix(struct igb_adapter *adapter)
885{
886 u32 tmp;
887 int i, vector = 0;
888 struct e1000_hw *hw = &adapter->hw;
889
890 adapter->eims_enable_mask = 0;
9d5c8243
AK		 891
892 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 893 switch (hw->mac.type) {
894 case e1000_82575:
9d5c8243
AK		 895 tmp = rd32(E1000_CTRL_EXT);
896 /* enable MSI-X PBA support*/
897 tmp |= E1000_CTRL_EXT_PBA_CLR;
898
899 /* Auto-Mask interrupts upon ICR read. */
900 tmp |= E1000_CTRL_EXT_EIAME;
901 tmp |= E1000_CTRL_EXT_IRCA;
902
903 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 904
905 /* enable msix_other interrupt */
b980ac18 906 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 907 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 908
2d064c06
AD		 909 break;
910
911 case e1000_82576:
55cac248 912 case e1000_82580:
d2ba2ed8 913 case e1000_i350:
ceb5f13b 914 case e1000_i354:
f96a8a0b
CW		 915 case e1000_i210:
916 case e1000_i211:
047e0030 917 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 918 * won't stick. And it will take days to debug.
919 */
047e0030 920 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 921 E1000_GPIE_PBA | E1000_GPIE_EIAME |
922 E1000_GPIE_NSICR);
047e0030
AD		 923
924 /* enable msix_other interrupt */
a51d8c21 925 adapter->eims_other = BIT(vector);
2d064c06 926 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 927
047e0030 928 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 929 break;
930 default:
931 /* do nothing, since nothing else supports MSI-X */
932 break;
933 } /* switch (hw->mac.type) */
047e0030
AD		 934
935 adapter->eims_enable_mask |= adapter->eims_other;
936
26b39276
AD		 937 for (i = 0; i < adapter->num_q_vectors; i++)
938 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 939
9d5c8243
AK		 940 wrfl();
941}
942
943/**
b980ac18
JK		 944 * igb_request_msix - Initialize MSI-X interrupts
945 * @adapter: board private structure to initialize
9d5c8243 946 *
b980ac18
JK		 947 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
948 * kernel.
9d5c8243
AK		 949 **/
950static int igb_request_msix(struct igb_adapter *adapter)
951{
952 struct net_device *netdev = adapter->netdev;
52285b76 953 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 954
047e0030 955 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 956 igb_msix_other, 0, netdev->name, adapter);
047e0030 957 if (err)
52285b76 958 goto err_out;
047e0030
AD		 959
960 for (i = 0; i < adapter->num_q_vectors; i++) {
961 struct igb_q_vector *q_vector = adapter->q_vector[i];
962
52285b76
SA		 963 vector++;
964
7b06a690 965 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 966
0ba82994 967 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 969 q_vector->rx.ring->queue_index);
970 else if (q_vector->tx.ring)
047e0030 971 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 972 q_vector->tx.ring->queue_index);
973 else if (q_vector->rx.ring)
047e0030 974 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 975 q_vector->rx.ring->queue_index);
9d5c8243 976 else
047e0030
AD		 977 sprintf(q_vector->name, "%s-unused", netdev->name);
978
9d5c8243 979 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 980 igb_msix_ring, 0, q_vector->name,
981 q_vector);
9d5c8243 982 if (err)
52285b76 983 goto err_free;
9d5c8243
AK		 984 }
985
9d5c8243
AK		 986 igb_configure_msix(adapter);
987 return 0;
52285b76
SA		 988
989err_free:
990 /* free already assigned IRQs */
991 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
992
993 vector--;
994 for (i = 0; i < vector; i++) {
995 free_irq(adapter->msix_entries[free_vector++].vector,
996 adapter->q_vector[i]);
997 }
998err_out:
9d5c8243
AK		 999 return err;
1000}
1001
5536d210 1002/**
b980ac18
JK		 1003 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1004 * @adapter: board private structure to initialize
1005 * @v_idx: Index of vector to be freed
5536d210 1006 *
02ef6e1d 1007 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1008 **/
1009static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1010{
1011 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1012
02ef6e1d
CW		 1013 adapter->q_vector[v_idx] = NULL;
1014
1015 /* igb_get_stats64() might access the rings on this vector,
1016 * we must wait a grace period before freeing it.
1017 */
17a402a0
CW		 1018 if (q_vector)
1019 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1020}
1021
1022/**
1023 * igb_reset_q_vector - Reset config for interrupt vector
1024 * @adapter: board private structure to initialize
1025 * @v_idx: Index of vector to be reset
1026 *
1027 * If NAPI is enabled it will delete any references to the
1028 * NAPI struct. This is preparation for igb_free_q_vector.
1029 **/
1030static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1031{
1032 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1033
cb06d102
CP		 1034 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1035 * allocated. So, q_vector is NULL so we should stop here.
1036 */
1037 if (!q_vector)
1038 return;
1039
5536d210
AD		 1040 if (q_vector->tx.ring)
1041 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1042
1043 if (q_vector->rx.ring)
2439fc4d 1044 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1045
5536d210
AD		 1046 netif_napi_del(&q_vector->napi);
1047
02ef6e1d
CW		 1048}
1049
1050static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1051{
1052 int v_idx = adapter->num_q_vectors;
1053
cd14ef54 1054 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1055 pci_disable_msix(adapter->pdev);
cd14ef54 1056 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1057 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1058
1059 while (v_idx--)
1060 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1061}
1062
047e0030 1063/**
b980ac18
JK		 1064 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1065 * @adapter: board private structure to initialize
047e0030 1066 *
b980ac18
JK		 1067 * This function frees the memory allocated to the q_vectors. In addition if
1068 * NAPI is enabled it will delete any references to the NAPI struct prior
1069 * to freeing the q_vector.
047e0030
AD		 1070 **/
1071static void igb_free_q_vectors(struct igb_adapter *adapter)
1072{
5536d210
AD		 1073 int v_idx = adapter->num_q_vectors;
1074
1075 adapter->num_tx_queues = 0;
1076 adapter->num_rx_queues = 0;
047e0030 1077 adapter->num_q_vectors = 0;
5536d210 1078
02ef6e1d
CW		 1079 while (v_idx--) {
1080 igb_reset_q_vector(adapter, v_idx);
5536d210 1081 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1082 }
047e0030
AD		 1083}
1084
1085/**
b980ac18
JK		 1086 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1087 * @adapter: board private structure to initialize
047e0030 1088 *
b980ac18
JK		 1089 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1090 * MSI-X interrupts allocated.
047e0030
AD		 1091 */
1092static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1093{
047e0030
AD		 1094 igb_free_q_vectors(adapter);
1095 igb_reset_interrupt_capability(adapter);
1096}
9d5c8243
AK		 1097
1098/**
b980ac18
JK		 1099 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1100 * @adapter: board private structure to initialize
1101 * @msix: boolean value of MSIX capability
9d5c8243 1102 *
b980ac18
JK		 1103 * Attempt to configure interrupts using the best available
1104 * capabilities of the hardware and kernel.
9d5c8243 1105 **/
53c7d064 1106static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1107{
1108 int err;
1109 int numvecs, i;
1110
53c7d064
SA		 1111 if (!msix)
1112 goto msi_only;
cd14ef54 1113 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1114
83b7180d 1115 /* Number of supported queues. */
a99955fc 1116 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1117 if (adapter->vfs_allocated_count)
1118 adapter->num_tx_queues = 1;
1119 else
1120 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1121
b980ac18 1122 /* start with one vector for every Rx queue */
047e0030
AD		 1123 numvecs = adapter->num_rx_queues;
1124
b980ac18 1125 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1126 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1127 numvecs += adapter->num_tx_queues;
047e0030
AD		 1128
1129 /* store the number of vectors reserved for queues */
1130 adapter->num_q_vectors = numvecs;
1131
1132 /* add 1 vector for link status interrupts */
1133 numvecs++;
9d5c8243
AK		 1134 for (i = 0; i < numvecs; i++)
1135 adapter->msix_entries[i].entry = i;
1136
479d02df
AG		 1137 err = pci_enable_msix_range(adapter->pdev,
1138 adapter->msix_entries,
1139 numvecs,
1140 numvecs);
1141 if (err > 0)
0c2cc02e 1142 return;
9d5c8243
AK		 1143
1144 igb_reset_interrupt_capability(adapter);
1145
1146 /* If we can't do MSI-X, try MSI */
1147msi_only:
b709323d 1148 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1149#ifdef CONFIG_PCI_IOV
1150 /* disable SR-IOV for non MSI-X configurations */
1151 if (adapter->vf_data) {
1152 struct e1000_hw *hw = &adapter->hw;
1153 /* disable iov and allow time for transactions to clear */
1154 pci_disable_sriov(adapter->pdev);
1155 msleep(500);
1156
1157 kfree(adapter->vf_data);
1158 adapter->vf_data = NULL;
1159 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1160 wrfl();
2a3abf6d
AD		 1161 msleep(100);
1162 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1163 }
1164#endif
4fc82adf 1165 adapter->vfs_allocated_count = 0;
a99955fc 1166 adapter->rss_queues = 1;
4fc82adf 1167 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1168 adapter->num_rx_queues = 1;
661086df 1169 adapter->num_tx_queues = 1;
047e0030 1170 adapter->num_q_vectors = 1;
9d5c8243 1171 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1172 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1173}
1174
5536d210
AD		 1175static void igb_add_ring(struct igb_ring *ring,
1176 struct igb_ring_container *head)
1177{
1178 head->ring = ring;
1179 head->count++;
1180}
1181
047e0030 1182/**
b980ac18
JK		 1183 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1184 * @adapter: board private structure to initialize
1185 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1186 * @v_idx: index of vector in adapter struct
1187 * @txr_count: total number of Tx rings to allocate
1188 * @txr_idx: index of first Tx ring to allocate
1189 * @rxr_count: total number of Rx rings to allocate
1190 * @rxr_idx: index of first Rx ring to allocate
047e0030 1191 *
b980ac18 1192 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1193 **/
5536d210
AD		 1194static int igb_alloc_q_vector(struct igb_adapter *adapter,
1195 int v_count, int v_idx,
1196 int txr_count, int txr_idx,
1197 int rxr_count, int rxr_idx)
047e0030
AD		 1198{
1199 struct igb_q_vector *q_vector;
5536d210
AD		 1200 struct igb_ring *ring;
1201 int ring_count, size;
047e0030 1202
5536d210
AD		 1203 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1204 if (txr_count > 1 || rxr_count > 1)
1205 return -ENOMEM;
1206
1207 ring_count = txr_count + rxr_count;
1208 size = sizeof(struct igb_q_vector) +
1209 (sizeof(struct igb_ring) * ring_count);
1210
1211 /* allocate q_vector and rings */
02ef6e1d 1212 q_vector = adapter->q_vector[v_idx];
72ddef05 1213 if (!q_vector) {
02ef6e1d 1214 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1215 } else if (size > ksize(q_vector)) {
1216 kfree_rcu(q_vector, rcu);
1217 q_vector = kzalloc(size, GFP_KERNEL);
1218 } else {
c0a06ee1 1219 memset(q_vector, 0, size);
72ddef05 1220 }
5536d210
AD		 1221 if (!q_vector)
1222 return -ENOMEM;
1223
1224 /* initialize NAPI */
1225 netif_napi_add(adapter->netdev, &q_vector->napi,
1226 igb_poll, 64);
1227
1228 /* tie q_vector and adapter together */
1229 adapter->q_vector[v_idx] = q_vector;
1230 q_vector->adapter = adapter;
1231
1232 /* initialize work limits */
1233 q_vector->tx.work_limit = adapter->tx_work_limit;
1234
1235 /* initialize ITR configuration */
7b06a690 1236 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1237 q_vector->itr_val = IGB_START_ITR;
1238
1239 /* initialize pointer to rings */
1240 ring = q_vector->ring;
1241
4e227667
AD		 1242 /* intialize ITR */
1243 if (rxr_count) {
1244 /* rx or rx/tx vector */
1245 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1246 q_vector->itr_val = adapter->rx_itr_setting;
1247 } else {
1248 /* tx only vector */
1249 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1250 q_vector->itr_val = adapter->tx_itr_setting;
1251 }
1252
5536d210
AD		 1253 if (txr_count) {
1254 /* assign generic ring traits */
1255 ring->dev = &adapter->pdev->dev;
1256 ring->netdev = adapter->netdev;
1257
1258 /* configure backlink on ring */
1259 ring->q_vector = q_vector;
1260
1261 /* update q_vector Tx values */
1262 igb_add_ring(ring, &q_vector->tx);
1263
1264 /* For 82575, context index must be unique per ring. */
1265 if (adapter->hw.mac.type == e1000_82575)
1266 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1267
1268 /* apply Tx specific ring traits */
1269 ring->count = adapter->tx_ring_count;
1270 ring->queue_index = txr_idx;
1271
827da44c
JS		 1272 u64_stats_init(&ring->tx_syncp);
1273 u64_stats_init(&ring->tx_syncp2);
1274
5536d210
AD		 1275 /* assign ring to adapter */
1276 adapter->tx_ring[txr_idx] = ring;
1277
1278 /* push pointer to next ring */
1279 ring++;
047e0030 1280 }
81c2fc22 1281
5536d210
AD		 1282 if (rxr_count) {
1283 /* assign generic ring traits */
1284 ring->dev = &adapter->pdev->dev;
1285 ring->netdev = adapter->netdev;
047e0030 1286
5536d210
AD		 1287 /* configure backlink on ring */
1288 ring->q_vector = q_vector;
047e0030 1289
5536d210
AD		 1290 /* update q_vector Rx values */
1291 igb_add_ring(ring, &q_vector->rx);
047e0030 1292
5536d210
AD		 1293 /* set flag indicating ring supports SCTP checksum offload */
1294 if (adapter->hw.mac.type >= e1000_82576)
1295 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1296
e52c0f96 1297 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1298 * have the tag byte-swapped.
b980ac18 1299 */
5536d210
AD		 1300 if (adapter->hw.mac.type >= e1000_i350)
1301 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1302
5536d210
AD		 1303 /* apply Rx specific ring traits */
1304 ring->count = adapter->rx_ring_count;
1305 ring->queue_index = rxr_idx;
1306
827da44c
JS		 1307 u64_stats_init(&ring->rx_syncp);
1308
5536d210
AD		 1309 /* assign ring to adapter */
1310 adapter->rx_ring[rxr_idx] = ring;
1311 }
1312
1313 return 0;
047e0030
AD		 1314}
1315
5536d210 1316
047e0030 1317/**
b980ac18
JK		 1318 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1319 * @adapter: board private structure to initialize
047e0030 1320 *
b980ac18
JK		 1321 * We allocate one q_vector per queue interrupt. If allocation fails we
1322 * return -ENOMEM.
047e0030 1323 **/
5536d210 1324static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1325{
5536d210
AD		 1326 int q_vectors = adapter->num_q_vectors;
1327 int rxr_remaining = adapter->num_rx_queues;
1328 int txr_remaining = adapter->num_tx_queues;
1329 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1330 int err;
047e0030 1331
5536d210
AD		 1332 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1333 for (; rxr_remaining; v_idx++) {
1334 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1335 0, 0, 1, rxr_idx);
047e0030 1336
5536d210
AD		 1337 if (err)
1338 goto err_out;
1339
1340 /* update counts and index */
1341 rxr_remaining--;
1342 rxr_idx++;
047e0030 1343 }
047e0030 1344 }
5536d210
AD		 1345
1346 for (; v_idx < q_vectors; v_idx++) {
1347 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1348 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1349
5536d210
AD		 1350 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1351 tqpv, txr_idx, rqpv, rxr_idx);
1352
1353 if (err)
1354 goto err_out;
1355
1356 /* update counts and index */
1357 rxr_remaining -= rqpv;
1358 txr_remaining -= tqpv;
1359 rxr_idx++;
1360 txr_idx++;
1361 }
1362
047e0030 1363 return 0;
5536d210
AD		 1364
1365err_out:
1366 adapter->num_tx_queues = 0;
1367 adapter->num_rx_queues = 0;
1368 adapter->num_q_vectors = 0;
1369
1370 while (v_idx--)
1371 igb_free_q_vector(adapter, v_idx);
1372
1373 return -ENOMEM;
047e0030
AD		 1374}
1375
1376/**
b980ac18
JK		 1377 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1378 * @adapter: board private structure to initialize
1379 * @msix: boolean value of MSIX capability
047e0030 1380 *
b980ac18 1381 * This function initializes the interrupts and allocates all of the queues.
047e0030 1382 **/
53c7d064 1383static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1384{
1385 struct pci_dev *pdev = adapter->pdev;
1386 int err;
1387
53c7d064 1388 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1389
1390 err = igb_alloc_q_vectors(adapter);
1391 if (err) {
1392 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1393 goto err_alloc_q_vectors;
1394 }
1395
5536d210 1396 igb_cache_ring_register(adapter);
047e0030
AD		 1397
1398 return 0;
5536d210 1399
047e0030
AD		 1400err_alloc_q_vectors:
1401 igb_reset_interrupt_capability(adapter);
1402 return err;
1403}
1404
9d5c8243 1405/**
b980ac18
JK		 1406 * igb_request_irq - initialize interrupts
1407 * @adapter: board private structure to initialize
9d5c8243 1408 *
b980ac18
JK		 1409 * Attempts to configure interrupts using the best available
1410 * capabilities of the hardware and kernel.
9d5c8243
AK		 1411 **/
1412static int igb_request_irq(struct igb_adapter *adapter)
1413{
1414 struct net_device *netdev = adapter->netdev;
047e0030 1415 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1416 int err = 0;
1417
cd14ef54 1418 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1419 err = igb_request_msix(adapter);
844290e5 1420 if (!err)
9d5c8243 1421 goto request_done;
9d5c8243 1422 /* fall back to MSI */
5536d210
AD		 1423 igb_free_all_tx_resources(adapter);
1424 igb_free_all_rx_resources(adapter);
53c7d064 1425
047e0030 1426 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1427 err = igb_init_interrupt_scheme(adapter, false);
1428 if (err)
047e0030 1429 goto request_done;
53c7d064 1430
047e0030
AD		 1431 igb_setup_all_tx_resources(adapter);
1432 igb_setup_all_rx_resources(adapter);
53c7d064 1433 igb_configure(adapter);
9d5c8243 1434 }
844290e5 1435
c74d588e
AD		 1436 igb_assign_vector(adapter->q_vector[0], 0);
1437
7dfc16fa 1438 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1439 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1440 netdev->name, adapter);
9d5c8243
AK		 1441 if (!err)
1442 goto request_done;
047e0030 1443
9d5c8243
AK		 1444 /* fall back to legacy interrupts */
1445 igb_reset_interrupt_capability(adapter);
7dfc16fa 1446 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1447 }
1448
c74d588e 1449 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1450 netdev->name, adapter);
9d5c8243 1451
6cb5e577 1452 if (err)
c74d588e 1453 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1454 err);
9d5c8243
AK		 1455
1456request_done:
1457 return err;
1458}
1459
1460static void igb_free_irq(struct igb_adapter *adapter)
1461{
cd14ef54 1462 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1463 int vector = 0, i;
1464
047e0030 1465 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1466
0d1ae7f4 1467 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1468 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1469 adapter->q_vector[i]);
047e0030
AD		 1470 } else {
1471 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1472 }
9d5c8243
AK		 1473}
1474
1475/**
b980ac18
JK		 1476 * igb_irq_disable - Mask off interrupt generation on the NIC
1477 * @adapter: board private structure
9d5c8243
AK		 1478 **/
1479static void igb_irq_disable(struct igb_adapter *adapter)
1480{
1481 struct e1000_hw *hw = &adapter->hw;
1482
b980ac18 1483 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1484 * mapped into these registers and so clearing the bits can cause
1485 * issues on the VF drivers so we only need to clear what we set
1486 */
cd14ef54 1487 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1488 u32 regval = rd32(E1000_EIAM);
9005df38 1489
2dfd1212
AD		 1490 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1491 wr32(E1000_EIMC, adapter->eims_enable_mask);
1492 regval = rd32(E1000_EIAC);
1493 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1494 }
844290e5
PW		 1495
1496 wr32(E1000_IAM, 0);
9d5c8243
AK		 1497 wr32(E1000_IMC, ~0);
1498 wrfl();
cd14ef54 1499 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1500 int i;
9005df38 1501
81a61859
ET		 1502 for (i = 0; i < adapter->num_q_vectors; i++)
1503 synchronize_irq(adapter->msix_entries[i].vector);
1504 } else {
1505 synchronize_irq(adapter->pdev->irq);
1506 }
9d5c8243
AK		 1507}
1508
1509/**
b980ac18
JK		 1510 * igb_irq_enable - Enable default interrupt generation settings
1511 * @adapter: board private structure
9d5c8243
AK		 1512 **/
1513static void igb_irq_enable(struct igb_adapter *adapter)
1514{
1515 struct e1000_hw *hw = &adapter->hw;
1516
cd14ef54 1517 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1518 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1519 u32 regval = rd32(E1000_EIAC);
9005df38 1520
2dfd1212
AD		 1521 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1522 regval = rd32(E1000_EIAM);
1523 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1524 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1525 if (adapter->vfs_allocated_count) {
4ae196df 1526 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1527 ims |= E1000_IMS_VMMB;
1528 }
1529 wr32(E1000_IMS, ims);
844290e5 1530 } else {
55cac248
AD		 1531 wr32(E1000_IMS, IMS_ENABLE_MASK |
1532 E1000_IMS_DRSTA);
1533 wr32(E1000_IAM, IMS_ENABLE_MASK |
1534 E1000_IMS_DRSTA);
844290e5 1535 }
9d5c8243
AK		 1536}
1537
1538static void igb_update_mng_vlan(struct igb_adapter *adapter)
1539{
51466239 1540 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1541 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1542 u16 vid = adapter->hw.mng_cookie.vlan_id;
1543 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1544
1545 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1546 /* add VID to filter table */
8b77c6b2 1547 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1548 adapter->mng_vlan_id = vid;
1549 } else {
1550 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1551 }
1552
1553 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1554 (vid != old_vid) &&
b2cb09b1 1555 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1556 /* remove VID from filter table */
8b77c6b2 1557 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1558 }
1559}
1560
1561/**
b980ac18
JK		 1562 * igb_release_hw_control - release control of the h/w to f/w
1563 * @adapter: address of board private structure
9d5c8243 1564 *
b980ac18
JK		 1565 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1566 * For ASF and Pass Through versions of f/w this means that the
1567 * driver is no longer loaded.
9d5c8243
AK		 1568 **/
1569static void igb_release_hw_control(struct igb_adapter *adapter)
1570{
1571 struct e1000_hw *hw = &adapter->hw;
1572 u32 ctrl_ext;
1573
1574 /* Let firmware take over control of h/w */
1575 ctrl_ext = rd32(E1000_CTRL_EXT);
1576 wr32(E1000_CTRL_EXT,
1577 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1578}
1579
9d5c8243 1580/**
b980ac18
JK		 1581 * igb_get_hw_control - get control of the h/w from f/w
1582 * @adapter: address of board private structure
9d5c8243 1583 *
b980ac18
JK		 1584 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1585 * For ASF and Pass Through versions of f/w this means that
1586 * the driver is loaded.
9d5c8243
AK		 1587 **/
1588static void igb_get_hw_control(struct igb_adapter *adapter)
1589{
1590 struct e1000_hw *hw = &adapter->hw;
1591 u32 ctrl_ext;
1592
1593 /* Let firmware know the driver has taken over */
1594 ctrl_ext = rd32(E1000_CTRL_EXT);
1595 wr32(E1000_CTRL_EXT,
1596 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1597}
1598
9d5c8243 1599/**
b980ac18
JK		 1600 * igb_configure - configure the hardware for RX and TX
1601 * @adapter: private board structure
9d5c8243
AK		 1602 **/
1603static void igb_configure(struct igb_adapter *adapter)
1604{
1605 struct net_device *netdev = adapter->netdev;
1606 int i;
1607
1608 igb_get_hw_control(adapter);
ff41f8dc 1609 igb_set_rx_mode(netdev);
9d5c8243
AK		 1610
1611 igb_restore_vlan(adapter);
9d5c8243 1612
85b430b4 1613 igb_setup_tctl(adapter);
06cf2666 1614 igb_setup_mrqc(adapter);
9d5c8243 1615 igb_setup_rctl(adapter);
85b430b4 1616
0e71def2 1617 igb_nfc_filter_restore(adapter);
85b430b4 1618 igb_configure_tx(adapter);
9d5c8243 1619 igb_configure_rx(adapter);
662d7205
AD		 1620
1621 igb_rx_fifo_flush_82575(&adapter->hw);
1622
c493ea45 1623 /* call igb_desc_unused which always leaves
9d5c8243 1624 * at least 1 descriptor unused to make sure
b980ac18
JK		 1625 * next_to_use != next_to_clean
1626 */
9d5c8243 1627 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1628 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1629 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1630 }
9d5c8243
AK		 1631}
1632
88a268c1 1633/**
b980ac18
JK		 1634 * igb_power_up_link - Power up the phy/serdes link
1635 * @adapter: address of board private structure
88a268c1
NN		 1636 **/
1637void igb_power_up_link(struct igb_adapter *adapter)
1638{
76886596
AA		 1639 igb_reset_phy(&adapter->hw);
1640
88a268c1
NN		 1641 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1642 igb_power_up_phy_copper(&adapter->hw);
1643 else
1644 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1645
1646 igb_setup_link(&adapter->hw);
88a268c1
NN		 1647}
1648
1649/**
b980ac18
JK		 1650 * igb_power_down_link - Power down the phy/serdes link
1651 * @adapter: address of board private structure
88a268c1
NN		 1652 */
1653static void igb_power_down_link(struct igb_adapter *adapter)
1654{
1655 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1656 igb_power_down_phy_copper_82575(&adapter->hw);
1657 else
1658 igb_shutdown_serdes_link_82575(&adapter->hw);
1659}
9d5c8243 1660
56cec249
CW		 1661/**
1662 * Detect and switch function for Media Auto Sense
1663 * @adapter: address of the board private structure
1664 **/
1665static void igb_check_swap_media(struct igb_adapter *adapter)
1666{
1667 struct e1000_hw *hw = &adapter->hw;
1668 u32 ctrl_ext, connsw;
1669 bool swap_now = false;
1670
1671 ctrl_ext = rd32(E1000_CTRL_EXT);
1672 connsw = rd32(E1000_CONNSW);
1673
1674 /* need to live swap if current media is copper and we have fiber/serdes
1675 * to go to.
1676 */
1677
1678 if ((hw->phy.media_type == e1000_media_type_copper) &&
1679 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1680 swap_now = true;
1681 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1682 /* copper signal takes time to appear */
1683 if (adapter->copper_tries < 4) {
1684 adapter->copper_tries++;
1685 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1686 wr32(E1000_CONNSW, connsw);
1687 return;
1688 } else {
1689 adapter->copper_tries = 0;
1690 if ((connsw & E1000_CONNSW_PHYSD) &&
1691 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1692 swap_now = true;
1693 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1694 wr32(E1000_CONNSW, connsw);
1695 }
1696 }
1697 }
1698
1699 if (!swap_now)
1700 return;
1701
1702 switch (hw->phy.media_type) {
1703 case e1000_media_type_copper:
1704 netdev_info(adapter->netdev,
1705 "MAS: changing media to fiber/serdes\n");
1706 ctrl_ext |=
1707 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1708 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1709 adapter->copper_tries = 0;
1710 break;
1711 case e1000_media_type_internal_serdes:
1712 case e1000_media_type_fiber:
1713 netdev_info(adapter->netdev,
1714 "MAS: changing media to copper\n");
1715 ctrl_ext &=
1716 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1717 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1718 break;
1719 default:
1720 /* shouldn't get here during regular operation */
1721 netdev_err(adapter->netdev,
1722 "AMS: Invalid media type found, returning\n");
1723 break;
1724 }
1725 wr32(E1000_CTRL_EXT, ctrl_ext);
1726}
1727
9d5c8243 1728/**
b980ac18
JK		 1729 * igb_up - Open the interface and prepare it to handle traffic
1730 * @adapter: board private structure
9d5c8243 1731 **/
9d5c8243
AK		 1732int igb_up(struct igb_adapter *adapter)
1733{
1734 struct e1000_hw *hw = &adapter->hw;
1735 int i;
1736
1737 /* hardware has been reset, we need to reload some things */
1738 igb_configure(adapter);
1739
1740 clear_bit(__IGB_DOWN, &adapter->state);
1741
0d1ae7f4
AD		 1742 for (i = 0; i < adapter->num_q_vectors; i++)
1743 napi_enable(&(adapter->q_vector[i]->napi));
1744
cd14ef54 1745 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1746 igb_configure_msix(adapter);
feeb2721
AD		 1747 else
1748 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1749
1750 /* Clear any pending interrupts. */
1751 rd32(E1000_ICR);
1752 igb_irq_enable(adapter);
1753
d4960307
AD		 1754 /* notify VFs that reset has been completed */
1755 if (adapter->vfs_allocated_count) {
1756 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1757
d4960307
AD		 1758 reg_data |= E1000_CTRL_EXT_PFRSTD;
1759 wr32(E1000_CTRL_EXT, reg_data);
1760 }
1761
4cb9be7a
JB		 1762 netif_tx_start_all_queues(adapter->netdev);
1763
25568a53
AD		 1764 /* start the watchdog. */
1765 hw->mac.get_link_status = 1;
1766 schedule_work(&adapter->watchdog_task);
1767
f4c01e96
CW		 1768 if ((adapter->flags & IGB_FLAG_EEE) &&
1769 (!hw->dev_spec._82575.eee_disable))
1770 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1771
9d5c8243
AK		 1772 return 0;
1773}
1774
1775void igb_down(struct igb_adapter *adapter)
1776{
9d5c8243 1777 struct net_device *netdev = adapter->netdev;
330a6d6a 1778 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1779 u32 tctl, rctl;
1780 int i;
1781
1782 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1783 * reschedule our watchdog timer
1784 */
9d5c8243
AK		 1785 set_bit(__IGB_DOWN, &adapter->state);
1786
1787 /* disable receives in the hardware */
1788 rctl = rd32(E1000_RCTL);
1789 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1790 /* flush and sleep below */
1791
f28ea083 1792 netif_carrier_off(netdev);
fd2ea0a7 1793 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1794
1795 /* disable transmits in the hardware */
1796 tctl = rd32(E1000_TCTL);
1797 tctl &= ~E1000_TCTL_EN;
1798 wr32(E1000_TCTL, tctl);
1799 /* flush both disables and wait for them to finish */
1800 wrfl();
0d451e79 1801 usleep_range(10000, 11000);
9d5c8243 1802
41f149a2
CW		 1803 igb_irq_disable(adapter);
1804
aa9b8cc4
AA		 1805 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1806
41f149a2 1807 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1808 if (adapter->q_vector[i]) {
1809 napi_synchronize(&adapter->q_vector[i]->napi);
1810 napi_disable(&adapter->q_vector[i]->napi);
1811 }
41f149a2 1812 }
9d5c8243 1813
9d5c8243
AK		 1814 del_timer_sync(&adapter->watchdog_timer);
1815 del_timer_sync(&adapter->phy_info_timer);
1816
04fe6358 1817 /* record the stats before reset*/
12dcd86b
ED		 1818 spin_lock(&adapter->stats64_lock);
1819 igb_update_stats(adapter, &adapter->stats64);
1820 spin_unlock(&adapter->stats64_lock);
04fe6358 1821
9d5c8243
AK		 1822 adapter->link_speed = 0;
1823 adapter->link_duplex = 0;
1824
3023682e
JK		 1825 if (!pci_channel_offline(adapter->pdev))
1826 igb_reset(adapter);
16903caa
AD		 1827
1828 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1829 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1830
9d5c8243
AK		 1831 igb_clean_all_tx_rings(adapter);
1832 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1833#ifdef CONFIG_IGB_DCA
1834
1835 /* since we reset the hardware DCA settings were cleared */
1836 igb_setup_dca(adapter);
1837#endif
9d5c8243
AK		 1838}
1839
1840void igb_reinit_locked(struct igb_adapter *adapter)
1841{
1842 WARN_ON(in_interrupt());
1843 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1844 usleep_range(1000, 2000);
9d5c8243
AK		 1845 igb_down(adapter);
1846 igb_up(adapter);
1847 clear_bit(__IGB_RESETTING, &adapter->state);
1848}
1849
56cec249
CW		 1850/** igb_enable_mas - Media Autosense re-enable after swap
1851 *
1852 * @adapter: adapter struct
1853 **/
8cfb879d 1854static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1855{
1856 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1857 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1858
1859 /* configure for SerDes media detect */
8cfb879d
TF		 1860 if ((hw->phy.media_type == e1000_media_type_copper) &&
1861 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1862 connsw |= E1000_CONNSW_ENRGSRC;
1863 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1864 wr32(E1000_CONNSW, connsw);
1865 wrfl();
56cec249 1866 }
56cec249
CW		 1867}
1868
9d5c8243
AK		 1869void igb_reset(struct igb_adapter *adapter)
1870{
090b1795 1871 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1872 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1873 struct e1000_mac_info *mac = &hw->mac;
1874 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1875 u32 pba, hwm;
9d5c8243
AK		 1876
1877 /* Repartition Pba for greater than 9k mtu
1878 * To take effect CTRL.RST is required.
1879 */
fa4dfae0 1880 switch (mac->type) {
d2ba2ed8 1881 case e1000_i350:
ceb5f13b 1882 case e1000_i354:
55cac248
AD		 1883 case e1000_82580:
1884 pba = rd32(E1000_RXPBS);
1885 pba = igb_rxpbs_adjust_82580(pba);
1886 break;
fa4dfae0 1887 case e1000_82576:
d249be54
AD		 1888 pba = rd32(E1000_RXPBS);
1889 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1890 break;
1891 case e1000_82575:
f96a8a0b
CW		 1892 case e1000_i210:
1893 case e1000_i211:
fa4dfae0
AD		 1894 default:
1895 pba = E1000_PBA_34K;
1896 break;
2d064c06 1897 }
9d5c8243 1898
45693bcb
AD		 1899 if (mac->type == e1000_82575) {
1900 u32 min_rx_space, min_tx_space, needed_tx_space;
1901
1902 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1903 wr32(E1000_PBA, pba);
1904
1905 /* To maintain wire speed transmits, the Tx FIFO should be
1906 * large enough to accommodate two full transmit packets,
1907 * rounded up to the next 1KB and expressed in KB. Likewise,
1908 * the Rx FIFO should be large enough to accommodate at least
1909 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1910 * expressed in KB.
1911 */
45693bcb
AD		 1912 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1913
1914 /* The Tx FIFO also stores 16 bytes of information about the Tx
1915 * but don't include Ethernet FCS because hardware appends it.
1916 * We only need to round down to the nearest 512 byte block
1917 * count since the value we care about is 2 frames, not 1.
b980ac18 1918 */
45693bcb
AD		 1919 min_tx_space = adapter->max_frame_size;
1920 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1921 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1922
1923 /* upper 16 bits has Tx packet buffer allocation size in KB */
1924 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1925
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1928 * allocation, take space away from current Rx allocation.
b980ac18 1929 */
45693bcb
AD		 1930 if (needed_tx_space < pba) {
1931 pba -= needed_tx_space;
9d5c8243 1932
b980ac18
JK		 1933 /* if short on Rx space, Rx wins and must trump Tx
1934 * adjustment
1935 */
9d5c8243
AK		 1936 if (pba < min_rx_space)
1937 pba = min_rx_space;
1938 }
45693bcb
AD		 1939
1940 /* adjust PBA for jumbo frames */
2d064c06 1941 wr32(E1000_PBA, pba);
9d5c8243 1942 }
9d5c8243 1943
45693bcb
AD		 1944 /* flow control settings
1945 * The high water mark must be low enough to fit one full frame
1946 * after transmitting the pause frame. As such we must have enough
1947 * space to allow for us to complete our current transmit and then
1948 * receive the frame that is in progress from the link partner.
1949 * Set it to:
1950 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1951 */
45693bcb 1952 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1953
d48507fe 1954 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1955 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1956 fc->pause_time = 0xFFFF;
1957 fc->send_xon = 1;
0cce119a 1958 fc->current_mode = fc->requested_mode;
9d5c8243 1959
4ae196df
AD		 1960 /* disable receive for all VFs and wait one second */
1961 if (adapter->vfs_allocated_count) {
1962 int i;
9005df38 1963
4ae196df 1964 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1965 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1966
1967 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1968 igb_ping_all_vfs(adapter);
4ae196df
AD		 1969
1970 /* disable transmits and receives */
1971 wr32(E1000_VFRE, 0);
1972 wr32(E1000_VFTE, 0);
1973 }
1974
9d5c8243 1975 /* Allow time for pending master requests to run */
330a6d6a 1976 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1977 wr32(E1000_WUC, 0);
1978
56cec249
CW		 1979 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1980 /* need to resetup here after media swap */
1981 adapter->ei.get_invariants(hw);
1982 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1983 }
8cfb879d
TF		 1984 if ((mac->type == e1000_82575) &&
1985 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1986 igb_enable_mas(adapter);
56cec249 1987 }
330a6d6a 1988 if (hw->mac.ops.init_hw(hw))
090b1795 1989 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1990
b980ac18 1991 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1992 * control is off when forcing speed.
1993 */
1994 if (!hw->mac.autoneg)
1995 igb_force_mac_fc(hw);
1996
b6e0c419 1997 igb_init_dmac(adapter, pba);
e428893b
CW		 1998#ifdef CONFIG_IGB_HWMON
1999 /* Re-initialize the thermal sensor on i350 devices. */
2000 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2001 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2002 /* If present, re-initialize the external thermal sensor
2003 * interface.
2004 */
2005 if (adapter->ets)
2006 mac->ops.init_thermal_sensor_thresh(hw);
2007 }
2008 }
2009#endif
b936136d 2010 /* Re-establish EEE setting */
f4c01e96
CW		 2011 if (hw->phy.media_type == e1000_media_type_copper) {
2012 switch (mac->type) {
2013 case e1000_i350:
2014 case e1000_i210:
2015 case e1000_i211:
c4c112f1 2016 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2017 break;
2018 case e1000_i354:
c4c112f1 2019 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2020 break;
2021 default:
2022 break;
2023 }
2024 }
88a268c1
NN		 2025 if (!netif_running(adapter->netdev))
2026 igb_power_down_link(adapter);
2027
9d5c8243
AK		 2028 igb_update_mng_vlan(adapter);
2029
2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2031 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2032
1f6e8178 2033 /* Re-enable PTP, where applicable. */
4f3ce71b
JK		 2034 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2035 igb_ptp_reset(adapter);
1f6e8178 2036
330a6d6a 2037 igb_get_phy_info(hw);
9d5c8243
AK		 2038}
2039
c8f44aff
MM		 2040static netdev_features_t igb_fix_features(struct net_device *netdev,
2041 netdev_features_t features)
b2cb09b1 2042{
b980ac18
JK		 2043 /* Since there is no support for separate Rx/Tx vlan accel
2044 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2045 */
f646968f
PM		 2046 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2047 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2048 else
f646968f 2049 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2050
2051 return features;
2052}
2053
c8f44aff
MM		 2054static int igb_set_features(struct net_device *netdev,
2055 netdev_features_t features)
ac52caa3 2056{
c8f44aff 2057 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2058 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2059
f646968f 2060 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2061 igb_vlan_mode(netdev, features);
2062
16903caa 2063 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2064 return 0;
2065
0e71def2
GH		 2066 if (!(features & NETIF_F_NTUPLE)) {
2067 struct hlist_node *node2;
2068 struct igb_nfc_filter *rule;
2069
2070 spin_lock(&adapter->nfc_lock);
2071 hlist_for_each_entry_safe(rule, node2,
2072 &adapter->nfc_filter_list, nfc_node) {
2073 igb_erase_filter(adapter, rule);
2074 hlist_del(&rule->nfc_node);
2075 kfree(rule);
2076 }
2077 spin_unlock(&adapter->nfc_lock);
2078 adapter->nfc_filter_count = 0;
2079 }
2080
89eaefb6
BG		 2081 netdev->features = features;
2082
2083 if (netif_running(netdev))
2084 igb_reinit_locked(adapter);
2085 else
2086 igb_reset(adapter);
2087
ac52caa3
MM		 2088 return 0;
2089}
2090
268f9d33
AD		 2091static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2092 struct net_device *dev,
2093 const unsigned char *addr, u16 vid,
2094 u16 flags)
2095{
2096 /* guarantee we can provide a unique filter for the unicast address */
2097 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2098 struct igb_adapter *adapter = netdev_priv(dev);
2099 struct e1000_hw *hw = &adapter->hw;
2100 int vfn = adapter->vfs_allocated_count;
2101 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2102
2103 if (netdev_uc_count(dev) >= rar_entries)
2104 return -ENOMEM;
2105 }
2106
2107 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2108}
2109
e10715d3
AD		 2110#define IGB_MAX_MAC_HDR_LEN 127
2111#define IGB_MAX_NETWORK_HDR_LEN 511
2112
2113static netdev_features_t
2114igb_features_check(struct sk_buff *skb, struct net_device *dev,
2115 netdev_features_t features)
2116{
2117 unsigned int network_hdr_len, mac_hdr_len;
2118
2119 /* Make certain the headers can be described by a context descriptor */
2120 mac_hdr_len = skb_network_header(skb) - skb->data;
2121 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2122 return features & ~(NETIF_F_HW_CSUM |
2123 NETIF_F_SCTP_CRC |
2124 NETIF_F_HW_VLAN_CTAG_TX |
2125 NETIF_F_TSO |
2126 NETIF_F_TSO6);
2127
2128 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2129 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2130 return features & ~(NETIF_F_HW_CSUM |
2131 NETIF_F_SCTP_CRC |
2132 NETIF_F_TSO |
2133 NETIF_F_TSO6);
2134
2135 /* We can only support IPV4 TSO in tunnels if we can mangle the
2136 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2137 */
2138 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2139 features &= ~NETIF_F_TSO;
2140
2141 return features;
2142}
2143
2e5c6922 2144static const struct net_device_ops igb_netdev_ops = {
559e9c49 2145 .ndo_open = igb_open,
2e5c6922 2146 .ndo_stop = igb_close,
cd392f5c 2147 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2148 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2149 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2150 .ndo_set_mac_address = igb_set_mac,
2151 .ndo_change_mtu = igb_change_mtu,
2152 .ndo_do_ioctl = igb_ioctl,
2153 .ndo_tx_timeout = igb_tx_timeout,
2154 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2155 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2156 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2157 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2158 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2159 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2160 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2161 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2162#ifdef CONFIG_NET_POLL_CONTROLLER
2163 .ndo_poll_controller = igb_netpoll,
2164#endif
b2cb09b1
JP		 2165 .ndo_fix_features = igb_fix_features,
2166 .ndo_set_features = igb_set_features,
268f9d33 2167 .ndo_fdb_add = igb_ndo_fdb_add,
e10715d3 2168 .ndo_features_check = igb_features_check,
2e5c6922
SH		 2169};
2170
d67974f0
CW		 2171/**
2172 * igb_set_fw_version - Configure version string for ethtool
2173 * @adapter: adapter struct
d67974f0
CW		 2174 **/
2175void igb_set_fw_version(struct igb_adapter *adapter)
2176{
2177 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2178 struct e1000_fw_version fw;
2179
2180 igb_get_fw_version(hw, &fw);
2181
2182 switch (hw->mac.type) {
7dc98a62 2183 case e1000_i210:
0b1a6f2e 2184 case e1000_i211:
7dc98a62
CW		 2185 if (!(igb_get_flash_presence_i210(hw))) {
2186 snprintf(adapter->fw_version,
2187 sizeof(adapter->fw_version),
2188 "%2d.%2d-%d",
2189 fw.invm_major, fw.invm_minor,
2190 fw.invm_img_type);
2191 break;
2192 }
2193 /* fall through */
0b1a6f2e
CW		 2194 default:
2195 /* if option is rom valid, display its version too */
2196 if (fw.or_valid) {
2197 snprintf(adapter->fw_version,
2198 sizeof(adapter->fw_version),
2199 "%d.%d, 0x%08x, %d.%d.%d",
2200 fw.eep_major, fw.eep_minor, fw.etrack_id,
2201 fw.or_major, fw.or_build, fw.or_patch);
2202 /* no option rom */
7dc98a62 2203 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2204 snprintf(adapter->fw_version,
7dc98a62
CW		 2205 sizeof(adapter->fw_version),
2206 "%d.%d, 0x%08x",
2207 fw.eep_major, fw.eep_minor, fw.etrack_id);
2208 } else {
2209 snprintf(adapter->fw_version,
2210 sizeof(adapter->fw_version),
2211 "%d.%d.%d",
2212 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2213 }
2214 break;
d67974f0 2215 }
d67974f0
CW		 2216}
2217
56cec249
CW		 2218/**
2219 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2220 *
2221 * @adapter: adapter struct
2222 **/
2223static void igb_init_mas(struct igb_adapter *adapter)
2224{
2225 struct e1000_hw *hw = &adapter->hw;
2226 u16 eeprom_data;
2227
2228 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2229 switch (hw->bus.func) {
2230 case E1000_FUNC_0:
2231 if (eeprom_data & IGB_MAS_ENABLE_0) {
2232 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2233 netdev_info(adapter->netdev,
2234 "MAS: Enabling Media Autosense for port %d\n",
2235 hw->bus.func);
2236 }
2237 break;
2238 case E1000_FUNC_1:
2239 if (eeprom_data & IGB_MAS_ENABLE_1) {
2240 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2241 netdev_info(adapter->netdev,
2242 "MAS: Enabling Media Autosense for port %d\n",
2243 hw->bus.func);
2244 }
2245 break;
2246 case E1000_FUNC_2:
2247 if (eeprom_data & IGB_MAS_ENABLE_2) {
2248 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2249 netdev_info(adapter->netdev,
2250 "MAS: Enabling Media Autosense for port %d\n",
2251 hw->bus.func);
2252 }
2253 break;
2254 case E1000_FUNC_3:
2255 if (eeprom_data & IGB_MAS_ENABLE_3) {
2256 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2257 netdev_info(adapter->netdev,
2258 "MAS: Enabling Media Autosense for port %d\n",
2259 hw->bus.func);
2260 }
2261 break;
2262 default:
2263 /* Shouldn't get here */
2264 netdev_err(adapter->netdev,
2265 "MAS: Invalid port configuration, returning\n");
2266 break;
2267 }
2268}
2269
b980ac18
JK		 2270/**
2271 * igb_init_i2c - Init I2C interface
441fc6fd 2272 * @adapter: pointer to adapter structure
b980ac18 2273 **/
441fc6fd
CW		 2274static s32 igb_init_i2c(struct igb_adapter *adapter)
2275{
23d87824 2276 s32 status = 0;
441fc6fd
CW		 2277
2278 /* I2C interface supported on i350 devices */
2279 if (adapter->hw.mac.type != e1000_i350)
23d87824 2280 return 0;
441fc6fd
CW		 2281
2282 /* Initialize the i2c bus which is controlled by the registers.
2283 * This bus will use the i2c_algo_bit structue that implements
2284 * the protocol through toggling of the 4 bits in the register.
2285 */
2286 adapter->i2c_adap.owner = THIS_MODULE;
2287 adapter->i2c_algo = igb_i2c_algo;
2288 adapter->i2c_algo.data = adapter;
2289 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2290 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2291 strlcpy(adapter->i2c_adap.name, "igb BB",
2292 sizeof(adapter->i2c_adap.name));
2293 status = i2c_bit_add_bus(&adapter->i2c_adap);
2294 return status;
2295}
2296
9d5c8243 2297/**
b980ac18
JK		 2298 * igb_probe - Device Initialization Routine
2299 * @pdev: PCI device information struct
2300 * @ent: entry in igb_pci_tbl
9d5c8243 2301 *
b980ac18 2302 * Returns 0 on success, negative on failure
9d5c8243 2303 *
b980ac18
JK		 2304 * igb_probe initializes an adapter identified by a pci_dev structure.
2305 * The OS initialization, configuring of the adapter private structure,
2306 * and a hardware reset occur.
9d5c8243 2307 **/
1dd06ae8 2308static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2309{
2310 struct net_device *netdev;
2311 struct igb_adapter *adapter;
2312 struct e1000_hw *hw;
4337e993 2313 u16 eeprom_data = 0;
9835fd73 2314 s32 ret_val;
4337e993 2315 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2316 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2317 int err, pci_using_dac;
9835fd73 2318 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2319
bded64a7
AG		 2320 /* Catch broken hardware that put the wrong VF device ID in
2321 * the PCIe SR-IOV capability.
2322 */
2323 if (pdev->is_virtfn) {
2324 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2325 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2326 return -EINVAL;
2327 }
2328
aed5dec3 2329 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2330 if (err)
2331 return err;
2332
2333 pci_using_dac = 0;
dc4ff9bb 2334 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2335 if (!err) {
dc4ff9bb 2336 pci_using_dac = 1;
9d5c8243 2337 } else {
dc4ff9bb 2338 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2339 if (err) {
dc4ff9bb
RK		 2340 dev_err(&pdev->dev,
2341 "No usable DMA configuration, aborting\n");
2342 goto err_dma;
9d5c8243
AK		 2343 }
2344 }
2345
56d766d6 2346 err = pci_request_mem_regions(pdev, igb_driver_name);
9d5c8243
AK		 2347 if (err)
2348 goto err_pci_reg;
2349
19d5afd4 2350 pci_enable_pcie_error_reporting(pdev);
40a914fa 2351
9d5c8243 2352 pci_set_master(pdev);
c682fc23 2353 pci_save_state(pdev);
9d5c8243
AK		 2354
2355 err = -ENOMEM;
1bfaf07b 2356 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2357 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2358 if (!netdev)
2359 goto err_alloc_etherdev;
2360
2361 SET_NETDEV_DEV(netdev, &pdev->dev);
2362
2363 pci_set_drvdata(pdev, netdev);
2364 adapter = netdev_priv(netdev);
2365 adapter->netdev = netdev;
2366 adapter->pdev = pdev;
2367 hw = &adapter->hw;
2368 hw->back = adapter;
b3f4d599 2369 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2370
9d5c8243 2371 err = -EIO;
73bf8048
JW		 2372 adapter->io_addr = pci_iomap(pdev, 0, 0);
2373 if (!adapter->io_addr)
9d5c8243 2374 goto err_ioremap;
73bf8048
JW		 2375 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2376 hw->hw_addr = adapter->io_addr;
9d5c8243 2377
2e5c6922 2378 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2379 igb_set_ethtool_ops(netdev);
9d5c8243 2380 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2381
2382 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2383
89dbefb2
AS		 2384 netdev->mem_start = pci_resource_start(pdev, 0);
2385 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2386
9d5c8243
AK		 2387 /* PCI config space info */
2388 hw->vendor_id = pdev->vendor;
2389 hw->device_id = pdev->device;
2390 hw->revision_id = pdev->revision;
2391 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2392 hw->subsystem_device_id = pdev->subsystem_device;
2393
9d5c8243
AK		 2394 /* Copy the default MAC, PHY and NVM function pointers */
2395 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2396 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2397 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2398 /* Initialize skew-specific constants */
2399 err = ei->get_invariants(hw);
2400 if (err)
450c87c8 2401 goto err_sw_init;
9d5c8243 2402
450c87c8 2403 /* setup the private structure */
9d5c8243
AK		 2404 err = igb_sw_init(adapter);
2405 if (err)
2406 goto err_sw_init;
2407
2408 igb_get_bus_info_pcie(hw);
2409
2410 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2411
2412 /* Copper options */
2413 if (hw->phy.media_type == e1000_media_type_copper) {
2414 hw->phy.mdix = AUTO_ALL_MODES;
2415 hw->phy.disable_polarity_correction = false;
2416 hw->phy.ms_type = e1000_ms_hw_default;
2417 }
2418
2419 if (igb_check_reset_block(hw))
2420 dev_info(&pdev->dev,
2421 "PHY reset is blocked due to SOL/IDER session.\n");
2422
b980ac18 2423 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2424 * set by igb_sw_init so we should use an or instead of an
2425 * assignment.
2426 */
2427 netdev->features |= NETIF_F_SG |
077887c3
AD		 2428 NETIF_F_TSO |
2429 NETIF_F_TSO6 |
2430 NETIF_F_RXHASH |
2431 NETIF_F_RXCSUM |
e10715d3 2432 NETIF_F_HW_CSUM;
077887c3 2433
6e033700
AD		 2434 if (hw->mac.type >= e1000_82576)
2435 netdev->features |= NETIF_F_SCTP_CRC;
2436
e10715d3
AD		 2437#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2438 NETIF_F_GSO_GRE_CSUM | \
7e13318d 2439 NETIF_F_GSO_IPXIP4 | \
bf2d1df3 2440 NETIF_F_GSO_IPXIP6 | \
e10715d3
AD		 2441 NETIF_F_GSO_UDP_TUNNEL | \
2442 NETIF_F_GSO_UDP_TUNNEL_CSUM)
2443
2444 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
2445 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
2446
077887c3 2447 /* copy netdev features into list of user selectable features */
e10715d3
AD		 2448 netdev->hw_features |= netdev->features |
2449 NETIF_F_HW_VLAN_CTAG_RX |
2450 NETIF_F_HW_VLAN_CTAG_TX |
2451 NETIF_F_RXALL;
077887c3 2452
6e033700
AD		 2453 if (hw->mac.type >= e1000_i350)
2454 netdev->hw_features |= NETIF_F_NTUPLE;
2455
e10715d3
AD		 2456 if (pci_using_dac)
2457 netdev->features |= NETIF_F_HIGHDMA;
6e033700 2458
e10715d3 2459 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
6e033700 2460 netdev->mpls_features |= NETIF_F_HW_CSUM;
e10715d3 2461 netdev->hw_enc_features |= netdev->vlan_features;
48f29ffc 2462
e10715d3
AD		 2463 /* set this bit last since it cannot be part of vlan_features */
2464 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2465 NETIF_F_HW_VLAN_CTAG_RX |
2466 NETIF_F_HW_VLAN_CTAG_TX;
6b8f0922 2467
e10715d3 2468 netdev->priv_flags |= IFF_SUPP_NOFCS;
9d5c8243 2469
01789349
JP		 2470 netdev->priv_flags |= IFF_UNICAST_FLT;
2471
91c527a5
JW		 2472 /* MTU range: 68 - 9216 */
2473 netdev->min_mtu = ETH_MIN_MTU;
2474 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
2475
330a6d6a 2476 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2477
2478 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2479 * known good starting state
2480 */
9d5c8243
AK		 2481 hw->mac.ops.reset_hw(hw);
2482
ef3a0092
CW		 2483 /* make sure the NVM is good , i211/i210 parts can have special NVM
2484 * that doesn't contain a checksum
f96a8a0b 2485 */
ef3a0092
CW		 2486 switch (hw->mac.type) {
2487 case e1000_i210:
2488 case e1000_i211:
2489 if (igb_get_flash_presence_i210(hw)) {
2490 if (hw->nvm.ops.validate(hw) < 0) {
2491 dev_err(&pdev->dev,
2492 "The NVM Checksum Is Not Valid\n");
2493 err = -EIO;
2494 goto err_eeprom;
2495 }
2496 }
2497 break;
2498 default:
f96a8a0b
CW		 2499 if (hw->nvm.ops.validate(hw) < 0) {
2500 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2501 err = -EIO;
2502 goto err_eeprom;
2503 }
ef3a0092 2504 break;
9d5c8243
AK		 2505 }
2506
806ffb1d
JH		 2507 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
2508 /* copy the MAC address out of the NVM */
2509 if (hw->mac.ops.read_mac_addr(hw))
2510 dev_err(&pdev->dev, "NVM Read Error\n");
2511 }
9d5c8243
AK		 2512
2513 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2514
aaeb6cdf 2515 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2516 dev_err(&pdev->dev, "Invalid MAC Address\n");
2517 err = -EIO;
2518 goto err_eeprom;
2519 }
2520
d67974f0
CW		 2521 /* get firmware version for ethtool -i */
2522 igb_set_fw_version(adapter);
2523
27dff8b2
TF		 2524 /* configure RXPBSIZE and TXPBSIZE */
2525 if (hw->mac.type == e1000_i210) {
2526 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2527 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2528 }
2529
c061b18d 2530 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2531 (unsigned long) adapter);
c061b18d 2532 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2533 (unsigned long) adapter);
9d5c8243
AK		 2534
2535 INIT_WORK(&adapter->reset_task, igb_reset_task);
2536 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2537
450c87c8 2538 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2539 adapter->fc_autoneg = true;
2540 hw->mac.autoneg = true;
2541 hw->phy.autoneg_advertised = 0x2f;
2542
0cce119a
AD		 2543 hw->fc.requested_mode = e1000_fc_default;
2544 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2545
9d5c8243
AK		 2546 igb_validate_mdi_setting(hw);
2547
63d4a8f9 2548 /* By default, support wake on port A */
a2cf8b6c 2549 if (hw->bus.func == 0)
63d4a8f9
MV		 2550 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2551
2552 /* Check the NVM for wake support on non-port A ports */
2553 if (hw->mac.type >= e1000_82580)
55cac248 2554 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2555 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2556 &eeprom_data);
a2cf8b6c
AD		 2557 else if (hw->bus.func == 1)
2558 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2559
63d4a8f9
MV		 2560 if (eeprom_data & IGB_EEPROM_APME)
2561 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2562
2563 /* now that we have the eeprom settings, apply the special cases where
2564 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2565 * lan on a particular port
2566 */
9d5c8243
AK		 2567 switch (pdev->device) {
2568 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2569 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2570 break;
2571 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2572 case E1000_DEV_ID_82576_FIBER:
2573 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2574 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2575 * regardless of eeprom setting
2576 */
9d5c8243 2577 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2578 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2579 break;
c8ea5ea9 2580 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2581 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2582 /* if quad port adapter, disable WoL on all but port A */
2583 if (global_quad_port_a != 0)
63d4a8f9 2584 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2585 else
2586 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2587 /* Reset for multiple quad port adapters */
2588 if (++global_quad_port_a == 4)
2589 global_quad_port_a = 0;
2590 break;
63d4a8f9
MV		 2591 default:
2592 /* If the device can't wake, don't set software support */
2593 if (!device_can_wakeup(&adapter->pdev->dev))
2594 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2595 }
2596
2597 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2598 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2599 adapter->wol |= E1000_WUFC_MAG;
2600
2601 /* Some vendors want WoL disabled by default, but still supported */
2602 if ((hw->mac.type == e1000_i350) &&
2603 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2604 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2605 adapter->wol = 0;
2606 }
2607
5e350b92
TF		 2608 /* Some vendors want the ability to Use the EEPROM setting as
2609 * enable/disable only, and not for capability
2610 */
2611 if (((hw->mac.type == e1000_i350) ||
2612 (hw->mac.type == e1000_i354)) &&
2613 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2614 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2615 adapter->wol = 0;
2616 }
2617 if (hw->mac.type == e1000_i350) {
2618 if (((pdev->subsystem_device == 0x5001) ||
2619 (pdev->subsystem_device == 0x5002)) &&
2620 (hw->bus.func == 0)) {
2621 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2622 adapter->wol = 0;
2623 }
2624 if (pdev->subsystem_device == 0x1F52)
2625 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2626 }
2627
63d4a8f9
MV		 2628 device_set_wakeup_enable(&adapter->pdev->dev,
2629 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2630
2631 /* reset the hardware with the new settings */
2632 igb_reset(adapter);
2633
441fc6fd
CW		 2634 /* Init the I2C interface */
2635 err = igb_init_i2c(adapter);
2636 if (err) {
2637 dev_err(&pdev->dev, "failed to init i2c interface\n");
2638 goto err_eeprom;
2639 }
2640
9d5c8243 2641 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2642 * driver.
2643 */
9d5c8243
AK		 2644 igb_get_hw_control(adapter);
2645
9d5c8243
AK		 2646 strcpy(netdev->name, "eth%d");
2647 err = register_netdev(netdev);
2648 if (err)
2649 goto err_register;
2650
b168dfc5
JB		 2651 /* carrier off reporting is important to ethtool even BEFORE open */
2652 netif_carrier_off(netdev);
2653
421e02f0 2654#ifdef CONFIG_IGB_DCA
bbd98fe4 2655 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2656 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2657 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2658 igb_setup_dca(adapter);
2659 }
fe4506b6 2660
38c845c7 2661#endif
e428893b
CW		 2662#ifdef CONFIG_IGB_HWMON
2663 /* Initialize the thermal sensor on i350 devices. */
2664 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2665 u16 ets_word;
3c89f6d0 2666
b980ac18 2667 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2668 * external thermal sensor.
2669 */
2670 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2671 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2672 adapter->ets = true;
2673 else
2674 adapter->ets = false;
2675 if (igb_sysfs_init(adapter))
2676 dev_err(&pdev->dev,
2677 "failed to allocate sysfs resources\n");
2678 } else {
2679 adapter->ets = false;
2680 }
2681#endif
56cec249
CW		 2682 /* Check if Media Autosense is enabled */
2683 adapter->ei = *ei;
2684 if (hw->dev_spec._82575.mas_capable)
2685 igb_init_mas(adapter);
2686
673b8b70 2687 /* do hw tstamp init after resetting */
7ebae817 2688 igb_ptp_init(adapter);
673b8b70 2689
9d5c8243 2690 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2691 /* print bus type/speed/width info, not applicable to i354 */
2692 if (hw->mac.type != e1000_i354) {
2693 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2694 netdev->name,
2695 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2696 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2697 "unknown"),
2698 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2699 "Width x4" :
2700 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2701 "Width x2" :
2702 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2703 "Width x1" : "unknown"), netdev->dev_addr);
2704 }
9d5c8243 2705
53ea6c7e
TF		 2706 if ((hw->mac.type >= e1000_i210 ||
2707 igb_get_flash_presence_i210(hw))) {
2708 ret_val = igb_read_part_string(hw, part_str,
2709 E1000_PBANUM_LENGTH);
2710 } else {
2711 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2712 }
2713
9835fd73
CW		 2714 if (ret_val)
2715 strcpy(part_str, "Unknown");
2716 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2717 dev_info(&pdev->dev,
2718 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2719 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2720 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2721 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2722 if (hw->phy.media_type == e1000_media_type_copper) {
2723 switch (hw->mac.type) {
2724 case e1000_i350:
2725 case e1000_i210:
2726 case e1000_i211:
2727 /* Enable EEE for internal copper PHY devices */
c4c112f1 2728 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2729 if ((!err) &&
2730 (!hw->dev_spec._82575.eee_disable)) {
2731 adapter->eee_advert =
2732 MDIO_EEE_100TX | MDIO_EEE_1000T;
2733 adapter->flags |= IGB_FLAG_EEE;
2734 }
2735 break;
2736 case e1000_i354:
ceb5f13b 2737 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2738 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2739 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2740 if ((!err) &&
2741 (!hw->dev_spec._82575.eee_disable)) {
2742 adapter->eee_advert =
2743 MDIO_EEE_100TX | MDIO_EEE_1000T;
2744 adapter->flags |= IGB_FLAG_EEE;
2745 }
2746 }
2747 break;
2748 default:
2749 break;
ceb5f13b 2750 }
09b068d4 2751 }
749ab2cd 2752 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2753 return 0;
2754
2755err_register:
2756 igb_release_hw_control(adapter);
441fc6fd 2757 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2758err_eeprom:
2759 if (!igb_check_reset_block(hw))
f5f4cf08 2760 igb_reset_phy(hw);
9d5c8243
AK		 2761
2762 if (hw->flash_address)
2763 iounmap(hw->flash_address);
9d5c8243 2764err_sw_init:
42ad1a03 2765 kfree(adapter->shadow_vfta);
047e0030 2766 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2767#ifdef CONFIG_PCI_IOV
2768 igb_disable_sriov(pdev);
2769#endif
73bf8048 2770 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2771err_ioremap:
2772 free_netdev(netdev);
2773err_alloc_etherdev:
56d766d6 2774 pci_release_mem_regions(pdev);
9d5c8243
AK		 2775err_pci_reg:
2776err_dma:
2777 pci_disable_device(pdev);
2778 return err;
2779}
2780
fa44f2f1 2781#ifdef CONFIG_PCI_IOV
781798a1 2782static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2783{
2784 struct net_device *netdev = pci_get_drvdata(pdev);
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786 struct e1000_hw *hw = &adapter->hw;
2787
2788 /* reclaim resources allocated to VFs */
2789 if (adapter->vf_data) {
2790 /* disable iov and allow time for transactions to clear */
b09186d2 2791 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2792 dev_warn(&pdev->dev,
2793 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2794 return -EPERM;
2795 } else {
2796 pci_disable_sriov(pdev);
2797 msleep(500);
2798 }
2799
2800 kfree(adapter->vf_data);
2801 adapter->vf_data = NULL;
2802 adapter->vfs_allocated_count = 0;
2803 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2804 wrfl();
2805 msleep(100);
2806 dev_info(&pdev->dev, "IOV Disabled\n");
2807
2808 /* Re-enable DMA Coalescing flag since IOV is turned off */
2809 adapter->flags |= IGB_FLAG_DMAC;
2810 }
2811
2812 return 0;
2813}
2814
2815static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2816{
2817 struct net_device *netdev = pci_get_drvdata(pdev);
2818 struct igb_adapter *adapter = netdev_priv(netdev);
2819 int old_vfs = pci_num_vf(pdev);
2820 int err = 0;
2821 int i;
2822
cd14ef54 2823 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2824 err = -EPERM;
2825 goto out;
2826 }
fa44f2f1
GR		 2827 if (!num_vfs)
2828 goto out;
fa44f2f1 2829
781798a1
SA		 2830 if (old_vfs) {
2831 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2832 old_vfs, max_vfs);
2833 adapter->vfs_allocated_count = old_vfs;
2834 } else
2835 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2836
2837 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2838 sizeof(struct vf_data_storage), GFP_KERNEL);
2839
2840 /* if allocation failed then we do not support SR-IOV */
2841 if (!adapter->vf_data) {
2842 adapter->vfs_allocated_count = 0;
2843 dev_err(&pdev->dev,
2844 "Unable to allocate memory for VF Data Storage\n");
2845 err = -ENOMEM;
2846 goto out;
2847 }
2848
781798a1
SA		 2849 /* only call pci_enable_sriov() if no VFs are allocated already */
2850 if (!old_vfs) {
2851 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2852 if (err)
2853 goto err_out;
2854 }
fa44f2f1
GR		 2855 dev_info(&pdev->dev, "%d VFs allocated\n",
2856 adapter->vfs_allocated_count);
2857 for (i = 0; i < adapter->vfs_allocated_count; i++)
2858 igb_vf_configure(adapter, i);
2859
2860 /* DMA Coalescing is not supported in IOV mode. */
2861 adapter->flags &= ~IGB_FLAG_DMAC;
2862 goto out;
2863
2864err_out:
2865 kfree(adapter->vf_data);
2866 adapter->vf_data = NULL;
2867 adapter->vfs_allocated_count = 0;
2868out:
2869 return err;
2870}
2871
2872#endif
b980ac18 2873/**
441fc6fd
CW		 2874 * igb_remove_i2c - Cleanup I2C interface
2875 * @adapter: pointer to adapter structure
b980ac18 2876 **/
441fc6fd
CW		 2877static void igb_remove_i2c(struct igb_adapter *adapter)
2878{
441fc6fd
CW		 2879 /* free the adapter bus structure */
2880 i2c_del_adapter(&adapter->i2c_adap);
2881}
2882
9d5c8243 2883/**
b980ac18
JK		 2884 * igb_remove - Device Removal Routine
2885 * @pdev: PCI device information struct
9d5c8243 2886 *
b980ac18
JK		 2887 * igb_remove is called by the PCI subsystem to alert the driver
2888 * that it should release a PCI device. The could be caused by a
2889 * Hot-Plug event, or because the driver is going to be removed from
2890 * memory.
9d5c8243 2891 **/
9f9a12f8 2892static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2893{
2894 struct net_device *netdev = pci_get_drvdata(pdev);
2895 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2896 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2897
749ab2cd 2898 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2899#ifdef CONFIG_IGB_HWMON
2900 igb_sysfs_exit(adapter);
2901#endif
441fc6fd 2902 igb_remove_i2c(adapter);
a79f4f88 2903 igb_ptp_stop(adapter);
b980ac18 2904 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2905 * disable watchdog from being rescheduled.
2906 */
9d5c8243
AK		 2907 set_bit(__IGB_DOWN, &adapter->state);
2908 del_timer_sync(&adapter->watchdog_timer);
2909 del_timer_sync(&adapter->phy_info_timer);
2910
760141a5
TH		 2911 cancel_work_sync(&adapter->reset_task);
2912 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2913
421e02f0 2914#ifdef CONFIG_IGB_DCA
7dfc16fa 2915 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2916 dev_info(&pdev->dev, "DCA disabled\n");
2917 dca_remove_requester(&pdev->dev);
7dfc16fa 2918 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2919 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2920 }
2921#endif
2922
9d5c8243 2923 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2924 * would have already happened in close and is redundant.
2925 */
9d5c8243
AK		 2926 igb_release_hw_control(adapter);
2927
37680117 2928#ifdef CONFIG_PCI_IOV
fa44f2f1 2929 igb_disable_sriov(pdev);
37680117 2930#endif
559e9c49 2931
c23d92b8
AW		 2932 unregister_netdev(netdev);
2933
2934 igb_clear_interrupt_scheme(adapter);
2935
73bf8048 2936 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2937 if (hw->flash_address)
2938 iounmap(hw->flash_address);
56d766d6 2939 pci_release_mem_regions(pdev);
9d5c8243 2940
1128c756 2941 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2942 free_netdev(netdev);
2943
19d5afd4 2944 pci_disable_pcie_error_reporting(pdev);
40a914fa 2945
9d5c8243
AK		 2946 pci_disable_device(pdev);
2947}
2948
a6b623e0 2949/**
b980ac18
JK		 2950 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2951 * @adapter: board private structure to initialize
a6b623e0 2952 *
b980ac18
JK		 2953 * This function initializes the vf specific data storage and then attempts to
2954 * allocate the VFs. The reason for ordering it this way is because it is much
2955 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2956 * the memory for the VFs.
a6b623e0 2957 **/
9f9a12f8 2958static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2959{
2960#ifdef CONFIG_PCI_IOV
2961 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2962 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2963
f96a8a0b
CW		 2964 /* Virtualization features not supported on i210 family. */
2965 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2966 return;
2967
be06998f
JB		 2968 /* Of the below we really only want the effect of getting
2969 * IGB_FLAG_HAS_MSIX set (if available), without which
2970 * igb_enable_sriov() has no effect.
2971 */
2972 igb_set_interrupt_capability(adapter, true);
2973 igb_reset_interrupt_capability(adapter);
2974
fa44f2f1 2975 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2976 igb_enable_sriov(pdev, max_vfs);
0224d663 2977
a6b623e0
AD		 2978#endif /* CONFIG_PCI_IOV */
2979}
2980
fa44f2f1 2981static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2982{
2983 struct e1000_hw *hw = &adapter->hw;
374a542d 2984 u32 max_rss_queues;
9d5c8243 2985
374a542d 2986 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2987 switch (hw->mac.type) {
374a542d
MV		 2988 case e1000_i211:
2989 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2990 break;
2991 case e1000_82575:
f96a8a0b 2992 case e1000_i210:
374a542d
MV		 2993 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2994 break;
2995 case e1000_i350:
2996 /* I350 cannot do RSS and SR-IOV at the same time */
2997 if (!!adapter->vfs_allocated_count) {
2998 max_rss_queues = 1;
2999 break;
3000 }
3001 /* fall through */
3002 case e1000_82576:
3003 if (!!adapter->vfs_allocated_count) {
3004 max_rss_queues = 2;
3005 break;
3006 }
3007 /* fall through */
3008 case e1000_82580:
ceb5f13b 3009 case e1000_i354:
374a542d
MV		 3010 default:
3011 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 3012 break;
374a542d
MV		 3013 }
3014
3015 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3016
72ddef05
SS		 3017 igb_set_flag_queue_pairs(adapter, max_rss_queues);
3018}
3019
3020void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3021 const u32 max_rss_queues)
3022{
3023 struct e1000_hw *hw = &adapter->hw;
3024
374a542d
MV		 3025 /* Determine if we need to pair queues. */
3026 switch (hw->mac.type) {
3027 case e1000_82575:
f96a8a0b 3028 case e1000_i211:
374a542d 3029 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 3030 break;
374a542d 3031 case e1000_82576:
374a542d
MV		 3032 case e1000_82580:
3033 case e1000_i350:
ceb5f13b 3034 case e1000_i354:
374a542d 3035 case e1000_i210:
f96a8a0b 3036 default:
b980ac18 3037 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 3038 * order to conserve interrupts due to limited supply.
3039 */
3040 if (adapter->rss_queues > (max_rss_queues / 2))
3041 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 3042 else
3043 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 3044 break;
3045 }
fa44f2f1
GR		 3046}
3047
3048/**
b980ac18
JK		 3049 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3050 * @adapter: board private structure to initialize
fa44f2f1 3051 *
b980ac18
JK		 3052 * igb_sw_init initializes the Adapter private data structure.
3053 * Fields are initialized based on PCI device information and
3054 * OS network device settings (MTU size).
fa44f2f1
GR		 3055 **/
3056static int igb_sw_init(struct igb_adapter *adapter)
3057{
3058 struct e1000_hw *hw = &adapter->hw;
3059 struct net_device *netdev = adapter->netdev;
3060 struct pci_dev *pdev = adapter->pdev;
3061
3062 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3063
3064 /* set default ring sizes */
3065 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3066 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3067
3068 /* set default ITR values */
3069 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3070 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3071
3072 /* set default work limits */
3073 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3074
3075 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3076 VLAN_HLEN;
3077 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3078
0e71def2 3079 spin_lock_init(&adapter->nfc_lock);
fa44f2f1
GR		 3080 spin_lock_init(&adapter->stats64_lock);
3081#ifdef CONFIG_PCI_IOV
3082 switch (hw->mac.type) {
3083 case e1000_82576:
3084 case e1000_i350:
3085 if (max_vfs > 7) {
3086 dev_warn(&pdev->dev,
3087 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 3088 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 3089 } else
3090 adapter->vfs_allocated_count = max_vfs;
3091 if (adapter->vfs_allocated_count)
3092 dev_warn(&pdev->dev,
3093 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3094 break;
3095 default:
3096 break;
3097 }
3098#endif /* CONFIG_PCI_IOV */
3099
cbfe360a
SA		 3100 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3101 adapter->flags |= IGB_FLAG_HAS_MSIX;
3102
ceee3450
TF		 3103 igb_probe_vfs(adapter);
3104
fa44f2f1 3105 igb_init_queue_configuration(adapter);
a99955fc 3106
1128c756 3107 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3108 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3109 GFP_ATOMIC);
1128c756 3110
a6b623e0 3111 /* This call may decrease the number of queues */
53c7d064 3112 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3113 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3114 return -ENOMEM;
3115 }
3116
3117 /* Explicitly disable IRQ since the NIC can be in any state. */
3118 igb_irq_disable(adapter);
3119
f96a8a0b 3120 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3121 adapter->flags &= ~IGB_FLAG_DMAC;
3122
9d5c8243
AK		 3123 set_bit(__IGB_DOWN, &adapter->state);
3124 return 0;
3125}
3126
3127/**
b980ac18
JK		 3128 * igb_open - Called when a network interface is made active
3129 * @netdev: network interface device structure
9d5c8243 3130 *
b980ac18 3131 * Returns 0 on success, negative value on failure
9d5c8243 3132 *
b980ac18
JK		 3133 * The open entry point is called when a network interface is made
3134 * active by the system (IFF_UP). At this point all resources needed
3135 * for transmit and receive operations are allocated, the interrupt
3136 * handler is registered with the OS, the watchdog timer is started,
3137 * and the stack is notified that the interface is ready.
9d5c8243 3138 **/
749ab2cd 3139static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3140{
3141 struct igb_adapter *adapter = netdev_priv(netdev);
3142 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3143 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3144 int err;
3145 int i;
3146
3147 /* disallow open during test */
749ab2cd
YZ		 3148 if (test_bit(__IGB_TESTING, &adapter->state)) {
3149 WARN_ON(resuming);
9d5c8243 3150 return -EBUSY;
749ab2cd
YZ		 3151 }
3152
3153 if (!resuming)
3154 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3155
b168dfc5
JB		 3156 netif_carrier_off(netdev);
3157
9d5c8243
AK		 3158 /* allocate transmit descriptors */
3159 err = igb_setup_all_tx_resources(adapter);
3160 if (err)
3161 goto err_setup_tx;
3162
3163 /* allocate receive descriptors */
3164 err = igb_setup_all_rx_resources(adapter);
3165 if (err)
3166 goto err_setup_rx;
3167
88a268c1 3168 igb_power_up_link(adapter);
9d5c8243 3169
9d5c8243
AK		 3170 /* before we allocate an interrupt, we must be ready to handle it.
3171 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3172 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3173 * clean_rx handler before we do so.
3174 */
9d5c8243
AK		 3175 igb_configure(adapter);
3176
3177 err = igb_request_irq(adapter);
3178 if (err)
3179 goto err_req_irq;
3180
0c2cc02e
AD		 3181 /* Notify the stack of the actual queue counts. */
3182 err = netif_set_real_num_tx_queues(adapter->netdev,
3183 adapter->num_tx_queues);
3184 if (err)
3185 goto err_set_queues;
3186
3187 err = netif_set_real_num_rx_queues(adapter->netdev,
3188 adapter->num_rx_queues);
3189 if (err)
3190 goto err_set_queues;
3191
9d5c8243
AK		 3192 /* From here on the code is the same as igb_up() */
3193 clear_bit(__IGB_DOWN, &adapter->state);
3194
0d1ae7f4
AD		 3195 for (i = 0; i < adapter->num_q_vectors; i++)
3196 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3197
3198 /* Clear any pending interrupts. */
3199 rd32(E1000_ICR);
844290e5
PW		 3200
3201 igb_irq_enable(adapter);
3202
d4960307
AD		 3203 /* notify VFs that reset has been completed */
3204 if (adapter->vfs_allocated_count) {
3205 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3206
d4960307
AD		 3207 reg_data |= E1000_CTRL_EXT_PFRSTD;
3208 wr32(E1000_CTRL_EXT, reg_data);
3209 }
3210
d55b53ff
JK		 3211 netif_tx_start_all_queues(netdev);
3212
749ab2cd
YZ		 3213 if (!resuming)
3214 pm_runtime_put(&pdev->dev);
3215
25568a53
AD		 3216 /* start the watchdog. */
3217 hw->mac.get_link_status = 1;
3218 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3219
3220 return 0;
3221
0c2cc02e
AD		 3222err_set_queues:
3223 igb_free_irq(adapter);
9d5c8243
AK		 3224err_req_irq:
3225 igb_release_hw_control(adapter);
88a268c1 3226 igb_power_down_link(adapter);
9d5c8243
AK		 3227 igb_free_all_rx_resources(adapter);
3228err_setup_rx:
3229 igb_free_all_tx_resources(adapter);
3230err_setup_tx:
3231 igb_reset(adapter);
749ab2cd
YZ		 3232 if (!resuming)
3233 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3234
3235 return err;
3236}
3237
46eafa59 3238int igb_open(struct net_device *netdev)
749ab2cd
YZ		 3239{
3240 return __igb_open(netdev, false);
3241}
3242
9d5c8243 3243/**
b980ac18
JK		 3244 * igb_close - Disables a network interface
3245 * @netdev: network interface device structure
9d5c8243 3246 *
b980ac18 3247 * Returns 0, this is not allowed to fail
9d5c8243 3248 *
b980ac18
JK		 3249 * The close entry point is called when an interface is de-activated
3250 * by the OS. The hardware is still under the driver's control, but
3251 * needs to be disabled. A global MAC reset is issued to stop the
3252 * hardware, and all transmit and receive resources are freed.
9d5c8243 3253 **/
749ab2cd 3254static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3255{
3256 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3257 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3258
3259 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3260
749ab2cd
YZ		 3261 if (!suspending)
3262 pm_runtime_get_sync(&pdev->dev);
3263
3264 igb_down(adapter);
9d5c8243
AK		 3265 igb_free_irq(adapter);
3266
0e71def2
GH		 3267 igb_nfc_filter_exit(adapter);
3268
9d5c8243
AK		 3269 igb_free_all_tx_resources(adapter);
3270 igb_free_all_rx_resources(adapter);
3271
749ab2cd
YZ		 3272 if (!suspending)
3273 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3274 return 0;
3275}
3276
46eafa59 3277int igb_close(struct net_device *netdev)
749ab2cd
YZ		 3278{
3279 return __igb_close(netdev, false);
3280}
3281
9d5c8243 3282/**
b980ac18
JK		 3283 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3284 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3285 *
b980ac18 3286 * Return 0 on success, negative on failure
9d5c8243 3287 **/
80785298 3288int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3289{
59d71989 3290 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3291 int size;
3292
06034649 3293 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3294
3295 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3296 if (!tx_ring->tx_buffer_info)
9d5c8243 3297 goto err;
9d5c8243
AK		 3298
3299 /* round up to nearest 4K */
85e8d004 3300 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3301 tx_ring->size = ALIGN(tx_ring->size, 4096);
3302
5536d210
AD		 3303 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3304 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3305 if (!tx_ring->desc)
3306 goto err;
3307
9d5c8243
AK		 3308 tx_ring->next_to_use = 0;
3309 tx_ring->next_to_clean = 0;
81c2fc22 3310
9d5c8243
AK		 3311 return 0;
3312
3313err:
06034649 3314 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3315 tx_ring->tx_buffer_info = NULL;
3316 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3317 return -ENOMEM;
3318}
3319
3320/**
b980ac18
JK		 3321 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3322 * (Descriptors) for all queues
3323 * @adapter: board private structure
9d5c8243 3324 *
b980ac18 3325 * Return 0 on success, negative on failure
9d5c8243
AK		 3326 **/
3327static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3328{
439705e1 3329 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3330 int i, err = 0;
3331
3332 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3333 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3334 if (err) {
439705e1 3335 dev_err(&pdev->dev,
9d5c8243
AK		 3336 "Allocation for Tx Queue %u failed\n", i);
3337 for (i--; i >= 0; i--)
3025a446 3338 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3339 break;
3340 }
3341 }
3342
3343 return err;
3344}
3345
3346/**
b980ac18
JK		 3347 * igb_setup_tctl - configure the transmit control registers
3348 * @adapter: Board private structure
9d5c8243 3349 **/
d7ee5b3a 3350void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3351{
9d5c8243
AK		 3352 struct e1000_hw *hw = &adapter->hw;
3353 u32 tctl;
9d5c8243 3354
85b430b4
AD		 3355 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3356 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3357
3358 /* Program the Transmit Control Register */
9d5c8243
AK		 3359 tctl = rd32(E1000_TCTL);
3360 tctl &= ~E1000_TCTL_CT;
3361 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3362 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3363
3364 igb_config_collision_dist(hw);
3365
9d5c8243
AK		 3366 /* Enable transmits */
3367 tctl |= E1000_TCTL_EN;
3368
3369 wr32(E1000_TCTL, tctl);
3370}
3371
85b430b4 3372/**
b980ac18
JK		 3373 * igb_configure_tx_ring - Configure transmit ring after Reset
3374 * @adapter: board private structure
3375 * @ring: tx ring to configure
85b430b4 3376 *
b980ac18 3377 * Configure a transmit ring after a reset.
85b430b4 3378 **/
d7ee5b3a 3379void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3380 struct igb_ring *ring)
85b430b4
AD		 3381{
3382 struct e1000_hw *hw = &adapter->hw;
a74420e0 3383 u32 txdctl = 0;
85b430b4
AD		 3384 u64 tdba = ring->dma;
3385 int reg_idx = ring->reg_idx;
3386
3387 /* disable the queue */
a74420e0 3388 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3389 wrfl();
3390 mdelay(10);
3391
3392 wr32(E1000_TDLEN(reg_idx),
b980ac18 3393 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3394 wr32(E1000_TDBAL(reg_idx),
b980ac18 3395 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3396 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3397
fce99e34 3398 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3399 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3400 writel(0, ring->tail);
85b430b4
AD		 3401
3402 txdctl |= IGB_TX_PTHRESH;
3403 txdctl |= IGB_TX_HTHRESH << 8;
3404 txdctl |= IGB_TX_WTHRESH << 16;
3405
3406 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3407 wr32(E1000_TXDCTL(reg_idx), txdctl);
3408}
3409
3410/**
b980ac18
JK		 3411 * igb_configure_tx - Configure transmit Unit after Reset
3412 * @adapter: board private structure
85b430b4 3413 *
b980ac18 3414 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3415 **/
3416static void igb_configure_tx(struct igb_adapter *adapter)
3417{
3418 int i;
3419
3420 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3421 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3422}
3423
9d5c8243 3424/**
b980ac18
JK		 3425 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3426 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3427 *
b980ac18 3428 * Returns 0 on success, negative on failure
9d5c8243 3429 **/
80785298 3430int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3431{
59d71989 3432 struct device *dev = rx_ring->dev;
f33005a6 3433 int size;
9d5c8243 3434
06034649 3435 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3436
3437 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3438 if (!rx_ring->rx_buffer_info)
9d5c8243 3439 goto err;
9d5c8243 3440
9d5c8243 3441 /* Round up to nearest 4K */
f33005a6 3442 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3443 rx_ring->size = ALIGN(rx_ring->size, 4096);
3444
5536d210
AD		 3445 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3446 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3447 if (!rx_ring->desc)
3448 goto err;
3449
cbc8e55f 3450 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3451 rx_ring->next_to_clean = 0;
3452 rx_ring->next_to_use = 0;
9d5c8243 3453
9d5c8243
AK		 3454 return 0;
3455
3456err:
06034649
AD		 3457 vfree(rx_ring->rx_buffer_info);
3458 rx_ring->rx_buffer_info = NULL;
f33005a6 3459 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3460 return -ENOMEM;
3461}
3462
3463/**
b980ac18
JK		 3464 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3465 * (Descriptors) for all queues
3466 * @adapter: board private structure
9d5c8243 3467 *
b980ac18 3468 * Return 0 on success, negative on failure
9d5c8243
AK		 3469 **/
3470static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3471{
439705e1 3472 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3473 int i, err = 0;
3474
3475 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3476 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3477 if (err) {
439705e1 3478 dev_err(&pdev->dev,
9d5c8243
AK		 3479 "Allocation for Rx Queue %u failed\n", i);
3480 for (i--; i >= 0; i--)
3025a446 3481 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3482 break;
3483 }
3484 }
3485
3486 return err;
3487}
3488
06cf2666 3489/**
b980ac18
JK		 3490 * igb_setup_mrqc - configure the multiple receive queue control registers
3491 * @adapter: Board private structure
06cf2666
AD		 3492 **/
3493static void igb_setup_mrqc(struct igb_adapter *adapter)
3494{
3495 struct e1000_hw *hw = &adapter->hw;
3496 u32 mrqc, rxcsum;
ed12cc9a 3497 u32 j, num_rx_queues;
eb31f849 3498 u32 rss_key[10];
06cf2666 3499
eb31f849 3500 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3501 for (j = 0; j < 10; j++)
eb31f849 3502 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3503
a99955fc 3504 num_rx_queues = adapter->rss_queues;
06cf2666 3505
797fd4be 3506 switch (hw->mac.type) {
797fd4be
AD		 3507 case e1000_82576:
3508 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3509 if (adapter->vfs_allocated_count)
06cf2666 3510 num_rx_queues = 2;
797fd4be
AD		 3511 break;
3512 default:
3513 break;
06cf2666
AD		 3514 }
3515
ed12cc9a
LMV		 3516 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3517 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3518 adapter->rss_indir_tbl[j] =
3519 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3520 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3521 }
ed12cc9a 3522 igb_write_rss_indir_tbl(adapter);
06cf2666 3523
b980ac18 3524 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3525 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3526 * offloads as they are enabled by default
3527 */
3528 rxcsum = rd32(E1000_RXCSUM);
3529 rxcsum |= E1000_RXCSUM_PCSD;
3530
3531 if (adapter->hw.mac.type >= e1000_82576)
3532 /* Enable Receive Checksum Offload for SCTP */
3533 rxcsum |= E1000_RXCSUM_CRCOFL;
3534
3535 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3536 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3537
039454a8
AA		 3538 /* Generate RSS hash based on packet types, TCP/UDP
3539 * port numbers and/or IPv4/v6 src and dst addresses
3540 */
f96a8a0b
CW		 3541 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3542 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3543 E1000_MRQC_RSS_FIELD_IPV6 |
3544 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3545 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3546
039454a8
AA		 3547 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3548 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3549 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3550 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3551
06cf2666
AD		 3552 /* If VMDq is enabled then we set the appropriate mode for that, else
3553 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3554 * if we are only using one queue
3555 */
06cf2666
AD		 3556 if (adapter->vfs_allocated_count) {
3557 if (hw->mac.type > e1000_82575) {
3558 /* Set the default pool for the PF's first queue */
3559 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3560
06cf2666
AD		 3561 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3562 E1000_VT_CTL_DISABLE_DEF_POOL);
3563 vtctl |= adapter->vfs_allocated_count <<
3564 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3565 wr32(E1000_VT_CTL, vtctl);
3566 }
a99955fc 3567 if (adapter->rss_queues > 1)
c883de9f 3568 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
06cf2666 3569 else
f96a8a0b 3570 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3571 } else {
f96a8a0b 3572 if (hw->mac.type != e1000_i211)
c883de9f 3573 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
06cf2666
AD		 3574 }
3575 igb_vmm_control(adapter);
3576
06cf2666
AD		 3577 wr32(E1000_MRQC, mrqc);
3578}
3579
9d5c8243 3580/**
b980ac18
JK		 3581 * igb_setup_rctl - configure the receive control registers
3582 * @adapter: Board private structure
9d5c8243 3583 **/
d7ee5b3a 3584void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3585{
3586 struct e1000_hw *hw = &adapter->hw;
3587 u32 rctl;
9d5c8243
AK		 3588
3589 rctl = rd32(E1000_RCTL);
3590
3591 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3592 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3593
69d728ba 3594 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3595 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3596
b980ac18 3597 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3598 * redirection as it did with e1000. Newer features require
3599 * that the HW strips the CRC.
73cd78f1 3600 */
87cb7e8c 3601 rctl |= E1000_RCTL_SECRC;
9d5c8243 3602
559e9c49 3603 /* disable store bad packets and clear size bits. */
ec54d7d6 3604 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3605
45693bcb 3606 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3607 rctl |= E1000_RCTL_LPE;
9d5c8243 3608
952f72a8
AD		 3609 /* disable queue 0 to prevent tail write w/o re-config */
3610 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3611
e1739522
AD		 3612 /* Attention!!! For SR-IOV PF driver operations you must enable
3613 * queue drop for all VF and PF queues to prevent head of line blocking
3614 * if an un-trusted VF does not provide descriptors to hardware.
3615 */
3616 if (adapter->vfs_allocated_count) {
e1739522
AD		 3617 /* set all queue drop enable bits */
3618 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3619 }
3620
89eaefb6
BG		 3621 /* This is useful for sniffing bad packets. */
3622 if (adapter->netdev->features & NETIF_F_RXALL) {
3623 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3624 * in e1000e_set_rx_mode
3625 */
89eaefb6
BG		 3626 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3627 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3628 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3629
16903caa 3630 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3631 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3632 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3633 * and that breaks VLANs.
3634 */
3635 }
3636
9d5c8243
AK		 3637 wr32(E1000_RCTL, rctl);
3638}
3639
7d5753f0 3640static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3641 int vfn)
7d5753f0
AD		 3642{
3643 struct e1000_hw *hw = &adapter->hw;
3644 u32 vmolr;
3645
d3836f8e
AD		 3646 if (size > MAX_JUMBO_FRAME_SIZE)
3647 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3648
3649 vmolr = rd32(E1000_VMOLR(vfn));
3650 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3651 vmolr |= size | E1000_VMOLR_LPE;
3652 wr32(E1000_VMOLR(vfn), vmolr);
3653
3654 return 0;
3655}
3656
030f9f52
CV		 3657static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
3658 int vfn, bool enable)
e1739522 3659{
e1739522 3660 struct e1000_hw *hw = &adapter->hw;
030f9f52 3661 u32 val, reg;
e1739522 3662
030f9f52
CV		 3663 if (hw->mac.type < e1000_82576)
3664 return;
e1739522 3665
030f9f52
CV		 3666 if (hw->mac.type == e1000_i350)
3667 reg = E1000_DVMOLR(vfn);
3668 else
3669 reg = E1000_VMOLR(vfn);
3670
3671 val = rd32(reg);
3672 if (enable)
3673 val |= E1000_VMOLR_STRVLAN;
3674 else
3675 val &= ~(E1000_VMOLR_STRVLAN);
3676 wr32(reg, val);
e1739522
AD		 3677}
3678
8151d294
WM		 3679static inline void igb_set_vmolr(struct igb_adapter *adapter,
3680 int vfn, bool aupe)
7d5753f0
AD		 3681{
3682 struct e1000_hw *hw = &adapter->hw;
3683 u32 vmolr;
3684
b980ac18 3685 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3686 * we should exit and do nothing
3687 */
3688 if (hw->mac.type < e1000_82576)
3689 return;
3690
3691 vmolr = rd32(E1000_VMOLR(vfn));
8151d294 3692 if (aupe)
b980ac18 3693 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3694 else
3695 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3696
3697 /* clear all bits that might not be set */
3698 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3699
a99955fc 3700 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3701 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3702 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3703 * multicast packets
3704 */
3705 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3706 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3707
3708 wr32(E1000_VMOLR(vfn), vmolr);
3709}
3710
85b430b4 3711/**
b980ac18
JK		 3712 * igb_configure_rx_ring - Configure a receive ring after Reset
3713 * @adapter: board private structure
3714 * @ring: receive ring to be configured
85b430b4 3715 *
b980ac18 3716 * Configure the Rx unit of the MAC after a reset.
85b430b4 3717 **/
d7ee5b3a 3718void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3719 struct igb_ring *ring)
85b430b4
AD		 3720{
3721 struct e1000_hw *hw = &adapter->hw;
3722 u64 rdba = ring->dma;
3723 int reg_idx = ring->reg_idx;
a74420e0 3724 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3725
3726 /* disable the queue */
a74420e0 3727 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3728
3729 /* Set DMA base address registers */
3730 wr32(E1000_RDBAL(reg_idx),
3731 rdba & 0x00000000ffffffffULL);
3732 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3733 wr32(E1000_RDLEN(reg_idx),
b980ac18 3734 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3735
3736 /* initialize head and tail */
fce99e34 3737 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3738 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3739 writel(0, ring->tail);
85b430b4 3740
952f72a8 3741 /* set descriptor configuration */
44390ca6 3742 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3743 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3744 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3745 if (hw->mac.type >= e1000_82580)
757b77e2 3746 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3747 /* Only set Drop Enable if we are supporting multiple queues */
3748 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3749 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3750
3751 wr32(E1000_SRRCTL(reg_idx), srrctl);
3752
7d5753f0 3753 /* set filtering for VMDQ pools */
8151d294 3754 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3755
85b430b4
AD		 3756 rxdctl |= IGB_RX_PTHRESH;
3757 rxdctl |= IGB_RX_HTHRESH << 8;
3758 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3759
3760 /* enable receive descriptor fetching */
3761 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3762 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3763}
3764
9d5c8243 3765/**
b980ac18
JK		 3766 * igb_configure_rx - Configure receive Unit after Reset
3767 * @adapter: board private structure
9d5c8243 3768 *
b980ac18 3769 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3770 **/
3771static void igb_configure_rx(struct igb_adapter *adapter)
3772{
9107584e 3773 int i;
9d5c8243 3774
26ad9178
AD		 3775 /* set the correct pool for the PF default MAC address in entry 0 */
3776 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3777 adapter->vfs_allocated_count);
26ad9178 3778
06cf2666 3779 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3780 * the Base and Length of the Rx Descriptor Ring
3781 */
f9d40f6a
AD		 3782 for (i = 0; i < adapter->num_rx_queues; i++)
3783 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3784}
3785
3786/**
b980ac18
JK		 3787 * igb_free_tx_resources - Free Tx Resources per Queue
3788 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3789 *
b980ac18 3790 * Free all transmit software resources
9d5c8243 3791 **/
68fd9910 3792void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3793{
3b644cf6 3794 igb_clean_tx_ring(tx_ring);
9d5c8243 3795
06034649
AD		 3796 vfree(tx_ring->tx_buffer_info);
3797 tx_ring->tx_buffer_info = NULL;
9d5c8243 3798
439705e1
AD		 3799 /* if not set, then don't free */
3800 if (!tx_ring->desc)
3801 return;
3802
59d71989
AD		 3803 dma_free_coherent(tx_ring->dev, tx_ring->size,
3804 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3805
3806 tx_ring->desc = NULL;
3807}
3808
3809/**
b980ac18
JK		 3810 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3811 * @adapter: board private structure
9d5c8243 3812 *
b980ac18 3813 * Free all transmit software resources
9d5c8243
AK		 3814 **/
3815static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3816{
3817 int i;
3818
3819 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3820 if (adapter->tx_ring[i])
3821 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3822}
3823
ebe42d16
AD		 3824void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3825 struct igb_tx_buffer *tx_buffer)
3826{
3827 if (tx_buffer->skb) {
3828 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3829 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3830 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3831 dma_unmap_addr(tx_buffer, dma),
3832 dma_unmap_len(tx_buffer, len),
ebe42d16 3833 DMA_TO_DEVICE);
c9f14bf3 3834 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3835 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3836 dma_unmap_addr(tx_buffer, dma),
3837 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3838 DMA_TO_DEVICE);
3839 }
3840 tx_buffer->next_to_watch = NULL;
3841 tx_buffer->skb = NULL;
c9f14bf3 3842 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3843 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3844}
3845
3846/**
b980ac18
JK		 3847 * igb_clean_tx_ring - Free Tx Buffers
3848 * @tx_ring: ring to be cleaned
9d5c8243 3849 **/
3b644cf6 3850static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3851{
06034649 3852 struct igb_tx_buffer *buffer_info;
9d5c8243 3853 unsigned long size;
6ad4edfc 3854 u16 i;
9d5c8243 3855
06034649 3856 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3857 return;
3858 /* Free all the Tx ring sk_buffs */
3859
3860 for (i = 0; i < tx_ring->count; i++) {
06034649 3861 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3862 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3863 }
3864
dad8a3b3
JF		 3865 netdev_tx_reset_queue(txring_txq(tx_ring));
3866
06034649
AD		 3867 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3868 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3869
3870 /* Zero out the descriptor ring */
9d5c8243
AK		 3871 memset(tx_ring->desc, 0, tx_ring->size);
3872
3873 tx_ring->next_to_use = 0;
3874 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3875}
3876
3877/**
b980ac18
JK		 3878 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3879 * @adapter: board private structure
9d5c8243
AK		 3880 **/
3881static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3882{
3883 int i;
3884
3885 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3886 if (adapter->tx_ring[i])
3887 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3888}
3889
3890/**
b980ac18
JK		 3891 * igb_free_rx_resources - Free Rx Resources
3892 * @rx_ring: ring to clean the resources from
9d5c8243 3893 *
b980ac18 3894 * Free all receive software resources
9d5c8243 3895 **/
68fd9910 3896void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3897{
3b644cf6 3898 igb_clean_rx_ring(rx_ring);
9d5c8243 3899
06034649
AD		 3900 vfree(rx_ring->rx_buffer_info);
3901 rx_ring->rx_buffer_info = NULL;
9d5c8243 3902
439705e1
AD		 3903 /* if not set, then don't free */
3904 if (!rx_ring->desc)
3905 return;
3906
59d71989
AD		 3907 dma_free_coherent(rx_ring->dev, rx_ring->size,
3908 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3909
3910 rx_ring->desc = NULL;
3911}
3912
3913/**
b980ac18
JK		 3914 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3915 * @adapter: board private structure
9d5c8243 3916 *
b980ac18 3917 * Free all receive software resources
9d5c8243
AK		 3918 **/
3919static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3920{
3921 int i;
3922
3923 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3924 if (adapter->rx_ring[i])
3925 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3926}
3927
3928/**
b980ac18
JK		 3929 * igb_clean_rx_ring - Free Rx Buffers per Queue
3930 * @rx_ring: ring to free buffers from
9d5c8243 3931 **/
3b644cf6 3932static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3933{
9d5c8243 3934 unsigned long size;
c023cd88 3935 u16 i;
9d5c8243 3936
1a1c225b
AD		 3937 if (rx_ring->skb)
3938 dev_kfree_skb(rx_ring->skb);
3939 rx_ring->skb = NULL;
3940
06034649 3941 if (!rx_ring->rx_buffer_info)
9d5c8243 3942 return;
439705e1 3943
9d5c8243
AK		 3944 /* Free all the Rx ring sk_buffs */
3945 for (i = 0; i < rx_ring->count; i++) {
06034649 3946 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3947
cbc8e55f
AD		 3948 if (!buffer_info->page)
3949 continue;
3950
5be59554
AD		 3951 /* Invalidate cache lines that may have been written to by
3952 * device so that we avoid corrupting memory.
3953 */
3954 dma_sync_single_range_for_cpu(rx_ring->dev,
3955 buffer_info->dma,
3956 buffer_info->page_offset,
3957 IGB_RX_BUFSZ,
3958 DMA_FROM_DEVICE);
3959
3960 /* free resources associated with mapping */
3961 dma_unmap_page_attrs(rx_ring->dev,
3962 buffer_info->dma,
3963 PAGE_SIZE,
3964 DMA_FROM_DEVICE,
3965 DMA_ATTR_SKIP_CPU_SYNC);
2976db80
AD		 3966 __page_frag_cache_drain(buffer_info->page,
3967 buffer_info->pagecnt_bias);
cbc8e55f 3968
1a1c225b 3969 buffer_info->page = NULL;
9d5c8243
AK		 3970 }
3971
06034649
AD		 3972 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3973 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3974
3975 /* Zero out the descriptor ring */
3976 memset(rx_ring->desc, 0, rx_ring->size);
3977
cbc8e55f 3978 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3979 rx_ring->next_to_clean = 0;
3980 rx_ring->next_to_use = 0;
9d5c8243
AK		 3981}
3982
3983/**
b980ac18
JK		 3984 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3985 * @adapter: board private structure
9d5c8243
AK		 3986 **/
3987static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3988{
3989 int i;
3990
3991 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3992 if (adapter->rx_ring[i])
3993 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3994}
3995
3996/**
b980ac18
JK		 3997 * igb_set_mac - Change the Ethernet Address of the NIC
3998 * @netdev: network interface device structure
3999 * @p: pointer to an address structure
9d5c8243 4000 *
b980ac18 4001 * Returns 0 on success, negative on failure
9d5c8243
AK		 4002 **/
4003static int igb_set_mac(struct net_device *netdev, void *p)
4004{
4005 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 4006 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4007 struct sockaddr *addr = p;
4008
4009 if (!is_valid_ether_addr(addr->sa_data))
4010 return -EADDRNOTAVAIL;
4011
4012 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 4013 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 4014
26ad9178
AD		 4015 /* set the correct pool for the new PF MAC address in entry 0 */
4016 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 4017 adapter->vfs_allocated_count);
e1739522 4018
9d5c8243
AK		 4019 return 0;
4020}
4021
4022/**
b980ac18
JK		 4023 * igb_write_mc_addr_list - write multicast addresses to MTA
4024 * @netdev: network interface device structure
9d5c8243 4025 *
b980ac18
JK		 4026 * Writes multicast address list to the MTA hash table.
4027 * Returns: -ENOMEM on failure
4028 * 0 on no addresses written
4029 * X on writing X addresses to MTA
9d5c8243 4030 **/
68d480c4 4031static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 4032{
4033 struct igb_adapter *adapter = netdev_priv(netdev);
4034 struct e1000_hw *hw = &adapter->hw;
22bedad3 4035 struct netdev_hw_addr *ha;
68d480c4 4036 u8 *mta_list;
9d5c8243
AK		 4037 int i;
4038
4cd24eaf 4039 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 4040 /* nothing to program, so clear mc list */
4041 igb_update_mc_addr_list(hw, NULL, 0);
4042 igb_restore_vf_multicasts(adapter);
4043 return 0;
4044 }
9d5c8243 4045
4cd24eaf 4046 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 4047 if (!mta_list)
4048 return -ENOMEM;
ff41f8dc 4049
68d480c4 4050 /* The shared function expects a packed array of only addresses. */
48e2f183 4051 i = 0;
22bedad3
JP		 4052 netdev_for_each_mc_addr(ha, netdev)
4053 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 4054
68d480c4
AD		 4055 igb_update_mc_addr_list(hw, mta_list, i);
4056 kfree(mta_list);
4057
4cd24eaf 4058 return netdev_mc_count(netdev);
68d480c4
AD		 4059}
4060
4061/**
b980ac18
JK		 4062 * igb_write_uc_addr_list - write unicast addresses to RAR table
4063 * @netdev: network interface device structure
68d480c4 4064 *
b980ac18
JK		 4065 * Writes unicast address list to the RAR table.
4066 * Returns: -ENOMEM on failure/insufficient address space
4067 * 0 on no addresses written
4068 * X on writing X addresses to the RAR table
68d480c4
AD		 4069 **/
4070static int igb_write_uc_addr_list(struct net_device *netdev)
4071{
4072 struct igb_adapter *adapter = netdev_priv(netdev);
4073 struct e1000_hw *hw = &adapter->hw;
4074 unsigned int vfn = adapter->vfs_allocated_count;
4075 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
4076 int count = 0;
4077
4078 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 4079 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 4080 return -ENOMEM;
9d5c8243 4081
32e7bfc4 4082 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 4083 struct netdev_hw_addr *ha;
32e7bfc4
JP		 4084
4085 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 4086 if (!rar_entries)
4087 break;
26ad9178 4088 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 4089 rar_entries--,
4090 vfn);
68d480c4 4091 count++;
ff41f8dc
AD		 4092 }
4093 }
4094 /* write the addresses in reverse order to avoid write combining */
4095 for (; rar_entries > 0 ; rar_entries--) {
4096 wr32(E1000_RAH(rar_entries), 0);
4097 wr32(E1000_RAL(rar_entries), 0);
4098 }
4099 wrfl();
4100
68d480c4
AD		 4101 return count;
4102}
4103
16903caa
AD		 4104static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4105{
4106 struct e1000_hw *hw = &adapter->hw;
4107 u32 i, pf_id;
4108
4109 switch (hw->mac.type) {
4110 case e1000_i210:
4111 case e1000_i211:
4112 case e1000_i350:
4113 /* VLAN filtering needed for VLAN prio filter */
4114 if (adapter->netdev->features & NETIF_F_NTUPLE)
4115 break;
4116 /* fall through */
4117 case e1000_82576:
4118 case e1000_82580:
4119 case e1000_i354:
4120 /* VLAN filtering needed for pool filtering */
4121 if (adapter->vfs_allocated_count)
4122 break;
4123 /* fall through */
4124 default:
4125 return 1;
4126 }
4127
4128 /* We are already in VLAN promisc, nothing to do */
4129 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4130 return 0;
4131
4132 if (!adapter->vfs_allocated_count)
4133 goto set_vfta;
4134
4135 /* Add PF to all active pools */
4136 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4137
4138 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4139 u32 vlvf = rd32(E1000_VLVF(i));
4140
a51d8c21 4141 vlvf |= BIT(pf_id);
16903caa
AD		 4142 wr32(E1000_VLVF(i), vlvf);
4143 }
4144
4145set_vfta:
4146 /* Set all bits in the VLAN filter table array */
4147 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4148 hw->mac.ops.write_vfta(hw, i, ~0U);
4149
4150 /* Set flag so we don't redo unnecessary work */
4151 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4152
4153 return 0;
4154}
4155
4156#define VFTA_BLOCK_SIZE 8
4157static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4158{
4159 struct e1000_hw *hw = &adapter->hw;
4160 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4161 u32 vid_start = vfta_offset * 32;
4162 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4163 u32 i, vid, word, bits, pf_id;
4164
4165 /* guarantee that we don't scrub out management VLAN */
4166 vid = adapter->mng_vlan_id;
4167 if (vid >= vid_start && vid < vid_end)
a51d8c21 4168 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16903caa
AD		 4169
4170 if (!adapter->vfs_allocated_count)
4171 goto set_vfta;
4172
4173 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4174
4175 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4176 u32 vlvf = rd32(E1000_VLVF(i));
4177
4178 /* pull VLAN ID from VLVF */
4179 vid = vlvf & VLAN_VID_MASK;
4180
4181 /* only concern ourselves with a certain range */
4182 if (vid < vid_start || vid >= vid_end)
4183 continue;
4184
4185 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4186 /* record VLAN ID in VFTA */
a51d8c21 4187 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16903caa
AD		 4188
4189 /* if PF is part of this then continue */
4190 if (test_bit(vid, adapter->active_vlans))
4191 continue;
4192 }
4193
4194 /* remove PF from the pool */
a51d8c21 4195 bits = ~BIT(pf_id);
16903caa
AD		 4196 bits &= rd32(E1000_VLVF(i));
4197 wr32(E1000_VLVF(i), bits);
4198 }
4199
4200set_vfta:
4201 /* extract values from active_vlans and write back to VFTA */
4202 for (i = VFTA_BLOCK_SIZE; i--;) {
4203 vid = (vfta_offset + i) * 32;
4204 word = vid / BITS_PER_LONG;
4205 bits = vid % BITS_PER_LONG;
4206
4207 vfta[i] |= adapter->active_vlans[word] >> bits;
4208
4209 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4210 }
4211}
4212
4213static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4214{
4215 u32 i;
4216
4217 /* We are not in VLAN promisc, nothing to do */
4218 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4219 return;
4220
4221 /* Set flag so we don't redo unnecessary work */
4222 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4223
4224 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4225 igb_scrub_vfta(adapter, i);
4226}
4227
68d480c4 4228/**
b980ac18
JK		 4229 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4230 * @netdev: network interface device structure
68d480c4 4231 *
b980ac18
JK		 4232 * The set_rx_mode entry point is called whenever the unicast or multicast
4233 * address lists or the network interface flags are updated. This routine is
4234 * responsible for configuring the hardware for proper unicast, multicast,
4235 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4236 **/
4237static void igb_set_rx_mode(struct net_device *netdev)
4238{
4239 struct igb_adapter *adapter = netdev_priv(netdev);
4240 struct e1000_hw *hw = &adapter->hw;
4241 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4242 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4243 int count;
4244
4245 /* Check for Promiscuous and All Multicast modes */
68d480c4 4246 if (netdev->flags & IFF_PROMISC) {
16903caa 4247 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
bf456abb
AD		 4248 vmolr |= E1000_VMOLR_MPME;
4249
4250 /* enable use of UTA filter to force packets to default pool */
4251 if (hw->mac.type == e1000_82576)
4252 vmolr |= E1000_VMOLR_ROPE;
68d480c4
AD		 4253 } else {
4254 if (netdev->flags & IFF_ALLMULTI) {
4255 rctl |= E1000_RCTL_MPE;
4256 vmolr |= E1000_VMOLR_MPME;
4257 } else {
b980ac18 4258 /* Write addresses to the MTA, if the attempt fails
25985edc 4259 * then we should just turn on promiscuous mode so
68d480c4
AD		 4260 * that we can at least receive multicast traffic
4261 */
4262 count = igb_write_mc_addr_list(netdev);
4263 if (count < 0) {
4264 rctl |= E1000_RCTL_MPE;
4265 vmolr |= E1000_VMOLR_MPME;
4266 } else if (count) {
4267 vmolr |= E1000_VMOLR_ROMPE;
4268 }
4269 }
28fc06f5 4270 }
268f9d33
AD		 4271
4272 /* Write addresses to available RAR registers, if there is not
4273 * sufficient space to store all the addresses then enable
4274 * unicast promiscuous mode
4275 */
4276 count = igb_write_uc_addr_list(netdev);
4277 if (count < 0) {
4278 rctl |= E1000_RCTL_UPE;
4279 vmolr |= E1000_VMOLR_ROPE;
28fc06f5 4280 }
16903caa
AD		 4281
4282 /* enable VLAN filtering by default */
4283 rctl |= E1000_RCTL_VFE;
4284
4285 /* disable VLAN filtering for modes that require it */
4286 if ((netdev->flags & IFF_PROMISC) ||
4287 (netdev->features & NETIF_F_RXALL)) {
4288 /* if we fail to set all rules then just clear VFE */
4289 if (igb_vlan_promisc_enable(adapter))
4290 rctl &= ~E1000_RCTL_VFE;
4291 } else {
4292 igb_vlan_promisc_disable(adapter);
4293 }
4294
4295 /* update state of unicast, multicast, and VLAN filtering modes */
4296 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4297 E1000_RCTL_VFE);
68d480c4 4298 wr32(E1000_RCTL, rctl);
28fc06f5 4299
b980ac18 4300 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4301 * the VMOLR to enable the appropriate modes. Without this workaround
4302 * we will have issues with VLAN tag stripping not being done for frames
4303 * that are only arriving because we are the default pool
4304 */
f96a8a0b 4305 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4306 return;
9d5c8243 4307
bf456abb
AD		 4308 /* set UTA to appropriate mode */
4309 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4310
68d480c4 4311 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4312 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4313
4314 /* enable Rx jumbo frames, no need for restriction */
4315 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4316 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4317
68d480c4 4318 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4319 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4320
28fc06f5 4321 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4322}
4323
13800469
GR		 4324static void igb_check_wvbr(struct igb_adapter *adapter)
4325{
4326 struct e1000_hw *hw = &adapter->hw;
4327 u32 wvbr = 0;
4328
4329 switch (hw->mac.type) {
4330 case e1000_82576:
4331 case e1000_i350:
81ad807b
CW		 4332 wvbr = rd32(E1000_WVBR);
4333 if (!wvbr)
13800469
GR		 4334 return;
4335 break;
4336 default:
4337 break;
4338 }
4339
4340 adapter->wvbr |= wvbr;
4341}
4342
4343#define IGB_STAGGERED_QUEUE_OFFSET 8
4344
4345static void igb_spoof_check(struct igb_adapter *adapter)
4346{
4347 int j;
4348
4349 if (!adapter->wvbr)
4350 return;
4351
9005df38 4352 for (j = 0; j < adapter->vfs_allocated_count; j++) {
a51d8c21
JK		 4353 if (adapter->wvbr & BIT(j) ||
4354 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
13800469
GR		 4355 dev_warn(&adapter->pdev->dev,
4356 "Spoof event(s) detected on VF %d\n", j);
4357 adapter->wvbr &=
a51d8c21
JK		 4358 ~(BIT(j) |
4359 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
13800469
GR		 4360 }
4361 }
4362}
4363
9d5c8243 4364/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4365 * the phy
4366 */
9d5c8243
AK		 4367static void igb_update_phy_info(unsigned long data)
4368{
4369 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4370 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4371}
4372
4d6b725e 4373/**
b980ac18
JK		 4374 * igb_has_link - check shared code for link and determine up/down
4375 * @adapter: pointer to driver private info
4d6b725e 4376 **/
3145535a 4377bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4378{
4379 struct e1000_hw *hw = &adapter->hw;
4380 bool link_active = false;
4d6b725e
AD		 4381
4382 /* get_link_status is set on LSC (link status) interrupt or
4383 * rx sequence error interrupt. get_link_status will stay
4384 * false until the e1000_check_for_link establishes link
4385 * for copper adapters ONLY
4386 */
4387 switch (hw->phy.media_type) {
4388 case e1000_media_type_copper:
e5c3370f
AA		 4389 if (!hw->mac.get_link_status)
4390 return true;
4d6b725e 4391 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4392 hw->mac.ops.check_for_link(hw);
4393 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4394 break;
4395 default:
4396 case e1000_media_type_unknown:
4397 break;
4398 }
4399
aa9b8cc4
AA		 4400 if (((hw->mac.type == e1000_i210) ||
4401 (hw->mac.type == e1000_i211)) &&
4402 (hw->phy.id == I210_I_PHY_ID)) {
4403 if (!netif_carrier_ok(adapter->netdev)) {
4404 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4405 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4406 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4407 adapter->link_check_timeout = jiffies;
4408 }
4409 }
4410
4d6b725e
AD		 4411 return link_active;
4412}
4413
563988dc
SA		 4414static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4415{
4416 bool ret = false;
4417 u32 ctrl_ext, thstat;
4418
f96a8a0b 4419 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4420 if (hw->mac.type == e1000_i350) {
4421 thstat = rd32(E1000_THSTAT);
4422 ctrl_ext = rd32(E1000_CTRL_EXT);
4423
4424 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4425 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4426 ret = !!(thstat & event);
563988dc
SA		 4427 }
4428
4429 return ret;
4430}
4431
1516f0a6
CW		 4432/**
4433 * igb_check_lvmmc - check for malformed packets received
4434 * and indicated in LVMMC register
4435 * @adapter: pointer to adapter
4436 **/
4437static void igb_check_lvmmc(struct igb_adapter *adapter)
4438{
4439 struct e1000_hw *hw = &adapter->hw;
4440 u32 lvmmc;
4441
4442 lvmmc = rd32(E1000_LVMMC);
4443 if (lvmmc) {
4444 if (unlikely(net_ratelimit())) {
4445 netdev_warn(adapter->netdev,
4446 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4447 lvmmc);
4448 }
4449 }
4450}
4451
9d5c8243 4452/**
b980ac18
JK		 4453 * igb_watchdog - Timer Call-back
4454 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4455 **/
4456static void igb_watchdog(unsigned long data)
4457{
4458 struct igb_adapter *adapter = (struct igb_adapter *)data;
4459 /* Do the rest outside of interrupt context */
4460 schedule_work(&adapter->watchdog_task);
4461}
4462
4463static void igb_watchdog_task(struct work_struct *work)
4464{
4465 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4466 struct igb_adapter,
4467 watchdog_task);
9d5c8243 4468 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4469 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4470 struct net_device *netdev = adapter->netdev;
563988dc 4471 u32 link;
7a6ea550 4472 int i;
56cec249 4473 u32 connsw;
b72f3f72 4474 u16 phy_data, retry_count = 20;
9d5c8243 4475
4d6b725e 4476 link = igb_has_link(adapter);
aa9b8cc4
AA		 4477
4478 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4479 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4480 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4481 else
4482 link = false;
4483 }
4484
56cec249
CW		 4485 /* Force link down if we have fiber to swap to */
4486 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4487 if (hw->phy.media_type == e1000_media_type_copper) {
4488 connsw = rd32(E1000_CONNSW);
4489 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4490 link = 0;
4491 }
4492 }
9d5c8243 4493 if (link) {
2bdfc4e2
CW		 4494 /* Perform a reset if the media type changed. */
4495 if (hw->dev_spec._82575.media_changed) {
4496 hw->dev_spec._82575.media_changed = false;
4497 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4498 igb_reset(adapter);
4499 }
749ab2cd
YZ		 4500 /* Cancel scheduled suspend requests. */
4501 pm_runtime_resume(netdev->dev.parent);
4502
9d5c8243
AK		 4503 if (!netif_carrier_ok(netdev)) {
4504 u32 ctrl;
9005df38 4505
330a6d6a 4506 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4507 &adapter->link_speed,
4508 &adapter->link_duplex);
9d5c8243
AK		 4509
4510 ctrl = rd32(E1000_CTRL);
527d47c1 4511 /* Links status message must follow this format */
c75c4edf
CW		 4512 netdev_info(netdev,
4513 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4514 netdev->name,
4515 adapter->link_speed,
4516 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4517 "Full" : "Half",
4518 (ctrl & E1000_CTRL_TFCE) &&
4519 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4520 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4521 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4522
f4c01e96
CW		 4523 /* disable EEE if enabled */
4524 if ((adapter->flags & IGB_FLAG_EEE) &&
4525 (adapter->link_duplex == HALF_DUPLEX)) {
4526 dev_info(&adapter->pdev->dev,
4527 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4528 adapter->hw.dev_spec._82575.eee_disable = true;
4529 adapter->flags &= ~IGB_FLAG_EEE;
4530 }
4531
c0ba4778
KS		 4532 /* check if SmartSpeed worked */
4533 igb_check_downshift(hw);
4534 if (phy->speed_downgraded)
4535 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4536
563988dc 4537 /* check for thermal sensor event */
876d2d6f 4538 if (igb_thermal_sensor_event(hw,
d34a15ab 4539 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4540 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4541
d07f3e37 4542 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4543 adapter->tx_timeout_factor = 1;
4544 switch (adapter->link_speed) {
4545 case SPEED_10:
9d5c8243
AK		 4546 adapter->tx_timeout_factor = 14;
4547 break;
4548 case SPEED_100:
9d5c8243
AK		 4549 /* maybe add some timeout factor ? */
4550 break;
4551 }
4552
b72f3f72
TU		 4553 if (adapter->link_speed != SPEED_1000)
4554 goto no_wait;
4555
4556 /* wait for Remote receiver status OK */
4557retry_read_status:
4558 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4559 &phy_data)) {
4560 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4561 retry_count) {
4562 msleep(100);
4563 retry_count--;
4564 goto retry_read_status;
4565 } else if (!retry_count) {
4566 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4567 }
4568 } else {
4569 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4570 }
4571no_wait:
9d5c8243 4572 netif_carrier_on(netdev);
9d5c8243 4573
4ae196df 4574 igb_ping_all_vfs(adapter);
17dc566c 4575 igb_check_vf_rate_limit(adapter);
4ae196df 4576
4b1a9877 4577 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4578 if (!test_bit(__IGB_DOWN, &adapter->state))
4579 mod_timer(&adapter->phy_info_timer,
4580 round_jiffies(jiffies + 2 * HZ));
4581 }
4582 } else {
4583 if (netif_carrier_ok(netdev)) {
4584 adapter->link_speed = 0;
4585 adapter->link_duplex = 0;
563988dc
SA		 4586
4587 /* check for thermal sensor event */
876d2d6f
JK		 4588 if (igb_thermal_sensor_event(hw,
4589 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4590 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4591 }
563988dc 4592
527d47c1 4593 /* Links status message must follow this format */
c75c4edf 4594 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4595 netdev->name);
9d5c8243 4596 netif_carrier_off(netdev);
4b1a9877 4597
4ae196df
AD		 4598 igb_ping_all_vfs(adapter);
4599
4b1a9877 4600 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4601 if (!test_bit(__IGB_DOWN, &adapter->state))
4602 mod_timer(&adapter->phy_info_timer,
4603 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4604
56cec249
CW		 4605 /* link is down, time to check for alternate media */
4606 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4607 igb_check_swap_media(adapter);
4608 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4609 schedule_work(&adapter->reset_task);
4610 /* return immediately */
4611 return;
4612 }
4613 }
749ab2cd
YZ		 4614 pm_schedule_suspend(netdev->dev.parent,
4615 MSEC_PER_SEC * 5);
56cec249
CW		 4616
4617 /* also check for alternate media here */
4618 } else if (!netif_carrier_ok(netdev) &&
4619 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4620 igb_check_swap_media(adapter);
4621 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4622 schedule_work(&adapter->reset_task);
4623 /* return immediately */
4624 return;
4625 }
9d5c8243
AK		 4626 }
4627 }
4628
12dcd86b
ED		 4629 spin_lock(&adapter->stats64_lock);
4630 igb_update_stats(adapter, &adapter->stats64);
4631 spin_unlock(&adapter->stats64_lock);
9d5c8243 4632
dbabb065 4633 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4634 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4635 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4636 /* We've lost link, so the controller stops DMA,
4637 * but we've got queued Tx work that's never going
4638 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4639 * (Do the reset outside of interrupt context).
4640 */
dbabb065
AD		 4641 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4642 adapter->tx_timeout_count++;
4643 schedule_work(&adapter->reset_task);
4644 /* return immediately since reset is imminent */
4645 return;
4646 }
9d5c8243 4647 }
9d5c8243 4648
dbabb065 4649 /* Force detection of hung controller every watchdog period */
6d095fa8 4650 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4651 }
f7ba205e 4652
b980ac18 4653 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4654 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4655 u32 eics = 0;
9005df38 4656
0d1ae7f4
AD		 4657 for (i = 0; i < adapter->num_q_vectors; i++)
4658 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4659 wr32(E1000_EICS, eics);
4660 } else {
4661 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4662 }
9d5c8243 4663
13800469 4664 igb_spoof_check(adapter);
fc580751 4665 igb_ptp_rx_hang(adapter);
13800469 4666
1516f0a6
CW		 4667 /* Check LVMMC register on i350/i354 only */
4668 if ((adapter->hw.mac.type == e1000_i350) ||
4669 (adapter->hw.mac.type == e1000_i354))
4670 igb_check_lvmmc(adapter);
4671
9d5c8243 4672 /* Reset the timer */
aa9b8cc4
AA		 4673 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4674 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4675 mod_timer(&adapter->watchdog_timer,
4676 round_jiffies(jiffies + HZ));
4677 else
4678 mod_timer(&adapter->watchdog_timer,
4679 round_jiffies(jiffies + 2 * HZ));
4680 }
9d5c8243
AK		 4681}
4682
4683enum latency_range {
4684 lowest_latency = 0,
4685 low_latency = 1,
4686 bulk_latency = 2,
4687 latency_invalid = 255
4688};
4689
6eb5a7f1 4690/**
b980ac18
JK		 4691 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4692 * @q_vector: pointer to q_vector
6eb5a7f1 4693 *
b980ac18
JK		 4694 * Stores a new ITR value based on strictly on packet size. This
4695 * algorithm is less sophisticated than that used in igb_update_itr,
4696 * due to the difficulty of synchronizing statistics across multiple
4697 * receive rings. The divisors and thresholds used by this function
4698 * were determined based on theoretical maximum wire speed and testing
4699 * data, in order to minimize response time while increasing bulk
4700 * throughput.
406d4965 4701 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4702 * NOTE: This function is called only when operating in a multiqueue
4703 * receive environment.
6eb5a7f1 4704 **/
047e0030 4705static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4706{
047e0030 4707 int new_val = q_vector->itr_val;
6eb5a7f1 4708 int avg_wire_size = 0;
047e0030 4709 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4710 unsigned int packets;
9d5c8243 4711
6eb5a7f1
AD		 4712 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4713 * ints/sec - ITR timer value of 120 ticks.
4714 */
4715 if (adapter->link_speed != SPEED_1000) {
0ba82994 4716 new_val = IGB_4K_ITR;
6eb5a7f1 4717 goto set_itr_val;
9d5c8243 4718 }
047e0030 4719
0ba82994
AD		 4720 packets = q_vector->rx.total_packets;
4721 if (packets)
4722 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4723
0ba82994
AD		 4724 packets = q_vector->tx.total_packets;
4725 if (packets)
4726 avg_wire_size = max_t(u32, avg_wire_size,
4727 q_vector->tx.total_bytes / packets);
047e0030
AD		 4728
4729 /* if avg_wire_size isn't set no work was done */
4730 if (!avg_wire_size)
4731 goto clear_counts;
9d5c8243 4732
6eb5a7f1
AD		 4733 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4734 avg_wire_size += 24;
4735
4736 /* Don't starve jumbo frames */
4737 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4738
6eb5a7f1
AD		 4739 /* Give a little boost to mid-size frames */
4740 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4741 new_val = avg_wire_size / 3;
4742 else
4743 new_val = avg_wire_size / 2;
9d5c8243 4744
0ba82994
AD		 4745 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4746 if (new_val < IGB_20K_ITR &&
4747 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4748 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4749 new_val = IGB_20K_ITR;
abe1c363 4750
6eb5a7f1 4751set_itr_val:
047e0030
AD		 4752 if (new_val != q_vector->itr_val) {
4753 q_vector->itr_val = new_val;
4754 q_vector->set_itr = 1;
9d5c8243 4755 }
6eb5a7f1 4756clear_counts:
0ba82994
AD		 4757 q_vector->rx.total_bytes = 0;
4758 q_vector->rx.total_packets = 0;
4759 q_vector->tx.total_bytes = 0;
4760 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4761}
4762
4763/**
b980ac18
JK		 4764 * igb_update_itr - update the dynamic ITR value based on statistics
4765 * @q_vector: pointer to q_vector
4766 * @ring_container: ring info to update the itr for
4767 *
4768 * Stores a new ITR value based on packets and byte
4769 * counts during the last interrupt. The advantage of per interrupt
4770 * computation is faster updates and more accurate ITR for the current
4771 * traffic pattern. Constants in this function were computed
4772 * based on theoretical maximum wire speed and thresholds were set based
4773 * on testing data as well as attempting to minimize response time
4774 * while increasing bulk throughput.
406d4965 4775 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4776 * NOTE: These calculations are only valid when operating in a single-
4777 * queue environment.
9d5c8243 4778 **/
0ba82994
AD		 4779static void igb_update_itr(struct igb_q_vector *q_vector,
4780 struct igb_ring_container *ring_container)
9d5c8243 4781{
0ba82994
AD		 4782 unsigned int packets = ring_container->total_packets;
4783 unsigned int bytes = ring_container->total_bytes;
4784 u8 itrval = ring_container->itr;
9d5c8243 4785
0ba82994 4786 /* no packets, exit with status unchanged */
9d5c8243 4787 if (packets == 0)
0ba82994 4788 return;
9d5c8243 4789
0ba82994 4790 switch (itrval) {
9d5c8243
AK		 4791 case lowest_latency:
4792 /* handle TSO and jumbo frames */
4793 if (bytes/packets > 8000)
0ba82994 4794 itrval = bulk_latency;
9d5c8243 4795 else if ((packets < 5) && (bytes > 512))
0ba82994 4796 itrval = low_latency;
9d5c8243
AK		 4797 break;
4798 case low_latency: /* 50 usec aka 20000 ints/s */
4799 if (bytes > 10000) {
4800 /* this if handles the TSO accounting */
d34a15ab 4801 if (bytes/packets > 8000)
0ba82994 4802 itrval = bulk_latency;
d34a15ab 4803 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4804 itrval = bulk_latency;
d34a15ab 4805 else if ((packets > 35))
0ba82994 4806 itrval = lowest_latency;
9d5c8243 4807 } else if (bytes/packets > 2000) {
0ba82994 4808 itrval = bulk_latency;
9d5c8243 4809 } else if (packets <= 2 && bytes < 512) {
0ba82994 4810 itrval = lowest_latency;
9d5c8243
AK		 4811 }
4812 break;
4813 case bulk_latency: /* 250 usec aka 4000 ints/s */
4814 if (bytes > 25000) {
4815 if (packets > 35)
0ba82994 4816 itrval = low_latency;
1e5c3d21 4817 } else if (bytes < 1500) {
0ba82994 4818 itrval = low_latency;
9d5c8243
AK		 4819 }
4820 break;
4821 }
4822
0ba82994
AD		 4823 /* clear work counters since we have the values we need */
4824 ring_container->total_bytes = 0;
4825 ring_container->total_packets = 0;
4826
4827 /* write updated itr to ring container */
4828 ring_container->itr = itrval;
9d5c8243
AK		 4829}
4830
0ba82994 4831static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4832{
0ba82994 4833 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4834 u32 new_itr = q_vector->itr_val;
0ba82994 4835 u8 current_itr = 0;
9d5c8243
AK		 4836
4837 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4838 if (adapter->link_speed != SPEED_1000) {
4839 current_itr = 0;
0ba82994 4840 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4841 goto set_itr_now;
4842 }
4843
0ba82994
AD		 4844 igb_update_itr(q_vector, &q_vector->tx);
4845 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4846
0ba82994 4847 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4848
6eb5a7f1 4849 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4850 if (current_itr == lowest_latency &&
4851 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4852 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4853 current_itr = low_latency;
4854
9d5c8243
AK		 4855 switch (current_itr) {
4856 /* counts and packets in update_itr are dependent on these numbers */
4857 case lowest_latency:
0ba82994 4858 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4859 break;
4860 case low_latency:
0ba82994 4861 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4862 break;
4863 case bulk_latency:
0ba82994 4864 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4865 break;
4866 default:
4867 break;
4868 }
4869
4870set_itr_now:
047e0030 4871 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4872 /* this attempts to bias the interrupt rate towards Bulk
4873 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4874 * increasing
4875 */
047e0030 4876 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4877 max((new_itr * q_vector->itr_val) /
4878 (new_itr + (q_vector->itr_val >> 2)),
4879 new_itr) : new_itr;
9d5c8243
AK		 4880 /* Don't write the value here; it resets the adapter's
4881 * internal timer, and causes us to delay far longer than
4882 * we should between interrupts. Instead, we write the ITR
4883 * value at the beginning of the next interrupt so the timing
4884 * ends up being correct.
4885 */
047e0030
AD		 4886 q_vector->itr_val = new_itr;
4887 q_vector->set_itr = 1;
9d5c8243 4888 }
9d5c8243
AK		 4889}
4890
c50b52a0
SH		 4891static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4892 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4893{
4894 struct e1000_adv_tx_context_desc *context_desc;
4895 u16 i = tx_ring->next_to_use;
4896
4897 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4898
4899 i++;
4900 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4901
4902 /* set bits to identify this as an advanced context descriptor */
4903 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4904
4905 /* For 82575, context index must be unique per ring. */
866cff06 4906 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4907 mss_l4len_idx |= tx_ring->reg_idx << 4;
4908
4909 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4910 context_desc->seqnum_seed = 0;
4911 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4912 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4913}
4914
7af40ad9
AD		 4915static int igb_tso(struct igb_ring *tx_ring,
4916 struct igb_tx_buffer *first,
4917 u8 *hdr_len)
9d5c8243 4918{
e10715d3 4919 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7af40ad9 4920 struct sk_buff *skb = first->skb;
e10715d3
AD		 4921 union {
4922 struct iphdr *v4;
4923 struct ipv6hdr *v6;
4924 unsigned char *hdr;
4925 } ip;
4926 union {
4927 struct tcphdr *tcp;
4928 unsigned char *hdr;
4929 } l4;
4930 u32 paylen, l4_offset;
06c14e5a 4931 int err;
7d13a7d0 4932
ed6aa105
AD		 4933 if (skb->ip_summed != CHECKSUM_PARTIAL)
4934 return 0;
4935
7d13a7d0
AD		 4936 if (!skb_is_gso(skb))
4937 return 0;
9d5c8243 4938
06c14e5a
FR		 4939 err = skb_cow_head(skb, 0);
4940 if (err < 0)
4941 return err;
9d5c8243 4942
e10715d3
AD		 4943 ip.hdr = skb_network_header(skb);
4944 l4.hdr = skb_checksum_start(skb);
4945
7d13a7d0
AD		 4946 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4947 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4948
e10715d3
AD		 4949 /* initialize outer IP header fields */
4950 if (ip.v4->version == 4) {
516165a1
AD		 4951 unsigned char *csum_start = skb_checksum_start(skb);
4952 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
4953
e10715d3
AD		 4954 /* IP header will have to cancel out any data that
4955 * is not a part of the outer IP header
4956 */
516165a1
AD		 4957 ip.v4->check = csum_fold(csum_partial(trans_start,
4958 csum_start - trans_start,
4959 0));
7d13a7d0 4960 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
e10715d3
AD		 4961
4962 ip.v4->tot_len = 0;
7af40ad9
AD		 4963 first->tx_flags |= IGB_TX_FLAGS_TSO |
4964 IGB_TX_FLAGS_CSUM |
4965 IGB_TX_FLAGS_IPV4;
e10715d3
AD		 4966 } else {
4967 ip.v6->payload_len = 0;
7af40ad9
AD		 4968 first->tx_flags |= IGB_TX_FLAGS_TSO |
4969 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4970 }
4971
e10715d3
AD		 4972 /* determine offset of inner transport header */
4973 l4_offset = l4.hdr - skb->data;
4974
4975 /* compute length of segmentation header */
4976 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
4977
4978 /* remove payload length from inner checksum */
4979 paylen = skb->len - l4_offset;
4980 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
9d5c8243 4981
7af40ad9
AD		 4982 /* update gso size and bytecount with header size */
4983 first->gso_segs = skb_shinfo(skb)->gso_segs;
4984 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4985
9d5c8243 4986 /* MSS L4LEN IDX */
e10715d3 4987 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
7d13a7d0 4988 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4989
7d13a7d0 4990 /* VLAN MACLEN IPLEN */
e10715d3
AD		 4991 vlan_macip_lens = l4.hdr - ip.hdr;
4992 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4993 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4994
7d13a7d0 4995 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4996
7d13a7d0 4997 return 1;
9d5c8243
AK		 4998}
4999
6e033700
AD		 5000static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
5001{
5002 unsigned int offset = 0;
5003
5004 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
5005
5006 return offset == skb_checksum_start_offset(skb);
5007}
5008
7af40ad9 5009static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 5010{
7af40ad9 5011 struct sk_buff *skb = first->skb;
7d13a7d0 5012 u32 vlan_macip_lens = 0;
7d13a7d0 5013 u32 type_tucmd = 0;
9d5c8243 5014
7d13a7d0 5015 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6e033700 5016csum_failed:
7af40ad9
AD		 5017 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
5018 return;
6e033700
AD		 5019 goto no_csum;
5020 }
fa4a7ef3 5021
6e033700
AD		 5022 switch (skb->csum_offset) {
5023 case offsetof(struct tcphdr, check):
5024 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5025 /* fall through */
5026 case offsetof(struct udphdr, check):
5027 break;
5028 case offsetof(struct sctphdr, checksum):
5029 /* validate that this is actually an SCTP request */
5030 if (((first->protocol == htons(ETH_P_IP)) &&
5031 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
5032 ((first->protocol == htons(ETH_P_IPV6)) &&
5033 igb_ipv6_csum_is_sctp(skb))) {
5034 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
7d13a7d0 5035 break;
9d5c8243 5036 }
6e033700
AD		 5037 default:
5038 skb_checksum_help(skb);
5039 goto csum_failed;
7d13a7d0 5040 }
9d5c8243 5041
6e033700
AD		 5042 /* update TX checksum flag */
5043 first->tx_flags |= IGB_TX_FLAGS_CSUM;
5044 vlan_macip_lens = skb_checksum_start_offset(skb) -
5045 skb_network_offset(skb);
5046no_csum:
7d13a7d0 5047 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 5048 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 5049
6e033700 5050 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
9d5c8243
AK		 5051}
5052
1d9daf45
AD		 5053#define IGB_SET_FLAG(_input, _flag, _result) \
5054 ((_flag <= _result) ? \
5055 ((u32)(_input & _flag) * (_result / _flag)) : \
5056 ((u32)(_input & _flag) / (_flag / _result)))
5057
5058static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 5059{
5060 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 5061 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5062 E1000_ADVTXD_DCMD_DEXT |
5063 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 5064
5065 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 5066 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5067 (E1000_ADVTXD_DCMD_VLE));
5068
5069 /* set segmentation bits for TSO */
5070 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5071 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 5072
5073 /* set timestamp bit if present */
1d9daf45
AD		 5074 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5075 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 5076
1d9daf45
AD		 5077 /* insert frame checksum */
5078 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 5079
5080 return cmd_type;
5081}
5082
7af40ad9
AD		 5083static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5084 union e1000_adv_tx_desc *tx_desc,
5085 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 5086{
5087 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5088
1d9daf45
AD		 5089 /* 82575 requires a unique index per ring */
5090 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 5091 olinfo_status |= tx_ring->reg_idx << 4;
5092
5093 /* insert L4 checksum */
1d9daf45
AD		 5094 olinfo_status |= IGB_SET_FLAG(tx_flags,
5095 IGB_TX_FLAGS_CSUM,
5096 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 5097
1d9daf45
AD		 5098 /* insert IPv4 checksum */
5099 olinfo_status |= IGB_SET_FLAG(tx_flags,
5100 IGB_TX_FLAGS_IPV4,
5101 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 5102
7af40ad9 5103 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 5104}
5105
6f19e12f
DM		 5106static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5107{
5108 struct net_device *netdev = tx_ring->netdev;
5109
5110 netif_stop_subqueue(netdev, tx_ring->queue_index);
5111
5112 /* Herbert's original patch had:
5113 * smp_mb__after_netif_stop_queue();
5114 * but since that doesn't exist yet, just open code it.
5115 */
5116 smp_mb();
5117
5118 /* We need to check again in a case another CPU has just
5119 * made room available.
5120 */
5121 if (igb_desc_unused(tx_ring) < size)
5122 return -EBUSY;
5123
5124 /* A reprieve! */
5125 netif_wake_subqueue(netdev, tx_ring->queue_index);
5126
5127 u64_stats_update_begin(&tx_ring->tx_syncp2);
5128 tx_ring->tx_stats.restart_queue2++;
5129 u64_stats_update_end(&tx_ring->tx_syncp2);
5130
5131 return 0;
5132}
5133
5134static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5135{
5136 if (igb_desc_unused(tx_ring) >= size)
5137 return 0;
5138 return __igb_maybe_stop_tx(tx_ring, size);
5139}
5140
7af40ad9
AD		 5141static void igb_tx_map(struct igb_ring *tx_ring,
5142 struct igb_tx_buffer *first,
ebe42d16 5143 const u8 hdr_len)
9d5c8243 5144{
7af40ad9 5145 struct sk_buff *skb = first->skb;
c9f14bf3 5146 struct igb_tx_buffer *tx_buffer;
ebe42d16 5147 union e1000_adv_tx_desc *tx_desc;
80d0759e 5148 struct skb_frag_struct *frag;
ebe42d16 5149 dma_addr_t dma;
80d0759e 5150 unsigned int data_len, size;
7af40ad9 5151 u32 tx_flags = first->tx_flags;
1d9daf45 5152 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 5153 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 5154
5155 tx_desc = IGB_TX_DESC(tx_ring, i);
5156
80d0759e
AD		 5157 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5158
5159 size = skb_headlen(skb);
5160 data_len = skb->data_len;
ebe42d16
AD		 5161
5162 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 5163
80d0759e
AD		 5164 tx_buffer = first;
5165
5166 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5167 if (dma_mapping_error(tx_ring->dev, dma))
5168 goto dma_error;
5169
5170 /* record length, and DMA address */
5171 dma_unmap_len_set(tx_buffer, len, size);
5172 dma_unmap_addr_set(tx_buffer, dma, dma);
5173
5174 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5175
ebe42d16
AD		 5176 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5177 tx_desc->read.cmd_type_len =
1d9daf45 5178 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5179
5180 i++;
5181 tx_desc++;
5182 if (i == tx_ring->count) {
5183 tx_desc = IGB_TX_DESC(tx_ring, 0);
5184 i = 0;
5185 }
80d0759e 5186 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5187
5188 dma += IGB_MAX_DATA_PER_TXD;
5189 size -= IGB_MAX_DATA_PER_TXD;
5190
ebe42d16
AD		 5191 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5192 }
5193
5194 if (likely(!data_len))
5195 break;
2bbfebe2 5196
1d9daf45 5197 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5198
65689fef 5199 i++;
ebe42d16
AD		 5200 tx_desc++;
5201 if (i == tx_ring->count) {
5202 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5203 i = 0;
ebe42d16 5204 }
80d0759e 5205 tx_desc->read.olinfo_status = 0;
65689fef 5206
9e903e08 5207 size = skb_frag_size(frag);
ebe42d16
AD		 5208 data_len -= size;
5209
5210 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5211 size, DMA_TO_DEVICE);
6366ad33 5212
c9f14bf3 5213 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5214 }
5215
ebe42d16 5216 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5217 cmd_type |= size | IGB_TXD_DCMD;
5218 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5219
80d0759e
AD		 5220 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5221
8542db05
AD		 5222 /* set the timestamp */
5223 first->time_stamp = jiffies;
5224
b980ac18 5225 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5226 * are new descriptors to fetch. (Only applicable for weak-ordered
5227 * memory model archs, such as IA-64).
5228 *
5229 * We also need this memory barrier to make certain all of the
5230 * status bits have been updated before next_to_watch is written.
5231 */
5232 wmb();
5233
8542db05 5234 /* set next_to_watch value indicating a packet is present */
ebe42d16 5235 first->next_to_watch = tx_desc;
9d5c8243 5236
ebe42d16
AD		 5237 i++;
5238 if (i == tx_ring->count)
5239 i = 0;
6366ad33 5240
ebe42d16 5241 tx_ring->next_to_use = i;
6366ad33 5242
6f19e12f
DM		 5243 /* Make sure there is space in the ring for the next send. */
5244 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5245
5246 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5247 writel(i, tx_ring->tail);
5248
5249 /* we need this if more than one processor can write to our tail
5250 * at a time, it synchronizes IO on IA64/Altix systems
5251 */
5252 mmiowb();
5253 }
ebe42d16
AD		 5254 return;
5255
5256dma_error:
5257 dev_err(tx_ring->dev, "TX DMA map failed\n");
5258
5259 /* clear dma mappings for failed tx_buffer_info map */
5260 for (;;) {
c9f14bf3
AD		 5261 tx_buffer = &tx_ring->tx_buffer_info[i];
5262 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5263 if (tx_buffer == first)
ebe42d16 5264 break;
a77ff709
NN		 5265 if (i == 0)
5266 i = tx_ring->count;
6366ad33 5267 i--;
6366ad33
AD		 5268 }
5269
9d5c8243 5270 tx_ring->next_to_use = i;
9d5c8243
AK		 5271}
5272
cd392f5c
AD		 5273netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5274 struct igb_ring *tx_ring)
9d5c8243 5275{
8542db05 5276 struct igb_tx_buffer *first;
ebe42d16 5277 int tso;
91d4ee33 5278 u32 tx_flags = 0;
2ee52ad4 5279 unsigned short f;
21ba6fe1 5280 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5281 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5282 u8 hdr_len = 0;
9d5c8243 5283
21ba6fe1
AD		 5284 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5285 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5286 * + 2 desc gap to keep tail from touching head,
9d5c8243 5287 * + 1 desc for context descriptor,
21ba6fe1
AD		 5288 * otherwise try next time
5289 */
2ee52ad4
AD		 5290 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5291 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5292
5293 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5294 /* this is a hard error */
9d5c8243
AK		 5295 return NETDEV_TX_BUSY;
5296 }
33af6bcc 5297
7af40ad9
AD		 5298 /* record the location of the first descriptor for this packet */
5299 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5300 first->skb = skb;
5301 first->bytecount = skb->len;
5302 first->gso_segs = 1;
5303
b646c22e
AD		 5304 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5305 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5306
ed4420a3
JK		 5307 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5308 &adapter->state)) {
b646c22e
AD		 5309 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5310 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5311
5312 adapter->ptp_tx_skb = skb_get(skb);
5313 adapter->ptp_tx_start = jiffies;
5314 if (adapter->hw.mac.type == e1000_82576)
5315 schedule_work(&adapter->ptp_tx_work);
5316 }
33af6bcc 5317 }
9d5c8243 5318
afc835d1
JK		 5319 skb_tx_timestamp(skb);
5320
df8a39de 5321 if (skb_vlan_tag_present(skb)) {
9d5c8243 5322 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5323 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5324 }
5325
7af40ad9
AD		 5326 /* record initial flags and protocol */
5327 first->tx_flags = tx_flags;
5328 first->protocol = protocol;
cdfd01fc 5329
7af40ad9
AD		 5330 tso = igb_tso(tx_ring, first, &hdr_len);
5331 if (tso < 0)
7d13a7d0 5332 goto out_drop;
7af40ad9
AD		 5333 else if (!tso)
5334 igb_tx_csum(tx_ring, first);
9d5c8243 5335
7af40ad9 5336 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5337
9d5c8243 5338 return NETDEV_TX_OK;
7d13a7d0
AD		 5339
5340out_drop:
7af40ad9
AD		 5341 igb_unmap_and_free_tx_resource(tx_ring, first);
5342
7d13a7d0 5343 return NETDEV_TX_OK;
9d5c8243
AK		 5344}
5345
0b725a2c
DM		 5346static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5347 struct sk_buff *skb)
1cc3bd87 5348{
0b725a2c
DM		 5349 unsigned int r_idx = skb->queue_mapping;
5350
1cc3bd87
AD		 5351 if (r_idx >= adapter->num_tx_queues)
5352 r_idx = r_idx % adapter->num_tx_queues;
5353
5354 return adapter->tx_ring[r_idx];
5355}
5356
cd392f5c
AD		 5357static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5358 struct net_device *netdev)
9d5c8243
AK		 5359{
5360 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3 5361
b980ac18 5362 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5363 * in order to meet this minimum size requirement.
5364 */
a94d9e22
AD		 5365 if (skb_put_padto(skb, 17))
5366 return NETDEV_TX_OK;
9d5c8243 5367
1cc3bd87 5368 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5369}
5370
5371/**
b980ac18
JK		 5372 * igb_tx_timeout - Respond to a Tx Hang
5373 * @netdev: network interface device structure
9d5c8243
AK		 5374 **/
5375static void igb_tx_timeout(struct net_device *netdev)
5376{
5377 struct igb_adapter *adapter = netdev_priv(netdev);
5378 struct e1000_hw *hw = &adapter->hw;
5379
5380 /* Do the reset outside of interrupt context */
5381 adapter->tx_timeout_count++;
f7ba205e 5382
06218a8d 5383 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5384 hw->dev_spec._82575.global_device_reset = true;
5385
9d5c8243 5386 schedule_work(&adapter->reset_task);
265de409
AD		 5387 wr32(E1000_EICS,
5388 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5389}
5390
5391static void igb_reset_task(struct work_struct *work)
5392{
5393 struct igb_adapter *adapter;
5394 adapter = container_of(work, struct igb_adapter, reset_task);
5395
c97ec42a
TI		 5396 igb_dump(adapter);
5397 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5398 igb_reinit_locked(adapter);
5399}
5400
5401/**
b980ac18
JK		 5402 * igb_get_stats64 - Get System Network Statistics
5403 * @netdev: network interface device structure
5404 * @stats: rtnl_link_stats64 pointer
9d5c8243 5405 **/
12dcd86b 5406static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5407 struct rtnl_link_stats64 *stats)
9d5c8243 5408{
12dcd86b
ED		 5409 struct igb_adapter *adapter = netdev_priv(netdev);
5410
5411 spin_lock(&adapter->stats64_lock);
5412 igb_update_stats(adapter, &adapter->stats64);
5413 memcpy(stats, &adapter->stats64, sizeof(*stats));
5414 spin_unlock(&adapter->stats64_lock);
5415
5416 return stats;
9d5c8243
AK		 5417}
5418
5419/**
b980ac18
JK		 5420 * igb_change_mtu - Change the Maximum Transfer Unit
5421 * @netdev: network interface device structure
5422 * @new_mtu: new value for maximum frame size
9d5c8243 5423 *
b980ac18 5424 * Returns 0 on success, negative on failure
9d5c8243
AK		 5425 **/
5426static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5427{
5428 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5429 struct pci_dev *pdev = adapter->pdev;
153285f9 5430 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5431
2ccd994c
AD		 5432 /* adjust max frame to be at least the size of a standard frame */
5433 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5434 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5435
9d5c8243 5436 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5437 usleep_range(1000, 2000);
73cd78f1 5438
9d5c8243
AK		 5439 /* igb_down has a dependency on max_frame_size */
5440 adapter->max_frame_size = max_frame;
559e9c49 5441
4c844851
AD		 5442 if (netif_running(netdev))
5443 igb_down(adapter);
9d5c8243 5444
090b1795 5445 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5446 netdev->mtu, new_mtu);
5447 netdev->mtu = new_mtu;
5448
5449 if (netif_running(netdev))
5450 igb_up(adapter);
5451 else
5452 igb_reset(adapter);
5453
5454 clear_bit(__IGB_RESETTING, &adapter->state);
5455
5456 return 0;
5457}
5458
5459/**
b980ac18
JK		 5460 * igb_update_stats - Update the board statistics counters
5461 * @adapter: board private structure
9d5c8243 5462 **/
12dcd86b
ED		 5463void igb_update_stats(struct igb_adapter *adapter,
5464 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5465{
5466 struct e1000_hw *hw = &adapter->hw;
5467 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5468 u32 reg, mpc;
3f9c0164
AD		 5469 int i;
5470 u64 bytes, packets;
12dcd86b
ED		 5471 unsigned int start;
5472 u64 _bytes, _packets;
9d5c8243 5473
b980ac18 5474 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5475 * connection is down.
5476 */
5477 if (adapter->link_speed == 0)
5478 return;
5479 if (pci_channel_offline(pdev))
5480 return;
5481
3f9c0164
AD		 5482 bytes = 0;
5483 packets = 0;
7f90128e
AA		 5484
5485 rcu_read_lock();
3f9c0164 5486 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5487 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5488 u32 rqdpc = rd32(E1000_RQDPC(i));
5489 if (hw->mac.type >= e1000_i210)
5490 wr32(E1000_RQDPC(i), 0);
12dcd86b 5491
ae1c07a6
AD		 5492 if (rqdpc) {
5493 ring->rx_stats.drops += rqdpc;
5494 net_stats->rx_fifo_errors += rqdpc;
5495 }
12dcd86b
ED		 5496
5497 do {
57a7744e 5498 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5499 _bytes = ring->rx_stats.bytes;
5500 _packets = ring->rx_stats.packets;
57a7744e 5501 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5502 bytes += _bytes;
5503 packets += _packets;
3f9c0164
AD		 5504 }
5505
128e45eb
AD		 5506 net_stats->rx_bytes = bytes;
5507 net_stats->rx_packets = packets;
3f9c0164
AD		 5508
5509 bytes = 0;
5510 packets = 0;
5511 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5512 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5513 do {
57a7744e 5514 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5515 _bytes = ring->tx_stats.bytes;
5516 _packets = ring->tx_stats.packets;
57a7744e 5517 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5518 bytes += _bytes;
5519 packets += _packets;
3f9c0164 5520 }
128e45eb
AD		 5521 net_stats->tx_bytes = bytes;
5522 net_stats->tx_packets = packets;
7f90128e 5523 rcu_read_unlock();
3f9c0164
AD		 5524
5525 /* read stats registers */
9d5c8243
AK		 5526 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5527 adapter->stats.gprc += rd32(E1000_GPRC);
5528 adapter->stats.gorc += rd32(E1000_GORCL);
5529 rd32(E1000_GORCH); /* clear GORCL */
5530 adapter->stats.bprc += rd32(E1000_BPRC);
5531 adapter->stats.mprc += rd32(E1000_MPRC);
5532 adapter->stats.roc += rd32(E1000_ROC);
5533
5534 adapter->stats.prc64 += rd32(E1000_PRC64);
5535 adapter->stats.prc127 += rd32(E1000_PRC127);
5536 adapter->stats.prc255 += rd32(E1000_PRC255);
5537 adapter->stats.prc511 += rd32(E1000_PRC511);
5538 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5539 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5540 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5541 adapter->stats.sec += rd32(E1000_SEC);
5542
fa3d9a6d
MW		 5543 mpc = rd32(E1000_MPC);
5544 adapter->stats.mpc += mpc;
5545 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5546 adapter->stats.scc += rd32(E1000_SCC);
5547 adapter->stats.ecol += rd32(E1000_ECOL);
5548 adapter->stats.mcc += rd32(E1000_MCC);
5549 adapter->stats.latecol += rd32(E1000_LATECOL);
5550 adapter->stats.dc += rd32(E1000_DC);
5551 adapter->stats.rlec += rd32(E1000_RLEC);
5552 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5553 adapter->stats.xontxc += rd32(E1000_XONTXC);
5554 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5555 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5556 adapter->stats.fcruc += rd32(E1000_FCRUC);
5557 adapter->stats.gptc += rd32(E1000_GPTC);
5558 adapter->stats.gotc += rd32(E1000_GOTCL);
5559 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5560 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5561 adapter->stats.ruc += rd32(E1000_RUC);
5562 adapter->stats.rfc += rd32(E1000_RFC);
5563 adapter->stats.rjc += rd32(E1000_RJC);
5564 adapter->stats.tor += rd32(E1000_TORH);
5565 adapter->stats.tot += rd32(E1000_TOTH);
5566 adapter->stats.tpr += rd32(E1000_TPR);
5567
5568 adapter->stats.ptc64 += rd32(E1000_PTC64);
5569 adapter->stats.ptc127 += rd32(E1000_PTC127);
5570 adapter->stats.ptc255 += rd32(E1000_PTC255);
5571 adapter->stats.ptc511 += rd32(E1000_PTC511);
5572 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5573 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5574
5575 adapter->stats.mptc += rd32(E1000_MPTC);
5576 adapter->stats.bptc += rd32(E1000_BPTC);
5577
2d0b0f69
NN		 5578 adapter->stats.tpt += rd32(E1000_TPT);
5579 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5580
5581 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5582 /* read internal phy specific stats */
5583 reg = rd32(E1000_CTRL_EXT);
5584 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5585 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5586
5587 /* this stat has invalid values on i210/i211 */
5588 if ((hw->mac.type != e1000_i210) &&
5589 (hw->mac.type != e1000_i211))
5590 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5591 }
5592
9d5c8243
AK		 5593 adapter->stats.tsctc += rd32(E1000_TSCTC);
5594 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5595
5596 adapter->stats.iac += rd32(E1000_IAC);
5597 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5598 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5599 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5600 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5601 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5602 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5603 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5604 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5605
5606 /* Fill out the OS statistics structure */
128e45eb
AD		 5607 net_stats->multicast = adapter->stats.mprc;
5608 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5609
5610 /* Rx Errors */
5611
5612 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5613 * our own version based on RUC and ROC
5614 */
128e45eb 5615 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5616 adapter->stats.crcerrs + adapter->stats.algnerrc +
5617 adapter->stats.ruc + adapter->stats.roc +
5618 adapter->stats.cexterr;
128e45eb
AD		 5619 net_stats->rx_length_errors = adapter->stats.ruc +
5620 adapter->stats.roc;
5621 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5622 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5623 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5624
5625 /* Tx Errors */
128e45eb
AD		 5626 net_stats->tx_errors = adapter->stats.ecol +
5627 adapter->stats.latecol;
5628 net_stats->tx_aborted_errors = adapter->stats.ecol;
5629 net_stats->tx_window_errors = adapter->stats.latecol;
5630 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5631
5632 /* Tx Dropped needs to be maintained elsewhere */
5633
9d5c8243
AK		 5634 /* Management Stats */
5635 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5636 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5637 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5638
5639 /* OS2BMC Stats */
5640 reg = rd32(E1000_MANC);
5641 if (reg & E1000_MANC_EN_BMC2OS) {
5642 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5643 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5644 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5645 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5646 }
9d5c8243
AK		 5647}
5648
61d7f75f
RC		 5649static void igb_tsync_interrupt(struct igb_adapter *adapter)
5650{
5651 struct e1000_hw *hw = &adapter->hw;
00c65578 5652 struct ptp_clock_event event;
40c9b079 5653 struct timespec64 ts;
720db4ff 5654 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5655
5656 if (tsicr & TSINTR_SYS_WRAP) {
5657 event.type = PTP_CLOCK_PPS;
5658 if (adapter->ptp_caps.pps)
5659 ptp_clock_event(adapter->ptp_clock, &event);
5660 else
5661 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5662 ack |= TSINTR_SYS_WRAP;
5663 }
61d7f75f
RC		 5664
5665 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5666 /* retrieve hardware timestamp */
5667 schedule_work(&adapter->ptp_tx_work);
00c65578 5668 ack |= E1000_TSICR_TXTS;
61d7f75f 5669 }
00c65578 5670
720db4ff
RC		 5671 if (tsicr & TSINTR_TT0) {
5672 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5673 ts = timespec64_add(adapter->perout[0].start,
5674 adapter->perout[0].period);
5675 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5676 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5677 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5678 tsauxc = rd32(E1000_TSAUXC);
5679 tsauxc |= TSAUXC_EN_TT0;
5680 wr32(E1000_TSAUXC, tsauxc);
5681 adapter->perout[0].start = ts;
5682 spin_unlock(&adapter->tmreg_lock);
5683 ack |= TSINTR_TT0;
5684 }
5685
5686 if (tsicr & TSINTR_TT1) {
5687 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5688 ts = timespec64_add(adapter->perout[1].start,
5689 adapter->perout[1].period);
720db4ff 5690 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5691 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5692 tsauxc = rd32(E1000_TSAUXC);
5693 tsauxc |= TSAUXC_EN_TT1;
5694 wr32(E1000_TSAUXC, tsauxc);
5695 adapter->perout[1].start = ts;
5696 spin_unlock(&adapter->tmreg_lock);
5697 ack |= TSINTR_TT1;
5698 }
5699
5700 if (tsicr & TSINTR_AUTT0) {
5701 nsec = rd32(E1000_AUXSTMPL0);
5702 sec = rd32(E1000_AUXSTMPH0);
5703 event.type = PTP_CLOCK_EXTTS;
5704 event.index = 0;
5705 event.timestamp = sec * 1000000000ULL + nsec;
5706 ptp_clock_event(adapter->ptp_clock, &event);
5707 ack |= TSINTR_AUTT0;
5708 }
5709
5710 if (tsicr & TSINTR_AUTT1) {
5711 nsec = rd32(E1000_AUXSTMPL1);
5712 sec = rd32(E1000_AUXSTMPH1);
5713 event.type = PTP_CLOCK_EXTTS;
5714 event.index = 1;
5715 event.timestamp = sec * 1000000000ULL + nsec;
5716 ptp_clock_event(adapter->ptp_clock, &event);
5717 ack |= TSINTR_AUTT1;
5718 }
5719
00c65578
RC		 5720 /* acknowledge the interrupts */
5721 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5722}
5723
9d5c8243
AK		 5724static irqreturn_t igb_msix_other(int irq, void *data)
5725{
047e0030 5726 struct igb_adapter *adapter = data;
9d5c8243 5727 struct e1000_hw *hw = &adapter->hw;
844290e5 5728 u32 icr = rd32(E1000_ICR);
844290e5 5729 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5730
7f081d40
AD		 5731 if (icr & E1000_ICR_DRSTA)
5732 schedule_work(&adapter->reset_task);
5733
047e0030 5734 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5735 /* HW is reporting DMA is out of sync */
5736 adapter->stats.doosync++;
13800469
GR		 5737 /* The DMA Out of Sync is also indication of a spoof event
5738 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5739 * see if it is really a spoof event.
5740 */
13800469 5741 igb_check_wvbr(adapter);
dda0e083 5742 }
eebbbdba 5743
4ae196df
AD		 5744 /* Check for a mailbox event */
5745 if (icr & E1000_ICR_VMMB)
5746 igb_msg_task(adapter);
5747
5748 if (icr & E1000_ICR_LSC) {
5749 hw->mac.get_link_status = 1;
5750 /* guard against interrupt when we're going down */
5751 if (!test_bit(__IGB_DOWN, &adapter->state))
5752 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5753 }
5754
61d7f75f
RC		 5755 if (icr & E1000_ICR_TS)
5756 igb_tsync_interrupt(adapter);
1f6e8178 5757
844290e5 5758 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5759
5760 return IRQ_HANDLED;
5761}
5762
047e0030 5763static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5764{
26b39276 5765 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5766 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5767
047e0030
AD		 5768 if (!q_vector->set_itr)
5769 return;
73cd78f1 5770
047e0030
AD		 5771 if (!itr_val)
5772 itr_val = 0x4;
661086df 5773
26b39276
AD		 5774 if (adapter->hw.mac.type == e1000_82575)
5775 itr_val |= itr_val << 16;
661086df 5776 else
0ba82994 5777 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5778
047e0030
AD		 5779 writel(itr_val, q_vector->itr_register);
5780 q_vector->set_itr = 0;
6eb5a7f1
AD		 5781}
5782
047e0030 5783static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5784{
047e0030 5785 struct igb_q_vector *q_vector = data;
9d5c8243 5786
047e0030
AD		 5787 /* Write the ITR value calculated from the previous interrupt. */
5788 igb_write_itr(q_vector);
9d5c8243 5789
047e0030 5790 napi_schedule(&q_vector->napi);
844290e5 5791
047e0030 5792 return IRQ_HANDLED;
fe4506b6
JC		 5793}
5794
421e02f0 5795#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5796static void igb_update_tx_dca(struct igb_adapter *adapter,
5797 struct igb_ring *tx_ring,
5798 int cpu)
5799{
5800 struct e1000_hw *hw = &adapter->hw;
5801 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5802
5803 if (hw->mac.type != e1000_82575)
5804 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5805
b980ac18 5806 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5807 * DCA is enabled. This is due to a known issue in some chipsets
5808 * which will cause the DCA tag to be cleared.
5809 */
5810 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5811 E1000_DCA_TXCTRL_DATA_RRO_EN |
5812 E1000_DCA_TXCTRL_DESC_DCA_EN;
5813
5814 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5815}
5816
5817static void igb_update_rx_dca(struct igb_adapter *adapter,
5818 struct igb_ring *rx_ring,
5819 int cpu)
5820{
5821 struct e1000_hw *hw = &adapter->hw;
5822 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5823
5824 if (hw->mac.type != e1000_82575)
5825 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5826
b980ac18 5827 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5828 * DCA is enabled. This is due to a known issue in some chipsets
5829 * which will cause the DCA tag to be cleared.
5830 */
5831 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5832 E1000_DCA_RXCTRL_DESC_DCA_EN;
5833
5834 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5835}
5836
047e0030 5837static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5838{
047e0030 5839 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5840 int cpu = get_cpu();
fe4506b6 5841
047e0030
AD		 5842 if (q_vector->cpu == cpu)
5843 goto out_no_update;
5844
6a05004a
AD		 5845 if (q_vector->tx.ring)
5846 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5847
5848 if (q_vector->rx.ring)
5849 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5850
047e0030
AD		 5851 q_vector->cpu = cpu;
5852out_no_update:
fe4506b6
JC		 5853 put_cpu();
5854}
5855
5856static void igb_setup_dca(struct igb_adapter *adapter)
5857{
7e0e99ef 5858 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5859 int i;
5860
7dfc16fa 5861 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5862 return;
5863
7e0e99ef
AD		 5864 /* Always use CB2 mode, difference is masked in the CB driver. */
5865 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5866
047e0030 5867 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5868 adapter->q_vector[i]->cpu = -1;
5869 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5870 }
5871}
5872
5873static int __igb_notify_dca(struct device *dev, void *data)
5874{
5875 struct net_device *netdev = dev_get_drvdata(dev);
5876 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5877 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5878 struct e1000_hw *hw = &adapter->hw;
5879 unsigned long event = *(unsigned long *)data;
5880
5881 switch (event) {
5882 case DCA_PROVIDER_ADD:
5883 /* if already enabled, don't do it again */
7dfc16fa 5884 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5885 break;
fe4506b6 5886 if (dca_add_requester(dev) == 0) {
bbd98fe4 5887 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5888 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5889 igb_setup_dca(adapter);
5890 break;
5891 }
5892 /* Fall Through since DCA is disabled. */
5893 case DCA_PROVIDER_REMOVE:
7dfc16fa 5894 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5895 /* without this a class_device is left
b980ac18
JK		 5896 * hanging around in the sysfs model
5897 */
fe4506b6 5898 dca_remove_requester(dev);
090b1795 5899 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5900 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5901 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5902 }
5903 break;
5904 }
bbd98fe4 5905
fe4506b6 5906 return 0;
9d5c8243
AK		 5907}
5908
fe4506b6 5909static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5910 void *p)
fe4506b6
JC		 5911{
5912 int ret_val;
5913
5914 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5915 __igb_notify_dca);
fe4506b6
JC		 5916
5917 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5918}
421e02f0 5919#endif /* CONFIG_IGB_DCA */
9d5c8243 5920
0224d663
GR		 5921#ifdef CONFIG_PCI_IOV
5922static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5923{
5924 unsigned char mac_addr[ETH_ALEN];
0224d663 5925
5ac6f91d 5926 eth_zero_addr(mac_addr);
0224d663
GR		 5927 igb_set_vf_mac(adapter, vf, mac_addr);
5928
70ea4783
LL		 5929 /* By default spoof check is enabled for all VFs */
5930 adapter->vf_data[vf].spoofchk_enabled = true;
5931
f557147c 5932 return 0;
0224d663
GR		 5933}
5934
0224d663 5935#endif
4ae196df
AD		 5936static void igb_ping_all_vfs(struct igb_adapter *adapter)
5937{
5938 struct e1000_hw *hw = &adapter->hw;
5939 u32 ping;
5940 int i;
5941
5942 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5943 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5944 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5945 ping |= E1000_VT_MSGTYPE_CTS;
5946 igb_write_mbx(hw, &ping, 1, i);
5947 }
5948}
5949
7d5753f0
AD		 5950static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5951{
5952 struct e1000_hw *hw = &adapter->hw;
5953 u32 vmolr = rd32(E1000_VMOLR(vf));
5954 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5955
d85b9004 5956 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5957 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5958 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5959
5960 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5961 vmolr |= E1000_VMOLR_MPME;
d85b9004 5962 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5963 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5964 } else {
b980ac18 5965 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5966 * flag we need to write the hashes to the MTA as this step
5967 * was previously skipped
5968 */
5969 if (vf_data->num_vf_mc_hashes > 30) {
5970 vmolr |= E1000_VMOLR_MPME;
5971 } else if (vf_data->num_vf_mc_hashes) {
5972 int j;
9005df38 5973
7d5753f0
AD		 5974 vmolr |= E1000_VMOLR_ROMPE;
5975 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5976 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5977 }
5978 }
5979
5980 wr32(E1000_VMOLR(vf), vmolr);
5981
5982 /* there are flags left unprocessed, likely not supported */
5983 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5984 return -EINVAL;
5985
5986 return 0;
7d5753f0
AD		 5987}
5988
4ae196df
AD		 5989static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5990 u32 *msgbuf, u32 vf)
5991{
5992 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5993 u16 *hash_list = (u16 *)&msgbuf[1];
5994 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5995 int i;
5996
7d5753f0 5997 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5998 * to this VF for later use to restore when the PF multi cast
5999 * list changes
6000 */
6001 vf_data->num_vf_mc_hashes = n;
6002
7d5753f0
AD		 6003 /* only up to 30 hash values supported */
6004 if (n > 30)
6005 n = 30;
6006
6007 /* store the hashes for later use */
4ae196df 6008 for (i = 0; i < n; i++)
a419aef8 6009 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 6010
6011 /* Flush and reset the mta with the new values */
ff41f8dc 6012 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6013
6014 return 0;
6015}
6016
6017static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
6018{
6019 struct e1000_hw *hw = &adapter->hw;
6020 struct vf_data_storage *vf_data;
6021 int i, j;
6022
6023 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 6024 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 6025
7d5753f0
AD		 6026 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6027
4ae196df 6028 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 6029
6030 if ((vf_data->num_vf_mc_hashes > 30) ||
6031 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6032 vmolr |= E1000_VMOLR_MPME;
6033 } else if (vf_data->num_vf_mc_hashes) {
6034 vmolr |= E1000_VMOLR_ROMPE;
6035 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6036 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6037 }
6038 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 6039 }
6040}
6041
6042static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6043{
6044 struct e1000_hw *hw = &adapter->hw;
16903caa 6045 u32 pool_mask, vlvf_mask, i;
4ae196df 6046
16903caa
AD		 6047 /* create mask for VF and other pools */
6048 pool_mask = E1000_VLVF_POOLSEL_MASK;
a51d8c21 6049 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
16903caa
AD		 6050
6051 /* drop PF from pool bits */
a51d8c21
JK		 6052 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6053 adapter->vfs_allocated_count);
4ae196df
AD		 6054
6055 /* Find the vlan filter for this id */
16903caa
AD		 6056 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6057 u32 vlvf = rd32(E1000_VLVF(i));
6058 u32 vfta_mask, vid, vfta;
4ae196df
AD		 6059
6060 /* remove the vf from the pool */
16903caa
AD		 6061 if (!(vlvf & vlvf_mask))
6062 continue;
6063
6064 /* clear out bit from VLVF */
6065 vlvf ^= vlvf_mask;
6066
6067 /* if other pools are present, just remove ourselves */
6068 if (vlvf & pool_mask)
6069 goto update_vlvfb;
4ae196df 6070
16903caa
AD		 6071 /* if PF is present, leave VFTA */
6072 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6073 goto update_vlvf;
4ae196df 6074
16903caa 6075 vid = vlvf & E1000_VLVF_VLANID_MASK;
a51d8c21 6076 vfta_mask = BIT(vid % 32);
16903caa
AD		 6077
6078 /* clear bit from VFTA */
6079 vfta = adapter->shadow_vfta[vid / 32];
6080 if (vfta & vfta_mask)
6081 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6082update_vlvf:
6083 /* clear pool selection enable */
6084 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6085 vlvf &= E1000_VLVF_POOLSEL_MASK;
6086 else
6087 vlvf = 0;
6088update_vlvfb:
6089 /* clear pool bits */
6090 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 6091 }
6092}
ae641bdc 6093
16903caa 6094static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 6095{
16903caa
AD		 6096 u32 vlvf;
6097 int idx;
6f3dc319 6098
16903caa
AD		 6099 /* short cut the special case */
6100 if (vlan == 0)
6101 return 0;
6102
6103 /* Search for the VLAN id in the VLVF entries */
6104 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6105 vlvf = rd32(E1000_VLVF(idx));
6106 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 6107 break;
6108 }
6109
16903caa 6110 return idx;
4ae196df
AD		 6111}
6112
8008f68c 6113static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
4ae196df
AD		 6114{
6115 struct e1000_hw *hw = &adapter->hw;
16903caa
AD		 6116 u32 bits, pf_id;
6117 int idx;
51466239 6118
16903caa
AD		 6119 idx = igb_find_vlvf_entry(hw, vid);
6120 if (!idx)
6121 return;
4ae196df 6122
16903caa
AD		 6123 /* See if any other pools are set for this VLAN filter
6124 * entry other than the PF.
6125 */
6126 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
a51d8c21 6127 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
16903caa
AD		 6128 bits &= rd32(E1000_VLVF(idx));
6129
6130 /* Disable the filter so this falls into the default pool. */
6131 if (!bits) {
6132 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
a51d8c21 6133 wr32(E1000_VLVF(idx), BIT(pf_id));
16903caa
AD		 6134 else
6135 wr32(E1000_VLVF(idx), 0);
4ae196df 6136 }
6f3dc319 6137}
4ae196df 6138
a15d9259
AD		 6139static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6140 bool add, u32 vf)
4ae196df 6141{
a15d9259 6142 int pf_id = adapter->vfs_allocated_count;
6f3dc319 6143 struct e1000_hw *hw = &adapter->hw;
a15d9259 6144 int err;
ae641bdc 6145
a15d9259
AD		 6146 /* If VLAN overlaps with one the PF is currently monitoring make
6147 * sure that we are able to allocate a VLVF entry. This may be
6148 * redundant but it guarantees PF will maintain visibility to
6149 * the VLAN.
6f3dc319 6150 */
16903caa 6151 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6152 err = igb_vfta_set(hw, vid, pf_id, true, false);
6153 if (err)
6154 return err;
4ae196df 6155 }
6f3dc319 6156
a15d9259 6157 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6158
16903caa
AD		 6159 if (add && !err)
6160 return err;
6f3dc319 6161
16903caa
AD		 6162 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6163 * we may need to drop the PF pool bit in order to allow us to free
6164 * up the VLVF resources.
6f3dc319 6165 */
16903caa
AD		 6166 if (test_bit(vid, adapter->active_vlans) ||
6167 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6168 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6169
6f3dc319 6170 return err;
8151d294
WM		 6171}
6172
6173static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6174{
6175 struct e1000_hw *hw = &adapter->hw;
6176
6177 if (vid)
6178 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6179 else
6180 wr32(E1000_VMVIR(vf), 0);
6181}
6182
a15d9259
AD		 6183static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6184 u16 vlan, u8 qos)
8151d294 6185{
a15d9259 6186 int err;
8151d294 6187
a15d9259
AD		 6188 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6189 if (err)
6190 return err;
6191
6192 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6193 igb_set_vmolr(adapter, vf, !vlan);
6194
6195 /* revoke access to previous VLAN */
6196 if (vlan != adapter->vf_data[vf].pf_vlan)
6197 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6198 false, vf);
6199
6200 adapter->vf_data[vf].pf_vlan = vlan;
6201 adapter->vf_data[vf].pf_qos = qos;
030f9f52 6202 igb_set_vf_vlan_strip(adapter, vf, true);
a15d9259
AD		 6203 dev_info(&adapter->pdev->dev,
6204 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6205 if (test_bit(__IGB_DOWN, &adapter->state)) {
6206 dev_warn(&adapter->pdev->dev,
6207 "The VF VLAN has been set, but the PF device is not up.\n");
6208 dev_warn(&adapter->pdev->dev,
6209 "Bring the PF device up before attempting to use the VF device.\n");
b980ac18 6210 }
a15d9259 6211
b980ac18 6212 return err;
4ae196df
AD		 6213}
6214
a15d9259 6215static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6f3dc319 6216{
a15d9259
AD		 6217 /* Restore tagless access via VLAN 0 */
6218 igb_set_vf_vlan(adapter, 0, true, vf);
6f3dc319 6219
a15d9259 6220 igb_set_vmvir(adapter, 0, vf);
8151d294 6221 igb_set_vmolr(adapter, vf, true);
4ae196df 6222
a15d9259
AD		 6223 /* Remove any PF assigned VLAN */
6224 if (adapter->vf_data[vf].pf_vlan)
6225 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6226 false, vf);
6f3dc319 6227
a15d9259
AD		 6228 adapter->vf_data[vf].pf_vlan = 0;
6229 adapter->vf_data[vf].pf_qos = 0;
030f9f52 6230 igb_set_vf_vlan_strip(adapter, vf, false);
6f3dc319 6231
a15d9259 6232 return 0;
6f3dc319
GR		 6233}
6234
79aab093
MS		 6235static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
6236 u16 vlan, u8 qos, __be16 vlan_proto)
4ae196df 6237{
a15d9259 6238 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 6239
a15d9259
AD		 6240 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6241 return -EINVAL;
6f3dc319 6242
79aab093
MS		 6243 if (vlan_proto != htons(ETH_P_8021Q))
6244 return -EPROTONOSUPPORT;
6245
a15d9259
AD		 6246 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6247 igb_disable_port_vlan(adapter, vf);
6248}
6f3dc319 6249
a15d9259
AD		 6250static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6251{
6252 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6253 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
030f9f52 6254 int ret;
6f3dc319 6255
a15d9259
AD		 6256 if (adapter->vf_data[vf].pf_vlan)
6257 return -1;
6f3dc319 6258
a15d9259
AD		 6259 /* VLAN 0 is a special case, don't allow it to be removed */
6260 if (!vid && !add)
6261 return 0;
6262
030f9f52
CV		 6263 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
6264 if (!ret)
6265 igb_set_vf_vlan_strip(adapter, vf, !!vid);
6266 return ret;
4ae196df
AD		 6267}
6268
f2ca0dbe 6269static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6270{
a15d9259 6271 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df 6272
a15d9259
AD		 6273 /* clear flags - except flag that indicates PF has set the MAC */
6274 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6275 vf_data->last_nack = jiffies;
4ae196df
AD		 6276
6277 /* reset vlans for device */
6278 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6279 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6280 igb_set_vmvir(adapter, vf_data->pf_vlan |
6281 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6282 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
030f9f52 6283 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
4ae196df
AD		 6284
6285 /* reset multicast table array for vf */
6286 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6287
6288 /* Flush and reset the mta with the new values */
ff41f8dc 6289 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6290}
6291
f2ca0dbe
AD		 6292static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6293{
6294 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6295
5ac6f91d 6296 /* clear mac address as we were hotplug removed/added */
8151d294 6297 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6298 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6299
6300 /* process remaining reset events */
6301 igb_vf_reset(adapter, vf);
6302}
6303
6304static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6305{
6306 struct e1000_hw *hw = &adapter->hw;
6307 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6308 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6309 u32 reg, msgbuf[3];
6310 u8 *addr = (u8 *)(&msgbuf[1]);
6311
6312 /* process all the same items cleared in a function level reset */
f2ca0dbe 6313 igb_vf_reset(adapter, vf);
4ae196df
AD		 6314
6315 /* set vf mac address */
26ad9178 6316 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6317
6318 /* enable transmit and receive for vf */
6319 reg = rd32(E1000_VFTE);
a51d8c21 6320 wr32(E1000_VFTE, reg | BIT(vf));
4ae196df 6321 reg = rd32(E1000_VFRE);
a51d8c21 6322 wr32(E1000_VFRE, reg | BIT(vf));
4ae196df 6323
8fa7e0f7 6324 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6325
6326 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6327 if (!is_zero_ether_addr(vf_mac)) {
6328 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6329 memcpy(addr, vf_mac, ETH_ALEN);
6330 } else {
6331 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6332 }
4ae196df
AD		 6333 igb_write_mbx(hw, msgbuf, 3, vf);
6334}
6335
6336static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6337{
b980ac18 6338 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6339 * starting at the second 32 bit word of the msg array
6340 */
f2ca0dbe
AD		 6341 unsigned char *addr = (char *)&msg[1];
6342 int err = -1;
4ae196df 6343
f2ca0dbe
AD		 6344 if (is_valid_ether_addr(addr))
6345 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6346
f2ca0dbe 6347 return err;
4ae196df
AD		 6348}
6349
6350static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6351{
6352 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6353 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6354 u32 msg = E1000_VT_MSGTYPE_NACK;
6355
6356 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6357 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6358 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6359 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6360 vf_data->last_nack = jiffies;
4ae196df
AD		 6361 }
6362}
6363
f2ca0dbe 6364static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6365{
f2ca0dbe
AD		 6366 struct pci_dev *pdev = adapter->pdev;
6367 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6368 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6369 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6370 s32 retval;
6371
f2ca0dbe 6372 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6373
fef45f4c
AD		 6374 if (retval) {
6375 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6376 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6377 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6378 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6379 return;
6380 goto out;
6381 }
4ae196df
AD		 6382
6383 /* this is a message we already processed, do nothing */
6384 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6385 return;
4ae196df 6386
b980ac18 6387 /* until the vf completes a reset it should not be
4ae196df
AD		 6388 * allowed to start any configuration.
6389 */
4ae196df
AD		 6390 if (msgbuf[0] == E1000_VF_RESET) {
6391 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6392 return;
4ae196df
AD		 6393 }
6394
f2ca0dbe 6395 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6396 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6397 return;
6398 retval = -1;
6399 goto out;
4ae196df
AD		 6400 }
6401
6402 switch ((msgbuf[0] & 0xFFFF)) {
6403 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6404 retval = -EINVAL;
6405 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6406 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6407 else
6408 dev_warn(&pdev->dev,
b980ac18
JK		 6409 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6410 vf);
4ae196df 6411 break;
7d5753f0
AD		 6412 case E1000_VF_SET_PROMISC:
6413 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6414 break;
4ae196df
AD		 6415 case E1000_VF_SET_MULTICAST:
6416 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6417 break;
6418 case E1000_VF_SET_LPE:
6419 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6420 break;
6421 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6422 retval = -1;
6423 if (vf_data->pf_vlan)
6424 dev_warn(&pdev->dev,
b980ac18
JK		 6425 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6426 vf);
8151d294 6427 else
a15d9259 6428 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6429 break;
6430 default:
090b1795 6431 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6432 retval = -1;
6433 break;
6434 }
6435
fef45f4c
AD		 6436 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6437out:
4ae196df
AD		 6438 /* notify the VF of the results of what it sent us */
6439 if (retval)
6440 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6441 else
6442 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6443
4ae196df 6444 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6445}
4ae196df 6446
f2ca0dbe
AD		 6447static void igb_msg_task(struct igb_adapter *adapter)
6448{
6449 struct e1000_hw *hw = &adapter->hw;
6450 u32 vf;
6451
6452 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6453 /* process any reset requests */
6454 if (!igb_check_for_rst(hw, vf))
6455 igb_vf_reset_event(adapter, vf);
6456
6457 /* process any messages pending */
6458 if (!igb_check_for_msg(hw, vf))
6459 igb_rcv_msg_from_vf(adapter, vf);
6460
6461 /* process any acks */
6462 if (!igb_check_for_ack(hw, vf))
6463 igb_rcv_ack_from_vf(adapter, vf);
6464 }
4ae196df
AD		 6465}
6466
68d480c4
AD		 6467/**
6468 * igb_set_uta - Set unicast filter table address
6469 * @adapter: board private structure
bf456abb 6470 * @set: boolean indicating if we are setting or clearing bits
68d480c4
AD		 6471 *
6472 * The unicast table address is a register array of 32-bit registers.
6473 * The table is meant to be used in a way similar to how the MTA is used
6474 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6475 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6476 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4 6477 **/
bf456abb 6478static void igb_set_uta(struct igb_adapter *adapter, bool set)
68d480c4
AD		 6479{
6480 struct e1000_hw *hw = &adapter->hw;
bf456abb 6481 u32 uta = set ? ~0 : 0;
68d480c4
AD		 6482 int i;
6483
68d480c4
AD		 6484 /* we only need to do this if VMDq is enabled */
6485 if (!adapter->vfs_allocated_count)
6486 return;
6487
bf456abb
AD		 6488 for (i = hw->mac.uta_reg_count; i--;)
6489 array_wr32(E1000_UTA, i, uta);
68d480c4
AD		 6490}
6491
9d5c8243 6492/**
b980ac18
JK		 6493 * igb_intr_msi - Interrupt Handler
6494 * @irq: interrupt number
6495 * @data: pointer to a network interface device structure
9d5c8243
AK		 6496 **/
6497static irqreturn_t igb_intr_msi(int irq, void *data)
6498{
047e0030
AD		 6499 struct igb_adapter *adapter = data;
6500 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6501 struct e1000_hw *hw = &adapter->hw;
6502 /* read ICR disables interrupts using IAM */
6503 u32 icr = rd32(E1000_ICR);
6504
047e0030 6505 igb_write_itr(q_vector);
9d5c8243 6506
7f081d40
AD		 6507 if (icr & E1000_ICR_DRSTA)
6508 schedule_work(&adapter->reset_task);
6509
047e0030 6510 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6511 /* HW is reporting DMA is out of sync */
6512 adapter->stats.doosync++;
6513 }
6514
9d5c8243
AK		 6515 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6516 hw->mac.get_link_status = 1;
6517 if (!test_bit(__IGB_DOWN, &adapter->state))
6518 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6519 }
6520
61d7f75f
RC		 6521 if (icr & E1000_ICR_TS)
6522 igb_tsync_interrupt(adapter);
1f6e8178 6523
047e0030 6524 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6525
6526 return IRQ_HANDLED;
6527}
6528
6529/**
b980ac18
JK		 6530 * igb_intr - Legacy Interrupt Handler
6531 * @irq: interrupt number
6532 * @data: pointer to a network interface device structure
9d5c8243
AK		 6533 **/
6534static irqreturn_t igb_intr(int irq, void *data)
6535{
047e0030
AD		 6536 struct igb_adapter *adapter = data;
6537 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6538 struct e1000_hw *hw = &adapter->hw;
6539 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6540 * need for the IMC write
6541 */
9d5c8243 6542 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6543
6544 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6545 * not set, then the adapter didn't send an interrupt
6546 */
9d5c8243
AK		 6547 if (!(icr & E1000_ICR_INT_ASSERTED))
6548 return IRQ_NONE;
6549
0ba82994
AD		 6550 igb_write_itr(q_vector);
6551
7f081d40
AD		 6552 if (icr & E1000_ICR_DRSTA)
6553 schedule_work(&adapter->reset_task);
6554
047e0030 6555 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6556 /* HW is reporting DMA is out of sync */
6557 adapter->stats.doosync++;
6558 }
6559
9d5c8243
AK		 6560 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6561 hw->mac.get_link_status = 1;
6562 /* guard against interrupt when we're going down */
6563 if (!test_bit(__IGB_DOWN, &adapter->state))
6564 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6565 }
6566
61d7f75f
RC		 6567 if (icr & E1000_ICR_TS)
6568 igb_tsync_interrupt(adapter);
1f6e8178 6569
047e0030 6570 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6571
6572 return IRQ_HANDLED;
6573}
6574
c50b52a0 6575static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6576{
047e0030 6577 struct igb_adapter *adapter = q_vector->adapter;
46544258 6578 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6579
0ba82994
AD		 6580 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6581 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6582 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6583 igb_set_itr(q_vector);
46544258 6584 else
047e0030 6585 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6586 }
6587
46544258 6588 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6589 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6590 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6591 else
6592 igb_irq_enable(adapter);
6593 }
9d5c8243
AK		 6594}
6595
46544258 6596/**
b980ac18
JK		 6597 * igb_poll - NAPI Rx polling callback
6598 * @napi: napi polling structure
6599 * @budget: count of how many packets we should handle
46544258
AD		 6600 **/
6601static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6602{
047e0030 6603 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6604 struct igb_q_vector,
6605 napi);
16eb8815 6606 bool clean_complete = true;
32b3e08f 6607 int work_done = 0;
9d5c8243 6608
421e02f0 6609#ifdef CONFIG_IGB_DCA
047e0030
AD		 6610 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6611 igb_update_dca(q_vector);
fe4506b6 6612#endif
0ba82994 6613 if (q_vector->tx.ring)
7f0ba845 6614 clean_complete = igb_clean_tx_irq(q_vector, budget);
9d5c8243 6615
32b3e08f
JB		 6616 if (q_vector->rx.ring) {
6617 int cleaned = igb_clean_rx_irq(q_vector, budget);
6618
6619 work_done += cleaned;
7f0ba845
AD		 6620 if (cleaned >= budget)
6621 clean_complete = false;
32b3e08f 6622 }
047e0030 6623
16eb8815
AD		 6624 /* If all work not completed, return budget and keep polling */
6625 if (!clean_complete)
6626 return budget;
46544258 6627
9d5c8243 6628 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6629 napi_complete_done(napi, work_done);
16eb8815 6630 igb_ring_irq_enable(q_vector);
9d5c8243 6631
16eb8815 6632 return 0;
9d5c8243 6633}
6d8126f9 6634
9d5c8243 6635/**
b980ac18
JK		 6636 * igb_clean_tx_irq - Reclaim resources after transmit completes
6637 * @q_vector: pointer to q_vector containing needed info
7f0ba845 6638 * @napi_budget: Used to determine if we are in netpoll
49ce9c2c 6639 *
b980ac18 6640 * returns true if ring is completely cleaned
9d5c8243 6641 **/
7f0ba845 6642static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
9d5c8243 6643{
047e0030 6644 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6645 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6646 struct igb_tx_buffer *tx_buffer;
f4128785 6647 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6648 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6649 unsigned int budget = q_vector->tx.work_limit;
8542db05 6650 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6651
13fde97a
AD		 6652 if (test_bit(__IGB_DOWN, &adapter->state))
6653 return true;
0e014cb1 6654
06034649 6655 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6656 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6657 i -= tx_ring->count;
9d5c8243 6658
f4128785
AD		 6659 do {
6660 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6661
6662 /* if next_to_watch is not set then there is no work pending */
6663 if (!eop_desc)
6664 break;
13fde97a 6665
f4128785 6666 /* prevent any other reads prior to eop_desc */
70d289bc 6667 read_barrier_depends();
f4128785 6668
13fde97a
AD		 6669 /* if DD is not set pending work has not been completed */
6670 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6671 break;
6672
8542db05
AD		 6673 /* clear next_to_watch to prevent false hangs */
6674 tx_buffer->next_to_watch = NULL;
9d5c8243 6675
ebe42d16
AD		 6676 /* update the statistics for this packet */
6677 total_bytes += tx_buffer->bytecount;
6678 total_packets += tx_buffer->gso_segs;
13fde97a 6679
ebe42d16 6680 /* free the skb */
7f0ba845 6681 napi_consume_skb(tx_buffer->skb, napi_budget);
13fde97a 6682
ebe42d16
AD		 6683 /* unmap skb header data */
6684 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6685 dma_unmap_addr(tx_buffer, dma),
6686 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6687 DMA_TO_DEVICE);
6688
c9f14bf3
AD		 6689 /* clear tx_buffer data */
6690 tx_buffer->skb = NULL;
6691 dma_unmap_len_set(tx_buffer, len, 0);
6692
ebe42d16
AD		 6693 /* clear last DMA location and unmap remaining buffers */
6694 while (tx_desc != eop_desc) {
13fde97a
AD		 6695 tx_buffer++;
6696 tx_desc++;
9d5c8243 6697 i++;
8542db05
AD		 6698 if (unlikely(!i)) {
6699 i -= tx_ring->count;
06034649 6700 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6701 tx_desc = IGB_TX_DESC(tx_ring, 0);
6702 }
ebe42d16
AD		 6703
6704 /* unmap any remaining paged data */
c9f14bf3 6705 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6706 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6707 dma_unmap_addr(tx_buffer, dma),
6708 dma_unmap_len(tx_buffer, len),
ebe42d16 6709 DMA_TO_DEVICE);
c9f14bf3 6710 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6711 }
6712 }
6713
ebe42d16
AD		 6714 /* move us one more past the eop_desc for start of next pkt */
6715 tx_buffer++;
6716 tx_desc++;
6717 i++;
6718 if (unlikely(!i)) {
6719 i -= tx_ring->count;
6720 tx_buffer = tx_ring->tx_buffer_info;
6721 tx_desc = IGB_TX_DESC(tx_ring, 0);
6722 }
f4128785
AD		 6723
6724 /* issue prefetch for next Tx descriptor */
6725 prefetch(tx_desc);
6726
6727 /* update budget accounting */
6728 budget--;
6729 } while (likely(budget));
0e014cb1 6730
bdbc0631
ED		 6731 netdev_tx_completed_queue(txring_txq(tx_ring),
6732 total_packets, total_bytes);
8542db05 6733 i += tx_ring->count;
9d5c8243 6734 tx_ring->next_to_clean = i;
13fde97a
AD		 6735 u64_stats_update_begin(&tx_ring->tx_syncp);
6736 tx_ring->tx_stats.bytes += total_bytes;
6737 tx_ring->tx_stats.packets += total_packets;
6738 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6739 q_vector->tx.total_bytes += total_bytes;
6740 q_vector->tx.total_packets += total_packets;
9d5c8243 6741
6d095fa8 6742 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6743 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6744
9d5c8243 6745 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6746 * check with the clearing of time_stamp and movement of i
6747 */
6d095fa8 6748 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6749 if (tx_buffer->next_to_watch &&
8542db05 6750 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6751 (adapter->tx_timeout_factor * HZ)) &&
6752 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6753
9d5c8243 6754 /* detected Tx unit hang */
59d71989 6755 dev_err(tx_ring->dev,
9d5c8243 6756 "Detected Tx Unit Hang\n"
2d064c06 6757 " Tx Queue <%d>\n"
9d5c8243
AK		 6758 " TDH <%x>\n"
6759 " TDT <%x>\n"
6760 " next_to_use <%x>\n"
6761 " next_to_clean <%x>\n"
9d5c8243
AK		 6762 "buffer_info[next_to_clean]\n"
6763 " time_stamp <%lx>\n"
8542db05 6764 " next_to_watch <%p>\n"
9d5c8243
AK		 6765 " jiffies <%lx>\n"
6766 " desc.status <%x>\n",
2d064c06 6767 tx_ring->queue_index,
238ac817 6768 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6769 readl(tx_ring->tail),
9d5c8243
AK		 6770 tx_ring->next_to_use,
6771 tx_ring->next_to_clean,
8542db05 6772 tx_buffer->time_stamp,
f4128785 6773 tx_buffer->next_to_watch,
9d5c8243 6774 jiffies,
f4128785 6775 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6776 netif_stop_subqueue(tx_ring->netdev,
6777 tx_ring->queue_index);
6778
6779 /* we are about to reset, no point in enabling stuff */
6780 return true;
9d5c8243
AK		 6781 }
6782 }
13fde97a 6783
21ba6fe1 6784#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6785 if (unlikely(total_packets &&
b980ac18
JK		 6786 netif_carrier_ok(tx_ring->netdev) &&
6787 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6788 /* Make sure that anybody stopping the queue after this
6789 * sees the new next_to_clean.
6790 */
6791 smp_mb();
6792 if (__netif_subqueue_stopped(tx_ring->netdev,
6793 tx_ring->queue_index) &&
6794 !(test_bit(__IGB_DOWN, &adapter->state))) {
6795 netif_wake_subqueue(tx_ring->netdev,
6796 tx_ring->queue_index);
6797
6798 u64_stats_update_begin(&tx_ring->tx_syncp);
6799 tx_ring->tx_stats.restart_queue++;
6800 u64_stats_update_end(&tx_ring->tx_syncp);
6801 }
6802 }
6803
6804 return !!budget;
9d5c8243
AK		 6805}
6806
cbc8e55f 6807/**
b980ac18
JK		 6808 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6809 * @rx_ring: rx descriptor ring to store buffers on
6810 * @old_buff: donor buffer to have page reused
cbc8e55f 6811 *
b980ac18 6812 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6813 **/
6814static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6815 struct igb_rx_buffer *old_buff)
6816{
6817 struct igb_rx_buffer *new_buff;
6818 u16 nta = rx_ring->next_to_alloc;
6819
6820 new_buff = &rx_ring->rx_buffer_info[nta];
6821
6822 /* update, and store next to alloc */
6823 nta++;
6824 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6825
6826 /* transfer page from old buffer to new buffer */
a1f63473 6827 *new_buff = *old_buff;
cbc8e55f
AD		 6828}
6829
95dd44b4
AD		 6830static inline bool igb_page_is_reserved(struct page *page)
6831{
2f064f34 6832 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6833}
6834
74e238ea
AD		 6835static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6836 struct page *page,
6837 unsigned int truesize)
6838{
bd4171a5
AD		 6839 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias--;
6840
74e238ea 6841 /* avoid re-using remote pages */
95dd44b4 6842 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6843 return false;
6844
74e238ea
AD		 6845#if (PAGE_SIZE < 8192)
6846 /* if we are only owner of page we can reuse it */
bd4171a5 6847 if (unlikely(page_ref_count(page) != pagecnt_bias))
74e238ea
AD		 6848 return false;
6849
6850 /* flip page offset to other buffer */
6851 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6852#else
6853 /* move offset up to the next cache line */
6854 rx_buffer->page_offset += truesize;
6855
6856 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6857 return false;
74e238ea
AD		 6858#endif
6859
bd4171a5
AD		 6860 /* If we have drained the page fragment pool we need to update
6861 * the pagecnt_bias and page count so that we fully restock the
6862 * number of references the driver holds.
95dd44b4 6863 */
bd4171a5
AD		 6864 if (unlikely(pagecnt_bias == 1)) {
6865 page_ref_add(page, USHRT_MAX);
6866 rx_buffer->pagecnt_bias = USHRT_MAX;
6867 }
95dd44b4 6868
74e238ea
AD		 6869 return true;
6870}
6871
cbc8e55f 6872/**
b980ac18
JK		 6873 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6874 * @rx_ring: rx descriptor ring to transact packets on
6875 * @rx_buffer: buffer containing page to add
6876 * @rx_desc: descriptor containing length of buffer written by hardware
6877 * @skb: sk_buff to place the data into
cbc8e55f 6878 *
b980ac18
JK		 6879 * This function will add the data contained in rx_buffer->page to the skb.
6880 * This is done either through a direct copy if the data in the buffer is
6881 * less than the skb header size, otherwise it will just attach the page as
6882 * a frag to the skb.
cbc8e55f 6883 *
b980ac18
JK		 6884 * The function will then update the page offset if necessary and return
6885 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6886 **/
6887static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6888 struct igb_rx_buffer *rx_buffer,
64f2525c 6889 unsigned int size,
cbc8e55f
AD		 6890 union e1000_adv_rx_desc *rx_desc,
6891 struct sk_buff *skb)
6892{
6893 struct page *page = rx_buffer->page;
f56e7bba 6894 unsigned char *va = page_address(page) + rx_buffer->page_offset;
74e238ea
AD		 6895#if (PAGE_SIZE < 8192)
6896 unsigned int truesize = IGB_RX_BUFSZ;
6897#else
f56e7bba 6898 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6899#endif
f56e7bba 6900 unsigned int pull_len;
cbc8e55f 6901
f56e7bba
AD		 6902 if (unlikely(skb_is_nonlinear(skb)))
6903 goto add_tail_frag;
cbc8e55f 6904
f56e7bba
AD		 6905 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6906 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6907 va += IGB_TS_HDR_LEN;
6908 size -= IGB_TS_HDR_LEN;
6909 }
cbc8e55f 6910
f56e7bba 6911 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6912 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6913
95dd44b4
AD		 6914 /* page is not reserved, we can reuse buffer as-is */
6915 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6916 return true;
6917
6918 /* this page cannot be reused so discard it */
cbc8e55f
AD		 6919 return false;
6920 }
6921
f56e7bba
AD		 6922 /* we need the header to contain the greater of either ETH_HLEN or
6923 * 60 bytes if the skb->len is less than 60 for skb_pad.
6924 */
6925 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6926
6927 /* align pull length to size of long to optimize memcpy performance */
6928 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6929
6930 /* update all of the pointers */
6931 va += pull_len;
6932 size -= pull_len;
6933
6934add_tail_frag:
cbc8e55f 6935 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6936 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6937
74e238ea
AD		 6938 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6939}
cbc8e55f 6940
2e334eee
AD		 6941static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6942 union e1000_adv_rx_desc *rx_desc,
6943 struct sk_buff *skb)
6944{
64f2525c 6945 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
2e334eee
AD		 6946 struct igb_rx_buffer *rx_buffer;
6947 struct page *page;
6948
6949 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6950 page = rx_buffer->page;
6951 prefetchw(page);
6952
5be59554
AD		 6953 /* we are reusing so sync this buffer for CPU use */
6954 dma_sync_single_range_for_cpu(rx_ring->dev,
6955 rx_buffer->dma,
6956 rx_buffer->page_offset,
6957 size,
6958 DMA_FROM_DEVICE);
6959
2e334eee
AD		 6960 if (likely(!skb)) {
6961 void *page_addr = page_address(page) +
6962 rx_buffer->page_offset;
6963
6964 /* prefetch first cache line of first page */
6965 prefetch(page_addr);
6966#if L1_CACHE_BYTES < 128
6967 prefetch(page_addr + L1_CACHE_BYTES);
6968#endif
6969
6970 /* allocate a skb to store the frags */
67fd893e 6971 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6972 if (unlikely(!skb)) {
6973 rx_ring->rx_stats.alloc_failed++;
6974 return NULL;
6975 }
6976
b980ac18 6977 /* we will be copying header into skb->data in
2e334eee
AD		 6978 * pskb_may_pull so it is in our interest to prefetch
6979 * it now to avoid a possible cache miss
6980 */
6981 prefetchw(skb->data);
6982 }
6983
2e334eee 6984 /* pull page into skb */
64f2525c 6985 if (igb_add_rx_frag(rx_ring, rx_buffer, size, rx_desc, skb)) {
2e334eee
AD		 6986 /* hand second half of page back to the ring */
6987 igb_reuse_rx_page(rx_ring, rx_buffer);
6988 } else {
bd4171a5
AD		 6989 /* We are not reusing the buffer so unmap it and free
6990 * any references we are holding to it
6991 */
5be59554
AD		 6992 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
6993 PAGE_SIZE, DMA_FROM_DEVICE,
6994 DMA_ATTR_SKIP_CPU_SYNC);
2976db80 6995 __page_frag_cache_drain(page, rx_buffer->pagecnt_bias);
2e334eee
AD		 6996 }
6997
6998 /* clear contents of rx_buffer */
6999 rx_buffer->page = NULL;
7000
7001 return skb;
7002}
7003
cd392f5c 7004static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 7005 union e1000_adv_rx_desc *rx_desc,
7006 struct sk_buff *skb)
9d5c8243 7007{
bc8acf2c 7008 skb_checksum_none_assert(skb);
9d5c8243 7009
294e7d78 7010 /* Ignore Checksum bit is set */
3ceb90fd 7011 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 7012 return;
7013
7014 /* Rx checksum disabled via ethtool */
7015 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 7016 return;
85ad76b2 7017
9d5c8243 7018 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 7019 if (igb_test_staterr(rx_desc,
7020 E1000_RXDEXT_STATERR_TCPE |
7021 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 7022 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 7023 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
7024 * packets, (aka let the stack check the crc32c)
7025 */
866cff06
AD		 7026 if (!((skb->len == 60) &&
7027 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 7028 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 7029 ring->rx_stats.csum_err++;
12dcd86b
ED		 7030 u64_stats_update_end(&ring->rx_syncp);
7031 }
9d5c8243 7032 /* let the stack verify checksum errors */
9d5c8243
AK		 7033 return;
7034 }
7035 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 7036 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
7037 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 7038 skb->ip_summed = CHECKSUM_UNNECESSARY;
7039
3ceb90fd
AD		 7040 dev_dbg(ring->dev, "cksum success: bits %08X\n",
7041 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 7042}
7043
077887c3
AD		 7044static inline void igb_rx_hash(struct igb_ring *ring,
7045 union e1000_adv_rx_desc *rx_desc,
7046 struct sk_buff *skb)
7047{
7048 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 7049 skb_set_hash(skb,
7050 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
7051 PKT_HASH_TYPE_L3);
077887c3
AD		 7052}
7053
2e334eee 7054/**
b980ac18
JK		 7055 * igb_is_non_eop - process handling of non-EOP buffers
7056 * @rx_ring: Rx ring being processed
7057 * @rx_desc: Rx descriptor for current buffer
7058 * @skb: current socket buffer containing buffer in progress
2e334eee 7059 *
b980ac18
JK		 7060 * This function updates next to clean. If the buffer is an EOP buffer
7061 * this function exits returning false, otherwise it will place the
7062 * sk_buff in the next buffer to be chained and return true indicating
7063 * that this is in fact a non-EOP buffer.
2e334eee
AD		 7064 **/
7065static bool igb_is_non_eop(struct igb_ring *rx_ring,
7066 union e1000_adv_rx_desc *rx_desc)
7067{
7068 u32 ntc = rx_ring->next_to_clean + 1;
7069
7070 /* fetch, update, and store next to clean */
7071 ntc = (ntc < rx_ring->count) ? ntc : 0;
7072 rx_ring->next_to_clean = ntc;
7073
7074 prefetch(IGB_RX_DESC(rx_ring, ntc));
7075
7076 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
7077 return false;
7078
7079 return true;
7080}
7081
1a1c225b 7082/**
b980ac18
JK		 7083 * igb_cleanup_headers - Correct corrupted or empty headers
7084 * @rx_ring: rx descriptor ring packet is being transacted on
7085 * @rx_desc: pointer to the EOP Rx descriptor
7086 * @skb: pointer to current skb being fixed
1a1c225b 7087 *
b980ac18
JK		 7088 * Address the case where we are pulling data in on pages only
7089 * and as such no data is present in the skb header.
1a1c225b 7090 *
b980ac18
JK		 7091 * In addition if skb is not at least 60 bytes we need to pad it so that
7092 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 7093 *
b980ac18 7094 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 7095 **/
7096static bool igb_cleanup_headers(struct igb_ring *rx_ring,
7097 union e1000_adv_rx_desc *rx_desc,
7098 struct sk_buff *skb)
7099{
1a1c225b
AD		 7100 if (unlikely((igb_test_staterr(rx_desc,
7101 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
7102 struct net_device *netdev = rx_ring->netdev;
7103 if (!(netdev->features & NETIF_F_RXALL)) {
7104 dev_kfree_skb_any(skb);
7105 return true;
7106 }
7107 }
7108
a94d9e22
AD		 7109 /* if eth_skb_pad returns an error the skb was freed */
7110 if (eth_skb_pad(skb))
7111 return true;
1a1c225b
AD		 7112
7113 return false;
2d94d8ab
AD		 7114}
7115
db2ee5bd 7116/**
b980ac18
JK		 7117 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7118 * @rx_ring: rx descriptor ring packet is being transacted on
7119 * @rx_desc: pointer to the EOP Rx descriptor
7120 * @skb: pointer to current skb being populated
db2ee5bd 7121 *
b980ac18
JK		 7122 * This function checks the ring, descriptor, and packet information in
7123 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7124 * other fields within the skb.
db2ee5bd
AD		 7125 **/
7126static void igb_process_skb_fields(struct igb_ring *rx_ring,
7127 union e1000_adv_rx_desc *rx_desc,
7128 struct sk_buff *skb)
7129{
7130 struct net_device *dev = rx_ring->netdev;
7131
7132 igb_rx_hash(rx_ring, rx_desc, skb);
7133
7134 igb_rx_checksum(rx_ring, rx_desc, skb);
7135
5499a968
JK		 7136 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7137 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7138 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 7139
f646968f 7140 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 7141 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7142 u16 vid;
9005df38 7143
db2ee5bd
AD		 7144 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7145 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7146 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7147 else
7148 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7149
86a9bad3 7150 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7151 }
7152
7153 skb_record_rx_queue(skb, rx_ring->queue_index);
7154
7155 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7156}
7157
32b3e08f 7158static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7159{
0ba82994 7160 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7161 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7162 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7163 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7164
57ba34c9 7165 while (likely(total_packets < budget)) {
2e334eee 7166 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7167
2e334eee
AD		 7168 /* return some buffers to hardware, one at a time is too slow */
7169 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7170 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7171 cleaned_count = 0;
7172 }
bf36c1a0 7173
2e334eee 7174 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7175
124b74c1 7176 if (!rx_desc->wb.upper.status_error)
2e334eee 7177 break;
9d5c8243 7178
74e238ea
AD		 7179 /* This memory barrier is needed to keep us from reading
7180 * any other fields out of the rx_desc until we know the
124b74c1 7181 * descriptor has been written back
74e238ea 7182 */
124b74c1 7183 dma_rmb();
74e238ea 7184
2e334eee 7185 /* retrieve a buffer from the ring */
f9d40f6a 7186 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7187
2e334eee
AD		 7188 /* exit if we failed to retrieve a buffer */
7189 if (!skb)
7190 break;
1a1c225b 7191
2e334eee 7192 cleaned_count++;
1a1c225b 7193
2e334eee
AD		 7194 /* fetch next buffer in frame if non-eop */
7195 if (igb_is_non_eop(rx_ring, rx_desc))
7196 continue;
1a1c225b
AD		 7197
7198 /* verify the packet layout is correct */
7199 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7200 skb = NULL;
7201 continue;
9d5c8243 7202 }
9d5c8243 7203
db2ee5bd 7204 /* probably a little skewed due to removing CRC */
3ceb90fd 7205 total_bytes += skb->len;
3ceb90fd 7206
db2ee5bd
AD		 7207 /* populate checksum, timestamp, VLAN, and protocol */
7208 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7209
b2cb09b1 7210 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7211
1a1c225b
AD		 7212 /* reset skb pointer */
7213 skb = NULL;
7214
2e334eee
AD		 7215 /* update budget accounting */
7216 total_packets++;
57ba34c9 7217 }
bf36c1a0 7218
1a1c225b
AD		 7219 /* place incomplete frames back on ring for completion */
7220 rx_ring->skb = skb;
7221
12dcd86b 7222 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7223 rx_ring->rx_stats.packets += total_packets;
7224 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7225 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7226 q_vector->rx.total_packets += total_packets;
7227 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7228
7229 if (cleaned_count)
cd392f5c 7230 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7231
32b3e08f 7232 return total_packets;
9d5c8243
AK		 7233}
7234
c023cd88 7235static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7236 struct igb_rx_buffer *bi)
c023cd88
AD		 7237{
7238 struct page *page = bi->page;
cbc8e55f 7239 dma_addr_t dma;
c023cd88 7240
cbc8e55f
AD		 7241 /* since we are recycling buffers we should seldom need to alloc */
7242 if (likely(page))
c023cd88
AD		 7243 return true;
7244
cbc8e55f 7245 /* alloc new page for storage */
42b17f09 7246 page = dev_alloc_page();
cbc8e55f
AD		 7247 if (unlikely(!page)) {
7248 rx_ring->rx_stats.alloc_failed++;
7249 return false;
c023cd88
AD		 7250 }
7251
cbc8e55f 7252 /* map page for use */
5be59554
AD		 7253 dma = dma_map_page_attrs(rx_ring->dev, page, 0, PAGE_SIZE,
7254 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
c023cd88 7255
b980ac18 7256 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7257 * there isn't much point in holding memory we can't use
7258 */
1a1c225b 7259 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7260 __free_page(page);
7261
c023cd88
AD		 7262 rx_ring->rx_stats.alloc_failed++;
7263 return false;
7264 }
7265
1a1c225b 7266 bi->dma = dma;
cbc8e55f
AD		 7267 bi->page = page;
7268 bi->page_offset = 0;
bd4171a5 7269 bi->pagecnt_bias = 1;
1a1c225b 7270
c023cd88
AD		 7271 return true;
7272}
7273
9d5c8243 7274/**
b980ac18
JK		 7275 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7276 * @adapter: address of board private structure
9d5c8243 7277 **/
cd392f5c 7278void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7279{
9d5c8243 7280 union e1000_adv_rx_desc *rx_desc;
06034649 7281 struct igb_rx_buffer *bi;
c023cd88 7282 u16 i = rx_ring->next_to_use;
9d5c8243 7283
cbc8e55f
AD		 7284 /* nothing to do */
7285 if (!cleaned_count)
7286 return;
7287
60136906 7288 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7289 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7290 i -= rx_ring->count;
9d5c8243 7291
cbc8e55f 7292 do {
1a1c225b 7293 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7294 break;
9d5c8243 7295
5be59554
AD		 7296 /* sync the buffer for use by the device */
7297 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
7298 bi->page_offset,
7299 IGB_RX_BUFSZ,
7300 DMA_FROM_DEVICE);
7301
b980ac18 7302 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7303 * because each write-back erases this info.
7304 */
f9d40f6a 7305 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7306
c023cd88
AD		 7307 rx_desc++;
7308 bi++;
9d5c8243 7309 i++;
c023cd88 7310 if (unlikely(!i)) {
60136906 7311 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7312 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7313 i -= rx_ring->count;
7314 }
7315
95dd44b4
AD		 7316 /* clear the status bits for the next_to_use descriptor */
7317 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7318
7319 cleaned_count--;
7320 } while (cleaned_count);
9d5c8243 7321
c023cd88
AD		 7322 i += rx_ring->count;
7323
9d5c8243 7324 if (rx_ring->next_to_use != i) {
cbc8e55f 7325 /* record the next descriptor to use */
9d5c8243 7326 rx_ring->next_to_use = i;
9d5c8243 7327
cbc8e55f
AD		 7328 /* update next to alloc since we have filled the ring */
7329 rx_ring->next_to_alloc = i;
7330
b980ac18 7331 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7332 * know there are new descriptors to fetch. (Only
7333 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7334 * such as IA-64).
7335 */
9d5c8243 7336 wmb();
fce99e34 7337 writel(i, rx_ring->tail);
9d5c8243
AK		 7338 }
7339}
7340
7341/**
7342 * igb_mii_ioctl -
7343 * @netdev:
7344 * @ifreq:
7345 * @cmd:
7346 **/
7347static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7348{
7349 struct igb_adapter *adapter = netdev_priv(netdev);
7350 struct mii_ioctl_data *data = if_mii(ifr);
7351
7352 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7353 return -EOPNOTSUPP;
7354
7355 switch (cmd) {
7356 case SIOCGMIIPHY:
7357 data->phy_id = adapter->hw.phy.addr;
7358 break;
7359 case SIOCGMIIREG:
f5f4cf08 7360 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7361 &data->val_out))
9d5c8243
AK		 7362 return -EIO;
7363 break;
7364 case SIOCSMIIREG:
7365 default:
7366 return -EOPNOTSUPP;
7367 }
7368 return 0;
7369}
7370
7371/**
7372 * igb_ioctl -
7373 * @netdev:
7374 * @ifreq:
7375 * @cmd:
7376 **/
7377static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7378{
7379 switch (cmd) {
7380 case SIOCGMIIPHY:
7381 case SIOCGMIIREG:
7382 case SIOCSMIIREG:
7383 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7384 case SIOCGHWTSTAMP:
7385 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7386 case SIOCSHWTSTAMP:
6ab5f7b2 7387 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7388 default:
7389 return -EOPNOTSUPP;
7390 }
7391}
7392
94826487
TF		 7393void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7394{
7395 struct igb_adapter *adapter = hw->back;
7396
7397 pci_read_config_word(adapter->pdev, reg, value);
7398}
7399
7400void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7401{
7402 struct igb_adapter *adapter = hw->back;
7403
7404 pci_write_config_word(adapter->pdev, reg, *value);
7405}
7406
009bc06e
AD		 7407s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7408{
7409 struct igb_adapter *adapter = hw->back;
009bc06e 7410
23d028cc 7411 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7412 return -E1000_ERR_CONFIG;
7413
009bc06e
AD		 7414 return 0;
7415}
7416
7417s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7418{
7419 struct igb_adapter *adapter = hw->back;
009bc06e 7420
23d028cc 7421 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7422 return -E1000_ERR_CONFIG;
7423
009bc06e
AD		 7424 return 0;
7425}
7426
c8f44aff 7427static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7428{
7429 struct igb_adapter *adapter = netdev_priv(netdev);
7430 struct e1000_hw *hw = &adapter->hw;
7431 u32 ctrl, rctl;
f646968f 7432 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7433
5faf030c 7434 if (enable) {
9d5c8243
AK		 7435 /* enable VLAN tag insert/strip */
7436 ctrl = rd32(E1000_CTRL);
7437 ctrl |= E1000_CTRL_VME;
7438 wr32(E1000_CTRL, ctrl);
7439
51466239 7440 /* Disable CFI check */
9d5c8243 7441 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7442 rctl &= ~E1000_RCTL_CFIEN;
7443 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7444 } else {
7445 /* disable VLAN tag insert/strip */
7446 ctrl = rd32(E1000_CTRL);
7447 ctrl &= ~E1000_CTRL_VME;
7448 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7449 }
7450
030f9f52 7451 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9d5c8243
AK		 7452}
7453
80d5c368
PM		 7454static int igb_vlan_rx_add_vid(struct net_device *netdev,
7455 __be16 proto, u16 vid)
9d5c8243
AK		 7456{
7457 struct igb_adapter *adapter = netdev_priv(netdev);
7458 struct e1000_hw *hw = &adapter->hw;
4ae196df 7459 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7460
51466239 7461 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7462 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7463 igb_vfta_set(hw, vid, pf_id, true, !!vid);
b2cb09b1
JP		 7464
7465 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7466
7467 return 0;
9d5c8243
AK		 7468}
7469
80d5c368
PM		 7470static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7471 __be16 proto, u16 vid)
9d5c8243
AK		 7472{
7473 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7474 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7475 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7476
8b77c6b2 7477 /* remove VID from filter table */
16903caa
AD		 7478 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7479 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7480
7481 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7482
7483 return 0;
9d5c8243
AK		 7484}
7485
7486static void igb_restore_vlan(struct igb_adapter *adapter)
7487{
5982a556 7488 u16 vid = 1;
9d5c8243 7489
5faf030c 7490 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7491 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7492
5982a556 7493 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7494 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7495}
7496
14ad2513 7497int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7498{
090b1795 7499 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7500 struct e1000_mac_info *mac = &adapter->hw.mac;
7501
7502 mac->autoneg = 0;
7503
14ad2513 7504 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7505 * for the switch() below to work
7506 */
14ad2513
DD		 7507 if ((spd & 1) || (dplx & ~1))
7508 goto err_inval;
7509
f502ef7d
AA		 7510 /* Fiber NIC's only allow 1000 gbps Full duplex
7511 * and 100Mbps Full duplex for 100baseFx sfp
7512 */
7513 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7514 switch (spd + dplx) {
7515 case SPEED_10 + DUPLEX_HALF:
7516 case SPEED_10 + DUPLEX_FULL:
7517 case SPEED_100 + DUPLEX_HALF:
7518 goto err_inval;
7519 default:
7520 break;
7521 }
7522 }
cd2638a8 7523
14ad2513 7524 switch (spd + dplx) {
9d5c8243
AK		 7525 case SPEED_10 + DUPLEX_HALF:
7526 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7527 break;
7528 case SPEED_10 + DUPLEX_FULL:
7529 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7530 break;
7531 case SPEED_100 + DUPLEX_HALF:
7532 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7533 break;
7534 case SPEED_100 + DUPLEX_FULL:
7535 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7536 break;
7537 case SPEED_1000 + DUPLEX_FULL:
7538 mac->autoneg = 1;
7539 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7540 break;
7541 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7542 default:
14ad2513 7543 goto err_inval;
9d5c8243 7544 }
8376dad0
JB		 7545
7546 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7547 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7548
9d5c8243 7549 return 0;
14ad2513
DD		 7550
7551err_inval:
7552 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7553 return -EINVAL;
9d5c8243
AK		 7554}
7555
749ab2cd
YZ		 7556static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7557 bool runtime)
9d5c8243
AK		 7558{
7559 struct net_device *netdev = pci_get_drvdata(pdev);
7560 struct igb_adapter *adapter = netdev_priv(netdev);
7561 struct e1000_hw *hw = &adapter->hw;
2d064c06 7562 u32 ctrl, rctl, status;
749ab2cd 7563 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7564#ifdef CONFIG_PM
7565 int retval = 0;
7566#endif
7567
7568 netif_device_detach(netdev);
7569
a88f10ec 7570 if (netif_running(netdev))
749ab2cd 7571 __igb_close(netdev, true);
a88f10ec 7572
8646f7b4
JK		 7573 igb_ptp_suspend(adapter);
7574
047e0030 7575 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7576
7577#ifdef CONFIG_PM
7578 retval = pci_save_state(pdev);
7579 if (retval)
7580 return retval;
7581#endif
7582
7583 status = rd32(E1000_STATUS);
7584 if (status & E1000_STATUS_LU)
7585 wufc &= ~E1000_WUFC_LNKC;
7586
7587 if (wufc) {
7588 igb_setup_rctl(adapter);
ff41f8dc 7589 igb_set_rx_mode(netdev);
9d5c8243
AK		 7590
7591 /* turn on all-multi mode if wake on multicast is enabled */
7592 if (wufc & E1000_WUFC_MC) {
7593 rctl = rd32(E1000_RCTL);
7594 rctl |= E1000_RCTL_MPE;
7595 wr32(E1000_RCTL, rctl);
7596 }
7597
7598 ctrl = rd32(E1000_CTRL);
7599 /* advertise wake from D3Cold */
7600 #define E1000_CTRL_ADVD3WUC 0x00100000
7601 /* phy power management enable */
7602 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7603 ctrl |= E1000_CTRL_ADVD3WUC;
7604 wr32(E1000_CTRL, ctrl);
7605
9d5c8243 7606 /* Allow time for pending master requests to run */
330a6d6a 7607 igb_disable_pcie_master(hw);
9d5c8243
AK		 7608
7609 wr32(E1000_WUC, E1000_WUC_PME_EN);
7610 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7611 } else {
7612 wr32(E1000_WUC, 0);
7613 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7614 }
7615
3fe7c4c9
RW		 7616 *enable_wake = wufc || adapter->en_mng_pt;
7617 if (!*enable_wake)
88a268c1
NN		 7618 igb_power_down_link(adapter);
7619 else
7620 igb_power_up_link(adapter);
9d5c8243
AK		 7621
7622 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7623 * would have already happened in close and is redundant.
7624 */
9d5c8243
AK		 7625 igb_release_hw_control(adapter);
7626
7627 pci_disable_device(pdev);
7628
9d5c8243
AK		 7629 return 0;
7630}
7631
7632#ifdef CONFIG_PM
d9dd966d 7633#ifdef CONFIG_PM_SLEEP
749ab2cd 7634static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7635{
7636 int retval;
7637 bool wake;
749ab2cd 7638 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7639
749ab2cd 7640 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7641 if (retval)
7642 return retval;
7643
7644 if (wake) {
7645 pci_prepare_to_sleep(pdev);
7646 } else {
7647 pci_wake_from_d3(pdev, false);
7648 pci_set_power_state(pdev, PCI_D3hot);
7649 }
7650
7651 return 0;
7652}
d9dd966d 7653#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7654
749ab2cd 7655static int igb_resume(struct device *dev)
9d5c8243 7656{
749ab2cd 7657 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7658 struct net_device *netdev = pci_get_drvdata(pdev);
7659 struct igb_adapter *adapter = netdev_priv(netdev);
7660 struct e1000_hw *hw = &adapter->hw;
7661 u32 err;
7662
7663 pci_set_power_state(pdev, PCI_D0);
7664 pci_restore_state(pdev);
b94f2d77 7665 pci_save_state(pdev);
42bfd33a 7666
17a402a0
CW		 7667 if (!pci_device_is_present(pdev))
7668 return -ENODEV;
aed5dec3 7669 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7670 if (err) {
7671 dev_err(&pdev->dev,
7672 "igb: Cannot enable PCI device from suspend\n");
7673 return err;
7674 }
7675 pci_set_master(pdev);
7676
7677 pci_enable_wake(pdev, PCI_D3hot, 0);
7678 pci_enable_wake(pdev, PCI_D3cold, 0);
7679
53c7d064 7680 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7681 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7682 return -ENOMEM;
9d5c8243
AK		 7683 }
7684
9d5c8243 7685 igb_reset(adapter);
a8564f03
AD		 7686
7687 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7688 * driver.
7689 */
a8564f03
AD		 7690 igb_get_hw_control(adapter);
7691
9d5c8243
AK		 7692 wr32(E1000_WUS, ~0);
7693
749ab2cd 7694 if (netdev->flags & IFF_UP) {
0c2cc02e 7695 rtnl_lock();
749ab2cd 7696 err = __igb_open(netdev, true);
0c2cc02e 7697 rtnl_unlock();
a88f10ec
AD		 7698 if (err)
7699 return err;
7700 }
9d5c8243
AK		 7701
7702 netif_device_attach(netdev);
749ab2cd
YZ		 7703 return 0;
7704}
7705
749ab2cd
YZ		 7706static int igb_runtime_idle(struct device *dev)
7707{
7708 struct pci_dev *pdev = to_pci_dev(dev);
7709 struct net_device *netdev = pci_get_drvdata(pdev);
7710 struct igb_adapter *adapter = netdev_priv(netdev);
7711
7712 if (!igb_has_link(adapter))
7713 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7714
7715 return -EBUSY;
7716}
7717
7718static int igb_runtime_suspend(struct device *dev)
7719{
7720 struct pci_dev *pdev = to_pci_dev(dev);
7721 int retval;
7722 bool wake;
7723
7724 retval = __igb_shutdown(pdev, &wake, 1);
7725 if (retval)
7726 return retval;
7727
7728 if (wake) {
7729 pci_prepare_to_sleep(pdev);
7730 } else {
7731 pci_wake_from_d3(pdev, false);
7732 pci_set_power_state(pdev, PCI_D3hot);
7733 }
9d5c8243 7734
9d5c8243
AK		 7735 return 0;
7736}
749ab2cd
YZ		 7737
7738static int igb_runtime_resume(struct device *dev)
7739{
7740 return igb_resume(dev);
7741}
d61c81cb 7742#endif /* CONFIG_PM */
9d5c8243
AK		 7743
7744static void igb_shutdown(struct pci_dev *pdev)
7745{
3fe7c4c9
RW		 7746 bool wake;
7747
749ab2cd 7748 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7749
7750 if (system_state == SYSTEM_POWER_OFF) {
7751 pci_wake_from_d3(pdev, wake);
7752 pci_set_power_state(pdev, PCI_D3hot);
7753 }
9d5c8243
AK		 7754}
7755
fa44f2f1
GR		 7756#ifdef CONFIG_PCI_IOV
7757static int igb_sriov_reinit(struct pci_dev *dev)
7758{
7759 struct net_device *netdev = pci_get_drvdata(dev);
7760 struct igb_adapter *adapter = netdev_priv(netdev);
7761 struct pci_dev *pdev = adapter->pdev;
7762
7763 rtnl_lock();
7764
7765 if (netif_running(netdev))
7766 igb_close(netdev);
76252723
SA		 7767 else
7768 igb_reset(adapter);
fa44f2f1
GR		 7769
7770 igb_clear_interrupt_scheme(adapter);
7771
7772 igb_init_queue_configuration(adapter);
7773
7774 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7775 rtnl_unlock();
fa44f2f1
GR		 7776 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7777 return -ENOMEM;
7778 }
7779
7780 if (netif_running(netdev))
7781 igb_open(netdev);
7782
7783 rtnl_unlock();
7784
7785 return 0;
7786}
7787
7788static int igb_pci_disable_sriov(struct pci_dev *dev)
7789{
7790 int err = igb_disable_sriov(dev);
7791
7792 if (!err)
7793 err = igb_sriov_reinit(dev);
7794
7795 return err;
7796}
7797
7798static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7799{
7800 int err = igb_enable_sriov(dev, num_vfs);
7801
7802 if (err)
7803 goto out;
7804
7805 err = igb_sriov_reinit(dev);
7806 if (!err)
7807 return num_vfs;
7808
7809out:
7810 return err;
7811}
7812
7813#endif
7814static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7815{
7816#ifdef CONFIG_PCI_IOV
7817 if (num_vfs == 0)
7818 return igb_pci_disable_sriov(dev);
7819 else
7820 return igb_pci_enable_sriov(dev, num_vfs);
7821#endif
7822 return 0;
7823}
7824
9d5c8243 7825#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7826/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7827 * without having to re-enable interrupts. It's not called while
7828 * the interrupt routine is executing.
7829 */
7830static void igb_netpoll(struct net_device *netdev)
7831{
7832 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7833 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7834 struct igb_q_vector *q_vector;
9d5c8243 7835 int i;
9d5c8243 7836
047e0030 7837 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7838 q_vector = adapter->q_vector[i];
cd14ef54 7839 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7840 wr32(E1000_EIMC, q_vector->eims_value);
7841 else
7842 igb_irq_disable(adapter);
047e0030 7843 napi_schedule(&q_vector->napi);
eebbbdba 7844 }
9d5c8243
AK		 7845}
7846#endif /* CONFIG_NET_POLL_CONTROLLER */
7847
7848/**
b980ac18
JK		 7849 * igb_io_error_detected - called when PCI error is detected
7850 * @pdev: Pointer to PCI device
7851 * @state: The current pci connection state
9d5c8243 7852 *
b980ac18
JK		 7853 * This function is called after a PCI bus error affecting
7854 * this device has been detected.
7855 **/
9d5c8243
AK		 7856static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7857 pci_channel_state_t state)
7858{
7859 struct net_device *netdev = pci_get_drvdata(pdev);
7860 struct igb_adapter *adapter = netdev_priv(netdev);
7861
7862 netif_device_detach(netdev);
7863
59ed6eec
AD		 7864 if (state == pci_channel_io_perm_failure)
7865 return PCI_ERS_RESULT_DISCONNECT;
7866
9d5c8243
AK		 7867 if (netif_running(netdev))
7868 igb_down(adapter);
7869 pci_disable_device(pdev);
7870
7871 /* Request a slot slot reset. */
7872 return PCI_ERS_RESULT_NEED_RESET;
7873}
7874
7875/**
b980ac18
JK		 7876 * igb_io_slot_reset - called after the pci bus has been reset.
7877 * @pdev: Pointer to PCI device
9d5c8243 7878 *
b980ac18
JK		 7879 * Restart the card from scratch, as if from a cold-boot. Implementation
7880 * resembles the first-half of the igb_resume routine.
7881 **/
9d5c8243
AK		 7882static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7883{
7884 struct net_device *netdev = pci_get_drvdata(pdev);
7885 struct igb_adapter *adapter = netdev_priv(netdev);
7886 struct e1000_hw *hw = &adapter->hw;
40a914fa 7887 pci_ers_result_t result;
42bfd33a 7888 int err;
9d5c8243 7889
aed5dec3 7890 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7891 dev_err(&pdev->dev,
7892 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7893 result = PCI_ERS_RESULT_DISCONNECT;
7894 } else {
7895 pci_set_master(pdev);
7896 pci_restore_state(pdev);
b94f2d77 7897 pci_save_state(pdev);
9d5c8243 7898
40a914fa
AD		 7899 pci_enable_wake(pdev, PCI_D3hot, 0);
7900 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7901
40a914fa
AD		 7902 igb_reset(adapter);
7903 wr32(E1000_WUS, ~0);
7904 result = PCI_ERS_RESULT_RECOVERED;
7905 }
9d5c8243 7906
ea943d41
JK		 7907 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7908 if (err) {
b980ac18
JK		 7909 dev_err(&pdev->dev,
7910 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7911 err);
ea943d41
JK		 7912 /* non-fatal, continue */
7913 }
40a914fa
AD		 7914
7915 return result;
9d5c8243
AK		 7916}
7917
7918/**
b980ac18
JK		 7919 * igb_io_resume - called when traffic can start flowing again.
7920 * @pdev: Pointer to PCI device
9d5c8243 7921 *
b980ac18
JK		 7922 * This callback is called when the error recovery driver tells us that
7923 * its OK to resume normal operation. Implementation resembles the
7924 * second-half of the igb_resume routine.
9d5c8243
AK		 7925 */
7926static void igb_io_resume(struct pci_dev *pdev)
7927{
7928 struct net_device *netdev = pci_get_drvdata(pdev);
7929 struct igb_adapter *adapter = netdev_priv(netdev);
7930
9d5c8243
AK		 7931 if (netif_running(netdev)) {
7932 if (igb_up(adapter)) {
7933 dev_err(&pdev->dev, "igb_up failed after reset\n");
7934 return;
7935 }
7936 }
7937
7938 netif_device_attach(netdev);
7939
7940 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7941 * driver.
7942 */
9d5c8243 7943 igb_get_hw_control(adapter);
9d5c8243
AK		 7944}
7945
26ad9178 7946static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7947 u8 qsel)
26ad9178 7948{
26ad9178 7949 struct e1000_hw *hw = &adapter->hw;
c3278587 7950 u32 rar_low, rar_high;
26ad9178 7951
415cd2a6
AD		 7952 /* HW expects these to be in network order when they are plugged
7953 * into the registers which are little endian. In order to guarantee
7954 * that ordering we need to do an leXX_to_cpup here in order to be
7955 * ready for the byteswap that occurs with writel
26ad9178 7956 */
415cd2a6
AD		 7957 rar_low = le32_to_cpup((__le32 *)(addr));
7958 rar_high = le16_to_cpup((__le16 *)(addr + 4));
26ad9178
AD		 7959
7960 /* Indicate to hardware the Address is Valid. */
7961 rar_high |= E1000_RAH_AV;
7962
7963 if (hw->mac.type == e1000_82575)
7964 rar_high |= E1000_RAH_POOL_1 * qsel;
7965 else
7966 rar_high |= E1000_RAH_POOL_1 << qsel;
7967
7968 wr32(E1000_RAL(index), rar_low);
7969 wrfl();
7970 wr32(E1000_RAH(index), rar_high);
7971 wrfl();
7972}
7973
4ae196df 7974static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7975 int vf, unsigned char *mac_addr)
4ae196df
AD		 7976{
7977 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7978 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7979 * towards the first, as a result a collision should not be possible
7980 */
ff41f8dc 7981 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7982
37680117 7983 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7984
26ad9178 7985 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7986
7987 return 0;
7988}
7989
8151d294
WM		 7990static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7991{
7992 struct igb_adapter *adapter = netdev_priv(netdev);
7993 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7994 return -EINVAL;
7995 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7996 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7997 dev_info(&adapter->pdev->dev,
7998 "Reload the VF driver to make this change effective.");
8151d294 7999 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 8000 dev_warn(&adapter->pdev->dev,
8001 "The VF MAC address has been set, but the PF device is not up.\n");
8002 dev_warn(&adapter->pdev->dev,
8003 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 8004 }
8005 return igb_set_vf_mac(adapter, vf, mac);
8006}
8007
17dc566c
LL		 8008static int igb_link_mbps(int internal_link_speed)
8009{
8010 switch (internal_link_speed) {
8011 case SPEED_100:
8012 return 100;
8013 case SPEED_1000:
8014 return 1000;
8015 default:
8016 return 0;
8017 }
8018}
8019
8020static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
8021 int link_speed)
8022{
8023 int rf_dec, rf_int;
8024 u32 bcnrc_val;
8025
8026 if (tx_rate != 0) {
8027 /* Calculate the rate factor values to set */
8028 rf_int = link_speed / tx_rate;
8029 rf_dec = (link_speed - (rf_int * tx_rate));
a51d8c21 8030 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
b980ac18 8031 tx_rate;
17dc566c
LL		 8032
8033 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 8034 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
8035 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 8036 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
8037 } else {
8038 bcnrc_val = 0;
8039 }
8040
8041 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 8042 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 8043 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
8044 */
8045 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 8046 wr32(E1000_RTTBCNRC, bcnrc_val);
8047}
8048
8049static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
8050{
8051 int actual_link_speed, i;
8052 bool reset_rate = false;
8053
8054 /* VF TX rate limit was not set or not supported */
8055 if ((adapter->vf_rate_link_speed == 0) ||
8056 (adapter->hw.mac.type != e1000_82576))
8057 return;
8058
8059 actual_link_speed = igb_link_mbps(adapter->link_speed);
8060 if (actual_link_speed != adapter->vf_rate_link_speed) {
8061 reset_rate = true;
8062 adapter->vf_rate_link_speed = 0;
8063 dev_info(&adapter->pdev->dev,
b980ac18 8064 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 8065 }
8066
8067 for (i = 0; i < adapter->vfs_allocated_count; i++) {
8068 if (reset_rate)
8069 adapter->vf_data[i].tx_rate = 0;
8070
8071 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 8072 adapter->vf_data[i].tx_rate,
8073 actual_link_speed);
17dc566c
LL		 8074 }
8075}
8076
ed616689
SC		 8077static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
8078 int min_tx_rate, int max_tx_rate)
8151d294 8079{
17dc566c
LL		 8080 struct igb_adapter *adapter = netdev_priv(netdev);
8081 struct e1000_hw *hw = &adapter->hw;
8082 int actual_link_speed;
8083
8084 if (hw->mac.type != e1000_82576)
8085 return -EOPNOTSUPP;
8086
ed616689
SC		 8087 if (min_tx_rate)
8088 return -EINVAL;
8089
17dc566c
LL		 8090 actual_link_speed = igb_link_mbps(adapter->link_speed);
8091 if ((vf >= adapter->vfs_allocated_count) ||
8092 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 8093 (max_tx_rate < 0) ||
8094 (max_tx_rate > actual_link_speed))
17dc566c
LL		 8095 return -EINVAL;
8096
8097 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 8098 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
8099 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 8100
8101 return 0;
8151d294
WM		 8102}
8103
70ea4783
LL		 8104static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8105 bool setting)
8106{
8107 struct igb_adapter *adapter = netdev_priv(netdev);
8108 struct e1000_hw *hw = &adapter->hw;
8109 u32 reg_val, reg_offset;
8110
8111 if (!adapter->vfs_allocated_count)
8112 return -EOPNOTSUPP;
8113
8114 if (vf >= adapter->vfs_allocated_count)
8115 return -EINVAL;
8116
8117 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8118 reg_val = rd32(reg_offset);
8119 if (setting)
a51d8c21
JK		 8120 reg_val |= (BIT(vf) |
8121 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
70ea4783 8122 else
a51d8c21
JK		 8123 reg_val &= ~(BIT(vf) |
8124 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
70ea4783
LL		 8125 wr32(reg_offset, reg_val);
8126
8127 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 8128 return 0;
70ea4783
LL		 8129}
8130
8151d294
WM		 8131static int igb_ndo_get_vf_config(struct net_device *netdev,
8132 int vf, struct ifla_vf_info *ivi)
8133{
8134 struct igb_adapter *adapter = netdev_priv(netdev);
8135 if (vf >= adapter->vfs_allocated_count)
8136 return -EINVAL;
8137 ivi->vf = vf;
8138 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 8139 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8140 ivi->min_tx_rate = 0;
8151d294
WM		 8141 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8142 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 8143 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 8144 return 0;
8145}
8146
4ae196df
AD		 8147static void igb_vmm_control(struct igb_adapter *adapter)
8148{
8149 struct e1000_hw *hw = &adapter->hw;
10d8e907 8150 u32 reg;
4ae196df 8151
52a1dd4d
AD		 8152 switch (hw->mac.type) {
8153 case e1000_82575:
f96a8a0b
CW		 8154 case e1000_i210:
8155 case e1000_i211:
ceb5f13b 8156 case e1000_i354:
52a1dd4d
AD		 8157 default:
8158 /* replication is not supported for 82575 */
4ae196df 8159 return;
52a1dd4d
AD		 8160 case e1000_82576:
8161 /* notify HW that the MAC is adding vlan tags */
8162 reg = rd32(E1000_DTXCTL);
8163 reg |= E1000_DTXCTL_VLAN_ADDED;
8164 wr32(E1000_DTXCTL, reg);
b26141d4 8165 /* Fall through */
52a1dd4d
AD		 8166 case e1000_82580:
8167 /* enable replication vlan tag stripping */
8168 reg = rd32(E1000_RPLOLR);
8169 reg |= E1000_RPLOLR_STRVLAN;
8170 wr32(E1000_RPLOLR, reg);
b26141d4 8171 /* Fall through */
d2ba2ed8
AD		 8172 case e1000_i350:
8173 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8174 break;
8175 }
10d8e907 8176
d4960307
AD		 8177 if (adapter->vfs_allocated_count) {
8178 igb_vmdq_set_loopback_pf(hw, true);
8179 igb_vmdq_set_replication_pf(hw, true);
13800469 8180 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8181 adapter->vfs_allocated_count);
d4960307
AD		 8182 } else {
8183 igb_vmdq_set_loopback_pf(hw, false);
8184 igb_vmdq_set_replication_pf(hw, false);
8185 }
4ae196df
AD		 8186}
8187
b6e0c419
CW		 8188static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8189{
8190 struct e1000_hw *hw = &adapter->hw;
8191 u32 dmac_thr;
8192 u16 hwm;
8193
8194 if (hw->mac.type > e1000_82580) {
8195 if (adapter->flags & IGB_FLAG_DMAC) {
8196 u32 reg;
8197
8198 /* force threshold to 0. */
8199 wr32(E1000_DMCTXTH, 0);
8200
b980ac18 8201 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8202 * than the Rx threshold. Set hwm to PBA - max frame
8203 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8204 */
45693bcb 8205 hwm = 64 * (pba - 6);
e8c626e9
MV		 8206 reg = rd32(E1000_FCRTC);
8207 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8208 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8209 & E1000_FCRTC_RTH_COAL_MASK);
8210 wr32(E1000_FCRTC, reg);
8211
b980ac18 8212 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8213 * frame size, capping it at PBA - 10KB.
8214 */
45693bcb 8215 dmac_thr = pba - 10;
b6e0c419
CW		 8216 reg = rd32(E1000_DMACR);
8217 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8218 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8219 & E1000_DMACR_DMACTHR_MASK);
8220
8221 /* transition to L0x or L1 if available..*/
8222 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8223
8224 /* watchdog timer= +-1000 usec in 32usec intervals */
8225 reg |= (1000 >> 5);
0c02dd98
MV		 8226
8227 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8228 if (hw->mac.type != e1000_i354)
8229 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8230
b6e0c419
CW		 8231 wr32(E1000_DMACR, reg);
8232
b980ac18 8233 /* no lower threshold to disable
b6e0c419
CW		 8234 * coalescing(smart fifb)-UTRESH=0
8235 */
8236 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8237
8238 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8239
8240 wr32(E1000_DMCTLX, reg);
8241
b980ac18 8242 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8243 * DMA coal
8244 */
8245 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8246 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8247
b980ac18 8248 /* make low power state decision controlled
b6e0c419
CW		 8249 * by DMA coal
8250 */
8251 reg = rd32(E1000_PCIEMISC);
8252 reg &= ~E1000_PCIEMISC_LX_DECISION;
8253 wr32(E1000_PCIEMISC, reg);
8254 } /* endif adapter->dmac is not disabled */
8255 } else if (hw->mac.type == e1000_82580) {
8256 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8257
b6e0c419
CW		 8258 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8259 wr32(E1000_DMACR, 0);
8260 }
8261}
8262
b980ac18
JK		 8263/**
8264 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8265 * @hw: pointer to hardware structure
8266 * @byte_offset: byte offset to read
8267 * @dev_addr: device address
8268 * @data: value read
8269 *
8270 * Performs byte read operation over I2C interface at
8271 * a specified device address.
b980ac18 8272 **/
441fc6fd 8273s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8274 u8 dev_addr, u8 *data)
441fc6fd
CW		 8275{
8276 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8277 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8278 s32 status;
8279 u16 swfw_mask = 0;
8280
8281 if (!this_client)
8282 return E1000_ERR_I2C;
8283
8284 swfw_mask = E1000_SWFW_PHY0_SM;
8285
23d87824 8286 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8287 return E1000_ERR_SWFW_SYNC;
8288
8289 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8290 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8291
8292 if (status < 0)
8293 return E1000_ERR_I2C;
8294 else {
8295 *data = status;
23d87824 8296 return 0;
441fc6fd
CW		 8297 }
8298}
8299
b980ac18
JK		 8300/**
8301 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8302 * @hw: pointer to hardware structure
8303 * @byte_offset: byte offset to write
8304 * @dev_addr: device address
8305 * @data: value to write
8306 *
8307 * Performs byte write operation over I2C interface at
8308 * a specified device address.
b980ac18 8309 **/
441fc6fd 8310s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8311 u8 dev_addr, u8 data)
441fc6fd
CW		 8312{
8313 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8314 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8315 s32 status;
8316 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8317
8318 if (!this_client)
8319 return E1000_ERR_I2C;
8320
23d87824 8321 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8322 return E1000_ERR_SWFW_SYNC;
8323 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8324 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8325
8326 if (status)
8327 return E1000_ERR_I2C;
8328 else
23d87824 8329 return 0;
441fc6fd
CW		 8330
8331}
907b7835
LMV		 8332
8333int igb_reinit_queues(struct igb_adapter *adapter)
8334{
8335 struct net_device *netdev = adapter->netdev;
8336 struct pci_dev *pdev = adapter->pdev;
8337 int err = 0;
8338
8339 if (netif_running(netdev))
8340 igb_close(netdev);
8341
02ef6e1d 8342 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8343
8344 if (igb_init_interrupt_scheme(adapter, true)) {
8345 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8346 return -ENOMEM;
8347 }
8348
8349 if (netif_running(netdev))
8350 err = igb_open(netdev);
8351
8352 return err;
8353}
0e71def2
GH		 8354
8355static void igb_nfc_filter_exit(struct igb_adapter *adapter)
8356{
8357 struct igb_nfc_filter *rule;
8358
8359 spin_lock(&adapter->nfc_lock);
8360
8361 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
8362 igb_erase_filter(adapter, rule);
8363
8364 spin_unlock(&adapter->nfc_lock);
8365}
8366
8367static void igb_nfc_filter_restore(struct igb_adapter *adapter)
8368{
8369 struct igb_nfc_filter *rule;
8370
8371 spin_lock(&adapter->nfc_lock);
8372
8373 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
8374 igb_add_filter(adapter, rule);
8375
8376 spin_unlock(&adapter->nfc_lock);
8377}
9d5c8243 8378/* igb_main.c */
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