[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / cxlflash / common.h

/*
 * CXL Flash Device Driver
 *
 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
 *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
 *
 * Copyright (C) 2015 IBM Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _CXLFLASH_COMMON_H
#define _CXLFLASH_COMMON_H

#include <linux/async.h>
#include <linux/cdev.h>
#include <linux/irq_poll.h>
#include <linux/list.h>
#include <linux/rwsem.h>
#include <linux/types.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>

extern const struct file_operations cxlflash_cxl_fops;

#define MAX_CONTEXT	CXLFLASH_MAX_CONTEXT	/* num contexts per afu */
#define MAX_FC_PORTS	CXLFLASH_MAX_FC_PORTS	/* max ports per AFU */
#define LEGACY_FC_PORTS	2			/* legacy ports per AFU */

#define CHAN2PORTBANK(_x)	((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
#define CHAN2BANKPORT(_x)	((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))

#define CHAN2PORTMASK(_x)	(1 << (_x))	/* channel to port mask */
#define PORTMASK2CHAN(_x)	(ilog2((_x)))	/* port mask to channel */
#define PORTNUM2CHAN(_x)	((_x) - 1)	/* port number to channel */

#define CXLFLASH_BLOCK_SIZE	4096		/* 4K blocks */
#define CXLFLASH_MAX_XFER_SIZE	16777216	/* 16MB transfer */
#define CXLFLASH_MAX_SECTORS	(CXLFLASH_MAX_XFER_SIZE/512)	/* SCSI wants
								 * max_sectors
								 * in units of
								 * 512 byte
								 * sectors
								 */

#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))

/* AFU command retry limit */
#define MC_RETRY_CNT	5	/* Sufficient for SCSI and certain AFU errors */

/* Command management definitions */
#define CXLFLASH_MAX_CMDS               256
#define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS

/* RRQ for master issued cmds */
#define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS

/* SQ for master issued cmds */
#define NUM_SQ_ENTRY			CXLFLASH_MAX_CMDS

/* Hardware queue definitions */
#define CXLFLASH_DEF_HWQS		1
#define CXLFLASH_MAX_HWQS		8
#define PRIMARY_HWQ			0


static inline void check_sizes(void)
{
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
}

/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
#define CMD_BUFSIZE     SIZE_4K

enum cxlflash_lr_state {
	LINK_RESET_INVALID,
	LINK_RESET_REQUIRED,
	LINK_RESET_COMPLETE
};

enum cxlflash_init_state {
	INIT_STATE_NONE,
	INIT_STATE_PCI,
	INIT_STATE_AFU,
	INIT_STATE_SCSI,
	INIT_STATE_CDEV
};

enum cxlflash_state {
	STATE_PROBING,	/* Initial state during probe */
	STATE_PROBED,	/* Temporary state, probe completed but EEH occurred */
	STATE_NORMAL,	/* Normal running state, everything good */
	STATE_RESET,	/* Reset state, trying to reset/recover */
	STATE_FAILTERM	/* Failed/terminating state, error out users/threads */
};

enum cxlflash_hwq_mode {
	HWQ_MODE_RR,	/* Roundrobin (default) */
	HWQ_MODE_TAG,	/* Distribute based on block MQ tag */
	HWQ_MODE_CPU,	/* CPU affinity */
	MAX_HWQ_MODE
};

/*
 * Each context has its own set of resource handles that is visible
 * only from that context.
 */

struct cxlflash_cfg {
	struct afu *afu;

	struct pci_dev *dev;
	struct pci_device_id *dev_id;
	struct Scsi_Host *host;
	int num_fc_ports;
	struct cdev cdev;
	struct device *chardev;

	ulong cxlflash_regs_pci;

	struct work_struct work_q;
	enum cxlflash_init_state init_state;
	enum cxlflash_lr_state lr_state;
	int lr_port;
	atomic_t scan_host_needed;

	struct cxl_afu *cxl_afu;

	atomic_t recovery_threads;
	struct mutex ctx_recovery_mutex;
	struct mutex ctx_tbl_list_mutex;
	struct rw_semaphore ioctl_rwsem;
	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	struct file_operations cxl_fops;

	/* Parameters that are LUN table related */
	int last_lun_index[MAX_FC_PORTS];
	int promote_lun_index;
	struct list_head lluns; /* list of llun_info structs */

	wait_queue_head_t tmf_waitq;
	spinlock_t tmf_slock;
	bool tmf_active;
	wait_queue_head_t reset_waitq;
	enum cxlflash_state state;
	async_cookie_t async_reset_cookie;
};

struct afu_cmd {
	struct sisl_ioarcb rcb;	/* IOARCB (cache line aligned) */
	struct sisl_ioasa sa;	/* IOASA must follow IOARCB */
	struct afu *parent;
	struct scsi_cmnd *scp;
	struct completion cevent;
	struct list_head queue;
	u32 hwq_index;

	u8 cmd_tmf:1,
	   cmd_aborted:1;

	struct list_head list;	/* Pending commands link */

	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	 * However for performance reasons the IOARCB/IOASA should be
	 * cache line aligned.
	 */
} __aligned(cache_line_size());

static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
{
	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
}

static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
{
	struct afu_cmd *afuc = sc_to_afuc(sc);

	memset(afuc, 0, sizeof(*afuc));
	INIT_LIST_HEAD(&afuc->queue);
	return afuc;
}

struct hwq {
	/* Stuff requiring alignment go first. */
	struct sisl_ioarcb sq[NUM_SQ_ENTRY];		/* 16K SQ */
	u64 rrq_entry[NUM_RRQ_ENTRY];			/* 2K RRQ */

	/* Beware of alignment till here. Preferably introduce new
	 * fields after this point
	 */
	struct afu *afu;
	struct cxl_context *ctx;
	struct cxl_ioctl_start_work work;
	struct sisl_host_map __iomem *host_map;		/* MC host map */
	struct sisl_ctrl_map __iomem *ctrl_map;		/* MC control map */
	ctx_hndl_t ctx_hndl;	/* master's context handle */
	u32 index;		/* Index of this hwq */
	struct list_head pending_cmds;	/* Commands pending completion */

	atomic_t hsq_credits;
	spinlock_t hsq_slock;	/* Hardware send queue lock */
	struct sisl_ioarcb *hsq_start;
	struct sisl_ioarcb *hsq_end;
	struct sisl_ioarcb *hsq_curr;
	spinlock_t hrrq_slock;
	u64 *hrrq_start;
	u64 *hrrq_end;
	u64 *hrrq_curr;
	bool toggle;

	s64 room;

	struct irq_poll irqpoll;
} __aligned(cache_line_size());

struct afu {
	struct hwq hwqs[CXLFLASH_MAX_HWQS];
	int (*send_cmd)(struct afu *, struct afu_cmd *);
	int (*context_reset)(struct hwq *);

	/* AFU HW */
	struct cxlflash_afu_map __iomem *afu_map;	/* entire MMIO map */

	atomic_t cmds_active;	/* Number of currently active AFU commands */
	u64 hb;
	u32 internal_lun;	/* User-desired LUN mode for this AFU */

	u32 num_hwqs;		/* Number of hardware queues */
	u32 desired_hwqs;	/* Desired h/w queues, effective on AFU reset */
	enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
	u32 hwq_rr_count;	/* Count to distribute traffic for roundrobin */

	char version[16];
	u64 interface_version;

	u32 irqpoll_weight;
	struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
};

static inline struct hwq *get_hwq(struct afu *afu, u32 index)
{
	WARN_ON(index >= CXLFLASH_MAX_HWQS);

	return &afu->hwqs[index];
}

static inline bool afu_is_irqpoll_enabled(struct afu *afu)
{
	return !!afu->irqpoll_weight;
}

static inline bool afu_has_cap(struct afu *afu, u64 cap)
{
	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;

	return afu_cap & cap;
}

static inline bool afu_is_afu_debug(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
}

static inline bool afu_is_lun_provision(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
}

static inline bool afu_is_sq_cmd_mode(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
}

static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
}

static inline u64 lun_to_lunid(u64 lun)
{
	__be64 lun_id;

	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
	return be64_to_cpu(lun_id);
}

static inline struct fc_port_bank __iomem *get_fc_port_bank(
					    struct cxlflash_cfg *cfg, int i)
{
	struct afu *afu = cfg->afu;

	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
}

static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
}

static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
}

int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
void cxlflash_list_init(void);
void cxlflash_term_global_luns(void);
void cxlflash_free_errpage(void);
int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg);
void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);

#endif /* ifndef _CXLFLASH_COMMON_H */
Commit	Line	Data
c21e0bbf MO	1	/*
	2	* CXL Flash Device Driver
	3	*
	4	* Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
	5	* Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
	6	*
	7	* Copyright (C) 2015 IBM Corporation
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#ifndef _CXLFLASH_COMMON_H
	16	#define _CXLFLASH_COMMON_H
	17
3b4f03cd	18	#include <linux/async.h>
f3d79b3e	19	#include <linux/cdev.h>
2588f222	20	#include <linux/irq_poll.h>
c21e0bbf	21	#include <linux/list.h>
0a27ae51	22	#include <linux/rwsem.h>
c21e0bbf MO	23	#include <linux/types.h>
c21e0bbf MO	24	#include <scsi/scsi.h>
5fbb96c8	25	#include <scsi/scsi_cmnd.h>
c21e0bbf MO	26	#include <scsi/scsi_device.h>
c21e0bbf MO	27
17ead26f	28	extern const struct file_operations cxlflash_cxl_fops;
c21e0bbf	29
66d4bce4	30	#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
a290b480 MO	31	#define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
	32	#define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
	33
	34	#define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
	35	#define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
c21e0bbf	36
e8e17ea6 MO	37	#define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
	38	#define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
	39	#define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
	40
39e9d618	41	#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
c21e0bbf MO	42	#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
c21e0bbf MO	43	#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
39e9d618 MO	44	* max_sectors
	45	* in units of
	46	* 512 byte
	47	* sectors
	48	*/
c21e0bbf	49
c21e0bbf MO	50	#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
	51
	52	/* AFU command retry limit */
39e9d618	53	#define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */
c21e0bbf MO	54
c21e0bbf MO	55	/* Command management definitions */
83430833	56	#define CXLFLASH_MAX_CMDS 256
c21e0bbf MO	57	#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
c21e0bbf MO	58
83430833 MK	59	/* RRQ for master issued cmds */
	60	#define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
	61
bae0ac69 MO	62	/* SQ for master issued cmds */
	63	#define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
	64
bb85ef68 MO	65	/* Hardware queue definitions */
	66	#define CXLFLASH_DEF_HWQS 1
	67	#define CXLFLASH_MAX_HWQS 8
a583d00a UK	68	#define PRIMARY_HWQ 0
a583d00a UK	69
c21e0bbf MO	70
	71	static inline void check_sizes(void)
	72	{
a290b480	73	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
db853d50	74	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
c21e0bbf MO	75	}
	76
	77	/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
	78	#define CMD_BUFSIZE SIZE_4K
	79
c21e0bbf MO	80	enum cxlflash_lr_state {
	81	LINK_RESET_INVALID,
	82	LINK_RESET_REQUIRED,
	83	LINK_RESET_COMPLETE
	84	};
	85
	86	enum cxlflash_init_state {
	87	INIT_STATE_NONE,
	88	INIT_STATE_PCI,
	89	INIT_STATE_AFU,
f3d79b3e UK	90	INIT_STATE_SCSI,
f3d79b3e UK	91	INIT_STATE_CDEV
c21e0bbf MO	92	};
c21e0bbf MO	93
5cdac81a	94	enum cxlflash_state {
f92ba507 MO	95	STATE_PROBING, /* Initial state during probe */
f92ba507 MO	96	STATE_PROBED, /* Temporary state, probe completed but EEH occurred */
5cdac81a	97	STATE_NORMAL, /* Normal running state, everything good */
439e85c1	98	STATE_RESET, /* Reset state, trying to reset/recover */
5cdac81a MO	99	STATE_FAILTERM /* Failed/terminating state, error out users/threads */
	100	};
	101
8c052e9e MO	102	enum cxlflash_hwq_mode {
	103	HWQ_MODE_RR, /* Roundrobin (default) */
	104	HWQ_MODE_TAG, /* Distribute based on block MQ tag */
	105	HWQ_MODE_CPU, /* CPU affinity */
	106	MAX_HWQ_MODE
	107	};
	108
c21e0bbf MO	109	/*
	110	* Each context has its own set of resource handles that is visible
	111	* only from that context.
	112	*/
	113
	114	struct cxlflash_cfg {
	115	struct afu *afu;
c21e0bbf MO	116
	117	struct pci_dev *dev;
	118	struct pci_device_id *dev_id;
	119	struct Scsi_Host *host;
66d4bce4	120	int num_fc_ports;
f3d79b3e UK	121	struct cdev cdev;
f3d79b3e UK	122	struct device *chardev;
c21e0bbf MO	123
	124	ulong cxlflash_regs_pci;
	125
c21e0bbf MO	126	struct work_struct work_q;
	127	enum cxlflash_init_state init_state;
	128	enum cxlflash_lr_state lr_state;
	129	int lr_port;
ef51074a	130	atomic_t scan_host_needed;
c21e0bbf MO	131
c21e0bbf MO	132	struct cxl_afu *cxl_afu;
c21e0bbf	133
65be2c79 MO	134	atomic_t recovery_threads;
	135	struct mutex ctx_recovery_mutex;
	136	struct mutex ctx_tbl_list_mutex;
0a27ae51	137	struct rw_semaphore ioctl_rwsem;
65be2c79 MO	138	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	139	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	140	struct file_operations cxl_fops;
	141
2cb79266	142	/* Parameters that are LUN table related */
66d4bce4	143	int last_lun_index[MAX_FC_PORTS];
2cb79266	144	int promote_lun_index;
65be2c79 MO	145	struct list_head lluns; /* list of llun_info structs */
65be2c79 MO	146
c21e0bbf	147	wait_queue_head_t tmf_waitq;
018d1dc9	148	spinlock_t tmf_slock;
c21e0bbf	149	bool tmf_active;
439e85c1	150	wait_queue_head_t reset_waitq;
5cdac81a	151	enum cxlflash_state state;
3b4f03cd	152	async_cookie_t async_reset_cookie;
c21e0bbf MO	153	};
	154
	155	struct afu_cmd {
	156	struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
	157	struct sisl_ioasa sa; /* IOASA must follow IOARCB */
c21e0bbf	158	struct afu *parent;
fe7f9698	159	struct scsi_cmnd *scp;
9ba848ac	160	struct completion cevent;
7bb512aa	161	struct list_head queue;
8c052e9e	162	u32 hwq_index;
c21e0bbf	163
2450a5e3 UK	164	u8 cmd_tmf:1,
	165	cmd_aborted:1;
	166
d732d14f	167	struct list_head list; /* Pending commands link */
c21e0bbf MO	168
	169	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	170	* However for performance reasons the IOARCB/IOASA should be
	171	* cache line aligned.
	172	*/
	173	} __aligned(cache_line_size());
	174
5fbb96c8 MO	175	static inline struct afu_cmd sc_to_afuc(struct scsi_cmnd sc)
	176	{
	177	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
	178	}
	179
	180	static inline struct afu_cmd sc_to_afucz(struct scsi_cmnd sc)
	181	{
	182	struct afu_cmd *afuc = sc_to_afuc(sc);
	183
	184	memset(afuc, 0, sizeof(*afuc));
2450a5e3	185	INIT_LIST_HEAD(&afuc->queue);
5fbb96c8 MO	186	return afuc;
	187	}
	188
a583d00a	189	struct hwq {
c21e0bbf	190	/* Stuff requiring alignment go first. */
bae0ac69 MO	191	struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */
bae0ac69 MO	192	u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */
c21e0bbf MO	193
	194	/* Beware of alignment till here. Preferably introduce new
	195	* fields after this point
	196	*/
a583d00a UK	197	struct afu *afu;
a583d00a UK	198	struct cxl_context *ctx;
c21e0bbf	199	struct cxl_ioctl_start_work work;
1786f4a0 MO	200	struct sisl_host_map __iomem host_map; / MC host map */
1786f4a0 MO	201	struct sisl_ctrl_map __iomem ctrl_map; / MC control map */
c21e0bbf	202	ctx_hndl_t ctx_hndl; /* master's context handle */
a583d00a	203	u32 index; /* Index of this hwq */
d732d14f	204	struct list_head pending_cmds; /* Commands pending completion */
bae0ac69 MO	205
bae0ac69 MO	206	atomic_t hsq_credits;
edc034e8	207	spinlock_t hsq_slock; /* Hardware send queue lock */
bae0ac69 MO	208	struct sisl_ioarcb *hsq_start;
	209	struct sisl_ioarcb *hsq_end;
	210	struct sisl_ioarcb *hsq_curr;
7bb512aa	211	spinlock_t hrrq_slock;
c21e0bbf MO	212	u64 *hrrq_start;
	213	u64 *hrrq_end;
	214	u64 *hrrq_curr;
	215	bool toggle;
a583d00a	216
11f7b184	217	s64 room;
a583d00a UK	218
	219	struct irq_poll irqpoll;
	220	} __aligned(cache_line_size());
	221
	222	struct afu {
bb85ef68	223	struct hwq hwqs[CXLFLASH_MAX_HWQS];
a583d00a	224	int (send_cmd)(struct afu , struct afu_cmd *);
ddc869e9	225	int (context_reset)(struct hwq );
a583d00a UK	226
	227	/* AFU HW */
	228	struct cxlflash_afu_map __iomem afu_map; / entire MMIO map */
	229
	230	atomic_t cmds_active; /* Number of currently active AFU commands */
c21e0bbf	231	u64 hb;
c21e0bbf	232	u32 internal_lun; /* User-desired LUN mode for this AFU */
8c052e9e	233
bb85ef68 MO	234	u32 num_hwqs; /* Number of hardware queues */
bb85ef68 MO	235	u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */
8c052e9e MO	236	enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
8c052e9e MO	237	u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */
c21e0bbf	238
e5ce067b	239	char version[16];
c21e0bbf MO	240	u64 interface_version;
c21e0bbf MO	241
2588f222	242	u32 irqpoll_weight;
c21e0bbf	243	struct cxlflash_cfg parent; / Pointer back to parent cxlflash_cfg */
c21e0bbf MO	244	};
c21e0bbf MO	245
a583d00a UK	246	static inline struct hwq get_hwq(struct afu afu, u32 index)
a583d00a UK	247	{
bb85ef68	248	WARN_ON(index >= CXLFLASH_MAX_HWQS);
a583d00a UK	249
	250	return &afu->hwqs[index];
	251	}
	252
2588f222 MO	253	static inline bool afu_is_irqpoll_enabled(struct afu *afu)
	254	{
	255	return !!afu->irqpoll_weight;
	256	}
	257
0808aa95	258	static inline bool afu_has_cap(struct afu *afu, u64 cap)
bae0ac69 MO	259	{
	260	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
	261
0808aa95	262	return afu_cap & cap;
bae0ac69 MO	263	}
bae0ac69 MO	264
d3c606a7 MO	265	static inline bool afu_is_afu_debug(struct afu *afu)
	266	{
	267	return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
	268	}
	269
1f829583 MO	270	static inline bool afu_is_lun_provision(struct afu *afu)
	271	{
	272	return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
	273	}
	274
bae0ac69 MO	275	static inline bool afu_is_sq_cmd_mode(struct afu *afu)
bae0ac69 MO	276	{
0808aa95	277	return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
bae0ac69 MO	278	}
	279
	280	static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
	281	{
0808aa95	282	return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
bae0ac69 MO	283	}
bae0ac69 MO	284
c21e0bbf MO	285	static inline u64 lun_to_lunid(u64 lun)
c21e0bbf MO	286	{
1786f4a0	287	__be64 lun_id;
c21e0bbf MO	288
c21e0bbf MO	289	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
1786f4a0	290	return be64_to_cpu(lun_id);
c21e0bbf MO	291	}
c21e0bbf MO	292
a290b480 MO	293	static inline struct fc_port_bank __iomem *get_fc_port_bank(
a290b480 MO	294	struct cxlflash_cfg *cfg, int i)
c885d3fe MO	295	{
	296	struct afu *afu = cfg->afu;
	297
a290b480 MO	298	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
	299	}
	300
	301	static inline __be64 __iomem get_fc_port_regs(struct cxlflash_cfg cfg, int i)
	302	{
	303	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
	304
	305	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
c885d3fe MO	306	}
	307
	308	static inline __be64 __iomem get_fc_port_luns(struct cxlflash_cfg cfg, int i)
	309	{
a290b480	310	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
c885d3fe	311
a290b480	312	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
c885d3fe MO	313	}
c885d3fe MO	314
39e9d618	315	int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
65be2c79 MO	316	void cxlflash_list_init(void);
	317	void cxlflash_term_global_luns(void);
	318	void cxlflash_free_errpage(void);
39e9d618 MO	319	int cxlflash_ioctl(struct scsi_device sdev, int cmd, void __user arg);
	320	void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
	321	int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
	322	void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
	323	void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
65be2c79	324
c21e0bbf	325	#endif /* ifndef _CXLFLASH_COMMON_H */