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[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / imx6qdl-nitrogen6_max.dtsi
1 /*
2 * Copyright 2015 Boundary Devices, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/input/input.h>
43
44 / {
45 chosen {
46 stdout-path = &uart2;
47 };
48
49 memory {
50 reg = <0x10000000 0xF0000000>;
51 };
52
53 regulators {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 reg_1p8v: regulator@0 {
59 compatible = "regulator-fixed";
60 reg = <0>;
61 regulator-name = "1P8V";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 regulator-always-on;
65 };
66
67 reg_2p5v: regulator@1 {
68 compatible = "regulator-fixed";
69 reg = <1>;
70 regulator-name = "2P5V";
71 regulator-min-microvolt = <2500000>;
72 regulator-max-microvolt = <2500000>;
73 regulator-always-on;
74 };
75
76 reg_3p3v: regulator@2 {
77 compatible = "regulator-fixed";
78 reg = <2>;
79 regulator-name = "3P3V";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 regulator-always-on;
83 };
84
85 reg_usb_otg_vbus: regulator@3 {
86 compatible = "regulator-fixed";
87 reg = <3>;
88 regulator-name = "usb_otg_vbus";
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
91 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
92 enable-active-high;
93 };
94
95 reg_usb_h1_vbus: regulator@4 {
96 compatible = "regulator-fixed";
97 reg = <4>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_usbh1>;
100 regulator-name = "usb_h1_vbus";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
104 enable-active-high;
105 };
106
107 reg_wlan_vmmc: regulator@5 {
108 compatible = "regulator-fixed";
109 reg = <5>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_wlan_vmmc>;
112 regulator-name = "reg_wlan_vmmc";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
116 startup-delay-us = <70000>;
117 enable-active-high;
118 };
119
120 reg_can_xcvr: regulator@6 {
121 compatible = "regulator-fixed";
122 reg = <6>;
123 regulator-name = "CAN XCVR";
124 regulator-min-microvolt = <3300000>;
125 regulator-max-microvolt = <3300000>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_can_xcvr>;
128 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
129 };
130 };
131
132 gpio-keys {
133 compatible = "gpio-keys";
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_gpio_keys>;
136
137 power {
138 label = "Power Button";
139 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
140 linux,code = <KEY_POWER>;
141 gpio-key,wakeup;
142 };
143
144 menu {
145 label = "Menu";
146 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
147 linux,code = <KEY_MENU>;
148 };
149
150 home {
151 label = "Home";
152 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
153 linux,code = <KEY_HOME>;
154 };
155
156 back {
157 label = "Back";
158 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
159 linux,code = <KEY_BACK>;
160 };
161
162 volume-up {
163 label = "Volume Up";
164 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
165 linux,code = <KEY_VOLUMEUP>;
166 };
167
168 volume-down {
169 label = "Volume Down";
170 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
171 linux,code = <KEY_VOLUMEDOWN>;
172 };
173 };
174
175 i2cmux@2 {
176 compatible = "i2c-mux-gpio";
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c2mux>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH
182 &gpio4 15 GPIO_ACTIVE_HIGH>;
183 i2c-parent = <&i2c2>;
184 idle-state = <0>;
185
186 i2c2@1 {
187 reg = <1>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 };
191
192 i2c2@2 {
193 reg = <2>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
197 };
198
199 i2cmux@3 {
200 compatible = "i2c-mux-gpio";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c3mux>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
206 i2c-parent = <&i2c3>;
207 idle-state = <0>;
208
209 i2c3@1 {
210 reg = <1>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 };
214 };
215
216 leds {
217 compatible = "gpio-leds";
218
219 speaker-enable {
220 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
221 retain-state-suspended;
222 default-state = "off";
223 };
224
225 ttymxc4-rs232 {
226 gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
227 retain-state-suspended;
228 default-state = "on";
229 };
230 };
231
232 backlight_lcd: backlight_lcd {
233 compatible = "pwm-backlight";
234 pwms = <&pwm1 0 5000000>;
235 brightness-levels = <0 4 8 16 32 64 128 255>;
236 default-brightness-level = <7>;
237 power-supply = <&reg_3p3v>;
238 status = "okay";
239 };
240
241 backlight_lvds0: backlight_lvds0 {
242 compatible = "pwm-backlight";
243 pwms = <&pwm4 0 5000000>;
244 brightness-levels = <0 4 8 16 32 64 128 255>;
245 default-brightness-level = <7>;
246 power-supply = <&reg_3p3v>;
247 status = "okay";
248 };
249
250 backlight_lvds1: backlight_lvds1 {
251 compatible = "pwm-backlight";
252 pwms = <&pwm2 0 5000000>;
253 brightness-levels = <0 4 8 16 32 64 128 255>;
254 default-brightness-level = <7>;
255 power-supply = <&reg_3p3v>;
256 status = "okay";
257 };
258
259 lcd_display: display@di0 {
260 compatible = "fsl,imx-parallel-display";
261 #address-cells = <1>;
262 #size-cells = <0>;
263 interface-pix-fmt = "bgr666";
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_j15>;
266 status = "okay";
267
268 port@0 {
269 reg = <0>;
270
271 lcd_display_in: endpoint {
272 remote-endpoint = <&ipu1_di0_disp0>;
273 };
274 };
275
276 port@1 {
277 reg = <1>;
278
279 lcd_display_out: endpoint {
280 remote-endpoint = <&lcd_panel_in>;
281 };
282 };
283 };
284
285 panel_lcd {
286 compatible = "okaya,rs800480t-7x0gp";
287 backlight = <&backlight_lcd>;
288
289 port {
290 lcd_panel_in: endpoint {
291 remote-endpoint = <&lcd_display_out>;
292 };
293 };
294 };
295
296 panel_lvds0 {
297 compatible = "hannstar,hsd100pxn1";
298 backlight = <&backlight_lvds0>;
299
300 port {
301 panel_in_lvds0: endpoint {
302 remote-endpoint = <&lvds0_out>;
303 };
304 };
305 };
306
307 panel_lvds1 {
308 compatible = "hannstar,hsd100pxn1";
309 backlight = <&backlight_lvds1>;
310
311 port {
312 panel_in_lvds1: endpoint {
313 remote-endpoint = <&lvds1_out>;
314 };
315 };
316 };
317
318 sound {
319 compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
320 "fsl,imx-audio-sgtl5000";
321 model = "imx6q-nitrogen6_max-sgtl5000";
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_sgtl5000>;
324 ssi-controller = <&ssi1>;
325 audio-codec = <&codec>;
326 audio-routing =
327 "MIC_IN", "Mic Jack",
328 "Mic Jack", "Mic Bias",
329 "Headphone Jack", "HP_OUT";
330 mux-int-port = <1>;
331 mux-ext-port = <3>;
332 };
333 };
334
335 &audmux {
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_audmux>;
338 status = "okay";
339 };
340
341 &can1 {
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_can1>;
344 xceiver-supply = <&reg_can_xcvr>;
345 status = "okay";
346 };
347
348 &clks {
349 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
350 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
351 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
352 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
353 };
354
355 &ecspi1 {
356 fsl,spi-num-chipselects = <1>;
357 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_ecspi1>;
360 status = "okay";
361
362 flash: m25p80@0 {
363 compatible = "microchip,sst25vf016b";
364 spi-max-frequency = <20000000>;
365 reg = <0>;
366 };
367 };
368
369 &fec {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_enet>;
372 phy-mode = "rgmii";
373 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
374 txen-skew-ps = <0>;
375 txc-skew-ps = <3000>;
376 rxdv-skew-ps = <0>;
377 rxc-skew-ps = <3000>;
378 rxd0-skew-ps = <0>;
379 rxd1-skew-ps = <0>;
380 rxd2-skew-ps = <0>;
381 rxd3-skew-ps = <0>;
382 txd0-skew-ps = <0>;
383 txd1-skew-ps = <0>;
384 txd2-skew-ps = <0>;
385 txd3-skew-ps = <0>;
386 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
387 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
388 status = "okay";
389 };
390
391 &hdmi {
392 ddc-i2c-bus = <&i2c2>;
393 status = "okay";
394 };
395
396 &i2c1 {
397 clock-frequency = <100000>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_i2c1>;
400 status = "okay";
401
402 codec: sgtl5000@0a {
403 compatible = "fsl,sgtl5000";
404 reg = <0x0a>;
405 clocks = <&clks 201>;
406 VDDA-supply = <&reg_2p5v>;
407 VDDIO-supply = <&reg_3p3v>;
408 };
409
410 rtc: rtc@68 {
411 compatible = "st,rv4162";
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_rv4162>;
414 reg = <0x68>;
415 interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>;
416 };
417 };
418
419 &i2c2 {
420 clock-frequency = <100000>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_i2c2>;
423 status = "okay";
424 };
425
426 &i2c3 {
427 clock-frequency = <100000>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_i2c3>;
430 status = "okay";
431
432 touchscreen@04 {
433 compatible = "eeti,egalax_ts";
434 reg = <0x04>;
435 interrupt-parent = <&gpio1>;
436 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
437 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
438 };
439
440 touchscreen@38 {
441 compatible = "edt,edt-ft5x06";
442 reg = <0x38>;
443 interrupt-parent = <&gpio1>;
444 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
445 };
446 };
447
448 &iomuxc {
449 imx6q-nitrogen6_max {
450 pinctrl_audmux: audmuxgrp {
451 fsl,pins = <
452 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
453 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
454 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
455 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
456 >;
457 };
458
459 pinctrl_can1: can1grp {
460 fsl,pins = <
461 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
462 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
463 >;
464 };
465
466 pinctrl_can_xcvr: can-xcvrgrp {
467 fsl,pins = <
468 /* Flexcan XCVR enable */
469 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
470 >;
471 };
472
473 pinctrl_ecspi1: ecspi1grp {
474 fsl,pins = <
475 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
476 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
477 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
478 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
479 >;
480 };
481
482 pinctrl_enet: enetgrp {
483 fsl,pins = <
484 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
485 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
486 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
487 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
488 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
489 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
490 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
491 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
492 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
493 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
494 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
495 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
496 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
497 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
498 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
499 /* Phy reset */
500 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
501 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
502 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
503 >;
504 };
505
506 pinctrl_gpio_keys: gpio_keysgrp {
507 fsl,pins = <
508 /* Power Button */
509 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
510 /* Menu Button */
511 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
512 /* Home Button */
513 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
514 /* Back Button */
515 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
516 /* Volume Up Button */
517 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
518 /* Volume Down Button */
519 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
520 >;
521 };
522
523 pinctrl_i2c1: i2c1grp {
524 fsl,pins = <
525 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
526 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
527 >;
528 };
529
530 pinctrl_i2c2: i2c2grp {
531 fsl,pins = <
532 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
533 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
534 >;
535 };
536
537 pinctrl_i2c2mux: i2c2muxgrp {
538 fsl,pins = <
539 /* ov5642 camera i2c enable */
540 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0
541 /* ov5640_mipi camera i2c enable */
542 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
543 >;
544 };
545
546 pinctrl_i2c3: i2c3grp {
547 fsl,pins = <
548 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
549 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
550 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
551 >;
552 };
553
554 pinctrl_i2c3mux: i2c3muxgrp {
555 fsl,pins = <
556 /* PCIe I2C enable */
557 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
558 >;
559 };
560
561 pinctrl_j15: j15grp {
562 fsl,pins = <
563 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
564 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
565 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
566 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
567 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
568 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
569 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
570 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
571 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
572 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
573 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
574 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
575 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
576 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
577 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
578 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
579 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
580 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
581 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
582 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
583 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
584 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
585 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
586 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
587 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
588 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
589 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
590 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
591 >;
592 };
593
594 pinctrl_pcie: pciegrp {
595 fsl,pins = <
596 /* PCIe reset */
597 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0
598 >;
599 };
600
601 pinctrl_pwm1: pwm1grp {
602 fsl,pins = <
603 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
604 >;
605 };
606
607 pinctrl_pwm2: pwm2grp {
608 fsl,pins = <
609 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
610 >;
611 };
612
613 pinctrl_pwm3: pwm3grp {
614 fsl,pins = <
615 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
616 >;
617 };
618
619 pinctrl_pwm4: pwm4grp {
620 fsl,pins = <
621 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
622 >;
623 };
624
625 pinctrl_rv4162: rv4162grp {
626 fsl,pins = <
627 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
628 >;
629 };
630
631 pinctrl_sgtl5000: sgtl5000grp {
632 fsl,pins = <
633 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
634 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
635 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
636 >;
637 };
638
639 pinctrl_uart1: uart1grp {
640 fsl,pins = <
641 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
642 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
643 >;
644 };
645
646 pinctrl_uart2: uart2grp {
647 fsl,pins = <
648 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
649 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
650 >;
651 };
652
653 pinctrl_uart5: uart5grp {
654 fsl,pins = <
655 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1
656 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1
657 /* RS485 RX Enable: pull up */
658 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1
659 /* RS485 DEN: pull down */
660 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1
661 /* RS485/!RS232 Select: pull down (rs232) */
662 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1
663 /* ON: pull down */
664 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1
665 >;
666 };
667
668 pinctrl_usbh1: usbh1grp {
669 fsl,pins = <
670 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0
671 >;
672 };
673
674 pinctrl_usbotg: usbotggrp {
675 fsl,pins = <
676 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
677 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
678 /* power enable, high active */
679 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
680 >;
681 };
682
683 pinctrl_usdhc2: usdhc2grp {
684 fsl,pins = <
685 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
686 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
687 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
688 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
689 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
690 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
691 >;
692 };
693
694 pinctrl_usdhc3: usdhc3grp {
695 fsl,pins = <
696 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
697 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
698 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
699 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
700 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
701 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
702 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0
703 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
704 >;
705 };
706
707 pinctrl_usdhc4: usdhc4grp {
708 fsl,pins = <
709 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
710 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
711 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
712 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
713 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
714 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
715 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
716 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
717 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
718 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
719 >;
720 };
721
722 pinctrl_wlan_vmmc: wlan_vmmcgrp {
723 fsl,pins = <
724 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
725 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
726 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
727 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
728 >;
729 };
730 };
731 };
732
733 &ipu1_di0_disp0 {
734 remote-endpoint = <&lcd_display_in>;
735 };
736
737 &ldb {
738 status = "okay";
739
740 lvds-channel@0 {
741 fsl,data-mapping = "spwg";
742 fsl,data-width = <18>;
743 status = "okay";
744
745 port@4 {
746 reg = <4>;
747
748 lvds0_out: endpoint {
749 remote-endpoint = <&panel_in_lvds0>;
750 };
751 };
752 };
753
754 lvds-channel@1 {
755 fsl,data-mapping = "spwg";
756 fsl,data-width = <18>;
757 status = "okay";
758
759 port@4 {
760 reg = <4>;
761
762 lvds1_out: endpoint {
763 remote-endpoint = <&panel_in_lvds1>;
764 };
765 };
766 };
767 };
768
769 &pcie {
770 pinctrl-names = "default";
771 pinctrl-0 = <&pinctrl_pcie>;
772 reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
773 status = "okay";
774 };
775
776 &pwm1 {
777 pinctrl-names = "default";
778 pinctrl-0 = <&pinctrl_pwm1>;
779 status = "okay";
780 };
781
782 &pwm2 {
783 pinctrl-names = "default";
784 pinctrl-0 = <&pinctrl_pwm2>;
785 status = "okay";
786 };
787
788 &pwm3 {
789 pinctrl-names = "default";
790 pinctrl-0 = <&pinctrl_pwm3>;
791 status = "okay";
792 };
793
794 &pwm4 {
795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_pwm4>;
797 status = "okay";
798 };
799
800 &ssi1 {
801 status = "okay";
802 };
803
804 &uart1 {
805 pinctrl-names = "default";
806 pinctrl-0 = <&pinctrl_uart1>;
807 status = "okay";
808 };
809
810 &uart2 {
811 pinctrl-names = "default";
812 pinctrl-0 = <&pinctrl_uart2>;
813 status = "okay";
814 };
815
816 &uart5 {
817 pinctrl-names = "default";
818 pinctrl-0 = <&pinctrl_uart5>;
819 status = "okay";
820 };
821
822 &usbh1 {
823 vbus-supply = <&reg_usb_h1_vbus>;
824 status = "okay";
825 };
826
827 &usbotg {
828 vbus-supply = <&reg_usb_otg_vbus>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&pinctrl_usbotg>;
831 disable-over-current;
832 status = "okay";
833 };
834
835 &usdhc2 {
836 pinctrl-names = "default";
837 pinctrl-0 = <&pinctrl_usdhc2>;
838 bus-width = <4>;
839 non-removable;
840 vmmc-supply = <&reg_wlan_vmmc>;
841 cap-power-off-card;
842 keep-power-in-suspend;
843 status = "okay";
844
845 #address-cells = <1>;
846 #size-cells = <0>;
847 wlcore: wlcore@2 {
848 compatible = "ti,wl1271";
849 reg = <2>;
850 interrupt-parent = <&gpio6>;
851 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
852 ref-clock-frequency = <38400000>;
853 };
854 };
855
856 &usdhc3 {
857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_usdhc3>;
859 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
860 bus-width = <4>;
861 vmmc-supply = <&reg_3p3v>;
862 status = "okay";
863 };
864
865 &usdhc4 {
866 pinctrl-names = "default";
867 pinctrl-0 = <&pinctrl_usdhc4>;
868 bus-width = <8>;
869 non-removable;
870 vmmc-supply = <&reg_1p8v>;
871 keep-power-in-suspend;
872 status = "okay";
873 };
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