arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright (c) 2015 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/clock/bcm-ns2.h>
  35
  36 / {
  37         compatible = "brcm,ns2";
  38         interrupt-parent = <&gic>;
  39         #address-cells = <2>;
  40         #size-cells = <2>;
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 A57_0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a57", "arm,armv8";
  49                         reg = <0 0>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&CLUSTER0_L2>;
  52                 };
  53
  54                 A57_1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a57", "arm,armv8";
  57                         reg = <0 1>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&CLUSTER0_L2>;
  60                 };
  61
  62                 A57_2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a57", "arm,armv8";
  65                         reg = <0 2>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&CLUSTER0_L2>;
  68                 };
  69
  70                 A57_3: cpu@3 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a57", "arm,armv8";
  73                         reg = <0 3>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&CLUSTER0_L2>;
  76                 };
  77
  78                 CLUSTER0_L2: l2-cache@000 {
  79                         compatible = "cache";
  80                 };
  81         };
  82
  83         psci {
  84                 compatible = "arm,psci-1.0";
  85                 method = "smc";
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv8-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  91                               IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  93                               IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  95                               IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  97                               IRQ_TYPE_LEVEL_LOW)>;
  98         };
  99
 100         pmu {
 101                 compatible = "arm,armv8-pmuv3";
 102                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 103                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 106                 interrupt-affinity = <&A57_0>,
 107                                      <&A57_1>,
 108                                      <&A57_2>,
 109                                      <&A57_3>;
 110         };
 111
 112         pcie0: pcie@20020000 {
 113                 compatible = "brcm,iproc-pcie";
 114                 reg = <0 0x20020000 0 0x1000>;
 115
 116                 #interrupt-cells = <1>;
 117                 interrupt-map-mask = <0 0 0 0>;
 118                 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
 119
 120                 linux,pci-domain = <0>;
 121
 122                 bus-range = <0x00 0xff>;
 123
 124                 #address-cells = <3>;
 125                 #size-cells = <2>;
 126                 device_type = "pci";
 127                 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
 128
 129                 brcm,pcie-ob;
 130                 brcm,pcie-ob-oarr-size;
 131                 brcm,pcie-ob-axi-offset = <0x00000000>;
 132                 brcm,pcie-ob-window-size = <256>;
 133
 134                 status = "disabled";
 135
 136                 phys = <&pci_phy0>;
 137                 phy-names = "pcie-phy";
 138
 139                 msi-parent = <&msi0>;
 140                 msi0: msi@20020000 {
 141                         compatible = "brcm,iproc-msi";
 142                         msi-controller;
 143                         interrupt-parent = <&gic>;
 144                         interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
 145                                      <GIC_SPI 278 IRQ_TYPE_NONE>,
 146                                      <GIC_SPI 279 IRQ_TYPE_NONE>,
 147                                      <GIC_SPI 280 IRQ_TYPE_NONE>;
 148                         brcm,num-eq-region = <1>;
 149                         brcm,num-msi-msg-region = <1>;
 150                 };
 151         };
 152
 153         pcie4: pcie@50020000 {
 154                 compatible = "brcm,iproc-pcie";
 155                 reg = <0 0x50020000 0 0x1000>;
 156
 157                 #interrupt-cells = <1>;
 158                 interrupt-map-mask = <0 0 0 0>;
 159                 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
 160
 161                 linux,pci-domain = <4>;
 162
 163                 bus-range = <0x00 0xff>;
 164
 165                 #address-cells = <3>;
 166                 #size-cells = <2>;
 167                 device_type = "pci";
 168                 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
 169
 170                 brcm,pcie-ob;
 171                 brcm,pcie-ob-oarr-size;
 172                 brcm,pcie-ob-axi-offset = <0x30000000>;
 173                 brcm,pcie-ob-window-size = <256>;
 174
 175                 status = "disabled";
 176
 177                 phys = <&pci_phy1>;
 178                 phy-names = "pcie-phy";
 179
 180                 msi-parent = <&msi4>;
 181                 msi4: msi@50020000 {
 182                         compatible = "brcm,iproc-msi";
 183                         msi-controller;
 184                         interrupt-parent = <&gic>;
 185                         interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
 186                                      <GIC_SPI 302 IRQ_TYPE_NONE>,
 187                                      <GIC_SPI 303 IRQ_TYPE_NONE>,
 188                                      <GIC_SPI 304 IRQ_TYPE_NONE>;
 189                 };
 190         };
 191
 192         soc: soc {
 193                 compatible = "simple-bus";
 194                 #address-cells = <1>;
 195                 #size-cells = <1>;
 196                 ranges = <0 0 0 0xffffffff>;
 197
 198                 #include "ns2-clock.dtsi"
 199
 200                 enet: ethernet@61000000 {
 201                         compatible = "brcm,ns2-amac";
 202                         reg = <0x61000000 0x1000>,
 203                               <0x61090000 0x1000>,
 204                               <0x61030000 0x100>;
 205                         reg-names = "amac_base", "idm_base", "nicpm_base";
 206                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 207                         phy-handle = <&gphy0>;
 208                         phy-mode = "rgmii";
 209                         status = "disabled";
 210                 };
 211
 212                 pdc0: iproc-pdc0@612c0000 {
 213                         compatible = "brcm,iproc-pdc-mbox";
 214                         reg = <0x612c0000 0x445>;  /* PDC FS0 regs */
 215                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 216                         #mbox-cells = <1>;
 217                         brcm,rx-status-len = <32>;
 218                         brcm,use-bcm-hdr;
 219                 };
 220
 221                 pdc1: iproc-pdc1@612e0000 {
 222                         compatible = "brcm,iproc-pdc-mbox";
 223                         reg = <0x612e0000 0x445>;  /* PDC FS1 regs */
 224                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 225                         #mbox-cells = <1>;
 226                         brcm,rx-status-len = <32>;
 227                         brcm,use-bcm-hdr;
 228                 };
 229
 230                 pdc2: iproc-pdc2@61300000 {
 231                         compatible = "brcm,iproc-pdc-mbox";
 232                         reg = <0x61300000 0x445>;  /* PDC FS2 regs */
 233                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 234                         #mbox-cells = <1>;
 235                         brcm,rx-status-len = <32>;
 236                         brcm,use-bcm-hdr;
 237                 };
 238
 239                 pdc3: iproc-pdc3@61320000 {
 240                         compatible = "brcm,iproc-pdc-mbox";
 241                         reg = <0x61320000 0x445>;  /* PDC FS3 regs */
 242                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 243                         #mbox-cells = <1>;
 244                         brcm,rx-status-len = <32>;
 245                         brcm,use-bcm-hdr;
 246                 };
 247
 248                 dma0: dma@61360000 {
 249                         compatible = "arm,pl330", "arm,primecell";
 250                         reg = <0x61360000 0x1000>;
 251                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 253                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 258                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 259                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 260                         #dma-cells = <1>;
 261                         #dma-channels = <8>;
 262                         #dma-requests = <32>;
 263                         clocks = <&iprocslow>;
 264                         clock-names = "apb_pclk";
 265                 };
 266
 267                 smmu: mmu@64000000 {
 268                         compatible = "arm,mmu-500";
 269                         reg = <0x64000000 0x40000>;
 270                         #global-interrupts = <2>;
 271                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 293                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 294                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 297                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
 305                         #iommu-cells = <1>;
 306                 };
 307
 308                 pinctrl: pinctrl@6501d130 {
 309                         compatible = "brcm,ns2-pinmux";
 310                         reg = <0x6501d130 0x08>,
 311                               <0x660a0028 0x04>,
 312                               <0x660009b0 0x40>;
 313                 };
 314
 315                 gpio_aon: gpio@65024800 {
 316                         compatible = "brcm,iproc-gpio";
 317                         reg = <0x65024800 0x50>,
 318                               <0x65024008 0x18>;
 319                         ngpios = <6>;
 320                         #gpio-cells = <2>;
 321                         gpio-controller;
 322                 };
 323
 324                 gic: interrupt-controller@65210000 {
 325                         compatible = "arm,gic-400";
 326                         #interrupt-cells = <3>;
 327                         interrupt-controller;
 328                         reg = <0x65210000 0x1000>,
 329                               <0x65220000 0x1000>,
 330                               <0x65240000 0x2000>,
 331                               <0x65260000 0x1000>;
 332                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 333                                       IRQ_TYPE_LEVEL_HIGH)>;
 334                 };
 335
 336                 cci@65590000 {
 337                         compatible = "arm,cci-400";
 338                         #address-cells = <1>;
 339                         #size-cells = <1>;
 340                         reg = <0x65590000 0x1000>;
 341                         ranges = <0 0x65590000 0x10000>;
 342
 343                         pmu@9000 {
 344                                 compatible = "arm,cci-400-pmu,r1",
 345                                              "arm,cci-400-pmu";
 346                                 reg = <0x9000 0x4000>;
 347                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 348                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 349                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 350                                              <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 351                                              <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 352                                              <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
 353                         };
 354                 };
 355
 356                 pwm: pwm@66010000 {
 357                         compatible = "brcm,iproc-pwm";
 358                         reg = <0x66010000 0x28>;
 359                         clocks = <&osc>;
 360                         #pwm-cells = <3>;
 361                         status = "disabled";
 362                 };
 363
 364                 mdio_mux_iproc: mdio-mux@6602023c {
 365                         compatible = "brcm,mdio-mux-iproc";
 366                         reg = <0x6602023c 0x14>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369
 370                         mdio@0 {
 371                                 reg = <0x0>;
 372                                 #address-cells = <1>;
 373                                 #size-cells = <0>;
 374
 375                                 pci_phy0: pci-phy@0 {
 376                                         compatible = "brcm,ns2-pcie-phy";
 377                                         reg = <0x0>;
 378                                         #phy-cells = <0>;
 379                                         status = "disabled";
 380                                 };
 381                         };
 382
 383                         mdio@7 {
 384                                 reg = <0x7>;
 385                                 #address-cells = <1>;
 386                                 #size-cells = <0>;
 387
 388                                 pci_phy1: pci-phy@0 {
 389                                         compatible = "brcm,ns2-pcie-phy";
 390                                         reg = <0x0>;
 391                                         #phy-cells = <0>;
 392                                         status = "disabled";
 393                                 };
 394                         };
 395
 396                         mdio@10 {
 397                                 reg = <0x10>;
 398                                 #address-cells = <1>;
 399                                 #size-cells = <0>;
 400                         };
 401                 };
 402
 403                 timer0: timer@66030000 {
 404                         compatible = "arm,sp804", "arm,primecell";
 405                         reg = <0x66030000 0x1000>;
 406                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&iprocslow>,
 408                                  <&iprocslow>,
 409                                  <&iprocslow>;
 410                         clock-names = "timer1", "timer2", "apb_pclk";
 411                 };
 412
 413                 timer1: timer@66040000 {
 414                         compatible = "arm,sp804", "arm,primecell";
 415                         reg = <0x66040000 0x1000>;
 416                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&iprocslow>,
 418                                  <&iprocslow>,
 419                                  <&iprocslow>;
 420                         clock-names = "timer1", "timer2", "apb_pclk";
 421                 };
 422
 423                 timer2: timer@66050000 {
 424                         compatible = "arm,sp804", "arm,primecell";
 425                         reg = <0x66050000 0x1000>;
 426                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&iprocslow>,
 428                                  <&iprocslow>,
 429                                  <&iprocslow>;
 430                         clock-names = "timer1", "timer2", "apb_pclk";
 431                 };
 432
 433                 timer3: timer@66060000 {
 434                         compatible = "arm,sp804", "arm,primecell";
 435                         reg = <0x66060000 0x1000>;
 436                         interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&iprocslow>,
 438                                  <&iprocslow>,
 439                                  <&iprocslow>;
 440                         clock-names = "timer1", "timer2", "apb_pclk";
 441                 };
 442
 443                 i2c0: i2c@66080000 {
 444                         compatible = "brcm,iproc-i2c";
 445                         reg = <0x66080000 0x100>;
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
 449                         clock-frequency = <100000>;
 450                         status = "disabled";
 451                 };
 452
 453                 wdt0: watchdog@66090000 {
 454                         compatible = "arm,sp805", "arm,primecell";
 455                         reg = <0x66090000 0x1000>;
 456                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&iprocslow>, <&iprocslow>;
 458                         clock-names = "wdogclk", "apb_pclk";
 459                 };
 460
 461                 gpio_g: gpio@660a0000 {
 462                         compatible = "brcm,iproc-gpio";
 463                         reg = <0x660a0000 0x50>;
 464                         ngpios = <32>;
 465                         #gpio-cells = <2>;
 466                         gpio-controller;
 467                         interrupt-controller;
 468                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
 469                 };
 470
 471                 i2c1: i2c@660b0000 {
 472                         compatible = "brcm,iproc-i2c";
 473                         reg = <0x660b0000 0x100>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
 477                         clock-frequency = <100000>;
 478                         status = "disabled";
 479                 };
 480
 481                 uart0: serial@66100000 {
 482                         compatible = "snps,dw-apb-uart";
 483                         reg = <0x66100000 0x100>;
 484                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
 485                         clocks = <&iprocslow>;
 486                         reg-shift = <2>;
 487                         reg-io-width = <4>;
 488                         status = "disabled";
 489                 };
 490
 491                 uart1: serial@66110000 {
 492                         compatible = "snps,dw-apb-uart";
 493                         reg = <0x66110000 0x100>;
 494                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
 495                         clocks = <&iprocslow>;
 496                         reg-shift = <2>;
 497                         reg-io-width = <4>;
 498                         status = "disabled";
 499                 };
 500
 501                 uart2: serial@66120000 {
 502                         compatible = "snps,dw-apb-uart";
 503                         reg = <0x66120000 0x100>;
 504                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&iprocslow>;
 506                         reg-shift = <2>;
 507                         reg-io-width = <4>;
 508                         status = "disabled";
 509                 };
 510
 511                 uart3: serial@66130000 {
 512                         compatible = "snps,dw-apb-uart";
 513                         reg = <0x66130000 0x100>;
 514                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 515                         reg-shift = <2>;
 516                         reg-io-width = <4>;
 517                         clocks = <&osc>;
 518                         status = "disabled";
 519                 };
 520
 521                 ssp0: ssp@66180000 {
 522                         compatible = "arm,pl022", "arm,primecell";
 523                         reg = <0x66180000 0x1000>;
 524                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&iprocslow>, <&iprocslow>;
 526                         clock-names = "spiclk", "apb_pclk";
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         status = "disabled";
 530                 };
 531
 532                 ssp1: ssp@66190000 {
 533                         compatible = "arm,pl022", "arm,primecell";
 534                         reg = <0x66190000 0x1000>;
 535                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&iprocslow>, <&iprocslow>;
 537                         clock-names = "spiclk", "apb_pclk";
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         status = "disabled";
 541                 };
 542
 543                 hwrng: hwrng@66220000 {
 544                         compatible = "brcm,iproc-rng200";
 545                         reg = <0x66220000 0x28>;
 546                 };
 547
 548                 sata_phy: sata_phy@663f0100 {
 549                         compatible = "brcm,iproc-ns2-sata-phy";
 550                         reg = <0x663f0100 0x1f00>,
 551                               <0x663f004c 0x10>;
 552                         reg-names = "phy", "phy-ctrl";
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555
 556                         sata_phy0: sata-phy@0 {
 557                                 reg = <0>;
 558                                 #phy-cells = <0>;
 559                                 status = "disabled";
 560                         };
 561
 562                         sata_phy1: sata-phy@1 {
 563                                 reg = <1>;
 564                                 #phy-cells = <0>;
 565                                 status = "disabled";
 566                         };
 567                 };
 568
 569                 sata: ahci@663f2000 {
 570                         compatible = "brcm,iproc-ahci", "generic-ahci";
 571                         reg = <0x663f2000 0x1000>;
 572                         reg-names = "ahci";
 573                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 574                         #address-cells = <1>;
 575                         #size-cells = <0>;
 576                         status = "disabled";
 577
 578                         sata0: sata-port@0 {
 579                                 reg = <0>;
 580                                 phys = <&sata_phy0>;
 581                                 phy-names = "sata-phy";
 582                         };
 583
 584                         sata1: sata-port@1 {
 585                                 reg = <1>;
 586                                 phys = <&sata_phy1>;
 587                                 phy-names = "sata-phy";
 588                         };
 589                 };
 590
 591                 sdio0: sdhci@66420000 {
 592                         compatible = "brcm,sdhci-iproc-cygnus";
 593                         reg = <0x66420000 0x100>;
 594                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 595                         bus-width = <8>;
 596                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 597                         status = "disabled";
 598                 };
 599
 600                 sdio1: sdhci@66430000 {
 601                         compatible = "brcm,sdhci-iproc-cygnus";
 602                         reg = <0x66430000 0x100>;
 603                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 604                         bus-width = <8>;
 605                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 606                         status = "disabled";
 607                 };
 608
 609                 nand: nand@66460000 {
 610                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 611                         reg = <0x66460000 0x600>,
 612                               <0x67015408 0x600>,
 613                               <0x66460f00 0x20>;
 614                         reg-names = "nand", "iproc-idm", "iproc-ext";
 615                         interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 616
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619
 620                         brcm,nand-has-wp;
 621                 };
 622
 623                 qspi: spi@66470200 {
 624                         compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
 625                         reg = <0x66470200 0x184>,
 626                                 <0x66470000 0x124>,
 627                                 <0x67017408 0x004>,
 628                                 <0x664703a0 0x01c>;
 629                         reg-names = "mspi", "bspi", "intr_regs",
 630                                 "intr_status_reg";
 631                         interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
 632                         interrupt-names = "spi_l1_intr";
 633                         clocks = <&iprocmed>;
 634                         clock-names = "iprocmed";
 635                         num-cs = <2>;
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                 };
 639
 640         };
 641 };