arch/arm64/include/asm/arch_gicv3.h

   1 /*
   2  * arch/arm64/include/asm/arch_gicv3.h
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #ifndef __ASM_ARCH_GICV3_H
  19 #define __ASM_ARCH_GICV3_H
  20
  21 #include <asm/sysreg.h>
  22
  23 #define ICC_IAR0_EL1                    sys_reg(3, 0, 12, 8, 0)
  24 #define ICC_EOIR0_EL1                   sys_reg(3, 0, 12, 8, 1)
  25 #define ICC_HPPIR0_EL1                  sys_reg(3, 0, 12, 8, 2)
  26 #define ICC_BPR0_EL1                    sys_reg(3, 0, 12, 8, 3)
  27 #define ICC_AP0Rn_EL1(n)                sys_reg(3, 0, 12, 8, 4 | n)
  28 #define ICC_AP1Rn_EL1(n)                sys_reg(3, 0, 12, 9, n)
  29 #define ICC_EOIR1_EL1                   sys_reg(3, 0, 12, 12, 1)
  30 #define ICC_DIR_EL1                     sys_reg(3, 0, 12, 11, 1)
  31 #define ICC_IAR1_EL1                    sys_reg(3, 0, 12, 12, 0)
  32 #define ICC_SGI1R_EL1                   sys_reg(3, 0, 12, 11, 5)
  33 #define ICC_PMR_EL1                     sys_reg(3, 0, 4, 6, 0)
  34 #define ICC_CTLR_EL1                    sys_reg(3, 0, 12, 12, 4)
  35 #define ICC_SRE_EL1                     sys_reg(3, 0, 12, 12, 5)
  36 #define ICC_GRPEN0_EL1                  sys_reg(3, 0, 12, 12, 6)
  37 #define ICC_GRPEN1_EL1                  sys_reg(3, 0, 12, 12, 7)
  38 #define ICC_BPR1_EL1                    sys_reg(3, 0, 12, 12, 3)
  39 #define ICC_HPPIR1_EL1                  sys_reg(3, 0, 12, 12, 2)
  40 #define ICC_SRE_EL2                     sys_reg(3, 4, 12, 9, 5)
  41
  42 /*
  43  * System register definitions
  44  */
  45 #define ICH_VSEIR_EL2                   sys_reg(3, 4, 12, 9, 4)
  46 #define ICH_HCR_EL2                     sys_reg(3, 4, 12, 11, 0)
  47 #define ICH_VTR_EL2                     sys_reg(3, 4, 12, 11, 1)
  48 #define ICH_MISR_EL2                    sys_reg(3, 4, 12, 11, 2)
  49 #define ICH_EISR_EL2                    sys_reg(3, 4, 12, 11, 3)
  50 #define ICH_ELSR_EL2                    sys_reg(3, 4, 12, 11, 5)
  51 #define ICH_VMCR_EL2                    sys_reg(3, 4, 12, 11, 7)
  52
  53 #define __LR0_EL2(x)                    sys_reg(3, 4, 12, 12, x)
  54 #define __LR8_EL2(x)                    sys_reg(3, 4, 12, 13, x)
  55
  56 #define ICH_LR0_EL2                     __LR0_EL2(0)
  57 #define ICH_LR1_EL2                     __LR0_EL2(1)
  58 #define ICH_LR2_EL2                     __LR0_EL2(2)
  59 #define ICH_LR3_EL2                     __LR0_EL2(3)
  60 #define ICH_LR4_EL2                     __LR0_EL2(4)
  61 #define ICH_LR5_EL2                     __LR0_EL2(5)
  62 #define ICH_LR6_EL2                     __LR0_EL2(6)
  63 #define ICH_LR7_EL2                     __LR0_EL2(7)
  64 #define ICH_LR8_EL2                     __LR8_EL2(0)
  65 #define ICH_LR9_EL2                     __LR8_EL2(1)
  66 #define ICH_LR10_EL2                    __LR8_EL2(2)
  67 #define ICH_LR11_EL2                    __LR8_EL2(3)
  68 #define ICH_LR12_EL2                    __LR8_EL2(4)
  69 #define ICH_LR13_EL2                    __LR8_EL2(5)
  70 #define ICH_LR14_EL2                    __LR8_EL2(6)
  71 #define ICH_LR15_EL2                    __LR8_EL2(7)
  72
  73 #define __AP0Rx_EL2(x)                  sys_reg(3, 4, 12, 8, x)
  74 #define ICH_AP0R0_EL2                   __AP0Rx_EL2(0)
  75 #define ICH_AP0R1_EL2                   __AP0Rx_EL2(1)
  76 #define ICH_AP0R2_EL2                   __AP0Rx_EL2(2)
  77 #define ICH_AP0R3_EL2                   __AP0Rx_EL2(3)
  78
  79 #define __AP1Rx_EL2(x)                  sys_reg(3, 4, 12, 9, x)
  80 #define ICH_AP1R0_EL2                   __AP1Rx_EL2(0)
  81 #define ICH_AP1R1_EL2                   __AP1Rx_EL2(1)
  82 #define ICH_AP1R2_EL2                   __AP1Rx_EL2(2)
  83 #define ICH_AP1R3_EL2                   __AP1Rx_EL2(3)
  84
  85 #ifndef __ASSEMBLY__
  86
  87 #include <linux/stringify.h>
  88 #include <asm/barrier.h>
  89 #include <asm/cacheflush.h>
  90
  91 #define read_gicreg                     read_sysreg_s
  92 #define write_gicreg                    write_sysreg_s
  93
  94 /*
  95  * Low-level accessors
  96  *
  97  * These system registers are 32 bits, but we make sure that the compiler
  98  * sets the GP register's most significant bits to 0 with an explicit cast.
  99  */
 100
 101 static inline void gic_write_eoir(u32 irq)
 102 {
 103         write_sysreg_s(irq, ICC_EOIR1_EL1);
 104         isb();
 105 }
 106
 107 static inline void gic_write_dir(u32 irq)
 108 {
 109         write_sysreg_s(irq, ICC_DIR_EL1);
 110         isb();
 111 }
 112
 113 static inline u64 gic_read_iar_common(void)
 114 {
 115         u64 irqstat;
 116
 117         irqstat = read_sysreg_s(ICC_IAR1_EL1);
 118         dsb(sy);
 119         return irqstat;
 120 }
 121
 122 /*
 123  * Cavium ThunderX erratum 23154
 124  *
 125  * The gicv3 of ThunderX requires a modified version for reading the
 126  * IAR status to ensure data synchronization (access to icc_iar1_el1
 127  * is not sync'ed before and after).
 128  */
 129 static inline u64 gic_read_iar_cavium_thunderx(void)
 130 {
 131         u64 irqstat;
 132
 133         nops(8);
 134         irqstat = read_sysreg_s(ICC_IAR1_EL1);
 135         nops(4);
 136         mb();
 137
 138         return irqstat;
 139 }
 140
 141 static inline void gic_write_pmr(u32 val)
 142 {
 143         write_sysreg_s(val, ICC_PMR_EL1);
 144 }
 145
 146 static inline void gic_write_ctlr(u32 val)
 147 {
 148         write_sysreg_s(val, ICC_CTLR_EL1);
 149         isb();
 150 }
 151
 152 static inline void gic_write_grpen1(u32 val)
 153 {
 154         write_sysreg_s(val, ICC_GRPEN1_EL1);
 155         isb();
 156 }
 157
 158 static inline void gic_write_sgi1r(u64 val)
 159 {
 160         write_sysreg_s(val, ICC_SGI1R_EL1);
 161 }
 162
 163 static inline u32 gic_read_sre(void)
 164 {
 165         return read_sysreg_s(ICC_SRE_EL1);
 166 }
 167
 168 static inline void gic_write_sre(u32 val)
 169 {
 170         write_sysreg_s(val, ICC_SRE_EL1);
 171         isb();
 172 }
 173
 174 static inline void gic_write_bpr1(u32 val)
 175 {
 176         asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
 177 }
 178
 179 #define gic_read_typer(c)               readq_relaxed(c)
 180 #define gic_write_irouter(v, c)         writeq_relaxed(v, c)
 181
 182 #define gic_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
 183
 184 #define gits_read_baser(c)              readq_relaxed(c)
 185 #define gits_write_baser(v, c)          writeq_relaxed(v, c)
 186
 187 #define gits_read_cbaser(c)             readq_relaxed(c)
 188 #define gits_write_cbaser(v, c)         writeq_relaxed(v, c)
 189
 190 #define gits_write_cwriter(v, c)        writeq_relaxed(v, c)
 191
 192 #define gicr_read_propbaser(c)          readq_relaxed(c)
 193 #define gicr_write_propbaser(v, c)      writeq_relaxed(v, c)
 194
 195 #define gicr_write_pendbaser(v, c)      writeq_relaxed(v, c)
 196 #define gicr_read_pendbaser(c)          readq_relaxed(c)
 197
 198 #endif /* __ASSEMBLY__ */
 199 #endif /* __ASM_ARCH_GICV3_H */