arch/powerpc/include/asm/opal-api.h

   1 /*
   2  * OPAL API definitions.
   3  *
   4  * Copyright 2011-2015 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_API_H
  13 #define __OPAL_API_H
  14
  15 /****** OPAL APIs ******/
  16
  17 /* Return codes */
  18 #define OPAL_SUCCESS            0
  19 #define OPAL_PARAMETER          -1
  20 #define OPAL_BUSY               -2
  21 #define OPAL_PARTIAL            -3
  22 #define OPAL_CONSTRAINED        -4
  23 #define OPAL_CLOSED             -5
  24 #define OPAL_HARDWARE           -6
  25 #define OPAL_UNSUPPORTED        -7
  26 #define OPAL_PERMISSION         -8
  27 #define OPAL_NO_MEM             -9
  28 #define OPAL_RESOURCE           -10
  29 #define OPAL_INTERNAL_ERROR     -11
  30 #define OPAL_BUSY_EVENT         -12
  31 #define OPAL_HARDWARE_FROZEN    -13
  32 #define OPAL_WRONG_STATE        -14
  33 #define OPAL_ASYNC_COMPLETION   -15
  34 #define OPAL_EMPTY              -16
  35 #define OPAL_I2C_TIMEOUT        -17
  36 #define OPAL_I2C_INVALID_CMD    -18
  37 #define OPAL_I2C_LBUS_PARITY    -19
  38 #define OPAL_I2C_BKEND_OVERRUN  -20
  39 #define OPAL_I2C_BKEND_ACCESS   -21
  40 #define OPAL_I2C_ARBT_LOST      -22
  41 #define OPAL_I2C_NACK_RCVD      -23
  42 #define OPAL_I2C_STOP_ERR       -24
  43
  44 /* API Tokens (in r0) */
  45 #define OPAL_INVALID_CALL                      -1
  46 #define OPAL_TEST                               0
  47 #define OPAL_CONSOLE_WRITE                      1
  48 #define OPAL_CONSOLE_READ                       2
  49 #define OPAL_RTC_READ                           3
  50 #define OPAL_RTC_WRITE                          4
  51 #define OPAL_CEC_POWER_DOWN                     5
  52 #define OPAL_CEC_REBOOT                         6
  53 #define OPAL_READ_NVRAM                         7
  54 #define OPAL_WRITE_NVRAM                        8
  55 #define OPAL_HANDLE_INTERRUPT                   9
  56 #define OPAL_POLL_EVENTS                        10
  57 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  58 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  59 #define OPAL_PCI_CONFIG_READ_BYTE               13
  60 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  61 #define OPAL_PCI_CONFIG_READ_WORD               15
  62 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  64 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  65 #define OPAL_SET_XIVE                           19
  66 #define OPAL_GET_XIVE                           20
  67 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  69 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  70 #define OPAL_PCI_SHPC                           24
  71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  72 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  73 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  74 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  77 #define OPAL_PCI_SET_PE                         31
  78 #define OPAL_PCI_SET_PELTV                      32
  79 #define OPAL_PCI_SET_MVE                        33
  80 #define OPAL_PCI_SET_MVE_ENABLE                 34
  81 #define OPAL_PCI_GET_XIVE_REISSUE               35
  82 #define OPAL_PCI_SET_XIVE_REISSUE               36
  83 #define OPAL_PCI_SET_XIVE_PE                    37
  84 #define OPAL_GET_XIVE_SOURCE                    38
  85 #define OPAL_GET_MSI_32                         39
  86 #define OPAL_GET_MSI_64                         40
  87 #define OPAL_START_CPU                          41
  88 #define OPAL_QUERY_CPU_STATUS                   42
  89 #define OPAL_WRITE_OPPANEL                      43 /* unimplemented */
  90 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
  91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
  92 #define OPAL_PCI_RESET                          49
  93 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
  94 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
  95 #define OPAL_PCI_FENCE_PHB                      52
  96 #define OPAL_PCI_REINIT                         53
  97 #define OPAL_PCI_MASK_PE_ERROR                  54
  98 #define OPAL_SET_SLOT_LED_STATUS                55
  99 #define OPAL_GET_EPOW_STATUS                    56
 100 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 101 #define OPAL_RESERVED1                          58
 102 #define OPAL_RESERVED2                          59
 103 #define OPAL_PCI_NEXT_ERROR                     60
 104 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 105 #define OPAL_PCI_POLL                           62
 106 #define OPAL_PCI_MSI_EOI                        63
 107 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 108 #define OPAL_XSCOM_READ                         65
 109 #define OPAL_XSCOM_WRITE                        66
 110 #define OPAL_LPC_READ                           67
 111 #define OPAL_LPC_WRITE                          68
 112 #define OPAL_RETURN_CPU                         69
 113 #define OPAL_REINIT_CPUS                        70
 114 #define OPAL_ELOG_READ                          71
 115 #define OPAL_ELOG_WRITE                         72
 116 #define OPAL_ELOG_ACK                           73
 117 #define OPAL_ELOG_RESEND                        74
 118 #define OPAL_ELOG_SIZE                          75
 119 #define OPAL_FLASH_VALIDATE                     76
 120 #define OPAL_FLASH_MANAGE                       77
 121 #define OPAL_FLASH_UPDATE                       78
 122 #define OPAL_RESYNC_TIMEBASE                    79
 123 #define OPAL_CHECK_TOKEN                        80
 124 #define OPAL_DUMP_INIT                          81
 125 #define OPAL_DUMP_INFO                          82
 126 #define OPAL_DUMP_READ                          83
 127 #define OPAL_DUMP_ACK                           84
 128 #define OPAL_GET_MSG                            85
 129 #define OPAL_CHECK_ASYNC_COMPLETION             86
 130 #define OPAL_SYNC_HOST_REBOOT                   87
 131 #define OPAL_SENSOR_READ                        88
 132 #define OPAL_GET_PARAM                          89
 133 #define OPAL_SET_PARAM                          90
 134 #define OPAL_DUMP_RESEND                        91
 135 #define OPAL_ELOG_SEND                          92      /* Deprecated */
 136 #define OPAL_PCI_SET_PHB_CAPI_MODE              93
 137 #define OPAL_DUMP_INFO2                         94
 138 #define OPAL_WRITE_OPPANEL_ASYNC                95
 139 #define OPAL_PCI_ERR_INJECT                     96
 140 #define OPAL_PCI_EEH_FREEZE_SET                 97
 141 #define OPAL_HANDLE_HMI                         98
 142 #define OPAL_CONFIG_CPU_IDLE_STATE              99
 143 #define OPAL_SLW_SET_REG                        100
 144 #define OPAL_REGISTER_DUMP_REGION               101
 145 #define OPAL_UNREGISTER_DUMP_REGION             102
 146 #define OPAL_WRITE_TPO                          103
 147 #define OPAL_READ_TPO                           104
 148 #define OPAL_GET_DPO_STATUS                     105
 149 #define OPAL_OLD_I2C_REQUEST                    106     /* Deprecated */
 150 #define OPAL_IPMI_SEND                          107
 151 #define OPAL_IPMI_RECV                          108
 152 #define OPAL_I2C_REQUEST                        109
 153 #define OPAL_FLASH_READ                         110
 154 #define OPAL_FLASH_WRITE                        111
 155 #define OPAL_FLASH_ERASE                        112
 156 #define OPAL_PRD_MSG                            113
 157 #define OPAL_LEDS_GET_INDICATOR                 114
 158 #define OPAL_LEDS_SET_INDICATOR                 115
 159 #define OPAL_CEC_REBOOT2                        116
 160 #define OPAL_CONSOLE_FLUSH                      117
 161 #define OPAL_GET_DEVICE_TREE                    118
 162 #define OPAL_PCI_GET_PRESENCE_STATE             119
 163 #define OPAL_PCI_GET_POWER_STATE                120
 164 #define OPAL_PCI_SET_POWER_STATE                121
 165 #define OPAL_LAST                               121
 166
 167 /* Device tree flags */
 168
 169 /* Flags set in power-mgmt nodes in device tree if
 170  * respective idle states are supported in the platform.
 171  */
 172 #define OPAL_PM_NAP_ENABLED             0x00010000
 173 #define OPAL_PM_SLEEP_ENABLED           0x00020000
 174 #define OPAL_PM_WINKLE_ENABLED          0x00040000
 175 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000 /* with workaround */
 176
 177 /*
 178  * OPAL_CONFIG_CPU_IDLE_STATE parameters
 179  */
 180 #define OPAL_CONFIG_IDLE_FASTSLEEP      1
 181 #define OPAL_CONFIG_IDLE_UNDO           0
 182 #define OPAL_CONFIG_IDLE_APPLY          1
 183
 184 #ifndef __ASSEMBLY__
 185
 186 /* Other enums */
 187 enum OpalFreezeState {
 188         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 189         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 190         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 191         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 192         OPAL_EEH_STOPPED_RESET = 4,
 193         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 194         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 195 };
 196
 197 enum OpalEehFreezeActionToken {
 198         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 199         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 200         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 201
 202         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 203         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 204         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 205 };
 206
 207 enum OpalPciStatusToken {
 208         OPAL_EEH_NO_ERROR       = 0,
 209         OPAL_EEH_IOC_ERROR      = 1,
 210         OPAL_EEH_PHB_ERROR      = 2,
 211         OPAL_EEH_PE_ERROR       = 3,
 212         OPAL_EEH_PE_MMIO_ERROR  = 4,
 213         OPAL_EEH_PE_DMA_ERROR   = 5
 214 };
 215
 216 enum OpalPciErrorSeverity {
 217         OPAL_EEH_SEV_NO_ERROR   = 0,
 218         OPAL_EEH_SEV_IOC_DEAD   = 1,
 219         OPAL_EEH_SEV_PHB_DEAD   = 2,
 220         OPAL_EEH_SEV_PHB_FENCED = 3,
 221         OPAL_EEH_SEV_PE_ER      = 4,
 222         OPAL_EEH_SEV_INF        = 5
 223 };
 224
 225 enum OpalErrinjectType {
 226         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 227         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 228 };
 229
 230 enum OpalErrinjectFunc {
 231         /* IOA bus specific errors */
 232         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 233         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 234         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 235         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 236         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 237         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 238         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 239         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 240         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 241         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 242         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 243         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 244         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 245         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 246         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 247         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 248         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 249         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 250         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 251         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 252 };
 253
 254 enum OpalMmioWindowType {
 255         OPAL_M32_WINDOW_TYPE = 1,
 256         OPAL_M64_WINDOW_TYPE = 2,
 257         OPAL_IO_WINDOW_TYPE  = 3
 258 };
 259
 260 enum OpalExceptionHandler {
 261         OPAL_MACHINE_CHECK_HANDLER          = 1,
 262         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 263         OPAL_SOFTPATCH_HANDLER              = 3
 264 };
 265
 266 enum OpalPendingState {
 267         OPAL_EVENT_OPAL_INTERNAL   = 0x1,
 268         OPAL_EVENT_NVRAM           = 0x2,
 269         OPAL_EVENT_RTC             = 0x4,
 270         OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
 271         OPAL_EVENT_CONSOLE_INPUT   = 0x10,
 272         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
 273         OPAL_EVENT_ERROR_LOG       = 0x40,
 274         OPAL_EVENT_EPOW            = 0x80,
 275         OPAL_EVENT_LED_STATUS      = 0x100,
 276         OPAL_EVENT_PCI_ERROR       = 0x200,
 277         OPAL_EVENT_DUMP_AVAIL      = 0x400,
 278         OPAL_EVENT_MSG_PENDING     = 0x800,
 279 };
 280
 281 enum OpalThreadStatus {
 282         OPAL_THREAD_INACTIVE = 0x0,
 283         OPAL_THREAD_STARTED = 0x1,
 284         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 285 };
 286
 287 enum OpalPciBusCompare {
 288         OpalPciBusAny   = 0,    /* Any bus number match */
 289         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 290         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 291         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 292         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 293         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 294         OpalPciBusAll   = 7,    /* Match bus number exactly */
 295 };
 296
 297 enum OpalDeviceCompare {
 298         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 299         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 300 };
 301
 302 enum OpalFuncCompare {
 303         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 304         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 305 };
 306
 307 enum OpalPeAction {
 308         OPAL_UNMAP_PE = 0,
 309         OPAL_MAP_PE = 1
 310 };
 311
 312 enum OpalPeltvAction {
 313         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 314         OPAL_ADD_PE_TO_DOMAIN = 1
 315 };
 316
 317 enum OpalMveEnableAction {
 318         OPAL_DISABLE_MVE = 0,
 319         OPAL_ENABLE_MVE = 1
 320 };
 321
 322 enum OpalM64Action {
 323         OPAL_DISABLE_M64 = 0,
 324         OPAL_ENABLE_M64_SPLIT = 1,
 325         OPAL_ENABLE_M64_NON_SPLIT = 2
 326 };
 327
 328 enum OpalPciResetScope {
 329         OPAL_RESET_PHB_COMPLETE         = 1,
 330         OPAL_RESET_PCI_LINK             = 2,
 331         OPAL_RESET_PHB_ERROR            = 3,
 332         OPAL_RESET_PCI_HOT              = 4,
 333         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 334         OPAL_RESET_PCI_IODA_TABLE       = 6
 335 };
 336
 337 enum OpalPciReinitScope {
 338         /*
 339          * Note: we chose values that do not overlap
 340          * OpalPciResetScope as OPAL v2 used the same
 341          * enum for both
 342          */
 343         OPAL_REINIT_PCI_DEV = 1000
 344 };
 345
 346 enum OpalPciResetState {
 347         OPAL_DEASSERT_RESET = 0,
 348         OPAL_ASSERT_RESET   = 1
 349 };
 350
 351 enum OpalPciSlotPresence {
 352         OPAL_PCI_SLOT_EMPTY     = 0,
 353         OPAL_PCI_SLOT_PRESENT   = 1
 354 };
 355
 356 enum OpalPciSlotPower {
 357         OPAL_PCI_SLOT_POWER_OFF = 0,
 358         OPAL_PCI_SLOT_POWER_ON  = 1,
 359         OPAL_PCI_SLOT_OFFLINE   = 2,
 360         OPAL_PCI_SLOT_ONLINE    = 3
 361 };
 362
 363 enum OpalSlotLedType {
 364         OPAL_SLOT_LED_TYPE_ID = 0,      /* IDENTIFY LED */
 365         OPAL_SLOT_LED_TYPE_FAULT = 1,   /* FAULT LED */
 366         OPAL_SLOT_LED_TYPE_ATTN = 2,    /* System Attention LED */
 367         OPAL_SLOT_LED_TYPE_MAX = 3
 368 };
 369
 370 enum OpalSlotLedState {
 371         OPAL_SLOT_LED_STATE_OFF = 0,    /* LED is OFF */
 372         OPAL_SLOT_LED_STATE_ON = 1      /* LED is ON */
 373 };
 374
 375 /*
 376  * Address cycle types for LPC accesses. These also correspond
 377  * to the content of the first cell of the "reg" property for
 378  * device nodes on the LPC bus
 379  */
 380 enum OpalLPCAddressType {
 381         OPAL_LPC_MEM    = 0,
 382         OPAL_LPC_IO     = 1,
 383         OPAL_LPC_FW     = 2,
 384 };
 385
 386 enum opal_msg_type {
 387         OPAL_MSG_ASYNC_COMP     = 0,    /* params[0] = token, params[1] = rc,
 388                                          * additional params function-specific
 389                                          */
 390         OPAL_MSG_MEM_ERR        = 1,
 391         OPAL_MSG_EPOW           = 2,
 392         OPAL_MSG_SHUTDOWN       = 3,    /* params[0] = 1 reboot, 0 shutdown */
 393         OPAL_MSG_HMI_EVT        = 4,
 394         OPAL_MSG_DPO            = 5,
 395         OPAL_MSG_PRD            = 6,
 396         OPAL_MSG_OCC            = 7,
 397         OPAL_MSG_TYPE_MAX,
 398 };
 399
 400 struct opal_msg {
 401         __be32 msg_type;
 402         __be32 reserved;
 403         __be64 params[8];
 404 };
 405
 406 /* System parameter permission */
 407 enum OpalSysparamPerm {
 408         OPAL_SYSPARAM_READ  = 0x1,
 409         OPAL_SYSPARAM_WRITE = 0x2,
 410         OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 411 };
 412
 413 enum {
 414         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 415 };
 416
 417 struct opal_ipmi_msg {
 418         uint8_t version;
 419         uint8_t netfn;
 420         uint8_t cmd;
 421         uint8_t data[];
 422 };
 423
 424 /* FSP memory errors handling */
 425 enum OpalMemErr_Version {
 426         OpalMemErr_V1 = 1,
 427 };
 428
 429 enum OpalMemErrType {
 430         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 431         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 432 };
 433
 434 /* Memory Reilience error type */
 435 enum OpalMemErr_ResilErrType {
 436         OPAL_MEM_RESILIENCE_CE          = 0,
 437         OPAL_MEM_RESILIENCE_UE,
 438         OPAL_MEM_RESILIENCE_UE_SCRUB,
 439 };
 440
 441 /* Dynamic Memory Deallocation type */
 442 enum OpalMemErr_DynErrType {
 443         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 444 };
 445
 446 struct OpalMemoryErrorData {
 447         enum OpalMemErr_Version version:8;      /* 0x00 */
 448         enum OpalMemErrType     type:8;         /* 0x01 */
 449         __be16                  flags;          /* 0x02 */
 450         uint8_t                 reserved_1[4];  /* 0x04 */
 451
 452         union {
 453                 /* Memory Resilience corrected/uncorrected error info */
 454                 struct {
 455                         enum OpalMemErr_ResilErrType    resil_err_type:8;
 456                         uint8_t                         reserved_1[7];
 457                         __be64                          physical_address_start;
 458                         __be64                          physical_address_end;
 459                 } resilience;
 460                 /* Dynamic memory deallocation error info */
 461                 struct {
 462                         enum OpalMemErr_DynErrType      dyn_err_type:8;
 463                         uint8_t                         reserved_1[7];
 464                         __be64                          physical_address_start;
 465                         __be64                          physical_address_end;
 466                 } dyn_dealloc;
 467         } u;
 468 };
 469
 470 /* HMI interrupt event */
 471 enum OpalHMI_Version {
 472         OpalHMIEvt_V1 = 1,
 473         OpalHMIEvt_V2 = 2,
 474 };
 475
 476 enum OpalHMI_Severity {
 477         OpalHMI_SEV_NO_ERROR = 0,
 478         OpalHMI_SEV_WARNING = 1,
 479         OpalHMI_SEV_ERROR_SYNC = 2,
 480         OpalHMI_SEV_FATAL = 3,
 481 };
 482
 483 enum OpalHMI_Disposition {
 484         OpalHMI_DISPOSITION_RECOVERED = 0,
 485         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 486 };
 487
 488 enum OpalHMI_ErrType {
 489         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 490         OpalHMI_ERROR_PROC_RECOV_DONE,
 491         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 492         OpalHMI_ERROR_PROC_RECOV_MASKED,
 493         OpalHMI_ERROR_TFAC,
 494         OpalHMI_ERROR_TFMR_PARITY,
 495         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 496         OpalHMI_ERROR_XSCOM_FAIL,
 497         OpalHMI_ERROR_XSCOM_DONE,
 498         OpalHMI_ERROR_SCOM_FIR,
 499         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 500         OpalHMI_ERROR_HYP_RESOURCE,
 501         OpalHMI_ERROR_CAPP_RECOVERY,
 502 };
 503
 504 enum OpalHMI_XstopType {
 505         CHECKSTOP_TYPE_UNKNOWN  =       0,
 506         CHECKSTOP_TYPE_CORE     =       1,
 507         CHECKSTOP_TYPE_NX       =       2,
 508 };
 509
 510 enum OpalHMI_CoreXstopReason {
 511         CORE_CHECKSTOP_IFU_REGFILE              = 0x00000001,
 512         CORE_CHECKSTOP_IFU_LOGIC                = 0x00000002,
 513         CORE_CHECKSTOP_PC_DURING_RECOV          = 0x00000004,
 514         CORE_CHECKSTOP_ISU_REGFILE              = 0x00000008,
 515         CORE_CHECKSTOP_ISU_LOGIC                = 0x00000010,
 516         CORE_CHECKSTOP_FXU_LOGIC                = 0x00000020,
 517         CORE_CHECKSTOP_VSU_LOGIC                = 0x00000040,
 518         CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE   = 0x00000080,
 519         CORE_CHECKSTOP_LSU_REGFILE              = 0x00000100,
 520         CORE_CHECKSTOP_PC_FWD_PROGRESS          = 0x00000200,
 521         CORE_CHECKSTOP_LSU_LOGIC                = 0x00000400,
 522         CORE_CHECKSTOP_PC_LOGIC                 = 0x00000800,
 523         CORE_CHECKSTOP_PC_HYP_RESOURCE          = 0x00001000,
 524         CORE_CHECKSTOP_PC_HANG_RECOV_FAILED     = 0x00002000,
 525         CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED    = 0x00004000,
 526         CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ    = 0x00008000,
 527         CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ      = 0x00010000,
 528 };
 529
 530 enum OpalHMI_NestAccelXstopReason {
 531         NX_CHECKSTOP_SHM_INVAL_STATE_ERR        = 0x00000001,
 532         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1      = 0x00000002,
 533         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2      = 0x00000004,
 534         NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR    = 0x00000008,
 535         NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR    = 0x00000010,
 536         NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR    = 0x00000020,
 537         NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR    = 0x00000040,
 538         NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR    = 0x00000080,
 539         NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR    = 0x00000100,
 540         NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR    = 0x00000200,
 541         NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR    = 0x00000400,
 542         NX_CHECKSTOP_DMA_CRB_UE                 = 0x00000800,
 543         NX_CHECKSTOP_DMA_CRB_SUE                = 0x00001000,
 544         NX_CHECKSTOP_PBI_ISN_UE                 = 0x00002000,
 545 };
 546
 547 struct OpalHMIEvent {
 548         uint8_t         version;        /* 0x00 */
 549         uint8_t         severity;       /* 0x01 */
 550         uint8_t         type;           /* 0x02 */
 551         uint8_t         disposition;    /* 0x03 */
 552         uint8_t         reserved_1[4];  /* 0x04 */
 553
 554         __be64          hmer;
 555         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 556         __be64          tfmr;
 557
 558         /* version 2 and later */
 559         union {
 560                 /*
 561                  * checkstop info (Core/NX).
 562                  * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
 563                  */
 564                 struct {
 565                         uint8_t xstop_type;     /* enum OpalHMI_XstopType */
 566                         uint8_t reserved_1[3];
 567                         __be32  xstop_reason;
 568                         union {
 569                                 __be32 pir;     /* for CHECKSTOP_TYPE_CORE */
 570                                 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
 571                         } u;
 572                 } xstop_error;
 573         } u;
 574 };
 575
 576 enum {
 577         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 578         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 579         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 580         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 581         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 582         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 583         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 584 };
 585
 586 struct OpalIoP7IOCErrorData {
 587         __be16 type;
 588
 589         /* GEM */
 590         __be64 gemXfir;
 591         __be64 gemRfir;
 592         __be64 gemRirqfir;
 593         __be64 gemMask;
 594         __be64 gemRwof;
 595
 596         /* LEM */
 597         __be64 lemFir;
 598         __be64 lemErrMask;
 599         __be64 lemAction0;
 600         __be64 lemAction1;
 601         __be64 lemWof;
 602
 603         union {
 604                 struct OpalIoP7IOCRgcErrorData {
 605                         __be64 rgcStatus;       /* 3E1C10 */
 606                         __be64 rgcLdcp;         /* 3E1C18 */
 607                 }rgc;
 608                 struct OpalIoP7IOCBiErrorData {
 609                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 610                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 611                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 612                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 613
 614                         uint8_t biDownbound;    /* BI Downbound or Upbound */
 615                 }bi;
 616                 struct OpalIoP7IOCCiErrorData {
 617                         __be64 ciPortStatus;    /* 3Dn008 */
 618                         __be64 ciPortLdcp;      /* 3Dn010 */
 619
 620                         uint8_t ciPort;         /* Index of CI port: 0/1 */
 621                 }ci;
 622         };
 623 };
 624
 625 /**
 626  * This structure defines the overlay which will be used to store PHB error
 627  * data upon request.
 628  */
 629 enum {
 630         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 631 };
 632
 633 enum {
 634         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 635         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 636 };
 637
 638 enum {
 639         OPAL_P7IOC_NUM_PEST_REGS = 128,
 640         OPAL_PHB3_NUM_PEST_REGS = 256
 641 };
 642
 643 struct OpalIoPhbErrorCommon {
 644         __be32 version;
 645         __be32 ioType;
 646         __be32 len;
 647 };
 648
 649 struct OpalIoP7IOCPhbErrorData {
 650         struct OpalIoPhbErrorCommon common;
 651
 652         __be32 brdgCtl;
 653
 654         // P7IOC utl regs
 655         __be32 portStatusReg;
 656         __be32 rootCmplxStatus;
 657         __be32 busAgentStatus;
 658
 659         // P7IOC cfg regs
 660         __be32 deviceStatus;
 661         __be32 slotStatus;
 662         __be32 linkStatus;
 663         __be32 devCmdStatus;
 664         __be32 devSecStatus;
 665
 666         // cfg AER regs
 667         __be32 rootErrorStatus;
 668         __be32 uncorrErrorStatus;
 669         __be32 corrErrorStatus;
 670         __be32 tlpHdr1;
 671         __be32 tlpHdr2;
 672         __be32 tlpHdr3;
 673         __be32 tlpHdr4;
 674         __be32 sourceId;
 675
 676         __be32 rsv3;
 677
 678         // Record data about the call to allocate a buffer.
 679         __be64 errorClass;
 680         __be64 correlator;
 681
 682         //P7IOC MMIO Error Regs
 683         __be64 p7iocPlssr;                // n120
 684         __be64 p7iocCsr;                  // n110
 685         __be64 lemFir;                    // nC00
 686         __be64 lemErrorMask;              // nC18
 687         __be64 lemWOF;                    // nC40
 688         __be64 phbErrorStatus;            // nC80
 689         __be64 phbFirstErrorStatus;       // nC88
 690         __be64 phbErrorLog0;              // nCC0
 691         __be64 phbErrorLog1;              // nCC8
 692         __be64 mmioErrorStatus;           // nD00
 693         __be64 mmioFirstErrorStatus;      // nD08
 694         __be64 mmioErrorLog0;             // nD40
 695         __be64 mmioErrorLog1;             // nD48
 696         __be64 dma0ErrorStatus;           // nD80
 697         __be64 dma0FirstErrorStatus;      // nD88
 698         __be64 dma0ErrorLog0;             // nDC0
 699         __be64 dma0ErrorLog1;             // nDC8
 700         __be64 dma1ErrorStatus;           // nE00
 701         __be64 dma1FirstErrorStatus;      // nE08
 702         __be64 dma1ErrorLog0;             // nE40
 703         __be64 dma1ErrorLog1;             // nE48
 704         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 705         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 706 };
 707
 708 struct OpalIoPhb3ErrorData {
 709         struct OpalIoPhbErrorCommon common;
 710
 711         __be32 brdgCtl;
 712
 713         /* PHB3 UTL regs */
 714         __be32 portStatusReg;
 715         __be32 rootCmplxStatus;
 716         __be32 busAgentStatus;
 717
 718         /* PHB3 cfg regs */
 719         __be32 deviceStatus;
 720         __be32 slotStatus;
 721         __be32 linkStatus;
 722         __be32 devCmdStatus;
 723         __be32 devSecStatus;
 724
 725         /* cfg AER regs */
 726         __be32 rootErrorStatus;
 727         __be32 uncorrErrorStatus;
 728         __be32 corrErrorStatus;
 729         __be32 tlpHdr1;
 730         __be32 tlpHdr2;
 731         __be32 tlpHdr3;
 732         __be32 tlpHdr4;
 733         __be32 sourceId;
 734
 735         __be32 rsv3;
 736
 737         /* Record data about the call to allocate a buffer */
 738         __be64 errorClass;
 739         __be64 correlator;
 740
 741         /* PHB3 MMIO Error Regs */
 742         __be64 nFir;                    /* 000 */
 743         __be64 nFirMask;                /* 003 */
 744         __be64 nFirWOF;         /* 008 */
 745         __be64 phbPlssr;                /* 120 */
 746         __be64 phbCsr;          /* 110 */
 747         __be64 lemFir;          /* C00 */
 748         __be64 lemErrorMask;            /* C18 */
 749         __be64 lemWOF;          /* C40 */
 750         __be64 phbErrorStatus;  /* C80 */
 751         __be64 phbFirstErrorStatus;     /* C88 */
 752         __be64 phbErrorLog0;            /* CC0 */
 753         __be64 phbErrorLog1;            /* CC8 */
 754         __be64 mmioErrorStatus; /* D00 */
 755         __be64 mmioFirstErrorStatus;    /* D08 */
 756         __be64 mmioErrorLog0;           /* D40 */
 757         __be64 mmioErrorLog1;           /* D48 */
 758         __be64 dma0ErrorStatus; /* D80 */
 759         __be64 dma0FirstErrorStatus;    /* D88 */
 760         __be64 dma0ErrorLog0;           /* DC0 */
 761         __be64 dma0ErrorLog1;           /* DC8 */
 762         __be64 dma1ErrorStatus; /* E00 */
 763         __be64 dma1FirstErrorStatus;    /* E08 */
 764         __be64 dma1ErrorLog0;           /* E40 */
 765         __be64 dma1ErrorLog1;           /* E48 */
 766         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 767         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 768 };
 769
 770 enum {
 771         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 772         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 773 };
 774
 775 typedef struct oppanel_line {
 776         __be64 line;
 777         __be64 line_len;
 778 } oppanel_line_t;
 779
 780 enum opal_prd_msg_type {
 781         OPAL_PRD_MSG_TYPE_INIT = 0,     /* HBRT --> OPAL */
 782         OPAL_PRD_MSG_TYPE_FINI,         /* HBRT/kernel --> OPAL */
 783         OPAL_PRD_MSG_TYPE_ATTN,         /* HBRT <-- OPAL */
 784         OPAL_PRD_MSG_TYPE_ATTN_ACK,     /* HBRT --> OPAL */
 785         OPAL_PRD_MSG_TYPE_OCC_ERROR,    /* HBRT <-- OPAL */
 786         OPAL_PRD_MSG_TYPE_OCC_RESET,    /* HBRT <-- OPAL */
 787 };
 788
 789 struct opal_prd_msg_header {
 790         uint8_t         type;
 791         uint8_t         pad[1];
 792         __be16          size;
 793 };
 794
 795 struct opal_prd_msg;
 796
 797 #define OCC_RESET                       0
 798 #define OCC_LOAD                        1
 799 #define OCC_THROTTLE                    2
 800 #define OCC_MAX_THROTTLE_STATUS         5
 801
 802 struct opal_occ_msg {
 803         __be64 type;
 804         __be64 chip;
 805         __be64 throttle_status;
 806 };
 807
 808 /*
 809  * SG entries
 810  *
 811  * WARNING: The current implementation requires each entry
 812  * to represent a block that is 4k aligned *and* each block
 813  * size except the last one in the list to be as well.
 814  */
 815 struct opal_sg_entry {
 816         __be64 data;
 817         __be64 length;
 818 };
 819
 820 /*
 821  * Candidate image SG list.
 822  *
 823  * length = VER | length
 824  */
 825 struct opal_sg_list {
 826         __be64 length;
 827         __be64 next;
 828         struct opal_sg_entry entry[];
 829 };
 830
 831 /*
 832  * Dump region ID range usable by the OS
 833  */
 834 #define OPAL_DUMP_REGION_HOST_START             0x80
 835 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 836 #define OPAL_DUMP_REGION_HOST_END               0xFF
 837
 838 /* CAPI modes for PHB */
 839 enum {
 840         OPAL_PHB_CAPI_MODE_PCIE         = 0,
 841         OPAL_PHB_CAPI_MODE_CAPI         = 1,
 842         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
 843         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
 844         OPAL_PHB_CAPI_MODE_DMA          = 4,
 845 };
 846
 847 /* OPAL I2C request */
 848 struct opal_i2c_request {
 849         uint8_t type;
 850 #define OPAL_I2C_RAW_READ       0
 851 #define OPAL_I2C_RAW_WRITE      1
 852 #define OPAL_I2C_SM_READ        2
 853 #define OPAL_I2C_SM_WRITE       3
 854         uint8_t flags;
 855 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
 856         uint8_t subaddr_sz;             /* Max 4 */
 857         uint8_t reserved;
 858         __be16 addr;                    /* 7 or 10 bit address */
 859         __be16 reserved2;
 860         __be32 subaddr;         /* Sub-address if any */
 861         __be32 size;                    /* Data size */
 862         __be64 buffer_ra;               /* Buffer real address */
 863 };
 864
 865 /*
 866  * EPOW status sharing (OPAL and the host)
 867  *
 868  * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
 869  * with individual elements being 16 bits wide to fetch the system
 870  * wide EPOW status. Each element in the buffer will contain the
 871  * EPOW status in it's bit representation for a particular EPOW sub
 872  * class as defined here. So multiple detailed EPOW status bits
 873  * specific for any sub class can be represented in a single buffer
 874  * element as it's bit representation.
 875  */
 876
 877 /* System EPOW type */
 878 enum OpalSysEpow {
 879         OPAL_SYSEPOW_POWER      = 0,    /* Power EPOW */
 880         OPAL_SYSEPOW_TEMP       = 1,    /* Temperature EPOW */
 881         OPAL_SYSEPOW_COOLING    = 2,    /* Cooling EPOW */
 882         OPAL_SYSEPOW_MAX        = 3,    /* Max EPOW categories */
 883 };
 884
 885 /* Power EPOW */
 886 enum OpalSysPower {
 887         OPAL_SYSPOWER_UPS       = 0x0001, /* System on UPS power */
 888         OPAL_SYSPOWER_CHNG      = 0x0002, /* System power config change */
 889         OPAL_SYSPOWER_FAIL      = 0x0004, /* System impending power failure */
 890         OPAL_SYSPOWER_INCL      = 0x0008, /* System incomplete power */
 891 };
 892
 893 /* Temperature EPOW */
 894 enum OpalSysTemp {
 895         OPAL_SYSTEMP_AMB        = 0x0001, /* System over ambient temperature */
 896         OPAL_SYSTEMP_INT        = 0x0002, /* System over internal temperature */
 897         OPAL_SYSTEMP_HMD        = 0x0004, /* System over ambient humidity */
 898 };
 899
 900 /* Cooling EPOW */
 901 enum OpalSysCooling {
 902         OPAL_SYSCOOL_INSF       = 0x0001, /* System insufficient cooling */
 903 };
 904
 905 /* Argument to OPAL_CEC_REBOOT2() */
 906 enum {
 907         OPAL_REBOOT_NORMAL              = 0,
 908         OPAL_REBOOT_PLATFORM_ERROR      = 1,
 909 };
 910
 911 #endif /* __ASSEMBLY__ */
 912
 913 #endif /* __OPAL_API_H */