arch/powerpc/mm/pgtable-radix.c

   1 /*
   2  * Page table handling routines for radix page table.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/sched.h>
  12 #include <linux/memblock.h>
  13 #include <linux/of_fdt.h>
  14
  15 #include <asm/pgtable.h>
  16 #include <asm/pgalloc.h>
  17 #include <asm/dma.h>
  18 #include <asm/machdep.h>
  19 #include <asm/mmu.h>
  20 #include <asm/firmware.h>
  21
  22 #include <trace/events/thp.h>
  23
  24 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
  25                                          unsigned long table_size)
  26 {
  27         unsigned long patb1 = base | table_size | PATB_GR;
  28
  29         partition_tb->patb1 = cpu_to_be64(patb1);
  30         return 0;
  31 }
  32
  33 static __ref void *early_alloc_pgtable(unsigned long size)
  34 {
  35         void *pt;
  36
  37         pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
  38         memset(pt, 0, size);
  39
  40         return pt;
  41 }
  42
  43 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
  44                           pgprot_t flags,
  45                           unsigned int map_page_size)
  46 {
  47         pgd_t *pgdp;
  48         pud_t *pudp;
  49         pmd_t *pmdp;
  50         pte_t *ptep;
  51         /*
  52          * Make sure task size is correct as per the max adddr
  53          */
  54         BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
  55         if (slab_is_available()) {
  56                 pgdp = pgd_offset_k(ea);
  57                 pudp = pud_alloc(&init_mm, pgdp, ea);
  58                 if (!pudp)
  59                         return -ENOMEM;
  60                 if (map_page_size == PUD_SIZE) {
  61                         ptep = (pte_t *)pudp;
  62                         goto set_the_pte;
  63                 }
  64                 pmdp = pmd_alloc(&init_mm, pudp, ea);
  65                 if (!pmdp)
  66                         return -ENOMEM;
  67                 if (map_page_size == PMD_SIZE) {
  68                         ptep = (pte_t *)pudp;
  69                         goto set_the_pte;
  70                 }
  71                 ptep = pte_alloc_kernel(pmdp, ea);
  72                 if (!ptep)
  73                         return -ENOMEM;
  74         } else {
  75                 pgdp = pgd_offset_k(ea);
  76                 if (pgd_none(*pgdp)) {
  77                         pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
  78                         BUG_ON(pudp == NULL);
  79                         pgd_populate(&init_mm, pgdp, pudp);
  80                 }
  81                 pudp = pud_offset(pgdp, ea);
  82                 if (map_page_size == PUD_SIZE) {
  83                         ptep = (pte_t *)pudp;
  84                         goto set_the_pte;
  85                 }
  86                 if (pud_none(*pudp)) {
  87                         pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
  88                         BUG_ON(pmdp == NULL);
  89                         pud_populate(&init_mm, pudp, pmdp);
  90                 }
  91                 pmdp = pmd_offset(pudp, ea);
  92                 if (map_page_size == PMD_SIZE) {
  93                         ptep = (pte_t *)pudp;
  94                         goto set_the_pte;
  95                 }
  96                 if (!pmd_present(*pmdp)) {
  97                         ptep = early_alloc_pgtable(PAGE_SIZE);
  98                         BUG_ON(ptep == NULL);
  99                         pmd_populate_kernel(&init_mm, pmdp, ptep);
 100                 }
 101                 ptep = pte_offset_kernel(pmdp, ea);
 102         }
 103
 104 set_the_pte:
 105         set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
 106         smp_wmb();
 107         return 0;
 108 }
 109
 110 static void __init radix_init_pgtable(void)
 111 {
 112         int loop_count;
 113         u64 base, end, start_addr;
 114         unsigned long rts_field;
 115         struct memblock_region *reg;
 116         unsigned long linear_page_size;
 117
 118         /* We don't support slb for radix */
 119         mmu_slb_size = 0;
 120         /*
 121          * Create the linear mapping, using standard page size for now
 122          */
 123         loop_count = 0;
 124         for_each_memblock(memory, reg) {
 125
 126                 start_addr = reg->base;
 127
 128 redo:
 129                 if (loop_count < 1 && mmu_psize_defs[MMU_PAGE_1G].shift)
 130                         linear_page_size = PUD_SIZE;
 131                 else if (loop_count < 2 && mmu_psize_defs[MMU_PAGE_2M].shift)
 132                         linear_page_size = PMD_SIZE;
 133                 else
 134                         linear_page_size = PAGE_SIZE;
 135
 136                 base = _ALIGN_UP(start_addr, linear_page_size);
 137                 end = _ALIGN_DOWN(reg->base + reg->size, linear_page_size);
 138
 139                 pr_info("Mapping range 0x%lx - 0x%lx with 0x%lx\n",
 140                         (unsigned long)base, (unsigned long)end,
 141                         linear_page_size);
 142
 143                 while (base < end) {
 144                         radix__map_kernel_page((unsigned long)__va(base),
 145                                               base, PAGE_KERNEL_X,
 146                                               linear_page_size);
 147                         base += linear_page_size;
 148                 }
 149                 /*
 150                  * map the rest using lower page size
 151                  */
 152                 if (end < reg->base + reg->size) {
 153                         start_addr = end;
 154                         loop_count++;
 155                         goto redo;
 156                 }
 157         }
 158         /*
 159          * Allocate Partition table and process table for the
 160          * host.
 161          */
 162         BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large.");
 163         process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
 164         /*
 165          * Fill in the process table.
 166          */
 167         rts_field = radix__get_tree_size();
 168         process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
 169         /*
 170          * Fill in the partition table. We are suppose to use effective address
 171          * of process table here. But our linear mapping also enable us to use
 172          * physical address here.
 173          */
 174         register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
 175         pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
 176 }
 177
 178 static void __init radix_init_partition_table(void)
 179 {
 180         unsigned long rts_field, dw0;
 181
 182         mmu_partition_table_init();
 183         rts_field = radix__get_tree_size();
 184         dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
 185         mmu_partition_table_set_entry(0, dw0, 0);
 186
 187         pr_info("Initializing Radix MMU\n");
 188         pr_info("Partition table %p\n", partition_tb);
 189 }
 190
 191 void __init radix_init_native(void)
 192 {
 193         register_process_table = native_register_process_table;
 194 }
 195
 196 static int __init get_idx_from_shift(unsigned int shift)
 197 {
 198         int idx = -1;
 199
 200         switch (shift) {
 201         case 0xc:
 202                 idx = MMU_PAGE_4K;
 203                 break;
 204         case 0x10:
 205                 idx = MMU_PAGE_64K;
 206                 break;
 207         case 0x15:
 208                 idx = MMU_PAGE_2M;
 209                 break;
 210         case 0x1e:
 211                 idx = MMU_PAGE_1G;
 212                 break;
 213         }
 214         return idx;
 215 }
 216
 217 static int __init radix_dt_scan_page_sizes(unsigned long node,
 218                                            const char *uname, int depth,
 219                                            void *data)
 220 {
 221         int size = 0;
 222         int shift, idx;
 223         unsigned int ap;
 224         const __be32 *prop;
 225         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 226
 227         /* We are scanning "cpu" nodes only */
 228         if (type == NULL || strcmp(type, "cpu") != 0)
 229                 return 0;
 230
 231         prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
 232         if (!prop)
 233                 return 0;
 234
 235         pr_info("Page sizes from device-tree:\n");
 236         for (; size >= 4; size -= 4, ++prop) {
 237
 238                 struct mmu_psize_def *def;
 239
 240                 /* top 3 bit is AP encoding */
 241                 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
 242                 ap = be32_to_cpu(prop[0]) >> 29;
 243                 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
 244
 245                 idx = get_idx_from_shift(shift);
 246                 if (idx < 0)
 247                         continue;
 248
 249                 def = &mmu_psize_defs[idx];
 250                 def->shift = shift;
 251                 def->ap  = ap;
 252         }
 253
 254         /* needed ? */
 255         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 256         return 1;
 257 }
 258
 259 void __init radix__early_init_devtree(void)
 260 {
 261         int rc;
 262
 263         /*
 264          * Try to find the available page sizes in the device-tree
 265          */
 266         rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
 267         if (rc != 0)  /* Found */
 268                 goto found;
 269         /*
 270          * let's assume we have page 4k and 64k support
 271          */
 272         mmu_psize_defs[MMU_PAGE_4K].shift = 12;
 273         mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
 274
 275         mmu_psize_defs[MMU_PAGE_64K].shift = 16;
 276         mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
 277 found:
 278 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 279         if (mmu_psize_defs[MMU_PAGE_2M].shift) {
 280                 /*
 281                  * map vmemmap using 2M if available
 282                  */
 283                 mmu_vmemmap_psize = MMU_PAGE_2M;
 284         }
 285 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 286         return;
 287 }
 288
 289 static void update_hid_for_radix(void)
 290 {
 291         unsigned long hid0;
 292         unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
 293
 294         asm volatile("ptesync": : :"memory");
 295         /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
 296         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 297                      : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
 298         /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
 299         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 300                      : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
 301         asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
 302         /*
 303          * now switch the HID
 304          */
 305         hid0  = mfspr(SPRN_HID0);
 306         hid0 |= HID0_POWER9_RADIX;
 307         mtspr(SPRN_HID0, hid0);
 308         asm volatile("isync": : :"memory");
 309
 310         /* Wait for it to happen */
 311         while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
 312                 cpu_relax();
 313 }
 314
 315 static void radix_init_amor(void)
 316 {
 317         /*
 318         * In HV mode, we init AMOR (Authority Mask Override Register) so that
 319         * the hypervisor and guest can setup IAMR (Instruction Authority Mask
 320         * Register), enable key 0 and set it to 1.
 321         *
 322         * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
 323         */
 324         mtspr(SPRN_AMOR, (3ul << 62));
 325 }
 326
 327 static void radix_init_iamr(void)
 328 {
 329         unsigned long iamr;
 330
 331         /*
 332          * The IAMR should set to 0 on DD1.
 333          */
 334         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 335                 iamr = 0;
 336         else
 337                 iamr = (1ul << 62);
 338
 339         /*
 340          * Radix always uses key0 of the IAMR to determine if an access is
 341          * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
 342          * fetch.
 343          */
 344         mtspr(SPRN_IAMR, iamr);
 345 }
 346
 347 void __init radix__early_init_mmu(void)
 348 {
 349         unsigned long lpcr;
 350
 351 #ifdef CONFIG_PPC_64K_PAGES
 352         /* PAGE_SIZE mappings */
 353         mmu_virtual_psize = MMU_PAGE_64K;
 354 #else
 355         mmu_virtual_psize = MMU_PAGE_4K;
 356 #endif
 357
 358 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 359         /* vmemmap mapping */
 360         mmu_vmemmap_psize = mmu_virtual_psize;
 361 #endif
 362         /*
 363          * initialize page table size
 364          */
 365         __pte_index_size = RADIX_PTE_INDEX_SIZE;
 366         __pmd_index_size = RADIX_PMD_INDEX_SIZE;
 367         __pud_index_size = RADIX_PUD_INDEX_SIZE;
 368         __pgd_index_size = RADIX_PGD_INDEX_SIZE;
 369         __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
 370         __pte_table_size = RADIX_PTE_TABLE_SIZE;
 371         __pmd_table_size = RADIX_PMD_TABLE_SIZE;
 372         __pud_table_size = RADIX_PUD_TABLE_SIZE;
 373         __pgd_table_size = RADIX_PGD_TABLE_SIZE;
 374
 375         __pmd_val_bits = RADIX_PMD_VAL_BITS;
 376         __pud_val_bits = RADIX_PUD_VAL_BITS;
 377         __pgd_val_bits = RADIX_PGD_VAL_BITS;
 378
 379         __kernel_virt_start = RADIX_KERN_VIRT_START;
 380         __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
 381         __vmalloc_start = RADIX_VMALLOC_START;
 382         __vmalloc_end = RADIX_VMALLOC_END;
 383         vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
 384         ioremap_bot = IOREMAP_BASE;
 385
 386 #ifdef CONFIG_PCI
 387         pci_io_base = ISA_IO_BASE;
 388 #endif
 389
 390         /*
 391          * For now radix also use the same frag size
 392          */
 393         __pte_frag_nr = H_PTE_FRAG_NR;
 394         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
 395
 396         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 397                 radix_init_native();
 398                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 399                         update_hid_for_radix();
 400                 lpcr = mfspr(SPRN_LPCR);
 401                 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 402                 radix_init_partition_table();
 403                 radix_init_amor();
 404         }
 405
 406         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 407
 408         radix_init_iamr();
 409         radix_init_pgtable();
 410 }
 411
 412 void radix__early_init_mmu_secondary(void)
 413 {
 414         unsigned long lpcr;
 415         /*
 416          * update partition table control register and UPRT
 417          */
 418         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 419
 420                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 421                         update_hid_for_radix();
 422
 423                 lpcr = mfspr(SPRN_LPCR);
 424                 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 425
 426                 mtspr(SPRN_PTCR,
 427                       __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
 428                 radix_init_amor();
 429         }
 430         radix_init_iamr();
 431 }
 432
 433 void radix__mmu_cleanup_all(void)
 434 {
 435         unsigned long lpcr;
 436
 437         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 438                 lpcr = mfspr(SPRN_LPCR);
 439                 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
 440                 mtspr(SPRN_PTCR, 0);
 441                 radix__flush_tlb_all();
 442         }
 443 }
 444
 445 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 446                                 phys_addr_t first_memblock_size)
 447 {
 448         /* We don't currently support the first MEMBLOCK not mapping 0
 449          * physical on those processors
 450          */
 451         BUG_ON(first_memblock_base != 0);
 452         /*
 453          * We limit the allocation that depend on ppc64_rma_size
 454          * to first_memblock_size. We also clamp it to 1GB to
 455          * avoid some funky things such as RTAS bugs.
 456          *
 457          * On radix config we really don't have a limitation
 458          * on real mode access. But keeping it as above works
 459          * well enough.
 460          */
 461         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
 462         /*
 463          * Finally limit subsequent allocations. We really don't want
 464          * to limit the memblock allocations to rma_size. FIXME!! should
 465          * we even limit at all ?
 466          */
 467         memblock_set_current_limit(first_memblock_base + first_memblock_size);
 468 }
 469
 470 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 471 int __meminit radix__vmemmap_create_mapping(unsigned long start,
 472                                       unsigned long page_size,
 473                                       unsigned long phys)
 474 {
 475         /* Create a PTE encoding */
 476         unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
 477
 478         BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
 479         return 0;
 480 }
 481
 482 #ifdef CONFIG_MEMORY_HOTPLUG
 483 void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
 484 {
 485         /* FIXME!! intel does more. We should free page tables mapping vmemmap ? */
 486 }
 487 #endif
 488 #endif
 489
 490 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 491
 492 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
 493                                   pmd_t *pmdp, unsigned long clr,
 494                                   unsigned long set)
 495 {
 496         unsigned long old;
 497
 498 #ifdef CONFIG_DEBUG_VM
 499         WARN_ON(!radix__pmd_trans_huge(*pmdp));
 500         assert_spin_locked(&mm->page_table_lock);
 501 #endif
 502
 503         old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
 504         trace_hugepage_update(addr, old, clr, set);
 505
 506         return old;
 507 }
 508
 509 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
 510                         pmd_t *pmdp)
 511
 512 {
 513         pmd_t pmd;
 514
 515         VM_BUG_ON(address & ~HPAGE_PMD_MASK);
 516         VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
 517         /*
 518          * khugepaged calls this for normal pmd
 519          */
 520         pmd = *pmdp;
 521         pmd_clear(pmdp);
 522         /*FIXME!!  Verify whether we need this kick below */
 523         kick_all_cpus_sync();
 524         flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
 525         return pmd;
 526 }
 527
 528 /*
 529  * For us pgtable_t is pte_t *. Inorder to save the deposisted
 530  * page table, we consider the allocated page table as a list
 531  * head. On withdraw we need to make sure we zero out the used
 532  * list_head memory area.
 533  */
 534 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 535                                  pgtable_t pgtable)
 536 {
 537         struct list_head *lh = (struct list_head *) pgtable;
 538
 539         assert_spin_locked(pmd_lockptr(mm, pmdp));
 540
 541         /* FIFO */
 542         if (!pmd_huge_pte(mm, pmdp))
 543                 INIT_LIST_HEAD(lh);
 544         else
 545                 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
 546         pmd_huge_pte(mm, pmdp) = pgtable;
 547 }
 548
 549 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
 550 {
 551         pte_t *ptep;
 552         pgtable_t pgtable;
 553         struct list_head *lh;
 554
 555         assert_spin_locked(pmd_lockptr(mm, pmdp));
 556
 557         /* FIFO */
 558         pgtable = pmd_huge_pte(mm, pmdp);
 559         lh = (struct list_head *) pgtable;
 560         if (list_empty(lh))
 561                 pmd_huge_pte(mm, pmdp) = NULL;
 562         else {
 563                 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
 564                 list_del(lh);
 565         }
 566         ptep = (pte_t *) pgtable;
 567         *ptep = __pte(0);
 568         ptep++;
 569         *ptep = __pte(0);
 570         return pgtable;
 571 }
 572
 573
 574 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
 575                                unsigned long addr, pmd_t *pmdp)
 576 {
 577         pmd_t old_pmd;
 578         unsigned long old;
 579
 580         old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
 581         old_pmd = __pmd(old);
 582         /*
 583          * Serialize against find_linux_pte_or_hugepte which does lock-less
 584          * lookup in page tables with local interrupts disabled. For huge pages
 585          * it casts pmd_t to pte_t. Since format of pte_t is different from
 586          * pmd_t we want to prevent transit from pmd pointing to page table
 587          * to pmd pointing to huge page (and back) while interrupts are disabled.
 588          * We clear pmd to possibly replace it with page table pointer in
 589          * different code paths. So make sure we wait for the parallel
 590          * find_linux_pte_or_hugepage to finish.
 591          */
 592         kick_all_cpus_sync();
 593         return old_pmd;
 594 }
 595
 596 int radix__has_transparent_hugepage(void)
 597 {
 598         /* For radix 2M at PMD level means thp */
 599         if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
 600                 return 1;
 601         return 0;
 602 }
 603 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */