arch/powerpc/mm/tlb-radix.c

   1 /*
   2  * TLB flush routines for radix kernels.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/mm.h>
  13 #include <linux/hugetlb.h>
  14 #include <linux/memblock.h>
  15 #include <asm/ppc-opcode.h>
  16
  17 #include <asm/tlb.h>
  18 #include <asm/tlbflush.h>
  19
  20 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
  21
  22 #define RIC_FLUSH_TLB 0
  23 #define RIC_FLUSH_PWC 1
  24 #define RIC_FLUSH_ALL 2
  25
  26 static inline void __tlbiel_pid(unsigned long pid, int set,
  27                                 unsigned long ric)
  28 {
  29         unsigned long rb,rs,prs,r;
  30
  31         rb = PPC_BIT(53); /* IS = 1 */
  32         rb |= set << PPC_BITLSHIFT(51);
  33         rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
  34         prs = 1; /* process scoped */
  35         r = 1;   /* raidx format */
  36
  37         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  38                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  39 }
  40
  41 /*
  42  * We use 128 set in radix mode and 256 set in hpt mode.
  43  */
  44 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
  45 {
  46         int set;
  47
  48         asm volatile("ptesync": : :"memory");
  49
  50         /*
  51          * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
  52          * also flush the entire Page Walk Cache.
  53          */
  54         __tlbiel_pid(pid, 0, ric);
  55
  56         if (ric == RIC_FLUSH_ALL)
  57                 /* For the remaining sets, just flush the TLB */
  58                 ric = RIC_FLUSH_TLB;
  59
  60         for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
  61                 __tlbiel_pid(pid, set, ric);
  62
  63         asm volatile("ptesync": : :"memory");
  64         asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
  65 }
  66
  67 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
  68 {
  69         unsigned long rb,rs,prs,r;
  70
  71         rb = PPC_BIT(53); /* IS = 1 */
  72         rs = pid << PPC_BITLSHIFT(31);
  73         prs = 1; /* process scoped */
  74         r = 1;   /* raidx format */
  75
  76         asm volatile("ptesync": : :"memory");
  77         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
  78                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  79         asm volatile("eieio; tlbsync; ptesync": : :"memory");
  80 }
  81
  82 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
  83                               unsigned long ap, unsigned long ric)
  84 {
  85         unsigned long rb,rs,prs,r;
  86
  87         rb = va & ~(PPC_BITMASK(52, 63));
  88         rb |= ap << PPC_BITLSHIFT(58);
  89         rs = pid << PPC_BITLSHIFT(31);
  90         prs = 1; /* process scoped */
  91         r = 1;   /* raidx format */
  92
  93         asm volatile("ptesync": : :"memory");
  94         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  95                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  96         asm volatile("ptesync": : :"memory");
  97 }
  98
  99 static inline void _tlbie_va(unsigned long va, unsigned long pid,
 100                              unsigned long ap, unsigned long ric)
 101 {
 102         unsigned long rb,rs,prs,r;
 103
 104         rb = va & ~(PPC_BITMASK(52, 63));
 105         rb |= ap << PPC_BITLSHIFT(58);
 106         rs = pid << PPC_BITLSHIFT(31);
 107         prs = 1; /* process scoped */
 108         r = 1;   /* raidx format */
 109
 110         asm volatile("ptesync": : :"memory");
 111         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 112                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 113         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 114 }
 115
 116 /*
 117  * Base TLB flushing operations:
 118  *
 119  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 120  *  - flush_tlb_page(vma, vmaddr) flushes one page
 121  *  - flush_tlb_range(vma, start, end) flushes a range of pages
 122  *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 123  *
 124  *  - local_* variants of page and mm only apply to the current
 125  *    processor
 126  */
 127 void radix__local_flush_tlb_mm(struct mm_struct *mm)
 128 {
 129         unsigned long pid;
 130
 131         preempt_disable();
 132         pid = mm->context.id;
 133         if (pid != MMU_NO_CONTEXT)
 134                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 135         preempt_enable();
 136 }
 137 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
 138
 139 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 140 {
 141         unsigned long pid;
 142         struct mm_struct *mm = tlb->mm;
 143         /*
 144          * If we are doing a full mm flush, we will do a tlb flush
 145          * with RIC_FLUSH_ALL later.
 146          */
 147         if (tlb->fullmm)
 148                 return;
 149
 150         preempt_disable();
 151
 152         pid = mm->context.id;
 153         if (pid != MMU_NO_CONTEXT)
 154                 _tlbiel_pid(pid, RIC_FLUSH_PWC);
 155
 156         preempt_enable();
 157 }
 158 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
 159
 160 void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
 161                                        int psize)
 162 {
 163         unsigned long pid;
 164         unsigned long ap = mmu_get_ap(psize);
 165
 166         preempt_disable();
 167         pid = mm ? mm->context.id : 0;
 168         if (pid != MMU_NO_CONTEXT)
 169                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 170         preempt_enable();
 171 }
 172
 173 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 174 {
 175 #ifdef CONFIG_HUGETLB_PAGE
 176         /* need the return fix for nohash.c */
 177         if (vma && is_vm_hugetlb_page(vma))
 178                 return __local_flush_hugetlb_page(vma, vmaddr);
 179 #endif
 180         radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
 181                                           mmu_virtual_psize);
 182 }
 183 EXPORT_SYMBOL(radix__local_flush_tlb_page);
 184
 185 #ifdef CONFIG_SMP
 186 void radix__flush_tlb_mm(struct mm_struct *mm)
 187 {
 188         unsigned long pid;
 189
 190         preempt_disable();
 191         pid = mm->context.id;
 192         if (unlikely(pid == MMU_NO_CONTEXT))
 193                 goto no_context;
 194
 195         if (!mm_is_thread_local(mm)) {
 196                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 197
 198                 if (lock_tlbie)
 199                         raw_spin_lock(&native_tlbie_lock);
 200                 _tlbie_pid(pid, RIC_FLUSH_ALL);
 201                 if (lock_tlbie)
 202                         raw_spin_unlock(&native_tlbie_lock);
 203         } else
 204                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 205 no_context:
 206         preempt_enable();
 207 }
 208 EXPORT_SYMBOL(radix__flush_tlb_mm);
 209
 210 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 211 {
 212         unsigned long pid;
 213         struct mm_struct *mm = tlb->mm;
 214
 215         /*
 216          * If we are doing a full mm flush, we will do a tlb flush
 217          * with RIC_FLUSH_ALL later.
 218          */
 219         if (tlb->fullmm)
 220                 return;
 221         preempt_disable();
 222
 223         pid = mm->context.id;
 224         if (unlikely(pid == MMU_NO_CONTEXT))
 225                 goto no_context;
 226
 227         if (!mm_is_thread_local(mm)) {
 228                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 229
 230                 if (lock_tlbie)
 231                         raw_spin_lock(&native_tlbie_lock);
 232                 _tlbie_pid(pid, RIC_FLUSH_PWC);
 233                 if (lock_tlbie)
 234                         raw_spin_unlock(&native_tlbie_lock);
 235         } else
 236                 _tlbiel_pid(pid, RIC_FLUSH_PWC);
 237 no_context:
 238         preempt_enable();
 239 }
 240 EXPORT_SYMBOL(radix__flush_tlb_pwc);
 241
 242 void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
 243                                  int psize)
 244 {
 245         unsigned long pid;
 246         unsigned long ap = mmu_get_ap(psize);
 247
 248         preempt_disable();
 249         pid = mm ? mm->context.id : 0;
 250         if (unlikely(pid == MMU_NO_CONTEXT))
 251                 goto bail;
 252         if (!mm_is_thread_local(mm)) {
 253                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 254
 255                 if (lock_tlbie)
 256                         raw_spin_lock(&native_tlbie_lock);
 257                 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 258                 if (lock_tlbie)
 259                         raw_spin_unlock(&native_tlbie_lock);
 260         } else
 261                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 262 bail:
 263         preempt_enable();
 264 }
 265
 266 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 267 {
 268 #ifdef CONFIG_HUGETLB_PAGE
 269         if (vma && is_vm_hugetlb_page(vma))
 270                 return flush_hugetlb_page(vma, vmaddr);
 271 #endif
 272         radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
 273                                     mmu_virtual_psize);
 274 }
 275 EXPORT_SYMBOL(radix__flush_tlb_page);
 276
 277 #endif /* CONFIG_SMP */
 278
 279 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
 280 {
 281         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 282
 283         if (lock_tlbie)
 284                 raw_spin_lock(&native_tlbie_lock);
 285         _tlbie_pid(0, RIC_FLUSH_ALL);
 286         if (lock_tlbie)
 287                 raw_spin_unlock(&native_tlbie_lock);
 288 }
 289 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
 290
 291 /*
 292  * Currently, for range flushing, we just do a full mm flush. Because
 293  * we use this in code path where we don' track the page size.
 294  */
 295 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 296                      unsigned long end)
 297
 298 {
 299         struct mm_struct *mm = vma->vm_mm;
 300         radix__flush_tlb_mm(mm);
 301 }
 302 EXPORT_SYMBOL(radix__flush_tlb_range);
 303
 304 static int radix_get_mmu_psize(int page_size)
 305 {
 306         int psize;
 307
 308         if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
 309                 psize = mmu_virtual_psize;
 310         else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
 311                 psize = MMU_PAGE_2M;
 312         else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
 313                 psize = MMU_PAGE_1G;
 314         else
 315                 return -1;
 316         return psize;
 317 }
 318
 319 void radix__tlb_flush(struct mmu_gather *tlb)
 320 {
 321         int psize = 0;
 322         struct mm_struct *mm = tlb->mm;
 323         int page_size = tlb->page_size;
 324
 325         psize = radix_get_mmu_psize(page_size);
 326         /*
 327          * if page size is not something we understand, do a full mm flush
 328          */
 329         if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
 330                 radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
 331         else
 332                 radix__flush_tlb_mm(mm);
 333 }
 334
 335 #define TLB_FLUSH_ALL -1UL
 336 /*
 337  * Number of pages above which we will do a bcast tlbie. Just a
 338  * number at this point copied from x86
 339  */
 340 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
 341
 342 void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
 343                                   unsigned long end, int psize)
 344 {
 345         unsigned long pid;
 346         unsigned long addr;
 347         int local = mm_is_thread_local(mm);
 348         unsigned long ap = mmu_get_ap(psize);
 349         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 350         unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
 351
 352
 353         preempt_disable();
 354         pid = mm ? mm->context.id : 0;
 355         if (unlikely(pid == MMU_NO_CONTEXT))
 356                 goto err_out;
 357
 358         if (end == TLB_FLUSH_ALL ||
 359             (end - start) > tlb_single_page_flush_ceiling * page_size) {
 360                 if (local)
 361                         _tlbiel_pid(pid, RIC_FLUSH_TLB);
 362                 else
 363                         _tlbie_pid(pid, RIC_FLUSH_TLB);
 364                 goto err_out;
 365         }
 366         for (addr = start; addr < end; addr += page_size) {
 367
 368                 if (local)
 369                         _tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
 370                 else {
 371                         if (lock_tlbie)
 372                                 raw_spin_lock(&native_tlbie_lock);
 373                         _tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
 374                         if (lock_tlbie)
 375                                 raw_spin_unlock(&native_tlbie_lock);
 376                 }
 377         }
 378 err_out:
 379         preempt_enable();
 380 }
 381
 382 void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
 383                               unsigned long page_size)
 384 {
 385         unsigned long rb,rs,prs,r;
 386         unsigned long ap;
 387         unsigned long ric = RIC_FLUSH_TLB;
 388
 389         ap = mmu_get_ap(radix_get_mmu_psize(page_size));
 390         rb = gpa & ~(PPC_BITMASK(52, 63));
 391         rb |= ap << PPC_BITLSHIFT(58);
 392         rs = lpid & ((1UL << 32) - 1);
 393         prs = 0; /* process scoped */
 394         r = 1;   /* raidx format */
 395
 396         asm volatile("ptesync": : :"memory");
 397         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 398                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 399         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 400 }
 401 EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
 402
 403 void radix__flush_tlb_lpid(unsigned long lpid)
 404 {
 405         unsigned long rb,rs,prs,r;
 406         unsigned long ric = RIC_FLUSH_ALL;
 407
 408         rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
 409         rs = lpid & ((1UL << 32) - 1);
 410         prs = 0; /* partition scoped */
 411         r = 1;   /* raidx format */
 412
 413         asm volatile("ptesync": : :"memory");
 414         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 415                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 416         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 417 }
 418 EXPORT_SYMBOL(radix__flush_tlb_lpid);
 419
 420 void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
 421                                 unsigned long start, unsigned long end)
 422 {
 423         radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
 424 }
 425 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
 426
 427 void radix__flush_tlb_all(void)
 428 {
 429         unsigned long rb,prs,r,rs;
 430         unsigned long ric = RIC_FLUSH_ALL;
 431
 432         rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
 433         prs = 0; /* partition scoped */
 434         r = 1;   /* raidx format */
 435         rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
 436
 437         asm volatile("ptesync": : :"memory");
 438         /*
 439          * now flush guest entries by passing PRS = 1 and LPID != 0
 440          */
 441         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 442                      : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
 443         /*
 444          * now flush host entires by passing PRS = 0 and LPID == 0
 445          */
 446         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 447                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
 448         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 449 }
 450
 451 void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
 452                                  unsigned long address)
 453 {
 454         /*
 455          * We track page size in pte only for DD1, So we can
 456          * call this only on DD1.
 457          */
 458         if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 459                 VM_WARN_ON(1);
 460                 return;
 461         }
 462
 463         if (old_pte & _PAGE_LARGE)
 464                 radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
 465         else
 466                 radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
 467 }