2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
30 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
38 #include <asm/iommu.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
46 #include <misc/cxl-base.h>
51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
56 #define POWERNV_IOMMU_MAX_LEVELS 5
58 static const char * const pnv_phb_names
[] = { "IODA1", "IODA2", "NPU" };
59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table
*tbl
);
61 void pe_level_printk(const struct pnv_ioda_pe
*pe
, const char *level
,
73 if (pe
->flags
& PNV_IODA_PE_DEV
)
74 strlcpy(pfix
, dev_name(&pe
->pdev
->dev
), sizeof(pfix
));
75 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
76 sprintf(pfix
, "%04x:%02x ",
77 pci_domain_nr(pe
->pbus
), pe
->pbus
->number
);
79 else if (pe
->flags
& PNV_IODA_PE_VF
)
80 sprintf(pfix
, "%04x:%02x:%2x.%d",
81 pci_domain_nr(pe
->parent_dev
->bus
),
82 (pe
->rid
& 0xff00) >> 8,
83 PCI_SLOT(pe
->rid
), PCI_FUNC(pe
->rid
));
84 #endif /* CONFIG_PCI_IOV*/
86 printk("%spci %s: [PE# %.2x] %pV",
87 level
, pfix
, pe
->pe_number
, &vaf
);
92 static bool pnv_iommu_bypass_disabled __read_mostly
;
94 static int __init
iommu_setup(char *str
)
100 if (!strncmp(str
, "nobypass", 8)) {
101 pnv_iommu_bypass_disabled
= true;
102 pr_info("PowerNV: IOMMU bypass window disabled.\n");
105 str
+= strcspn(str
, ",");
112 early_param("iommu", iommu_setup
);
114 static inline bool pnv_pci_is_m64(struct pnv_phb
*phb
, struct resource
*r
)
117 * WARNING: We cannot rely on the resource flags. The Linux PCI
118 * allocation code sometimes decides to put a 64-bit prefetchable
119 * BAR in the 32-bit window, so we have to compare the addresses.
121 * For simplicity we only test resource start.
123 return (r
->start
>= phb
->ioda
.m64_base
&&
124 r
->start
< (phb
->ioda
.m64_base
+ phb
->ioda
.m64_size
));
127 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags
)
129 unsigned long flags
= (IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
);
131 return (resource_flags
& flags
) == flags
;
134 static struct pnv_ioda_pe
*pnv_ioda_init_pe(struct pnv_phb
*phb
, int pe_no
)
138 phb
->ioda
.pe_array
[pe_no
].phb
= phb
;
139 phb
->ioda
.pe_array
[pe_no
].pe_number
= pe_no
;
142 * Clear the PE frozen state as it might be put into frozen state
143 * in the last PCI remove path. It's not harmful to do so when the
144 * PE is already in unfrozen state.
146 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
, pe_no
,
147 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
148 if (rc
!= OPAL_SUCCESS
&& rc
!= OPAL_UNSUPPORTED
)
149 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
150 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
152 return &phb
->ioda
.pe_array
[pe_no
];
155 static void pnv_ioda_reserve_pe(struct pnv_phb
*phb
, int pe_no
)
157 if (!(pe_no
>= 0 && pe_no
< phb
->ioda
.total_pe_num
)) {
158 pr_warn("%s: Invalid PE %x on PHB#%x\n",
159 __func__
, pe_no
, phb
->hose
->global_number
);
163 if (test_and_set_bit(pe_no
, phb
->ioda
.pe_alloc
))
164 pr_debug("%s: PE %x was reserved on PHB#%x\n",
165 __func__
, pe_no
, phb
->hose
->global_number
);
167 pnv_ioda_init_pe(phb
, pe_no
);
170 static struct pnv_ioda_pe
*pnv_ioda_alloc_pe(struct pnv_phb
*phb
)
174 for (pe
= phb
->ioda
.total_pe_num
- 1; pe
>= 0; pe
--) {
175 if (!test_and_set_bit(pe
, phb
->ioda
.pe_alloc
))
176 return pnv_ioda_init_pe(phb
, pe
);
182 static void pnv_ioda_free_pe(struct pnv_ioda_pe
*pe
)
184 struct pnv_phb
*phb
= pe
->phb
;
185 unsigned int pe_num
= pe
->pe_number
;
189 memset(pe
, 0, sizeof(struct pnv_ioda_pe
));
190 clear_bit(pe_num
, phb
->ioda
.pe_alloc
);
193 /* The default M64 BAR is shared by all PEs */
194 static int pnv_ioda2_init_m64(struct pnv_phb
*phb
)
200 /* Configure the default M64 BAR */
201 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
202 OPAL_M64_WINDOW_TYPE
,
203 phb
->ioda
.m64_bar_idx
,
207 if (rc
!= OPAL_SUCCESS
) {
208 desc
= "configuring";
212 /* Enable the default M64 BAR */
213 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
214 OPAL_M64_WINDOW_TYPE
,
215 phb
->ioda
.m64_bar_idx
,
216 OPAL_ENABLE_M64_SPLIT
);
217 if (rc
!= OPAL_SUCCESS
) {
223 * Exclude the segments for reserved and root bus PE, which
224 * are first or last two PEs.
226 r
= &phb
->hose
->mem_resources
[1];
227 if (phb
->ioda
.reserved_pe_idx
== 0)
228 r
->start
+= (2 * phb
->ioda
.m64_segsize
);
229 else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1))
230 r
->end
-= (2 * phb
->ioda
.m64_segsize
);
232 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
233 phb
->ioda
.reserved_pe_idx
);
238 pr_warn(" Failure %lld %s M64 BAR#%d\n",
239 rc
, desc
, phb
->ioda
.m64_bar_idx
);
240 opal_pci_phb_mmio_enable(phb
->opal_id
,
241 OPAL_M64_WINDOW_TYPE
,
242 phb
->ioda
.m64_bar_idx
,
247 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev
*pdev
,
248 unsigned long *pe_bitmap
)
250 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
251 struct pnv_phb
*phb
= hose
->private_data
;
253 resource_size_t base
, sgsz
, start
, end
;
256 base
= phb
->ioda
.m64_base
;
257 sgsz
= phb
->ioda
.m64_segsize
;
258 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
259 r
= &pdev
->resource
[i
];
260 if (!r
->parent
|| !pnv_pci_is_m64(phb
, r
))
263 start
= _ALIGN_DOWN(r
->start
- base
, sgsz
);
264 end
= _ALIGN_UP(r
->end
- base
, sgsz
);
265 for (segno
= start
/ sgsz
; segno
< end
/ sgsz
; segno
++) {
267 set_bit(segno
, pe_bitmap
);
269 pnv_ioda_reserve_pe(phb
, segno
);
274 static int pnv_ioda1_init_m64(struct pnv_phb
*phb
)
280 * There are 16 M64 BARs, each of which has 8 segments. So
281 * there are as many M64 segments as the maximum number of
284 for (index
= 0; index
< PNV_IODA1_M64_NUM
; index
++) {
285 unsigned long base
, segsz
= phb
->ioda
.m64_segsize
;
288 base
= phb
->ioda
.m64_base
+
289 index
* PNV_IODA1_M64_SEGS
* segsz
;
290 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
291 OPAL_M64_WINDOW_TYPE
, index
, base
, 0,
292 PNV_IODA1_M64_SEGS
* segsz
);
293 if (rc
!= OPAL_SUCCESS
) {
294 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
295 rc
, phb
->hose
->global_number
, index
);
299 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
300 OPAL_M64_WINDOW_TYPE
, index
,
301 OPAL_ENABLE_M64_SPLIT
);
302 if (rc
!= OPAL_SUCCESS
) {
303 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
304 rc
, phb
->hose
->global_number
, index
);
310 * Exclude the segments for reserved and root bus PE, which
311 * are first or last two PEs.
313 r
= &phb
->hose
->mem_resources
[1];
314 if (phb
->ioda
.reserved_pe_idx
== 0)
315 r
->start
+= (2 * phb
->ioda
.m64_segsize
);
316 else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1))
317 r
->end
-= (2 * phb
->ioda
.m64_segsize
);
319 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
320 phb
->ioda
.reserved_pe_idx
, phb
->hose
->global_number
);
325 for ( ; index
>= 0; index
--)
326 opal_pci_phb_mmio_enable(phb
->opal_id
,
327 OPAL_M64_WINDOW_TYPE
, index
, OPAL_DISABLE_M64
);
332 static void pnv_ioda_reserve_m64_pe(struct pci_bus
*bus
,
333 unsigned long *pe_bitmap
,
336 struct pci_dev
*pdev
;
338 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
339 pnv_ioda_reserve_dev_m64_pe(pdev
, pe_bitmap
);
341 if (all
&& pdev
->subordinate
)
342 pnv_ioda_reserve_m64_pe(pdev
->subordinate
,
347 static struct pnv_ioda_pe
*pnv_ioda_pick_m64_pe(struct pci_bus
*bus
, bool all
)
349 struct pci_controller
*hose
= pci_bus_to_host(bus
);
350 struct pnv_phb
*phb
= hose
->private_data
;
351 struct pnv_ioda_pe
*master_pe
, *pe
;
352 unsigned long size
, *pe_alloc
;
355 /* Root bus shouldn't use M64 */
356 if (pci_is_root_bus(bus
))
359 /* Allocate bitmap */
360 size
= _ALIGN_UP(phb
->ioda
.total_pe_num
/ 8, sizeof(unsigned long));
361 pe_alloc
= kzalloc(size
, GFP_KERNEL
);
363 pr_warn("%s: Out of memory !\n",
368 /* Figure out reserved PE numbers by the PE */
369 pnv_ioda_reserve_m64_pe(bus
, pe_alloc
, all
);
372 * the current bus might not own M64 window and that's all
373 * contributed by its child buses. For the case, we needn't
374 * pick M64 dependent PE#.
376 if (bitmap_empty(pe_alloc
, phb
->ioda
.total_pe_num
)) {
382 * Figure out the master PE and put all slave PEs to master
383 * PE's list to form compound PE.
387 while ((i
= find_next_bit(pe_alloc
, phb
->ioda
.total_pe_num
, i
+ 1)) <
388 phb
->ioda
.total_pe_num
) {
389 pe
= &phb
->ioda
.pe_array
[i
];
391 phb
->ioda
.m64_segmap
[pe
->pe_number
] = pe
->pe_number
;
393 pe
->flags
|= PNV_IODA_PE_MASTER
;
394 INIT_LIST_HEAD(&pe
->slaves
);
397 pe
->flags
|= PNV_IODA_PE_SLAVE
;
398 pe
->master
= master_pe
;
399 list_add_tail(&pe
->list
, &master_pe
->slaves
);
403 * P7IOC supports M64DT, which helps mapping M64 segment
404 * to one particular PE#. However, PHB3 has fixed mapping
405 * between M64 segment and PE#. In order to have same logic
406 * for P7IOC and PHB3, we enforce fixed mapping between M64
407 * segment and PE# on P7IOC.
409 if (phb
->type
== PNV_PHB_IODA1
) {
412 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
413 pe
->pe_number
, OPAL_M64_WINDOW_TYPE
,
414 pe
->pe_number
/ PNV_IODA1_M64_SEGS
,
415 pe
->pe_number
% PNV_IODA1_M64_SEGS
);
416 if (rc
!= OPAL_SUCCESS
)
417 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
418 __func__
, rc
, phb
->hose
->global_number
,
427 static void __init
pnv_ioda_parse_m64_window(struct pnv_phb
*phb
)
429 struct pci_controller
*hose
= phb
->hose
;
430 struct device_node
*dn
= hose
->dn
;
431 struct resource
*res
;
436 if (phb
->type
!= PNV_PHB_IODA1
&& phb
->type
!= PNV_PHB_IODA2
) {
437 pr_info(" Not support M64 window\n");
441 if (!firmware_has_feature(FW_FEATURE_OPAL
)) {
442 pr_info(" Firmware too old to support M64 window\n");
446 r
= of_get_property(dn
, "ibm,opal-m64-window", NULL
);
448 pr_info(" No <ibm,opal-m64-window> on %s\n",
454 * Find the available M64 BAR range and pickup the last one for
455 * covering the whole 64-bits space. We support only one range.
457 if (of_property_read_u32_array(dn
, "ibm,opal-available-m64-ranges",
459 /* In absence of the property, assume 0..15 */
463 /* We only support 64 bits in our allocator */
464 if (m64_range
[1] > 63) {
465 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
466 __func__
, m64_range
[1], phb
->hose
->global_number
);
469 /* Empty range, no m64 */
470 if (m64_range
[1] <= m64_range
[0]) {
471 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
472 __func__
, phb
->hose
->global_number
);
476 /* Configure M64 informations */
477 res
= &hose
->mem_resources
[1];
478 res
->name
= dn
->full_name
;
479 res
->start
= of_translate_address(dn
, r
+ 2);
480 res
->end
= res
->start
+ of_read_number(r
+ 4, 2) - 1;
481 res
->flags
= (IORESOURCE_MEM
| IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
);
482 pci_addr
= of_read_number(r
, 2);
483 hose
->mem_offset
[1] = res
->start
- pci_addr
;
485 phb
->ioda
.m64_size
= resource_size(res
);
486 phb
->ioda
.m64_segsize
= phb
->ioda
.m64_size
/ phb
->ioda
.total_pe_num
;
487 phb
->ioda
.m64_base
= pci_addr
;
489 /* This lines up nicely with the display from processing OF ranges */
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
491 res
->start
, res
->end
, pci_addr
, m64_range
[0],
492 m64_range
[0] + m64_range
[1] - 1);
494 /* Mark all M64 used up by default */
495 phb
->ioda
.m64_bar_alloc
= (unsigned long)-1;
497 /* Use last M64 BAR to cover M64 window */
499 phb
->ioda
.m64_bar_idx
= m64_range
[0] + m64_range
[1];
501 pr_info(" Using M64 #%d as default window\n", phb
->ioda
.m64_bar_idx
);
503 /* Mark remaining ones free */
504 for (i
= m64_range
[0]; i
< m64_range
[1]; i
++)
505 clear_bit(i
, &phb
->ioda
.m64_bar_alloc
);
508 * Setup init functions for M64 based on IODA version, IODA3 uses
511 if (phb
->type
== PNV_PHB_IODA1
)
512 phb
->init_m64
= pnv_ioda1_init_m64
;
514 phb
->init_m64
= pnv_ioda2_init_m64
;
515 phb
->reserve_m64_pe
= pnv_ioda_reserve_m64_pe
;
516 phb
->pick_m64_pe
= pnv_ioda_pick_m64_pe
;
519 static void pnv_ioda_freeze_pe(struct pnv_phb
*phb
, int pe_no
)
521 struct pnv_ioda_pe
*pe
= &phb
->ioda
.pe_array
[pe_no
];
522 struct pnv_ioda_pe
*slave
;
525 /* Fetch master PE */
526 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
528 if (WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
)))
531 pe_no
= pe
->pe_number
;
534 /* Freeze master PE */
535 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
537 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
538 if (rc
!= OPAL_SUCCESS
) {
539 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
540 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
544 /* Freeze slave PEs */
545 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
548 list_for_each_entry(slave
, &pe
->slaves
, list
) {
549 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
551 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
552 if (rc
!= OPAL_SUCCESS
)
553 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
554 __func__
, rc
, phb
->hose
->global_number
,
559 static int pnv_ioda_unfreeze_pe(struct pnv_phb
*phb
, int pe_no
, int opt
)
561 struct pnv_ioda_pe
*pe
, *slave
;
565 pe
= &phb
->ioda
.pe_array
[pe_no
];
566 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
568 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
569 pe_no
= pe
->pe_number
;
572 /* Clear frozen state for master PE */
573 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
, pe_no
, opt
);
574 if (rc
!= OPAL_SUCCESS
) {
575 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
576 __func__
, rc
, opt
, phb
->hose
->global_number
, pe_no
);
580 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
583 /* Clear frozen state for slave PEs */
584 list_for_each_entry(slave
, &pe
->slaves
, list
) {
585 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
,
588 if (rc
!= OPAL_SUCCESS
) {
589 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
590 __func__
, rc
, opt
, phb
->hose
->global_number
,
599 static int pnv_ioda_get_pe_state(struct pnv_phb
*phb
, int pe_no
)
601 struct pnv_ioda_pe
*slave
, *pe
;
606 /* Sanity check on PE number */
607 if (pe_no
< 0 || pe_no
>= phb
->ioda
.total_pe_num
)
608 return OPAL_EEH_STOPPED_PERM_UNAVAIL
;
611 * Fetch the master PE and the PE instance might be
612 * not initialized yet.
614 pe
= &phb
->ioda
.pe_array
[pe_no
];
615 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
617 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
618 pe_no
= pe
->pe_number
;
621 /* Check the master PE */
622 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
, pe_no
,
623 &state
, &pcierr
, NULL
);
624 if (rc
!= OPAL_SUCCESS
) {
625 pr_warn("%s: Failure %lld getting "
626 "PHB#%x-PE#%x state\n",
628 phb
->hose
->global_number
, pe_no
);
629 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
632 /* Check the slave PE */
633 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
636 list_for_each_entry(slave
, &pe
->slaves
, list
) {
637 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
,
642 if (rc
!= OPAL_SUCCESS
) {
643 pr_warn("%s: Failure %lld getting "
644 "PHB#%x-PE#%x state\n",
646 phb
->hose
->global_number
, slave
->pe_number
);
647 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
651 * Override the result based on the ascending
661 /* Currently those 2 are only used when MSIs are enabled, this will change
662 * but in the meantime, we need to protect them to avoid warnings
664 #ifdef CONFIG_PCI_MSI
665 struct pnv_ioda_pe
*pnv_ioda_get_pe(struct pci_dev
*dev
)
667 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
668 struct pnv_phb
*phb
= hose
->private_data
;
669 struct pci_dn
*pdn
= pci_get_pdn(dev
);
673 if (pdn
->pe_number
== IODA_INVALID_PE
)
675 return &phb
->ioda
.pe_array
[pdn
->pe_number
];
677 #endif /* CONFIG_PCI_MSI */
679 static int pnv_ioda_set_one_peltv(struct pnv_phb
*phb
,
680 struct pnv_ioda_pe
*parent
,
681 struct pnv_ioda_pe
*child
,
684 const char *desc
= is_add
? "adding" : "removing";
685 uint8_t op
= is_add
? OPAL_ADD_PE_TO_DOMAIN
:
686 OPAL_REMOVE_PE_FROM_DOMAIN
;
687 struct pnv_ioda_pe
*slave
;
690 /* Parent PE affects child PE */
691 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
692 child
->pe_number
, op
);
693 if (rc
!= OPAL_SUCCESS
) {
694 pe_warn(child
, "OPAL error %ld %s to parent PELTV\n",
699 if (!(child
->flags
& PNV_IODA_PE_MASTER
))
702 /* Compound case: parent PE affects slave PEs */
703 list_for_each_entry(slave
, &child
->slaves
, list
) {
704 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
705 slave
->pe_number
, op
);
706 if (rc
!= OPAL_SUCCESS
) {
707 pe_warn(slave
, "OPAL error %ld %s to parent PELTV\n",
716 static int pnv_ioda_set_peltv(struct pnv_phb
*phb
,
717 struct pnv_ioda_pe
*pe
,
720 struct pnv_ioda_pe
*slave
;
721 struct pci_dev
*pdev
= NULL
;
725 * Clear PE frozen state. If it's master PE, we need
726 * clear slave PE frozen state as well.
729 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
730 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
731 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
732 list_for_each_entry(slave
, &pe
->slaves
, list
)
733 opal_pci_eeh_freeze_clear(phb
->opal_id
,
735 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
740 * Associate PE in PELT. We need add the PE into the
741 * corresponding PELT-V as well. Otherwise, the error
742 * originated from the PE might contribute to other
745 ret
= pnv_ioda_set_one_peltv(phb
, pe
, pe
, is_add
);
749 /* For compound PEs, any one affects all of them */
750 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
751 list_for_each_entry(slave
, &pe
->slaves
, list
) {
752 ret
= pnv_ioda_set_one_peltv(phb
, slave
, pe
, is_add
);
758 if (pe
->flags
& (PNV_IODA_PE_BUS_ALL
| PNV_IODA_PE_BUS
))
759 pdev
= pe
->pbus
->self
;
760 else if (pe
->flags
& PNV_IODA_PE_DEV
)
761 pdev
= pe
->pdev
->bus
->self
;
762 #ifdef CONFIG_PCI_IOV
763 else if (pe
->flags
& PNV_IODA_PE_VF
)
764 pdev
= pe
->parent_dev
;
765 #endif /* CONFIG_PCI_IOV */
767 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
768 struct pnv_ioda_pe
*parent
;
770 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
771 parent
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
772 ret
= pnv_ioda_set_one_peltv(phb
, parent
, pe
, is_add
);
777 pdev
= pdev
->bus
->self
;
783 static int pnv_ioda_deconfigure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
785 struct pci_dev
*parent
;
786 uint8_t bcomp
, dcomp
, fcomp
;
790 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
794 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
795 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
796 parent
= pe
->pbus
->self
;
797 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
798 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
803 case 1: bcomp
= OpalPciBusAll
; break;
804 case 2: bcomp
= OpalPciBus7Bits
; break;
805 case 4: bcomp
= OpalPciBus6Bits
; break;
806 case 8: bcomp
= OpalPciBus5Bits
; break;
807 case 16: bcomp
= OpalPciBus4Bits
; break;
808 case 32: bcomp
= OpalPciBus3Bits
; break;
810 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
812 /* Do an exact match only */
813 bcomp
= OpalPciBusAll
;
815 rid_end
= pe
->rid
+ (count
<< 8);
817 #ifdef CONFIG_PCI_IOV
818 if (pe
->flags
& PNV_IODA_PE_VF
)
819 parent
= pe
->parent_dev
;
822 parent
= pe
->pdev
->bus
->self
;
823 bcomp
= OpalPciBusAll
;
824 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
825 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
826 rid_end
= pe
->rid
+ 1;
829 /* Clear the reverse map */
830 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
831 phb
->ioda
.pe_rmap
[rid
] = IODA_INVALID_PE
;
833 /* Release from all parents PELT-V */
835 struct pci_dn
*pdn
= pci_get_pdn(parent
);
836 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
837 rc
= opal_pci_set_peltv(phb
->opal_id
, pdn
->pe_number
,
838 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
839 /* XXX What to do in case of error ? */
841 parent
= parent
->bus
->self
;
844 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
845 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
847 /* Disassociate PE in PELT */
848 rc
= opal_pci_set_peltv(phb
->opal_id
, pe
->pe_number
,
849 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
851 pe_warn(pe
, "OPAL error %ld remove self from PELTV\n", rc
);
852 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
853 bcomp
, dcomp
, fcomp
, OPAL_UNMAP_PE
);
855 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
859 #ifdef CONFIG_PCI_IOV
860 pe
->parent_dev
= NULL
;
866 static int pnv_ioda_configure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
868 struct pci_dev
*parent
;
869 uint8_t bcomp
, dcomp
, fcomp
;
870 long rc
, rid_end
, rid
;
872 /* Bus validation ? */
876 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
877 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
878 parent
= pe
->pbus
->self
;
879 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
880 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
885 case 1: bcomp
= OpalPciBusAll
; break;
886 case 2: bcomp
= OpalPciBus7Bits
; break;
887 case 4: bcomp
= OpalPciBus6Bits
; break;
888 case 8: bcomp
= OpalPciBus5Bits
; break;
889 case 16: bcomp
= OpalPciBus4Bits
; break;
890 case 32: bcomp
= OpalPciBus3Bits
; break;
892 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
894 /* Do an exact match only */
895 bcomp
= OpalPciBusAll
;
897 rid_end
= pe
->rid
+ (count
<< 8);
899 #ifdef CONFIG_PCI_IOV
900 if (pe
->flags
& PNV_IODA_PE_VF
)
901 parent
= pe
->parent_dev
;
903 #endif /* CONFIG_PCI_IOV */
904 parent
= pe
->pdev
->bus
->self
;
905 bcomp
= OpalPciBusAll
;
906 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
907 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
908 rid_end
= pe
->rid
+ 1;
912 * Associate PE in PELT. We need add the PE into the
913 * corresponding PELT-V as well. Otherwise, the error
914 * originated from the PE might contribute to other
917 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
918 bcomp
, dcomp
, fcomp
, OPAL_MAP_PE
);
920 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
925 * Configure PELTV. NPUs don't have a PELTV table so skip
926 * configuration on them.
928 if (phb
->type
!= PNV_PHB_NPU
)
929 pnv_ioda_set_peltv(phb
, pe
, true);
931 /* Setup reverse map */
932 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
933 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
935 /* Setup one MVTs on IODA1 */
936 if (phb
->type
!= PNV_PHB_IODA1
) {
941 pe
->mve_number
= pe
->pe_number
;
942 rc
= opal_pci_set_mve(phb
->opal_id
, pe
->mve_number
, pe
->pe_number
);
943 if (rc
!= OPAL_SUCCESS
) {
944 pe_err(pe
, "OPAL error %ld setting up MVE %x\n",
948 rc
= opal_pci_set_mve_enable(phb
->opal_id
,
949 pe
->mve_number
, OPAL_ENABLE_MVE
);
951 pe_err(pe
, "OPAL error %ld enabling MVE %x\n",
961 #ifdef CONFIG_PCI_IOV
962 static int pnv_pci_vf_resource_shift(struct pci_dev
*dev
, int offset
)
964 struct pci_dn
*pdn
= pci_get_pdn(dev
);
966 struct resource
*res
, res2
;
967 resource_size_t size
;
974 * "offset" is in VFs. The M64 windows are sized so that when they
975 * are segmented, each segment is the same size as the IOV BAR.
976 * Each segment is in a separate PE, and the high order bits of the
977 * address are the PE number. Therefore, each VF's BAR is in a
978 * separate PE, and changing the IOV BAR start address changes the
979 * range of PEs the VFs are in.
981 num_vfs
= pdn
->num_vfs
;
982 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
983 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
984 if (!res
->flags
|| !res
->parent
)
988 * The actual IOV BAR range is determined by the start address
989 * and the actual size for num_vfs VFs BAR. This check is to
990 * make sure that after shifting, the range will not overlap
991 * with another device.
993 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
994 res2
.flags
= res
->flags
;
995 res2
.start
= res
->start
+ (size
* offset
);
996 res2
.end
= res2
.start
+ (size
* num_vfs
) - 1;
998 if (res2
.end
> res
->end
) {
999 dev_err(&dev
->dev
, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1000 i
, &res2
, res
, num_vfs
, offset
);
1006 * After doing so, there would be a "hole" in the /proc/iomem when
1007 * offset is a positive value. It looks like the device return some
1008 * mmio back to the system, which actually no one could use it.
1010 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
1011 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
1012 if (!res
->flags
|| !res
->parent
)
1015 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
1017 res
->start
+= size
* offset
;
1019 dev_info(&dev
->dev
, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1020 i
, &res2
, res
, (offset
> 0) ? "En" : "Dis",
1022 pci_update_resource(dev
, i
+ PCI_IOV_RESOURCES
);
1026 #endif /* CONFIG_PCI_IOV */
1028 static struct pnv_ioda_pe
*pnv_ioda_setup_dev_PE(struct pci_dev
*dev
)
1030 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1031 struct pnv_phb
*phb
= hose
->private_data
;
1032 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1033 struct pnv_ioda_pe
*pe
;
1036 pr_err("%s: Device tree node not associated properly\n",
1040 if (pdn
->pe_number
!= IODA_INVALID_PE
)
1043 pe
= pnv_ioda_alloc_pe(phb
);
1045 pr_warning("%s: Not enough PE# available, disabling device\n",
1050 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1051 * pointer in the PE data structure, both should be destroyed at the
1052 * same time. However, this needs to be looked at more closely again
1053 * once we actually start removing things (Hotplug, SR-IOV, ...)
1055 * At some point we want to remove the PDN completely anyways
1059 pdn
->pe_number
= pe
->pe_number
;
1060 pe
->flags
= PNV_IODA_PE_DEV
;
1063 pe
->mve_number
= -1;
1064 pe
->rid
= dev
->bus
->number
<< 8 | pdn
->devfn
;
1066 pe_info(pe
, "Associated device to PE\n");
1068 if (pnv_ioda_configure_pe(phb
, pe
)) {
1069 /* XXX What do we do here ? */
1070 pnv_ioda_free_pe(pe
);
1071 pdn
->pe_number
= IODA_INVALID_PE
;
1077 /* Put PE to the list */
1078 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1083 static void pnv_ioda_setup_same_PE(struct pci_bus
*bus
, struct pnv_ioda_pe
*pe
)
1085 struct pci_dev
*dev
;
1087 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1088 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1091 pr_warn("%s: No device node associated with device !\n",
1097 * In partial hotplug case, the PCI device might be still
1098 * associated with the PE and needn't attach it to the PE
1101 if (pdn
->pe_number
!= IODA_INVALID_PE
)
1106 pdn
->pe_number
= pe
->pe_number
;
1107 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1108 pnv_ioda_setup_same_PE(dev
->subordinate
, pe
);
1113 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1114 * single PCI bus. Another one that contains the primary PCI bus and its
1115 * subordinate PCI devices and buses. The second type of PE is normally
1116 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1118 static struct pnv_ioda_pe
*pnv_ioda_setup_bus_PE(struct pci_bus
*bus
, bool all
)
1120 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1121 struct pnv_phb
*phb
= hose
->private_data
;
1122 struct pnv_ioda_pe
*pe
= NULL
;
1123 unsigned int pe_num
;
1126 * In partial hotplug case, the PE instance might be still alive.
1127 * We should reuse it instead of allocating a new one.
1129 pe_num
= phb
->ioda
.pe_rmap
[bus
->number
<< 8];
1130 if (pe_num
!= IODA_INVALID_PE
) {
1131 pe
= &phb
->ioda
.pe_array
[pe_num
];
1132 pnv_ioda_setup_same_PE(bus
, pe
);
1136 /* PE number for root bus should have been reserved */
1137 if (pci_is_root_bus(bus
) &&
1138 phb
->ioda
.root_pe_idx
!= IODA_INVALID_PE
)
1139 pe
= &phb
->ioda
.pe_array
[phb
->ioda
.root_pe_idx
];
1141 /* Check if PE is determined by M64 */
1142 if (!pe
&& phb
->pick_m64_pe
)
1143 pe
= phb
->pick_m64_pe(bus
, all
);
1145 /* The PE number isn't pinned by M64 */
1147 pe
= pnv_ioda_alloc_pe(phb
);
1150 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1151 __func__
, pci_domain_nr(bus
), bus
->number
);
1155 pe
->flags
|= (all
? PNV_IODA_PE_BUS_ALL
: PNV_IODA_PE_BUS
);
1158 pe
->mve_number
= -1;
1159 pe
->rid
= bus
->busn_res
.start
<< 8;
1162 pe_info(pe
, "Secondary bus %d..%d associated with PE#%x\n",
1163 bus
->busn_res
.start
, bus
->busn_res
.end
, pe
->pe_number
);
1165 pe_info(pe
, "Secondary bus %d associated with PE#%x\n",
1166 bus
->busn_res
.start
, pe
->pe_number
);
1168 if (pnv_ioda_configure_pe(phb
, pe
)) {
1169 /* XXX What do we do here ? */
1170 pnv_ioda_free_pe(pe
);
1175 /* Associate it with all child devices */
1176 pnv_ioda_setup_same_PE(bus
, pe
);
1178 /* Put PE to the list */
1179 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1184 static struct pnv_ioda_pe
*pnv_ioda_setup_npu_PE(struct pci_dev
*npu_pdev
)
1186 int pe_num
, found_pe
= false, rc
;
1188 struct pnv_ioda_pe
*pe
;
1189 struct pci_dev
*gpu_pdev
;
1190 struct pci_dn
*npu_pdn
;
1191 struct pci_controller
*hose
= pci_bus_to_host(npu_pdev
->bus
);
1192 struct pnv_phb
*phb
= hose
->private_data
;
1195 * Due to a hardware errata PE#0 on the NPU is reserved for
1196 * error handling. This means we only have three PEs remaining
1197 * which need to be assigned to four links, implying some
1198 * links must share PEs.
1200 * To achieve this we assign PEs such that NPUs linking the
1201 * same GPU get assigned the same PE.
1203 gpu_pdev
= pnv_pci_get_gpu_dev(npu_pdev
);
1204 for (pe_num
= 0; pe_num
< phb
->ioda
.total_pe_num
; pe_num
++) {
1205 pe
= &phb
->ioda
.pe_array
[pe_num
];
1209 if (pnv_pci_get_gpu_dev(pe
->pdev
) == gpu_pdev
) {
1211 * This device has the same peer GPU so should
1212 * be assigned the same PE as the existing
1215 dev_info(&npu_pdev
->dev
,
1216 "Associating to existing PE %x\n", pe_num
);
1217 pci_dev_get(npu_pdev
);
1218 npu_pdn
= pci_get_pdn(npu_pdev
);
1219 rid
= npu_pdev
->bus
->number
<< 8 | npu_pdn
->devfn
;
1220 npu_pdn
->pcidev
= npu_pdev
;
1221 npu_pdn
->pe_number
= pe_num
;
1222 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
1224 /* Map the PE to this link */
1225 rc
= opal_pci_set_pe(phb
->opal_id
, pe_num
, rid
,
1227 OPAL_COMPARE_RID_DEVICE_NUMBER
,
1228 OPAL_COMPARE_RID_FUNCTION_NUMBER
,
1230 WARN_ON(rc
!= OPAL_SUCCESS
);
1238 * Could not find an existing PE so allocate a new
1241 return pnv_ioda_setup_dev_PE(npu_pdev
);
1246 static void pnv_ioda_setup_npu_PEs(struct pci_bus
*bus
)
1248 struct pci_dev
*pdev
;
1250 list_for_each_entry(pdev
, &bus
->devices
, bus_list
)
1251 pnv_ioda_setup_npu_PE(pdev
);
1254 static void pnv_pci_ioda_setup_PEs(void)
1256 struct pci_controller
*hose
, *tmp
;
1257 struct pnv_phb
*phb
;
1259 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1260 phb
= hose
->private_data
;
1261 if (phb
->type
== PNV_PHB_NPU
) {
1262 /* PE#0 is needed for error reporting */
1263 pnv_ioda_reserve_pe(phb
, 0);
1264 pnv_ioda_setup_npu_PEs(hose
->bus
);
1265 if (phb
->model
== PNV_PHB_MODEL_NPU2
)
1271 #ifdef CONFIG_PCI_IOV
1272 static int pnv_pci_vf_release_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1274 struct pci_bus
*bus
;
1275 struct pci_controller
*hose
;
1276 struct pnv_phb
*phb
;
1282 hose
= pci_bus_to_host(bus
);
1283 phb
= hose
->private_data
;
1284 pdn
= pci_get_pdn(pdev
);
1286 if (pdn
->m64_single_mode
)
1291 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++)
1292 for (j
= 0; j
< m64_bars
; j
++) {
1293 if (pdn
->m64_map
[j
][i
] == IODA_INVALID_M64
)
1295 opal_pci_phb_mmio_enable(phb
->opal_id
,
1296 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 0);
1297 clear_bit(pdn
->m64_map
[j
][i
], &phb
->ioda
.m64_bar_alloc
);
1298 pdn
->m64_map
[j
][i
] = IODA_INVALID_M64
;
1301 kfree(pdn
->m64_map
);
1305 static int pnv_pci_vf_assign_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1307 struct pci_bus
*bus
;
1308 struct pci_controller
*hose
;
1309 struct pnv_phb
*phb
;
1312 struct resource
*res
;
1316 resource_size_t size
, start
;
1321 hose
= pci_bus_to_host(bus
);
1322 phb
= hose
->private_data
;
1323 pdn
= pci_get_pdn(pdev
);
1324 total_vfs
= pci_sriov_get_totalvfs(pdev
);
1326 if (pdn
->m64_single_mode
)
1331 pdn
->m64_map
= kmalloc(sizeof(*pdn
->m64_map
) * m64_bars
, GFP_KERNEL
);
1334 /* Initialize the m64_map to IODA_INVALID_M64 */
1335 for (i
= 0; i
< m64_bars
; i
++)
1336 for (j
= 0; j
< PCI_SRIOV_NUM_BARS
; j
++)
1337 pdn
->m64_map
[i
][j
] = IODA_INVALID_M64
;
1340 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
1341 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
1342 if (!res
->flags
|| !res
->parent
)
1345 for (j
= 0; j
< m64_bars
; j
++) {
1347 win
= find_next_zero_bit(&phb
->ioda
.m64_bar_alloc
,
1348 phb
->ioda
.m64_bar_idx
+ 1, 0);
1350 if (win
>= phb
->ioda
.m64_bar_idx
+ 1)
1352 } while (test_and_set_bit(win
, &phb
->ioda
.m64_bar_alloc
));
1354 pdn
->m64_map
[j
][i
] = win
;
1356 if (pdn
->m64_single_mode
) {
1357 size
= pci_iov_resource_size(pdev
,
1358 PCI_IOV_RESOURCES
+ i
);
1359 start
= res
->start
+ size
* j
;
1361 size
= resource_size(res
);
1365 /* Map the M64 here */
1366 if (pdn
->m64_single_mode
) {
1367 pe_num
= pdn
->pe_num_map
[j
];
1368 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
1369 pe_num
, OPAL_M64_WINDOW_TYPE
,
1370 pdn
->m64_map
[j
][i
], 0);
1373 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
1374 OPAL_M64_WINDOW_TYPE
,
1381 if (rc
!= OPAL_SUCCESS
) {
1382 dev_err(&pdev
->dev
, "Failed to map M64 window #%d: %lld\n",
1387 if (pdn
->m64_single_mode
)
1388 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1389 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 2);
1391 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1392 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 1);
1394 if (rc
!= OPAL_SUCCESS
) {
1395 dev_err(&pdev
->dev
, "Failed to enable M64 window #%d: %llx\n",
1404 pnv_pci_vf_release_m64(pdev
, num_vfs
);
1408 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
1410 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
);
1412 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev
*dev
, struct pnv_ioda_pe
*pe
)
1414 struct iommu_table
*tbl
;
1417 tbl
= pe
->table_group
.tables
[0];
1418 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
1420 pe_warn(pe
, "OPAL error %ld release DMA window\n", rc
);
1422 pnv_pci_ioda2_set_bypass(pe
, false);
1423 if (pe
->table_group
.group
) {
1424 iommu_group_put(pe
->table_group
.group
);
1425 BUG_ON(pe
->table_group
.group
);
1427 pnv_pci_ioda2_table_free_pages(tbl
);
1428 iommu_free_table(tbl
, of_node_full_name(dev
->dev
.of_node
));
1431 static void pnv_ioda_release_vf_PE(struct pci_dev
*pdev
)
1433 struct pci_bus
*bus
;
1434 struct pci_controller
*hose
;
1435 struct pnv_phb
*phb
;
1436 struct pnv_ioda_pe
*pe
, *pe_n
;
1440 hose
= pci_bus_to_host(bus
);
1441 phb
= hose
->private_data
;
1442 pdn
= pci_get_pdn(pdev
);
1444 if (!pdev
->is_physfn
)
1447 list_for_each_entry_safe(pe
, pe_n
, &phb
->ioda
.pe_list
, list
) {
1448 if (pe
->parent_dev
!= pdev
)
1451 pnv_pci_ioda2_release_dma_pe(pdev
, pe
);
1453 /* Remove from list */
1454 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1455 list_del(&pe
->list
);
1456 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1458 pnv_ioda_deconfigure_pe(phb
, pe
);
1460 pnv_ioda_free_pe(pe
);
1464 void pnv_pci_sriov_disable(struct pci_dev
*pdev
)
1466 struct pci_bus
*bus
;
1467 struct pci_controller
*hose
;
1468 struct pnv_phb
*phb
;
1469 struct pnv_ioda_pe
*pe
;
1471 struct pci_sriov
*iov
;
1475 hose
= pci_bus_to_host(bus
);
1476 phb
= hose
->private_data
;
1477 pdn
= pci_get_pdn(pdev
);
1479 num_vfs
= pdn
->num_vfs
;
1481 /* Release VF PEs */
1482 pnv_ioda_release_vf_PE(pdev
);
1484 if (phb
->type
== PNV_PHB_IODA2
) {
1485 if (!pdn
->m64_single_mode
)
1486 pnv_pci_vf_resource_shift(pdev
, -*pdn
->pe_num_map
);
1488 /* Release M64 windows */
1489 pnv_pci_vf_release_m64(pdev
, num_vfs
);
1491 /* Release PE numbers */
1492 if (pdn
->m64_single_mode
) {
1493 for (i
= 0; i
< num_vfs
; i
++) {
1494 if (pdn
->pe_num_map
[i
] == IODA_INVALID_PE
)
1497 pe
= &phb
->ioda
.pe_array
[pdn
->pe_num_map
[i
]];
1498 pnv_ioda_free_pe(pe
);
1501 bitmap_clear(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1502 /* Releasing pe_num_map */
1503 kfree(pdn
->pe_num_map
);
1507 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
1508 struct pnv_ioda_pe
*pe
);
1509 static void pnv_ioda_setup_vf_PE(struct pci_dev
*pdev
, u16 num_vfs
)
1511 struct pci_bus
*bus
;
1512 struct pci_controller
*hose
;
1513 struct pnv_phb
*phb
;
1514 struct pnv_ioda_pe
*pe
;
1520 hose
= pci_bus_to_host(bus
);
1521 phb
= hose
->private_data
;
1522 pdn
= pci_get_pdn(pdev
);
1524 if (!pdev
->is_physfn
)
1527 /* Reserve PE for each VF */
1528 for (vf_index
= 0; vf_index
< num_vfs
; vf_index
++) {
1529 if (pdn
->m64_single_mode
)
1530 pe_num
= pdn
->pe_num_map
[vf_index
];
1532 pe_num
= *pdn
->pe_num_map
+ vf_index
;
1534 pe
= &phb
->ioda
.pe_array
[pe_num
];
1535 pe
->pe_number
= pe_num
;
1537 pe
->flags
= PNV_IODA_PE_VF
;
1539 pe
->parent_dev
= pdev
;
1540 pe
->mve_number
= -1;
1541 pe
->rid
= (pci_iov_virtfn_bus(pdev
, vf_index
) << 8) |
1542 pci_iov_virtfn_devfn(pdev
, vf_index
);
1544 pe_info(pe
, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1545 hose
->global_number
, pdev
->bus
->number
,
1546 PCI_SLOT(pci_iov_virtfn_devfn(pdev
, vf_index
)),
1547 PCI_FUNC(pci_iov_virtfn_devfn(pdev
, vf_index
)), pe_num
);
1549 if (pnv_ioda_configure_pe(phb
, pe
)) {
1550 /* XXX What do we do here ? */
1551 pnv_ioda_free_pe(pe
);
1556 /* Put PE to the list */
1557 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1558 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1559 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1561 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
1565 int pnv_pci_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1567 struct pci_bus
*bus
;
1568 struct pci_controller
*hose
;
1569 struct pnv_phb
*phb
;
1570 struct pnv_ioda_pe
*pe
;
1576 hose
= pci_bus_to_host(bus
);
1577 phb
= hose
->private_data
;
1578 pdn
= pci_get_pdn(pdev
);
1580 if (phb
->type
== PNV_PHB_IODA2
) {
1581 if (!pdn
->vfs_expanded
) {
1582 dev_info(&pdev
->dev
, "don't support this SRIOV device"
1583 " with non 64bit-prefetchable IOV BAR\n");
1588 * When M64 BARs functions in Single PE mode, the number of VFs
1589 * could be enabled must be less than the number of M64 BARs.
1591 if (pdn
->m64_single_mode
&& num_vfs
> phb
->ioda
.m64_bar_idx
) {
1592 dev_info(&pdev
->dev
, "Not enough M64 BAR for VFs\n");
1596 /* Allocating pe_num_map */
1597 if (pdn
->m64_single_mode
)
1598 pdn
->pe_num_map
= kmalloc(sizeof(*pdn
->pe_num_map
) * num_vfs
,
1601 pdn
->pe_num_map
= kmalloc(sizeof(*pdn
->pe_num_map
), GFP_KERNEL
);
1603 if (!pdn
->pe_num_map
)
1606 if (pdn
->m64_single_mode
)
1607 for (i
= 0; i
< num_vfs
; i
++)
1608 pdn
->pe_num_map
[i
] = IODA_INVALID_PE
;
1610 /* Calculate available PE for required VFs */
1611 if (pdn
->m64_single_mode
) {
1612 for (i
= 0; i
< num_vfs
; i
++) {
1613 pe
= pnv_ioda_alloc_pe(phb
);
1619 pdn
->pe_num_map
[i
] = pe
->pe_number
;
1622 mutex_lock(&phb
->ioda
.pe_alloc_mutex
);
1623 *pdn
->pe_num_map
= bitmap_find_next_zero_area(
1624 phb
->ioda
.pe_alloc
, phb
->ioda
.total_pe_num
,
1626 if (*pdn
->pe_num_map
>= phb
->ioda
.total_pe_num
) {
1627 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1628 dev_info(&pdev
->dev
, "Failed to enable VF%d\n", num_vfs
);
1629 kfree(pdn
->pe_num_map
);
1632 bitmap_set(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1633 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1635 pdn
->num_vfs
= num_vfs
;
1637 /* Assign M64 window accordingly */
1638 ret
= pnv_pci_vf_assign_m64(pdev
, num_vfs
);
1640 dev_info(&pdev
->dev
, "Not enough M64 window resources\n");
1645 * When using one M64 BAR to map one IOV BAR, we need to shift
1646 * the IOV BAR according to the PE# allocated to the VFs.
1647 * Otherwise, the PE# for the VF will conflict with others.
1649 if (!pdn
->m64_single_mode
) {
1650 ret
= pnv_pci_vf_resource_shift(pdev
, *pdn
->pe_num_map
);
1657 pnv_ioda_setup_vf_PE(pdev
, num_vfs
);
1662 if (pdn
->m64_single_mode
) {
1663 for (i
= 0; i
< num_vfs
; i
++) {
1664 if (pdn
->pe_num_map
[i
] == IODA_INVALID_PE
)
1667 pe
= &phb
->ioda
.pe_array
[pdn
->pe_num_map
[i
]];
1668 pnv_ioda_free_pe(pe
);
1671 bitmap_clear(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1673 /* Releasing pe_num_map */
1674 kfree(pdn
->pe_num_map
);
1679 int pcibios_sriov_disable(struct pci_dev
*pdev
)
1681 pnv_pci_sriov_disable(pdev
);
1683 /* Release PCI data */
1684 remove_dev_pci_data(pdev
);
1688 int pcibios_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1690 /* Allocate PCI data */
1691 add_dev_pci_data(pdev
);
1693 return pnv_pci_sriov_enable(pdev
, num_vfs
);
1695 #endif /* CONFIG_PCI_IOV */
1697 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb
*phb
, struct pci_dev
*pdev
)
1699 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1700 struct pnv_ioda_pe
*pe
;
1703 * The function can be called while the PE#
1704 * hasn't been assigned. Do nothing for the
1707 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
1710 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1711 WARN_ON(get_dma_ops(&pdev
->dev
) != &dma_iommu_ops
);
1712 set_dma_offset(&pdev
->dev
, pe
->tce_bypass_base
);
1713 set_iommu_table_base(&pdev
->dev
, pe
->table_group
.tables
[0]);
1715 * Note: iommu_add_device() will fail here as
1716 * for physical PE: the device is already added by now;
1717 * for virtual PE: sysfs entries are not ready yet and
1718 * tce_iommu_bus_notifier will add the device to a group later.
1722 static int pnv_pci_ioda_dma_set_mask(struct pci_dev
*pdev
, u64 dma_mask
)
1724 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
1725 struct pnv_phb
*phb
= hose
->private_data
;
1726 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1727 struct pnv_ioda_pe
*pe
;
1729 bool bypass
= false;
1731 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1734 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1735 if (pe
->tce_bypass_enabled
) {
1736 top
= pe
->tce_bypass_base
+ memblock_end_of_DRAM() - 1;
1737 bypass
= (dma_mask
>= top
);
1741 dev_info(&pdev
->dev
, "Using 64-bit DMA iommu bypass\n");
1742 set_dma_ops(&pdev
->dev
, &dma_direct_ops
);
1744 dev_info(&pdev
->dev
, "Using 32-bit DMA via iommu\n");
1745 set_dma_ops(&pdev
->dev
, &dma_iommu_ops
);
1747 *pdev
->dev
.dma_mask
= dma_mask
;
1749 /* Update peer npu devices */
1750 pnv_npu_try_dma_set_bypass(pdev
, bypass
);
1755 static u64
pnv_pci_ioda_dma_get_required_mask(struct pci_dev
*pdev
)
1757 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
1758 struct pnv_phb
*phb
= hose
->private_data
;
1759 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1760 struct pnv_ioda_pe
*pe
;
1763 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1766 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1767 if (!pe
->tce_bypass_enabled
)
1768 return __dma_get_required_mask(&pdev
->dev
);
1771 end
= pe
->tce_bypass_base
+ memblock_end_of_DRAM();
1772 mask
= 1ULL << (fls64(end
) - 1);
1778 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe
*pe
,
1779 struct pci_bus
*bus
)
1781 struct pci_dev
*dev
;
1783 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1784 set_iommu_table_base(&dev
->dev
, pe
->table_group
.tables
[0]);
1785 set_dma_offset(&dev
->dev
, pe
->tce_bypass_base
);
1786 iommu_add_device(&dev
->dev
);
1788 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1789 pnv_ioda_setup_bus_dma(pe
, dev
->subordinate
);
1793 static inline __be64 __iomem
*pnv_ioda_get_inval_reg(struct pnv_phb
*phb
,
1796 return real_mode
? (__be64 __iomem
*)(phb
->regs_phys
+ 0x210) :
1797 (phb
->regs
+ 0x210);
1800 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table
*tbl
,
1801 unsigned long index
, unsigned long npages
, bool rm
)
1803 struct iommu_table_group_link
*tgl
= list_first_entry_or_null(
1804 &tbl
->it_group_list
, struct iommu_table_group_link
,
1806 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1807 struct pnv_ioda_pe
, table_group
);
1808 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, rm
);
1809 unsigned long start
, end
, inc
;
1811 start
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
);
1812 end
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
+
1815 /* p7ioc-style invalidation, 2 TCEs per write */
1816 start
|= (1ull << 63);
1817 end
|= (1ull << 63);
1819 end
|= inc
- 1; /* round up end to be different than start */
1821 mb(); /* Ensure above stores are visible */
1822 while (start
<= end
) {
1824 __raw_rm_writeq(cpu_to_be64(start
), invalidate
);
1826 __raw_writeq(cpu_to_be64(start
), invalidate
);
1831 * The iommu layer will do another mb() for us on build()
1832 * and we don't care on free()
1836 static int pnv_ioda1_tce_build(struct iommu_table
*tbl
, long index
,
1837 long npages
, unsigned long uaddr
,
1838 enum dma_data_direction direction
,
1839 unsigned long attrs
)
1841 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
1845 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, npages
, false);
1850 #ifdef CONFIG_IOMMU_API
1851 static int pnv_ioda1_tce_xchg(struct iommu_table
*tbl
, long index
,
1852 unsigned long *hpa
, enum dma_data_direction
*direction
)
1854 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
1857 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, 1, false);
1862 static int pnv_ioda1_tce_xchg_rm(struct iommu_table
*tbl
, long index
,
1863 unsigned long *hpa
, enum dma_data_direction
*direction
)
1865 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
1868 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, 1, true);
1874 static void pnv_ioda1_tce_free(struct iommu_table
*tbl
, long index
,
1877 pnv_tce_free(tbl
, index
, npages
);
1879 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, npages
, false);
1882 static struct iommu_table_ops pnv_ioda1_iommu_ops
= {
1883 .set
= pnv_ioda1_tce_build
,
1884 #ifdef CONFIG_IOMMU_API
1885 .exchange
= pnv_ioda1_tce_xchg
,
1886 .exchange_rm
= pnv_ioda1_tce_xchg_rm
,
1888 .clear
= pnv_ioda1_tce_free
,
1892 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1893 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1894 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1896 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb
*phb
, bool rm
)
1898 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(phb
, rm
);
1899 const unsigned long val
= PHB3_TCE_KILL_INVAL_ALL
;
1901 mb(); /* Ensure previous TCE table stores are visible */
1903 __raw_rm_writeq(cpu_to_be64(val
), invalidate
);
1905 __raw_writeq(cpu_to_be64(val
), invalidate
);
1908 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe
*pe
)
1910 /* 01xb - invalidate TCEs that match the specified PE# */
1911 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, false);
1912 unsigned long val
= PHB3_TCE_KILL_INVAL_PE
| (pe
->pe_number
& 0xFF);
1914 mb(); /* Ensure above stores are visible */
1915 __raw_writeq(cpu_to_be64(val
), invalidate
);
1918 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe
*pe
, bool rm
,
1919 unsigned shift
, unsigned long index
,
1920 unsigned long npages
)
1922 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, rm
);
1923 unsigned long start
, end
, inc
;
1925 /* We'll invalidate DMA address in PE scope */
1926 start
= PHB3_TCE_KILL_INVAL_ONE
;
1927 start
|= (pe
->pe_number
& 0xFF);
1930 /* Figure out the start, end and step */
1931 start
|= (index
<< shift
);
1932 end
|= ((index
+ npages
- 1) << shift
);
1933 inc
= (0x1ull
<< shift
);
1936 while (start
<= end
) {
1938 __raw_rm_writeq(cpu_to_be64(start
), invalidate
);
1940 __raw_writeq(cpu_to_be64(start
), invalidate
);
1945 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe
*pe
)
1947 struct pnv_phb
*phb
= pe
->phb
;
1949 if (phb
->model
== PNV_PHB_MODEL_PHB3
&& phb
->regs
)
1950 pnv_pci_phb3_tce_invalidate_pe(pe
);
1952 opal_pci_tce_kill(phb
->opal_id
, OPAL_PCI_TCE_KILL_PE
,
1953 pe
->pe_number
, 0, 0, 0);
1956 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table
*tbl
,
1957 unsigned long index
, unsigned long npages
, bool rm
)
1959 struct iommu_table_group_link
*tgl
;
1961 list_for_each_entry_lockless(tgl
, &tbl
->it_group_list
, next
) {
1962 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1963 struct pnv_ioda_pe
, table_group
);
1964 struct pnv_phb
*phb
= pe
->phb
;
1965 unsigned int shift
= tbl
->it_page_shift
;
1968 * NVLink1 can use the TCE kill register directly as
1969 * it's the same as PHB3. NVLink2 is different and
1970 * should go via the OPAL call.
1972 if (phb
->model
== PNV_PHB_MODEL_NPU
) {
1974 * The NVLink hardware does not support TCE kill
1975 * per TCE entry so we have to invalidate
1976 * the entire cache for it.
1978 pnv_pci_phb3_tce_invalidate_entire(phb
, rm
);
1981 if (phb
->model
== PNV_PHB_MODEL_PHB3
&& phb
->regs
)
1982 pnv_pci_phb3_tce_invalidate(pe
, rm
, shift
,
1985 opal_pci_tce_kill(phb
->opal_id
,
1986 OPAL_PCI_TCE_KILL_PAGES
,
1987 pe
->pe_number
, 1u << shift
,
1988 index
<< shift
, npages
);
1992 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb
*phb
, bool rm
)
1994 if (phb
->model
== PNV_PHB_MODEL_NPU
|| phb
->model
== PNV_PHB_MODEL_PHB3
)
1995 pnv_pci_phb3_tce_invalidate_entire(phb
, rm
);
1997 opal_pci_tce_kill(phb
->opal_id
, OPAL_PCI_TCE_KILL
, 0, 0, 0, 0);
2000 static int pnv_ioda2_tce_build(struct iommu_table
*tbl
, long index
,
2001 long npages
, unsigned long uaddr
,
2002 enum dma_data_direction direction
,
2003 unsigned long attrs
)
2005 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
2009 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
2014 #ifdef CONFIG_IOMMU_API
2015 static int pnv_ioda2_tce_xchg(struct iommu_table
*tbl
, long index
,
2016 unsigned long *hpa
, enum dma_data_direction
*direction
)
2018 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
2021 pnv_pci_ioda2_tce_invalidate(tbl
, index
, 1, false);
2026 static int pnv_ioda2_tce_xchg_rm(struct iommu_table
*tbl
, long index
,
2027 unsigned long *hpa
, enum dma_data_direction
*direction
)
2029 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
2032 pnv_pci_ioda2_tce_invalidate(tbl
, index
, 1, true);
2038 static void pnv_ioda2_tce_free(struct iommu_table
*tbl
, long index
,
2041 pnv_tce_free(tbl
, index
, npages
);
2043 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
2046 static void pnv_ioda2_table_free(struct iommu_table
*tbl
)
2048 pnv_pci_ioda2_table_free_pages(tbl
);
2049 iommu_free_table(tbl
, "pnv");
2052 static struct iommu_table_ops pnv_ioda2_iommu_ops
= {
2053 .set
= pnv_ioda2_tce_build
,
2054 #ifdef CONFIG_IOMMU_API
2055 .exchange
= pnv_ioda2_tce_xchg
,
2056 .exchange_rm
= pnv_ioda2_tce_xchg_rm
,
2058 .clear
= pnv_ioda2_tce_free
,
2060 .free
= pnv_ioda2_table_free
,
2063 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev
*dev
, void *data
)
2065 unsigned int *weight
= (unsigned int *)data
;
2067 /* This is quite simplistic. The "base" weight of a device
2068 * is 10. 0 means no DMA is to be accounted for it.
2070 if (dev
->hdr_type
!= PCI_HEADER_TYPE_NORMAL
)
2073 if (dev
->class == PCI_CLASS_SERIAL_USB_UHCI
||
2074 dev
->class == PCI_CLASS_SERIAL_USB_OHCI
||
2075 dev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
2077 else if ((dev
->class >> 8) == PCI_CLASS_STORAGE_RAID
)
2085 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe
*pe
)
2087 unsigned int weight
= 0;
2089 /* SRIOV VF has same DMA32 weight as its PF */
2090 #ifdef CONFIG_PCI_IOV
2091 if ((pe
->flags
& PNV_IODA_PE_VF
) && pe
->parent_dev
) {
2092 pnv_pci_ioda_dev_dma_weight(pe
->parent_dev
, &weight
);
2097 if ((pe
->flags
& PNV_IODA_PE_DEV
) && pe
->pdev
) {
2098 pnv_pci_ioda_dev_dma_weight(pe
->pdev
, &weight
);
2099 } else if ((pe
->flags
& PNV_IODA_PE_BUS
) && pe
->pbus
) {
2100 struct pci_dev
*pdev
;
2102 list_for_each_entry(pdev
, &pe
->pbus
->devices
, bus_list
)
2103 pnv_pci_ioda_dev_dma_weight(pdev
, &weight
);
2104 } else if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && pe
->pbus
) {
2105 pci_walk_bus(pe
->pbus
, pnv_pci_ioda_dev_dma_weight
, &weight
);
2111 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb
*phb
,
2112 struct pnv_ioda_pe
*pe
)
2115 struct page
*tce_mem
= NULL
;
2116 struct iommu_table
*tbl
;
2117 unsigned int weight
, total_weight
= 0;
2118 unsigned int tce32_segsz
, base
, segs
, avail
, i
;
2122 /* XXX FIXME: Handle 64-bit only DMA devices */
2123 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2124 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2125 weight
= pnv_pci_ioda_pe_dma_weight(pe
);
2129 pci_walk_bus(phb
->hose
->bus
, pnv_pci_ioda_dev_dma_weight
,
2131 segs
= (weight
* phb
->ioda
.dma32_count
) / total_weight
;
2136 * Allocate contiguous DMA32 segments. We begin with the expected
2137 * number of segments. With one more attempt, the number of DMA32
2138 * segments to be allocated is decreased by one until one segment
2139 * is allocated successfully.
2142 for (base
= 0; base
<= phb
->ioda
.dma32_count
- segs
; base
++) {
2143 for (avail
= 0, i
= base
; i
< base
+ segs
; i
++) {
2144 if (phb
->ioda
.dma32_segmap
[i
] ==
2155 pe_warn(pe
, "No available DMA32 segments\n");
2160 tbl
= pnv_pci_table_alloc(phb
->hose
->node
);
2161 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
2163 pnv_pci_link_table_and_group(phb
->hose
->node
, 0, tbl
, &pe
->table_group
);
2165 /* Grab a 32-bit TCE table */
2166 pe_info(pe
, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2167 weight
, total_weight
, base
, segs
);
2168 pe_info(pe
, " Setting up 32-bit TCE table at %08x..%08x\n",
2169 base
* PNV_IODA1_DMA32_SEGSIZE
,
2170 (base
+ segs
) * PNV_IODA1_DMA32_SEGSIZE
- 1);
2172 /* XXX Currently, we allocate one big contiguous table for the
2173 * TCEs. We only really need one chunk per 256M of TCE space
2174 * (ie per segment) but that's an optimization for later, it
2175 * requires some added smarts with our get/put_tce implementation
2177 * Each TCE page is 4KB in size and each TCE entry occupies 8
2180 tce32_segsz
= PNV_IODA1_DMA32_SEGSIZE
>> (IOMMU_PAGE_SHIFT_4K
- 3);
2181 tce_mem
= alloc_pages_node(phb
->hose
->node
, GFP_KERNEL
,
2182 get_order(tce32_segsz
* segs
));
2184 pe_err(pe
, " Failed to allocate a 32-bit TCE memory\n");
2187 addr
= page_address(tce_mem
);
2188 memset(addr
, 0, tce32_segsz
* segs
);
2191 for (i
= 0; i
< segs
; i
++) {
2192 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
2195 __pa(addr
) + tce32_segsz
* i
,
2196 tce32_segsz
, IOMMU_PAGE_SIZE_4K
);
2198 pe_err(pe
, " Failed to configure 32-bit TCE table,"
2204 /* Setup DMA32 segment mapping */
2205 for (i
= base
; i
< base
+ segs
; i
++)
2206 phb
->ioda
.dma32_segmap
[i
] = pe
->pe_number
;
2208 /* Setup linux iommu table */
2209 pnv_pci_setup_iommu_table(tbl
, addr
, tce32_segsz
* segs
,
2210 base
* PNV_IODA1_DMA32_SEGSIZE
,
2211 IOMMU_PAGE_SHIFT_4K
);
2213 tbl
->it_ops
= &pnv_ioda1_iommu_ops
;
2214 pe
->table_group
.tce32_start
= tbl
->it_offset
<< tbl
->it_page_shift
;
2215 pe
->table_group
.tce32_size
= tbl
->it_size
<< tbl
->it_page_shift
;
2216 iommu_init_table(tbl
, phb
->hose
->node
);
2218 if (pe
->flags
& PNV_IODA_PE_DEV
) {
2220 * Setting table base here only for carrying iommu_group
2221 * further down to let iommu_add_device() do the job.
2222 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2224 set_iommu_table_base(&pe
->pdev
->dev
, tbl
);
2225 iommu_add_device(&pe
->pdev
->dev
);
2226 } else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2227 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2231 /* XXX Failure: Try to fallback to 64-bit only ? */
2233 __free_pages(tce_mem
, get_order(tce32_segsz
* segs
));
2235 pnv_pci_unlink_table_and_group(tbl
, &pe
->table_group
);
2236 iommu_free_table(tbl
, "pnv");
2240 static long pnv_pci_ioda2_set_window(struct iommu_table_group
*table_group
,
2241 int num
, struct iommu_table
*tbl
)
2243 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2245 struct pnv_phb
*phb
= pe
->phb
;
2247 const unsigned long size
= tbl
->it_indirect_levels
?
2248 tbl
->it_level_size
: tbl
->it_size
;
2249 const __u64 start_addr
= tbl
->it_offset
<< tbl
->it_page_shift
;
2250 const __u64 win_size
= tbl
->it_size
<< tbl
->it_page_shift
;
2252 pe_info(pe
, "Setting up window#%d %llx..%llx pg=%x\n", num
,
2253 start_addr
, start_addr
+ win_size
- 1,
2254 IOMMU_PAGE_SIZE(tbl
));
2257 * Map TCE table through TVT. The TVE index is the PE number
2258 * shifted by 1 bit for 32-bits DMA space.
2260 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
2262 (pe
->pe_number
<< 1) + num
,
2263 tbl
->it_indirect_levels
+ 1,
2266 IOMMU_PAGE_SIZE(tbl
));
2268 pe_err(pe
, "Failed to configure TCE table, err %ld\n", rc
);
2272 pnv_pci_link_table_and_group(phb
->hose
->node
, num
,
2273 tbl
, &pe
->table_group
);
2274 pnv_pci_ioda2_tce_invalidate_pe(pe
);
2279 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
)
2281 uint16_t window_id
= (pe
->pe_number
<< 1 ) + 1;
2284 pe_info(pe
, "%sabling 64-bit DMA bypass\n", enable
? "En" : "Dis");
2286 phys_addr_t top
= memblock_end_of_DRAM();
2288 top
= roundup_pow_of_two(top
);
2289 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2292 pe
->tce_bypass_base
,
2295 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2298 pe
->tce_bypass_base
,
2302 pe_err(pe
, "OPAL error %lld configuring bypass window\n", rc
);
2304 pe
->tce_bypass_enabled
= enable
;
2307 static long pnv_pci_ioda2_table_alloc_pages(int nid
, __u64 bus_offset
,
2308 __u32 page_shift
, __u64 window_size
, __u32 levels
,
2309 struct iommu_table
*tbl
);
2311 static long pnv_pci_ioda2_create_table(struct iommu_table_group
*table_group
,
2312 int num
, __u32 page_shift
, __u64 window_size
, __u32 levels
,
2313 struct iommu_table
**ptbl
)
2315 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2317 int nid
= pe
->phb
->hose
->node
;
2318 __u64 bus_offset
= num
? pe
->tce_bypass_base
: table_group
->tce32_start
;
2320 struct iommu_table
*tbl
;
2322 tbl
= pnv_pci_table_alloc(nid
);
2326 ret
= pnv_pci_ioda2_table_alloc_pages(nid
,
2327 bus_offset
, page_shift
, window_size
,
2330 iommu_free_table(tbl
, "pnv");
2334 tbl
->it_ops
= &pnv_ioda2_iommu_ops
;
2341 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe
*pe
)
2343 struct iommu_table
*tbl
= NULL
;
2347 * crashkernel= specifies the kdump kernel's maximum memory at
2348 * some offset and there is no guaranteed the result is a power
2349 * of 2, which will cause errors later.
2351 const u64 max_memory
= __rounddown_pow_of_two(memory_hotplug_max());
2354 * In memory constrained environments, e.g. kdump kernel, the
2355 * DMA window can be larger than available memory, which will
2356 * cause errors later.
2358 const u64 window_size
= min((u64
)pe
->table_group
.tce32_size
, max_memory
);
2360 rc
= pnv_pci_ioda2_create_table(&pe
->table_group
, 0,
2361 IOMMU_PAGE_SHIFT_4K
,
2363 POWERNV_IOMMU_DEFAULT_LEVELS
, &tbl
);
2365 pe_err(pe
, "Failed to create 32-bit TCE table, err %ld",
2370 iommu_init_table(tbl
, pe
->phb
->hose
->node
);
2372 rc
= pnv_pci_ioda2_set_window(&pe
->table_group
, 0, tbl
);
2374 pe_err(pe
, "Failed to configure 32-bit TCE table, err %ld\n",
2376 pnv_ioda2_table_free(tbl
);
2380 if (!pnv_iommu_bypass_disabled
)
2381 pnv_pci_ioda2_set_bypass(pe
, true);
2384 * Setting table base here only for carrying iommu_group
2385 * further down to let iommu_add_device() do the job.
2386 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2388 if (pe
->flags
& PNV_IODA_PE_DEV
)
2389 set_iommu_table_base(&pe
->pdev
->dev
, tbl
);
2394 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2395 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
2398 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2400 struct pnv_phb
*phb
= pe
->phb
;
2403 pe_info(pe
, "Removing DMA window #%d\n", num
);
2405 ret
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
2406 (pe
->pe_number
<< 1) + num
,
2407 0/* levels */, 0/* table address */,
2408 0/* table size */, 0/* page size */);
2410 pe_warn(pe
, "Unmapping failed, ret = %ld\n", ret
);
2412 pnv_pci_ioda2_tce_invalidate_pe(pe
);
2414 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
2420 #ifdef CONFIG_IOMMU_API
2421 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift
,
2422 __u64 window_size
, __u32 levels
)
2424 unsigned long bytes
= 0;
2425 const unsigned window_shift
= ilog2(window_size
);
2426 unsigned entries_shift
= window_shift
- page_shift
;
2427 unsigned table_shift
= entries_shift
+ 3;
2428 unsigned long tce_table_size
= max(0x1000UL
, 1UL << table_shift
);
2429 unsigned long direct_table_size
;
2431 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
) ||
2432 (window_size
> memory_hotplug_max()) ||
2433 !is_power_of_2(window_size
))
2436 /* Calculate a direct table size from window_size and levels */
2437 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2438 table_shift
= entries_shift
+ 3;
2439 table_shift
= max_t(unsigned, table_shift
, PAGE_SHIFT
);
2440 direct_table_size
= 1UL << table_shift
;
2442 for ( ; levels
; --levels
) {
2443 bytes
+= _ALIGN_UP(tce_table_size
, direct_table_size
);
2445 tce_table_size
/= direct_table_size
;
2446 tce_table_size
<<= 3;
2447 tce_table_size
= _ALIGN_UP(tce_table_size
, direct_table_size
);
2453 static void pnv_ioda2_take_ownership(struct iommu_table_group
*table_group
)
2455 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2457 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2458 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
2460 pnv_pci_ioda2_set_bypass(pe
, false);
2461 pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
2462 pnv_ioda2_table_free(tbl
);
2465 static void pnv_ioda2_release_ownership(struct iommu_table_group
*table_group
)
2467 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2470 pnv_pci_ioda2_setup_default_config(pe
);
2473 static struct iommu_table_group_ops pnv_pci_ioda2_ops
= {
2474 .get_table_size
= pnv_pci_ioda2_get_table_size
,
2475 .create_table
= pnv_pci_ioda2_create_table
,
2476 .set_window
= pnv_pci_ioda2_set_window
,
2477 .unset_window
= pnv_pci_ioda2_unset_window
,
2478 .take_ownership
= pnv_ioda2_take_ownership
,
2479 .release_ownership
= pnv_ioda2_release_ownership
,
2482 static int gpe_table_group_to_npe_cb(struct device
*dev
, void *opaque
)
2484 struct pci_controller
*hose
;
2485 struct pnv_phb
*phb
;
2486 struct pnv_ioda_pe
**ptmppe
= opaque
;
2487 struct pci_dev
*pdev
= container_of(dev
, struct pci_dev
, dev
);
2488 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
2490 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
2493 hose
= pci_bus_to_host(pdev
->bus
);
2494 phb
= hose
->private_data
;
2495 if (phb
->type
!= PNV_PHB_NPU
)
2498 *ptmppe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
2504 * This returns PE of associated NPU.
2505 * This assumes that NPU is in the same IOMMU group with GPU and there is
2508 static struct pnv_ioda_pe
*gpe_table_group_to_npe(
2509 struct iommu_table_group
*table_group
)
2511 struct pnv_ioda_pe
*npe
= NULL
;
2512 int ret
= iommu_group_for_each_dev(table_group
->group
, &npe
,
2513 gpe_table_group_to_npe_cb
);
2515 BUG_ON(!ret
|| !npe
);
2520 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group
*table_group
,
2521 int num
, struct iommu_table
*tbl
)
2523 long ret
= pnv_pci_ioda2_set_window(table_group
, num
, tbl
);
2528 ret
= pnv_npu_set_window(gpe_table_group_to_npe(table_group
), num
, tbl
);
2530 pnv_pci_ioda2_unset_window(table_group
, num
);
2535 static long pnv_pci_ioda2_npu_unset_window(
2536 struct iommu_table_group
*table_group
,
2539 long ret
= pnv_pci_ioda2_unset_window(table_group
, num
);
2544 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group
), num
);
2547 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group
*table_group
)
2550 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2551 * the iommu_table if 32bit DMA is enabled.
2553 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group
));
2554 pnv_ioda2_take_ownership(table_group
);
2557 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops
= {
2558 .get_table_size
= pnv_pci_ioda2_get_table_size
,
2559 .create_table
= pnv_pci_ioda2_create_table
,
2560 .set_window
= pnv_pci_ioda2_npu_set_window
,
2561 .unset_window
= pnv_pci_ioda2_npu_unset_window
,
2562 .take_ownership
= pnv_ioda2_npu_take_ownership
,
2563 .release_ownership
= pnv_ioda2_release_ownership
,
2566 static void pnv_pci_ioda_setup_iommu_api(void)
2568 struct pci_controller
*hose
, *tmp
;
2569 struct pnv_phb
*phb
;
2570 struct pnv_ioda_pe
*pe
, *gpe
;
2573 * Now we have all PHBs discovered, time to add NPU devices to
2574 * the corresponding IOMMU groups.
2576 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
2577 phb
= hose
->private_data
;
2579 if (phb
->type
!= PNV_PHB_NPU
)
2582 list_for_each_entry(pe
, &phb
->ioda
.pe_list
, list
) {
2583 gpe
= pnv_pci_npu_setup_iommu(pe
);
2585 gpe
->table_group
.ops
= &pnv_pci_ioda2_npu_ops
;
2589 #else /* !CONFIG_IOMMU_API */
2590 static void pnv_pci_ioda_setup_iommu_api(void) { };
2593 static __be64
*pnv_pci_ioda2_table_do_alloc_pages(int nid
, unsigned shift
,
2594 unsigned levels
, unsigned long limit
,
2595 unsigned long *current_offset
, unsigned long *total_allocated
)
2597 struct page
*tce_mem
= NULL
;
2599 unsigned order
= max_t(unsigned, shift
, PAGE_SHIFT
) - PAGE_SHIFT
;
2600 unsigned long allocated
= 1UL << (order
+ PAGE_SHIFT
);
2601 unsigned entries
= 1UL << (shift
- 3);
2604 tce_mem
= alloc_pages_node(nid
, GFP_KERNEL
, order
);
2606 pr_err("Failed to allocate a TCE memory, order=%d\n", order
);
2609 addr
= page_address(tce_mem
);
2610 memset(addr
, 0, allocated
);
2611 *total_allocated
+= allocated
;
2615 *current_offset
+= allocated
;
2619 for (i
= 0; i
< entries
; ++i
) {
2620 tmp
= pnv_pci_ioda2_table_do_alloc_pages(nid
, shift
,
2621 levels
, limit
, current_offset
, total_allocated
);
2625 addr
[i
] = cpu_to_be64(__pa(tmp
) |
2626 TCE_PCI_READ
| TCE_PCI_WRITE
);
2628 if (*current_offset
>= limit
)
2635 static void pnv_pci_ioda2_table_do_free_pages(__be64
*addr
,
2636 unsigned long size
, unsigned level
);
2638 static long pnv_pci_ioda2_table_alloc_pages(int nid
, __u64 bus_offset
,
2639 __u32 page_shift
, __u64 window_size
, __u32 levels
,
2640 struct iommu_table
*tbl
)
2643 unsigned long offset
= 0, level_shift
, total_allocated
= 0;
2644 const unsigned window_shift
= ilog2(window_size
);
2645 unsigned entries_shift
= window_shift
- page_shift
;
2646 unsigned table_shift
= max_t(unsigned, entries_shift
+ 3, PAGE_SHIFT
);
2647 const unsigned long tce_table_size
= 1UL << table_shift
;
2649 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
))
2652 if ((window_size
> memory_hotplug_max()) || !is_power_of_2(window_size
))
2655 /* Adjust direct table size from window_size and levels */
2656 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2657 level_shift
= entries_shift
+ 3;
2658 level_shift
= max_t(unsigned, level_shift
, PAGE_SHIFT
);
2660 /* Allocate TCE table */
2661 addr
= pnv_pci_ioda2_table_do_alloc_pages(nid
, level_shift
,
2662 levels
, tce_table_size
, &offset
, &total_allocated
);
2664 /* addr==NULL means that the first level allocation failed */
2669 * First level was allocated but some lower level failed as
2670 * we did not allocate as much as we wanted,
2671 * release partially allocated table.
2673 if (offset
< tce_table_size
) {
2674 pnv_pci_ioda2_table_do_free_pages(addr
,
2675 1ULL << (level_shift
- 3), levels
- 1);
2679 /* Setup linux iommu table */
2680 pnv_pci_setup_iommu_table(tbl
, addr
, tce_table_size
, bus_offset
,
2682 tbl
->it_level_size
= 1ULL << (level_shift
- 3);
2683 tbl
->it_indirect_levels
= levels
- 1;
2684 tbl
->it_allocated_size
= total_allocated
;
2686 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2687 window_size
, tce_table_size
, bus_offset
);
2692 static void pnv_pci_ioda2_table_do_free_pages(__be64
*addr
,
2693 unsigned long size
, unsigned level
)
2695 const unsigned long addr_ul
= (unsigned long) addr
&
2696 ~(TCE_PCI_READ
| TCE_PCI_WRITE
);
2700 u64
*tmp
= (u64
*) addr_ul
;
2702 for (i
= 0; i
< size
; ++i
) {
2703 unsigned long hpa
= be64_to_cpu(tmp
[i
]);
2705 if (!(hpa
& (TCE_PCI_READ
| TCE_PCI_WRITE
)))
2708 pnv_pci_ioda2_table_do_free_pages(__va(hpa
), size
,
2713 free_pages(addr_ul
, get_order(size
<< 3));
2716 static void pnv_pci_ioda2_table_free_pages(struct iommu_table
*tbl
)
2718 const unsigned long size
= tbl
->it_indirect_levels
?
2719 tbl
->it_level_size
: tbl
->it_size
;
2724 pnv_pci_ioda2_table_do_free_pages((__be64
*)tbl
->it_base
, size
,
2725 tbl
->it_indirect_levels
);
2728 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
2729 struct pnv_ioda_pe
*pe
)
2733 if (!pnv_pci_ioda_pe_dma_weight(pe
))
2736 /* TVE #1 is selected by PCI address bit 59 */
2737 pe
->tce_bypass_base
= 1ull << 59;
2739 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
2742 /* The PE will reserve all possible 32-bits space */
2743 pe_info(pe
, "Setting up 32-bit TCE table at 0..%08x\n",
2744 phb
->ioda
.m32_pci_base
);
2746 /* Setup linux iommu table */
2747 pe
->table_group
.tce32_start
= 0;
2748 pe
->table_group
.tce32_size
= phb
->ioda
.m32_pci_base
;
2749 pe
->table_group
.max_dynamic_windows_supported
=
2750 IOMMU_TABLE_GROUP_MAX_TABLES
;
2751 pe
->table_group
.max_levels
= POWERNV_IOMMU_MAX_LEVELS
;
2752 pe
->table_group
.pgsizes
= SZ_4K
| SZ_64K
| SZ_16M
;
2753 #ifdef CONFIG_IOMMU_API
2754 pe
->table_group
.ops
= &pnv_pci_ioda2_ops
;
2757 rc
= pnv_pci_ioda2_setup_default_config(pe
);
2761 if (pe
->flags
& PNV_IODA_PE_DEV
)
2762 iommu_add_device(&pe
->pdev
->dev
);
2763 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2764 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2767 #ifdef CONFIG_PCI_MSI
2768 int64_t pnv_opal_pci_msi_eoi(struct irq_chip
*chip
, unsigned int hw_irq
)
2770 struct pnv_phb
*phb
= container_of(chip
, struct pnv_phb
,
2773 return opal_pci_msi_eoi(phb
->opal_id
, hw_irq
);
2776 static void pnv_ioda2_msi_eoi(struct irq_data
*d
)
2779 unsigned int hw_irq
= (unsigned int)irqd_to_hwirq(d
);
2780 struct irq_chip
*chip
= irq_data_get_irq_chip(d
);
2782 rc
= pnv_opal_pci_msi_eoi(chip
, hw_irq
);
2789 void pnv_set_msi_irq_chip(struct pnv_phb
*phb
, unsigned int virq
)
2791 struct irq_data
*idata
;
2792 struct irq_chip
*ichip
;
2794 /* The MSI EOI OPAL call is only needed on PHB3 */
2795 if (phb
->model
!= PNV_PHB_MODEL_PHB3
)
2798 if (!phb
->ioda
.irq_chip_init
) {
2800 * First time we setup an MSI IRQ, we need to setup the
2801 * corresponding IRQ chip to route correctly.
2803 idata
= irq_get_irq_data(virq
);
2804 ichip
= irq_data_get_irq_chip(idata
);
2805 phb
->ioda
.irq_chip_init
= 1;
2806 phb
->ioda
.irq_chip
= *ichip
;
2807 phb
->ioda
.irq_chip
.irq_eoi
= pnv_ioda2_msi_eoi
;
2809 irq_set_chip(virq
, &phb
->ioda
.irq_chip
);
2813 * Returns true iff chip is something that we could call
2814 * pnv_opal_pci_msi_eoi for.
2816 bool is_pnv_opal_msi(struct irq_chip
*chip
)
2818 return chip
->irq_eoi
== pnv_ioda2_msi_eoi
;
2820 EXPORT_SYMBOL_GPL(is_pnv_opal_msi
);
2822 static int pnv_pci_ioda_msi_setup(struct pnv_phb
*phb
, struct pci_dev
*dev
,
2823 unsigned int hwirq
, unsigned int virq
,
2824 unsigned int is_64
, struct msi_msg
*msg
)
2826 struct pnv_ioda_pe
*pe
= pnv_ioda_get_pe(dev
);
2827 unsigned int xive_num
= hwirq
- phb
->msi_base
;
2831 /* No PE assigned ? bail out ... no MSI for you ! */
2835 /* Check if we have an MVE */
2836 if (pe
->mve_number
< 0)
2839 /* Force 32-bit MSI on some broken devices */
2840 if (dev
->no_64bit_msi
)
2843 /* Assign XIVE to PE */
2844 rc
= opal_pci_set_xive_pe(phb
->opal_id
, pe
->pe_number
, xive_num
);
2846 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2847 pci_name(dev
), rc
, xive_num
);
2854 rc
= opal_get_msi_64(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2857 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2861 msg
->address_hi
= be64_to_cpu(addr64
) >> 32;
2862 msg
->address_lo
= be64_to_cpu(addr64
) & 0xfffffffful
;
2866 rc
= opal_get_msi_32(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2869 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2873 msg
->address_hi
= 0;
2874 msg
->address_lo
= be32_to_cpu(addr32
);
2876 msg
->data
= be32_to_cpu(data
);
2878 pnv_set_msi_irq_chip(phb
, virq
);
2880 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2881 " address=%x_%08x data=%x PE# %x\n",
2882 pci_name(dev
), is_64
? "64" : "32", hwirq
, xive_num
,
2883 msg
->address_hi
, msg
->address_lo
, data
, pe
->pe_number
);
2888 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
)
2891 const __be32
*prop
= of_get_property(phb
->hose
->dn
,
2892 "ibm,opal-msi-ranges", NULL
);
2895 prop
= of_get_property(phb
->hose
->dn
, "msi-ranges", NULL
);
2900 phb
->msi_base
= be32_to_cpup(prop
);
2901 count
= be32_to_cpup(prop
+ 1);
2902 if (msi_bitmap_alloc(&phb
->msi_bmp
, count
, phb
->hose
->dn
)) {
2903 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2904 phb
->hose
->global_number
);
2908 phb
->msi_setup
= pnv_pci_ioda_msi_setup
;
2909 phb
->msi32_support
= 1;
2910 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2911 count
, phb
->msi_base
);
2914 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
) { }
2915 #endif /* CONFIG_PCI_MSI */
2917 #ifdef CONFIG_PCI_IOV
2918 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev
*pdev
)
2920 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
2921 struct pnv_phb
*phb
= hose
->private_data
;
2922 const resource_size_t gate
= phb
->ioda
.m64_segsize
>> 2;
2923 struct resource
*res
;
2925 resource_size_t size
, total_vf_bar_sz
;
2929 if (!pdev
->is_physfn
|| pdev
->is_added
)
2932 pdn
= pci_get_pdn(pdev
);
2933 pdn
->vfs_expanded
= 0;
2934 pdn
->m64_single_mode
= false;
2936 total_vfs
= pci_sriov_get_totalvfs(pdev
);
2937 mul
= phb
->ioda
.total_pe_num
;
2938 total_vf_bar_sz
= 0;
2940 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2941 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2942 if (!res
->flags
|| res
->parent
)
2944 if (!pnv_pci_is_m64_flags(res
->flags
)) {
2945 dev_warn(&pdev
->dev
, "Don't support SR-IOV with"
2946 " non M64 VF BAR%d: %pR. \n",
2951 total_vf_bar_sz
+= pci_iov_resource_size(pdev
,
2952 i
+ PCI_IOV_RESOURCES
);
2955 * If bigger than quarter of M64 segment size, just round up
2958 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2959 * with other devices, IOV BAR size is expanded to be
2960 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2961 * segment size , the expanded size would equal to half of the
2962 * whole M64 space size, which will exhaust the M64 Space and
2963 * limit the system flexibility. This is a design decision to
2964 * set the boundary to quarter of the M64 segment size.
2966 if (total_vf_bar_sz
> gate
) {
2967 mul
= roundup_pow_of_two(total_vfs
);
2968 dev_info(&pdev
->dev
,
2969 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2970 total_vf_bar_sz
, gate
, mul
);
2971 pdn
->m64_single_mode
= true;
2976 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2977 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2978 if (!res
->flags
|| res
->parent
)
2981 size
= pci_iov_resource_size(pdev
, i
+ PCI_IOV_RESOURCES
);
2983 * On PHB3, the minimum size alignment of M64 BAR in single
2986 if (pdn
->m64_single_mode
&& (size
< SZ_32M
))
2988 dev_dbg(&pdev
->dev
, " Fixing VF BAR%d: %pR to\n", i
, res
);
2989 res
->end
= res
->start
+ size
* mul
- 1;
2990 dev_dbg(&pdev
->dev
, " %pR\n", res
);
2991 dev_info(&pdev
->dev
, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2994 pdn
->vfs_expanded
= mul
;
2999 /* To save MMIO space, IOV BAR is truncated. */
3000 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
3001 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
3003 res
->end
= res
->start
- 1;
3006 #endif /* CONFIG_PCI_IOV */
3008 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe
*pe
,
3009 struct resource
*res
)
3011 struct pnv_phb
*phb
= pe
->phb
;
3012 struct pci_bus_region region
;
3016 if (!res
|| !res
->flags
|| res
->start
> res
->end
)
3019 if (res
->flags
& IORESOURCE_IO
) {
3020 region
.start
= res
->start
- phb
->ioda
.io_pci_base
;
3021 region
.end
= res
->end
- phb
->ioda
.io_pci_base
;
3022 index
= region
.start
/ phb
->ioda
.io_segsize
;
3024 while (index
< phb
->ioda
.total_pe_num
&&
3025 region
.start
<= region
.end
) {
3026 phb
->ioda
.io_segmap
[index
] = pe
->pe_number
;
3027 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3028 pe
->pe_number
, OPAL_IO_WINDOW_TYPE
, 0, index
);
3029 if (rc
!= OPAL_SUCCESS
) {
3030 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3031 __func__
, rc
, index
, pe
->pe_number
);
3035 region
.start
+= phb
->ioda
.io_segsize
;
3038 } else if ((res
->flags
& IORESOURCE_MEM
) &&
3039 !pnv_pci_is_m64(phb
, res
)) {
3040 region
.start
= res
->start
-
3041 phb
->hose
->mem_offset
[0] -
3042 phb
->ioda
.m32_pci_base
;
3043 region
.end
= res
->end
-
3044 phb
->hose
->mem_offset
[0] -
3045 phb
->ioda
.m32_pci_base
;
3046 index
= region
.start
/ phb
->ioda
.m32_segsize
;
3048 while (index
< phb
->ioda
.total_pe_num
&&
3049 region
.start
<= region
.end
) {
3050 phb
->ioda
.m32_segmap
[index
] = pe
->pe_number
;
3051 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3052 pe
->pe_number
, OPAL_M32_WINDOW_TYPE
, 0, index
);
3053 if (rc
!= OPAL_SUCCESS
) {
3054 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3055 __func__
, rc
, index
, pe
->pe_number
);
3059 region
.start
+= phb
->ioda
.m32_segsize
;
3066 * This function is supposed to be called on basis of PE from top
3067 * to bottom style. So the the I/O or MMIO segment assigned to
3068 * parent PE could be overrided by its child PEs if necessary.
3070 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe
*pe
)
3072 struct pci_dev
*pdev
;
3076 * NOTE: We only care PCI bus based PE for now. For PCI
3077 * device based PE, for example SRIOV sensitive VF should
3078 * be figured out later.
3080 BUG_ON(!(pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
)));
3082 list_for_each_entry(pdev
, &pe
->pbus
->devices
, bus_list
) {
3083 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
3084 pnv_ioda_setup_pe_res(pe
, &pdev
->resource
[i
]);
3087 * If the PE contains all subordinate PCI buses, the
3088 * windows of the child bridges should be mapped to
3091 if (!(pe
->flags
& PNV_IODA_PE_BUS_ALL
) || !pci_is_bridge(pdev
))
3093 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
3094 pnv_ioda_setup_pe_res(pe
,
3095 &pdev
->resource
[PCI_BRIDGE_RESOURCES
+ i
]);
3099 #ifdef CONFIG_DEBUG_FS
3100 static int pnv_pci_diag_data_set(void *data
, u64 val
)
3102 struct pci_controller
*hose
;
3103 struct pnv_phb
*phb
;
3109 hose
= (struct pci_controller
*)data
;
3110 if (!hose
|| !hose
->private_data
)
3113 phb
= hose
->private_data
;
3115 /* Retrieve the diag data from firmware */
3116 ret
= opal_pci_get_phb_diag_data2(phb
->opal_id
, phb
->diag
.blob
,
3117 PNV_PCI_DIAG_BUF_SIZE
);
3118 if (ret
!= OPAL_SUCCESS
)
3121 /* Print the diag data to the kernel log */
3122 pnv_pci_dump_phb_diag_data(phb
->hose
, phb
->diag
.blob
);
3126 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops
, NULL
,
3127 pnv_pci_diag_data_set
, "%llu\n");
3129 #endif /* CONFIG_DEBUG_FS */
3131 static void pnv_pci_ioda_create_dbgfs(void)
3133 #ifdef CONFIG_DEBUG_FS
3134 struct pci_controller
*hose
, *tmp
;
3135 struct pnv_phb
*phb
;
3138 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
3139 phb
= hose
->private_data
;
3141 /* Notify initialization of PHB done */
3142 phb
->initialized
= 1;
3144 sprintf(name
, "PCI%04x", hose
->global_number
);
3145 phb
->dbgfs
= debugfs_create_dir(name
, powerpc_debugfs_root
);
3147 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3148 __func__
, hose
->global_number
);
3152 debugfs_create_file("dump_diag_regs", 0200, phb
->dbgfs
, hose
,
3153 &pnv_pci_diag_data_fops
);
3155 #endif /* CONFIG_DEBUG_FS */
3158 static void pnv_pci_ioda_fixup(void)
3160 pnv_pci_ioda_setup_PEs();
3161 pnv_pci_ioda_setup_iommu_api();
3162 pnv_pci_ioda_create_dbgfs();
3166 eeh_addr_cache_build();
3171 * Returns the alignment for I/O or memory windows for P2P
3172 * bridges. That actually depends on how PEs are segmented.
3173 * For now, we return I/O or M32 segment size for PE sensitive
3174 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3175 * 1MiB for memory) will be returned.
3177 * The current PCI bus might be put into one PE, which was
3178 * create against the parent PCI bridge. For that case, we
3179 * needn't enlarge the alignment so that we can save some
3182 static resource_size_t
pnv_pci_window_alignment(struct pci_bus
*bus
,
3185 struct pci_dev
*bridge
;
3186 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3187 struct pnv_phb
*phb
= hose
->private_data
;
3188 int num_pci_bridges
= 0;
3192 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
3194 if (num_pci_bridges
>= 2)
3198 bridge
= bridge
->bus
->self
;
3202 * We fall back to M32 if M64 isn't supported. We enforce the M64
3203 * alignment for any 64-bit resource, PCIe doesn't care and
3204 * bridges only do 64-bit prefetchable anyway.
3206 if (phb
->ioda
.m64_segsize
&& pnv_pci_is_m64_flags(type
))
3207 return phb
->ioda
.m64_segsize
;
3208 if (type
& IORESOURCE_MEM
)
3209 return phb
->ioda
.m32_segsize
;
3211 return phb
->ioda
.io_segsize
;
3215 * We are updating root port or the upstream port of the
3216 * bridge behind the root port with PHB's windows in order
3217 * to accommodate the changes on required resources during
3218 * PCI (slot) hotplug, which is connected to either root
3219 * port or the downstream ports of PCIe switch behind the
3222 static void pnv_pci_fixup_bridge_resources(struct pci_bus
*bus
,
3225 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3226 struct pnv_phb
*phb
= hose
->private_data
;
3227 struct pci_dev
*bridge
= bus
->self
;
3228 struct resource
*r
, *w
;
3229 bool msi_region
= false;
3232 /* Check if we need apply fixup to the bridge's windows */
3233 if (!pci_is_root_bus(bridge
->bus
) &&
3234 !pci_is_root_bus(bridge
->bus
->self
->bus
))
3237 /* Fixup the resources */
3238 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
3239 r
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
3240 if (!r
->flags
|| !r
->parent
)
3244 if (r
->flags
& type
& IORESOURCE_IO
)
3245 w
= &hose
->io_resource
;
3246 else if (pnv_pci_is_m64(phb
, r
) &&
3247 (type
& IORESOURCE_PREFETCH
) &&
3248 phb
->ioda
.m64_segsize
)
3249 w
= &hose
->mem_resources
[1];
3250 else if (r
->flags
& type
& IORESOURCE_MEM
) {
3251 w
= &hose
->mem_resources
[0];
3255 r
->start
= w
->start
;
3258 /* The 64KB 32-bits MSI region shouldn't be included in
3259 * the 32-bits bridge window. Otherwise, we can see strange
3260 * issues. One of them is EEH error observed on Garrison.
3262 * Exclude top 1MB region which is the minimal alignment of
3263 * 32-bits bridge window.
3272 static void pnv_pci_setup_bridge(struct pci_bus
*bus
, unsigned long type
)
3274 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3275 struct pnv_phb
*phb
= hose
->private_data
;
3276 struct pci_dev
*bridge
= bus
->self
;
3277 struct pnv_ioda_pe
*pe
;
3278 bool all
= (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
);
3280 /* Extend bridge's windows if necessary */
3281 pnv_pci_fixup_bridge_resources(bus
, type
);
3283 /* The PE for root bus should be realized before any one else */
3284 if (!phb
->ioda
.root_pe_populated
) {
3285 pe
= pnv_ioda_setup_bus_PE(phb
->hose
->bus
, false);
3287 phb
->ioda
.root_pe_idx
= pe
->pe_number
;
3288 phb
->ioda
.root_pe_populated
= true;
3292 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3293 if (list_empty(&bus
->devices
))
3296 /* Reserve PEs according to used M64 resources */
3297 if (phb
->reserve_m64_pe
)
3298 phb
->reserve_m64_pe(bus
, NULL
, all
);
3301 * Assign PE. We might run here because of partial hotplug.
3302 * For the case, we just pick up the existing PE and should
3303 * not allocate resources again.
3305 pe
= pnv_ioda_setup_bus_PE(bus
, all
);
3309 pnv_ioda_setup_pe_seg(pe
);
3310 switch (phb
->type
) {
3312 pnv_pci_ioda1_setup_dma_pe(phb
, pe
);
3315 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
3318 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3319 __func__
, phb
->hose
->global_number
, phb
->type
);
3323 #ifdef CONFIG_PCI_IOV
3324 static resource_size_t
pnv_pci_iov_resource_alignment(struct pci_dev
*pdev
,
3327 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
3328 struct pnv_phb
*phb
= hose
->private_data
;
3329 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
3330 resource_size_t align
;
3333 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3334 * SR-IOV. While from hardware perspective, the range mapped by M64
3335 * BAR should be size aligned.
3337 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3338 * powernv-specific hardware restriction is gone. But if just use the
3339 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3340 * in one segment of M64 #15, which introduces the PE conflict between
3341 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3344 * This function returns the total IOV BAR size if M64 BAR is in
3345 * Shared PE mode or just VF BAR size if not.
3346 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3347 * M64 segment size if IOV BAR size is less.
3349 align
= pci_iov_resource_size(pdev
, resno
);
3350 if (!pdn
->vfs_expanded
)
3352 if (pdn
->m64_single_mode
)
3353 return max(align
, (resource_size_t
)phb
->ioda
.m64_segsize
);
3355 return pdn
->vfs_expanded
* align
;
3357 #endif /* CONFIG_PCI_IOV */
3359 /* Prevent enabling devices for which we couldn't properly
3362 bool pnv_pci_enable_device_hook(struct pci_dev
*dev
)
3364 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
3365 struct pnv_phb
*phb
= hose
->private_data
;
3368 /* The function is probably called while the PEs have
3369 * not be created yet. For example, resource reassignment
3370 * during PCI probe period. We just skip the check if
3373 if (!phb
->initialized
)
3376 pdn
= pci_get_pdn(dev
);
3377 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3383 static long pnv_pci_ioda1_unset_window(struct iommu_table_group
*table_group
,
3386 struct pnv_ioda_pe
*pe
= container_of(table_group
,
3387 struct pnv_ioda_pe
, table_group
);
3388 struct pnv_phb
*phb
= pe
->phb
;
3392 pe_info(pe
, "Removing DMA window #%d\n", num
);
3393 for (idx
= 0; idx
< phb
->ioda
.dma32_count
; idx
++) {
3394 if (phb
->ioda
.dma32_segmap
[idx
] != pe
->pe_number
)
3397 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
3398 idx
, 0, 0ul, 0ul, 0ul);
3399 if (rc
!= OPAL_SUCCESS
) {
3400 pe_warn(pe
, "Failure %ld unmapping DMA32 segment#%d\n",
3405 phb
->ioda
.dma32_segmap
[idx
] = IODA_INVALID_PE
;
3408 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
3409 return OPAL_SUCCESS
;
3412 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe
*pe
)
3414 unsigned int weight
= pnv_pci_ioda_pe_dma_weight(pe
);
3415 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
3421 rc
= pnv_pci_ioda1_unset_window(&pe
->table_group
, 0);
3422 if (rc
!= OPAL_SUCCESS
)
3425 pnv_pci_p7ioc_tce_invalidate(tbl
, tbl
->it_offset
, tbl
->it_size
, false);
3426 if (pe
->table_group
.group
) {
3427 iommu_group_put(pe
->table_group
.group
);
3428 WARN_ON(pe
->table_group
.group
);
3431 free_pages(tbl
->it_base
, get_order(tbl
->it_size
<< 3));
3432 iommu_free_table(tbl
, "pnv");
3435 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe
*pe
)
3437 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
3438 unsigned int weight
= pnv_pci_ioda_pe_dma_weight(pe
);
3439 #ifdef CONFIG_IOMMU_API
3446 #ifdef CONFIG_IOMMU_API
3447 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
3449 pe_warn(pe
, "OPAL error %ld release DMA window\n", rc
);
3452 pnv_pci_ioda2_set_bypass(pe
, false);
3453 if (pe
->table_group
.group
) {
3454 iommu_group_put(pe
->table_group
.group
);
3455 WARN_ON(pe
->table_group
.group
);
3458 pnv_pci_ioda2_table_free_pages(tbl
);
3459 iommu_free_table(tbl
, "pnv");
3462 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe
*pe
,
3466 struct pnv_phb
*phb
= pe
->phb
;
3470 for (idx
= 0; idx
< phb
->ioda
.total_pe_num
; idx
++) {
3471 if (map
[idx
] != pe
->pe_number
)
3474 if (win
== OPAL_M64_WINDOW_TYPE
)
3475 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3476 phb
->ioda
.reserved_pe_idx
, win
,
3477 idx
/ PNV_IODA1_M64_SEGS
,
3478 idx
% PNV_IODA1_M64_SEGS
);
3480 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3481 phb
->ioda
.reserved_pe_idx
, win
, 0, idx
);
3483 if (rc
!= OPAL_SUCCESS
)
3484 pe_warn(pe
, "Error %ld unmapping (%d) segment#%d\n",
3487 map
[idx
] = IODA_INVALID_PE
;
3491 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe
*pe
)
3493 struct pnv_phb
*phb
= pe
->phb
;
3495 if (phb
->type
== PNV_PHB_IODA1
) {
3496 pnv_ioda_free_pe_seg(pe
, OPAL_IO_WINDOW_TYPE
,
3497 phb
->ioda
.io_segmap
);
3498 pnv_ioda_free_pe_seg(pe
, OPAL_M32_WINDOW_TYPE
,
3499 phb
->ioda
.m32_segmap
);
3500 pnv_ioda_free_pe_seg(pe
, OPAL_M64_WINDOW_TYPE
,
3501 phb
->ioda
.m64_segmap
);
3502 } else if (phb
->type
== PNV_PHB_IODA2
) {
3503 pnv_ioda_free_pe_seg(pe
, OPAL_M32_WINDOW_TYPE
,
3504 phb
->ioda
.m32_segmap
);
3508 static void pnv_ioda_release_pe(struct pnv_ioda_pe
*pe
)
3510 struct pnv_phb
*phb
= pe
->phb
;
3511 struct pnv_ioda_pe
*slave
, *tmp
;
3513 list_del(&pe
->list
);
3514 switch (phb
->type
) {
3516 pnv_pci_ioda1_release_pe_dma(pe
);
3519 pnv_pci_ioda2_release_pe_dma(pe
);
3525 pnv_ioda_release_pe_seg(pe
);
3526 pnv_ioda_deconfigure_pe(pe
->phb
, pe
);
3528 /* Release slave PEs in the compound PE */
3529 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
3530 list_for_each_entry_safe(slave
, tmp
, &pe
->slaves
, list
) {
3531 list_del(&slave
->list
);
3532 pnv_ioda_free_pe(slave
);
3537 * The PE for root bus can be removed because of hotplug in EEH
3538 * recovery for fenced PHB error. We need to mark the PE dead so
3539 * that it can be populated again in PCI hot add path. The PE
3540 * shouldn't be destroyed as it's the global reserved resource.
3542 if (phb
->ioda
.root_pe_populated
&&
3543 phb
->ioda
.root_pe_idx
== pe
->pe_number
)
3544 phb
->ioda
.root_pe_populated
= false;
3546 pnv_ioda_free_pe(pe
);
3549 static void pnv_pci_release_device(struct pci_dev
*pdev
)
3551 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
3552 struct pnv_phb
*phb
= hose
->private_data
;
3553 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
3554 struct pnv_ioda_pe
*pe
;
3556 if (pdev
->is_virtfn
)
3559 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3563 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3564 * isn't removed and added afterwards in this scenario. We should
3565 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3566 * device count is decreased on removing devices while failing to
3567 * be increased on adding devices. It leads to unbalanced PE's device
3568 * count and eventually make normal PCI hotplug path broken.
3570 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
3571 pdn
->pe_number
= IODA_INVALID_PE
;
3573 WARN_ON(--pe
->device_count
< 0);
3574 if (pe
->device_count
== 0)
3575 pnv_ioda_release_pe(pe
);
3578 static void pnv_pci_ioda_shutdown(struct pci_controller
*hose
)
3580 struct pnv_phb
*phb
= hose
->private_data
;
3582 opal_pci_reset(phb
->opal_id
, OPAL_RESET_PCI_IODA_TABLE
,
3586 static const struct pci_controller_ops pnv_pci_ioda_controller_ops
= {
3587 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3588 .dma_bus_setup
= pnv_pci_dma_bus_setup
,
3589 #ifdef CONFIG_PCI_MSI
3590 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3591 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3593 .enable_device_hook
= pnv_pci_enable_device_hook
,
3594 .release_device
= pnv_pci_release_device
,
3595 .window_alignment
= pnv_pci_window_alignment
,
3596 .setup_bridge
= pnv_pci_setup_bridge
,
3597 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3598 .dma_set_mask
= pnv_pci_ioda_dma_set_mask
,
3599 .dma_get_required_mask
= pnv_pci_ioda_dma_get_required_mask
,
3600 .shutdown
= pnv_pci_ioda_shutdown
,
3603 static int pnv_npu_dma_set_mask(struct pci_dev
*npdev
, u64 dma_mask
)
3605 dev_err_once(&npdev
->dev
,
3606 "%s operation unsupported for NVLink devices\n",
3611 static const struct pci_controller_ops pnv_npu_ioda_controller_ops
= {
3612 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3613 #ifdef CONFIG_PCI_MSI
3614 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3615 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3617 .enable_device_hook
= pnv_pci_enable_device_hook
,
3618 .window_alignment
= pnv_pci_window_alignment
,
3619 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3620 .dma_set_mask
= pnv_npu_dma_set_mask
,
3621 .shutdown
= pnv_pci_ioda_shutdown
,
3624 #ifdef CONFIG_CXL_BASE
3625 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops
= {
3626 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3627 .dma_bus_setup
= pnv_pci_dma_bus_setup
,
3628 #ifdef CONFIG_PCI_MSI
3629 .setup_msi_irqs
= pnv_cxl_cx4_setup_msi_irqs
,
3630 .teardown_msi_irqs
= pnv_cxl_cx4_teardown_msi_irqs
,
3632 .enable_device_hook
= pnv_cxl_enable_device_hook
,
3633 .disable_device
= pnv_cxl_disable_device
,
3634 .release_device
= pnv_pci_release_device
,
3635 .window_alignment
= pnv_pci_window_alignment
,
3636 .setup_bridge
= pnv_pci_setup_bridge
,
3637 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3638 .dma_set_mask
= pnv_pci_ioda_dma_set_mask
,
3639 .dma_get_required_mask
= pnv_pci_ioda_dma_get_required_mask
,
3640 .shutdown
= pnv_pci_ioda_shutdown
,
3644 static void __init
pnv_pci_init_ioda_phb(struct device_node
*np
,
3645 u64 hub_id
, int ioda_type
)
3647 struct pci_controller
*hose
;
3648 struct pnv_phb
*phb
;
3649 unsigned long size
, m64map_off
, m32map_off
, pemap_off
;
3650 unsigned long iomap_off
= 0, dma32map_off
= 0;
3652 const __be64
*prop64
;
3653 const __be32
*prop32
;
3660 if (!of_device_is_available(np
))
3663 pr_info("Initializing %s PHB (%s)\n",
3664 pnv_phb_names
[ioda_type
], of_node_full_name(np
));
3666 prop64
= of_get_property(np
, "ibm,opal-phbid", NULL
);
3668 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3671 phb_id
= be64_to_cpup(prop64
);
3672 pr_debug(" PHB-ID : 0x%016llx\n", phb_id
);
3674 phb
= memblock_virt_alloc(sizeof(struct pnv_phb
), 0);
3676 /* Allocate PCI controller */
3677 phb
->hose
= hose
= pcibios_alloc_controller(np
);
3679 pr_err(" Can't allocate PCI controller for %s\n",
3681 memblock_free(__pa(phb
), sizeof(struct pnv_phb
));
3685 spin_lock_init(&phb
->lock
);
3686 prop32
= of_get_property(np
, "bus-range", &len
);
3687 if (prop32
&& len
== 8) {
3688 hose
->first_busno
= be32_to_cpu(prop32
[0]);
3689 hose
->last_busno
= be32_to_cpu(prop32
[1]);
3691 pr_warn(" Broken <bus-range> on %s\n", np
->full_name
);
3692 hose
->first_busno
= 0;
3693 hose
->last_busno
= 0xff;
3695 hose
->private_data
= phb
;
3696 phb
->hub_id
= hub_id
;
3697 phb
->opal_id
= phb_id
;
3698 phb
->type
= ioda_type
;
3699 mutex_init(&phb
->ioda
.pe_alloc_mutex
);
3701 /* Detect specific models for error handling */
3702 if (of_device_is_compatible(np
, "ibm,p7ioc-pciex"))
3703 phb
->model
= PNV_PHB_MODEL_P7IOC
;
3704 else if (of_device_is_compatible(np
, "ibm,power8-pciex"))
3705 phb
->model
= PNV_PHB_MODEL_PHB3
;
3706 else if (of_device_is_compatible(np
, "ibm,power8-npu-pciex"))
3707 phb
->model
= PNV_PHB_MODEL_NPU
;
3708 else if (of_device_is_compatible(np
, "ibm,power9-npu-pciex"))
3709 phb
->model
= PNV_PHB_MODEL_NPU2
;
3711 phb
->model
= PNV_PHB_MODEL_UNKNOWN
;
3713 /* Parse 32-bit and IO ranges (if any) */
3714 pci_process_bridge_OF_ranges(hose
, np
, !hose
->global_number
);
3717 if (!of_address_to_resource(np
, 0, &r
)) {
3718 phb
->regs_phys
= r
.start
;
3719 phb
->regs
= ioremap(r
.start
, resource_size(&r
));
3720 if (phb
->regs
== NULL
)
3721 pr_err(" Failed to map registers !\n");
3724 /* Initialize more IODA stuff */
3725 phb
->ioda
.total_pe_num
= 1;
3726 prop32
= of_get_property(np
, "ibm,opal-num-pes", NULL
);
3728 phb
->ioda
.total_pe_num
= be32_to_cpup(prop32
);
3729 prop32
= of_get_property(np
, "ibm,opal-reserved-pe", NULL
);
3731 phb
->ioda
.reserved_pe_idx
= be32_to_cpup(prop32
);
3733 /* Invalidate RID to PE# mapping */
3734 for (segno
= 0; segno
< ARRAY_SIZE(phb
->ioda
.pe_rmap
); segno
++)
3735 phb
->ioda
.pe_rmap
[segno
] = IODA_INVALID_PE
;
3737 /* Parse 64-bit MMIO range */
3738 pnv_ioda_parse_m64_window(phb
);
3740 phb
->ioda
.m32_size
= resource_size(&hose
->mem_resources
[0]);
3741 /* FW Has already off top 64k of M32 space (MSI space) */
3742 phb
->ioda
.m32_size
+= 0x10000;
3744 phb
->ioda
.m32_segsize
= phb
->ioda
.m32_size
/ phb
->ioda
.total_pe_num
;
3745 phb
->ioda
.m32_pci_base
= hose
->mem_resources
[0].start
- hose
->mem_offset
[0];
3746 phb
->ioda
.io_size
= hose
->pci_io_size
;
3747 phb
->ioda
.io_segsize
= phb
->ioda
.io_size
/ phb
->ioda
.total_pe_num
;
3748 phb
->ioda
.io_pci_base
= 0; /* XXX calculate this ? */
3750 /* Calculate how many 32-bit TCE segments we have */
3751 phb
->ioda
.dma32_count
= phb
->ioda
.m32_pci_base
/
3752 PNV_IODA1_DMA32_SEGSIZE
;
3754 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3755 size
= _ALIGN_UP(max_t(unsigned, phb
->ioda
.total_pe_num
, 8) / 8,
3756 sizeof(unsigned long));
3758 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.m64_segmap
[0]);
3760 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.m32_segmap
[0]);
3761 if (phb
->type
== PNV_PHB_IODA1
) {
3763 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.io_segmap
[0]);
3764 dma32map_off
= size
;
3765 size
+= phb
->ioda
.dma32_count
*
3766 sizeof(phb
->ioda
.dma32_segmap
[0]);
3769 size
+= phb
->ioda
.total_pe_num
* sizeof(struct pnv_ioda_pe
);
3770 aux
= memblock_virt_alloc(size
, 0);
3771 phb
->ioda
.pe_alloc
= aux
;
3772 phb
->ioda
.m64_segmap
= aux
+ m64map_off
;
3773 phb
->ioda
.m32_segmap
= aux
+ m32map_off
;
3774 for (segno
= 0; segno
< phb
->ioda
.total_pe_num
; segno
++) {
3775 phb
->ioda
.m64_segmap
[segno
] = IODA_INVALID_PE
;
3776 phb
->ioda
.m32_segmap
[segno
] = IODA_INVALID_PE
;
3778 if (phb
->type
== PNV_PHB_IODA1
) {
3779 phb
->ioda
.io_segmap
= aux
+ iomap_off
;
3780 for (segno
= 0; segno
< phb
->ioda
.total_pe_num
; segno
++)
3781 phb
->ioda
.io_segmap
[segno
] = IODA_INVALID_PE
;
3783 phb
->ioda
.dma32_segmap
= aux
+ dma32map_off
;
3784 for (segno
= 0; segno
< phb
->ioda
.dma32_count
; segno
++)
3785 phb
->ioda
.dma32_segmap
[segno
] = IODA_INVALID_PE
;
3787 phb
->ioda
.pe_array
= aux
+ pemap_off
;
3790 * Choose PE number for root bus, which shouldn't have
3791 * M64 resources consumed by its child devices. To pick
3792 * the PE number adjacent to the reserved one if possible.
3794 pnv_ioda_reserve_pe(phb
, phb
->ioda
.reserved_pe_idx
);
3795 if (phb
->ioda
.reserved_pe_idx
== 0) {
3796 phb
->ioda
.root_pe_idx
= 1;
3797 pnv_ioda_reserve_pe(phb
, phb
->ioda
.root_pe_idx
);
3798 } else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1)) {
3799 phb
->ioda
.root_pe_idx
= phb
->ioda
.reserved_pe_idx
- 1;
3800 pnv_ioda_reserve_pe(phb
, phb
->ioda
.root_pe_idx
);
3802 phb
->ioda
.root_pe_idx
= IODA_INVALID_PE
;
3805 INIT_LIST_HEAD(&phb
->ioda
.pe_list
);
3806 mutex_init(&phb
->ioda
.pe_list_mutex
);
3808 /* Calculate how many 32-bit TCE segments we have */
3809 phb
->ioda
.dma32_count
= phb
->ioda
.m32_pci_base
/
3810 PNV_IODA1_DMA32_SEGSIZE
;
3812 #if 0 /* We should really do that ... */
3813 rc
= opal_pci_set_phb_mem_window(opal
->phb_id
,
3816 starting_real_address
,
3817 starting_pci_address
,
3821 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3822 phb
->ioda
.total_pe_num
, phb
->ioda
.reserved_pe_idx
,
3823 phb
->ioda
.m32_size
, phb
->ioda
.m32_segsize
);
3824 if (phb
->ioda
.m64_size
)
3825 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3826 phb
->ioda
.m64_size
, phb
->ioda
.m64_segsize
);
3827 if (phb
->ioda
.io_size
)
3828 pr_info(" IO: 0x%x [segment=0x%x]\n",
3829 phb
->ioda
.io_size
, phb
->ioda
.io_segsize
);
3832 phb
->hose
->ops
= &pnv_pci_ops
;
3833 phb
->get_pe_state
= pnv_ioda_get_pe_state
;
3834 phb
->freeze_pe
= pnv_ioda_freeze_pe
;
3835 phb
->unfreeze_pe
= pnv_ioda_unfreeze_pe
;
3837 /* Setup MSI support */
3838 pnv_pci_init_ioda_msis(phb
);
3841 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3842 * to let the PCI core do resource assignment. It's supposed
3843 * that the PCI core will do correct I/O and MMIO alignment
3844 * for the P2P bridge bars so that each PCI bus (excluding
3845 * the child P2P bridges) can form individual PE.
3847 ppc_md
.pcibios_fixup
= pnv_pci_ioda_fixup
;
3849 if (phb
->type
== PNV_PHB_NPU
) {
3850 hose
->controller_ops
= pnv_npu_ioda_controller_ops
;
3852 phb
->dma_dev_setup
= pnv_pci_ioda_dma_dev_setup
;
3853 hose
->controller_ops
= pnv_pci_ioda_controller_ops
;
3856 #ifdef CONFIG_PCI_IOV
3857 ppc_md
.pcibios_fixup_sriov
= pnv_pci_ioda_fixup_iov_resources
;
3858 ppc_md
.pcibios_iov_resource_alignment
= pnv_pci_iov_resource_alignment
;
3861 pci_add_flags(PCI_REASSIGN_ALL_RSRC
);
3863 /* Reset IODA tables to a clean state */
3864 rc
= opal_pci_reset(phb_id
, OPAL_RESET_PCI_IODA_TABLE
, OPAL_ASSERT_RESET
);
3866 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc
);
3869 * If we're running in kdump kernel, the previous kernel never
3870 * shutdown PCI devices correctly. We already got IODA table
3871 * cleaned out. So we have to issue PHB reset to stop all PCI
3872 * transactions from previous kernel.
3874 if (is_kdump_kernel()) {
3875 pr_info(" Issue PHB reset ...\n");
3876 pnv_eeh_phb_reset(hose
, EEH_RESET_FUNDAMENTAL
);
3877 pnv_eeh_phb_reset(hose
, EEH_RESET_DEACTIVATE
);
3880 /* Remove M64 resource if we can't configure it successfully */
3881 if (!phb
->init_m64
|| phb
->init_m64(phb
))
3882 hose
->mem_resources
[1].flags
= 0;
3885 void __init
pnv_pci_init_ioda2_phb(struct device_node
*np
)
3887 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_IODA2
);
3890 void __init
pnv_pci_init_npu_phb(struct device_node
*np
)
3892 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_NPU
);
3895 void __init
pnv_pci_init_ioda_hub(struct device_node
*np
)
3897 struct device_node
*phbn
;
3898 const __be64
*prop64
;
3901 pr_info("Probing IODA IO-Hub %s\n", np
->full_name
);
3903 prop64
= of_get_property(np
, "ibm,opal-hubid", NULL
);
3905 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3908 hub_id
= be64_to_cpup(prop64
);
3909 pr_devel(" HUB-ID : 0x%016llx\n", hub_id
);
3911 /* Count child PHBs */
3912 for_each_child_of_node(np
, phbn
) {
3913 /* Look for IODA1 PHBs */
3914 if (of_device_is_compatible(phbn
, "ibm,ioda-phb"))
3915 pnv_pci_init_ioda_phb(phbn
, hub_id
, PNV_PHB_IODA1
);