2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk.h>
40 #include <linux/clk/bcm2835.h>
41 #include <linux/debugfs.h>
42 #include <linux/module.h>
44 #include <linux/platform_device.h>
45 #include <linux/slab.h>
46 #include <dt-bindings/clock/bcm2835.h>
47 #include <soc/bcm2835/raspberrypi-firmware.h>
49 #define CM_PASSWORD 0x5a000000
51 #define CM_GNRICCTL 0x000
52 #define CM_GNRICDIV 0x004
53 # define CM_DIV_FRAC_BITS 12
54 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
56 #define CM_VPUCTL 0x008
57 #define CM_VPUDIV 0x00c
58 #define CM_SYSCTL 0x010
59 #define CM_SYSDIV 0x014
60 #define CM_PERIACTL 0x018
61 #define CM_PERIADIV 0x01c
62 #define CM_PERIICTL 0x020
63 #define CM_PERIIDIV 0x024
64 #define CM_H264CTL 0x028
65 #define CM_H264DIV 0x02c
66 #define CM_ISPCTL 0x030
67 #define CM_ISPDIV 0x034
68 #define CM_V3DCTL 0x038
69 #define CM_V3DDIV 0x03c
70 #define CM_CAM0CTL 0x040
71 #define CM_CAM0DIV 0x044
72 #define CM_CAM1CTL 0x048
73 #define CM_CAM1DIV 0x04c
74 #define CM_CCP2CTL 0x050
75 #define CM_CCP2DIV 0x054
76 #define CM_DSI0ECTL 0x058
77 #define CM_DSI0EDIV 0x05c
78 #define CM_DSI0PCTL 0x060
79 #define CM_DSI0PDIV 0x064
80 #define CM_DPICTL 0x068
81 #define CM_DPIDIV 0x06c
82 #define CM_GP0CTL 0x070
83 #define CM_GP0DIV 0x074
84 #define CM_GP1CTL 0x078
85 #define CM_GP1DIV 0x07c
86 #define CM_GP2CTL 0x080
87 #define CM_GP2DIV 0x084
88 #define CM_HSMCTL 0x088
89 #define CM_HSMDIV 0x08c
90 #define CM_OTPCTL 0x090
91 #define CM_OTPDIV 0x094
92 #define CM_PCMCTL 0x098
93 #define CM_PCMDIV 0x09c
94 #define CM_PWMCTL 0x0a0
95 #define CM_PWMDIV 0x0a4
96 #define CM_SLIMCTL 0x0a8
97 #define CM_SLIMDIV 0x0ac
98 #define CM_SMICTL 0x0b0
99 #define CM_SMIDIV 0x0b4
100 /* no definition for 0x0b8 and 0x0bc */
101 #define CM_TCNTCTL 0x0c0
102 #define CM_TCNTDIV 0x0c4
103 #define CM_TECCTL 0x0c8
104 #define CM_TECDIV 0x0cc
105 #define CM_TD0CTL 0x0d0
106 #define CM_TD0DIV 0x0d4
107 #define CM_TD1CTL 0x0d8
108 #define CM_TD1DIV 0x0dc
109 #define CM_TSENSCTL 0x0e0
110 #define CM_TSENSDIV 0x0e4
111 #define CM_TIMERCTL 0x0e8
112 #define CM_TIMERDIV 0x0ec
113 #define CM_UARTCTL 0x0f0
114 #define CM_UARTDIV 0x0f4
115 #define CM_VECCTL 0x0f8
116 #define CM_VECDIV 0x0fc
117 #define CM_PULSECTL 0x190
118 #define CM_PULSEDIV 0x194
119 #define CM_SDCCTL 0x1a8
120 #define CM_SDCDIV 0x1ac
121 #define CM_ARMCTL 0x1b0
122 #define CM_AVEOCTL 0x1b8
123 #define CM_AVEODIV 0x1bc
124 #define CM_EMMCCTL 0x1c0
125 #define CM_EMMCDIV 0x1c4
127 /* General bits for the CM_*CTL regs */
128 # define CM_ENABLE BIT(4)
129 # define CM_KILL BIT(5)
130 # define CM_GATE_BIT 6
131 # define CM_GATE BIT(CM_GATE_BIT)
132 # define CM_BUSY BIT(7)
133 # define CM_BUSYD BIT(8)
134 # define CM_FRAC BIT(9)
135 # define CM_SRC_SHIFT 0
136 # define CM_SRC_BITS 4
137 # define CM_SRC_MASK 0xf
138 # define CM_SRC_GND 0
139 # define CM_SRC_OSC 1
140 # define CM_SRC_TESTDEBUG0 2
141 # define CM_SRC_TESTDEBUG1 3
142 # define CM_SRC_PLLA_CORE 4
143 # define CM_SRC_PLLA_PER 4
144 # define CM_SRC_PLLC_CORE0 5
145 # define CM_SRC_PLLC_PER 5
146 # define CM_SRC_PLLC_CORE1 8
147 # define CM_SRC_PLLD_CORE 6
148 # define CM_SRC_PLLD_PER 6
149 # define CM_SRC_PLLH_AUX 7
150 # define CM_SRC_PLLC_CORE1 8
151 # define CM_SRC_PLLC_CORE2 9
153 #define CM_OSCCOUNT 0x100
155 #define CM_PLLA 0x104
156 # define CM_PLL_ANARST BIT(8)
157 # define CM_PLLA_HOLDPER BIT(7)
158 # define CM_PLLA_LOADPER BIT(6)
159 # define CM_PLLA_HOLDCORE BIT(5)
160 # define CM_PLLA_LOADCORE BIT(4)
161 # define CM_PLLA_HOLDCCP2 BIT(3)
162 # define CM_PLLA_LOADCCP2 BIT(2)
163 # define CM_PLLA_HOLDDSI0 BIT(1)
164 # define CM_PLLA_LOADDSI0 BIT(0)
166 #define CM_PLLC 0x108
167 # define CM_PLLC_HOLDPER BIT(7)
168 # define CM_PLLC_LOADPER BIT(6)
169 # define CM_PLLC_HOLDCORE2 BIT(5)
170 # define CM_PLLC_LOADCORE2 BIT(4)
171 # define CM_PLLC_HOLDCORE1 BIT(3)
172 # define CM_PLLC_LOADCORE1 BIT(2)
173 # define CM_PLLC_HOLDCORE0 BIT(1)
174 # define CM_PLLC_LOADCORE0 BIT(0)
176 #define CM_PLLD 0x10c
177 # define CM_PLLD_HOLDPER BIT(7)
178 # define CM_PLLD_LOADPER BIT(6)
179 # define CM_PLLD_HOLDCORE BIT(5)
180 # define CM_PLLD_LOADCORE BIT(4)
181 # define CM_PLLD_HOLDDSI1 BIT(3)
182 # define CM_PLLD_LOADDSI1 BIT(2)
183 # define CM_PLLD_HOLDDSI0 BIT(1)
184 # define CM_PLLD_LOADDSI0 BIT(0)
186 #define CM_PLLH 0x110
187 # define CM_PLLH_LOADRCAL BIT(2)
188 # define CM_PLLH_LOADAUX BIT(1)
189 # define CM_PLLH_LOADPIX BIT(0)
191 #define CM_LOCK 0x114
192 # define CM_LOCK_FLOCKH BIT(12)
193 # define CM_LOCK_FLOCKD BIT(11)
194 # define CM_LOCK_FLOCKC BIT(10)
195 # define CM_LOCK_FLOCKB BIT(9)
196 # define CM_LOCK_FLOCKA BIT(8)
198 #define CM_EVENT 0x118
199 #define CM_DSI1ECTL 0x158
200 #define CM_DSI1EDIV 0x15c
201 #define CM_DSI1PCTL 0x160
202 #define CM_DSI1PDIV 0x164
203 #define CM_DFTCTL 0x168
204 #define CM_DFTDIV 0x16c
206 #define CM_PLLB 0x170
207 # define CM_PLLB_HOLDARM BIT(1)
208 # define CM_PLLB_LOADARM BIT(0)
210 #define A2W_PLLA_CTRL 0x1100
211 #define A2W_PLLC_CTRL 0x1120
212 #define A2W_PLLD_CTRL 0x1140
213 #define A2W_PLLH_CTRL 0x1160
214 #define A2W_PLLB_CTRL 0x11e0
215 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
216 # define A2W_PLL_CTRL_PWRDN BIT(16)
217 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
218 # define A2W_PLL_CTRL_PDIV_SHIFT 12
219 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
220 # define A2W_PLL_CTRL_NDIV_SHIFT 0
222 #define A2W_PLLA_ANA0 0x1010
223 #define A2W_PLLC_ANA0 0x1030
224 #define A2W_PLLD_ANA0 0x1050
225 #define A2W_PLLH_ANA0 0x1070
226 #define A2W_PLLB_ANA0 0x10f0
228 #define A2W_PLL_KA_SHIFT 7
229 #define A2W_PLL_KA_MASK GENMASK(9, 7)
230 #define A2W_PLL_KI_SHIFT 19
231 #define A2W_PLL_KI_MASK GENMASK(21, 19)
232 #define A2W_PLL_KP_SHIFT 15
233 #define A2W_PLL_KP_MASK GENMASK(18, 15)
235 #define A2W_PLLH_KA_SHIFT 19
236 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
237 #define A2W_PLLH_KI_LOW_SHIFT 22
238 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
239 #define A2W_PLLH_KI_HIGH_SHIFT 0
240 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
241 #define A2W_PLLH_KP_SHIFT 1
242 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
244 #define A2W_XOSC_CTRL 0x1190
245 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
246 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
247 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
248 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
249 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
250 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
251 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
252 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
254 #define A2W_PLLA_FRAC 0x1200
255 #define A2W_PLLC_FRAC 0x1220
256 #define A2W_PLLD_FRAC 0x1240
257 #define A2W_PLLH_FRAC 0x1260
258 #define A2W_PLLB_FRAC 0x12e0
259 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
260 # define A2W_PLL_FRAC_BITS 20
262 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
263 #define A2W_PLL_DIV_BITS 8
264 #define A2W_PLL_DIV_SHIFT 0
266 #define A2W_PLLA_DSI0 0x1300
267 #define A2W_PLLA_CORE 0x1400
268 #define A2W_PLLA_PER 0x1500
269 #define A2W_PLLA_CCP2 0x1600
271 #define A2W_PLLC_CORE2 0x1320
272 #define A2W_PLLC_CORE1 0x1420
273 #define A2W_PLLC_PER 0x1520
274 #define A2W_PLLC_CORE0 0x1620
276 #define A2W_PLLD_DSI0 0x1340
277 #define A2W_PLLD_CORE 0x1440
278 #define A2W_PLLD_PER 0x1540
279 #define A2W_PLLD_DSI1 0x1640
281 #define A2W_PLLH_AUX 0x1360
282 #define A2W_PLLH_RCAL 0x1460
283 #define A2W_PLLH_PIX 0x1560
284 #define A2W_PLLH_STS 0x1660
286 #define A2W_PLLH_CTRLR 0x1960
287 #define A2W_PLLH_FRACR 0x1a60
288 #define A2W_PLLH_AUXR 0x1b60
289 #define A2W_PLLH_RCALR 0x1c60
290 #define A2W_PLLH_PIXR 0x1d60
291 #define A2W_PLLH_STSR 0x1e60
293 #define A2W_PLLB_ARM 0x13e0
294 #define A2W_PLLB_SP0 0x14e0
295 #define A2W_PLLB_SP1 0x15e0
296 #define A2W_PLLB_SP2 0x16e0
298 #define LOCK_TIMEOUT_NS 100000000
299 #define BCM2835_MAX_FB_RATE 1750000000u
301 #define VCMSG_ID_CORE_CLOCK 4
303 struct bcm2835_cprman
{
306 struct rpi_firmware
*fw
;
307 spinlock_t regs_lock
; /* spinlock for all clocks */
308 const char *osc_name
;
311 struct clk_hw_onecell_data onecell
;
314 static inline void cprman_write(struct bcm2835_cprman
*cprman
, u32 reg
, u32 val
)
316 writel(CM_PASSWORD
| val
, cprman
->regs
+ reg
);
319 static inline u32
cprman_read(struct bcm2835_cprman
*cprman
, u32 reg
)
321 return readl(cprman
->regs
+ reg
);
324 static int bcm2835_debugfs_regset(struct bcm2835_cprman
*cprman
, u32 base
,
325 struct debugfs_reg32
*regs
, size_t nregs
,
326 struct dentry
*dentry
)
328 struct dentry
*regdump
;
329 struct debugfs_regset32
*regset
;
331 regset
= devm_kzalloc(cprman
->dev
, sizeof(*regset
), GFP_KERNEL
);
336 regset
->nregs
= nregs
;
337 regset
->base
= cprman
->regs
+ base
;
339 regdump
= debugfs_create_regset32("regdump", S_IRUGO
, dentry
,
342 return regdump
? 0 : -ENOMEM
;
346 * These are fixed clocks. They're probably not all root clocks and it may
347 * be possible to turn them on and off but until this is mapped out better
348 * it's the only way they can be used.
350 void __init
bcm2835_init_clocks(void)
355 hw
= clk_hw_register_fixed_rate(NULL
, "apb_pclk", NULL
, 0, 126000000);
357 pr_err("apb_pclk not registered\n");
359 hw
= clk_hw_register_fixed_rate(NULL
, "uart0_pclk", NULL
, 0, 3000000);
361 pr_err("uart0_pclk not registered\n");
362 ret
= clk_hw_register_clkdev(hw
, NULL
, "20201000.uart");
364 pr_err("uart0_pclk alias not registered\n");
366 hw
= clk_hw_register_fixed_rate(NULL
, "uart1_pclk", NULL
, 0, 125000000);
368 pr_err("uart1_pclk not registered\n");
369 ret
= clk_hw_register_clkdev(hw
, NULL
, "20215000.uart");
371 pr_err("uart1_pclk alias not registered\n");
374 struct bcm2835_pll_data
{
380 u32 reference_enable_mask
;
381 /* Bit in CM_LOCK to indicate when the PLL has locked. */
384 const struct bcm2835_pll_ana_bits
*ana
;
386 unsigned long min_rate
;
387 unsigned long max_rate
;
389 * Highest rate for the VCO before we have to use the
392 unsigned long max_fb_rate
;
395 struct bcm2835_pll_ana_bits
{
405 static const struct bcm2835_pll_ana_bits bcm2835_ana_default
= {
408 .mask1
= (u32
)~(A2W_PLL_KI_MASK
| A2W_PLL_KP_MASK
),
409 .set1
= (2 << A2W_PLL_KI_SHIFT
) | (8 << A2W_PLL_KP_SHIFT
),
410 .mask3
= (u32
)~A2W_PLL_KA_MASK
,
411 .set3
= (2 << A2W_PLL_KA_SHIFT
),
412 .fb_prediv_mask
= BIT(14),
415 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh
= {
416 .mask0
= (u32
)~(A2W_PLLH_KA_MASK
| A2W_PLLH_KI_LOW_MASK
),
417 .set0
= (2 << A2W_PLLH_KA_SHIFT
) | (2 << A2W_PLLH_KI_LOW_SHIFT
),
418 .mask1
= (u32
)~(A2W_PLLH_KI_HIGH_MASK
| A2W_PLLH_KP_MASK
),
419 .set1
= (6 << A2W_PLLH_KP_SHIFT
),
422 .fb_prediv_mask
= BIT(11),
425 struct bcm2835_pll_divider_data
{
427 const char *source_pll
;
438 struct bcm2835_clock_data
{
441 const char *const *parents
;
444 /* Bitmap encoding which parents accept rate change propagation. */
445 unsigned int set_rate_parent
;
450 /* Number of integer bits in the divider */
452 /* Number of fractional bits in the divider */
461 struct bcm2835_gate_data
{
470 struct bcm2835_cprman
*cprman
;
471 const struct bcm2835_pll_data
*data
;
474 static int bcm2835_pll_is_on(struct clk_hw
*hw
)
476 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
477 struct bcm2835_cprman
*cprman
= pll
->cprman
;
478 const struct bcm2835_pll_data
*data
= pll
->data
;
480 return cprman_read(cprman
, data
->a2w_ctrl_reg
) &
481 A2W_PLL_CTRL_PRST_DISABLE
;
484 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate
,
485 unsigned long parent_rate
,
486 u32
*ndiv
, u32
*fdiv
)
490 div
= (u64
)rate
<< A2W_PLL_FRAC_BITS
;
491 do_div(div
, parent_rate
);
493 *ndiv
= div
>> A2W_PLL_FRAC_BITS
;
494 *fdiv
= div
& ((1 << A2W_PLL_FRAC_BITS
) - 1);
497 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate
,
498 u32 ndiv
, u32 fdiv
, u32 pdiv
)
505 rate
= (u64
)parent_rate
* ((ndiv
<< A2W_PLL_FRAC_BITS
) + fdiv
);
507 return rate
>> A2W_PLL_FRAC_BITS
;
510 static long bcm2835_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
511 unsigned long *parent_rate
)
513 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
514 const struct bcm2835_pll_data
*data
= pll
->data
;
517 rate
= clamp(rate
, data
->min_rate
, data
->max_rate
);
519 bcm2835_pll_choose_ndiv_and_fdiv(rate
, *parent_rate
, &ndiv
, &fdiv
);
521 return bcm2835_pll_rate_from_divisors(*parent_rate
, ndiv
, fdiv
, 1);
524 static unsigned long bcm2835_pll_get_rate(struct clk_hw
*hw
,
525 unsigned long parent_rate
)
527 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
528 struct bcm2835_cprman
*cprman
= pll
->cprman
;
529 const struct bcm2835_pll_data
*data
= pll
->data
;
530 u32 a2wctrl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
531 u32 ndiv
, pdiv
, fdiv
;
534 if (parent_rate
== 0)
537 fdiv
= cprman_read(cprman
, data
->frac_reg
) & A2W_PLL_FRAC_MASK
;
538 ndiv
= (a2wctrl
& A2W_PLL_CTRL_NDIV_MASK
) >> A2W_PLL_CTRL_NDIV_SHIFT
;
539 pdiv
= (a2wctrl
& A2W_PLL_CTRL_PDIV_MASK
) >> A2W_PLL_CTRL_PDIV_SHIFT
;
540 using_prediv
= cprman_read(cprman
, data
->ana_reg_base
+ 4) &
541 data
->ana
->fb_prediv_mask
;
548 return bcm2835_pll_rate_from_divisors(parent_rate
, ndiv
, fdiv
, pdiv
);
551 static void bcm2835_pll_off(struct clk_hw
*hw
)
553 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
554 struct bcm2835_cprman
*cprman
= pll
->cprman
;
555 const struct bcm2835_pll_data
*data
= pll
->data
;
557 spin_lock(&cprman
->regs_lock
);
558 cprman_write(cprman
, data
->cm_ctrl_reg
,
559 cprman_read(cprman
, data
->cm_ctrl_reg
) |
561 cprman_write(cprman
, data
->a2w_ctrl_reg
,
562 cprman_read(cprman
, data
->a2w_ctrl_reg
) |
564 spin_unlock(&cprman
->regs_lock
);
567 static int bcm2835_pll_on(struct clk_hw
*hw
)
569 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
570 struct bcm2835_cprman
*cprman
= pll
->cprman
;
571 const struct bcm2835_pll_data
*data
= pll
->data
;
574 cprman_write(cprman
, data
->a2w_ctrl_reg
,
575 cprman_read(cprman
, data
->a2w_ctrl_reg
) &
576 ~A2W_PLL_CTRL_PWRDN
);
578 /* Take the PLL out of reset. */
579 cprman_write(cprman
, data
->cm_ctrl_reg
,
580 cprman_read(cprman
, data
->cm_ctrl_reg
) & ~CM_PLL_ANARST
);
582 /* Wait for the PLL to lock. */
583 timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
584 while (!(cprman_read(cprman
, CM_LOCK
) & data
->lock_mask
)) {
585 if (ktime_after(ktime_get(), timeout
)) {
586 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
587 clk_hw_get_name(hw
));
598 bcm2835_pll_write_ana(struct bcm2835_cprman
*cprman
, u32 ana_reg_base
, u32
*ana
)
603 * ANA register setup is done as a series of writes to
604 * ANA3-ANA0, in that order. This lets us write all 4
605 * registers as a single cycle of the serdes interface (taking
606 * 100 xosc clocks), whereas if we were to update ana0, 1, and
607 * 3 individually through their partial-write registers, each
608 * would be their own serdes cycle.
610 for (i
= 3; i
>= 0; i
--)
611 cprman_write(cprman
, ana_reg_base
+ i
* 4, ana
[i
]);
614 static int bcm2835_pll_set_rate(struct clk_hw
*hw
,
615 unsigned long rate
, unsigned long parent_rate
)
617 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
618 struct bcm2835_cprman
*cprman
= pll
->cprman
;
619 const struct bcm2835_pll_data
*data
= pll
->data
;
620 bool was_using_prediv
, use_fb_prediv
, do_ana_setup_first
;
621 u32 ndiv
, fdiv
, a2w_ctl
;
625 if (rate
> data
->max_fb_rate
) {
626 use_fb_prediv
= true;
629 use_fb_prediv
= false;
632 bcm2835_pll_choose_ndiv_and_fdiv(rate
, parent_rate
, &ndiv
, &fdiv
);
634 for (i
= 3; i
>= 0; i
--)
635 ana
[i
] = cprman_read(cprman
, data
->ana_reg_base
+ i
* 4);
637 was_using_prediv
= ana
[1] & data
->ana
->fb_prediv_mask
;
639 ana
[0] &= ~data
->ana
->mask0
;
640 ana
[0] |= data
->ana
->set0
;
641 ana
[1] &= ~data
->ana
->mask1
;
642 ana
[1] |= data
->ana
->set1
;
643 ana
[3] &= ~data
->ana
->mask3
;
644 ana
[3] |= data
->ana
->set3
;
646 if (was_using_prediv
&& !use_fb_prediv
) {
647 ana
[1] &= ~data
->ana
->fb_prediv_mask
;
648 do_ana_setup_first
= true;
649 } else if (!was_using_prediv
&& use_fb_prediv
) {
650 ana
[1] |= data
->ana
->fb_prediv_mask
;
651 do_ana_setup_first
= false;
653 do_ana_setup_first
= true;
656 /* Unmask the reference clock from the oscillator. */
657 cprman_write(cprman
, A2W_XOSC_CTRL
,
658 cprman_read(cprman
, A2W_XOSC_CTRL
) |
659 data
->reference_enable_mask
);
661 if (do_ana_setup_first
)
662 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
664 /* Set the PLL multiplier from the oscillator. */
665 cprman_write(cprman
, data
->frac_reg
, fdiv
);
667 a2w_ctl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
668 a2w_ctl
&= ~A2W_PLL_CTRL_NDIV_MASK
;
669 a2w_ctl
|= ndiv
<< A2W_PLL_CTRL_NDIV_SHIFT
;
670 a2w_ctl
&= ~A2W_PLL_CTRL_PDIV_MASK
;
671 a2w_ctl
|= 1 << A2W_PLL_CTRL_PDIV_SHIFT
;
672 cprman_write(cprman
, data
->a2w_ctrl_reg
, a2w_ctl
);
674 if (!do_ana_setup_first
)
675 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
680 static int bcm2835_pll_debug_init(struct clk_hw
*hw
,
681 struct dentry
*dentry
)
683 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
684 struct bcm2835_cprman
*cprman
= pll
->cprman
;
685 const struct bcm2835_pll_data
*data
= pll
->data
;
686 struct debugfs_reg32
*regs
;
688 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
692 regs
[0].name
= "cm_ctrl";
693 regs
[0].offset
= data
->cm_ctrl_reg
;
694 regs
[1].name
= "a2w_ctrl";
695 regs
[1].offset
= data
->a2w_ctrl_reg
;
696 regs
[2].name
= "frac";
697 regs
[2].offset
= data
->frac_reg
;
698 regs
[3].name
= "ana0";
699 regs
[3].offset
= data
->ana_reg_base
+ 0 * 4;
700 regs
[4].name
= "ana1";
701 regs
[4].offset
= data
->ana_reg_base
+ 1 * 4;
702 regs
[5].name
= "ana2";
703 regs
[5].offset
= data
->ana_reg_base
+ 2 * 4;
704 regs
[6].name
= "ana3";
705 regs
[6].offset
= data
->ana_reg_base
+ 3 * 4;
707 return bcm2835_debugfs_regset(cprman
, 0, regs
, 7, dentry
);
710 static const struct clk_ops bcm2835_pll_clk_ops
= {
711 .is_prepared
= bcm2835_pll_is_on
,
712 .prepare
= bcm2835_pll_on
,
713 .unprepare
= bcm2835_pll_off
,
714 .recalc_rate
= bcm2835_pll_get_rate
,
715 .set_rate
= bcm2835_pll_set_rate
,
716 .round_rate
= bcm2835_pll_round_rate
,
717 .debug_init
= bcm2835_pll_debug_init
,
720 struct bcm2835_pll_divider
{
721 struct clk_divider div
;
722 struct bcm2835_cprman
*cprman
;
723 const struct bcm2835_pll_divider_data
*data
;
726 static struct bcm2835_pll_divider
*
727 bcm2835_pll_divider_from_hw(struct clk_hw
*hw
)
729 return container_of(hw
, struct bcm2835_pll_divider
, div
.hw
);
732 static int bcm2835_pll_divider_is_on(struct clk_hw
*hw
)
734 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
735 struct bcm2835_cprman
*cprman
= divider
->cprman
;
736 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
738 return !(cprman_read(cprman
, data
->a2w_reg
) & A2W_PLL_CHANNEL_DISABLE
);
741 static long bcm2835_pll_divider_round_rate(struct clk_hw
*hw
,
743 unsigned long *parent_rate
)
745 return clk_divider_ops
.round_rate(hw
, rate
, parent_rate
);
748 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw
*hw
,
749 unsigned long parent_rate
)
751 return clk_divider_ops
.recalc_rate(hw
, parent_rate
);
754 static void bcm2835_pll_divider_off(struct clk_hw
*hw
)
756 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
757 struct bcm2835_cprman
*cprman
= divider
->cprman
;
758 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
760 spin_lock(&cprman
->regs_lock
);
761 cprman_write(cprman
, data
->cm_reg
,
762 (cprman_read(cprman
, data
->cm_reg
) &
763 ~data
->load_mask
) | data
->hold_mask
);
764 cprman_write(cprman
, data
->a2w_reg
,
765 cprman_read(cprman
, data
->a2w_reg
) |
766 A2W_PLL_CHANNEL_DISABLE
);
767 spin_unlock(&cprman
->regs_lock
);
770 static int bcm2835_pll_divider_on(struct clk_hw
*hw
)
772 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
773 struct bcm2835_cprman
*cprman
= divider
->cprman
;
774 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
776 spin_lock(&cprman
->regs_lock
);
777 cprman_write(cprman
, data
->a2w_reg
,
778 cprman_read(cprman
, data
->a2w_reg
) &
779 ~A2W_PLL_CHANNEL_DISABLE
);
781 cprman_write(cprman
, data
->cm_reg
,
782 cprman_read(cprman
, data
->cm_reg
) & ~data
->hold_mask
);
783 spin_unlock(&cprman
->regs_lock
);
788 static int bcm2835_pll_divider_set_rate(struct clk_hw
*hw
,
790 unsigned long parent_rate
)
792 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
793 struct bcm2835_cprman
*cprman
= divider
->cprman
;
794 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
795 u32 cm
, div
, max_div
= 1 << A2W_PLL_DIV_BITS
;
797 div
= DIV_ROUND_UP_ULL(parent_rate
, rate
);
799 div
= min(div
, max_div
);
803 cprman_write(cprman
, data
->a2w_reg
, div
);
804 cm
= cprman_read(cprman
, data
->cm_reg
);
805 cprman_write(cprman
, data
->cm_reg
, cm
| data
->load_mask
);
806 cprman_write(cprman
, data
->cm_reg
, cm
& ~data
->load_mask
);
811 static int bcm2835_pll_divider_debug_init(struct clk_hw
*hw
,
812 struct dentry
*dentry
)
814 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
815 struct bcm2835_cprman
*cprman
= divider
->cprman
;
816 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
817 struct debugfs_reg32
*regs
;
819 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
824 regs
[0].offset
= data
->cm_reg
;
825 regs
[1].name
= "a2w";
826 regs
[1].offset
= data
->a2w_reg
;
828 return bcm2835_debugfs_regset(cprman
, 0, regs
, 2, dentry
);
831 static const struct clk_ops bcm2835_pll_divider_clk_ops
= {
832 .is_prepared
= bcm2835_pll_divider_is_on
,
833 .prepare
= bcm2835_pll_divider_on
,
834 .unprepare
= bcm2835_pll_divider_off
,
835 .recalc_rate
= bcm2835_pll_divider_get_rate
,
836 .set_rate
= bcm2835_pll_divider_set_rate
,
837 .round_rate
= bcm2835_pll_divider_round_rate
,
838 .debug_init
= bcm2835_pll_divider_debug_init
,
842 * The CM dividers do fixed-point division, so we can't use the
843 * generic integer divider code like the PLL dividers do (and we can't
844 * fake it by having some fixed shifts preceding it in the clock tree,
845 * because we'd run out of bits in a 32-bit unsigned long).
847 struct bcm2835_clock
{
849 struct bcm2835_cprman
*cprman
;
850 const struct bcm2835_clock_data
*data
;
853 static struct bcm2835_clock
*bcm2835_clock_from_hw(struct clk_hw
*hw
)
855 return container_of(hw
, struct bcm2835_clock
, hw
);
858 static int bcm2835_clock_is_on(struct clk_hw
*hw
)
860 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
861 struct bcm2835_cprman
*cprman
= clock
->cprman
;
862 const struct bcm2835_clock_data
*data
= clock
->data
;
864 return (cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
) != 0;
867 static u32
bcm2835_clock_choose_div(struct clk_hw
*hw
,
869 unsigned long parent_rate
,
872 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
873 const struct bcm2835_clock_data
*data
= clock
->data
;
874 u32 unused_frac_mask
=
875 GENMASK(CM_DIV_FRAC_BITS
- data
->frac_bits
, 0) >> 1;
876 u64 temp
= (u64
)parent_rate
<< CM_DIV_FRAC_BITS
;
878 u32 div
, mindiv
, maxdiv
;
880 rem
= do_div(temp
, rate
);
883 /* Round up and mask off the unused bits */
884 if (round_up
&& ((div
& unused_frac_mask
) != 0 || rem
!= 0))
885 div
+= unused_frac_mask
+ 1;
886 div
&= ~unused_frac_mask
;
888 /* different clamping limits apply for a mash clock */
889 if (data
->is_mash_clock
) {
890 /* clamp to min divider of 2 */
891 mindiv
= 2 << CM_DIV_FRAC_BITS
;
892 /* clamp to the highest possible integer divider */
893 maxdiv
= (BIT(data
->int_bits
) - 1) << CM_DIV_FRAC_BITS
;
895 /* clamp to min divider of 1 */
896 mindiv
= 1 << CM_DIV_FRAC_BITS
;
897 /* clamp to the highest possible fractional divider */
898 maxdiv
= GENMASK(data
->int_bits
+ CM_DIV_FRAC_BITS
- 1,
899 CM_DIV_FRAC_BITS
- data
->frac_bits
);
902 /* apply the clamping limits */
903 div
= max_t(u32
, div
, mindiv
);
904 div
= min_t(u32
, div
, maxdiv
);
909 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock
*clock
,
910 unsigned long parent_rate
,
913 const struct bcm2835_clock_data
*data
= clock
->data
;
917 * The divisor is a 12.12 fixed point field, but only some of
918 * the bits are populated in any given clock.
920 div
>>= CM_DIV_FRAC_BITS
- data
->frac_bits
;
921 div
&= (1 << (data
->int_bits
+ data
->frac_bits
)) - 1;
926 temp
= (u64
)parent_rate
<< data
->frac_bits
;
933 static unsigned long bcm2835_clock_get_rate(struct clk_hw
*hw
,
934 unsigned long parent_rate
)
936 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
937 struct bcm2835_cprman
*cprman
= clock
->cprman
;
938 const struct bcm2835_clock_data
*data
= clock
->data
;
939 u32 div
= cprman_read(cprman
, data
->div_reg
);
941 return bcm2835_clock_rate_from_divisor(clock
, parent_rate
, div
);
944 static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw
*hw
,
945 unsigned long parent_rate
)
947 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
948 struct bcm2835_cprman
*cprman
= clock
->cprman
;
956 packet
.id
= VCMSG_ID_CORE_CLOCK
;
959 if (!rpi_firmware_property(cprman
->fw
,
960 RPI_FIRMWARE_GET_MAX_CLOCK_RATE
,
961 &packet
, sizeof(packet
)))
965 return bcm2835_clock_get_rate(hw
, parent_rate
);
968 static void bcm2835_clock_wait_busy(struct bcm2835_clock
*clock
)
970 struct bcm2835_cprman
*cprman
= clock
->cprman
;
971 const struct bcm2835_clock_data
*data
= clock
->data
;
972 ktime_t timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
974 while (cprman_read(cprman
, data
->ctl_reg
) & CM_BUSY
) {
975 if (ktime_after(ktime_get(), timeout
)) {
976 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
977 clk_hw_get_name(&clock
->hw
));
984 static void bcm2835_clock_off(struct clk_hw
*hw
)
986 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
987 struct bcm2835_cprman
*cprman
= clock
->cprman
;
988 const struct bcm2835_clock_data
*data
= clock
->data
;
990 spin_lock(&cprman
->regs_lock
);
991 cprman_write(cprman
, data
->ctl_reg
,
992 cprman_read(cprman
, data
->ctl_reg
) & ~CM_ENABLE
);
993 spin_unlock(&cprman
->regs_lock
);
995 /* BUSY will remain high until the divider completes its cycle. */
996 bcm2835_clock_wait_busy(clock
);
999 static int bcm2835_clock_on(struct clk_hw
*hw
)
1001 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1002 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1003 const struct bcm2835_clock_data
*data
= clock
->data
;
1005 spin_lock(&cprman
->regs_lock
);
1006 cprman_write(cprman
, data
->ctl_reg
,
1007 cprman_read(cprman
, data
->ctl_reg
) |
1010 spin_unlock(&cprman
->regs_lock
);
1015 static int bcm2835_clock_set_rate(struct clk_hw
*hw
,
1016 unsigned long rate
, unsigned long parent_rate
)
1018 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1019 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1020 const struct bcm2835_clock_data
*data
= clock
->data
;
1021 u32 div
= bcm2835_clock_choose_div(hw
, rate
, parent_rate
, false);
1024 spin_lock(&cprman
->regs_lock
);
1027 * Setting up frac support
1029 * In principle it is recommended to stop/start the clock first,
1030 * but as we set CLK_SET_RATE_GATE during registration of the
1031 * clock this requirement should be take care of by the
1034 ctl
= cprman_read(cprman
, data
->ctl_reg
) & ~CM_FRAC
;
1035 ctl
|= (div
& CM_DIV_FRAC_MASK
) ? CM_FRAC
: 0;
1036 cprman_write(cprman
, data
->ctl_reg
, ctl
);
1038 cprman_write(cprman
, data
->div_reg
, div
);
1040 spin_unlock(&cprman
->regs_lock
);
1046 bcm2835_clk_is_pllc(struct clk_hw
*hw
)
1051 return strncmp(clk_hw_get_name(hw
), "pllc", 4) == 0;
1054 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw
*hw
,
1058 unsigned long *prate
)
1060 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1061 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1062 const struct bcm2835_clock_data
*data
= clock
->data
;
1063 unsigned long best_rate
= 0;
1064 u32 curdiv
, mindiv
, maxdiv
;
1065 struct clk_hw
*parent
;
1067 parent
= clk_hw_get_parent_by_index(hw
, parent_idx
);
1069 if (!(BIT(parent_idx
) & data
->set_rate_parent
)) {
1070 *prate
= clk_hw_get_rate(parent
);
1071 *div
= bcm2835_clock_choose_div(hw
, rate
, *prate
, true);
1073 return bcm2835_clock_rate_from_divisor(clock
, *prate
,
1077 if (data
->frac_bits
)
1078 dev_warn(cprman
->dev
,
1079 "frac bits are not used when propagating rate change");
1081 /* clamp to min divider of 2 if we're dealing with a mash clock */
1082 mindiv
= data
->is_mash_clock
? 2 : 1;
1083 maxdiv
= BIT(data
->int_bits
) - 1;
1085 /* TODO: Be smart, and only test a subset of the available divisors. */
1086 for (curdiv
= mindiv
; curdiv
<= maxdiv
; curdiv
++) {
1087 unsigned long tmp_rate
;
1089 tmp_rate
= clk_hw_round_rate(parent
, rate
* curdiv
);
1091 if (curdiv
== mindiv
||
1092 (tmp_rate
> best_rate
&& tmp_rate
<= rate
))
1093 best_rate
= tmp_rate
;
1095 if (best_rate
== rate
)
1099 *div
= curdiv
<< CM_DIV_FRAC_BITS
;
1100 *prate
= curdiv
* best_rate
;
1105 static int bcm2835_clock_determine_rate(struct clk_hw
*hw
,
1106 struct clk_rate_request
*req
)
1108 struct clk_hw
*parent
, *best_parent
= NULL
;
1109 bool current_parent_is_pllc
;
1110 unsigned long rate
, best_rate
= 0;
1111 unsigned long prate
, best_prate
= 0;
1115 current_parent_is_pllc
= bcm2835_clk_is_pllc(clk_hw_get_parent(hw
));
1118 * Select parent clock that results in the closest but lower rate
1120 for (i
= 0; i
< clk_hw_get_num_parents(hw
); ++i
) {
1121 parent
= clk_hw_get_parent_by_index(hw
, i
);
1126 * Don't choose a PLLC-derived clock as our parent
1127 * unless it had been manually set that way. PLLC's
1128 * frequency gets adjusted by the firmware due to
1129 * over-temp or under-voltage conditions, without
1130 * prior notification to our clock consumer.
1132 if (bcm2835_clk_is_pllc(parent
) && !current_parent_is_pllc
)
1135 rate
= bcm2835_clock_choose_div_and_prate(hw
, i
, req
->rate
,
1137 if (rate
> best_rate
&& rate
<= req
->rate
) {
1138 best_parent
= parent
;
1147 req
->best_parent_hw
= best_parent
;
1148 req
->best_parent_rate
= best_prate
;
1150 req
->rate
= best_rate
;
1155 static int bcm2835_clock_set_parent(struct clk_hw
*hw
, u8 index
)
1157 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1158 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1159 const struct bcm2835_clock_data
*data
= clock
->data
;
1160 u8 src
= (index
<< CM_SRC_SHIFT
) & CM_SRC_MASK
;
1162 cprman_write(cprman
, data
->ctl_reg
, src
);
1166 static u8
bcm2835_clock_get_parent(struct clk_hw
*hw
)
1168 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1169 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1170 const struct bcm2835_clock_data
*data
= clock
->data
;
1171 u32 src
= cprman_read(cprman
, data
->ctl_reg
);
1173 return (src
& CM_SRC_MASK
) >> CM_SRC_SHIFT
;
1176 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32
[] = {
1187 static int bcm2835_clock_debug_init(struct clk_hw
*hw
,
1188 struct dentry
*dentry
)
1190 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1191 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1192 const struct bcm2835_clock_data
*data
= clock
->data
;
1194 return bcm2835_debugfs_regset(
1195 cprman
, data
->ctl_reg
,
1196 bcm2835_debugfs_clock_reg32
,
1197 ARRAY_SIZE(bcm2835_debugfs_clock_reg32
),
1201 static const struct clk_ops bcm2835_clock_clk_ops
= {
1202 .is_prepared
= bcm2835_clock_is_on
,
1203 .prepare
= bcm2835_clock_on
,
1204 .unprepare
= bcm2835_clock_off
,
1205 .recalc_rate
= bcm2835_clock_get_rate
,
1206 .set_rate
= bcm2835_clock_set_rate
,
1207 .determine_rate
= bcm2835_clock_determine_rate
,
1208 .set_parent
= bcm2835_clock_set_parent
,
1209 .get_parent
= bcm2835_clock_get_parent
,
1210 .debug_init
= bcm2835_clock_debug_init
,
1213 static int bcm2835_vpu_clock_is_on(struct clk_hw
*hw
)
1219 * The VPU clock can never be disabled (it doesn't have an ENABLE
1220 * bit), so it gets its own set of clock ops.
1222 static const struct clk_ops bcm2835_vpu_clock_clk_ops
= {
1223 .is_prepared
= bcm2835_vpu_clock_is_on
,
1224 .recalc_rate
= bcm2835_clock_get_rate_vpu
,
1225 .set_rate
= bcm2835_clock_set_rate
,
1226 .determine_rate
= bcm2835_clock_determine_rate
,
1227 .set_parent
= bcm2835_clock_set_parent
,
1228 .get_parent
= bcm2835_clock_get_parent
,
1229 .debug_init
= bcm2835_clock_debug_init
,
1232 static bool bcm2835_clk_is_claimed(const char *name
);
1234 static struct clk_hw
*bcm2835_register_pll(struct bcm2835_cprman
*cprman
,
1235 const struct bcm2835_pll_data
*data
)
1237 struct bcm2835_pll
*pll
;
1238 struct clk_init_data init
;
1241 memset(&init
, 0, sizeof(init
));
1243 /* All of the PLLs derive from the external oscillator. */
1244 init
.parent_names
= &cprman
->osc_name
;
1245 init
.num_parents
= 1;
1246 init
.name
= data
->name
;
1247 init
.ops
= &bcm2835_pll_clk_ops
;
1248 init
.flags
= CLK_IGNORE_UNUSED
;
1250 if (!bcm2835_clk_is_claimed(data
->name
))
1251 init
.flags
|= CLK_IS_CRITICAL
;
1253 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
1257 pll
->cprman
= cprman
;
1259 pll
->hw
.init
= &init
;
1261 ret
= devm_clk_hw_register(cprman
->dev
, &pll
->hw
);
1267 static struct clk_hw
*
1268 bcm2835_register_pll_divider(struct bcm2835_cprman
*cprman
,
1269 const struct bcm2835_pll_divider_data
*data
)
1271 struct bcm2835_pll_divider
*divider
;
1272 struct clk_init_data init
;
1273 const char *divider_name
;
1276 if (data
->fixed_divider
!= 1) {
1277 divider_name
= devm_kasprintf(cprman
->dev
, GFP_KERNEL
,
1278 "%s_prediv", data
->name
);
1282 divider_name
= data
->name
;
1285 memset(&init
, 0, sizeof(init
));
1287 init
.parent_names
= &data
->source_pll
;
1288 init
.num_parents
= 1;
1289 init
.name
= divider_name
;
1290 init
.ops
= &bcm2835_pll_divider_clk_ops
;
1291 init
.flags
= data
->flags
| CLK_IGNORE_UNUSED
;
1293 divider
= devm_kzalloc(cprman
->dev
, sizeof(*divider
), GFP_KERNEL
);
1297 divider
->div
.reg
= cprman
->regs
+ data
->a2w_reg
;
1298 divider
->div
.shift
= A2W_PLL_DIV_SHIFT
;
1299 divider
->div
.width
= A2W_PLL_DIV_BITS
;
1300 divider
->div
.flags
= CLK_DIVIDER_MAX_AT_ZERO
;
1301 divider
->div
.lock
= &cprman
->regs_lock
;
1302 divider
->div
.hw
.init
= &init
;
1303 divider
->div
.table
= NULL
;
1305 if (!(cprman_read(cprman
, data
->cm_reg
) & data
->hold_mask
)) {
1306 if (!bcm2835_clk_is_claimed(data
->source_pll
))
1307 init
.flags
|= CLK_IS_CRITICAL
;
1308 if (!bcm2835_clk_is_claimed(data
->name
))
1309 divider
->div
.flags
|= CLK_IS_CRITICAL
;
1312 divider
->cprman
= cprman
;
1313 divider
->data
= data
;
1315 ret
= devm_clk_hw_register(cprman
->dev
, ÷r
->div
.hw
);
1317 return ERR_PTR(ret
);
1320 * PLLH's channels have a fixed divide by 10 afterwards, which
1321 * is what our consumers are actually using.
1323 if (data
->fixed_divider
!= 1) {
1324 return clk_hw_register_fixed_factor(cprman
->dev
, data
->name
,
1326 CLK_SET_RATE_PARENT
,
1328 data
->fixed_divider
);
1331 return ÷r
->div
.hw
;
1334 static struct clk_hw
*bcm2835_register_clock(struct bcm2835_cprman
*cprman
,
1335 const struct bcm2835_clock_data
*data
)
1337 struct bcm2835_clock
*clock
;
1338 struct clk_init_data init
;
1339 const char *parents
[1 << CM_SRC_BITS
];
1344 * Replace our "xosc" references with the oscillator's
1347 for (i
= 0; i
< data
->num_mux_parents
; i
++) {
1348 if (strcmp(data
->parents
[i
], "xosc") == 0)
1349 parents
[i
] = cprman
->osc_name
;
1351 parents
[i
] = data
->parents
[i
];
1354 memset(&init
, 0, sizeof(init
));
1355 init
.parent_names
= parents
;
1356 init
.num_parents
= data
->num_mux_parents
;
1357 init
.name
= data
->name
;
1358 init
.flags
= data
->flags
| CLK_IGNORE_UNUSED
;
1361 * Some GPIO clocks for ethernet/wifi PLLs are marked as
1362 * critical (since some platforms use them), but if the
1363 * firmware didn't have them turned on then they clearly
1364 * aren't actually critical.
1366 if ((cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
) == 0)
1367 init
.flags
&= ~CLK_IS_CRITICAL
;
1370 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1371 * rate changes on at least of the parents.
1373 if (data
->set_rate_parent
)
1374 init
.flags
|= CLK_SET_RATE_PARENT
;
1376 if (data
->is_vpu_clock
) {
1377 init
.ops
= &bcm2835_vpu_clock_clk_ops
;
1379 init
.ops
= &bcm2835_clock_clk_ops
;
1380 init
.flags
|= CLK_SET_RATE_GATE
| CLK_SET_PARENT_GATE
;
1382 /* If the clock wasn't actually enabled at boot, it's not
1385 if (!(cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
))
1386 init
.flags
&= ~CLK_IS_CRITICAL
;
1389 clock
= devm_kzalloc(cprman
->dev
, sizeof(*clock
), GFP_KERNEL
);
1393 clock
->cprman
= cprman
;
1395 clock
->hw
.init
= &init
;
1397 ret
= devm_clk_hw_register(cprman
->dev
, &clock
->hw
);
1399 return ERR_PTR(ret
);
1403 static struct clk
*bcm2835_register_gate(struct bcm2835_cprman
*cprman
,
1404 const struct bcm2835_gate_data
*data
)
1406 return clk_register_gate(cprman
->dev
, data
->name
, data
->parent
,
1407 CLK_IGNORE_UNUSED
| CLK_SET_RATE_GATE
,
1408 cprman
->regs
+ data
->ctl_reg
,
1409 CM_GATE_BIT
, 0, &cprman
->regs_lock
);
1412 typedef struct clk_hw
*(*bcm2835_clk_register
)(struct bcm2835_cprman
*cprman
,
1414 struct bcm2835_clk_desc
{
1415 bcm2835_clk_register clk_register
;
1419 /* assignment helper macros for different clock types */
1420 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1421 .data = __VA_ARGS__ }
1422 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1423 &(struct bcm2835_pll_data) \
1425 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1426 &(struct bcm2835_pll_divider_data) \
1428 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1429 &(struct bcm2835_clock_data) \
1431 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1432 &(struct bcm2835_gate_data) \
1435 /* parent mux arrays plus helper macros */
1437 /* main oscillator parent mux */
1438 static const char *const bcm2835_clock_osc_parents
[] = {
1445 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1446 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1447 .parents = bcm2835_clock_osc_parents, \
1450 /* main peripherial parent mux */
1451 static const char *const bcm2835_clock_per_parents
[] = {
1462 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1463 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1464 .parents = bcm2835_clock_per_parents, \
1467 /* main vpu parent mux */
1468 static const char *const bcm2835_clock_vpu_parents
[] = {
1481 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1482 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1483 .parents = bcm2835_clock_vpu_parents, \
1487 * the real definition of all the pll, pll_dividers and clocks
1488 * these make use of the above REGISTER_* macros
1490 static const struct bcm2835_clk_desc clk_desc_array
[] = {
1491 /* the PLL + PLL dividers */
1494 * PLLA is the auxiliary PLL, used to drive the CCP2
1495 * (Compact Camera Port 2) transmitter clock.
1497 * It is in the PX LDO power domain, which is on when the
1498 * AUDIO domain is on.
1500 [BCM2835_PLLA
] = REGISTER_PLL(
1502 .cm_ctrl_reg
= CM_PLLA
,
1503 .a2w_ctrl_reg
= A2W_PLLA_CTRL
,
1504 .frac_reg
= A2W_PLLA_FRAC
,
1505 .ana_reg_base
= A2W_PLLA_ANA0
,
1506 .reference_enable_mask
= A2W_XOSC_CTRL_PLLA_ENABLE
,
1507 .lock_mask
= CM_LOCK_FLOCKA
,
1509 .ana
= &bcm2835_ana_default
,
1511 .min_rate
= 600000000u,
1512 .max_rate
= 2400000000u,
1513 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1514 [BCM2835_PLLA_CORE
] = REGISTER_PLL_DIV(
1515 .name
= "plla_core",
1516 .source_pll
= "plla",
1518 .a2w_reg
= A2W_PLLA_CORE
,
1519 .load_mask
= CM_PLLA_LOADCORE
,
1520 .hold_mask
= CM_PLLA_HOLDCORE
,
1522 .flags
= CLK_SET_RATE_PARENT
),
1523 [BCM2835_PLLA_PER
] = REGISTER_PLL_DIV(
1525 .source_pll
= "plla",
1527 .a2w_reg
= A2W_PLLA_PER
,
1528 .load_mask
= CM_PLLA_LOADPER
,
1529 .hold_mask
= CM_PLLA_HOLDPER
,
1531 .flags
= CLK_SET_RATE_PARENT
),
1532 [BCM2835_PLLA_DSI0
] = REGISTER_PLL_DIV(
1533 .name
= "plla_dsi0",
1534 .source_pll
= "plla",
1536 .a2w_reg
= A2W_PLLA_DSI0
,
1537 .load_mask
= CM_PLLA_LOADDSI0
,
1538 .hold_mask
= CM_PLLA_HOLDDSI0
,
1539 .fixed_divider
= 1),
1540 [BCM2835_PLLA_CCP2
] = REGISTER_PLL_DIV(
1541 .name
= "plla_ccp2",
1542 .source_pll
= "plla",
1544 .a2w_reg
= A2W_PLLA_CCP2
,
1545 .load_mask
= CM_PLLA_LOADCCP2
,
1546 .hold_mask
= CM_PLLA_HOLDCCP2
,
1548 .flags
= CLK_SET_RATE_PARENT
),
1550 /* PLLB is used for the ARM's clock. */
1551 [BCM2835_PLLB
] = REGISTER_PLL(
1553 .cm_ctrl_reg
= CM_PLLB
,
1554 .a2w_ctrl_reg
= A2W_PLLB_CTRL
,
1555 .frac_reg
= A2W_PLLB_FRAC
,
1556 .ana_reg_base
= A2W_PLLB_ANA0
,
1557 .reference_enable_mask
= A2W_XOSC_CTRL_PLLB_ENABLE
,
1558 .lock_mask
= CM_LOCK_FLOCKB
,
1560 .ana
= &bcm2835_ana_default
,
1562 .min_rate
= 600000000u,
1563 .max_rate
= 3000000000u,
1564 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1565 [BCM2835_PLLB_ARM
] = REGISTER_PLL_DIV(
1567 .source_pll
= "pllb",
1569 .a2w_reg
= A2W_PLLB_ARM
,
1570 .load_mask
= CM_PLLB_LOADARM
,
1571 .hold_mask
= CM_PLLB_HOLDARM
,
1573 .flags
= CLK_SET_RATE_PARENT
),
1576 * PLLC is the core PLL, used to drive the core VPU clock.
1578 * It is in the PX LDO power domain, which is on when the
1579 * AUDIO domain is on.
1581 [BCM2835_PLLC
] = REGISTER_PLL(
1583 .cm_ctrl_reg
= CM_PLLC
,
1584 .a2w_ctrl_reg
= A2W_PLLC_CTRL
,
1585 .frac_reg
= A2W_PLLC_FRAC
,
1586 .ana_reg_base
= A2W_PLLC_ANA0
,
1587 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1588 .lock_mask
= CM_LOCK_FLOCKC
,
1590 .ana
= &bcm2835_ana_default
,
1592 .min_rate
= 600000000u,
1593 .max_rate
= 3000000000u,
1594 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1595 [BCM2835_PLLC_CORE0
] = REGISTER_PLL_DIV(
1596 .name
= "pllc_core0",
1597 .source_pll
= "pllc",
1599 .a2w_reg
= A2W_PLLC_CORE0
,
1600 .load_mask
= CM_PLLC_LOADCORE0
,
1601 .hold_mask
= CM_PLLC_HOLDCORE0
,
1603 .flags
= CLK_SET_RATE_PARENT
),
1604 [BCM2835_PLLC_CORE1
] = REGISTER_PLL_DIV(
1605 .name
= "pllc_core1",
1606 .source_pll
= "pllc",
1608 .a2w_reg
= A2W_PLLC_CORE1
,
1609 .load_mask
= CM_PLLC_LOADCORE1
,
1610 .hold_mask
= CM_PLLC_HOLDCORE1
,
1612 .flags
= CLK_SET_RATE_PARENT
),
1613 [BCM2835_PLLC_CORE2
] = REGISTER_PLL_DIV(
1614 .name
= "pllc_core2",
1615 .source_pll
= "pllc",
1617 .a2w_reg
= A2W_PLLC_CORE2
,
1618 .load_mask
= CM_PLLC_LOADCORE2
,
1619 .hold_mask
= CM_PLLC_HOLDCORE2
,
1621 .flags
= CLK_SET_RATE_PARENT
),
1622 [BCM2835_PLLC_PER
] = REGISTER_PLL_DIV(
1624 .source_pll
= "pllc",
1626 .a2w_reg
= A2W_PLLC_PER
,
1627 .load_mask
= CM_PLLC_LOADPER
,
1628 .hold_mask
= CM_PLLC_HOLDPER
,
1630 .flags
= CLK_SET_RATE_PARENT
),
1633 * PLLD is the display PLL, used to drive DSI display panels.
1635 * It is in the PX LDO power domain, which is on when the
1636 * AUDIO domain is on.
1638 [BCM2835_PLLD
] = REGISTER_PLL(
1640 .cm_ctrl_reg
= CM_PLLD
,
1641 .a2w_ctrl_reg
= A2W_PLLD_CTRL
,
1642 .frac_reg
= A2W_PLLD_FRAC
,
1643 .ana_reg_base
= A2W_PLLD_ANA0
,
1644 .reference_enable_mask
= A2W_XOSC_CTRL_DDR_ENABLE
,
1645 .lock_mask
= CM_LOCK_FLOCKD
,
1647 .ana
= &bcm2835_ana_default
,
1649 .min_rate
= 600000000u,
1650 .max_rate
= 2400000000u,
1651 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1652 [BCM2835_PLLD_CORE
] = REGISTER_PLL_DIV(
1653 .name
= "plld_core",
1654 .source_pll
= "plld",
1656 .a2w_reg
= A2W_PLLD_CORE
,
1657 .load_mask
= CM_PLLD_LOADCORE
,
1658 .hold_mask
= CM_PLLD_HOLDCORE
,
1660 .flags
= CLK_SET_RATE_PARENT
),
1661 [BCM2835_PLLD_PER
] = REGISTER_PLL_DIV(
1663 .source_pll
= "plld",
1665 .a2w_reg
= A2W_PLLD_PER
,
1666 .load_mask
= CM_PLLD_LOADPER
,
1667 .hold_mask
= CM_PLLD_HOLDPER
,
1669 .flags
= CLK_SET_RATE_PARENT
),
1670 [BCM2835_PLLD_DSI0
] = REGISTER_PLL_DIV(
1671 .name
= "plld_dsi0",
1672 .source_pll
= "plld",
1674 .a2w_reg
= A2W_PLLD_DSI0
,
1675 .load_mask
= CM_PLLD_LOADDSI0
,
1676 .hold_mask
= CM_PLLD_HOLDDSI0
,
1677 .fixed_divider
= 1),
1678 [BCM2835_PLLD_DSI1
] = REGISTER_PLL_DIV(
1679 .name
= "plld_dsi1",
1680 .source_pll
= "plld",
1682 .a2w_reg
= A2W_PLLD_DSI1
,
1683 .load_mask
= CM_PLLD_LOADDSI1
,
1684 .hold_mask
= CM_PLLD_HOLDDSI1
,
1685 .fixed_divider
= 1),
1688 * PLLH is used to supply the pixel clock or the AUX clock for the
1691 * It is in the HDMI power domain.
1693 [BCM2835_PLLH
] = REGISTER_PLL(
1695 .cm_ctrl_reg
= CM_PLLH
,
1696 .a2w_ctrl_reg
= A2W_PLLH_CTRL
,
1697 .frac_reg
= A2W_PLLH_FRAC
,
1698 .ana_reg_base
= A2W_PLLH_ANA0
,
1699 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1700 .lock_mask
= CM_LOCK_FLOCKH
,
1702 .ana
= &bcm2835_ana_pllh
,
1704 .min_rate
= 600000000u,
1705 .max_rate
= 3000000000u,
1706 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1707 [BCM2835_PLLH_RCAL
] = REGISTER_PLL_DIV(
1708 .name
= "pllh_rcal",
1709 .source_pll
= "pllh",
1711 .a2w_reg
= A2W_PLLH_RCAL
,
1712 .load_mask
= CM_PLLH_LOADRCAL
,
1714 .fixed_divider
= 10,
1715 .flags
= CLK_SET_RATE_PARENT
),
1716 [BCM2835_PLLH_AUX
] = REGISTER_PLL_DIV(
1718 .source_pll
= "pllh",
1720 .a2w_reg
= A2W_PLLH_AUX
,
1721 .load_mask
= CM_PLLH_LOADAUX
,
1724 .flags
= CLK_SET_RATE_PARENT
),
1725 [BCM2835_PLLH_PIX
] = REGISTER_PLL_DIV(
1727 .source_pll
= "pllh",
1729 .a2w_reg
= A2W_PLLH_PIX
,
1730 .load_mask
= CM_PLLH_LOADPIX
,
1732 .fixed_divider
= 10,
1733 .flags
= CLK_SET_RATE_PARENT
),
1737 /* clocks with oscillator parent mux */
1739 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1740 [BCM2835_CLOCK_OTP
] = REGISTER_OSC_CLK(
1742 .ctl_reg
= CM_OTPCTL
,
1743 .div_reg
= CM_OTPDIV
,
1747 * Used for a 1Mhz clock for the system clocksource, and also used
1748 * bythe watchdog timer and the camera pulse generator.
1750 [BCM2835_CLOCK_TIMER
] = REGISTER_OSC_CLK(
1752 .ctl_reg
= CM_TIMERCTL
,
1753 .div_reg
= CM_TIMERDIV
,
1757 * Clock for the temperature sensor.
1758 * Generally run at 2Mhz, max 5Mhz.
1760 [BCM2835_CLOCK_TSENS
] = REGISTER_OSC_CLK(
1762 .ctl_reg
= CM_TSENSCTL
,
1763 .div_reg
= CM_TSENSDIV
,
1766 [BCM2835_CLOCK_TEC
] = REGISTER_OSC_CLK(
1768 .ctl_reg
= CM_TECCTL
,
1769 .div_reg
= CM_TECDIV
,
1773 /* clocks with vpu parent mux */
1774 [BCM2835_CLOCK_H264
] = REGISTER_VPU_CLK(
1776 .ctl_reg
= CM_H264CTL
,
1777 .div_reg
= CM_H264DIV
,
1780 [BCM2835_CLOCK_ISP
] = REGISTER_VPU_CLK(
1782 .ctl_reg
= CM_ISPCTL
,
1783 .div_reg
= CM_ISPDIV
,
1788 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1789 * in the SDRAM controller can't be used.
1791 [BCM2835_CLOCK_SDRAM
] = REGISTER_VPU_CLK(
1793 .ctl_reg
= CM_SDCCTL
,
1794 .div_reg
= CM_SDCDIV
,
1797 [BCM2835_CLOCK_V3D
] = REGISTER_VPU_CLK(
1799 .ctl_reg
= CM_V3DCTL
,
1800 .div_reg
= CM_V3DDIV
,
1804 * VPU clock. This doesn't have an enable bit, since it drives
1805 * the bus for everything else, and is special so it doesn't need
1806 * to be gated for rate changes. It is also known as "clk_audio"
1807 * in various hardware documentation.
1809 [BCM2835_CLOCK_VPU
] = REGISTER_VPU_CLK(
1811 .ctl_reg
= CM_VPUCTL
,
1812 .div_reg
= CM_VPUDIV
,
1815 .flags
= CLK_IS_CRITICAL
,
1816 .is_vpu_clock
= true),
1818 /* clocks with per parent mux */
1819 [BCM2835_CLOCK_AVEO
] = REGISTER_PER_CLK(
1821 .ctl_reg
= CM_AVEOCTL
,
1822 .div_reg
= CM_AVEODIV
,
1825 [BCM2835_CLOCK_CAM0
] = REGISTER_PER_CLK(
1827 .ctl_reg
= CM_CAM0CTL
,
1828 .div_reg
= CM_CAM0DIV
,
1831 [BCM2835_CLOCK_CAM1
] = REGISTER_PER_CLK(
1833 .ctl_reg
= CM_CAM1CTL
,
1834 .div_reg
= CM_CAM1DIV
,
1837 [BCM2835_CLOCK_DFT
] = REGISTER_PER_CLK(
1839 .ctl_reg
= CM_DFTCTL
,
1840 .div_reg
= CM_DFTDIV
,
1843 [BCM2835_CLOCK_DPI
] = REGISTER_PER_CLK(
1845 .ctl_reg
= CM_DPICTL
,
1846 .div_reg
= CM_DPIDIV
,
1850 /* Arasan EMMC clock */
1851 [BCM2835_CLOCK_EMMC
] = REGISTER_PER_CLK(
1853 .ctl_reg
= CM_EMMCCTL
,
1854 .div_reg
= CM_EMMCDIV
,
1858 /* General purpose (GPIO) clocks */
1859 [BCM2835_CLOCK_GP0
] = REGISTER_PER_CLK(
1861 .ctl_reg
= CM_GP0CTL
,
1862 .div_reg
= CM_GP0DIV
,
1865 .is_mash_clock
= true),
1866 [BCM2835_CLOCK_GP1
] = REGISTER_PER_CLK(
1868 .ctl_reg
= CM_GP1CTL
,
1869 .div_reg
= CM_GP1DIV
,
1872 .flags
= CLK_IS_CRITICAL
,
1873 .is_mash_clock
= true),
1874 [BCM2835_CLOCK_GP2
] = REGISTER_PER_CLK(
1876 .ctl_reg
= CM_GP2CTL
,
1877 .div_reg
= CM_GP2DIV
,
1880 .flags
= CLK_IS_CRITICAL
),
1882 /* HDMI state machine */
1883 [BCM2835_CLOCK_HSM
] = REGISTER_PER_CLK(
1885 .ctl_reg
= CM_HSMCTL
,
1886 .div_reg
= CM_HSMDIV
,
1889 [BCM2835_CLOCK_PCM
] = REGISTER_PER_CLK(
1891 .ctl_reg
= CM_PCMCTL
,
1892 .div_reg
= CM_PCMDIV
,
1895 .is_mash_clock
= true),
1896 [BCM2835_CLOCK_PWM
] = REGISTER_PER_CLK(
1898 .ctl_reg
= CM_PWMCTL
,
1899 .div_reg
= CM_PWMDIV
,
1902 .is_mash_clock
= true),
1903 [BCM2835_CLOCK_SLIM
] = REGISTER_PER_CLK(
1905 .ctl_reg
= CM_SLIMCTL
,
1906 .div_reg
= CM_SLIMDIV
,
1909 .is_mash_clock
= true),
1910 [BCM2835_CLOCK_SMI
] = REGISTER_PER_CLK(
1912 .ctl_reg
= CM_SMICTL
,
1913 .div_reg
= CM_SMIDIV
,
1916 [BCM2835_CLOCK_UART
] = REGISTER_PER_CLK(
1918 .ctl_reg
= CM_UARTCTL
,
1919 .div_reg
= CM_UARTDIV
,
1923 /* TV encoder clock. Only operating frequency is 108Mhz. */
1924 [BCM2835_CLOCK_VEC
] = REGISTER_PER_CLK(
1926 .ctl_reg
= CM_VECCTL
,
1927 .div_reg
= CM_VECDIV
,
1931 * Allow rate change propagation only on PLLH_AUX which is
1932 * assigned index 7 in the parent array.
1934 .set_rate_parent
= BIT(7)),
1937 [BCM2835_CLOCK_DSI0E
] = REGISTER_PER_CLK(
1939 .ctl_reg
= CM_DSI0ECTL
,
1940 .div_reg
= CM_DSI0EDIV
,
1943 [BCM2835_CLOCK_DSI1E
] = REGISTER_PER_CLK(
1945 .ctl_reg
= CM_DSI1ECTL
,
1946 .div_reg
= CM_DSI1EDIV
,
1953 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1954 * you have the debug bit set in the power manager, which we
1955 * don't bother exposing) are individual gates off of the
1956 * non-stop vpu clock.
1958 [BCM2835_CLOCK_PERI_IMAGE
] = REGISTER_GATE(
1959 .name
= "peri_image",
1961 .ctl_reg
= CM_PERIICTL
),
1964 static bool bcm2835_clk_claimed
[ARRAY_SIZE(clk_desc_array
)];
1967 * Permanently take a reference on the parent of the SDRAM clock.
1969 * While the SDRAM is being driven by its dedicated PLL most of the
1970 * time, there is a little loop running in the firmware that
1971 * periodically switches the SDRAM to using our CM clock to do PVT
1972 * recalibration, with the assumption that the previously configured
1973 * SDRAM parent is still enabled and running.
1975 static int bcm2835_mark_sdc_parent_critical(struct clk
*sdc
)
1977 struct clk
*parent
= clk_get_parent(sdc
);
1980 return PTR_ERR(parent
);
1982 return clk_prepare_enable(parent
);
1985 static bool bcm2835_clk_is_claimed(const char *name
)
1989 for (i
= 0; i
< ARRAY_SIZE(clk_desc_array
); i
++) {
1990 const char *clk_name
= *(const char **)(clk_desc_array
[i
].data
);
1991 if (!strcmp(name
, clk_name
))
1992 return bcm2835_clk_claimed
[i
];
1998 static int bcm2835_clk_probe(struct platform_device
*pdev
)
2000 struct device
*dev
= &pdev
->dev
;
2001 struct clk_hw
**hws
;
2002 struct bcm2835_cprman
*cprman
;
2003 struct resource
*res
;
2004 const struct bcm2835_clk_desc
*desc
;
2005 const size_t asize
= ARRAY_SIZE(clk_desc_array
);
2006 struct device_node
*fw_node
;
2011 cprman
= devm_kzalloc(dev
, sizeof(*cprman
) +
2012 sizeof(*cprman
->onecell
.hws
) * asize
,
2017 spin_lock_init(&cprman
->regs_lock
);
2019 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2020 cprman
->regs
= devm_ioremap_resource(dev
, res
);
2021 if (IS_ERR(cprman
->regs
))
2022 return PTR_ERR(cprman
->regs
);
2024 fw_node
= of_parse_phandle(dev
->of_node
, "firmware", 0);
2026 struct rpi_firmware
*fw
= rpi_firmware_get(NULL
);
2028 return -EPROBE_DEFER
;
2032 memset(bcm2835_clk_claimed
, 0, sizeof(bcm2835_clk_claimed
));
2034 !of_property_read_u32_index(pdev
->dev
.of_node
, "claim-clocks",
2037 bcm2835_clk_claimed
[clk_id
]= true;
2039 cprman
->osc_name
= of_clk_get_parent_name(dev
->of_node
, 0);
2040 if (!cprman
->osc_name
)
2043 platform_set_drvdata(pdev
, cprman
);
2045 cprman
->onecell
.num
= asize
;
2046 hws
= cprman
->onecell
.hws
;
2048 for (i
= 0; i
< asize
; i
++) {
2049 desc
= &clk_desc_array
[i
];
2050 if (desc
->clk_register
&& desc
->data
)
2051 hws
[i
] = desc
->clk_register(cprman
, desc
->data
);
2054 ret
= bcm2835_mark_sdc_parent_critical(hws
[BCM2835_CLOCK_SDRAM
]->clk
);
2058 ret
= of_clk_add_hw_provider(dev
->of_node
, of_clk_hw_onecell_get
,
2063 /* note that we have registered all the clocks */
2064 dev_dbg(dev
, "registered %d clocks\n", asize
);
2069 static const struct of_device_id bcm2835_clk_of_match
[] = {
2070 { .compatible
= "brcm,bcm2835-cprman", },
2073 MODULE_DEVICE_TABLE(of
, bcm2835_clk_of_match
);
2075 static struct platform_driver bcm2835_clk_driver
= {
2077 .name
= "bcm2835-clk",
2078 .of_match_table
= bcm2835_clk_of_match
,
2080 .probe
= bcm2835_clk_probe
,
2083 static int __init
__bcm2835_clk_driver_init(void)
2085 return platform_driver_register(&bcm2835_clk_driver
);
2087 core_initcall(__bcm2835_clk_driver_init
);
2089 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2090 MODULE_DESCRIPTION("BCM2835 clock driver");
2091 MODULE_LICENSE("GPL v2");